2 * Marvell 88e6xxx Ethernet switch single-chip support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #include <linux/delay.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_bridge.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/irqdomain.h>
24 #include <linux/jiffies.h>
25 #include <linux/list.h>
26 #include <linux/mdio.h>
27 #include <linux/module.h>
28 #include <linux/of_device.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_mdio.h>
31 #include <linux/netdevice.h>
32 #include <linux/gpio/consumer.h>
33 #include <linux/phy.h>
45 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
47 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
48 dev_err(chip->dev, "Switch registers lock not held!\n");
53 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
54 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
56 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
57 * is the only device connected to the SMI master. In this mode it responds to
58 * all 32 possible SMI addresses, and thus maps directly the internal devices.
60 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
61 * multiple devices to share the SMI interface. In this mode it responds to only
62 * 2 registers, used to indirectly access the internal SMI devices.
65 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
66 int addr, int reg, u16 *val)
71 return chip->smi_ops->read(chip, addr, reg, val);
74 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
75 int addr, int reg, u16 val)
80 return chip->smi_ops->write(chip, addr, reg, val);
83 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
84 int addr, int reg, u16 *val)
88 ret = mdiobus_read_nested(chip->bus, addr, reg);
97 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
98 int addr, int reg, u16 val)
102 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
109 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
110 .read = mv88e6xxx_smi_single_chip_read,
111 .write = mv88e6xxx_smi_single_chip_write,
114 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
119 for (i = 0; i < 16; i++) {
120 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
124 if ((ret & SMI_CMD_BUSY) == 0)
131 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
132 int addr, int reg, u16 *val)
136 /* Wait for the bus to become free. */
137 ret = mv88e6xxx_smi_multi_chip_wait(chip);
141 /* Transmit the read command. */
142 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
143 SMI_CMD_OP_22_READ | (addr << 5) | reg);
147 /* Wait for the read command to complete. */
148 ret = mv88e6xxx_smi_multi_chip_wait(chip);
153 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
162 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
163 int addr, int reg, u16 val)
167 /* Wait for the bus to become free. */
168 ret = mv88e6xxx_smi_multi_chip_wait(chip);
172 /* Transmit the data to write. */
173 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
177 /* Transmit the write command. */
178 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
179 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
183 /* Wait for the write command to complete. */
184 ret = mv88e6xxx_smi_multi_chip_wait(chip);
191 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
192 .read = mv88e6xxx_smi_multi_chip_read,
193 .write = mv88e6xxx_smi_multi_chip_write,
196 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
200 assert_reg_lock(chip);
202 err = mv88e6xxx_smi_read(chip, addr, reg, val);
206 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
212 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
216 assert_reg_lock(chip);
218 err = mv88e6xxx_smi_write(chip, addr, reg, val);
222 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
228 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
230 struct mv88e6xxx_mdio_bus *mdio_bus;
232 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
237 return mdio_bus->bus;
240 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
242 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
243 unsigned int n = d->hwirq;
245 chip->g1_irq.masked |= (1 << n);
248 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
250 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
251 unsigned int n = d->hwirq;
253 chip->g1_irq.masked &= ~(1 << n);
256 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
258 unsigned int nhandled = 0;
259 unsigned int sub_irq;
264 mutex_lock(&chip->reg_lock);
265 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
266 mutex_unlock(&chip->reg_lock);
271 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
272 if (reg & (1 << n)) {
273 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
274 handle_nested_irq(sub_irq);
279 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
282 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
284 struct mv88e6xxx_chip *chip = dev_id;
286 return mv88e6xxx_g1_irq_thread_work(chip);
289 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
291 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
293 mutex_lock(&chip->reg_lock);
296 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
298 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
299 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
303 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
308 reg |= (~chip->g1_irq.masked & mask);
310 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
315 mutex_unlock(&chip->reg_lock);
318 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
319 .name = "mv88e6xxx-g1",
320 .irq_mask = mv88e6xxx_g1_irq_mask,
321 .irq_unmask = mv88e6xxx_g1_irq_unmask,
322 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
323 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
326 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
328 irq_hw_number_t hwirq)
330 struct mv88e6xxx_chip *chip = d->host_data;
332 irq_set_chip_data(irq, d->host_data);
333 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
334 irq_set_noprobe(irq);
339 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
340 .map = mv88e6xxx_g1_irq_domain_map,
341 .xlate = irq_domain_xlate_twocell,
344 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
349 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
350 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
351 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
353 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
354 virq = irq_find_mapping(chip->g1_irq.domain, irq);
355 irq_dispose_mapping(virq);
358 irq_domain_remove(chip->g1_irq.domain);
361 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
363 mv88e6xxx_g1_irq_free_common(chip);
365 free_irq(chip->irq, chip);
368 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
373 chip->g1_irq.nirqs = chip->info->g1_irqs;
374 chip->g1_irq.domain = irq_domain_add_simple(
375 NULL, chip->g1_irq.nirqs, 0,
376 &mv88e6xxx_g1_irq_domain_ops, chip);
377 if (!chip->g1_irq.domain)
380 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
381 irq_create_mapping(chip->g1_irq.domain, irq);
383 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
384 chip->g1_irq.masked = ~0;
386 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
390 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
392 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
396 /* Reading the interrupt status clears (most of) them */
397 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
404 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
405 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
408 for (irq = 0; irq < 16; irq++) {
409 virq = irq_find_mapping(chip->g1_irq.domain, irq);
410 irq_dispose_mapping(virq);
413 irq_domain_remove(chip->g1_irq.domain);
418 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
422 err = mv88e6xxx_g1_irq_setup_common(chip);
426 err = request_threaded_irq(chip->irq, NULL,
427 mv88e6xxx_g1_irq_thread_fn,
429 dev_name(chip->dev), chip);
431 mv88e6xxx_g1_irq_free_common(chip);
436 static void mv88e6xxx_irq_poll(struct kthread_work *work)
438 struct mv88e6xxx_chip *chip = container_of(work,
439 struct mv88e6xxx_chip,
441 mv88e6xxx_g1_irq_thread_work(chip);
443 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
444 msecs_to_jiffies(100));
447 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
451 err = mv88e6xxx_g1_irq_setup_common(chip);
455 kthread_init_delayed_work(&chip->irq_poll_work,
458 chip->kworker = kthread_create_worker(0, dev_name(chip->dev));
459 if (IS_ERR(chip->kworker))
460 return PTR_ERR(chip->kworker);
462 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
463 msecs_to_jiffies(100));
468 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
470 mv88e6xxx_g1_irq_free_common(chip);
472 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
473 kthread_destroy_worker(chip->kworker);
476 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
480 for (i = 0; i < 16; i++) {
484 err = mv88e6xxx_read(chip, addr, reg, &val);
491 usleep_range(1000, 2000);
494 dev_err(chip->dev, "Timeout while waiting for switch\n");
498 /* Indirect write to single pointer-data register with an Update bit */
499 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
504 /* Wait until the previous operation is completed */
505 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
509 /* Set the Update bit to trigger a write operation */
510 val = BIT(15) | update;
512 return mv88e6xxx_write(chip, addr, reg, val);
515 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
516 int link, int speed, int duplex,
517 phy_interface_t mode)
521 if (!chip->info->ops->port_set_link)
524 /* Port's MAC control must not be changed unless the link is down */
525 err = chip->info->ops->port_set_link(chip, port, 0);
529 if (chip->info->ops->port_set_speed) {
530 err = chip->info->ops->port_set_speed(chip, port, speed);
531 if (err && err != -EOPNOTSUPP)
535 if (chip->info->ops->port_set_duplex) {
536 err = chip->info->ops->port_set_duplex(chip, port, duplex);
537 if (err && err != -EOPNOTSUPP)
541 if (chip->info->ops->port_set_rgmii_delay) {
542 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
543 if (err && err != -EOPNOTSUPP)
547 if (chip->info->ops->port_set_cmode) {
548 err = chip->info->ops->port_set_cmode(chip, port, mode);
549 if (err && err != -EOPNOTSUPP)
555 if (chip->info->ops->port_set_link(chip, port, link))
556 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
561 /* We expect the switch to perform auto negotiation if there is a real
562 * phy. However, in the case of a fixed link phy, we force the port
563 * settings from the fixed link settings.
565 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
566 struct phy_device *phydev)
568 struct mv88e6xxx_chip *chip = ds->priv;
571 if (!phy_is_pseudo_fixed_link(phydev))
574 mutex_lock(&chip->reg_lock);
575 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
576 phydev->duplex, phydev->interface);
577 mutex_unlock(&chip->reg_lock);
579 if (err && err != -EOPNOTSUPP)
580 dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
583 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
585 if (!chip->info->ops->stats_snapshot)
588 return chip->info->ops->stats_snapshot(chip, port);
591 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
592 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
593 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
594 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
595 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
596 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
597 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
598 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
599 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
600 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
601 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
602 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
603 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
604 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
605 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
606 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
607 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
608 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
609 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
610 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
611 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
612 { "single", 4, 0x14, STATS_TYPE_BANK0, },
613 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
614 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
615 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
616 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
617 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
618 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
619 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
620 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
621 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
622 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
623 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
624 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
625 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
626 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
627 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
628 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
629 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
630 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
631 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
632 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
633 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
634 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
635 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
636 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
637 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
638 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
639 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
640 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
641 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
642 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
643 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
644 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
645 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
646 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
647 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
648 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
649 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
650 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
653 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
654 struct mv88e6xxx_hw_stat *s,
655 int port, u16 bank1_select,
665 case STATS_TYPE_PORT:
666 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
672 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
678 case STATS_TYPE_BANK1:
681 case STATS_TYPE_BANK0:
682 reg |= s->reg | histogram;
683 mv88e6xxx_g1_stats_read(chip, reg, &low);
685 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
690 value = (((u64)high) << 16) | low;
694 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
695 uint8_t *data, int types)
697 struct mv88e6xxx_hw_stat *stat;
700 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
701 stat = &mv88e6xxx_hw_stats[i];
702 if (stat->type & types) {
703 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
712 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
715 return mv88e6xxx_stats_get_strings(chip, data,
716 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
719 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
722 return mv88e6xxx_stats_get_strings(chip, data,
723 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
726 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
727 "atu_member_violation",
728 "atu_miss_violation",
729 "atu_full_violation",
730 "vtu_member_violation",
731 "vtu_miss_violation",
734 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
738 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
739 strlcpy(data + i * ETH_GSTRING_LEN,
740 mv88e6xxx_atu_vtu_stats_strings[i],
744 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
745 u32 stringset, uint8_t *data)
747 struct mv88e6xxx_chip *chip = ds->priv;
750 if (stringset != ETH_SS_STATS)
753 mutex_lock(&chip->reg_lock);
755 if (chip->info->ops->stats_get_strings)
756 count = chip->info->ops->stats_get_strings(chip, data);
758 if (chip->info->ops->serdes_get_strings) {
759 data += count * ETH_GSTRING_LEN;
760 count = chip->info->ops->serdes_get_strings(chip, port, data);
763 data += count * ETH_GSTRING_LEN;
764 mv88e6xxx_atu_vtu_get_strings(data);
766 mutex_unlock(&chip->reg_lock);
769 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
772 struct mv88e6xxx_hw_stat *stat;
775 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
776 stat = &mv88e6xxx_hw_stats[i];
777 if (stat->type & types)
783 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
785 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
789 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
791 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
795 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
797 struct mv88e6xxx_chip *chip = ds->priv;
798 int serdes_count = 0;
801 if (sset != ETH_SS_STATS)
804 mutex_lock(&chip->reg_lock);
805 if (chip->info->ops->stats_get_sset_count)
806 count = chip->info->ops->stats_get_sset_count(chip);
810 if (chip->info->ops->serdes_get_sset_count)
811 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
813 if (serdes_count < 0) {
814 count = serdes_count;
817 count += serdes_count;
818 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
821 mutex_unlock(&chip->reg_lock);
826 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
827 uint64_t *data, int types,
828 u16 bank1_select, u16 histogram)
830 struct mv88e6xxx_hw_stat *stat;
833 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
834 stat = &mv88e6xxx_hw_stats[i];
835 if (stat->type & types) {
836 mutex_lock(&chip->reg_lock);
837 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
840 mutex_unlock(&chip->reg_lock);
848 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
851 return mv88e6xxx_stats_get_stats(chip, port, data,
852 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
853 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
856 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
859 return mv88e6xxx_stats_get_stats(chip, port, data,
860 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
861 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
862 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
865 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
868 return mv88e6xxx_stats_get_stats(chip, port, data,
869 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
870 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
874 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
877 *data++ = chip->ports[port].atu_member_violation;
878 *data++ = chip->ports[port].atu_miss_violation;
879 *data++ = chip->ports[port].atu_full_violation;
880 *data++ = chip->ports[port].vtu_member_violation;
881 *data++ = chip->ports[port].vtu_miss_violation;
884 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
889 if (chip->info->ops->stats_get_stats)
890 count = chip->info->ops->stats_get_stats(chip, port, data);
892 mutex_lock(&chip->reg_lock);
893 if (chip->info->ops->serdes_get_stats) {
895 count = chip->info->ops->serdes_get_stats(chip, port, data);
898 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
899 mutex_unlock(&chip->reg_lock);
902 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
905 struct mv88e6xxx_chip *chip = ds->priv;
908 mutex_lock(&chip->reg_lock);
910 ret = mv88e6xxx_stats_snapshot(chip, port);
911 mutex_unlock(&chip->reg_lock);
916 mv88e6xxx_get_stats(chip, port, data);
920 static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
922 if (chip->info->ops->stats_set_histogram)
923 return chip->info->ops->stats_set_histogram(chip);
928 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
930 return 32 * sizeof(u16);
933 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
934 struct ethtool_regs *regs, void *_p)
936 struct mv88e6xxx_chip *chip = ds->priv;
944 memset(p, 0xff, 32 * sizeof(u16));
946 mutex_lock(&chip->reg_lock);
948 for (i = 0; i < 32; i++) {
950 err = mv88e6xxx_port_read(chip, port, i, ®);
955 mutex_unlock(&chip->reg_lock);
958 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
959 struct ethtool_eee *e)
961 /* Nothing to do on the port's MAC */
965 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
966 struct ethtool_eee *e)
968 /* Nothing to do on the port's MAC */
972 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
974 struct dsa_switch *ds = NULL;
975 struct net_device *br;
979 if (dev < DSA_MAX_SWITCHES)
980 ds = chip->ds->dst->ds[dev];
982 /* Prevent frames from unknown switch or port */
983 if (!ds || port >= ds->num_ports)
986 /* Frames from DSA links and CPU ports can egress any local port */
987 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
988 return mv88e6xxx_port_mask(chip);
990 br = ds->ports[port].bridge_dev;
993 /* Frames from user ports can egress any local DSA links and CPU ports,
994 * as well as any local member of their bridge group.
996 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
997 if (dsa_is_cpu_port(chip->ds, i) ||
998 dsa_is_dsa_port(chip->ds, i) ||
999 (br && dsa_to_port(chip->ds, i)->bridge_dev == br))
1005 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1007 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1009 /* prevent frames from going back out of the port they came in on */
1010 output_ports &= ~BIT(port);
1012 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1015 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1018 struct mv88e6xxx_chip *chip = ds->priv;
1021 mutex_lock(&chip->reg_lock);
1022 err = mv88e6xxx_port_set_state(chip, port, state);
1023 mutex_unlock(&chip->reg_lock);
1026 dev_err(ds->dev, "p%d: failed to update state\n", port);
1029 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1031 /* Clear all trunk masks and mapping */
1032 if (chip->info->global2_addr)
1033 return mv88e6xxx_g2_trunk_clear(chip);
1038 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1040 if (chip->info->ops->pot_clear)
1041 return chip->info->ops->pot_clear(chip);
1046 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1048 if (chip->info->ops->mgmt_rsvd2cpu)
1049 return chip->info->ops->mgmt_rsvd2cpu(chip);
1054 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1058 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1062 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1066 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1069 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1074 if (!chip->info->ops->irl_init_all)
1077 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1078 /* Disable ingress rate limiting by resetting all per port
1079 * ingress rate limit resources to their initial state.
1081 err = chip->info->ops->irl_init_all(chip, port);
1089 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1091 if (chip->info->ops->set_switch_mac) {
1094 eth_random_addr(addr);
1096 return chip->info->ops->set_switch_mac(chip, addr);
1102 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1106 if (!mv88e6xxx_has_pvt(chip))
1109 /* Skip the local source device, which uses in-chip port VLAN */
1110 if (dev != chip->ds->index)
1111 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1113 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1116 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1121 if (!mv88e6xxx_has_pvt(chip))
1124 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1125 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1127 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1131 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1132 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1133 err = mv88e6xxx_pvt_map(chip, dev, port);
1142 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1144 struct mv88e6xxx_chip *chip = ds->priv;
1147 mutex_lock(&chip->reg_lock);
1148 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1149 mutex_unlock(&chip->reg_lock);
1152 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1155 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1157 if (!chip->info->max_vid)
1160 return mv88e6xxx_g1_vtu_flush(chip);
1163 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1164 struct mv88e6xxx_vtu_entry *entry)
1166 if (!chip->info->ops->vtu_getnext)
1169 return chip->info->ops->vtu_getnext(chip, entry);
1172 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1173 struct mv88e6xxx_vtu_entry *entry)
1175 if (!chip->info->ops->vtu_loadpurge)
1178 return chip->info->ops->vtu_loadpurge(chip, entry);
1181 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1183 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1184 struct mv88e6xxx_vtu_entry vlan = {
1185 .vid = chip->info->max_vid,
1189 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1191 /* Set every FID bit used by the (un)bridged ports */
1192 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1193 err = mv88e6xxx_port_get_fid(chip, i, fid);
1197 set_bit(*fid, fid_bitmap);
1200 /* Set every FID bit used by the VLAN entries */
1202 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1209 set_bit(vlan.fid, fid_bitmap);
1210 } while (vlan.vid < chip->info->max_vid);
1212 /* The reset value 0x000 is used to indicate that multiple address
1213 * databases are not needed. Return the next positive available.
1215 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1216 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1219 /* Clear the database */
1220 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1223 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1224 struct mv88e6xxx_vtu_entry *entry, bool new)
1231 entry->vid = vid - 1;
1232 entry->valid = false;
1234 err = mv88e6xxx_vtu_getnext(chip, entry);
1238 if (entry->vid == vid && entry->valid)
1244 /* Initialize a fresh VLAN entry */
1245 memset(entry, 0, sizeof(*entry));
1246 entry->valid = true;
1249 /* Exclude all ports */
1250 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1252 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1254 return mv88e6xxx_atu_new(chip, &entry->fid);
1257 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1261 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1262 u16 vid_begin, u16 vid_end)
1264 struct mv88e6xxx_chip *chip = ds->priv;
1265 struct mv88e6xxx_vtu_entry vlan = {
1266 .vid = vid_begin - 1,
1270 /* DSA and CPU ports have to be members of multiple vlans */
1271 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1277 mutex_lock(&chip->reg_lock);
1280 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1287 if (vlan.vid > vid_end)
1290 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1291 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1294 if (!ds->ports[i].slave)
1297 if (vlan.member[i] ==
1298 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1301 if (dsa_to_port(ds, i)->bridge_dev ==
1302 ds->ports[port].bridge_dev)
1303 break; /* same bridge, check next VLAN */
1305 if (!dsa_to_port(ds, i)->bridge_dev)
1308 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1310 netdev_name(dsa_to_port(ds, i)->bridge_dev));
1314 } while (vlan.vid < vid_end);
1317 mutex_unlock(&chip->reg_lock);
1322 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1323 bool vlan_filtering)
1325 struct mv88e6xxx_chip *chip = ds->priv;
1326 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1327 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1330 if (!chip->info->max_vid)
1333 mutex_lock(&chip->reg_lock);
1334 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1335 mutex_unlock(&chip->reg_lock);
1341 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1342 const struct switchdev_obj_port_vlan *vlan)
1344 struct mv88e6xxx_chip *chip = ds->priv;
1347 if (!chip->info->max_vid)
1350 /* If the requested port doesn't belong to the same bridge as the VLAN
1351 * members, do not support it (yet) and fallback to software VLAN.
1353 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1358 /* We don't need any dynamic resource from the kernel (yet),
1359 * so skip the prepare phase.
1364 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1365 const unsigned char *addr, u16 vid,
1368 struct mv88e6xxx_vtu_entry vlan;
1369 struct mv88e6xxx_atu_entry entry;
1372 /* Null VLAN ID corresponds to the port private database */
1374 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
1376 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1380 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1381 ether_addr_copy(entry.mac, addr);
1382 eth_addr_dec(entry.mac);
1384 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
1388 /* Initialize a fresh ATU entry if it isn't found */
1389 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
1390 !ether_addr_equal(entry.mac, addr)) {
1391 memset(&entry, 0, sizeof(entry));
1392 ether_addr_copy(entry.mac, addr);
1395 /* Purge the ATU entry only if no port is using it anymore */
1396 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
1397 entry.portvec &= ~BIT(port);
1399 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1401 entry.portvec |= BIT(port);
1402 entry.state = state;
1405 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
1408 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
1411 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1412 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
1414 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
1417 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
1422 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1423 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
1431 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1434 struct mv88e6xxx_vtu_entry vlan;
1437 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1441 vlan.member[port] = member;
1443 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1447 return mv88e6xxx_broadcast_setup(chip, vid);
1450 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1451 const struct switchdev_obj_port_vlan *vlan)
1453 struct mv88e6xxx_chip *chip = ds->priv;
1454 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1455 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1459 if (!chip->info->max_vid)
1462 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1463 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1465 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1467 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1469 mutex_lock(&chip->reg_lock);
1471 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1472 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
1473 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1474 vid, untagged ? 'u' : 't');
1476 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1477 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
1480 mutex_unlock(&chip->reg_lock);
1483 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1486 struct mv88e6xxx_vtu_entry vlan;
1489 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1493 /* Tell switchdev if this VLAN is handled in software */
1494 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1497 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1499 /* keep the VLAN unless all ports are excluded */
1501 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1502 if (vlan.member[i] !=
1503 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1509 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1513 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
1516 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1517 const struct switchdev_obj_port_vlan *vlan)
1519 struct mv88e6xxx_chip *chip = ds->priv;
1523 if (!chip->info->max_vid)
1526 mutex_lock(&chip->reg_lock);
1528 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1532 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1533 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1538 err = mv88e6xxx_port_set_pvid(chip, port, 0);
1545 mutex_unlock(&chip->reg_lock);
1550 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1551 const unsigned char *addr, u16 vid)
1553 struct mv88e6xxx_chip *chip = ds->priv;
1556 mutex_lock(&chip->reg_lock);
1557 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1558 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1559 mutex_unlock(&chip->reg_lock);
1564 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1565 const unsigned char *addr, u16 vid)
1567 struct mv88e6xxx_chip *chip = ds->priv;
1570 mutex_lock(&chip->reg_lock);
1571 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1572 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
1573 mutex_unlock(&chip->reg_lock);
1578 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
1579 u16 fid, u16 vid, int port,
1580 dsa_fdb_dump_cb_t *cb, void *data)
1582 struct mv88e6xxx_atu_entry addr;
1586 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1587 eth_broadcast_addr(addr.mac);
1590 mutex_lock(&chip->reg_lock);
1591 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
1592 mutex_unlock(&chip->reg_lock);
1596 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
1599 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
1602 if (!is_unicast_ether_addr(addr.mac))
1605 is_static = (addr.state ==
1606 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1607 err = cb(addr.mac, vid, is_static, data);
1610 } while (!is_broadcast_ether_addr(addr.mac));
1615 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
1616 dsa_fdb_dump_cb_t *cb, void *data)
1618 struct mv88e6xxx_vtu_entry vlan = {
1619 .vid = chip->info->max_vid,
1624 /* Dump port's default Filtering Information Database (VLAN ID 0) */
1625 mutex_lock(&chip->reg_lock);
1626 err = mv88e6xxx_port_get_fid(chip, port, &fid);
1627 mutex_unlock(&chip->reg_lock);
1632 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
1636 /* Dump VLANs' Filtering Information Databases */
1638 mutex_lock(&chip->reg_lock);
1639 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1640 mutex_unlock(&chip->reg_lock);
1647 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
1651 } while (vlan.vid < chip->info->max_vid);
1656 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1657 dsa_fdb_dump_cb_t *cb, void *data)
1659 struct mv88e6xxx_chip *chip = ds->priv;
1661 return mv88e6xxx_port_db_dump(chip, port, cb, data);
1664 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
1665 struct net_device *br)
1667 struct dsa_switch *ds;
1672 /* Remap the Port VLAN of each local bridge group member */
1673 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
1674 if (chip->ds->ports[port].bridge_dev == br) {
1675 err = mv88e6xxx_port_vlan_map(chip, port);
1681 if (!mv88e6xxx_has_pvt(chip))
1684 /* Remap the Port VLAN of each cross-chip bridge group member */
1685 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
1686 ds = chip->ds->dst->ds[dev];
1690 for (port = 0; port < ds->num_ports; ++port) {
1691 if (ds->ports[port].bridge_dev == br) {
1692 err = mv88e6xxx_pvt_map(chip, dev, port);
1702 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
1703 struct net_device *br)
1705 struct mv88e6xxx_chip *chip = ds->priv;
1708 mutex_lock(&chip->reg_lock);
1709 err = mv88e6xxx_bridge_map(chip, br);
1710 mutex_unlock(&chip->reg_lock);
1715 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
1716 struct net_device *br)
1718 struct mv88e6xxx_chip *chip = ds->priv;
1720 mutex_lock(&chip->reg_lock);
1721 if (mv88e6xxx_bridge_map(chip, br) ||
1722 mv88e6xxx_port_vlan_map(chip, port))
1723 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
1724 mutex_unlock(&chip->reg_lock);
1727 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
1728 int port, struct net_device *br)
1730 struct mv88e6xxx_chip *chip = ds->priv;
1733 if (!mv88e6xxx_has_pvt(chip))
1736 mutex_lock(&chip->reg_lock);
1737 err = mv88e6xxx_pvt_map(chip, dev, port);
1738 mutex_unlock(&chip->reg_lock);
1743 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
1744 int port, struct net_device *br)
1746 struct mv88e6xxx_chip *chip = ds->priv;
1748 if (!mv88e6xxx_has_pvt(chip))
1751 mutex_lock(&chip->reg_lock);
1752 if (mv88e6xxx_pvt_map(chip, dev, port))
1753 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
1754 mutex_unlock(&chip->reg_lock);
1757 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
1759 if (chip->info->ops->reset)
1760 return chip->info->ops->reset(chip);
1765 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
1767 struct gpio_desc *gpiod = chip->reset;
1769 /* If there is a GPIO connected to the reset pin, toggle it */
1771 gpiod_set_value_cansleep(gpiod, 1);
1772 usleep_range(10000, 20000);
1773 gpiod_set_value_cansleep(gpiod, 0);
1774 usleep_range(10000, 20000);
1778 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
1782 /* Set all ports to the Disabled state */
1783 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
1784 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
1789 /* Wait for transmit queues to drain,
1790 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
1792 usleep_range(2000, 4000);
1797 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
1801 err = mv88e6xxx_disable_ports(chip);
1805 mv88e6xxx_hardware_reset(chip);
1807 return mv88e6xxx_software_reset(chip);
1810 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
1811 enum mv88e6xxx_frame_mode frame,
1812 enum mv88e6xxx_egress_mode egress, u16 etype)
1816 if (!chip->info->ops->port_set_frame_mode)
1819 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
1823 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
1827 if (chip->info->ops->port_set_ether_type)
1828 return chip->info->ops->port_set_ether_type(chip, port, etype);
1833 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
1835 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
1836 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1837 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1840 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
1842 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
1843 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
1844 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
1847 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
1849 return mv88e6xxx_set_port_mode(chip, port,
1850 MV88E6XXX_FRAME_MODE_ETHERTYPE,
1851 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
1855 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
1857 if (dsa_is_dsa_port(chip->ds, port))
1858 return mv88e6xxx_set_port_mode_dsa(chip, port);
1860 if (dsa_is_user_port(chip->ds, port))
1861 return mv88e6xxx_set_port_mode_normal(chip, port);
1863 /* Setup CPU port mode depending on its supported tag format */
1864 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
1865 return mv88e6xxx_set_port_mode_dsa(chip, port);
1867 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
1868 return mv88e6xxx_set_port_mode_edsa(chip, port);
1873 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
1875 bool message = dsa_is_dsa_port(chip->ds, port);
1877 return mv88e6xxx_port_set_message_port(chip, port, message);
1880 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
1882 struct dsa_switch *ds = chip->ds;
1885 /* Upstream ports flood frames with unknown unicast or multicast DA */
1886 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port);
1887 if (chip->info->ops->port_set_egress_floods)
1888 return chip->info->ops->port_set_egress_floods(chip, port,
1894 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
1897 if (chip->info->ops->serdes_power)
1898 return chip->info->ops->serdes_power(chip, port, on);
1903 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
1905 struct dsa_switch *ds = chip->ds;
1909 upstream_port = dsa_upstream_port(ds, port);
1910 if (chip->info->ops->port_set_upstream_port) {
1911 err = chip->info->ops->port_set_upstream_port(chip, port,
1917 if (port == upstream_port) {
1918 if (chip->info->ops->set_cpu_port) {
1919 err = chip->info->ops->set_cpu_port(chip,
1925 if (chip->info->ops->set_egress_port) {
1926 err = chip->info->ops->set_egress_port(chip,
1936 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
1938 struct dsa_switch *ds = chip->ds;
1942 /* MAC Forcing register: don't force link, speed, duplex or flow control
1943 * state to any particular values on physical ports, but force the CPU
1944 * port and all DSA ports to their maximum bandwidth and full duplex.
1946 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1947 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
1948 SPEED_MAX, DUPLEX_FULL,
1949 PHY_INTERFACE_MODE_NA);
1951 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
1952 SPEED_UNFORCED, DUPLEX_UNFORCED,
1953 PHY_INTERFACE_MODE_NA);
1957 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
1958 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
1959 * tunneling, determine priority by looking at 802.1p and IP
1960 * priority fields (IP prio has precedence), and set STP state
1963 * If this is the CPU link, use DSA or EDSA tagging depending
1964 * on which tagging mode was configured.
1966 * If this is a link to another switch, use DSA tagging mode.
1968 * If this is the upstream port for this switch, enable
1969 * forwarding of unknown unicasts and multicasts.
1971 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
1972 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
1973 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
1974 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
1978 err = mv88e6xxx_setup_port_mode(chip, port);
1982 err = mv88e6xxx_setup_egress_floods(chip, port);
1986 /* Enable the SERDES interface for DSA and CPU ports. Normal
1987 * ports SERDES are enabled when the port is enabled, thus
1988 * saving a bit of power.
1990 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
1991 err = mv88e6xxx_serdes_power(chip, port, true);
1996 /* Port Control 2: don't force a good FCS, set the maximum frame size to
1997 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
1998 * untagged frames on this port, do a destination address lookup on all
1999 * received packets as usual, disable ARP mirroring and don't send a
2000 * copy of all transmitted/received frames on this port to the CPU.
2002 err = mv88e6xxx_port_set_map_da(chip, port);
2006 err = mv88e6xxx_setup_upstream_port(chip, port);
2010 err = mv88e6xxx_port_set_8021q_mode(chip, port,
2011 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
2015 if (chip->info->ops->port_set_jumbo_size) {
2016 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
2021 /* Port Association Vector: when learning source addresses
2022 * of packets, add the address to the address database using
2023 * a port bitmap that has only the bit for this port set and
2024 * the other bits clear.
2027 /* Disable learning for CPU port */
2028 if (dsa_is_cpu_port(ds, port))
2031 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
2036 /* Egress rate control 2: disable egress rate control. */
2037 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
2042 if (chip->info->ops->port_pause_limit) {
2043 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
2048 if (chip->info->ops->port_disable_learn_limit) {
2049 err = chip->info->ops->port_disable_learn_limit(chip, port);
2054 if (chip->info->ops->port_disable_pri_override) {
2055 err = chip->info->ops->port_disable_pri_override(chip, port);
2060 if (chip->info->ops->port_tag_remap) {
2061 err = chip->info->ops->port_tag_remap(chip, port);
2066 if (chip->info->ops->port_egress_rate_limiting) {
2067 err = chip->info->ops->port_egress_rate_limiting(chip, port);
2072 err = mv88e6xxx_setup_message_port(chip, port);
2076 /* Port based VLAN map: give each port the same default address
2077 * database, and allow bidirectional communication between the
2078 * CPU and DSA port(s), and the other ports.
2080 err = mv88e6xxx_port_set_fid(chip, port, 0);
2084 err = mv88e6xxx_port_vlan_map(chip, port);
2088 /* Default VLAN ID and priority: don't set a default VLAN
2089 * ID, and set the default packet priority to zero.
2091 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2094 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
2095 struct phy_device *phydev)
2097 struct mv88e6xxx_chip *chip = ds->priv;
2100 mutex_lock(&chip->reg_lock);
2101 err = mv88e6xxx_serdes_power(chip, port, true);
2102 mutex_unlock(&chip->reg_lock);
2107 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port,
2108 struct phy_device *phydev)
2110 struct mv88e6xxx_chip *chip = ds->priv;
2112 mutex_lock(&chip->reg_lock);
2113 if (mv88e6xxx_serdes_power(chip, port, false))
2114 dev_err(chip->dev, "failed to power off SERDES\n");
2115 mutex_unlock(&chip->reg_lock);
2118 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2119 unsigned int ageing_time)
2121 struct mv88e6xxx_chip *chip = ds->priv;
2124 mutex_lock(&chip->reg_lock);
2125 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2126 mutex_unlock(&chip->reg_lock);
2131 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
2133 struct dsa_switch *ds = chip->ds;
2136 /* Disable remote management, and set the switch's DSA device number. */
2137 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2,
2138 MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE |
2139 (ds->index & 0x1f));
2143 /* Configure the IP ToS mapping registers. */
2144 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
2147 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
2150 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
2153 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
2156 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
2159 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
2162 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
2165 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
2169 /* Configure the IEEE 802.1p priority mapping register. */
2170 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
2174 /* Initialize the statistics unit */
2175 err = mv88e6xxx_stats_set_histogram(chip);
2179 return mv88e6xxx_g1_stats_clear(chip);
2182 static int mv88e6xxx_setup(struct dsa_switch *ds)
2184 struct mv88e6xxx_chip *chip = ds->priv;
2189 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2191 mutex_lock(&chip->reg_lock);
2193 /* Setup Switch Port Registers */
2194 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2195 if (dsa_is_unused_port(ds, i))
2198 err = mv88e6xxx_setup_port(chip, i);
2203 /* Setup Switch Global 1 Registers */
2204 err = mv88e6xxx_g1_setup(chip);
2208 /* Setup Switch Global 2 Registers */
2209 if (chip->info->global2_addr) {
2210 err = mv88e6xxx_g2_setup(chip);
2215 err = mv88e6xxx_irl_setup(chip);
2219 err = mv88e6xxx_mac_setup(chip);
2223 err = mv88e6xxx_phy_setup(chip);
2227 err = mv88e6xxx_vtu_setup(chip);
2231 err = mv88e6xxx_pvt_setup(chip);
2235 err = mv88e6xxx_atu_setup(chip);
2239 err = mv88e6xxx_broadcast_setup(chip, 0);
2243 err = mv88e6xxx_pot_setup(chip);
2247 err = mv88e6xxx_rsvd2cpu_setup(chip);
2251 err = mv88e6xxx_trunk_setup(chip);
2255 /* Setup PTP Hardware Clock and timestamping */
2256 if (chip->info->ptp_support) {
2257 err = mv88e6xxx_ptp_setup(chip);
2261 err = mv88e6xxx_hwtstamp_setup(chip);
2267 mutex_unlock(&chip->reg_lock);
2272 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2274 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2275 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2279 if (!chip->info->ops->phy_read)
2282 mutex_lock(&chip->reg_lock);
2283 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
2284 mutex_unlock(&chip->reg_lock);
2286 if (reg == MII_PHYSID2) {
2287 /* Some internal PHYS don't have a model number. Use
2288 * the mv88e6390 family model number instead.
2291 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
2294 return err ? err : val;
2297 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2299 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2300 struct mv88e6xxx_chip *chip = mdio_bus->chip;
2303 if (!chip->info->ops->phy_write)
2306 mutex_lock(&chip->reg_lock);
2307 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
2308 mutex_unlock(&chip->reg_lock);
2313 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2314 struct device_node *np,
2318 struct mv88e6xxx_mdio_bus *mdio_bus;
2319 struct mii_bus *bus;
2323 mutex_lock(&chip->reg_lock);
2324 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
2325 mutex_unlock(&chip->reg_lock);
2331 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
2335 mdio_bus = bus->priv;
2336 mdio_bus->bus = bus;
2337 mdio_bus->chip = chip;
2338 INIT_LIST_HEAD(&mdio_bus->list);
2339 mdio_bus->external = external;
2342 bus->name = np->full_name;
2343 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
2345 bus->name = "mv88e6xxx SMI";
2346 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2349 bus->read = mv88e6xxx_mdio_read;
2350 bus->write = mv88e6xxx_mdio_write;
2351 bus->parent = chip->dev;
2354 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
2360 err = of_mdiobus_register(bus, np);
2362 err = mdiobus_register(bus);
2364 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2365 mv88e6xxx_g2_irq_mdio_free(chip, bus);
2370 list_add_tail(&mdio_bus->list, &chip->mdios);
2372 list_add(&mdio_bus->list, &chip->mdios);
2377 static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2378 { .compatible = "marvell,mv88e6xxx-mdio-external",
2379 .data = (void *)true },
2383 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
2386 struct mv88e6xxx_mdio_bus *mdio_bus;
2387 struct mii_bus *bus;
2389 list_for_each_entry(mdio_bus, &chip->mdios, list) {
2390 bus = mdio_bus->bus;
2392 if (!mdio_bus->external)
2393 mv88e6xxx_g2_irq_mdio_free(chip, bus);
2395 mdiobus_unregister(bus);
2399 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2400 struct device_node *np)
2402 const struct of_device_id *match;
2403 struct device_node *child;
2406 /* Always register one mdio bus for the internal/default mdio
2407 * bus. This maybe represented in the device tree, but is
2410 child = of_get_child_by_name(np, "mdio");
2411 err = mv88e6xxx_mdio_register(chip, child, false);
2415 /* Walk the device tree, and see if there are any other nodes
2416 * which say they are compatible with the external mdio
2419 for_each_available_child_of_node(np, child) {
2420 match = of_match_node(mv88e6xxx_mdio_external_match, child);
2422 err = mv88e6xxx_mdio_register(chip, child, true);
2424 mv88e6xxx_mdios_unregister(chip);
2433 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
2435 struct mv88e6xxx_chip *chip = ds->priv;
2437 return chip->eeprom_len;
2440 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
2441 struct ethtool_eeprom *eeprom, u8 *data)
2443 struct mv88e6xxx_chip *chip = ds->priv;
2446 if (!chip->info->ops->get_eeprom)
2449 mutex_lock(&chip->reg_lock);
2450 err = chip->info->ops->get_eeprom(chip, eeprom, data);
2451 mutex_unlock(&chip->reg_lock);
2456 eeprom->magic = 0xc3ec4951;
2461 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
2462 struct ethtool_eeprom *eeprom, u8 *data)
2464 struct mv88e6xxx_chip *chip = ds->priv;
2467 if (!chip->info->ops->set_eeprom)
2470 if (eeprom->magic != 0xc3ec4951)
2473 mutex_lock(&chip->reg_lock);
2474 err = chip->info->ops->set_eeprom(chip, eeprom, data);
2475 mutex_unlock(&chip->reg_lock);
2480 static const struct mv88e6xxx_ops mv88e6085_ops = {
2481 /* MV88E6XXX_FAMILY_6097 */
2482 .irl_init_all = mv88e6352_g2_irl_init_all,
2483 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2484 .phy_read = mv88e6185_phy_ppu_read,
2485 .phy_write = mv88e6185_phy_ppu_write,
2486 .port_set_link = mv88e6xxx_port_set_link,
2487 .port_set_duplex = mv88e6xxx_port_set_duplex,
2488 .port_set_speed = mv88e6185_port_set_speed,
2489 .port_tag_remap = mv88e6095_port_tag_remap,
2490 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2491 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2492 .port_set_ether_type = mv88e6351_port_set_ether_type,
2493 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2494 .port_pause_limit = mv88e6097_port_pause_limit,
2495 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2496 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2497 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2498 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2499 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2500 .stats_get_strings = mv88e6095_stats_get_strings,
2501 .stats_get_stats = mv88e6095_stats_get_stats,
2502 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2503 .set_egress_port = mv88e6095_g1_set_egress_port,
2504 .watchdog_ops = &mv88e6097_watchdog_ops,
2505 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2506 .pot_clear = mv88e6xxx_g2_pot_clear,
2507 .ppu_enable = mv88e6185_g1_ppu_enable,
2508 .ppu_disable = mv88e6185_g1_ppu_disable,
2509 .reset = mv88e6185_g1_reset,
2510 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2511 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2514 static const struct mv88e6xxx_ops mv88e6095_ops = {
2515 /* MV88E6XXX_FAMILY_6095 */
2516 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2517 .phy_read = mv88e6185_phy_ppu_read,
2518 .phy_write = mv88e6185_phy_ppu_write,
2519 .port_set_link = mv88e6xxx_port_set_link,
2520 .port_set_duplex = mv88e6xxx_port_set_duplex,
2521 .port_set_speed = mv88e6185_port_set_speed,
2522 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2523 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2524 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2525 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2526 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2527 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2528 .stats_get_strings = mv88e6095_stats_get_strings,
2529 .stats_get_stats = mv88e6095_stats_get_stats,
2530 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2531 .ppu_enable = mv88e6185_g1_ppu_enable,
2532 .ppu_disable = mv88e6185_g1_ppu_disable,
2533 .reset = mv88e6185_g1_reset,
2534 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2535 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2538 static const struct mv88e6xxx_ops mv88e6097_ops = {
2539 /* MV88E6XXX_FAMILY_6097 */
2540 .irl_init_all = mv88e6352_g2_irl_init_all,
2541 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2542 .phy_read = mv88e6xxx_g2_smi_phy_read,
2543 .phy_write = mv88e6xxx_g2_smi_phy_write,
2544 .port_set_link = mv88e6xxx_port_set_link,
2545 .port_set_duplex = mv88e6xxx_port_set_duplex,
2546 .port_set_speed = mv88e6185_port_set_speed,
2547 .port_tag_remap = mv88e6095_port_tag_remap,
2548 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2549 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2550 .port_set_ether_type = mv88e6351_port_set_ether_type,
2551 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2552 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2553 .port_pause_limit = mv88e6097_port_pause_limit,
2554 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2555 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2556 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2557 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2558 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2559 .stats_get_strings = mv88e6095_stats_get_strings,
2560 .stats_get_stats = mv88e6095_stats_get_stats,
2561 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2562 .set_egress_port = mv88e6095_g1_set_egress_port,
2563 .watchdog_ops = &mv88e6097_watchdog_ops,
2564 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2565 .pot_clear = mv88e6xxx_g2_pot_clear,
2566 .reset = mv88e6352_g1_reset,
2567 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2568 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2571 static const struct mv88e6xxx_ops mv88e6123_ops = {
2572 /* MV88E6XXX_FAMILY_6165 */
2573 .irl_init_all = mv88e6352_g2_irl_init_all,
2574 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2575 .phy_read = mv88e6xxx_g2_smi_phy_read,
2576 .phy_write = mv88e6xxx_g2_smi_phy_write,
2577 .port_set_link = mv88e6xxx_port_set_link,
2578 .port_set_duplex = mv88e6xxx_port_set_duplex,
2579 .port_set_speed = mv88e6185_port_set_speed,
2580 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2581 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2582 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2583 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2584 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2585 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2586 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2587 .stats_get_strings = mv88e6095_stats_get_strings,
2588 .stats_get_stats = mv88e6095_stats_get_stats,
2589 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2590 .set_egress_port = mv88e6095_g1_set_egress_port,
2591 .watchdog_ops = &mv88e6097_watchdog_ops,
2592 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2593 .pot_clear = mv88e6xxx_g2_pot_clear,
2594 .reset = mv88e6352_g1_reset,
2595 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2596 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2599 static const struct mv88e6xxx_ops mv88e6131_ops = {
2600 /* MV88E6XXX_FAMILY_6185 */
2601 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2602 .phy_read = mv88e6185_phy_ppu_read,
2603 .phy_write = mv88e6185_phy_ppu_write,
2604 .port_set_link = mv88e6xxx_port_set_link,
2605 .port_set_duplex = mv88e6xxx_port_set_duplex,
2606 .port_set_speed = mv88e6185_port_set_speed,
2607 .port_tag_remap = mv88e6095_port_tag_remap,
2608 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2609 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2610 .port_set_ether_type = mv88e6351_port_set_ether_type,
2611 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2612 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2613 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2614 .port_pause_limit = mv88e6097_port_pause_limit,
2615 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2616 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2617 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2618 .stats_get_strings = mv88e6095_stats_get_strings,
2619 .stats_get_stats = mv88e6095_stats_get_stats,
2620 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2621 .set_egress_port = mv88e6095_g1_set_egress_port,
2622 .watchdog_ops = &mv88e6097_watchdog_ops,
2623 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2624 .ppu_enable = mv88e6185_g1_ppu_enable,
2625 .ppu_disable = mv88e6185_g1_ppu_disable,
2626 .reset = mv88e6185_g1_reset,
2627 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2628 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2631 static const struct mv88e6xxx_ops mv88e6141_ops = {
2632 /* MV88E6XXX_FAMILY_6341 */
2633 .irl_init_all = mv88e6352_g2_irl_init_all,
2634 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2635 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2636 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2637 .phy_read = mv88e6xxx_g2_smi_phy_read,
2638 .phy_write = mv88e6xxx_g2_smi_phy_write,
2639 .port_set_link = mv88e6xxx_port_set_link,
2640 .port_set_duplex = mv88e6xxx_port_set_duplex,
2641 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2642 .port_set_speed = mv88e6390_port_set_speed,
2643 .port_tag_remap = mv88e6095_port_tag_remap,
2644 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2645 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2646 .port_set_ether_type = mv88e6351_port_set_ether_type,
2647 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2648 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2649 .port_pause_limit = mv88e6097_port_pause_limit,
2650 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2651 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2652 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2653 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2654 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2655 .stats_get_strings = mv88e6320_stats_get_strings,
2656 .stats_get_stats = mv88e6390_stats_get_stats,
2657 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2658 .set_egress_port = mv88e6390_g1_set_egress_port,
2659 .watchdog_ops = &mv88e6390_watchdog_ops,
2660 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2661 .pot_clear = mv88e6xxx_g2_pot_clear,
2662 .reset = mv88e6352_g1_reset,
2663 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2664 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2665 .gpio_ops = &mv88e6352_gpio_ops,
2668 static const struct mv88e6xxx_ops mv88e6161_ops = {
2669 /* MV88E6XXX_FAMILY_6165 */
2670 .irl_init_all = mv88e6352_g2_irl_init_all,
2671 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2672 .phy_read = mv88e6xxx_g2_smi_phy_read,
2673 .phy_write = mv88e6xxx_g2_smi_phy_write,
2674 .port_set_link = mv88e6xxx_port_set_link,
2675 .port_set_duplex = mv88e6xxx_port_set_duplex,
2676 .port_set_speed = mv88e6185_port_set_speed,
2677 .port_tag_remap = mv88e6095_port_tag_remap,
2678 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2679 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2680 .port_set_ether_type = mv88e6351_port_set_ether_type,
2681 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2682 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2683 .port_pause_limit = mv88e6097_port_pause_limit,
2684 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2685 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2686 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2687 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2688 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2689 .stats_get_strings = mv88e6095_stats_get_strings,
2690 .stats_get_stats = mv88e6095_stats_get_stats,
2691 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2692 .set_egress_port = mv88e6095_g1_set_egress_port,
2693 .watchdog_ops = &mv88e6097_watchdog_ops,
2694 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2695 .pot_clear = mv88e6xxx_g2_pot_clear,
2696 .reset = mv88e6352_g1_reset,
2697 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2698 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2701 static const struct mv88e6xxx_ops mv88e6165_ops = {
2702 /* MV88E6XXX_FAMILY_6165 */
2703 .irl_init_all = mv88e6352_g2_irl_init_all,
2704 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2705 .phy_read = mv88e6165_phy_read,
2706 .phy_write = mv88e6165_phy_write,
2707 .port_set_link = mv88e6xxx_port_set_link,
2708 .port_set_duplex = mv88e6xxx_port_set_duplex,
2709 .port_set_speed = mv88e6185_port_set_speed,
2710 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2711 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2712 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2713 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2714 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2715 .stats_get_strings = mv88e6095_stats_get_strings,
2716 .stats_get_stats = mv88e6095_stats_get_stats,
2717 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2718 .set_egress_port = mv88e6095_g1_set_egress_port,
2719 .watchdog_ops = &mv88e6097_watchdog_ops,
2720 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2721 .pot_clear = mv88e6xxx_g2_pot_clear,
2722 .reset = mv88e6352_g1_reset,
2723 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2724 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2727 static const struct mv88e6xxx_ops mv88e6171_ops = {
2728 /* MV88E6XXX_FAMILY_6351 */
2729 .irl_init_all = mv88e6352_g2_irl_init_all,
2730 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2731 .phy_read = mv88e6xxx_g2_smi_phy_read,
2732 .phy_write = mv88e6xxx_g2_smi_phy_write,
2733 .port_set_link = mv88e6xxx_port_set_link,
2734 .port_set_duplex = mv88e6xxx_port_set_duplex,
2735 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2736 .port_set_speed = mv88e6185_port_set_speed,
2737 .port_tag_remap = mv88e6095_port_tag_remap,
2738 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2739 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2740 .port_set_ether_type = mv88e6351_port_set_ether_type,
2741 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2742 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2743 .port_pause_limit = mv88e6097_port_pause_limit,
2744 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2745 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2746 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2747 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2748 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2749 .stats_get_strings = mv88e6095_stats_get_strings,
2750 .stats_get_stats = mv88e6095_stats_get_stats,
2751 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2752 .set_egress_port = mv88e6095_g1_set_egress_port,
2753 .watchdog_ops = &mv88e6097_watchdog_ops,
2754 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2755 .pot_clear = mv88e6xxx_g2_pot_clear,
2756 .reset = mv88e6352_g1_reset,
2757 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2758 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2761 static const struct mv88e6xxx_ops mv88e6172_ops = {
2762 /* MV88E6XXX_FAMILY_6352 */
2763 .irl_init_all = mv88e6352_g2_irl_init_all,
2764 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2765 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2766 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2767 .phy_read = mv88e6xxx_g2_smi_phy_read,
2768 .phy_write = mv88e6xxx_g2_smi_phy_write,
2769 .port_set_link = mv88e6xxx_port_set_link,
2770 .port_set_duplex = mv88e6xxx_port_set_duplex,
2771 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2772 .port_set_speed = mv88e6352_port_set_speed,
2773 .port_tag_remap = mv88e6095_port_tag_remap,
2774 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2775 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2776 .port_set_ether_type = mv88e6351_port_set_ether_type,
2777 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2778 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2779 .port_pause_limit = mv88e6097_port_pause_limit,
2780 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2781 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2782 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2783 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2784 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2785 .stats_get_strings = mv88e6095_stats_get_strings,
2786 .stats_get_stats = mv88e6095_stats_get_stats,
2787 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2788 .set_egress_port = mv88e6095_g1_set_egress_port,
2789 .watchdog_ops = &mv88e6097_watchdog_ops,
2790 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2791 .pot_clear = mv88e6xxx_g2_pot_clear,
2792 .reset = mv88e6352_g1_reset,
2793 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2794 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2795 .serdes_power = mv88e6352_serdes_power,
2796 .gpio_ops = &mv88e6352_gpio_ops,
2799 static const struct mv88e6xxx_ops mv88e6175_ops = {
2800 /* MV88E6XXX_FAMILY_6351 */
2801 .irl_init_all = mv88e6352_g2_irl_init_all,
2802 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2803 .phy_read = mv88e6xxx_g2_smi_phy_read,
2804 .phy_write = mv88e6xxx_g2_smi_phy_write,
2805 .port_set_link = mv88e6xxx_port_set_link,
2806 .port_set_duplex = mv88e6xxx_port_set_duplex,
2807 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2808 .port_set_speed = mv88e6185_port_set_speed,
2809 .port_tag_remap = mv88e6095_port_tag_remap,
2810 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2811 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2812 .port_set_ether_type = mv88e6351_port_set_ether_type,
2813 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2814 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2815 .port_pause_limit = mv88e6097_port_pause_limit,
2816 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2817 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2818 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2819 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2820 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2821 .stats_get_strings = mv88e6095_stats_get_strings,
2822 .stats_get_stats = mv88e6095_stats_get_stats,
2823 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2824 .set_egress_port = mv88e6095_g1_set_egress_port,
2825 .watchdog_ops = &mv88e6097_watchdog_ops,
2826 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2827 .pot_clear = mv88e6xxx_g2_pot_clear,
2828 .reset = mv88e6352_g1_reset,
2829 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2830 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2833 static const struct mv88e6xxx_ops mv88e6176_ops = {
2834 /* MV88E6XXX_FAMILY_6352 */
2835 .irl_init_all = mv88e6352_g2_irl_init_all,
2836 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
2837 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
2838 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2839 .phy_read = mv88e6xxx_g2_smi_phy_read,
2840 .phy_write = mv88e6xxx_g2_smi_phy_write,
2841 .port_set_link = mv88e6xxx_port_set_link,
2842 .port_set_duplex = mv88e6xxx_port_set_duplex,
2843 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
2844 .port_set_speed = mv88e6352_port_set_speed,
2845 .port_tag_remap = mv88e6095_port_tag_remap,
2846 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2847 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2848 .port_set_ether_type = mv88e6351_port_set_ether_type,
2849 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2850 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2851 .port_pause_limit = mv88e6097_port_pause_limit,
2852 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2853 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2854 .stats_snapshot = mv88e6320_g1_stats_snapshot,
2855 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2856 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2857 .stats_get_strings = mv88e6095_stats_get_strings,
2858 .stats_get_stats = mv88e6095_stats_get_stats,
2859 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2860 .set_egress_port = mv88e6095_g1_set_egress_port,
2861 .watchdog_ops = &mv88e6097_watchdog_ops,
2862 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2863 .pot_clear = mv88e6xxx_g2_pot_clear,
2864 .reset = mv88e6352_g1_reset,
2865 .vtu_getnext = mv88e6352_g1_vtu_getnext,
2866 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2867 .serdes_power = mv88e6352_serdes_power,
2868 .gpio_ops = &mv88e6352_gpio_ops,
2871 static const struct mv88e6xxx_ops mv88e6185_ops = {
2872 /* MV88E6XXX_FAMILY_6185 */
2873 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2874 .phy_read = mv88e6185_phy_ppu_read,
2875 .phy_write = mv88e6185_phy_ppu_write,
2876 .port_set_link = mv88e6xxx_port_set_link,
2877 .port_set_duplex = mv88e6xxx_port_set_duplex,
2878 .port_set_speed = mv88e6185_port_set_speed,
2879 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
2880 .port_set_egress_floods = mv88e6185_port_set_egress_floods,
2881 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2882 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
2883 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2884 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2885 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
2886 .stats_get_strings = mv88e6095_stats_get_strings,
2887 .stats_get_stats = mv88e6095_stats_get_stats,
2888 .set_cpu_port = mv88e6095_g1_set_cpu_port,
2889 .set_egress_port = mv88e6095_g1_set_egress_port,
2890 .watchdog_ops = &mv88e6097_watchdog_ops,
2891 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2892 .ppu_enable = mv88e6185_g1_ppu_enable,
2893 .ppu_disable = mv88e6185_g1_ppu_disable,
2894 .reset = mv88e6185_g1_reset,
2895 .vtu_getnext = mv88e6185_g1_vtu_getnext,
2896 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2899 static const struct mv88e6xxx_ops mv88e6190_ops = {
2900 /* MV88E6XXX_FAMILY_6390 */
2901 .irl_init_all = mv88e6390_g2_irl_init_all,
2902 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2903 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2904 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2905 .phy_read = mv88e6xxx_g2_smi_phy_read,
2906 .phy_write = mv88e6xxx_g2_smi_phy_write,
2907 .port_set_link = mv88e6xxx_port_set_link,
2908 .port_set_duplex = mv88e6xxx_port_set_duplex,
2909 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2910 .port_set_speed = mv88e6390_port_set_speed,
2911 .port_tag_remap = mv88e6390_port_tag_remap,
2912 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2913 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2914 .port_set_ether_type = mv88e6351_port_set_ether_type,
2915 .port_pause_limit = mv88e6390_port_pause_limit,
2916 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2917 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2918 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2919 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2920 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2921 .stats_get_strings = mv88e6320_stats_get_strings,
2922 .stats_get_stats = mv88e6390_stats_get_stats,
2923 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2924 .set_egress_port = mv88e6390_g1_set_egress_port,
2925 .watchdog_ops = &mv88e6390_watchdog_ops,
2926 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2927 .pot_clear = mv88e6xxx_g2_pot_clear,
2928 .reset = mv88e6352_g1_reset,
2929 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2930 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2931 .serdes_power = mv88e6390_serdes_power,
2932 .gpio_ops = &mv88e6352_gpio_ops,
2935 static const struct mv88e6xxx_ops mv88e6190x_ops = {
2936 /* MV88E6XXX_FAMILY_6390 */
2937 .irl_init_all = mv88e6390_g2_irl_init_all,
2938 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2939 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2940 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2941 .phy_read = mv88e6xxx_g2_smi_phy_read,
2942 .phy_write = mv88e6xxx_g2_smi_phy_write,
2943 .port_set_link = mv88e6xxx_port_set_link,
2944 .port_set_duplex = mv88e6xxx_port_set_duplex,
2945 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2946 .port_set_speed = mv88e6390x_port_set_speed,
2947 .port_tag_remap = mv88e6390_port_tag_remap,
2948 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2949 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2950 .port_set_ether_type = mv88e6351_port_set_ether_type,
2951 .port_pause_limit = mv88e6390_port_pause_limit,
2952 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2953 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2954 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2955 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2956 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2957 .stats_get_strings = mv88e6320_stats_get_strings,
2958 .stats_get_stats = mv88e6390_stats_get_stats,
2959 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2960 .set_egress_port = mv88e6390_g1_set_egress_port,
2961 .watchdog_ops = &mv88e6390_watchdog_ops,
2962 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2963 .pot_clear = mv88e6xxx_g2_pot_clear,
2964 .reset = mv88e6352_g1_reset,
2965 .vtu_getnext = mv88e6390_g1_vtu_getnext,
2966 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
2967 .serdes_power = mv88e6390_serdes_power,
2968 .gpio_ops = &mv88e6352_gpio_ops,
2971 static const struct mv88e6xxx_ops mv88e6191_ops = {
2972 /* MV88E6XXX_FAMILY_6390 */
2973 .irl_init_all = mv88e6390_g2_irl_init_all,
2974 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
2975 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
2976 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2977 .phy_read = mv88e6xxx_g2_smi_phy_read,
2978 .phy_write = mv88e6xxx_g2_smi_phy_write,
2979 .port_set_link = mv88e6xxx_port_set_link,
2980 .port_set_duplex = mv88e6xxx_port_set_duplex,
2981 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
2982 .port_set_speed = mv88e6390_port_set_speed,
2983 .port_tag_remap = mv88e6390_port_tag_remap,
2984 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
2985 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
2986 .port_set_ether_type = mv88e6351_port_set_ether_type,
2987 .port_pause_limit = mv88e6390_port_pause_limit,
2988 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2989 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2990 .stats_snapshot = mv88e6390_g1_stats_snapshot,
2991 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
2992 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
2993 .stats_get_strings = mv88e6320_stats_get_strings,
2994 .stats_get_stats = mv88e6390_stats_get_stats,
2995 .set_cpu_port = mv88e6390_g1_set_cpu_port,
2996 .set_egress_port = mv88e6390_g1_set_egress_port,
2997 .watchdog_ops = &mv88e6390_watchdog_ops,
2998 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
2999 .pot_clear = mv88e6xxx_g2_pot_clear,
3000 .reset = mv88e6352_g1_reset,
3001 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3002 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3003 .serdes_power = mv88e6390_serdes_power,
3006 static const struct mv88e6xxx_ops mv88e6240_ops = {
3007 /* MV88E6XXX_FAMILY_6352 */
3008 .irl_init_all = mv88e6352_g2_irl_init_all,
3009 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3010 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3011 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3012 .phy_read = mv88e6xxx_g2_smi_phy_read,
3013 .phy_write = mv88e6xxx_g2_smi_phy_write,
3014 .port_set_link = mv88e6xxx_port_set_link,
3015 .port_set_duplex = mv88e6xxx_port_set_duplex,
3016 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3017 .port_set_speed = mv88e6352_port_set_speed,
3018 .port_tag_remap = mv88e6095_port_tag_remap,
3019 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3020 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3021 .port_set_ether_type = mv88e6351_port_set_ether_type,
3022 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3023 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3024 .port_pause_limit = mv88e6097_port_pause_limit,
3025 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3026 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3027 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3028 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3029 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3030 .stats_get_strings = mv88e6095_stats_get_strings,
3031 .stats_get_stats = mv88e6095_stats_get_stats,
3032 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3033 .set_egress_port = mv88e6095_g1_set_egress_port,
3034 .watchdog_ops = &mv88e6097_watchdog_ops,
3035 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3036 .pot_clear = mv88e6xxx_g2_pot_clear,
3037 .reset = mv88e6352_g1_reset,
3038 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3039 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3040 .serdes_power = mv88e6352_serdes_power,
3041 .gpio_ops = &mv88e6352_gpio_ops,
3042 .avb_ops = &mv88e6352_avb_ops,
3045 static const struct mv88e6xxx_ops mv88e6290_ops = {
3046 /* MV88E6XXX_FAMILY_6390 */
3047 .irl_init_all = mv88e6390_g2_irl_init_all,
3048 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3049 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3050 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3051 .phy_read = mv88e6xxx_g2_smi_phy_read,
3052 .phy_write = mv88e6xxx_g2_smi_phy_write,
3053 .port_set_link = mv88e6xxx_port_set_link,
3054 .port_set_duplex = mv88e6xxx_port_set_duplex,
3055 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3056 .port_set_speed = mv88e6390_port_set_speed,
3057 .port_tag_remap = mv88e6390_port_tag_remap,
3058 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3059 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3060 .port_set_ether_type = mv88e6351_port_set_ether_type,
3061 .port_pause_limit = mv88e6390_port_pause_limit,
3062 .port_set_cmode = mv88e6390x_port_set_cmode,
3063 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3064 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3065 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3066 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3067 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3068 .stats_get_strings = mv88e6320_stats_get_strings,
3069 .stats_get_stats = mv88e6390_stats_get_stats,
3070 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3071 .set_egress_port = mv88e6390_g1_set_egress_port,
3072 .watchdog_ops = &mv88e6390_watchdog_ops,
3073 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3074 .pot_clear = mv88e6xxx_g2_pot_clear,
3075 .reset = mv88e6352_g1_reset,
3076 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3077 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3078 .serdes_power = mv88e6390_serdes_power,
3079 .gpio_ops = &mv88e6352_gpio_ops,
3080 .avb_ops = &mv88e6390_avb_ops,
3083 static const struct mv88e6xxx_ops mv88e6320_ops = {
3084 /* MV88E6XXX_FAMILY_6320 */
3085 .irl_init_all = mv88e6352_g2_irl_init_all,
3086 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3087 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3088 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3089 .phy_read = mv88e6xxx_g2_smi_phy_read,
3090 .phy_write = mv88e6xxx_g2_smi_phy_write,
3091 .port_set_link = mv88e6xxx_port_set_link,
3092 .port_set_duplex = mv88e6xxx_port_set_duplex,
3093 .port_set_speed = mv88e6185_port_set_speed,
3094 .port_tag_remap = mv88e6095_port_tag_remap,
3095 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3096 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3097 .port_set_ether_type = mv88e6351_port_set_ether_type,
3098 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3099 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3100 .port_pause_limit = mv88e6097_port_pause_limit,
3101 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3102 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3103 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3104 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3105 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3106 .stats_get_strings = mv88e6320_stats_get_strings,
3107 .stats_get_stats = mv88e6320_stats_get_stats,
3108 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3109 .set_egress_port = mv88e6095_g1_set_egress_port,
3110 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3111 .pot_clear = mv88e6xxx_g2_pot_clear,
3112 .reset = mv88e6352_g1_reset,
3113 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3114 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3115 .gpio_ops = &mv88e6352_gpio_ops,
3116 .avb_ops = &mv88e6352_avb_ops,
3119 static const struct mv88e6xxx_ops mv88e6321_ops = {
3120 /* MV88E6XXX_FAMILY_6320 */
3121 .irl_init_all = mv88e6352_g2_irl_init_all,
3122 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3123 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3124 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3125 .phy_read = mv88e6xxx_g2_smi_phy_read,
3126 .phy_write = mv88e6xxx_g2_smi_phy_write,
3127 .port_set_link = mv88e6xxx_port_set_link,
3128 .port_set_duplex = mv88e6xxx_port_set_duplex,
3129 .port_set_speed = mv88e6185_port_set_speed,
3130 .port_tag_remap = mv88e6095_port_tag_remap,
3131 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3132 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3133 .port_set_ether_type = mv88e6351_port_set_ether_type,
3134 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3135 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3136 .port_pause_limit = mv88e6097_port_pause_limit,
3137 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3138 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3139 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3140 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3141 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3142 .stats_get_strings = mv88e6320_stats_get_strings,
3143 .stats_get_stats = mv88e6320_stats_get_stats,
3144 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3145 .set_egress_port = mv88e6095_g1_set_egress_port,
3146 .reset = mv88e6352_g1_reset,
3147 .vtu_getnext = mv88e6185_g1_vtu_getnext,
3148 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3149 .gpio_ops = &mv88e6352_gpio_ops,
3150 .avb_ops = &mv88e6352_avb_ops,
3153 static const struct mv88e6xxx_ops mv88e6341_ops = {
3154 /* MV88E6XXX_FAMILY_6341 */
3155 .irl_init_all = mv88e6352_g2_irl_init_all,
3156 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3157 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3158 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3159 .phy_read = mv88e6xxx_g2_smi_phy_read,
3160 .phy_write = mv88e6xxx_g2_smi_phy_write,
3161 .port_set_link = mv88e6xxx_port_set_link,
3162 .port_set_duplex = mv88e6xxx_port_set_duplex,
3163 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3164 .port_set_speed = mv88e6390_port_set_speed,
3165 .port_tag_remap = mv88e6095_port_tag_remap,
3166 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3167 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3168 .port_set_ether_type = mv88e6351_port_set_ether_type,
3169 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3170 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3171 .port_pause_limit = mv88e6097_port_pause_limit,
3172 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3173 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3174 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3175 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3176 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3177 .stats_get_strings = mv88e6320_stats_get_strings,
3178 .stats_get_stats = mv88e6390_stats_get_stats,
3179 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3180 .set_egress_port = mv88e6390_g1_set_egress_port,
3181 .watchdog_ops = &mv88e6390_watchdog_ops,
3182 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3183 .pot_clear = mv88e6xxx_g2_pot_clear,
3184 .reset = mv88e6352_g1_reset,
3185 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3186 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3187 .gpio_ops = &mv88e6352_gpio_ops,
3188 .avb_ops = &mv88e6390_avb_ops,
3191 static const struct mv88e6xxx_ops mv88e6350_ops = {
3192 /* MV88E6XXX_FAMILY_6351 */
3193 .irl_init_all = mv88e6352_g2_irl_init_all,
3194 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3195 .phy_read = mv88e6xxx_g2_smi_phy_read,
3196 .phy_write = mv88e6xxx_g2_smi_phy_write,
3197 .port_set_link = mv88e6xxx_port_set_link,
3198 .port_set_duplex = mv88e6xxx_port_set_duplex,
3199 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3200 .port_set_speed = mv88e6185_port_set_speed,
3201 .port_tag_remap = mv88e6095_port_tag_remap,
3202 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3203 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3204 .port_set_ether_type = mv88e6351_port_set_ether_type,
3205 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3206 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3207 .port_pause_limit = mv88e6097_port_pause_limit,
3208 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3209 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3210 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3211 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3212 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3213 .stats_get_strings = mv88e6095_stats_get_strings,
3214 .stats_get_stats = mv88e6095_stats_get_stats,
3215 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3216 .set_egress_port = mv88e6095_g1_set_egress_port,
3217 .watchdog_ops = &mv88e6097_watchdog_ops,
3218 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3219 .pot_clear = mv88e6xxx_g2_pot_clear,
3220 .reset = mv88e6352_g1_reset,
3221 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3222 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3225 static const struct mv88e6xxx_ops mv88e6351_ops = {
3226 /* MV88E6XXX_FAMILY_6351 */
3227 .irl_init_all = mv88e6352_g2_irl_init_all,
3228 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3229 .phy_read = mv88e6xxx_g2_smi_phy_read,
3230 .phy_write = mv88e6xxx_g2_smi_phy_write,
3231 .port_set_link = mv88e6xxx_port_set_link,
3232 .port_set_duplex = mv88e6xxx_port_set_duplex,
3233 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3234 .port_set_speed = mv88e6185_port_set_speed,
3235 .port_tag_remap = mv88e6095_port_tag_remap,
3236 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3237 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3238 .port_set_ether_type = mv88e6351_port_set_ether_type,
3239 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3240 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3241 .port_pause_limit = mv88e6097_port_pause_limit,
3242 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3243 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3244 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3245 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3246 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3247 .stats_get_strings = mv88e6095_stats_get_strings,
3248 .stats_get_stats = mv88e6095_stats_get_stats,
3249 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3250 .set_egress_port = mv88e6095_g1_set_egress_port,
3251 .watchdog_ops = &mv88e6097_watchdog_ops,
3252 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3253 .pot_clear = mv88e6xxx_g2_pot_clear,
3254 .reset = mv88e6352_g1_reset,
3255 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3256 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3257 .avb_ops = &mv88e6352_avb_ops,
3260 static const struct mv88e6xxx_ops mv88e6352_ops = {
3261 /* MV88E6XXX_FAMILY_6352 */
3262 .irl_init_all = mv88e6352_g2_irl_init_all,
3263 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3264 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3265 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3266 .phy_read = mv88e6xxx_g2_smi_phy_read,
3267 .phy_write = mv88e6xxx_g2_smi_phy_write,
3268 .port_set_link = mv88e6xxx_port_set_link,
3269 .port_set_duplex = mv88e6xxx_port_set_duplex,
3270 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3271 .port_set_speed = mv88e6352_port_set_speed,
3272 .port_tag_remap = mv88e6095_port_tag_remap,
3273 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3274 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3275 .port_set_ether_type = mv88e6351_port_set_ether_type,
3276 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3277 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3278 .port_pause_limit = mv88e6097_port_pause_limit,
3279 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3280 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3281 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3282 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3283 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3284 .stats_get_strings = mv88e6095_stats_get_strings,
3285 .stats_get_stats = mv88e6095_stats_get_stats,
3286 .set_cpu_port = mv88e6095_g1_set_cpu_port,
3287 .set_egress_port = mv88e6095_g1_set_egress_port,
3288 .watchdog_ops = &mv88e6097_watchdog_ops,
3289 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3290 .pot_clear = mv88e6xxx_g2_pot_clear,
3291 .reset = mv88e6352_g1_reset,
3292 .vtu_getnext = mv88e6352_g1_vtu_getnext,
3293 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3294 .serdes_power = mv88e6352_serdes_power,
3295 .gpio_ops = &mv88e6352_gpio_ops,
3296 .avb_ops = &mv88e6352_avb_ops,
3297 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
3298 .serdes_get_strings = mv88e6352_serdes_get_strings,
3299 .serdes_get_stats = mv88e6352_serdes_get_stats,
3302 static const struct mv88e6xxx_ops mv88e6390_ops = {
3303 /* MV88E6XXX_FAMILY_6390 */
3304 .irl_init_all = mv88e6390_g2_irl_init_all,
3305 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3306 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3307 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3308 .phy_read = mv88e6xxx_g2_smi_phy_read,
3309 .phy_write = mv88e6xxx_g2_smi_phy_write,
3310 .port_set_link = mv88e6xxx_port_set_link,
3311 .port_set_duplex = mv88e6xxx_port_set_duplex,
3312 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3313 .port_set_speed = mv88e6390_port_set_speed,
3314 .port_tag_remap = mv88e6390_port_tag_remap,
3315 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3316 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3317 .port_set_ether_type = mv88e6351_port_set_ether_type,
3318 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3319 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3320 .port_pause_limit = mv88e6390_port_pause_limit,
3321 .port_set_cmode = mv88e6390x_port_set_cmode,
3322 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3323 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3324 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3325 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3326 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3327 .stats_get_strings = mv88e6320_stats_get_strings,
3328 .stats_get_stats = mv88e6390_stats_get_stats,
3329 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3330 .set_egress_port = mv88e6390_g1_set_egress_port,
3331 .watchdog_ops = &mv88e6390_watchdog_ops,
3332 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3333 .pot_clear = mv88e6xxx_g2_pot_clear,
3334 .reset = mv88e6352_g1_reset,
3335 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3336 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3337 .serdes_power = mv88e6390_serdes_power,
3338 .gpio_ops = &mv88e6352_gpio_ops,
3339 .avb_ops = &mv88e6390_avb_ops,
3342 static const struct mv88e6xxx_ops mv88e6390x_ops = {
3343 /* MV88E6XXX_FAMILY_6390 */
3344 .irl_init_all = mv88e6390_g2_irl_init_all,
3345 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3346 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3347 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3348 .phy_read = mv88e6xxx_g2_smi_phy_read,
3349 .phy_write = mv88e6xxx_g2_smi_phy_write,
3350 .port_set_link = mv88e6xxx_port_set_link,
3351 .port_set_duplex = mv88e6xxx_port_set_duplex,
3352 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3353 .port_set_speed = mv88e6390x_port_set_speed,
3354 .port_tag_remap = mv88e6390_port_tag_remap,
3355 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3356 .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3357 .port_set_ether_type = mv88e6351_port_set_ether_type,
3358 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3359 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3360 .port_pause_limit = mv88e6390_port_pause_limit,
3361 .port_set_cmode = mv88e6390x_port_set_cmode,
3362 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3363 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3364 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3365 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3366 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3367 .stats_get_strings = mv88e6320_stats_get_strings,
3368 .stats_get_stats = mv88e6390_stats_get_stats,
3369 .set_cpu_port = mv88e6390_g1_set_cpu_port,
3370 .set_egress_port = mv88e6390_g1_set_egress_port,
3371 .watchdog_ops = &mv88e6390_watchdog_ops,
3372 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3373 .pot_clear = mv88e6xxx_g2_pot_clear,
3374 .reset = mv88e6352_g1_reset,
3375 .vtu_getnext = mv88e6390_g1_vtu_getnext,
3376 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3377 .serdes_power = mv88e6390_serdes_power,
3378 .gpio_ops = &mv88e6352_gpio_ops,
3379 .avb_ops = &mv88e6390_avb_ops,
3382 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3384 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
3385 .family = MV88E6XXX_FAMILY_6097,
3386 .name = "Marvell 88E6085",
3387 .num_databases = 4096,
3389 .num_internal_phys = 5,
3391 .port_base_addr = 0x10,
3392 .global1_addr = 0x1b,
3393 .global2_addr = 0x1c,
3394 .age_time_coeff = 15000,
3397 .atu_move_port_mask = 0xf,
3400 .tag_protocol = DSA_TAG_PROTO_DSA,
3401 .ops = &mv88e6085_ops,
3405 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
3406 .family = MV88E6XXX_FAMILY_6095,
3407 .name = "Marvell 88E6095/88E6095F",
3408 .num_databases = 256,
3410 .num_internal_phys = 0,
3412 .port_base_addr = 0x10,
3413 .global1_addr = 0x1b,
3414 .global2_addr = 0x1c,
3415 .age_time_coeff = 15000,
3417 .atu_move_port_mask = 0xf,
3419 .tag_protocol = DSA_TAG_PROTO_DSA,
3420 .ops = &mv88e6095_ops,
3424 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
3425 .family = MV88E6XXX_FAMILY_6097,
3426 .name = "Marvell 88E6097/88E6097F",
3427 .num_databases = 4096,
3429 .num_internal_phys = 8,
3431 .port_base_addr = 0x10,
3432 .global1_addr = 0x1b,
3433 .global2_addr = 0x1c,
3434 .age_time_coeff = 15000,
3437 .atu_move_port_mask = 0xf,
3440 .tag_protocol = DSA_TAG_PROTO_EDSA,
3441 .ops = &mv88e6097_ops,
3445 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
3446 .family = MV88E6XXX_FAMILY_6165,
3447 .name = "Marvell 88E6123",
3448 .num_databases = 4096,
3450 .num_internal_phys = 5,
3452 .port_base_addr = 0x10,
3453 .global1_addr = 0x1b,
3454 .global2_addr = 0x1c,
3455 .age_time_coeff = 15000,
3458 .atu_move_port_mask = 0xf,
3461 .tag_protocol = DSA_TAG_PROTO_EDSA,
3462 .ops = &mv88e6123_ops,
3466 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
3467 .family = MV88E6XXX_FAMILY_6185,
3468 .name = "Marvell 88E6131",
3469 .num_databases = 256,
3471 .num_internal_phys = 0,
3473 .port_base_addr = 0x10,
3474 .global1_addr = 0x1b,
3475 .global2_addr = 0x1c,
3476 .age_time_coeff = 15000,
3478 .atu_move_port_mask = 0xf,
3480 .tag_protocol = DSA_TAG_PROTO_DSA,
3481 .ops = &mv88e6131_ops,
3485 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
3486 .family = MV88E6XXX_FAMILY_6341,
3487 .name = "Marvell 88E6141",
3488 .num_databases = 4096,
3490 .num_internal_phys = 5,
3493 .port_base_addr = 0x10,
3494 .global1_addr = 0x1b,
3495 .global2_addr = 0x1c,
3496 .age_time_coeff = 3750,
3497 .atu_move_port_mask = 0x1f,
3502 .tag_protocol = DSA_TAG_PROTO_EDSA,
3503 .ops = &mv88e6141_ops,
3507 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
3508 .family = MV88E6XXX_FAMILY_6165,
3509 .name = "Marvell 88E6161",
3510 .num_databases = 4096,
3512 .num_internal_phys = 5,
3514 .port_base_addr = 0x10,
3515 .global1_addr = 0x1b,
3516 .global2_addr = 0x1c,
3517 .age_time_coeff = 15000,
3520 .atu_move_port_mask = 0xf,
3523 .tag_protocol = DSA_TAG_PROTO_EDSA,
3524 .ops = &mv88e6161_ops,
3528 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
3529 .family = MV88E6XXX_FAMILY_6165,
3530 .name = "Marvell 88E6165",
3531 .num_databases = 4096,
3533 .num_internal_phys = 0,
3535 .port_base_addr = 0x10,
3536 .global1_addr = 0x1b,
3537 .global2_addr = 0x1c,
3538 .age_time_coeff = 15000,
3541 .atu_move_port_mask = 0xf,
3544 .tag_protocol = DSA_TAG_PROTO_DSA,
3545 .ops = &mv88e6165_ops,
3549 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
3550 .family = MV88E6XXX_FAMILY_6351,
3551 .name = "Marvell 88E6171",
3552 .num_databases = 4096,
3554 .num_internal_phys = 5,
3556 .port_base_addr = 0x10,
3557 .global1_addr = 0x1b,
3558 .global2_addr = 0x1c,
3559 .age_time_coeff = 15000,
3562 .atu_move_port_mask = 0xf,
3565 .tag_protocol = DSA_TAG_PROTO_EDSA,
3566 .ops = &mv88e6171_ops,
3570 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
3571 .family = MV88E6XXX_FAMILY_6352,
3572 .name = "Marvell 88E6172",
3573 .num_databases = 4096,
3575 .num_internal_phys = 5,
3578 .port_base_addr = 0x10,
3579 .global1_addr = 0x1b,
3580 .global2_addr = 0x1c,
3581 .age_time_coeff = 15000,
3584 .atu_move_port_mask = 0xf,
3587 .tag_protocol = DSA_TAG_PROTO_EDSA,
3588 .ops = &mv88e6172_ops,
3592 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
3593 .family = MV88E6XXX_FAMILY_6351,
3594 .name = "Marvell 88E6175",
3595 .num_databases = 4096,
3597 .num_internal_phys = 5,
3599 .port_base_addr = 0x10,
3600 .global1_addr = 0x1b,
3601 .global2_addr = 0x1c,
3602 .age_time_coeff = 15000,
3605 .atu_move_port_mask = 0xf,
3608 .tag_protocol = DSA_TAG_PROTO_EDSA,
3609 .ops = &mv88e6175_ops,
3613 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
3614 .family = MV88E6XXX_FAMILY_6352,
3615 .name = "Marvell 88E6176",
3616 .num_databases = 4096,
3618 .num_internal_phys = 5,
3621 .port_base_addr = 0x10,
3622 .global1_addr = 0x1b,
3623 .global2_addr = 0x1c,
3624 .age_time_coeff = 15000,
3627 .atu_move_port_mask = 0xf,
3630 .tag_protocol = DSA_TAG_PROTO_EDSA,
3631 .ops = &mv88e6176_ops,
3635 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
3636 .family = MV88E6XXX_FAMILY_6185,
3637 .name = "Marvell 88E6185",
3638 .num_databases = 256,
3640 .num_internal_phys = 0,
3642 .port_base_addr = 0x10,
3643 .global1_addr = 0x1b,
3644 .global2_addr = 0x1c,
3645 .age_time_coeff = 15000,
3647 .atu_move_port_mask = 0xf,
3649 .tag_protocol = DSA_TAG_PROTO_EDSA,
3650 .ops = &mv88e6185_ops,
3654 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
3655 .family = MV88E6XXX_FAMILY_6390,
3656 .name = "Marvell 88E6190",
3657 .num_databases = 4096,
3658 .num_ports = 11, /* 10 + Z80 */
3659 .num_internal_phys = 11,
3662 .port_base_addr = 0x0,
3663 .global1_addr = 0x1b,
3664 .global2_addr = 0x1c,
3665 .tag_protocol = DSA_TAG_PROTO_DSA,
3666 .age_time_coeff = 3750,
3671 .atu_move_port_mask = 0x1f,
3672 .ops = &mv88e6190_ops,
3676 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
3677 .family = MV88E6XXX_FAMILY_6390,
3678 .name = "Marvell 88E6190X",
3679 .num_databases = 4096,
3680 .num_ports = 11, /* 10 + Z80 */
3681 .num_internal_phys = 11,
3684 .port_base_addr = 0x0,
3685 .global1_addr = 0x1b,
3686 .global2_addr = 0x1c,
3687 .age_time_coeff = 3750,
3690 .atu_move_port_mask = 0x1f,
3693 .tag_protocol = DSA_TAG_PROTO_DSA,
3694 .ops = &mv88e6190x_ops,
3698 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
3699 .family = MV88E6XXX_FAMILY_6390,
3700 .name = "Marvell 88E6191",
3701 .num_databases = 4096,
3702 .num_ports = 11, /* 10 + Z80 */
3703 .num_internal_phys = 11,
3705 .port_base_addr = 0x0,
3706 .global1_addr = 0x1b,
3707 .global2_addr = 0x1c,
3708 .age_time_coeff = 3750,
3711 .atu_move_port_mask = 0x1f,
3714 .tag_protocol = DSA_TAG_PROTO_DSA,
3715 .ptp_support = true,
3716 .ops = &mv88e6191_ops,
3720 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
3721 .family = MV88E6XXX_FAMILY_6352,
3722 .name = "Marvell 88E6240",
3723 .num_databases = 4096,
3725 .num_internal_phys = 5,
3728 .port_base_addr = 0x10,
3729 .global1_addr = 0x1b,
3730 .global2_addr = 0x1c,
3731 .age_time_coeff = 15000,
3734 .atu_move_port_mask = 0xf,
3737 .tag_protocol = DSA_TAG_PROTO_EDSA,
3738 .ptp_support = true,
3739 .ops = &mv88e6240_ops,
3743 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
3744 .family = MV88E6XXX_FAMILY_6390,
3745 .name = "Marvell 88E6290",
3746 .num_databases = 4096,
3747 .num_ports = 11, /* 10 + Z80 */
3748 .num_internal_phys = 11,
3751 .port_base_addr = 0x0,
3752 .global1_addr = 0x1b,
3753 .global2_addr = 0x1c,
3754 .age_time_coeff = 3750,
3757 .atu_move_port_mask = 0x1f,
3760 .tag_protocol = DSA_TAG_PROTO_DSA,
3761 .ptp_support = true,
3762 .ops = &mv88e6290_ops,
3766 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
3767 .family = MV88E6XXX_FAMILY_6320,
3768 .name = "Marvell 88E6320",
3769 .num_databases = 4096,
3771 .num_internal_phys = 5,
3774 .port_base_addr = 0x10,
3775 .global1_addr = 0x1b,
3776 .global2_addr = 0x1c,
3777 .age_time_coeff = 15000,
3780 .atu_move_port_mask = 0xf,
3783 .tag_protocol = DSA_TAG_PROTO_EDSA,
3784 .ptp_support = true,
3785 .ops = &mv88e6320_ops,
3789 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
3790 .family = MV88E6XXX_FAMILY_6320,
3791 .name = "Marvell 88E6321",
3792 .num_databases = 4096,
3794 .num_internal_phys = 5,
3797 .port_base_addr = 0x10,
3798 .global1_addr = 0x1b,
3799 .global2_addr = 0x1c,
3800 .age_time_coeff = 15000,
3803 .atu_move_port_mask = 0xf,
3805 .tag_protocol = DSA_TAG_PROTO_EDSA,
3806 .ptp_support = true,
3807 .ops = &mv88e6321_ops,
3811 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3812 .family = MV88E6XXX_FAMILY_6341,
3813 .name = "Marvell 88E6341",
3814 .num_databases = 4096,
3815 .num_internal_phys = 5,
3819 .port_base_addr = 0x10,
3820 .global1_addr = 0x1b,
3821 .global2_addr = 0x1c,
3822 .age_time_coeff = 3750,
3823 .atu_move_port_mask = 0x1f,
3828 .tag_protocol = DSA_TAG_PROTO_EDSA,
3829 .ptp_support = true,
3830 .ops = &mv88e6341_ops,
3834 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
3835 .family = MV88E6XXX_FAMILY_6351,
3836 .name = "Marvell 88E6350",
3837 .num_databases = 4096,
3839 .num_internal_phys = 5,
3841 .port_base_addr = 0x10,
3842 .global1_addr = 0x1b,
3843 .global2_addr = 0x1c,
3844 .age_time_coeff = 15000,
3847 .atu_move_port_mask = 0xf,
3850 .tag_protocol = DSA_TAG_PROTO_EDSA,
3851 .ops = &mv88e6350_ops,
3855 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
3856 .family = MV88E6XXX_FAMILY_6351,
3857 .name = "Marvell 88E6351",
3858 .num_databases = 4096,
3860 .num_internal_phys = 5,
3862 .port_base_addr = 0x10,
3863 .global1_addr = 0x1b,
3864 .global2_addr = 0x1c,
3865 .age_time_coeff = 15000,
3868 .atu_move_port_mask = 0xf,
3871 .tag_protocol = DSA_TAG_PROTO_EDSA,
3872 .ops = &mv88e6351_ops,
3876 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
3877 .family = MV88E6XXX_FAMILY_6352,
3878 .name = "Marvell 88E6352",
3879 .num_databases = 4096,
3881 .num_internal_phys = 5,
3884 .port_base_addr = 0x10,
3885 .global1_addr = 0x1b,
3886 .global2_addr = 0x1c,
3887 .age_time_coeff = 15000,
3890 .atu_move_port_mask = 0xf,
3893 .tag_protocol = DSA_TAG_PROTO_EDSA,
3894 .ptp_support = true,
3895 .ops = &mv88e6352_ops,
3898 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3899 .family = MV88E6XXX_FAMILY_6390,
3900 .name = "Marvell 88E6390",
3901 .num_databases = 4096,
3902 .num_ports = 11, /* 10 + Z80 */
3903 .num_internal_phys = 11,
3906 .port_base_addr = 0x0,
3907 .global1_addr = 0x1b,
3908 .global2_addr = 0x1c,
3909 .age_time_coeff = 3750,
3912 .atu_move_port_mask = 0x1f,
3915 .tag_protocol = DSA_TAG_PROTO_DSA,
3916 .ptp_support = true,
3917 .ops = &mv88e6390_ops,
3920 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
3921 .family = MV88E6XXX_FAMILY_6390,
3922 .name = "Marvell 88E6390X",
3923 .num_databases = 4096,
3924 .num_ports = 11, /* 10 + Z80 */
3925 .num_internal_phys = 11,
3928 .port_base_addr = 0x0,
3929 .global1_addr = 0x1b,
3930 .global2_addr = 0x1c,
3931 .age_time_coeff = 3750,
3934 .atu_move_port_mask = 0x1f,
3937 .tag_protocol = DSA_TAG_PROTO_DSA,
3938 .ptp_support = true,
3939 .ops = &mv88e6390x_ops,
3943 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3947 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3948 if (mv88e6xxx_table[i].prod_num == prod_num)
3949 return &mv88e6xxx_table[i];
3954 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3956 const struct mv88e6xxx_info *info;
3957 unsigned int prod_num, rev;
3961 mutex_lock(&chip->reg_lock);
3962 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
3963 mutex_unlock(&chip->reg_lock);
3967 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
3968 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
3970 info = mv88e6xxx_lookup_info(prod_num);
3974 /* Update the compatible info with the probed one */
3977 err = mv88e6xxx_g2_require(chip);
3981 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3982 chip->info->prod_num, chip->info->name, rev);
3987 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3989 struct mv88e6xxx_chip *chip;
3991 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3997 mutex_init(&chip->reg_lock);
3998 INIT_LIST_HEAD(&chip->mdios);
4003 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4004 struct mii_bus *bus, int sw_addr)
4007 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
4008 else if (chip->info->multi_chip)
4009 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
4014 chip->sw_addr = sw_addr;
4019 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
4022 struct mv88e6xxx_chip *chip = ds->priv;
4024 return chip->info->tag_protocol;
4027 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
4028 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
4029 struct device *host_dev, int sw_addr,
4032 struct mv88e6xxx_chip *chip;
4033 struct mii_bus *bus;
4036 bus = dsa_host_dev_to_mii_bus(host_dev);
4040 chip = mv88e6xxx_alloc_chip(dsa_dev);
4044 /* Legacy SMI probing will only support chips similar to 88E6085 */
4045 chip->info = &mv88e6xxx_table[MV88E6085];
4047 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4051 err = mv88e6xxx_detect(chip);
4055 mutex_lock(&chip->reg_lock);
4056 err = mv88e6xxx_switch_reset(chip);
4057 mutex_unlock(&chip->reg_lock);
4061 mv88e6xxx_phy_init(chip);
4063 err = mv88e6xxx_mdios_register(chip, NULL);
4069 return chip->info->name;
4071 devm_kfree(dsa_dev, chip);
4077 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4078 const struct switchdev_obj_port_mdb *mdb)
4080 /* We don't need any dynamic resource from the kernel (yet),
4081 * so skip the prepare phase.
4087 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4088 const struct switchdev_obj_port_mdb *mdb)
4090 struct mv88e6xxx_chip *chip = ds->priv;
4092 mutex_lock(&chip->reg_lock);
4093 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4094 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
4095 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
4097 mutex_unlock(&chip->reg_lock);
4100 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4101 const struct switchdev_obj_port_mdb *mdb)
4103 struct mv88e6xxx_chip *chip = ds->priv;
4106 mutex_lock(&chip->reg_lock);
4107 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4108 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
4109 mutex_unlock(&chip->reg_lock);
4114 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
4115 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
4116 .probe = mv88e6xxx_drv_probe,
4118 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
4119 .setup = mv88e6xxx_setup,
4120 .adjust_link = mv88e6xxx_adjust_link,
4121 .get_strings = mv88e6xxx_get_strings,
4122 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
4123 .get_sset_count = mv88e6xxx_get_sset_count,
4124 .port_enable = mv88e6xxx_port_enable,
4125 .port_disable = mv88e6xxx_port_disable,
4126 .get_mac_eee = mv88e6xxx_get_mac_eee,
4127 .set_mac_eee = mv88e6xxx_set_mac_eee,
4128 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
4129 .get_eeprom = mv88e6xxx_get_eeprom,
4130 .set_eeprom = mv88e6xxx_set_eeprom,
4131 .get_regs_len = mv88e6xxx_get_regs_len,
4132 .get_regs = mv88e6xxx_get_regs,
4133 .set_ageing_time = mv88e6xxx_set_ageing_time,
4134 .port_bridge_join = mv88e6xxx_port_bridge_join,
4135 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
4136 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
4137 .port_fast_age = mv88e6xxx_port_fast_age,
4138 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
4139 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
4140 .port_vlan_add = mv88e6xxx_port_vlan_add,
4141 .port_vlan_del = mv88e6xxx_port_vlan_del,
4142 .port_fdb_add = mv88e6xxx_port_fdb_add,
4143 .port_fdb_del = mv88e6xxx_port_fdb_del,
4144 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
4145 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
4146 .port_mdb_add = mv88e6xxx_port_mdb_add,
4147 .port_mdb_del = mv88e6xxx_port_mdb_del,
4148 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
4149 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
4150 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
4151 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
4152 .port_txtstamp = mv88e6xxx_port_txtstamp,
4153 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
4154 .get_ts_info = mv88e6xxx_get_ts_info,
4157 static struct dsa_switch_driver mv88e6xxx_switch_drv = {
4158 .ops = &mv88e6xxx_switch_ops,
4161 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
4163 struct device *dev = chip->dev;
4164 struct dsa_switch *ds;
4166 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
4171 ds->ops = &mv88e6xxx_switch_ops;
4172 ds->ageing_time_min = chip->info->age_time_coeff;
4173 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
4175 dev_set_drvdata(dev, ds);
4177 return dsa_register_switch(ds);
4180 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4182 dsa_unregister_switch(chip->ds);
4185 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4187 struct device *dev = &mdiodev->dev;
4188 struct device_node *np = dev->of_node;
4189 const struct mv88e6xxx_info *compat_info;
4190 struct mv88e6xxx_chip *chip;
4194 compat_info = of_device_get_match_data(dev);
4198 chip = mv88e6xxx_alloc_chip(dev);
4202 chip->info = compat_info;
4204 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4208 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4209 if (IS_ERR(chip->reset))
4210 return PTR_ERR(chip->reset);
4212 err = mv88e6xxx_detect(chip);
4216 mv88e6xxx_phy_init(chip);
4218 if (chip->info->ops->get_eeprom &&
4219 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
4220 chip->eeprom_len = eeprom_len;
4222 mutex_lock(&chip->reg_lock);
4223 err = mv88e6xxx_switch_reset(chip);
4224 mutex_unlock(&chip->reg_lock);
4228 chip->irq = of_irq_get(np, 0);
4229 if (chip->irq == -EPROBE_DEFER) {
4234 /* Has to be performed before the MDIO bus is created, because
4235 * the PHYs will link their interrupts to these interrupt
4238 mutex_lock(&chip->reg_lock);
4240 err = mv88e6xxx_g1_irq_setup(chip);
4242 err = mv88e6xxx_irq_poll_setup(chip);
4243 mutex_unlock(&chip->reg_lock);
4248 if (chip->info->g2_irqs > 0) {
4249 err = mv88e6xxx_g2_irq_setup(chip);
4254 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
4258 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
4260 goto out_g1_atu_prob_irq;
4262 err = mv88e6xxx_mdios_register(chip, np);
4264 goto out_g1_vtu_prob_irq;
4266 err = mv88e6xxx_register_switch(chip);
4273 mv88e6xxx_mdios_unregister(chip);
4274 out_g1_vtu_prob_irq:
4275 mv88e6xxx_g1_vtu_prob_irq_free(chip);
4276 out_g1_atu_prob_irq:
4277 mv88e6xxx_g1_atu_prob_irq_free(chip);
4279 if (chip->info->g2_irqs > 0)
4280 mv88e6xxx_g2_irq_free(chip);
4282 mutex_lock(&chip->reg_lock);
4284 mv88e6xxx_g1_irq_free(chip);
4286 mv88e6xxx_irq_poll_free(chip);
4287 mutex_unlock(&chip->reg_lock);
4292 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4294 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4295 struct mv88e6xxx_chip *chip = ds->priv;
4297 if (chip->info->ptp_support) {
4298 mv88e6xxx_hwtstamp_free(chip);
4299 mv88e6xxx_ptp_free(chip);
4302 mv88e6xxx_phy_destroy(chip);
4303 mv88e6xxx_unregister_switch(chip);
4304 mv88e6xxx_mdios_unregister(chip);
4306 mv88e6xxx_g1_vtu_prob_irq_free(chip);
4307 mv88e6xxx_g1_atu_prob_irq_free(chip);
4309 if (chip->info->g2_irqs > 0)
4310 mv88e6xxx_g2_irq_free(chip);
4312 mutex_lock(&chip->reg_lock);
4314 mv88e6xxx_g1_irq_free(chip);
4316 mv88e6xxx_irq_poll_free(chip);
4317 mutex_unlock(&chip->reg_lock);
4320 static const struct of_device_id mv88e6xxx_of_match[] = {
4322 .compatible = "marvell,mv88e6085",
4323 .data = &mv88e6xxx_table[MV88E6085],
4326 .compatible = "marvell,mv88e6190",
4327 .data = &mv88e6xxx_table[MV88E6190],
4332 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4334 static struct mdio_driver mv88e6xxx_driver = {
4335 .probe = mv88e6xxx_probe,
4336 .remove = mv88e6xxx_remove,
4338 .name = "mv88e6085",
4339 .of_match_table = mv88e6xxx_of_match,
4343 static int __init mv88e6xxx_init(void)
4345 register_switch_driver(&mv88e6xxx_switch_drv);
4346 return mdio_driver_register(&mv88e6xxx_driver);
4348 module_init(mv88e6xxx_init);
4350 static void __exit mv88e6xxx_cleanup(void)
4352 mdio_driver_unregister(&mv88e6xxx_driver);
4353 unregister_switch_driver(&mv88e6xxx_switch_drv);
4355 module_exit(mv88e6xxx_cleanup);
4357 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4358 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4359 MODULE_LICENSE("GPL");