drivers/net/dsa/mv88e6xxx/chip.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Marvell 88e6xxx Ethernet switch single-chip support
   4  *
   5  * Copyright (c) 2008 Marvell Semiconductor
   6  *
   7  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
   8  *
   9  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
  10  *      Vivien Didelot <vivien.didelot@savoirfairelinux.com>
  11  */
  12
  13 #include <linux/bitfield.h>
  14 #include <linux/delay.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/ethtool.h>
  17 #include <linux/if_bridge.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/irq.h>
  20 #include <linux/irqdomain.h>
  21 #include <linux/jiffies.h>
  22 #include <linux/list.h>
  23 #include <linux/mdio.h>
  24 #include <linux/module.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_irq.h>
  27 #include <linux/of_mdio.h>
  28 #include <linux/platform_data/mv88e6xxx.h>
  29 #include <linux/netdevice.h>
  30 #include <linux/gpio/consumer.h>
  31 #include <linux/phylink.h>
  32 #include <net/dsa.h>
  33
  34 #include "chip.h"
  35 #include "global1.h"
  36 #include "global2.h"
  37 #include "hwtstamp.h"
  38 #include "phy.h"
  39 #include "port.h"
  40 #include "ptp.h"
  41 #include "serdes.h"
  42 #include "smi.h"
  43
  44 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
  45 {
  46         if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
  47                 dev_err(chip->dev, "Switch registers lock not held!\n");
  48                 dump_stack();
  49         }
  50 }
  51
  52 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
  53 {
  54         int err;
  55
  56         assert_reg_lock(chip);
  57
  58         err = mv88e6xxx_smi_read(chip, addr, reg, val);
  59         if (err)
  60                 return err;
  61
  62         dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
  63                 addr, reg, *val);
  64
  65         return 0;
  66 }
  67
  68 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
  69 {
  70         int err;
  71
  72         assert_reg_lock(chip);
  73
  74         err = mv88e6xxx_smi_write(chip, addr, reg, val);
  75         if (err)
  76                 return err;
  77
  78         dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
  79                 addr, reg, val);
  80
  81         return 0;
  82 }
  83
  84 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
  85                         u16 mask, u16 val)
  86 {
  87         u16 data;
  88         int err;
  89         int i;
  90
  91         /* There's no bus specific operation to wait for a mask */
  92         for (i = 0; i < 16; i++) {
  93                 err = mv88e6xxx_read(chip, addr, reg, &data);
  94                 if (err)
  95                         return err;
  96
  97                 if ((data & mask) == val)
  98                         return 0;
  99
 100                 usleep_range(1000, 2000);
 101         }
 102
 103         dev_err(chip->dev, "Timeout while waiting for switch\n");
 104         return -ETIMEDOUT;
 105 }
 106
 107 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
 108                        int bit, int val)
 109 {
 110         return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
 111                                    val ? BIT(bit) : 0x0000);
 112 }
 113
 114 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
 115 {
 116         struct mv88e6xxx_mdio_bus *mdio_bus;
 117
 118         mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
 119                                     list);
 120         if (!mdio_bus)
 121                 return NULL;
 122
 123         return mdio_bus->bus;
 124 }
 125
 126 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
 127 {
 128         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 129         unsigned int n = d->hwirq;
 130
 131         chip->g1_irq.masked |= (1 << n);
 132 }
 133
 134 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
 135 {
 136         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 137         unsigned int n = d->hwirq;
 138
 139         chip->g1_irq.masked &= ~(1 << n);
 140 }
 141
 142 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
 143 {
 144         unsigned int nhandled = 0;
 145         unsigned int sub_irq;
 146         unsigned int n;
 147         u16 reg;
 148         u16 ctl1;
 149         int err;
 150
 151         mv88e6xxx_reg_lock(chip);
 152         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 153         mv88e6xxx_reg_unlock(chip);
 154
 155         if (err)
 156                 goto out;
 157
 158         do {
 159                 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
 160                         if (reg & (1 << n)) {
 161                                 sub_irq = irq_find_mapping(chip->g1_irq.domain,
 162                                                            n);
 163                                 handle_nested_irq(sub_irq);
 164                                 ++nhandled;
 165                         }
 166                 }
 167
 168                 mv88e6xxx_reg_lock(chip);
 169                 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
 170                 if (err)
 171                         goto unlock;
 172                 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 173 unlock:
 174                 mv88e6xxx_reg_unlock(chip);
 175                 if (err)
 176                         goto out;
 177                 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
 178         } while (reg & ctl1);
 179
 180 out:
 181         return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
 182 }
 183
 184 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
 185 {
 186         struct mv88e6xxx_chip *chip = dev_id;
 187
 188         return mv88e6xxx_g1_irq_thread_work(chip);
 189 }
 190
 191 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
 192 {
 193         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 194
 195         mv88e6xxx_reg_lock(chip);
 196 }
 197
 198 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
 199 {
 200         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 201         u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
 202         u16 reg;
 203         int err;
 204
 205         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
 206         if (err)
 207                 goto out;
 208
 209         reg &= ~mask;
 210         reg |= (~chip->g1_irq.masked & mask);
 211
 212         err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
 213         if (err)
 214                 goto out;
 215
 216 out:
 217         mv88e6xxx_reg_unlock(chip);
 218 }
 219
 220 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
 221         .name                   = "mv88e6xxx-g1",
 222         .irq_mask               = mv88e6xxx_g1_irq_mask,
 223         .irq_unmask             = mv88e6xxx_g1_irq_unmask,
 224         .irq_bus_lock           = mv88e6xxx_g1_irq_bus_lock,
 225         .irq_bus_sync_unlock    = mv88e6xxx_g1_irq_bus_sync_unlock,
 226 };
 227
 228 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
 229                                        unsigned int irq,
 230                                        irq_hw_number_t hwirq)
 231 {
 232         struct mv88e6xxx_chip *chip = d->host_data;
 233
 234         irq_set_chip_data(irq, d->host_data);
 235         irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
 236         irq_set_noprobe(irq);
 237
 238         return 0;
 239 }
 240
 241 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
 242         .map    = mv88e6xxx_g1_irq_domain_map,
 243         .xlate  = irq_domain_xlate_twocell,
 244 };
 245
 246 /* To be called with reg_lock held */
 247 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
 248 {
 249         int irq, virq;
 250         u16 mask;
 251
 252         mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
 253         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 254         mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 255
 256         for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
 257                 virq = irq_find_mapping(chip->g1_irq.domain, irq);
 258                 irq_dispose_mapping(virq);
 259         }
 260
 261         irq_domain_remove(chip->g1_irq.domain);
 262 }
 263
 264 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
 265 {
 266         /*
 267          * free_irq must be called without reg_lock taken because the irq
 268          * handler takes this lock, too.
 269          */
 270         free_irq(chip->irq, chip);
 271
 272         mv88e6xxx_reg_lock(chip);
 273         mv88e6xxx_g1_irq_free_common(chip);
 274         mv88e6xxx_reg_unlock(chip);
 275 }
 276
 277 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
 278 {
 279         int err, irq, virq;
 280         u16 reg, mask;
 281
 282         chip->g1_irq.nirqs = chip->info->g1_irqs;
 283         chip->g1_irq.domain = irq_domain_add_simple(
 284                 NULL, chip->g1_irq.nirqs, 0,
 285                 &mv88e6xxx_g1_irq_domain_ops, chip);
 286         if (!chip->g1_irq.domain)
 287                 return -ENOMEM;
 288
 289         for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
 290                 irq_create_mapping(chip->g1_irq.domain, irq);
 291
 292         chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
 293         chip->g1_irq.masked = ~0;
 294
 295         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
 296         if (err)
 297                 goto out_mapping;
 298
 299         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 300
 301         err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 302         if (err)
 303                 goto out_disable;
 304
 305         /* Reading the interrupt status clears (most of) them */
 306         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 307         if (err)
 308                 goto out_disable;
 309
 310         return 0;
 311
 312 out_disable:
 313         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 314         mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 315
 316 out_mapping:
 317         for (irq = 0; irq < 16; irq++) {
 318                 virq = irq_find_mapping(chip->g1_irq.domain, irq);
 319                 irq_dispose_mapping(virq);
 320         }
 321
 322         irq_domain_remove(chip->g1_irq.domain);
 323
 324         return err;
 325 }
 326
 327 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
 328 {
 329         static struct lock_class_key lock_key;
 330         static struct lock_class_key request_key;
 331         int err;
 332
 333         err = mv88e6xxx_g1_irq_setup_common(chip);
 334         if (err)
 335                 return err;
 336
 337         /* These lock classes tells lockdep that global 1 irqs are in
 338          * a different category than their parent GPIO, so it won't
 339          * report false recursion.
 340          */
 341         irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
 342
 343         snprintf(chip->irq_name, sizeof(chip->irq_name),
 344                  "mv88e6xxx-%s", dev_name(chip->dev));
 345
 346         mv88e6xxx_reg_unlock(chip);
 347         err = request_threaded_irq(chip->irq, NULL,
 348                                    mv88e6xxx_g1_irq_thread_fn,
 349                                    IRQF_ONESHOT | IRQF_SHARED,
 350                                    chip->irq_name, chip);
 351         mv88e6xxx_reg_lock(chip);
 352         if (err)
 353                 mv88e6xxx_g1_irq_free_common(chip);
 354
 355         return err;
 356 }
 357
 358 static void mv88e6xxx_irq_poll(struct kthread_work *work)
 359 {
 360         struct mv88e6xxx_chip *chip = container_of(work,
 361                                                    struct mv88e6xxx_chip,
 362                                                    irq_poll_work.work);
 363         mv88e6xxx_g1_irq_thread_work(chip);
 364
 365         kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
 366                                    msecs_to_jiffies(100));
 367 }
 368
 369 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
 370 {
 371         int err;
 372
 373         err = mv88e6xxx_g1_irq_setup_common(chip);
 374         if (err)
 375                 return err;
 376
 377         kthread_init_delayed_work(&chip->irq_poll_work,
 378                                   mv88e6xxx_irq_poll);
 379
 380         chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
 381         if (IS_ERR(chip->kworker))
 382                 return PTR_ERR(chip->kworker);
 383
 384         kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
 385                                    msecs_to_jiffies(100));
 386
 387         return 0;
 388 }
 389
 390 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
 391 {
 392         kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
 393         kthread_destroy_worker(chip->kworker);
 394
 395         mv88e6xxx_reg_lock(chip);
 396         mv88e6xxx_g1_irq_free_common(chip);
 397         mv88e6xxx_reg_unlock(chip);
 398 }
 399
 400 int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link,
 401                              int speed, int duplex, int pause,
 402                              phy_interface_t mode)
 403 {
 404         struct phylink_link_state state;
 405         int err;
 406
 407         if (!chip->info->ops->port_set_link)
 408                 return 0;
 409
 410         if (!chip->info->ops->port_link_state)
 411                 return 0;
 412
 413         err = chip->info->ops->port_link_state(chip, port, &state);
 414         if (err)
 415                 return err;
 416
 417         /* Has anything actually changed? We don't expect the
 418          * interface mode to change without one of the other
 419          * parameters also changing
 420          */
 421         if (state.link == link &&
 422             state.speed == speed &&
 423             state.duplex == duplex &&
 424             (state.interface == mode ||
 425              state.interface == PHY_INTERFACE_MODE_NA))
 426                 return 0;
 427
 428         /* Port's MAC control must not be changed unless the link is down */
 429         err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
 430         if (err)
 431                 return err;
 432
 433         if (chip->info->ops->port_set_speed) {
 434                 err = chip->info->ops->port_set_speed(chip, port, speed);
 435                 if (err && err != -EOPNOTSUPP)
 436                         goto restore_link;
 437         }
 438
 439         if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode)
 440                 mode = chip->info->ops->port_max_speed_mode(port);
 441
 442         if (chip->info->ops->port_set_pause) {
 443                 err = chip->info->ops->port_set_pause(chip, port, pause);
 444                 if (err)
 445                         goto restore_link;
 446         }
 447
 448         if (chip->info->ops->port_set_duplex) {
 449                 err = chip->info->ops->port_set_duplex(chip, port, duplex);
 450                 if (err && err != -EOPNOTSUPP)
 451                         goto restore_link;
 452         }
 453
 454         if (chip->info->ops->port_set_rgmii_delay) {
 455                 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
 456                 if (err && err != -EOPNOTSUPP)
 457                         goto restore_link;
 458         }
 459
 460         if (chip->info->ops->port_set_cmode) {
 461                 err = chip->info->ops->port_set_cmode(chip, port, mode);
 462                 if (err && err != -EOPNOTSUPP)
 463                         goto restore_link;
 464         }
 465
 466         err = 0;
 467 restore_link:
 468         if (chip->info->ops->port_set_link(chip, port, link))
 469                 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
 470
 471         return err;
 472 }
 473
 474 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
 475 {
 476         struct mv88e6xxx_chip *chip = ds->priv;
 477
 478         return port < chip->info->num_internal_phys;
 479 }
 480
 481 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 482                                        unsigned long *mask,
 483                                        struct phylink_link_state *state)
 484 {
 485         if (!phy_interface_mode_is_8023z(state->interface)) {
 486                 /* 10M and 100M are only supported in non-802.3z mode */
 487                 phylink_set(mask, 10baseT_Half);
 488                 phylink_set(mask, 10baseT_Full);
 489                 phylink_set(mask, 100baseT_Half);
 490                 phylink_set(mask, 100baseT_Full);
 491         }
 492 }
 493
 494 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 495                                        unsigned long *mask,
 496                                        struct phylink_link_state *state)
 497 {
 498         /* FIXME: if the port is in 1000Base-X mode, then it only supports
 499          * 1000M FD speeds.  In this case, CMODE will indicate 5.
 500          */
 501         phylink_set(mask, 1000baseT_Full);
 502         phylink_set(mask, 1000baseX_Full);
 503
 504         mv88e6065_phylink_validate(chip, port, mask, state);
 505 }
 506
 507 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 508                                        unsigned long *mask,
 509                                        struct phylink_link_state *state)
 510 {
 511         if (port >= 5)
 512                 phylink_set(mask, 2500baseX_Full);
 513
 514         /* No ethtool bits for 200Mbps */
 515         phylink_set(mask, 1000baseT_Full);
 516         phylink_set(mask, 1000baseX_Full);
 517
 518         mv88e6065_phylink_validate(chip, port, mask, state);
 519 }
 520
 521 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 522                                        unsigned long *mask,
 523                                        struct phylink_link_state *state)
 524 {
 525         /* No ethtool bits for 200Mbps */
 526         phylink_set(mask, 1000baseT_Full);
 527         phylink_set(mask, 1000baseX_Full);
 528
 529         mv88e6065_phylink_validate(chip, port, mask, state);
 530 }
 531
 532 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 533                                        unsigned long *mask,
 534                                        struct phylink_link_state *state)
 535 {
 536         if (port >= 9) {
 537                 phylink_set(mask, 2500baseX_Full);
 538                 phylink_set(mask, 2500baseT_Full);
 539         }
 540
 541         /* No ethtool bits for 200Mbps */
 542         phylink_set(mask, 1000baseT_Full);
 543         phylink_set(mask, 1000baseX_Full);
 544
 545         mv88e6065_phylink_validate(chip, port, mask, state);
 546 }
 547
 548 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
 549                                         unsigned long *mask,
 550                                         struct phylink_link_state *state)
 551 {
 552         if (port >= 9) {
 553                 phylink_set(mask, 10000baseT_Full);
 554                 phylink_set(mask, 10000baseKR_Full);
 555         }
 556
 557         mv88e6390_phylink_validate(chip, port, mask, state);
 558 }
 559
 560 static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
 561                                unsigned long *supported,
 562                                struct phylink_link_state *state)
 563 {
 564         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 565         struct mv88e6xxx_chip *chip = ds->priv;
 566
 567         /* Allow all the expected bits */
 568         phylink_set(mask, Autoneg);
 569         phylink_set(mask, Pause);
 570         phylink_set_port_modes(mask);
 571
 572         if (chip->info->ops->phylink_validate)
 573                 chip->info->ops->phylink_validate(chip, port, mask, state);
 574
 575         bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
 576         bitmap_and(state->advertising, state->advertising, mask,
 577                    __ETHTOOL_LINK_MODE_MASK_NBITS);
 578
 579         /* We can only operate at 2500BaseX or 1000BaseX.  If requested
 580          * to advertise both, only report advertising at 2500BaseX.
 581          */
 582         phylink_helper_basex_speed(state);
 583 }
 584
 585 static int mv88e6xxx_link_state(struct dsa_switch *ds, int port,
 586                                 struct phylink_link_state *state)
 587 {
 588         struct mv88e6xxx_chip *chip = ds->priv;
 589         int err;
 590
 591         mv88e6xxx_reg_lock(chip);
 592         if (chip->info->ops->port_link_state)
 593                 err = chip->info->ops->port_link_state(chip, port, state);
 594         else
 595                 err = -EOPNOTSUPP;
 596         mv88e6xxx_reg_unlock(chip);
 597
 598         return err;
 599 }
 600
 601 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
 602                                  unsigned int mode,
 603                                  const struct phylink_link_state *state)
 604 {
 605         struct mv88e6xxx_chip *chip = ds->priv;
 606         int speed, duplex, link, pause, err;
 607
 608         if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port))
 609                 return;
 610
 611         if (mode == MLO_AN_FIXED) {
 612                 link = LINK_FORCED_UP;
 613                 speed = state->speed;
 614                 duplex = state->duplex;
 615         } else if (!mv88e6xxx_phy_is_internal(ds, port)) {
 616                 link = state->link;
 617                 speed = state->speed;
 618                 duplex = state->duplex;
 619         } else {
 620                 speed = SPEED_UNFORCED;
 621                 duplex = DUPLEX_UNFORCED;
 622                 link = LINK_UNFORCED;
 623         }
 624         pause = !!phylink_test(state->advertising, Pause);
 625
 626         mv88e6xxx_reg_lock(chip);
 627         err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex, pause,
 628                                        state->interface);
 629         mv88e6xxx_reg_unlock(chip);
 630
 631         if (err && err != -EOPNOTSUPP)
 632                 dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
 633 }
 634
 635 static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link)
 636 {
 637         struct mv88e6xxx_chip *chip = ds->priv;
 638         int err;
 639
 640         mv88e6xxx_reg_lock(chip);
 641         err = chip->info->ops->port_set_link(chip, port, link);
 642         mv88e6xxx_reg_unlock(chip);
 643
 644         if (err)
 645                 dev_err(chip->dev, "p%d: failed to force MAC link\n", port);
 646 }
 647
 648 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
 649                                     unsigned int mode,
 650                                     phy_interface_t interface)
 651 {
 652         if (mode == MLO_AN_FIXED)
 653                 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN);
 654 }
 655
 656 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
 657                                   unsigned int mode, phy_interface_t interface,
 658                                   struct phy_device *phydev)
 659 {
 660         if (mode == MLO_AN_FIXED)
 661                 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP);
 662 }
 663
 664 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
 665 {
 666         if (!chip->info->ops->stats_snapshot)
 667                 return -EOPNOTSUPP;
 668
 669         return chip->info->ops->stats_snapshot(chip, port);
 670 }
 671
 672 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
 673         { "in_good_octets",             8, 0x00, STATS_TYPE_BANK0, },
 674         { "in_bad_octets",              4, 0x02, STATS_TYPE_BANK0, },
 675         { "in_unicast",                 4, 0x04, STATS_TYPE_BANK0, },
 676         { "in_broadcasts",              4, 0x06, STATS_TYPE_BANK0, },
 677         { "in_multicasts",              4, 0x07, STATS_TYPE_BANK0, },
 678         { "in_pause",                   4, 0x16, STATS_TYPE_BANK0, },
 679         { "in_undersize",               4, 0x18, STATS_TYPE_BANK0, },
 680         { "in_fragments",               4, 0x19, STATS_TYPE_BANK0, },
 681         { "in_oversize",                4, 0x1a, STATS_TYPE_BANK0, },
 682         { "in_jabber",                  4, 0x1b, STATS_TYPE_BANK0, },
 683         { "in_rx_error",                4, 0x1c, STATS_TYPE_BANK0, },
 684         { "in_fcs_error",               4, 0x1d, STATS_TYPE_BANK0, },
 685         { "out_octets",                 8, 0x0e, STATS_TYPE_BANK0, },
 686         { "out_unicast",                4, 0x10, STATS_TYPE_BANK0, },
 687         { "out_broadcasts",             4, 0x13, STATS_TYPE_BANK0, },
 688         { "out_multicasts",             4, 0x12, STATS_TYPE_BANK0, },
 689         { "out_pause",                  4, 0x15, STATS_TYPE_BANK0, },
 690         { "excessive",                  4, 0x11, STATS_TYPE_BANK0, },
 691         { "collisions",                 4, 0x1e, STATS_TYPE_BANK0, },
 692         { "deferred",                   4, 0x05, STATS_TYPE_BANK0, },
 693         { "single",                     4, 0x14, STATS_TYPE_BANK0, },
 694         { "multiple",                   4, 0x17, STATS_TYPE_BANK0, },
 695         { "out_fcs_error",              4, 0x03, STATS_TYPE_BANK0, },
 696         { "late",                       4, 0x1f, STATS_TYPE_BANK0, },
 697         { "hist_64bytes",               4, 0x08, STATS_TYPE_BANK0, },
 698         { "hist_65_127bytes",           4, 0x09, STATS_TYPE_BANK0, },
 699         { "hist_128_255bytes",          4, 0x0a, STATS_TYPE_BANK0, },
 700         { "hist_256_511bytes",          4, 0x0b, STATS_TYPE_BANK0, },
 701         { "hist_512_1023bytes",         4, 0x0c, STATS_TYPE_BANK0, },
 702         { "hist_1024_max_bytes",        4, 0x0d, STATS_TYPE_BANK0, },
 703         { "sw_in_discards",             4, 0x10, STATS_TYPE_PORT, },
 704         { "sw_in_filtered",             2, 0x12, STATS_TYPE_PORT, },
 705         { "sw_out_filtered",            2, 0x13, STATS_TYPE_PORT, },
 706         { "in_discards",                4, 0x00, STATS_TYPE_BANK1, },
 707         { "in_filtered",                4, 0x01, STATS_TYPE_BANK1, },
 708         { "in_accepted",                4, 0x02, STATS_TYPE_BANK1, },
 709         { "in_bad_accepted",            4, 0x03, STATS_TYPE_BANK1, },
 710         { "in_good_avb_class_a",        4, 0x04, STATS_TYPE_BANK1, },
 711         { "in_good_avb_class_b",        4, 0x05, STATS_TYPE_BANK1, },
 712         { "in_bad_avb_class_a",         4, 0x06, STATS_TYPE_BANK1, },
 713         { "in_bad_avb_class_b",         4, 0x07, STATS_TYPE_BANK1, },
 714         { "tcam_counter_0",             4, 0x08, STATS_TYPE_BANK1, },
 715         { "tcam_counter_1",             4, 0x09, STATS_TYPE_BANK1, },
 716         { "tcam_counter_2",             4, 0x0a, STATS_TYPE_BANK1, },
 717         { "tcam_counter_3",             4, 0x0b, STATS_TYPE_BANK1, },
 718         { "in_da_unknown",              4, 0x0e, STATS_TYPE_BANK1, },
 719         { "in_management",              4, 0x0f, STATS_TYPE_BANK1, },
 720         { "out_queue_0",                4, 0x10, STATS_TYPE_BANK1, },
 721         { "out_queue_1",                4, 0x11, STATS_TYPE_BANK1, },
 722         { "out_queue_2",                4, 0x12, STATS_TYPE_BANK1, },
 723         { "out_queue_3",                4, 0x13, STATS_TYPE_BANK1, },
 724         { "out_queue_4",                4, 0x14, STATS_TYPE_BANK1, },
 725         { "out_queue_5",                4, 0x15, STATS_TYPE_BANK1, },
 726         { "out_queue_6",                4, 0x16, STATS_TYPE_BANK1, },
 727         { "out_queue_7",                4, 0x17, STATS_TYPE_BANK1, },
 728         { "out_cut_through",            4, 0x18, STATS_TYPE_BANK1, },
 729         { "out_octets_a",               4, 0x1a, STATS_TYPE_BANK1, },
 730         { "out_octets_b",               4, 0x1b, STATS_TYPE_BANK1, },
 731         { "out_management",             4, 0x1f, STATS_TYPE_BANK1, },
 732 };
 733
 734 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
 735                                             struct mv88e6xxx_hw_stat *s,
 736                                             int port, u16 bank1_select,
 737                                             u16 histogram)
 738 {
 739         u32 low;
 740         u32 high = 0;
 741         u16 reg = 0;
 742         int err;
 743         u64 value;
 744
 745         switch (s->type) {
 746         case STATS_TYPE_PORT:
 747                 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
 748                 if (err)
 749                         return U64_MAX;
 750
 751                 low = reg;
 752                 if (s->size == 4) {
 753                         err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
 754                         if (err)
 755                                 return U64_MAX;
 756                         low |= ((u32)reg) << 16;
 757                 }
 758                 break;
 759         case STATS_TYPE_BANK1:
 760                 reg = bank1_select;
 761                 /* fall through */
 762         case STATS_TYPE_BANK0:
 763                 reg |= s->reg | histogram;
 764                 mv88e6xxx_g1_stats_read(chip, reg, &low);
 765                 if (s->size == 8)
 766                         mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
 767                 break;
 768         default:
 769                 return U64_MAX;
 770         }
 771         value = (((u64)high) << 32) | low;
 772         return value;
 773 }
 774
 775 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
 776                                        uint8_t *data, int types)
 777 {
 778         struct mv88e6xxx_hw_stat *stat;
 779         int i, j;
 780
 781         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 782                 stat = &mv88e6xxx_hw_stats[i];
 783                 if (stat->type & types) {
 784                         memcpy(data + j * ETH_GSTRING_LEN, stat->string,
 785                                ETH_GSTRING_LEN);
 786                         j++;
 787                 }
 788         }
 789
 790         return j;
 791 }
 792
 793 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
 794                                        uint8_t *data)
 795 {
 796         return mv88e6xxx_stats_get_strings(chip, data,
 797                                            STATS_TYPE_BANK0 | STATS_TYPE_PORT);
 798 }
 799
 800 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
 801                                        uint8_t *data)
 802 {
 803         return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
 804 }
 805
 806 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
 807                                        uint8_t *data)
 808 {
 809         return mv88e6xxx_stats_get_strings(chip, data,
 810                                            STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
 811 }
 812
 813 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
 814         "atu_member_violation",
 815         "atu_miss_violation",
 816         "atu_full_violation",
 817         "vtu_member_violation",
 818         "vtu_miss_violation",
 819 };
 820
 821 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
 822 {
 823         unsigned int i;
 824
 825         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
 826                 strlcpy(data + i * ETH_GSTRING_LEN,
 827                         mv88e6xxx_atu_vtu_stats_strings[i],
 828                         ETH_GSTRING_LEN);
 829 }
 830
 831 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
 832                                   u32 stringset, uint8_t *data)
 833 {
 834         struct mv88e6xxx_chip *chip = ds->priv;
 835         int count = 0;
 836
 837         if (stringset != ETH_SS_STATS)
 838                 return;
 839
 840         mv88e6xxx_reg_lock(chip);
 841
 842         if (chip->info->ops->stats_get_strings)
 843                 count = chip->info->ops->stats_get_strings(chip, data);
 844
 845         if (chip->info->ops->serdes_get_strings) {
 846                 data += count * ETH_GSTRING_LEN;
 847                 count = chip->info->ops->serdes_get_strings(chip, port, data);
 848         }
 849
 850         data += count * ETH_GSTRING_LEN;
 851         mv88e6xxx_atu_vtu_get_strings(data);
 852
 853         mv88e6xxx_reg_unlock(chip);
 854 }
 855
 856 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
 857                                           int types)
 858 {
 859         struct mv88e6xxx_hw_stat *stat;
 860         int i, j;
 861
 862         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 863                 stat = &mv88e6xxx_hw_stats[i];
 864                 if (stat->type & types)
 865                         j++;
 866         }
 867         return j;
 868 }
 869
 870 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
 871 {
 872         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
 873                                               STATS_TYPE_PORT);
 874 }
 875
 876 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
 877 {
 878         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
 879 }
 880
 881 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
 882 {
 883         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
 884                                               STATS_TYPE_BANK1);
 885 }
 886
 887 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
 888 {
 889         struct mv88e6xxx_chip *chip = ds->priv;
 890         int serdes_count = 0;
 891         int count = 0;
 892
 893         if (sset != ETH_SS_STATS)
 894                 return 0;
 895
 896         mv88e6xxx_reg_lock(chip);
 897         if (chip->info->ops->stats_get_sset_count)
 898                 count = chip->info->ops->stats_get_sset_count(chip);
 899         if (count < 0)
 900                 goto out;
 901
 902         if (chip->info->ops->serdes_get_sset_count)
 903                 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
 904                                                                       port);
 905         if (serdes_count < 0) {
 906                 count = serdes_count;
 907                 goto out;
 908         }
 909         count += serdes_count;
 910         count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
 911
 912 out:
 913         mv88e6xxx_reg_unlock(chip);
 914
 915         return count;
 916 }
 917
 918 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
 919                                      uint64_t *data, int types,
 920                                      u16 bank1_select, u16 histogram)
 921 {
 922         struct mv88e6xxx_hw_stat *stat;
 923         int i, j;
 924
 925         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 926                 stat = &mv88e6xxx_hw_stats[i];
 927                 if (stat->type & types) {
 928                         mv88e6xxx_reg_lock(chip);
 929                         data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
 930                                                               bank1_select,
 931                                                               histogram);
 932                         mv88e6xxx_reg_unlock(chip);
 933
 934                         j++;
 935                 }
 936         }
 937         return j;
 938 }
 939
 940 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
 941                                      uint64_t *data)
 942 {
 943         return mv88e6xxx_stats_get_stats(chip, port, data,
 944                                          STATS_TYPE_BANK0 | STATS_TYPE_PORT,
 945                                          0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
 946 }
 947
 948 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
 949                                      uint64_t *data)
 950 {
 951         return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
 952                                          0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
 953 }
 954
 955 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
 956                                      uint64_t *data)
 957 {
 958         return mv88e6xxx_stats_get_stats(chip, port, data,
 959                                          STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
 960                                          MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
 961                                          MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
 962 }
 963
 964 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
 965                                      uint64_t *data)
 966 {
 967         return mv88e6xxx_stats_get_stats(chip, port, data,
 968                                          STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
 969                                          MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
 970                                          0);
 971 }
 972
 973 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
 974                                         uint64_t *data)
 975 {
 976         *data++ = chip->ports[port].atu_member_violation;
 977         *data++ = chip->ports[port].atu_miss_violation;
 978         *data++ = chip->ports[port].atu_full_violation;
 979         *data++ = chip->ports[port].vtu_member_violation;
 980         *data++ = chip->ports[port].vtu_miss_violation;
 981 }
 982
 983 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
 984                                 uint64_t *data)
 985 {
 986         int count = 0;
 987
 988         if (chip->info->ops->stats_get_stats)
 989                 count = chip->info->ops->stats_get_stats(chip, port, data);
 990
 991         mv88e6xxx_reg_lock(chip);
 992         if (chip->info->ops->serdes_get_stats) {
 993                 data += count;
 994                 count = chip->info->ops->serdes_get_stats(chip, port, data);
 995         }
 996         data += count;
 997         mv88e6xxx_atu_vtu_get_stats(chip, port, data);
 998         mv88e6xxx_reg_unlock(chip);
 999 }
1000
1001 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1002                                         uint64_t *data)
1003 {
1004         struct mv88e6xxx_chip *chip = ds->priv;
1005         int ret;
1006
1007         mv88e6xxx_reg_lock(chip);
1008
1009         ret = mv88e6xxx_stats_snapshot(chip, port);
1010         mv88e6xxx_reg_unlock(chip);
1011
1012         if (ret < 0)
1013                 return;
1014
1015         mv88e6xxx_get_stats(chip, port, data);
1016
1017 }
1018
1019 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1020 {
1021         return 32 * sizeof(u16);
1022 }
1023
1024 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1025                                struct ethtool_regs *regs, void *_p)
1026 {
1027         struct mv88e6xxx_chip *chip = ds->priv;
1028         int err;
1029         u16 reg;
1030         u16 *p = _p;
1031         int i;
1032
1033         regs->version = chip->info->prod_num;
1034
1035         memset(p, 0xff, 32 * sizeof(u16));
1036
1037         mv88e6xxx_reg_lock(chip);
1038
1039         for (i = 0; i < 32; i++) {
1040
1041                 err = mv88e6xxx_port_read(chip, port, i, &reg);
1042                 if (!err)
1043                         p[i] = reg;
1044         }
1045
1046         mv88e6xxx_reg_unlock(chip);
1047 }
1048
1049 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1050                                  struct ethtool_eee *e)
1051 {
1052         /* Nothing to do on the port's MAC */
1053         return 0;
1054 }
1055
1056 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1057                                  struct ethtool_eee *e)
1058 {
1059         /* Nothing to do on the port's MAC */
1060         return 0;
1061 }
1062
1063 /* Mask of the local ports allowed to receive frames from a given fabric port */
1064 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1065 {
1066         struct dsa_switch *ds = chip->ds;
1067         struct dsa_switch_tree *dst = ds->dst;
1068         struct net_device *br;
1069         struct dsa_port *dp;
1070         bool found = false;
1071         u16 pvlan;
1072
1073         list_for_each_entry(dp, &dst->ports, list) {
1074                 if (dp->ds->index == dev && dp->index == port) {
1075                         found = true;
1076                         break;
1077                 }
1078         }
1079
1080         /* Prevent frames from unknown switch or port */
1081         if (!found)
1082                 return 0;
1083
1084         /* Frames from DSA links and CPU ports can egress any local port */
1085         if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1086                 return mv88e6xxx_port_mask(chip);
1087
1088         br = dp->bridge_dev;
1089         pvlan = 0;
1090
1091         /* Frames from user ports can egress any local DSA links and CPU ports,
1092          * as well as any local member of their bridge group.
1093          */
1094         list_for_each_entry(dp, &dst->ports, list)
1095                 if (dp->ds == ds &&
1096                     (dp->type == DSA_PORT_TYPE_CPU ||
1097                      dp->type == DSA_PORT_TYPE_DSA ||
1098                      (br && dp->bridge_dev == br)))
1099                         pvlan |= BIT(dp->index);
1100
1101         return pvlan;
1102 }
1103
1104 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1105 {
1106         u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1107
1108         /* prevent frames from going back out of the port they came in on */
1109         output_ports &= ~BIT(port);
1110
1111         return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1112 }
1113
1114 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1115                                          u8 state)
1116 {
1117         struct mv88e6xxx_chip *chip = ds->priv;
1118         int err;
1119
1120         mv88e6xxx_reg_lock(chip);
1121         err = mv88e6xxx_port_set_state(chip, port, state);
1122         mv88e6xxx_reg_unlock(chip);
1123
1124         if (err)
1125                 dev_err(ds->dev, "p%d: failed to update state\n", port);
1126 }
1127
1128 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1129 {
1130         int err;
1131
1132         if (chip->info->ops->ieee_pri_map) {
1133                 err = chip->info->ops->ieee_pri_map(chip);
1134                 if (err)
1135                         return err;
1136         }
1137
1138         if (chip->info->ops->ip_pri_map) {
1139                 err = chip->info->ops->ip_pri_map(chip);
1140                 if (err)
1141                         return err;
1142         }
1143
1144         return 0;
1145 }
1146
1147 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1148 {
1149         struct dsa_switch *ds = chip->ds;
1150         int target, port;
1151         int err;
1152
1153         if (!chip->info->global2_addr)
1154                 return 0;
1155
1156         /* Initialize the routing port to the 32 possible target devices */
1157         for (target = 0; target < 32; target++) {
1158                 port = dsa_routing_port(ds, target);
1159                 if (port == ds->num_ports)
1160                         port = 0x1f;
1161
1162                 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1163                 if (err)
1164                         return err;
1165         }
1166
1167         if (chip->info->ops->set_cascade_port) {
1168                 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1169                 err = chip->info->ops->set_cascade_port(chip, port);
1170                 if (err)
1171                         return err;
1172         }
1173
1174         err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1175         if (err)
1176                 return err;
1177
1178         return 0;
1179 }
1180
1181 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1182 {
1183         /* Clear all trunk masks and mapping */
1184         if (chip->info->global2_addr)
1185                 return mv88e6xxx_g2_trunk_clear(chip);
1186
1187         return 0;
1188 }
1189
1190 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1191 {
1192         if (chip->info->ops->rmu_disable)
1193                 return chip->info->ops->rmu_disable(chip);
1194
1195         return 0;
1196 }
1197
1198 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1199 {
1200         if (chip->info->ops->pot_clear)
1201                 return chip->info->ops->pot_clear(chip);
1202
1203         return 0;
1204 }
1205
1206 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1207 {
1208         if (chip->info->ops->mgmt_rsvd2cpu)
1209                 return chip->info->ops->mgmt_rsvd2cpu(chip);
1210
1211         return 0;
1212 }
1213
1214 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1215 {
1216         int err;
1217
1218         err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1219         if (err)
1220                 return err;
1221
1222         err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1223         if (err)
1224                 return err;
1225
1226         return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1227 }
1228
1229 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1230 {
1231         int port;
1232         int err;
1233
1234         if (!chip->info->ops->irl_init_all)
1235                 return 0;
1236
1237         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1238                 /* Disable ingress rate limiting by resetting all per port
1239                  * ingress rate limit resources to their initial state.
1240                  */
1241                 err = chip->info->ops->irl_init_all(chip, port);
1242                 if (err)
1243                         return err;
1244         }
1245
1246         return 0;
1247 }
1248
1249 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1250 {
1251         if (chip->info->ops->set_switch_mac) {
1252                 u8 addr[ETH_ALEN];
1253
1254                 eth_random_addr(addr);
1255
1256                 return chip->info->ops->set_switch_mac(chip, addr);
1257         }
1258
1259         return 0;
1260 }
1261
1262 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1263 {
1264         u16 pvlan = 0;
1265
1266         if (!mv88e6xxx_has_pvt(chip))
1267                 return 0;
1268
1269         /* Skip the local source device, which uses in-chip port VLAN */
1270         if (dev != chip->ds->index)
1271                 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1272
1273         return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1274 }
1275
1276 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1277 {
1278         int dev, port;
1279         int err;
1280
1281         if (!mv88e6xxx_has_pvt(chip))
1282                 return 0;
1283
1284         /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1285          * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1286          */
1287         err = mv88e6xxx_g2_misc_4_bit_port(chip);
1288         if (err)
1289                 return err;
1290
1291         for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1292                 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1293                         err = mv88e6xxx_pvt_map(chip, dev, port);
1294                         if (err)
1295                                 return err;
1296                 }
1297         }
1298
1299         return 0;
1300 }
1301
1302 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1303 {
1304         struct mv88e6xxx_chip *chip = ds->priv;
1305         int err;
1306
1307         mv88e6xxx_reg_lock(chip);
1308         err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1309         mv88e6xxx_reg_unlock(chip);
1310
1311         if (err)
1312                 dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1313 }
1314
1315 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1316 {
1317         if (!chip->info->max_vid)
1318                 return 0;
1319
1320         return mv88e6xxx_g1_vtu_flush(chip);
1321 }
1322
1323 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1324                                  struct mv88e6xxx_vtu_entry *entry)
1325 {
1326         if (!chip->info->ops->vtu_getnext)
1327                 return -EOPNOTSUPP;
1328
1329         return chip->info->ops->vtu_getnext(chip, entry);
1330 }
1331
1332 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1333                                    struct mv88e6xxx_vtu_entry *entry)
1334 {
1335         if (!chip->info->ops->vtu_loadpurge)
1336                 return -EOPNOTSUPP;
1337
1338         return chip->info->ops->vtu_loadpurge(chip, entry);
1339 }
1340
1341 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1342 {
1343         DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1344         struct mv88e6xxx_vtu_entry vlan;
1345         int i, err;
1346
1347         bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1348
1349         /* Set every FID bit used by the (un)bridged ports */
1350         for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1351                 err = mv88e6xxx_port_get_fid(chip, i, fid);
1352                 if (err)
1353                         return err;
1354
1355                 set_bit(*fid, fid_bitmap);
1356         }
1357
1358         /* Set every FID bit used by the VLAN entries */
1359         vlan.vid = chip->info->max_vid;
1360         vlan.valid = false;
1361
1362         do {
1363                 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1364                 if (err)
1365                         return err;
1366
1367                 if (!vlan.valid)
1368                         break;
1369
1370                 set_bit(vlan.fid, fid_bitmap);
1371         } while (vlan.vid < chip->info->max_vid);
1372
1373         /* The reset value 0x000 is used to indicate that multiple address
1374          * databases are not needed. Return the next positive available.
1375          */
1376         *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1377         if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1378                 return -ENOSPC;
1379
1380         /* Clear the database */
1381         return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1382 }
1383
1384 static int mv88e6xxx_atu_get_hash(struct mv88e6xxx_chip *chip, u8 *hash)
1385 {
1386         if (chip->info->ops->atu_get_hash)
1387                 return chip->info->ops->atu_get_hash(chip, hash);
1388
1389         return -EOPNOTSUPP;
1390 }
1391
1392 static int mv88e6xxx_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash)
1393 {
1394         if (chip->info->ops->atu_set_hash)
1395                 return chip->info->ops->atu_set_hash(chip, hash);
1396
1397         return -EOPNOTSUPP;
1398 }
1399
1400 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1401                                         u16 vid_begin, u16 vid_end)
1402 {
1403         struct mv88e6xxx_chip *chip = ds->priv;
1404         struct mv88e6xxx_vtu_entry vlan;
1405         int i, err;
1406
1407         /* DSA and CPU ports have to be members of multiple vlans */
1408         if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1409                 return 0;
1410
1411         if (!vid_begin)
1412                 return -EOPNOTSUPP;
1413
1414         vlan.vid = vid_begin - 1;
1415         vlan.valid = false;
1416
1417         do {
1418                 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1419                 if (err)
1420                         return err;
1421
1422                 if (!vlan.valid)
1423                         break;
1424
1425                 if (vlan.vid > vid_end)
1426                         break;
1427
1428                 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1429                         if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1430                                 continue;
1431
1432                         if (!dsa_to_port(ds, i)->slave)
1433                                 continue;
1434
1435                         if (vlan.member[i] ==
1436                             MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1437                                 continue;
1438
1439                         if (dsa_to_port(ds, i)->bridge_dev ==
1440                             dsa_to_port(ds, port)->bridge_dev)
1441                                 break; /* same bridge, check next VLAN */
1442
1443                         if (!dsa_to_port(ds, i)->bridge_dev)
1444                                 continue;
1445
1446                         dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1447                                 port, vlan.vid, i,
1448                                 netdev_name(dsa_to_port(ds, i)->bridge_dev));
1449                         return -EOPNOTSUPP;
1450                 }
1451         } while (vlan.vid < vid_end);
1452
1453         return 0;
1454 }
1455
1456 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1457                                          bool vlan_filtering)
1458 {
1459         struct mv88e6xxx_chip *chip = ds->priv;
1460         u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1461                 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1462         int err;
1463
1464         if (!chip->info->max_vid)
1465                 return -EOPNOTSUPP;
1466
1467         mv88e6xxx_reg_lock(chip);
1468         err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1469         mv88e6xxx_reg_unlock(chip);
1470
1471         return err;
1472 }
1473
1474 static int
1475 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1476                             const struct switchdev_obj_port_vlan *vlan)
1477 {
1478         struct mv88e6xxx_chip *chip = ds->priv;
1479         int err;
1480
1481         if (!chip->info->max_vid)
1482                 return -EOPNOTSUPP;
1483
1484         /* If the requested port doesn't belong to the same bridge as the VLAN
1485          * members, do not support it (yet) and fallback to software VLAN.
1486          */
1487         mv88e6xxx_reg_lock(chip);
1488         err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1489                                            vlan->vid_end);
1490         mv88e6xxx_reg_unlock(chip);
1491
1492         /* We don't need any dynamic resource from the kernel (yet),
1493          * so skip the prepare phase.
1494          */
1495         return err;
1496 }
1497
1498 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1499                                         const unsigned char *addr, u16 vid,
1500                                         u8 state)
1501 {
1502         struct mv88e6xxx_atu_entry entry;
1503         struct mv88e6xxx_vtu_entry vlan;
1504         u16 fid;
1505         int err;
1506
1507         /* Null VLAN ID corresponds to the port private database */
1508         if (vid == 0) {
1509                 err = mv88e6xxx_port_get_fid(chip, port, &fid);
1510                 if (err)
1511                         return err;
1512         } else {
1513                 vlan.vid = vid - 1;
1514                 vlan.valid = false;
1515
1516                 err = mv88e6xxx_vtu_getnext(chip, &vlan);
1517                 if (err)
1518                         return err;
1519
1520                 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
1521                 if (vlan.vid != vid || !vlan.valid)
1522                         return -EOPNOTSUPP;
1523
1524                 fid = vlan.fid;
1525         }
1526
1527         entry.state = 0;
1528         ether_addr_copy(entry.mac, addr);
1529         eth_addr_dec(entry.mac);
1530
1531         err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
1532         if (err)
1533                 return err;
1534
1535         /* Initialize a fresh ATU entry if it isn't found */
1536         if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
1537                 memset(&entry, 0, sizeof(entry));
1538                 ether_addr_copy(entry.mac, addr);
1539         }
1540
1541         /* Purge the ATU entry only if no port is using it anymore */
1542         if (!state) {
1543                 entry.portvec &= ~BIT(port);
1544                 if (!entry.portvec)
1545                         entry.state = 0;
1546         } else {
1547                 entry.portvec |= BIT(port);
1548                 entry.state = state;
1549         }
1550
1551         return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
1552 }
1553
1554 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
1555                                   const struct mv88e6xxx_policy *policy)
1556 {
1557         enum mv88e6xxx_policy_mapping mapping = policy->mapping;
1558         enum mv88e6xxx_policy_action action = policy->action;
1559         const u8 *addr = policy->addr;
1560         u16 vid = policy->vid;
1561         u8 state;
1562         int err;
1563         int id;
1564
1565         if (!chip->info->ops->port_set_policy)
1566                 return -EOPNOTSUPP;
1567
1568         switch (mapping) {
1569         case MV88E6XXX_POLICY_MAPPING_DA:
1570         case MV88E6XXX_POLICY_MAPPING_SA:
1571                 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1572                         state = 0; /* Dissociate the port and address */
1573                 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1574                          is_multicast_ether_addr(addr))
1575                         state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
1576                 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
1577                          is_unicast_ether_addr(addr))
1578                         state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
1579                 else
1580                         return -EOPNOTSUPP;
1581
1582                 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1583                                                    state);
1584                 if (err)
1585                         return err;
1586                 break;
1587         default:
1588                 return -EOPNOTSUPP;
1589         }
1590
1591         /* Skip the port's policy clearing if the mapping is still in use */
1592         if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
1593                 idr_for_each_entry(&chip->policies, policy, id)
1594                         if (policy->port == port &&
1595                             policy->mapping == mapping &&
1596                             policy->action != action)
1597                                 return 0;
1598
1599         return chip->info->ops->port_set_policy(chip, port, mapping, action);
1600 }
1601
1602 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
1603                                    struct ethtool_rx_flow_spec *fs)
1604 {
1605         struct ethhdr *mac_entry = &fs->h_u.ether_spec;
1606         struct ethhdr *mac_mask = &fs->m_u.ether_spec;
1607         enum mv88e6xxx_policy_mapping mapping;
1608         enum mv88e6xxx_policy_action action;
1609         struct mv88e6xxx_policy *policy;
1610         u16 vid = 0;
1611         u8 *addr;
1612         int err;
1613         int id;
1614
1615         if (fs->location != RX_CLS_LOC_ANY)
1616                 return -EINVAL;
1617
1618         if (fs->ring_cookie == RX_CLS_FLOW_DISC)
1619                 action = MV88E6XXX_POLICY_ACTION_DISCARD;
1620         else
1621                 return -EOPNOTSUPP;
1622
1623         switch (fs->flow_type & ~FLOW_EXT) {
1624         case ETHER_FLOW:
1625                 if (!is_zero_ether_addr(mac_mask->h_dest) &&
1626                     is_zero_ether_addr(mac_mask->h_source)) {
1627                         mapping = MV88E6XXX_POLICY_MAPPING_DA;
1628                         addr = mac_entry->h_dest;
1629                 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
1630                     !is_zero_ether_addr(mac_mask->h_source)) {
1631                         mapping = MV88E6XXX_POLICY_MAPPING_SA;
1632                         addr = mac_entry->h_source;
1633                 } else {
1634                         /* Cannot support DA and SA mapping in the same rule */
1635                         return -EOPNOTSUPP;
1636                 }
1637                 break;
1638         default:
1639                 return -EOPNOTSUPP;
1640         }
1641
1642         if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
1643                 if (fs->m_ext.vlan_tci != 0xffff)
1644                         return -EOPNOTSUPP;
1645                 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
1646         }
1647
1648         idr_for_each_entry(&chip->policies, policy, id) {
1649                 if (policy->port == port && policy->mapping == mapping &&
1650                     policy->action == action && policy->vid == vid &&
1651                     ether_addr_equal(policy->addr, addr))
1652                         return -EEXIST;
1653         }
1654
1655         policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
1656         if (!policy)
1657                 return -ENOMEM;
1658
1659         fs->location = 0;
1660         err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
1661                             GFP_KERNEL);
1662         if (err) {
1663                 devm_kfree(chip->dev, policy);
1664                 return err;
1665         }
1666
1667         memcpy(&policy->fs, fs, sizeof(*fs));
1668         ether_addr_copy(policy->addr, addr);
1669         policy->mapping = mapping;
1670         policy->action = action;
1671         policy->port = port;
1672         policy->vid = vid;
1673
1674         err = mv88e6xxx_policy_apply(chip, port, policy);
1675         if (err) {
1676                 idr_remove(&chip->policies, fs->location);
1677                 devm_kfree(chip->dev, policy);
1678                 return err;
1679         }
1680
1681         return 0;
1682 }
1683
1684 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
1685                                struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
1686 {
1687         struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1688         struct mv88e6xxx_chip *chip = ds->priv;
1689         struct mv88e6xxx_policy *policy;
1690         int err;
1691         int id;
1692
1693         mv88e6xxx_reg_lock(chip);
1694
1695         switch (rxnfc->cmd) {
1696         case ETHTOOL_GRXCLSRLCNT:
1697                 rxnfc->data = 0;
1698                 rxnfc->data |= RX_CLS_LOC_SPECIAL;
1699                 rxnfc->rule_cnt = 0;
1700                 idr_for_each_entry(&chip->policies, policy, id)
1701                         if (policy->port == port)
1702                                 rxnfc->rule_cnt++;
1703                 err = 0;
1704                 break;
1705         case ETHTOOL_GRXCLSRULE:
1706                 err = -ENOENT;
1707                 policy = idr_find(&chip->policies, fs->location);
1708                 if (policy) {
1709                         memcpy(fs, &policy->fs, sizeof(*fs));
1710                         err = 0;
1711                 }
1712                 break;
1713         case ETHTOOL_GRXCLSRLALL:
1714                 rxnfc->data = 0;
1715                 rxnfc->rule_cnt = 0;
1716                 idr_for_each_entry(&chip->policies, policy, id)
1717                         if (policy->port == port)
1718                                 rule_locs[rxnfc->rule_cnt++] = id;
1719                 err = 0;
1720                 break;
1721         default:
1722                 err = -EOPNOTSUPP;
1723                 break;
1724         }
1725
1726         mv88e6xxx_reg_unlock(chip);
1727
1728         return err;
1729 }
1730
1731 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
1732                                struct ethtool_rxnfc *rxnfc)
1733 {
1734         struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
1735         struct mv88e6xxx_chip *chip = ds->priv;
1736         struct mv88e6xxx_policy *policy;
1737         int err;
1738
1739         mv88e6xxx_reg_lock(chip);
1740
1741         switch (rxnfc->cmd) {
1742         case ETHTOOL_SRXCLSRLINS:
1743                 err = mv88e6xxx_policy_insert(chip, port, fs);
1744                 break;
1745         case ETHTOOL_SRXCLSRLDEL:
1746                 err = -ENOENT;
1747                 policy = idr_remove(&chip->policies, fs->location);
1748                 if (policy) {
1749                         policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
1750                         err = mv88e6xxx_policy_apply(chip, port, policy);
1751                         devm_kfree(chip->dev, policy);
1752                 }
1753                 break;
1754         default:
1755                 err = -EOPNOTSUPP;
1756                 break;
1757         }
1758
1759         mv88e6xxx_reg_unlock(chip);
1760
1761         return err;
1762 }
1763
1764 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
1765                                         u16 vid)
1766 {
1767         const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1768         u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
1769
1770         return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
1771 }
1772
1773 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
1774 {
1775         int port;
1776         int err;
1777
1778         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1779                 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
1780                 if (err)
1781                         return err;
1782         }
1783
1784         return 0;
1785 }
1786
1787 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
1788                                     u16 vid, u8 member)
1789 {
1790         const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1791         struct mv88e6xxx_vtu_entry vlan;
1792         int i, err;
1793
1794         if (!vid)
1795                 return -EOPNOTSUPP;
1796
1797         vlan.vid = vid - 1;
1798         vlan.valid = false;
1799
1800         err = mv88e6xxx_vtu_getnext(chip, &vlan);
1801         if (err)
1802                 return err;
1803
1804         if (vlan.vid != vid || !vlan.valid) {
1805                 memset(&vlan, 0, sizeof(vlan));
1806
1807                 err = mv88e6xxx_atu_new(chip, &vlan.fid);
1808                 if (err)
1809                         return err;
1810
1811                 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1812                         if (i == port)
1813                                 vlan.member[i] = member;
1814                         else
1815                                 vlan.member[i] = non_member;
1816
1817                 vlan.vid = vid;
1818                 vlan.valid = true;
1819
1820                 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1821                 if (err)
1822                         return err;
1823
1824                 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
1825                 if (err)
1826                         return err;
1827         } else if (vlan.member[port] != member) {
1828                 vlan.member[port] = member;
1829
1830                 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1831                 if (err)
1832                         return err;
1833         } else {
1834                 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
1835                          port, vid);
1836         }
1837
1838         return 0;
1839 }
1840
1841 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1842                                     const struct switchdev_obj_port_vlan *vlan)
1843 {
1844         struct mv88e6xxx_chip *chip = ds->priv;
1845         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1846         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1847         u8 member;
1848         u16 vid;
1849
1850         if (!chip->info->max_vid)
1851                 return;
1852
1853         if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1854                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1855         else if (untagged)
1856                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1857         else
1858                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1859
1860         mv88e6xxx_reg_lock(chip);
1861
1862         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1863                 if (mv88e6xxx_port_vlan_join(chip, port, vid, member))
1864                         dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1865                                 vid, untagged ? 'u' : 't');
1866
1867         if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1868                 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
1869                         vlan->vid_end);
1870
1871         mv88e6xxx_reg_unlock(chip);
1872 }
1873
1874 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
1875                                      int port, u16 vid)
1876 {
1877         struct mv88e6xxx_vtu_entry vlan;
1878         int i, err;
1879
1880         if (!vid)
1881                 return -EOPNOTSUPP;
1882
1883         vlan.vid = vid - 1;
1884         vlan.valid = false;
1885
1886         err = mv88e6xxx_vtu_getnext(chip, &vlan);
1887         if (err)
1888                 return err;
1889
1890         /* If the VLAN doesn't exist in hardware or the port isn't a member,
1891          * tell switchdev that this VLAN is likely handled in software.
1892          */
1893         if (vlan.vid != vid || !vlan.valid ||
1894             vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1895                 return -EOPNOTSUPP;
1896
1897         vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1898
1899         /* keep the VLAN unless all ports are excluded */
1900         vlan.valid = false;
1901         for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1902                 if (vlan.member[i] !=
1903                     MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1904                         vlan.valid = true;
1905                         break;
1906                 }
1907         }
1908
1909         err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1910         if (err)
1911                 return err;
1912
1913         return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
1914 }
1915
1916 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1917                                    const struct switchdev_obj_port_vlan *vlan)
1918 {
1919         struct mv88e6xxx_chip *chip = ds->priv;
1920         u16 pvid, vid;
1921         int err = 0;
1922
1923         if (!chip->info->max_vid)
1924                 return -EOPNOTSUPP;
1925
1926         mv88e6xxx_reg_lock(chip);
1927
1928         err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1929         if (err)
1930                 goto unlock;
1931
1932         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1933                 err = mv88e6xxx_port_vlan_leave(chip, port, vid);
1934                 if (err)
1935                         goto unlock;
1936
1937                 if (vid == pvid) {
1938                         err = mv88e6xxx_port_set_pvid(chip, port, 0);
1939                         if (err)
1940                                 goto unlock;
1941                 }
1942         }
1943
1944 unlock:
1945         mv88e6xxx_reg_unlock(chip);
1946
1947         return err;
1948 }
1949
1950 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1951                                   const unsigned char *addr, u16 vid)
1952 {
1953         struct mv88e6xxx_chip *chip = ds->priv;
1954         int err;
1955
1956         mv88e6xxx_reg_lock(chip);
1957         err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1958                                            MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1959         mv88e6xxx_reg_unlock(chip);
1960
1961         return err;
1962 }
1963
1964 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1965                                   const unsigned char *addr, u16 vid)
1966 {
1967         struct mv88e6xxx_chip *chip = ds->priv;
1968         int err;
1969
1970         mv88e6xxx_reg_lock(chip);
1971         err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
1972         mv88e6xxx_reg_unlock(chip);
1973
1974         return err;
1975 }
1976
1977 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
1978                                       u16 fid, u16 vid, int port,
1979                                       dsa_fdb_dump_cb_t *cb, void *data)
1980 {
1981         struct mv88e6xxx_atu_entry addr;
1982         bool is_static;
1983         int err;
1984
1985         addr.state = 0;
1986         eth_broadcast_addr(addr.mac);
1987
1988         do {
1989                 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
1990                 if (err)
1991                         return err;
1992
1993                 if (!addr.state)
1994                         break;
1995
1996                 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
1997                         continue;
1998
1999                 if (!is_unicast_ether_addr(addr.mac))
2000                         continue;
2001
2002                 is_static = (addr.state ==
2003                              MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2004                 err = cb(addr.mac, vid, is_static, data);
2005                 if (err)
2006                         return err;
2007         } while (!is_broadcast_ether_addr(addr.mac));
2008
2009         return err;
2010 }
2011
2012 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2013                                   dsa_fdb_dump_cb_t *cb, void *data)
2014 {
2015         struct mv88e6xxx_vtu_entry vlan;
2016         u16 fid;
2017         int err;
2018
2019         /* Dump port's default Filtering Information Database (VLAN ID 0) */
2020         err = mv88e6xxx_port_get_fid(chip, port, &fid);
2021         if (err)
2022                 return err;
2023
2024         err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2025         if (err)
2026                 return err;
2027
2028         /* Dump VLANs' Filtering Information Databases */
2029         vlan.vid = chip->info->max_vid;
2030         vlan.valid = false;
2031
2032         do {
2033                 err = mv88e6xxx_vtu_getnext(chip, &vlan);
2034                 if (err)
2035                         return err;
2036
2037                 if (!vlan.valid)
2038                         break;
2039
2040                 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2041                                                  cb, data);
2042                 if (err)
2043                         return err;
2044         } while (vlan.vid < chip->info->max_vid);
2045
2046         return err;
2047 }
2048
2049 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2050                                    dsa_fdb_dump_cb_t *cb, void *data)
2051 {
2052         struct mv88e6xxx_chip *chip = ds->priv;
2053         int err;
2054
2055         mv88e6xxx_reg_lock(chip);
2056         err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2057         mv88e6xxx_reg_unlock(chip);
2058
2059         return err;
2060 }
2061
2062 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2063                                 struct net_device *br)
2064 {
2065         struct dsa_switch *ds = chip->ds;
2066         struct dsa_switch_tree *dst = ds->dst;
2067         struct dsa_port *dp;
2068         int err;
2069
2070         list_for_each_entry(dp, &dst->ports, list) {
2071                 if (dp->bridge_dev == br) {
2072                         if (dp->ds == ds) {
2073                                 /* This is a local bridge group member,
2074                                  * remap its Port VLAN Map.
2075                                  */
2076                                 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2077                                 if (err)
2078                                         return err;
2079                         } else {
2080                                 /* This is an external bridge group member,
2081                                  * remap its cross-chip Port VLAN Table entry.
2082                                  */
2083                                 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2084                                                         dp->index);
2085                                 if (err)
2086                                         return err;
2087                         }
2088                 }
2089         }
2090
2091         return 0;
2092 }
2093
2094 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2095                                       struct net_device *br)
2096 {
2097         struct mv88e6xxx_chip *chip = ds->priv;
2098         int err;
2099
2100         mv88e6xxx_reg_lock(chip);
2101         err = mv88e6xxx_bridge_map(chip, br);
2102         mv88e6xxx_reg_unlock(chip);
2103
2104         return err;
2105 }
2106
2107 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2108                                         struct net_device *br)
2109 {
2110         struct mv88e6xxx_chip *chip = ds->priv;
2111
2112         mv88e6xxx_reg_lock(chip);
2113         if (mv88e6xxx_bridge_map(chip, br) ||
2114             mv88e6xxx_port_vlan_map(chip, port))
2115                 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
2116         mv88e6xxx_reg_unlock(chip);
2117 }
2118
2119 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
2120                                            int port, struct net_device *br)
2121 {
2122         struct mv88e6xxx_chip *chip = ds->priv;
2123         int err;
2124
2125         mv88e6xxx_reg_lock(chip);
2126         err = mv88e6xxx_pvt_map(chip, dev, port);
2127         mv88e6xxx_reg_unlock(chip);
2128
2129         return err;
2130 }
2131
2132 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
2133                                              int port, struct net_device *br)
2134 {
2135         struct mv88e6xxx_chip *chip = ds->priv;
2136
2137         mv88e6xxx_reg_lock(chip);
2138         if (mv88e6xxx_pvt_map(chip, dev, port))
2139                 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2140         mv88e6xxx_reg_unlock(chip);
2141 }
2142
2143 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2144 {
2145         if (chip->info->ops->reset)
2146                 return chip->info->ops->reset(chip);
2147
2148         return 0;
2149 }
2150
2151 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2152 {
2153         struct gpio_desc *gpiod = chip->reset;
2154
2155         /* If there is a GPIO connected to the reset pin, toggle it */
2156         if (gpiod) {
2157                 gpiod_set_value_cansleep(gpiod, 1);
2158                 usleep_range(10000, 20000);
2159                 gpiod_set_value_cansleep(gpiod, 0);
2160                 usleep_range(10000, 20000);
2161         }
2162 }
2163
2164 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2165 {
2166         int i, err;
2167
2168         /* Set all ports to the Disabled state */
2169         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2170                 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
2171                 if (err)
2172                         return err;
2173         }
2174
2175         /* Wait for transmit queues to drain,
2176          * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2177          */
2178         usleep_range(2000, 4000);
2179
2180         return 0;
2181 }
2182
2183 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2184 {
2185         int err;
2186
2187         err = mv88e6xxx_disable_ports(chip);
2188         if (err)
2189                 return err;
2190
2191         mv88e6xxx_hardware_reset(chip);
2192
2193         return mv88e6xxx_software_reset(chip);
2194 }
2195
2196 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
2197                                    enum mv88e6xxx_frame_mode frame,
2198                                    enum mv88e6xxx_egress_mode egress, u16 etype)
2199 {
2200         int err;
2201
2202         if (!chip->info->ops->port_set_frame_mode)
2203                 return -EOPNOTSUPP;
2204
2205         err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
2206         if (err)
2207                 return err;
2208
2209         err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2210         if (err)
2211                 return err;
2212
2213         if (chip->info->ops->port_set_ether_type)
2214                 return chip->info->ops->port_set_ether_type(chip, port, etype);
2215
2216         return 0;
2217 }
2218
2219 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2220 {
2221         return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
2222                                        MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2223                                        MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2224 }
2225
2226 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2227 {
2228         return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
2229                                        MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2230                                        MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2231 }
2232
2233 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2234 {
2235         return mv88e6xxx_set_port_mode(chip, port,
2236                                        MV88E6XXX_FRAME_MODE_ETHERTYPE,
2237                                        MV88E6XXX_EGRESS_MODE_ETHERTYPE,
2238                                        ETH_P_EDSA);
2239 }
2240
2241 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2242 {
2243         if (dsa_is_dsa_port(chip->ds, port))
2244                 return mv88e6xxx_set_port_mode_dsa(chip, port);
2245
2246         if (dsa_is_user_port(chip->ds, port))
2247                 return mv88e6xxx_set_port_mode_normal(chip, port);
2248
2249         /* Setup CPU port mode depending on its supported tag format */
2250         if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
2251                 return mv88e6xxx_set_port_mode_dsa(chip, port);
2252
2253         if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
2254                 return mv88e6xxx_set_port_mode_edsa(chip, port);
2255
2256         return -EINVAL;
2257 }
2258
2259 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2260 {
2261         bool message = dsa_is_dsa_port(chip->ds, port);
2262
2263         return mv88e6xxx_port_set_message_port(chip, port, message);
2264 }
2265
2266 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2267 {
2268         struct dsa_switch *ds = chip->ds;
2269         bool flood;
2270
2271         /* Upstream ports flood frames with unknown unicast or multicast DA */
2272         flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port);
2273         if (chip->info->ops->port_set_egress_floods)
2274                 return chip->info->ops->port_set_egress_floods(chip, port,
2275                                                                flood, flood);
2276
2277         return 0;
2278 }
2279
2280 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id)
2281 {
2282         struct mv88e6xxx_port *mvp = dev_id;
2283         struct mv88e6xxx_chip *chip = mvp->chip;
2284         irqreturn_t ret = IRQ_NONE;
2285         int port = mvp->port;
2286         u8 lane;
2287
2288         mv88e6xxx_reg_lock(chip);
2289         lane = mv88e6xxx_serdes_get_lane(chip, port);
2290         if (lane)
2291                 ret = mv88e6xxx_serdes_irq_status(chip, port, lane);
2292         mv88e6xxx_reg_unlock(chip);
2293
2294         return ret;
2295 }
2296
2297 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port,
2298                                         u8 lane)
2299 {
2300         struct mv88e6xxx_port *dev_id = &chip->ports[port];
2301         unsigned int irq;
2302         int err;
2303
2304         /* Nothing to request if this SERDES port has no IRQ */
2305         irq = mv88e6xxx_serdes_irq_mapping(chip, port);
2306         if (!irq)
2307                 return 0;
2308
2309         snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name),
2310                  "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port);
2311
2312         /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */
2313         mv88e6xxx_reg_unlock(chip);
2314         err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn,
2315                                    IRQF_ONESHOT, dev_id->serdes_irq_name,
2316                                    dev_id);
2317         mv88e6xxx_reg_lock(chip);
2318         if (err)
2319                 return err;
2320
2321         dev_id->serdes_irq = irq;
2322
2323         return mv88e6xxx_serdes_irq_enable(chip, port, lane);
2324 }
2325
2326 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port,
2327                                      u8 lane)
2328 {
2329         struct mv88e6xxx_port *dev_id = &chip->ports[port];
2330         unsigned int irq = dev_id->serdes_irq;
2331         int err;
2332
2333         /* Nothing to free if no IRQ has been requested */
2334         if (!irq)
2335                 return 0;
2336
2337         err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
2338
2339         /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */
2340         mv88e6xxx_reg_unlock(chip);
2341         free_irq(irq, dev_id);
2342         mv88e6xxx_reg_lock(chip);
2343
2344         dev_id->serdes_irq = 0;
2345
2346         return err;
2347 }
2348
2349 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2350                                   bool on)
2351 {
2352         u8 lane;
2353         int err;
2354
2355         lane = mv88e6xxx_serdes_get_lane(chip, port);
2356         if (!lane)
2357                 return 0;
2358
2359         if (on) {
2360                 err = mv88e6xxx_serdes_power_up(chip, port, lane);
2361                 if (err)
2362                         return err;
2363
2364                 err = mv88e6xxx_serdes_irq_request(chip, port, lane);
2365         } else {
2366                 err = mv88e6xxx_serdes_irq_free(chip, port, lane);
2367                 if (err)
2368                         return err;
2369
2370                 err = mv88e6xxx_serdes_power_down(chip, port, lane);
2371         }
2372
2373         return err;
2374 }
2375
2376 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
2377 {
2378         struct dsa_switch *ds = chip->ds;
2379         int upstream_port;
2380         int err;
2381
2382         upstream_port = dsa_upstream_port(ds, port);
2383         if (chip->info->ops->port_set_upstream_port) {
2384                 err = chip->info->ops->port_set_upstream_port(chip, port,
2385                                                               upstream_port);
2386                 if (err)
2387                         return err;
2388         }
2389
2390         if (port == upstream_port) {
2391                 if (chip->info->ops->set_cpu_port) {
2392                         err = chip->info->ops->set_cpu_port(chip,
2393                                                             upstream_port);
2394                         if (err)
2395                                 return err;
2396                 }
2397
2398                 if (chip->info->ops->set_egress_port) {
2399                         err = chip->info->ops->set_egress_port(chip,
2400                                                 MV88E6XXX_EGRESS_DIR_INGRESS,
2401                                                 upstream_port);
2402                         if (err)
2403                                 return err;
2404
2405                         err = chip->info->ops->set_egress_port(chip,
2406                                                 MV88E6XXX_EGRESS_DIR_EGRESS,
2407                                                 upstream_port);
2408                         if (err)
2409                                 return err;
2410                 }
2411         }
2412
2413         return 0;
2414 }
2415
2416 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2417 {
2418         struct dsa_switch *ds = chip->ds;
2419         int err;
2420         u16 reg;
2421
2422         chip->ports[port].chip = chip;
2423         chip->ports[port].port = port;
2424
2425         /* MAC Forcing register: don't force link, speed, duplex or flow control
2426          * state to any particular values on physical ports, but force the CPU
2427          * port and all DSA ports to their maximum bandwidth and full duplex.
2428          */
2429         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2430                 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2431                                                SPEED_MAX, DUPLEX_FULL,
2432                                                PAUSE_OFF,
2433                                                PHY_INTERFACE_MODE_NA);
2434         else
2435                 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2436                                                SPEED_UNFORCED, DUPLEX_UNFORCED,
2437                                                PAUSE_ON,
2438                                                PHY_INTERFACE_MODE_NA);
2439         if (err)
2440                 return err;
2441
2442         /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2443          * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2444          * tunneling, determine priority by looking at 802.1p and IP
2445          * priority fields (IP prio has precedence), and set STP state
2446          * to Forwarding.
2447          *
2448          * If this is the CPU link, use DSA or EDSA tagging depending
2449          * on which tagging mode was configured.
2450          *
2451          * If this is a link to another switch, use DSA tagging mode.
2452          *
2453          * If this is the upstream port for this switch, enable
2454          * forwarding of unknown unicasts and multicasts.
2455          */
2456         reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
2457                 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
2458                 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2459         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
2460         if (err)
2461                 return err;
2462
2463         err = mv88e6xxx_setup_port_mode(chip, port);
2464         if (err)
2465                 return err;
2466
2467         err = mv88e6xxx_setup_egress_floods(chip, port);
2468         if (err)
2469                 return err;
2470
2471         /* Port Control 2: don't force a good FCS, set the maximum frame size to
2472          * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2473          * untagged frames on this port, do a destination address lookup on all
2474          * received packets as usual, disable ARP mirroring and don't send a
2475          * copy of all transmitted/received frames on this port to the CPU.
2476          */
2477         err = mv88e6xxx_port_set_map_da(chip, port);
2478         if (err)
2479                 return err;
2480
2481         err = mv88e6xxx_setup_upstream_port(chip, port);
2482         if (err)
2483                 return err;
2484
2485         err = mv88e6xxx_port_set_8021q_mode(chip, port,
2486                                 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
2487         if (err)
2488                 return err;
2489
2490         if (chip->info->ops->port_set_jumbo_size) {
2491                 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
2492                 if (err)
2493                         return err;
2494         }
2495
2496         /* Port Association Vector: when learning source addresses
2497          * of packets, add the address to the address database using
2498          * a port bitmap that has only the bit for this port set and
2499          * the other bits clear.
2500          */
2501         reg = 1 << port;
2502         /* Disable learning for CPU port */
2503         if (dsa_is_cpu_port(ds, port))
2504                 reg = 0;
2505
2506         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
2507                                    reg);
2508         if (err)
2509                 return err;
2510
2511         /* Egress rate control 2: disable egress rate control. */
2512         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
2513                                    0x0000);
2514         if (err)
2515                 return err;
2516
2517         if (chip->info->ops->port_pause_limit) {
2518                 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
2519                 if (err)
2520                         return err;
2521         }
2522
2523         if (chip->info->ops->port_disable_learn_limit) {
2524                 err = chip->info->ops->port_disable_learn_limit(chip, port);
2525                 if (err)
2526                         return err;
2527         }
2528
2529         if (chip->info->ops->port_disable_pri_override) {
2530                 err = chip->info->ops->port_disable_pri_override(chip, port);
2531                 if (err)
2532                         return err;
2533         }
2534
2535         if (chip->info->ops->port_tag_remap) {
2536                 err = chip->info->ops->port_tag_remap(chip, port);
2537                 if (err)
2538                         return err;
2539         }
2540
2541         if (chip->info->ops->port_egress_rate_limiting) {
2542                 err = chip->info->ops->port_egress_rate_limiting(chip, port);
2543                 if (err)
2544                         return err;
2545         }
2546
2547         if (chip->info->ops->port_setup_message_port) {
2548                 err = chip->info->ops->port_setup_message_port(chip, port);
2549                 if (err)
2550                         return err;
2551         }
2552
2553         /* Port based VLAN map: give each port the same default address
2554          * database, and allow bidirectional communication between the
2555          * CPU and DSA port(s), and the other ports.
2556          */
2557         err = mv88e6xxx_port_set_fid(chip, port, 0);
2558         if (err)
2559                 return err;
2560
2561         err = mv88e6xxx_port_vlan_map(chip, port);
2562         if (err)
2563                 return err;
2564
2565         /* Default VLAN ID and priority: don't set a default VLAN
2566          * ID, and set the default packet priority to zero.
2567          */
2568         return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2569 }
2570
2571 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
2572                                  struct phy_device *phydev)
2573 {
2574         struct mv88e6xxx_chip *chip = ds->priv;
2575         int err;
2576
2577         mv88e6xxx_reg_lock(chip);
2578         err = mv88e6xxx_serdes_power(chip, port, true);
2579         mv88e6xxx_reg_unlock(chip);
2580
2581         return err;
2582 }
2583
2584 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
2585 {
2586         struct mv88e6xxx_chip *chip = ds->priv;
2587
2588         mv88e6xxx_reg_lock(chip);
2589         if (mv88e6xxx_serdes_power(chip, port, false))
2590                 dev_err(chip->dev, "failed to power off SERDES\n");
2591         mv88e6xxx_reg_unlock(chip);
2592 }
2593
2594 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2595                                      unsigned int ageing_time)
2596 {
2597         struct mv88e6xxx_chip *chip = ds->priv;
2598         int err;
2599
2600         mv88e6xxx_reg_lock(chip);
2601         err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2602         mv88e6xxx_reg_unlock(chip);
2603
2604         return err;
2605 }
2606
2607 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
2608 {
2609         int err;
2610
2611         /* Initialize the statistics unit */
2612         if (chip->info->ops->stats_set_histogram) {
2613                 err = chip->info->ops->stats_set_histogram(chip);
2614                 if (err)
2615                         return err;
2616         }
2617
2618         return mv88e6xxx_g1_stats_clear(chip);
2619 }
2620
2621 /* Check if the errata has already been applied. */
2622 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
2623 {
2624         int port;
2625         int err;
2626         u16 val;
2627
2628         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2629                 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
2630                 if (err) {
2631                         dev_err(chip->dev,
2632                                 "Error reading hidden register: %d\n", err);
2633                         return false;
2634                 }
2635                 if (val != 0x01c0)
2636                         return false;
2637         }
2638
2639         return true;
2640 }
2641
2642 /* The 6390 copper ports have an errata which require poking magic
2643  * values into undocumented hidden registers and then performing a
2644  * software reset.
2645  */
2646 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
2647 {
2648         int port;
2649         int err;
2650
2651         if (mv88e6390_setup_errata_applied(chip))
2652                 return 0;
2653
2654         /* Set the ports into blocking mode */
2655         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2656                 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
2657                 if (err)
2658                         return err;
2659         }
2660
2661         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2662                 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
2663                 if (err)
2664                         return err;
2665         }
2666
2667         return mv88e6xxx_software_reset(chip);
2668 }
2669
2670 enum mv88e6xxx_devlink_param_id {
2671         MV88E6XXX_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
2672         MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH,
2673 };
2674
2675 static int mv88e6xxx_devlink_param_get(struct dsa_switch *ds, u32 id,
2676                                        struct devlink_param_gset_ctx *ctx)
2677 {
2678         struct mv88e6xxx_chip *chip = ds->priv;
2679         int err;
2680
2681         mv88e6xxx_reg_lock(chip);
2682
2683         switch (id) {
2684         case MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH:
2685                 err = mv88e6xxx_atu_get_hash(chip, &ctx->val.vu8);
2686                 break;
2687         default:
2688                 err = -EOPNOTSUPP;
2689                 break;
2690         }
2691
2692         mv88e6xxx_reg_unlock(chip);
2693
2694         return err;
2695 }
2696
2697 static int mv88e6xxx_devlink_param_set(struct dsa_switch *ds, u32 id,
2698                                        struct devlink_param_gset_ctx *ctx)
2699 {
2700         struct mv88e6xxx_chip *chip = ds->priv;
2701         int err;
2702
2703         mv88e6xxx_reg_lock(chip);
2704
2705         switch (id) {
2706         case MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH:
2707                 err = mv88e6xxx_atu_set_hash(chip, ctx->val.vu8);
2708                 break;
2709         default:
2710                 err = -EOPNOTSUPP;
2711                 break;
2712         }
2713
2714         mv88e6xxx_reg_unlock(chip);
2715
2716         return err;
2717 }
2718
2719 static const struct devlink_param mv88e6xxx_devlink_params[] = {
2720         DSA_DEVLINK_PARAM_DRIVER(MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH,
2721                                  "ATU_hash", DEVLINK_PARAM_TYPE_U8,
2722                                  BIT(DEVLINK_PARAM_CMODE_RUNTIME)),
2723 };
2724
2725 static int mv88e6xxx_setup_devlink_params(struct dsa_switch *ds)
2726 {
2727         return dsa_devlink_params_register(ds, mv88e6xxx_devlink_params,
2728                                            ARRAY_SIZE(mv88e6xxx_devlink_params));
2729 }
2730
2731 static void mv88e6xxx_teardown_devlink_params(struct dsa_switch *ds)
2732 {
2733         dsa_devlink_params_unregister(ds, mv88e6xxx_devlink_params,
2734                                       ARRAY_SIZE(mv88e6xxx_devlink_params));
2735 }
2736
2737 enum mv88e6xxx_devlink_resource_id {
2738         MV88E6XXX_RESOURCE_ID_ATU,
2739         MV88E6XXX_RESOURCE_ID_ATU_BIN_0,
2740         MV88E6XXX_RESOURCE_ID_ATU_BIN_1,
2741         MV88E6XXX_RESOURCE_ID_ATU_BIN_2,
2742         MV88E6XXX_RESOURCE_ID_ATU_BIN_3,
2743 };
2744
2745 static u64 mv88e6xxx_devlink_atu_bin_get(struct mv88e6xxx_chip *chip,
2746                                          u16 bin)
2747 {
2748         u16 occupancy = 0;
2749         int err;
2750
2751         mv88e6xxx_reg_lock(chip);
2752
2753         err = mv88e6xxx_g2_atu_stats_set(chip, MV88E6XXX_G2_ATU_STATS_MODE_ALL,
2754                                          bin);
2755         if (err) {
2756                 dev_err(chip->dev, "failed to set ATU stats kind/bin\n");
2757                 goto unlock;
2758         }
2759
2760         err = mv88e6xxx_g1_atu_get_next(chip, 0);
2761         if (err) {
2762                 dev_err(chip->dev, "failed to perform ATU get next\n");
2763                 goto unlock;
2764         }
2765
2766         err = mv88e6xxx_g2_atu_stats_get(chip, &occupancy);
2767         if (err) {
2768                 dev_err(chip->dev, "failed to get ATU stats\n");
2769                 goto unlock;
2770         }
2771
2772         occupancy &= MV88E6XXX_G2_ATU_STATS_MASK;
2773
2774 unlock:
2775         mv88e6xxx_reg_unlock(chip);
2776
2777         return occupancy;
2778 }
2779
2780 static u64 mv88e6xxx_devlink_atu_bin_0_get(void *priv)
2781 {
2782         struct mv88e6xxx_chip *chip = priv;
2783
2784         return mv88e6xxx_devlink_atu_bin_get(chip,
2785                                              MV88E6XXX_G2_ATU_STATS_BIN_0);
2786 }
2787
2788 static u64 mv88e6xxx_devlink_atu_bin_1_get(void *priv)
2789 {
2790         struct mv88e6xxx_chip *chip = priv;
2791
2792         return mv88e6xxx_devlink_atu_bin_get(chip,
2793                                              MV88E6XXX_G2_ATU_STATS_BIN_1);
2794 }
2795
2796 static u64 mv88e6xxx_devlink_atu_bin_2_get(void *priv)
2797 {
2798         struct mv88e6xxx_chip *chip = priv;
2799
2800         return mv88e6xxx_devlink_atu_bin_get(chip,
2801                                              MV88E6XXX_G2_ATU_STATS_BIN_2);
2802 }
2803
2804 static u64 mv88e6xxx_devlink_atu_bin_3_get(void *priv)
2805 {
2806         struct mv88e6xxx_chip *chip = priv;
2807
2808         return mv88e6xxx_devlink_atu_bin_get(chip,
2809                                              MV88E6XXX_G2_ATU_STATS_BIN_3);
2810 }
2811
2812 static u64 mv88e6xxx_devlink_atu_get(void *priv)
2813 {
2814         return mv88e6xxx_devlink_atu_bin_0_get(priv) +
2815                 mv88e6xxx_devlink_atu_bin_1_get(priv) +
2816                 mv88e6xxx_devlink_atu_bin_2_get(priv) +
2817                 mv88e6xxx_devlink_atu_bin_3_get(priv);
2818 }
2819
2820 static int mv88e6xxx_setup_devlink_resources(struct dsa_switch *ds)
2821 {
2822         struct devlink_resource_size_params size_params;
2823         struct mv88e6xxx_chip *chip = ds->priv;
2824         int err;
2825
2826         devlink_resource_size_params_init(&size_params,
2827                                           mv88e6xxx_num_macs(chip),
2828                                           mv88e6xxx_num_macs(chip),
2829                                           1, DEVLINK_RESOURCE_UNIT_ENTRY);
2830
2831         err = dsa_devlink_resource_register(ds, "ATU",
2832                                             mv88e6xxx_num_macs(chip),
2833                                             MV88E6XXX_RESOURCE_ID_ATU,
2834                                             DEVLINK_RESOURCE_ID_PARENT_TOP,
2835                                             &size_params);
2836         if (err)
2837                 goto out;
2838
2839         devlink_resource_size_params_init(&size_params,
2840                                           mv88e6xxx_num_macs(chip) / 4,
2841                                           mv88e6xxx_num_macs(chip) / 4,
2842                                           1, DEVLINK_RESOURCE_UNIT_ENTRY);
2843
2844         err = dsa_devlink_resource_register(ds, "ATU_bin_0",
2845                                             mv88e6xxx_num_macs(chip) / 4,
2846                                             MV88E6XXX_RESOURCE_ID_ATU_BIN_0,
2847                                             MV88E6XXX_RESOURCE_ID_ATU,
2848                                             &size_params);
2849         if (err)
2850                 goto out;
2851
2852         err = dsa_devlink_resource_register(ds, "ATU_bin_1",
2853                                             mv88e6xxx_num_macs(chip) / 4,
2854                                             MV88E6XXX_RESOURCE_ID_ATU_BIN_1,
2855                                             MV88E6XXX_RESOURCE_ID_ATU,
2856                                             &size_params);
2857         if (err)
2858                 goto out;
2859
2860         err = dsa_devlink_resource_register(ds, "ATU_bin_2",
2861                                             mv88e6xxx_num_macs(chip) / 4,
2862                                             MV88E6XXX_RESOURCE_ID_ATU_BIN_2,
2863                                             MV88E6XXX_RESOURCE_ID_ATU,
2864                                             &size_params);
2865         if (err)
2866                 goto out;
2867
2868         err = dsa_devlink_resource_register(ds, "ATU_bin_3",
2869                                             mv88e6xxx_num_macs(chip) / 4,
2870                                             MV88E6XXX_RESOURCE_ID_ATU_BIN_3,
2871                                             MV88E6XXX_RESOURCE_ID_ATU,
2872                                             &size_params);
2873         if (err)
2874                 goto out;
2875
2876         dsa_devlink_resource_occ_get_register(ds,
2877                                               MV88E6XXX_RESOURCE_ID_ATU,
2878                                               mv88e6xxx_devlink_atu_get,
2879                                               chip);
2880
2881         dsa_devlink_resource_occ_get_register(ds,
2882                                               MV88E6XXX_RESOURCE_ID_ATU_BIN_0,
2883                                               mv88e6xxx_devlink_atu_bin_0_get,
2884                                               chip);
2885
2886         dsa_devlink_resource_occ_get_register(ds,
2887                                               MV88E6XXX_RESOURCE_ID_ATU_BIN_1,
2888                                               mv88e6xxx_devlink_atu_bin_1_get,
2889                                               chip);
2890
2891         dsa_devlink_resource_occ_get_register(ds,
2892                                               MV88E6XXX_RESOURCE_ID_ATU_BIN_2,
2893                                               mv88e6xxx_devlink_atu_bin_2_get,
2894                                               chip);
2895
2896         dsa_devlink_resource_occ_get_register(ds,
2897                                               MV88E6XXX_RESOURCE_ID_ATU_BIN_3,
2898                                               mv88e6xxx_devlink_atu_bin_3_get,
2899                                               chip);
2900
2901         return 0;
2902
2903 out:
2904         dsa_devlink_resources_unregister(ds);
2905         return err;
2906 }
2907
2908 static void mv88e6xxx_teardown(struct dsa_switch *ds)
2909 {
2910         mv88e6xxx_teardown_devlink_params(ds);
2911         dsa_devlink_resources_unregister(ds);
2912 }
2913
2914 static int mv88e6xxx_setup(struct dsa_switch *ds)
2915 {
2916         struct mv88e6xxx_chip *chip = ds->priv;
2917         u8 cmode;
2918         int err;
2919         int i;
2920
2921         chip->ds = ds;
2922         ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2923
2924         mv88e6xxx_reg_lock(chip);
2925
2926         if (chip->info->ops->setup_errata) {
2927                 err = chip->info->ops->setup_errata(chip);
2928                 if (err)
2929                         goto unlock;
2930         }
2931
2932         /* Cache the cmode of each port. */
2933         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2934                 if (chip->info->ops->port_get_cmode) {
2935                         err = chip->info->ops->port_get_cmode(chip, i, &cmode);
2936                         if (err)
2937                                 goto unlock;
2938
2939                         chip->ports[i].cmode = cmode;
2940                 }
2941         }
2942
2943         /* Setup Switch Port Registers */
2944         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2945                 if (dsa_is_unused_port(ds, i))
2946                         continue;
2947
2948                 /* Prevent the use of an invalid port. */
2949                 if (mv88e6xxx_is_invalid_port(chip, i)) {
2950                         dev_err(chip->dev, "port %d is invalid\n", i);
2951                         err = -EINVAL;
2952                         goto unlock;
2953                 }
2954
2955                 err = mv88e6xxx_setup_port(chip, i);
2956                 if (err)
2957                         goto unlock;
2958         }
2959
2960         err = mv88e6xxx_irl_setup(chip);
2961         if (err)
2962                 goto unlock;
2963
2964         err = mv88e6xxx_mac_setup(chip);
2965         if (err)
2966                 goto unlock;
2967
2968         err = mv88e6xxx_phy_setup(chip);
2969         if (err)
2970                 goto unlock;
2971
2972         err = mv88e6xxx_vtu_setup(chip);
2973         if (err)
2974                 goto unlock;
2975
2976         err = mv88e6xxx_pvt_setup(chip);
2977         if (err)
2978                 goto unlock;
2979
2980         err = mv88e6xxx_atu_setup(chip);
2981         if (err)
2982                 goto unlock;
2983
2984         err = mv88e6xxx_broadcast_setup(chip, 0);
2985         if (err)
2986                 goto unlock;
2987
2988         err = mv88e6xxx_pot_setup(chip);
2989         if (err)
2990                 goto unlock;
2991
2992         err = mv88e6xxx_rmu_setup(chip);
2993         if (err)
2994                 goto unlock;
2995
2996         err = mv88e6xxx_rsvd2cpu_setup(chip);
2997         if (err)
2998                 goto unlock;
2999
3000         err = mv88e6xxx_trunk_setup(chip);
3001         if (err)
3002                 goto unlock;
3003
3004         err = mv88e6xxx_devmap_setup(chip);
3005         if (err)
3006                 goto unlock;
3007
3008         err = mv88e6xxx_pri_setup(chip);
3009         if (err)
3010                 goto unlock;
3011
3012         /* Setup PTP Hardware Clock and timestamping */
3013         if (chip->info->ptp_support) {
3014                 err = mv88e6xxx_ptp_setup(chip);
3015                 if (err)
3016                         goto unlock;
3017
3018                 err = mv88e6xxx_hwtstamp_setup(chip);
3019                 if (err)
3020                         goto unlock;
3021         }
3022
3023         err = mv88e6xxx_stats_setup(chip);
3024         if (err)
3025                 goto unlock;
3026
3027 unlock:
3028         mv88e6xxx_reg_unlock(chip);
3029
3030         if (err)
3031                 return err;
3032
3033         /* Have to be called without holding the register lock, since
3034          * they take the devlink lock, and we later take the locks in
3035          * the reverse order when getting/setting parameters or
3036          * resource occupancy.
3037          */
3038         err = mv88e6xxx_setup_devlink_resources(ds);
3039         if (err)
3040                 return err;
3041
3042         err = mv88e6xxx_setup_devlink_params(ds);
3043         if (err)
3044                 dsa_devlink_resources_unregister(ds);
3045
3046         return err;
3047 }
3048
3049 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3050 {
3051         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3052         struct mv88e6xxx_chip *chip = mdio_bus->chip;
3053         u16 val;
3054         int err;
3055
3056         if (!chip->info->ops->phy_read)
3057                 return -EOPNOTSUPP;
3058
3059         mv88e6xxx_reg_lock(chip);
3060         err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3061         mv88e6xxx_reg_unlock(chip);
3062
3063         if (reg == MII_PHYSID2) {
3064                 /* Some internal PHYs don't have a model number. */
3065                 if (chip->info->family != MV88E6XXX_FAMILY_6165)
3066                         /* Then there is the 6165 family. It gets is
3067                          * PHYs correct. But it can also have two
3068                          * SERDES interfaces in the PHY address
3069                          * space. And these don't have a model
3070                          * number. But they are not PHYs, so we don't
3071                          * want to give them something a PHY driver
3072                          * will recognise.
3073                          *
3074                          * Use the mv88e6390 family model number
3075                          * instead, for anything which really could be
3076                          * a PHY,
3077                          */
3078                         if (!(val & 0x3f0))
3079                                 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
3080         }
3081
3082         return err ? err : val;
3083 }
3084
3085 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3086 {
3087         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3088         struct mv88e6xxx_chip *chip = mdio_bus->chip;
3089         int err;
3090
3091         if (!chip->info->ops->phy_write)
3092                 return -EOPNOTSUPP;
3093
3094         mv88e6xxx_reg_lock(chip);
3095         err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3096         mv88e6xxx_reg_unlock(chip);
3097
3098         return err;
3099 }
3100
3101 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3102                                    struct device_node *np,
3103                                    bool external)
3104 {
3105         static int index;
3106         struct mv88e6xxx_mdio_bus *mdio_bus;
3107         struct mii_bus *bus;
3108         int err;
3109
3110         if (external) {
3111                 mv88e6xxx_reg_lock(chip);
3112                 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
3113                 mv88e6xxx_reg_unlock(chip);
3114
3115                 if (err)
3116                         return err;
3117         }
3118
3119         bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
3120         if (!bus)
3121                 return -ENOMEM;
3122
3123         mdio_bus = bus->priv;
3124         mdio_bus->bus = bus;
3125         mdio_bus->chip = chip;
3126         INIT_LIST_HEAD(&mdio_bus->list);
3127         mdio_bus->external = external;
3128
3129         if (np) {
3130                 bus->name = np->full_name;
3131                 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3132         } else {
3133                 bus->name = "mv88e6xxx SMI";
3134                 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3135         }
3136
3137         bus->read = mv88e6xxx_mdio_read;
3138         bus->write = mv88e6xxx_mdio_write;
3139         bus->parent = chip->dev;
3140
3141         if (!external) {
3142                 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3143                 if (err)
3144                         return err;
3145         }
3146
3147         err = of_mdiobus_register(bus, np);
3148         if (err) {
3149                 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3150                 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3151                 return err;
3152         }
3153
3154         if (external)
3155                 list_add_tail(&mdio_bus->list, &chip->mdios);
3156         else
3157                 list_add(&mdio_bus->list, &chip->mdios);
3158
3159         return 0;
3160 }
3161
3162 static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
3163         { .compatible = "marvell,mv88e6xxx-mdio-external",
3164           .data = (void *)true },
3165         { },
3166 };
3167
3168 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3169
3170 {
3171         struct mv88e6xxx_mdio_bus *mdio_bus;
3172         struct mii_bus *bus;
3173
3174         list_for_each_entry(mdio_bus, &chip->mdios, list) {
3175                 bus = mdio_bus->bus;
3176
3177                 if (!mdio_bus->external)
3178                         mv88e6xxx_g2_irq_mdio_free(chip, bus);
3179
3180                 mdiobus_unregister(bus);
3181         }
3182 }
3183
3184 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
3185                                     struct device_node *np)
3186 {
3187         const struct of_device_id *match;
3188         struct device_node *child;
3189         int err;
3190
3191         /* Always register one mdio bus for the internal/default mdio
3192          * bus. This maybe represented in the device tree, but is
3193          * optional.
3194          */
3195         child = of_get_child_by_name(np, "mdio");
3196         err = mv88e6xxx_mdio_register(chip, child, false);
3197         if (err)
3198                 return err;
3199
3200         /* Walk the device tree, and see if there are any other nodes
3201          * which say they are compatible with the external mdio
3202          * bus.
3203          */
3204         for_each_available_child_of_node(np, child) {
3205                 match = of_match_node(mv88e6xxx_mdio_external_match, child);
3206                 if (match) {
3207                         err = mv88e6xxx_mdio_register(chip, child, true);
3208                         if (err) {
3209                                 mv88e6xxx_mdios_unregister(chip);
3210                                 of_node_put(child);
3211                                 return err;
3212                         }
3213                 }
3214         }
3215
3216         return 0;
3217 }
3218
3219 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3220 {
3221         struct mv88e6xxx_chip *chip = ds->priv;
3222
3223         return chip->eeprom_len;
3224 }
3225
3226 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3227                                 struct ethtool_eeprom *eeprom, u8 *data)
3228 {
3229         struct mv88e6xxx_chip *chip = ds->priv;
3230         int err;
3231
3232         if (!chip->info->ops->get_eeprom)
3233                 return -EOPNOTSUPP;
3234
3235         mv88e6xxx_reg_lock(chip);
3236         err = chip->info->ops->get_eeprom(chip, eeprom, data);
3237         mv88e6xxx_reg_unlock(chip);
3238
3239         if (err)
3240                 return err;
3241
3242         eeprom->magic = 0xc3ec4951;
3243
3244         return 0;
3245 }
3246
3247 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3248                                 struct ethtool_eeprom *eeprom, u8 *data)
3249 {
3250         struct mv88e6xxx_chip *chip = ds->priv;
3251         int err;
3252
3253         if (!chip->info->ops->set_eeprom)
3254                 return -EOPNOTSUPP;
3255
3256         if (eeprom->magic != 0xc3ec4951)
3257                 return -EINVAL;
3258
3259         mv88e6xxx_reg_lock(chip);
3260         err = chip->info->ops->set_eeprom(chip, eeprom, data);
3261         mv88e6xxx_reg_unlock(chip);
3262
3263         return err;
3264 }
3265
3266 static const struct mv88e6xxx_ops mv88e6085_ops = {
3267         /* MV88E6XXX_FAMILY_6097 */
3268         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3269         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3270         .irl_init_all = mv88e6352_g2_irl_init_all,
3271         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3272         .phy_read = mv88e6185_phy_ppu_read,
3273         .phy_write = mv88e6185_phy_ppu_write,
3274         .port_set_link = mv88e6xxx_port_set_link,
3275         .port_set_duplex = mv88e6xxx_port_set_duplex,
3276         .port_set_speed = mv88e6185_port_set_speed,
3277         .port_tag_remap = mv88e6095_port_tag_remap,
3278         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3279         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3280         .port_set_ether_type = mv88e6351_port_set_ether_type,
3281         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3282         .port_pause_limit = mv88e6097_port_pause_limit,
3283         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3284         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3285         .port_link_state = mv88e6352_port_link_state,
3286         .port_get_cmode = mv88e6185_port_get_cmode,
3287         .port_setup_message_port = mv88e6xxx_setup_message_port,
3288         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3289         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3290         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3291         .stats_get_strings = mv88e6095_stats_get_strings,
3292         .stats_get_stats = mv88e6095_stats_get_stats,
3293         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3294         .set_egress_port = mv88e6095_g1_set_egress_port,
3295         .watchdog_ops = &mv88e6097_watchdog_ops,
3296         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3297         .pot_clear = mv88e6xxx_g2_pot_clear,
3298         .ppu_enable = mv88e6185_g1_ppu_enable,
3299         .ppu_disable = mv88e6185_g1_ppu_disable,
3300         .reset = mv88e6185_g1_reset,
3301         .rmu_disable = mv88e6085_g1_rmu_disable,
3302         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3303         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3304         .phylink_validate = mv88e6185_phylink_validate,
3305 };
3306
3307 static const struct mv88e6xxx_ops mv88e6095_ops = {
3308         /* MV88E6XXX_FAMILY_6095 */
3309         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3310         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3311         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3312         .phy_read = mv88e6185_phy_ppu_read,
3313         .phy_write = mv88e6185_phy_ppu_write,
3314         .port_set_link = mv88e6xxx_port_set_link,
3315         .port_set_duplex = mv88e6xxx_port_set_duplex,
3316         .port_set_speed = mv88e6185_port_set_speed,
3317         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3318         .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3319         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3320         .port_link_state = mv88e6185_port_link_state,
3321         .port_get_cmode = mv88e6185_port_get_cmode,
3322         .port_setup_message_port = mv88e6xxx_setup_message_port,
3323         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3324         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3325         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3326         .stats_get_strings = mv88e6095_stats_get_strings,
3327         .stats_get_stats = mv88e6095_stats_get_stats,
3328         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3329         .ppu_enable = mv88e6185_g1_ppu_enable,
3330         .ppu_disable = mv88e6185_g1_ppu_disable,
3331         .reset = mv88e6185_g1_reset,
3332         .vtu_getnext = mv88e6185_g1_vtu_getnext,
3333         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3334         .phylink_validate = mv88e6185_phylink_validate,
3335 };
3336
3337 static const struct mv88e6xxx_ops mv88e6097_ops = {
3338         /* MV88E6XXX_FAMILY_6097 */
3339         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3340         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3341         .irl_init_all = mv88e6352_g2_irl_init_all,
3342         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3343         .phy_read = mv88e6xxx_g2_smi_phy_read,
3344         .phy_write = mv88e6xxx_g2_smi_phy_write,
3345         .port_set_link = mv88e6xxx_port_set_link,
3346         .port_set_duplex = mv88e6xxx_port_set_duplex,
3347         .port_set_speed = mv88e6185_port_set_speed,
3348         .port_tag_remap = mv88e6095_port_tag_remap,
3349         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3350         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3351         .port_set_ether_type = mv88e6351_port_set_ether_type,
3352         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3353         .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3354         .port_pause_limit = mv88e6097_port_pause_limit,
3355         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3356         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3357         .port_link_state = mv88e6352_port_link_state,
3358         .port_get_cmode = mv88e6185_port_get_cmode,
3359         .port_setup_message_port = mv88e6xxx_setup_message_port,
3360         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3361         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3362         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3363         .stats_get_strings = mv88e6095_stats_get_strings,
3364         .stats_get_stats = mv88e6095_stats_get_stats,
3365         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3366         .set_egress_port = mv88e6095_g1_set_egress_port,
3367         .watchdog_ops = &mv88e6097_watchdog_ops,
3368         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3369         .pot_clear = mv88e6xxx_g2_pot_clear,
3370         .reset = mv88e6352_g1_reset,
3371         .rmu_disable = mv88e6085_g1_rmu_disable,
3372         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3373         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3374         .phylink_validate = mv88e6185_phylink_validate,
3375 };
3376
3377 static const struct mv88e6xxx_ops mv88e6123_ops = {
3378         /* MV88E6XXX_FAMILY_6165 */
3379         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3380         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3381         .irl_init_all = mv88e6352_g2_irl_init_all,
3382         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3383         .phy_read = mv88e6xxx_g2_smi_phy_read,
3384         .phy_write = mv88e6xxx_g2_smi_phy_write,
3385         .port_set_link = mv88e6xxx_port_set_link,
3386         .port_set_duplex = mv88e6xxx_port_set_duplex,
3387         .port_set_speed = mv88e6185_port_set_speed,
3388         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3389         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3390         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3391         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3392         .port_link_state = mv88e6352_port_link_state,
3393         .port_get_cmode = mv88e6185_port_get_cmode,
3394         .port_setup_message_port = mv88e6xxx_setup_message_port,
3395         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3396         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3397         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3398         .stats_get_strings = mv88e6095_stats_get_strings,
3399         .stats_get_stats = mv88e6095_stats_get_stats,
3400         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3401         .set_egress_port = mv88e6095_g1_set_egress_port,
3402         .watchdog_ops = &mv88e6097_watchdog_ops,
3403         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3404         .pot_clear = mv88e6xxx_g2_pot_clear,
3405         .reset = mv88e6352_g1_reset,
3406         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3407         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3408         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3409         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3410         .phylink_validate = mv88e6185_phylink_validate,
3411 };
3412
3413 static const struct mv88e6xxx_ops mv88e6131_ops = {
3414         /* MV88E6XXX_FAMILY_6185 */
3415         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3416         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3417         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3418         .phy_read = mv88e6185_phy_ppu_read,
3419         .phy_write = mv88e6185_phy_ppu_write,
3420         .port_set_link = mv88e6xxx_port_set_link,
3421         .port_set_duplex = mv88e6xxx_port_set_duplex,
3422         .port_set_speed = mv88e6185_port_set_speed,
3423         .port_tag_remap = mv88e6095_port_tag_remap,
3424         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3425         .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3426         .port_set_ether_type = mv88e6351_port_set_ether_type,
3427         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3428         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3429         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3430         .port_pause_limit = mv88e6097_port_pause_limit,
3431         .port_set_pause = mv88e6185_port_set_pause,
3432         .port_link_state = mv88e6352_port_link_state,
3433         .port_get_cmode = mv88e6185_port_get_cmode,
3434         .port_setup_message_port = mv88e6xxx_setup_message_port,
3435         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3436         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3437         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3438         .stats_get_strings = mv88e6095_stats_get_strings,
3439         .stats_get_stats = mv88e6095_stats_get_stats,
3440         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3441         .set_egress_port = mv88e6095_g1_set_egress_port,
3442         .watchdog_ops = &mv88e6097_watchdog_ops,
3443         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3444         .ppu_enable = mv88e6185_g1_ppu_enable,
3445         .set_cascade_port = mv88e6185_g1_set_cascade_port,
3446         .ppu_disable = mv88e6185_g1_ppu_disable,
3447         .reset = mv88e6185_g1_reset,
3448         .vtu_getnext = mv88e6185_g1_vtu_getnext,
3449         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3450         .phylink_validate = mv88e6185_phylink_validate,
3451 };
3452
3453 static const struct mv88e6xxx_ops mv88e6141_ops = {
3454         /* MV88E6XXX_FAMILY_6341 */
3455         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3456         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3457         .irl_init_all = mv88e6352_g2_irl_init_all,
3458         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3459         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3460         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3461         .phy_read = mv88e6xxx_g2_smi_phy_read,
3462         .phy_write = mv88e6xxx_g2_smi_phy_write,
3463         .port_set_link = mv88e6xxx_port_set_link,
3464         .port_set_duplex = mv88e6xxx_port_set_duplex,
3465         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3466         .port_set_speed = mv88e6341_port_set_speed,
3467         .port_max_speed_mode = mv88e6341_port_max_speed_mode,
3468         .port_tag_remap = mv88e6095_port_tag_remap,
3469         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3470         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3471         .port_set_ether_type = mv88e6351_port_set_ether_type,
3472         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3473         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3474         .port_pause_limit = mv88e6097_port_pause_limit,
3475         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3476         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3477         .port_link_state = mv88e6352_port_link_state,
3478         .port_get_cmode = mv88e6352_port_get_cmode,
3479         .port_set_cmode = mv88e6341_port_set_cmode,
3480         .port_setup_message_port = mv88e6xxx_setup_message_port,
3481         .stats_snapshot = mv88e6390_g1_stats_snapshot,
3482         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3483         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3484         .stats_get_strings = mv88e6320_stats_get_strings,
3485         .stats_get_stats = mv88e6390_stats_get_stats,
3486         .set_cpu_port = mv88e6390_g1_set_cpu_port,
3487         .set_egress_port = mv88e6390_g1_set_egress_port,
3488         .watchdog_ops = &mv88e6390_watchdog_ops,
3489         .mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
3490         .pot_clear = mv88e6xxx_g2_pot_clear,
3491         .reset = mv88e6352_g1_reset,
3492         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3493         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3494         .serdes_power = mv88e6390_serdes_power,
3495         .serdes_get_lane = mv88e6341_serdes_get_lane,
3496         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3497         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3498         .serdes_irq_status = mv88e6390_serdes_irq_status,
3499         .gpio_ops = &mv88e6352_gpio_ops,
3500         .phylink_validate = mv88e6341_phylink_validate,
3501 };
3502
3503 static const struct mv88e6xxx_ops mv88e6161_ops = {
3504         /* MV88E6XXX_FAMILY_6165 */
3505         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3506         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3507         .irl_init_all = mv88e6352_g2_irl_init_all,
3508         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3509         .phy_read = mv88e6xxx_g2_smi_phy_read,
3510         .phy_write = mv88e6xxx_g2_smi_phy_write,
3511         .port_set_link = mv88e6xxx_port_set_link,
3512         .port_set_duplex = mv88e6xxx_port_set_duplex,
3513         .port_set_speed = mv88e6185_port_set_speed,
3514         .port_tag_remap = mv88e6095_port_tag_remap,
3515         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3516         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3517         .port_set_ether_type = mv88e6351_port_set_ether_type,
3518         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3519         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3520         .port_pause_limit = mv88e6097_port_pause_limit,
3521         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3522         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3523         .port_link_state = mv88e6352_port_link_state,
3524         .port_get_cmode = mv88e6185_port_get_cmode,
3525         .port_setup_message_port = mv88e6xxx_setup_message_port,
3526         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3527         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3528         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3529         .stats_get_strings = mv88e6095_stats_get_strings,
3530         .stats_get_stats = mv88e6095_stats_get_stats,
3531         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3532         .set_egress_port = mv88e6095_g1_set_egress_port,
3533         .watchdog_ops = &mv88e6097_watchdog_ops,
3534         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3535         .pot_clear = mv88e6xxx_g2_pot_clear,
3536         .reset = mv88e6352_g1_reset,
3537         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3538         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3539         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3540         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3541         .avb_ops = &mv88e6165_avb_ops,
3542         .ptp_ops = &mv88e6165_ptp_ops,
3543         .phylink_validate = mv88e6185_phylink_validate,
3544 };
3545
3546 static const struct mv88e6xxx_ops mv88e6165_ops = {
3547         /* MV88E6XXX_FAMILY_6165 */
3548         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3549         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3550         .irl_init_all = mv88e6352_g2_irl_init_all,
3551         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3552         .phy_read = mv88e6165_phy_read,
3553         .phy_write = mv88e6165_phy_write,
3554         .port_set_link = mv88e6xxx_port_set_link,
3555         .port_set_duplex = mv88e6xxx_port_set_duplex,
3556         .port_set_speed = mv88e6185_port_set_speed,
3557         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3558         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3559         .port_link_state = mv88e6352_port_link_state,
3560         .port_get_cmode = mv88e6185_port_get_cmode,
3561         .port_setup_message_port = mv88e6xxx_setup_message_port,
3562         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3563         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3564         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3565         .stats_get_strings = mv88e6095_stats_get_strings,
3566         .stats_get_stats = mv88e6095_stats_get_stats,
3567         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3568         .set_egress_port = mv88e6095_g1_set_egress_port,
3569         .watchdog_ops = &mv88e6097_watchdog_ops,
3570         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3571         .pot_clear = mv88e6xxx_g2_pot_clear,
3572         .reset = mv88e6352_g1_reset,
3573         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3574         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3575         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3576         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3577         .avb_ops = &mv88e6165_avb_ops,
3578         .ptp_ops = &mv88e6165_ptp_ops,
3579         .phylink_validate = mv88e6185_phylink_validate,
3580 };
3581
3582 static const struct mv88e6xxx_ops mv88e6171_ops = {
3583         /* MV88E6XXX_FAMILY_6351 */
3584         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3585         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3586         .irl_init_all = mv88e6352_g2_irl_init_all,
3587         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3588         .phy_read = mv88e6xxx_g2_smi_phy_read,
3589         .phy_write = mv88e6xxx_g2_smi_phy_write,
3590         .port_set_link = mv88e6xxx_port_set_link,
3591         .port_set_duplex = mv88e6xxx_port_set_duplex,
3592         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3593         .port_set_speed = mv88e6185_port_set_speed,
3594         .port_tag_remap = mv88e6095_port_tag_remap,
3595         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3596         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3597         .port_set_ether_type = mv88e6351_port_set_ether_type,
3598         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3599         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3600         .port_pause_limit = mv88e6097_port_pause_limit,
3601         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3602         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3603         .port_link_state = mv88e6352_port_link_state,
3604         .port_get_cmode = mv88e6352_port_get_cmode,
3605         .port_setup_message_port = mv88e6xxx_setup_message_port,
3606         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3607         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3608         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3609         .stats_get_strings = mv88e6095_stats_get_strings,
3610         .stats_get_stats = mv88e6095_stats_get_stats,
3611         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3612         .set_egress_port = mv88e6095_g1_set_egress_port,
3613         .watchdog_ops = &mv88e6097_watchdog_ops,
3614         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3615         .pot_clear = mv88e6xxx_g2_pot_clear,
3616         .reset = mv88e6352_g1_reset,
3617         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3618         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3619         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3620         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3621         .phylink_validate = mv88e6185_phylink_validate,
3622 };
3623
3624 static const struct mv88e6xxx_ops mv88e6172_ops = {
3625         /* MV88E6XXX_FAMILY_6352 */
3626         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3627         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3628         .irl_init_all = mv88e6352_g2_irl_init_all,
3629         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3630         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3631         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3632         .phy_read = mv88e6xxx_g2_smi_phy_read,
3633         .phy_write = mv88e6xxx_g2_smi_phy_write,
3634         .port_set_link = mv88e6xxx_port_set_link,
3635         .port_set_duplex = mv88e6xxx_port_set_duplex,
3636         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3637         .port_set_speed = mv88e6352_port_set_speed,
3638         .port_tag_remap = mv88e6095_port_tag_remap,
3639         .port_set_policy = mv88e6352_port_set_policy,
3640         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3641         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3642         .port_set_ether_type = mv88e6351_port_set_ether_type,
3643         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3644         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3645         .port_pause_limit = mv88e6097_port_pause_limit,
3646         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3647         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3648         .port_link_state = mv88e6352_port_link_state,
3649         .port_get_cmode = mv88e6352_port_get_cmode,
3650         .port_setup_message_port = mv88e6xxx_setup_message_port,
3651         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3652         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3653         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3654         .stats_get_strings = mv88e6095_stats_get_strings,
3655         .stats_get_stats = mv88e6095_stats_get_stats,
3656         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3657         .set_egress_port = mv88e6095_g1_set_egress_port,
3658         .watchdog_ops = &mv88e6097_watchdog_ops,
3659         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3660         .pot_clear = mv88e6xxx_g2_pot_clear,
3661         .reset = mv88e6352_g1_reset,
3662         .rmu_disable = mv88e6352_g1_rmu_disable,
3663         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3664         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3665         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3666         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3667         .serdes_get_lane = mv88e6352_serdes_get_lane,
3668         .serdes_power = mv88e6352_serdes_power,
3669         .gpio_ops = &mv88e6352_gpio_ops,
3670         .phylink_validate = mv88e6352_phylink_validate,
3671 };
3672
3673 static const struct mv88e6xxx_ops mv88e6175_ops = {
3674         /* MV88E6XXX_FAMILY_6351 */
3675         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3676         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3677         .irl_init_all = mv88e6352_g2_irl_init_all,
3678         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3679         .phy_read = mv88e6xxx_g2_smi_phy_read,
3680         .phy_write = mv88e6xxx_g2_smi_phy_write,
3681         .port_set_link = mv88e6xxx_port_set_link,
3682         .port_set_duplex = mv88e6xxx_port_set_duplex,
3683         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3684         .port_set_speed = mv88e6185_port_set_speed,
3685         .port_tag_remap = mv88e6095_port_tag_remap,
3686         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3687         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3688         .port_set_ether_type = mv88e6351_port_set_ether_type,
3689         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3690         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3691         .port_pause_limit = mv88e6097_port_pause_limit,
3692         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3693         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3694         .port_link_state = mv88e6352_port_link_state,
3695         .port_get_cmode = mv88e6352_port_get_cmode,
3696         .port_setup_message_port = mv88e6xxx_setup_message_port,
3697         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3698         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3699         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3700         .stats_get_strings = mv88e6095_stats_get_strings,
3701         .stats_get_stats = mv88e6095_stats_get_stats,
3702         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3703         .set_egress_port = mv88e6095_g1_set_egress_port,
3704         .watchdog_ops = &mv88e6097_watchdog_ops,
3705         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3706         .pot_clear = mv88e6xxx_g2_pot_clear,
3707         .reset = mv88e6352_g1_reset,
3708         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3709         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3710         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3711         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3712         .phylink_validate = mv88e6185_phylink_validate,
3713 };
3714
3715 static const struct mv88e6xxx_ops mv88e6176_ops = {
3716         /* MV88E6XXX_FAMILY_6352 */
3717         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3718         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3719         .irl_init_all = mv88e6352_g2_irl_init_all,
3720         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3721         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3722         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3723         .phy_read = mv88e6xxx_g2_smi_phy_read,
3724         .phy_write = mv88e6xxx_g2_smi_phy_write,
3725         .port_set_link = mv88e6xxx_port_set_link,
3726         .port_set_duplex = mv88e6xxx_port_set_duplex,
3727         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3728         .port_set_speed = mv88e6352_port_set_speed,
3729         .port_tag_remap = mv88e6095_port_tag_remap,
3730         .port_set_policy = mv88e6352_port_set_policy,
3731         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3732         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3733         .port_set_ether_type = mv88e6351_port_set_ether_type,
3734         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3735         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3736         .port_pause_limit = mv88e6097_port_pause_limit,
3737         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3738         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3739         .port_link_state = mv88e6352_port_link_state,
3740         .port_get_cmode = mv88e6352_port_get_cmode,
3741         .port_setup_message_port = mv88e6xxx_setup_message_port,
3742         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3743         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3744         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3745         .stats_get_strings = mv88e6095_stats_get_strings,
3746         .stats_get_stats = mv88e6095_stats_get_stats,
3747         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3748         .set_egress_port = mv88e6095_g1_set_egress_port,
3749         .watchdog_ops = &mv88e6097_watchdog_ops,
3750         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3751         .pot_clear = mv88e6xxx_g2_pot_clear,
3752         .reset = mv88e6352_g1_reset,
3753         .rmu_disable = mv88e6352_g1_rmu_disable,
3754         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3755         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3756         .vtu_getnext = mv88e6352_g1_vtu_getnext,
3757         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3758         .serdes_get_lane = mv88e6352_serdes_get_lane,
3759         .serdes_power = mv88e6352_serdes_power,
3760         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
3761         .serdes_irq_enable = mv88e6352_serdes_irq_enable,
3762         .serdes_irq_status = mv88e6352_serdes_irq_status,
3763         .gpio_ops = &mv88e6352_gpio_ops,
3764         .phylink_validate = mv88e6352_phylink_validate,
3765 };
3766
3767 static const struct mv88e6xxx_ops mv88e6185_ops = {
3768         /* MV88E6XXX_FAMILY_6185 */
3769         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3770         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3771         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3772         .phy_read = mv88e6185_phy_ppu_read,
3773         .phy_write = mv88e6185_phy_ppu_write,
3774         .port_set_link = mv88e6xxx_port_set_link,
3775         .port_set_duplex = mv88e6xxx_port_set_duplex,
3776         .port_set_speed = mv88e6185_port_set_speed,
3777         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3778         .port_set_egress_floods = mv88e6185_port_set_egress_floods,
3779         .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3780         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
3781         .port_set_pause = mv88e6185_port_set_pause,
3782         .port_link_state = mv88e6185_port_link_state,
3783         .port_get_cmode = mv88e6185_port_get_cmode,
3784         .port_setup_message_port = mv88e6xxx_setup_message_port,
3785         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3786         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3787         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3788         .stats_get_strings = mv88e6095_stats_get_strings,
3789         .stats_get_stats = mv88e6095_stats_get_stats,
3790         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3791         .set_egress_port = mv88e6095_g1_set_egress_port,
3792         .watchdog_ops = &mv88e6097_watchdog_ops,
3793         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3794         .set_cascade_port = mv88e6185_g1_set_cascade_port,
3795         .ppu_enable = mv88e6185_g1_ppu_enable,
3796         .ppu_disable = mv88e6185_g1_ppu_disable,
3797         .reset = mv88e6185_g1_reset,
3798         .vtu_getnext = mv88e6185_g1_vtu_getnext,
3799         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3800         .phylink_validate = mv88e6185_phylink_validate,
3801 };
3802
3803 static const struct mv88e6xxx_ops mv88e6190_ops = {
3804         /* MV88E6XXX_FAMILY_6390 */
3805         .setup_errata = mv88e6390_setup_errata,
3806         .irl_init_all = mv88e6390_g2_irl_init_all,
3807         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3808         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3809         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3810         .phy_read = mv88e6xxx_g2_smi_phy_read,
3811         .phy_write = mv88e6xxx_g2_smi_phy_write,
3812         .port_set_link = mv88e6xxx_port_set_link,
3813         .port_set_duplex = mv88e6xxx_port_set_duplex,
3814         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3815         .port_set_speed = mv88e6390_port_set_speed,
3816         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3817         .port_tag_remap = mv88e6390_port_tag_remap,
3818         .port_set_policy = mv88e6352_port_set_policy,
3819         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3820         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3821         .port_set_ether_type = mv88e6351_port_set_ether_type,
3822         .port_pause_limit = mv88e6390_port_pause_limit,
3823         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3824         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3825         .port_link_state = mv88e6352_port_link_state,
3826         .port_get_cmode = mv88e6352_port_get_cmode,
3827         .port_set_cmode = mv88e6390_port_set_cmode,
3828         .port_setup_message_port = mv88e6xxx_setup_message_port,
3829         .stats_snapshot = mv88e6390_g1_stats_snapshot,
3830         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3831         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3832         .stats_get_strings = mv88e6320_stats_get_strings,
3833         .stats_get_stats = mv88e6390_stats_get_stats,
3834         .set_cpu_port = mv88e6390_g1_set_cpu_port,
3835         .set_egress_port = mv88e6390_g1_set_egress_port,
3836         .watchdog_ops = &mv88e6390_watchdog_ops,
3837         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3838         .pot_clear = mv88e6xxx_g2_pot_clear,
3839         .reset = mv88e6352_g1_reset,
3840         .rmu_disable = mv88e6390_g1_rmu_disable,
3841         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3842         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3843         .vtu_getnext = mv88e6390_g1_vtu_getnext,
3844         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3845         .serdes_power = mv88e6390_serdes_power,
3846         .serdes_get_lane = mv88e6390_serdes_get_lane,
3847         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3848         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3849         .serdes_irq_status = mv88e6390_serdes_irq_status,
3850         .serdes_get_strings = mv88e6390_serdes_get_strings,
3851         .serdes_get_stats = mv88e6390_serdes_get_stats,
3852         .phylink_validate = mv88e6390_phylink_validate,
3853         .gpio_ops = &mv88e6352_gpio_ops,
3854         .phylink_validate = mv88e6390_phylink_validate,
3855 };
3856
3857 static const struct mv88e6xxx_ops mv88e6190x_ops = {
3858         /* MV88E6XXX_FAMILY_6390 */
3859         .setup_errata = mv88e6390_setup_errata,
3860         .irl_init_all = mv88e6390_g2_irl_init_all,
3861         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3862         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3863         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3864         .phy_read = mv88e6xxx_g2_smi_phy_read,
3865         .phy_write = mv88e6xxx_g2_smi_phy_write,
3866         .port_set_link = mv88e6xxx_port_set_link,
3867         .port_set_duplex = mv88e6xxx_port_set_duplex,
3868         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3869         .port_set_speed = mv88e6390x_port_set_speed,
3870         .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
3871         .port_tag_remap = mv88e6390_port_tag_remap,
3872         .port_set_policy = mv88e6352_port_set_policy,
3873         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3874         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3875         .port_set_ether_type = mv88e6351_port_set_ether_type,
3876         .port_pause_limit = mv88e6390_port_pause_limit,
3877         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3878         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3879         .port_link_state = mv88e6352_port_link_state,
3880         .port_get_cmode = mv88e6352_port_get_cmode,
3881         .port_set_cmode = mv88e6390x_port_set_cmode,
3882         .port_setup_message_port = mv88e6xxx_setup_message_port,
3883         .stats_snapshot = mv88e6390_g1_stats_snapshot,
3884         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3885         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3886         .stats_get_strings = mv88e6320_stats_get_strings,
3887         .stats_get_stats = mv88e6390_stats_get_stats,
3888         .set_cpu_port = mv88e6390_g1_set_cpu_port,
3889         .set_egress_port = mv88e6390_g1_set_egress_port,
3890         .watchdog_ops = &mv88e6390_watchdog_ops,
3891         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3892         .pot_clear = mv88e6xxx_g2_pot_clear,
3893         .reset = mv88e6352_g1_reset,
3894         .rmu_disable = mv88e6390_g1_rmu_disable,
3895         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3896         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3897         .vtu_getnext = mv88e6390_g1_vtu_getnext,
3898         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3899         .serdes_power = mv88e6390_serdes_power,
3900         .serdes_get_lane = mv88e6390x_serdes_get_lane,
3901         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3902         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3903         .serdes_irq_status = mv88e6390_serdes_irq_status,
3904         .serdes_get_strings = mv88e6390_serdes_get_strings,
3905         .serdes_get_stats = mv88e6390_serdes_get_stats,
3906         .phylink_validate = mv88e6390_phylink_validate,
3907         .gpio_ops = &mv88e6352_gpio_ops,
3908         .phylink_validate = mv88e6390x_phylink_validate,
3909 };
3910
3911 static const struct mv88e6xxx_ops mv88e6191_ops = {
3912         /* MV88E6XXX_FAMILY_6390 */
3913         .setup_errata = mv88e6390_setup_errata,
3914         .irl_init_all = mv88e6390_g2_irl_init_all,
3915         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3916         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3917         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3918         .phy_read = mv88e6xxx_g2_smi_phy_read,
3919         .phy_write = mv88e6xxx_g2_smi_phy_write,
3920         .port_set_link = mv88e6xxx_port_set_link,
3921         .port_set_duplex = mv88e6xxx_port_set_duplex,
3922         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3923         .port_set_speed = mv88e6390_port_set_speed,
3924         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
3925         .port_tag_remap = mv88e6390_port_tag_remap,
3926         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3927         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3928         .port_set_ether_type = mv88e6351_port_set_ether_type,
3929         .port_pause_limit = mv88e6390_port_pause_limit,
3930         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3931         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3932         .port_link_state = mv88e6352_port_link_state,
3933         .port_get_cmode = mv88e6352_port_get_cmode,
3934         .port_set_cmode = mv88e6390_port_set_cmode,
3935         .port_setup_message_port = mv88e6xxx_setup_message_port,
3936         .stats_snapshot = mv88e6390_g1_stats_snapshot,
3937         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3938         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3939         .stats_get_strings = mv88e6320_stats_get_strings,
3940         .stats_get_stats = mv88e6390_stats_get_stats,
3941         .set_cpu_port = mv88e6390_g1_set_cpu_port,
3942         .set_egress_port = mv88e6390_g1_set_egress_port,
3943         .watchdog_ops = &mv88e6390_watchdog_ops,
3944         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3945         .pot_clear = mv88e6xxx_g2_pot_clear,
3946         .reset = mv88e6352_g1_reset,
3947         .rmu_disable = mv88e6390_g1_rmu_disable,
3948         .atu_get_hash = mv88e6165_g1_atu_get_hash,
3949         .atu_set_hash = mv88e6165_g1_atu_set_hash,
3950         .vtu_getnext = mv88e6390_g1_vtu_getnext,
3951         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3952         .serdes_power = mv88e6390_serdes_power,
3953         .serdes_get_lane = mv88e6390_serdes_get_lane,
3954         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
3955         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
3956         .serdes_irq_status = mv88e6390_serdes_irq_status,
3957         .serdes_get_strings = mv88e6390_serdes_get_strings,
3958         .serdes_get_stats = mv88e6390_serdes_get_stats,
3959         .phylink_validate = mv88e6390_phylink_validate,
3960         .avb_ops = &mv88e6390_avb_ops,
3961         .ptp_ops = &mv88e6352_ptp_ops,
3962         .phylink_validate = mv88e6390_phylink_validate,
3963 };
3964
3965 static const struct mv88e6xxx_ops mv88e6240_ops = {
3966         /* MV88E6XXX_FAMILY_6352 */
3967         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3968         .ip_pri_map = mv88e6085_g1_ip_pri_map,
3969         .irl_init_all = mv88e6352_g2_irl_init_all,
3970         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3971         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3972         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3973         .phy_read = mv88e6xxx_g2_smi_phy_read,
3974         .phy_write = mv88e6xxx_g2_smi_phy_write,
3975         .port_set_link = mv88e6xxx_port_set_link,
3976         .port_set_duplex = mv88e6xxx_port_set_duplex,
3977         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3978         .port_set_speed = mv88e6352_port_set_speed,
3979         .port_tag_remap = mv88e6095_port_tag_remap,
3980         .port_set_policy = mv88e6352_port_set_policy,
3981         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3982         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
3983         .port_set_ether_type = mv88e6351_port_set_ether_type,
3984         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3985         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3986         .port_pause_limit = mv88e6097_port_pause_limit,
3987         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3988         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3989         .port_link_state = mv88e6352_port_link_state,
3990         .port_get_cmode = mv88e6352_port_get_cmode,
3991         .port_setup_message_port = mv88e6xxx_setup_message_port,
3992         .stats_snapshot = mv88e6320_g1_stats_snapshot,
3993         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3994         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3995         .stats_get_strings = mv88e6095_stats_get_strings,
3996         .stats_get_stats = mv88e6095_stats_get_stats,
3997         .set_cpu_port = mv88e6095_g1_set_cpu_port,
3998         .set_egress_port = mv88e6095_g1_set_egress_port,
3999         .watchdog_ops = &mv88e6097_watchdog_ops,
4000         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4001         .pot_clear = mv88e6xxx_g2_pot_clear,
4002         .reset = mv88e6352_g1_reset,
4003         .rmu_disable = mv88e6352_g1_rmu_disable,
4004         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4005         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4006         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4007         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4008         .serdes_get_lane = mv88e6352_serdes_get_lane,
4009         .serdes_power = mv88e6352_serdes_power,
4010         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4011         .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4012         .serdes_irq_status = mv88e6352_serdes_irq_status,
4013         .gpio_ops = &mv88e6352_gpio_ops,
4014         .avb_ops = &mv88e6352_avb_ops,
4015         .ptp_ops = &mv88e6352_ptp_ops,
4016         .phylink_validate = mv88e6352_phylink_validate,
4017 };
4018
4019 static const struct mv88e6xxx_ops mv88e6250_ops = {
4020         /* MV88E6XXX_FAMILY_6250 */
4021         .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
4022         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4023         .irl_init_all = mv88e6352_g2_irl_init_all,
4024         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4025         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4026         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4027         .phy_read = mv88e6xxx_g2_smi_phy_read,
4028         .phy_write = mv88e6xxx_g2_smi_phy_write,
4029         .port_set_link = mv88e6xxx_port_set_link,
4030         .port_set_duplex = mv88e6xxx_port_set_duplex,
4031         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4032         .port_set_speed = mv88e6250_port_set_speed,
4033         .port_tag_remap = mv88e6095_port_tag_remap,
4034         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4035         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4036         .port_set_ether_type = mv88e6351_port_set_ether_type,
4037         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4038         .port_pause_limit = mv88e6097_port_pause_limit,
4039         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4040         .port_link_state = mv88e6250_port_link_state,
4041         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4042         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4043         .stats_get_sset_count = mv88e6250_stats_get_sset_count,
4044         .stats_get_strings = mv88e6250_stats_get_strings,
4045         .stats_get_stats = mv88e6250_stats_get_stats,
4046         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4047         .set_egress_port = mv88e6095_g1_set_egress_port,
4048         .watchdog_ops = &mv88e6250_watchdog_ops,
4049         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4050         .pot_clear = mv88e6xxx_g2_pot_clear,
4051         .reset = mv88e6250_g1_reset,
4052         .vtu_getnext = mv88e6250_g1_vtu_getnext,
4053         .vtu_loadpurge = mv88e6250_g1_vtu_loadpurge,
4054         .avb_ops = &mv88e6352_avb_ops,
4055         .ptp_ops = &mv88e6250_ptp_ops,
4056         .phylink_validate = mv88e6065_phylink_validate,
4057 };
4058
4059 static const struct mv88e6xxx_ops mv88e6290_ops = {
4060         /* MV88E6XXX_FAMILY_6390 */
4061         .setup_errata = mv88e6390_setup_errata,
4062         .irl_init_all = mv88e6390_g2_irl_init_all,
4063         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4064         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4065         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4066         .phy_read = mv88e6xxx_g2_smi_phy_read,
4067         .phy_write = mv88e6xxx_g2_smi_phy_write,
4068         .port_set_link = mv88e6xxx_port_set_link,
4069         .port_set_duplex = mv88e6xxx_port_set_duplex,
4070         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4071         .port_set_speed = mv88e6390_port_set_speed,
4072         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4073         .port_tag_remap = mv88e6390_port_tag_remap,
4074         .port_set_policy = mv88e6352_port_set_policy,
4075         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4076         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4077         .port_set_ether_type = mv88e6351_port_set_ether_type,
4078         .port_pause_limit = mv88e6390_port_pause_limit,
4079         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4080         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4081         .port_link_state = mv88e6352_port_link_state,
4082         .port_get_cmode = mv88e6352_port_get_cmode,
4083         .port_set_cmode = mv88e6390_port_set_cmode,
4084         .port_setup_message_port = mv88e6xxx_setup_message_port,
4085         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4086         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4087         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4088         .stats_get_strings = mv88e6320_stats_get_strings,
4089         .stats_get_stats = mv88e6390_stats_get_stats,
4090         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4091         .set_egress_port = mv88e6390_g1_set_egress_port,
4092         .watchdog_ops = &mv88e6390_watchdog_ops,
4093         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4094         .pot_clear = mv88e6xxx_g2_pot_clear,
4095         .reset = mv88e6352_g1_reset,
4096         .rmu_disable = mv88e6390_g1_rmu_disable,
4097         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4098         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4099         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4100         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4101         .serdes_power = mv88e6390_serdes_power,
4102         .serdes_get_lane = mv88e6390_serdes_get_lane,
4103         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4104         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4105         .serdes_irq_status = mv88e6390_serdes_irq_status,
4106         .serdes_get_strings = mv88e6390_serdes_get_strings,
4107         .serdes_get_stats = mv88e6390_serdes_get_stats,
4108         .phylink_validate = mv88e6390_phylink_validate,
4109         .gpio_ops = &mv88e6352_gpio_ops,
4110         .avb_ops = &mv88e6390_avb_ops,
4111         .ptp_ops = &mv88e6352_ptp_ops,
4112         .phylink_validate = mv88e6390_phylink_validate,
4113 };
4114
4115 static const struct mv88e6xxx_ops mv88e6320_ops = {
4116         /* MV88E6XXX_FAMILY_6320 */
4117         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4118         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4119         .irl_init_all = mv88e6352_g2_irl_init_all,
4120         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4121         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4122         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4123         .phy_read = mv88e6xxx_g2_smi_phy_read,
4124         .phy_write = mv88e6xxx_g2_smi_phy_write,
4125         .port_set_link = mv88e6xxx_port_set_link,
4126         .port_set_duplex = mv88e6xxx_port_set_duplex,
4127         .port_set_speed = mv88e6185_port_set_speed,
4128         .port_tag_remap = mv88e6095_port_tag_remap,
4129         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4130         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4131         .port_set_ether_type = mv88e6351_port_set_ether_type,
4132         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4133         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4134         .port_pause_limit = mv88e6097_port_pause_limit,
4135         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4136         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4137         .port_link_state = mv88e6352_port_link_state,
4138         .port_get_cmode = mv88e6352_port_get_cmode,
4139         .port_setup_message_port = mv88e6xxx_setup_message_port,
4140         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4141         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4142         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4143         .stats_get_strings = mv88e6320_stats_get_strings,
4144         .stats_get_stats = mv88e6320_stats_get_stats,
4145         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4146         .set_egress_port = mv88e6095_g1_set_egress_port,
4147         .watchdog_ops = &mv88e6390_watchdog_ops,
4148         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4149         .pot_clear = mv88e6xxx_g2_pot_clear,
4150         .reset = mv88e6352_g1_reset,
4151         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4152         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4153         .gpio_ops = &mv88e6352_gpio_ops,
4154         .avb_ops = &mv88e6352_avb_ops,
4155         .ptp_ops = &mv88e6352_ptp_ops,
4156         .phylink_validate = mv88e6185_phylink_validate,
4157 };
4158
4159 static const struct mv88e6xxx_ops mv88e6321_ops = {
4160         /* MV88E6XXX_FAMILY_6320 */
4161         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4162         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4163         .irl_init_all = mv88e6352_g2_irl_init_all,
4164         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4165         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4166         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4167         .phy_read = mv88e6xxx_g2_smi_phy_read,
4168         .phy_write = mv88e6xxx_g2_smi_phy_write,
4169         .port_set_link = mv88e6xxx_port_set_link,
4170         .port_set_duplex = mv88e6xxx_port_set_duplex,
4171         .port_set_speed = mv88e6185_port_set_speed,
4172         .port_tag_remap = mv88e6095_port_tag_remap,
4173         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4174         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4175         .port_set_ether_type = mv88e6351_port_set_ether_type,
4176         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4177         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4178         .port_pause_limit = mv88e6097_port_pause_limit,
4179         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4180         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4181         .port_link_state = mv88e6352_port_link_state,
4182         .port_get_cmode = mv88e6352_port_get_cmode,
4183         .port_setup_message_port = mv88e6xxx_setup_message_port,
4184         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4185         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4186         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4187         .stats_get_strings = mv88e6320_stats_get_strings,
4188         .stats_get_stats = mv88e6320_stats_get_stats,
4189         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4190         .set_egress_port = mv88e6095_g1_set_egress_port,
4191         .watchdog_ops = &mv88e6390_watchdog_ops,
4192         .reset = mv88e6352_g1_reset,
4193         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4194         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4195         .gpio_ops = &mv88e6352_gpio_ops,
4196         .avb_ops = &mv88e6352_avb_ops,
4197         .ptp_ops = &mv88e6352_ptp_ops,
4198         .phylink_validate = mv88e6185_phylink_validate,
4199 };
4200
4201 static const struct mv88e6xxx_ops mv88e6341_ops = {
4202         /* MV88E6XXX_FAMILY_6341 */
4203         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4204         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4205         .irl_init_all = mv88e6352_g2_irl_init_all,
4206         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4207         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4208         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4209         .phy_read = mv88e6xxx_g2_smi_phy_read,
4210         .phy_write = mv88e6xxx_g2_smi_phy_write,
4211         .port_set_link = mv88e6xxx_port_set_link,
4212         .port_set_duplex = mv88e6xxx_port_set_duplex,
4213         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4214         .port_set_speed = mv88e6341_port_set_speed,
4215         .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4216         .port_tag_remap = mv88e6095_port_tag_remap,
4217         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4218         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4219         .port_set_ether_type = mv88e6351_port_set_ether_type,
4220         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4221         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4222         .port_pause_limit = mv88e6097_port_pause_limit,
4223         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4224         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4225         .port_link_state = mv88e6352_port_link_state,
4226         .port_get_cmode = mv88e6352_port_get_cmode,
4227         .port_set_cmode = mv88e6341_port_set_cmode,
4228         .port_setup_message_port = mv88e6xxx_setup_message_port,
4229         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4230         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4231         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4232         .stats_get_strings = mv88e6320_stats_get_strings,
4233         .stats_get_stats = mv88e6390_stats_get_stats,
4234         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4235         .set_egress_port = mv88e6390_g1_set_egress_port,
4236         .watchdog_ops = &mv88e6390_watchdog_ops,
4237         .mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
4238         .pot_clear = mv88e6xxx_g2_pot_clear,
4239         .reset = mv88e6352_g1_reset,
4240         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4241         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4242         .serdes_power = mv88e6390_serdes_power,
4243         .serdes_get_lane = mv88e6341_serdes_get_lane,
4244         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4245         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4246         .serdes_irq_status = mv88e6390_serdes_irq_status,
4247         .gpio_ops = &mv88e6352_gpio_ops,
4248         .avb_ops = &mv88e6390_avb_ops,
4249         .ptp_ops = &mv88e6352_ptp_ops,
4250         .phylink_validate = mv88e6341_phylink_validate,
4251 };
4252
4253 static const struct mv88e6xxx_ops mv88e6350_ops = {
4254         /* MV88E6XXX_FAMILY_6351 */
4255         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4256         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4257         .irl_init_all = mv88e6352_g2_irl_init_all,
4258         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4259         .phy_read = mv88e6xxx_g2_smi_phy_read,
4260         .phy_write = mv88e6xxx_g2_smi_phy_write,
4261         .port_set_link = mv88e6xxx_port_set_link,
4262         .port_set_duplex = mv88e6xxx_port_set_duplex,
4263         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4264         .port_set_speed = mv88e6185_port_set_speed,
4265         .port_tag_remap = mv88e6095_port_tag_remap,
4266         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4267         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4268         .port_set_ether_type = mv88e6351_port_set_ether_type,
4269         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4270         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4271         .port_pause_limit = mv88e6097_port_pause_limit,
4272         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4273         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4274         .port_link_state = mv88e6352_port_link_state,
4275         .port_get_cmode = mv88e6352_port_get_cmode,
4276         .port_setup_message_port = mv88e6xxx_setup_message_port,
4277         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4278         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4279         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4280         .stats_get_strings = mv88e6095_stats_get_strings,
4281         .stats_get_stats = mv88e6095_stats_get_stats,
4282         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4283         .set_egress_port = mv88e6095_g1_set_egress_port,
4284         .watchdog_ops = &mv88e6097_watchdog_ops,
4285         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4286         .pot_clear = mv88e6xxx_g2_pot_clear,
4287         .reset = mv88e6352_g1_reset,
4288         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4289         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4290         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4291         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4292         .phylink_validate = mv88e6185_phylink_validate,
4293 };
4294
4295 static const struct mv88e6xxx_ops mv88e6351_ops = {
4296         /* MV88E6XXX_FAMILY_6351 */
4297         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4298         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4299         .irl_init_all = mv88e6352_g2_irl_init_all,
4300         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4301         .phy_read = mv88e6xxx_g2_smi_phy_read,
4302         .phy_write = mv88e6xxx_g2_smi_phy_write,
4303         .port_set_link = mv88e6xxx_port_set_link,
4304         .port_set_duplex = mv88e6xxx_port_set_duplex,
4305         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4306         .port_set_speed = mv88e6185_port_set_speed,
4307         .port_tag_remap = mv88e6095_port_tag_remap,
4308         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4309         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4310         .port_set_ether_type = mv88e6351_port_set_ether_type,
4311         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4312         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4313         .port_pause_limit = mv88e6097_port_pause_limit,
4314         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4315         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4316         .port_link_state = mv88e6352_port_link_state,
4317         .port_get_cmode = mv88e6352_port_get_cmode,
4318         .port_setup_message_port = mv88e6xxx_setup_message_port,
4319         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4320         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4321         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4322         .stats_get_strings = mv88e6095_stats_get_strings,
4323         .stats_get_stats = mv88e6095_stats_get_stats,
4324         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4325         .set_egress_port = mv88e6095_g1_set_egress_port,
4326         .watchdog_ops = &mv88e6097_watchdog_ops,
4327         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4328         .pot_clear = mv88e6xxx_g2_pot_clear,
4329         .reset = mv88e6352_g1_reset,
4330         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4331         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4332         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4333         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4334         .avb_ops = &mv88e6352_avb_ops,
4335         .ptp_ops = &mv88e6352_ptp_ops,
4336         .phylink_validate = mv88e6185_phylink_validate,
4337 };
4338
4339 static const struct mv88e6xxx_ops mv88e6352_ops = {
4340         /* MV88E6XXX_FAMILY_6352 */
4341         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4342         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4343         .irl_init_all = mv88e6352_g2_irl_init_all,
4344         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4345         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4346         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4347         .phy_read = mv88e6xxx_g2_smi_phy_read,
4348         .phy_write = mv88e6xxx_g2_smi_phy_write,
4349         .port_set_link = mv88e6xxx_port_set_link,
4350         .port_set_duplex = mv88e6xxx_port_set_duplex,
4351         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4352         .port_set_speed = mv88e6352_port_set_speed,
4353         .port_tag_remap = mv88e6095_port_tag_remap,
4354         .port_set_policy = mv88e6352_port_set_policy,
4355         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4356         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4357         .port_set_ether_type = mv88e6351_port_set_ether_type,
4358         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4359         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4360         .port_pause_limit = mv88e6097_port_pause_limit,
4361         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4362         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4363         .port_link_state = mv88e6352_port_link_state,
4364         .port_get_cmode = mv88e6352_port_get_cmode,
4365         .port_setup_message_port = mv88e6xxx_setup_message_port,
4366         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4367         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4368         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4369         .stats_get_strings = mv88e6095_stats_get_strings,
4370         .stats_get_stats = mv88e6095_stats_get_stats,
4371         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4372         .set_egress_port = mv88e6095_g1_set_egress_port,
4373         .watchdog_ops = &mv88e6097_watchdog_ops,
4374         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4375         .pot_clear = mv88e6xxx_g2_pot_clear,
4376         .reset = mv88e6352_g1_reset,
4377         .rmu_disable = mv88e6352_g1_rmu_disable,
4378         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4379         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4380         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4381         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4382         .serdes_get_lane = mv88e6352_serdes_get_lane,
4383         .serdes_power = mv88e6352_serdes_power,
4384         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4385         .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4386         .serdes_irq_status = mv88e6352_serdes_irq_status,
4387         .gpio_ops = &mv88e6352_gpio_ops,
4388         .avb_ops = &mv88e6352_avb_ops,
4389         .ptp_ops = &mv88e6352_ptp_ops,
4390         .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
4391         .serdes_get_strings = mv88e6352_serdes_get_strings,
4392         .serdes_get_stats = mv88e6352_serdes_get_stats,
4393         .phylink_validate = mv88e6352_phylink_validate,
4394 };
4395
4396 static const struct mv88e6xxx_ops mv88e6390_ops = {
4397         /* MV88E6XXX_FAMILY_6390 */
4398         .setup_errata = mv88e6390_setup_errata,
4399         .irl_init_all = mv88e6390_g2_irl_init_all,
4400         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4401         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4402         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4403         .phy_read = mv88e6xxx_g2_smi_phy_read,
4404         .phy_write = mv88e6xxx_g2_smi_phy_write,
4405         .port_set_link = mv88e6xxx_port_set_link,
4406         .port_set_duplex = mv88e6xxx_port_set_duplex,
4407         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4408         .port_set_speed = mv88e6390_port_set_speed,
4409         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4410         .port_tag_remap = mv88e6390_port_tag_remap,
4411         .port_set_policy = mv88e6352_port_set_policy,
4412         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4413         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4414         .port_set_ether_type = mv88e6351_port_set_ether_type,
4415         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4416         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4417         .port_pause_limit = mv88e6390_port_pause_limit,
4418         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4419         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4420         .port_link_state = mv88e6352_port_link_state,
4421         .port_get_cmode = mv88e6352_port_get_cmode,
4422         .port_set_cmode = mv88e6390_port_set_cmode,
4423         .port_setup_message_port = mv88e6xxx_setup_message_port,
4424         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4425         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4426         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4427         .stats_get_strings = mv88e6320_stats_get_strings,
4428         .stats_get_stats = mv88e6390_stats_get_stats,
4429         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4430         .set_egress_port = mv88e6390_g1_set_egress_port,
4431         .watchdog_ops = &mv88e6390_watchdog_ops,
4432         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4433         .pot_clear = mv88e6xxx_g2_pot_clear,
4434         .reset = mv88e6352_g1_reset,
4435         .rmu_disable = mv88e6390_g1_rmu_disable,
4436         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4437         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4438         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4439         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4440         .serdes_power = mv88e6390_serdes_power,
4441         .serdes_get_lane = mv88e6390_serdes_get_lane,
4442         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4443         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4444         .serdes_irq_status = mv88e6390_serdes_irq_status,
4445         .gpio_ops = &mv88e6352_gpio_ops,
4446         .avb_ops = &mv88e6390_avb_ops,
4447         .ptp_ops = &mv88e6352_ptp_ops,
4448         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4449         .serdes_get_strings = mv88e6390_serdes_get_strings,
4450         .serdes_get_stats = mv88e6390_serdes_get_stats,
4451         .phylink_validate = mv88e6390_phylink_validate,
4452 };
4453
4454 static const struct mv88e6xxx_ops mv88e6390x_ops = {
4455         /* MV88E6XXX_FAMILY_6390 */
4456         .setup_errata = mv88e6390_setup_errata,
4457         .irl_init_all = mv88e6390_g2_irl_init_all,
4458         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4459         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4460         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4461         .phy_read = mv88e6xxx_g2_smi_phy_read,
4462         .phy_write = mv88e6xxx_g2_smi_phy_write,
4463         .port_set_link = mv88e6xxx_port_set_link,
4464         .port_set_duplex = mv88e6xxx_port_set_duplex,
4465         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4466         .port_set_speed = mv88e6390x_port_set_speed,
4467         .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4468         .port_tag_remap = mv88e6390_port_tag_remap,
4469         .port_set_policy = mv88e6352_port_set_policy,
4470         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4471         .port_set_egress_floods = mv88e6352_port_set_egress_floods,
4472         .port_set_ether_type = mv88e6351_port_set_ether_type,
4473         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4474         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4475         .port_pause_limit = mv88e6390_port_pause_limit,
4476         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4477         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4478         .port_link_state = mv88e6352_port_link_state,
4479         .port_get_cmode = mv88e6352_port_get_cmode,
4480         .port_set_cmode = mv88e6390x_port_set_cmode,
4481         .port_setup_message_port = mv88e6xxx_setup_message_port,
4482         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4483         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4484         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4485         .stats_get_strings = mv88e6320_stats_get_strings,
4486         .stats_get_stats = mv88e6390_stats_get_stats,
4487         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4488         .set_egress_port = mv88e6390_g1_set_egress_port,
4489         .watchdog_ops = &mv88e6390_watchdog_ops,
4490         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4491         .pot_clear = mv88e6xxx_g2_pot_clear,
4492         .reset = mv88e6352_g1_reset,
4493         .rmu_disable = mv88e6390_g1_rmu_disable,
4494         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4495         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4496         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4497         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4498         .serdes_power = mv88e6390_serdes_power,
4499         .serdes_get_lane = mv88e6390x_serdes_get_lane,
4500         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4501         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4502         .serdes_irq_status = mv88e6390_serdes_irq_status,
4503         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4504         .serdes_get_strings = mv88e6390_serdes_get_strings,
4505         .serdes_get_stats = mv88e6390_serdes_get_stats,
4506         .gpio_ops = &mv88e6352_gpio_ops,
4507         .avb_ops = &mv88e6390_avb_ops,
4508         .ptp_ops = &mv88e6352_ptp_ops,
4509         .phylink_validate = mv88e6390x_phylink_validate,
4510 };
4511
4512 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
4513         [MV88E6085] = {
4514                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
4515                 .family = MV88E6XXX_FAMILY_6097,
4516                 .name = "Marvell 88E6085",
4517                 .num_databases = 4096,
4518                 .num_macs = 8192,
4519                 .num_ports = 10,
4520                 .num_internal_phys = 5,
4521                 .max_vid = 4095,
4522                 .port_base_addr = 0x10,
4523                 .phy_base_addr = 0x0,
4524                 .global1_addr = 0x1b,
4525                 .global2_addr = 0x1c,
4526                 .age_time_coeff = 15000,
4527                 .g1_irqs = 8,
4528                 .g2_irqs = 10,
4529                 .atu_move_port_mask = 0xf,
4530                 .pvt = true,
4531                 .multi_chip = true,
4532                 .tag_protocol = DSA_TAG_PROTO_DSA,
4533                 .ops = &mv88e6085_ops,
4534         },
4535
4536         [MV88E6095] = {
4537                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
4538                 .family = MV88E6XXX_FAMILY_6095,
4539                 .name = "Marvell 88E6095/88E6095F",
4540                 .num_databases = 256,
4541                 .num_macs = 8192,
4542                 .num_ports = 11,
4543                 .num_internal_phys = 0,
4544                 .max_vid = 4095,
4545                 .port_base_addr = 0x10,
4546                 .phy_base_addr = 0x0,
4547                 .global1_addr = 0x1b,
4548                 .global2_addr = 0x1c,
4549                 .age_time_coeff = 15000,
4550                 .g1_irqs = 8,
4551                 .atu_move_port_mask = 0xf,
4552                 .multi_chip = true,
4553                 .tag_protocol = DSA_TAG_PROTO_DSA,
4554                 .ops = &mv88e6095_ops,
4555         },
4556
4557         [MV88E6097] = {
4558                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
4559                 .family = MV88E6XXX_FAMILY_6097,
4560                 .name = "Marvell 88E6097/88E6097F",
4561                 .num_databases = 4096,
4562                 .num_macs = 8192,
4563                 .num_ports = 11,
4564                 .num_internal_phys = 8,
4565                 .max_vid = 4095,
4566                 .port_base_addr = 0x10,
4567                 .phy_base_addr = 0x0,
4568                 .global1_addr = 0x1b,
4569                 .global2_addr = 0x1c,
4570                 .age_time_coeff = 15000,
4571                 .g1_irqs = 8,
4572                 .g2_irqs = 10,
4573                 .atu_move_port_mask = 0xf,
4574                 .pvt = true,
4575                 .multi_chip = true,
4576                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4577                 .ops = &mv88e6097_ops,
4578         },
4579
4580         [MV88E6123] = {
4581                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
4582                 .family = MV88E6XXX_FAMILY_6165,
4583                 .name = "Marvell 88E6123",
4584                 .num_databases = 4096,
4585                 .num_macs = 1024,
4586                 .num_ports = 3,
4587                 .num_internal_phys = 5,
4588                 .max_vid = 4095,
4589                 .port_base_addr = 0x10,
4590                 .phy_base_addr = 0x0,
4591                 .global1_addr = 0x1b,
4592                 .global2_addr = 0x1c,
4593                 .age_time_coeff = 15000,
4594                 .g1_irqs = 9,
4595                 .g2_irqs = 10,
4596                 .atu_move_port_mask = 0xf,
4597                 .pvt = true,
4598                 .multi_chip = true,
4599                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4600                 .ops = &mv88e6123_ops,
4601         },
4602
4603         [MV88E6131] = {
4604                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
4605                 .family = MV88E6XXX_FAMILY_6185,
4606                 .name = "Marvell 88E6131",
4607                 .num_databases = 256,
4608                 .num_macs = 8192,
4609                 .num_ports = 8,
4610                 .num_internal_phys = 0,
4611                 .max_vid = 4095,
4612                 .port_base_addr = 0x10,
4613                 .phy_base_addr = 0x0,
4614                 .global1_addr = 0x1b,
4615                 .global2_addr = 0x1c,
4616                 .age_time_coeff = 15000,
4617                 .g1_irqs = 9,
4618                 .atu_move_port_mask = 0xf,
4619                 .multi_chip = true,
4620                 .tag_protocol = DSA_TAG_PROTO_DSA,
4621                 .ops = &mv88e6131_ops,
4622         },
4623
4624         [MV88E6141] = {
4625                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
4626                 .family = MV88E6XXX_FAMILY_6341,
4627                 .name = "Marvell 88E6141",
4628                 .num_databases = 4096,
4629                 .num_macs = 2048,
4630                 .num_ports = 6,
4631                 .num_internal_phys = 5,
4632                 .num_gpio = 11,
4633                 .max_vid = 4095,
4634                 .port_base_addr = 0x10,
4635                 .phy_base_addr = 0x10,
4636                 .global1_addr = 0x1b,
4637                 .global2_addr = 0x1c,
4638                 .age_time_coeff = 3750,
4639                 .atu_move_port_mask = 0x1f,
4640                 .g1_irqs = 9,
4641                 .g2_irqs = 10,
4642                 .pvt = true,
4643                 .multi_chip = true,
4644                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4645                 .ops = &mv88e6141_ops,
4646         },
4647
4648         [MV88E6161] = {
4649                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
4650                 .family = MV88E6XXX_FAMILY_6165,
4651                 .name = "Marvell 88E6161",
4652                 .num_databases = 4096,
4653                 .num_macs = 1024,
4654                 .num_ports = 6,
4655                 .num_internal_phys = 5,
4656                 .max_vid = 4095,
4657                 .port_base_addr = 0x10,
4658                 .phy_base_addr = 0x0,
4659                 .global1_addr = 0x1b,
4660                 .global2_addr = 0x1c,
4661                 .age_time_coeff = 15000,
4662                 .g1_irqs = 9,
4663                 .g2_irqs = 10,
4664                 .atu_move_port_mask = 0xf,
4665                 .pvt = true,
4666                 .multi_chip = true,
4667                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4668                 .ptp_support = true,
4669                 .ops = &mv88e6161_ops,
4670         },
4671
4672         [MV88E6165] = {
4673                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
4674                 .family = MV88E6XXX_FAMILY_6165,
4675                 .name = "Marvell 88E6165",
4676                 .num_databases = 4096,
4677                 .num_macs = 8192,
4678                 .num_ports = 6,
4679                 .num_internal_phys = 0,
4680                 .max_vid = 4095,
4681                 .port_base_addr = 0x10,
4682                 .phy_base_addr = 0x0,
4683                 .global1_addr = 0x1b,
4684                 .global2_addr = 0x1c,
4685                 .age_time_coeff = 15000,
4686                 .g1_irqs = 9,
4687                 .g2_irqs = 10,
4688                 .atu_move_port_mask = 0xf,
4689                 .pvt = true,
4690                 .multi_chip = true,
4691                 .tag_protocol = DSA_TAG_PROTO_DSA,
4692                 .ptp_support = true,
4693                 .ops = &mv88e6165_ops,
4694         },
4695
4696         [MV88E6171] = {
4697                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
4698                 .family = MV88E6XXX_FAMILY_6351,
4699                 .name = "Marvell 88E6171",
4700                 .num_databases = 4096,
4701                 .num_macs = 8192,
4702                 .num_ports = 7,
4703                 .num_internal_phys = 5,
4704                 .max_vid = 4095,
4705                 .port_base_addr = 0x10,
4706                 .phy_base_addr = 0x0,
4707                 .global1_addr = 0x1b,
4708                 .global2_addr = 0x1c,
4709                 .age_time_coeff = 15000,
4710                 .g1_irqs = 9,
4711                 .g2_irqs = 10,
4712                 .atu_move_port_mask = 0xf,
4713                 .pvt = true,
4714                 .multi_chip = true,
4715                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4716                 .ops = &mv88e6171_ops,
4717         },
4718
4719         [MV88E6172] = {
4720                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
4721                 .family = MV88E6XXX_FAMILY_6352,
4722                 .name = "Marvell 88E6172",
4723                 .num_databases = 4096,
4724                 .num_macs = 8192,
4725                 .num_ports = 7,
4726                 .num_internal_phys = 5,
4727                 .num_gpio = 15,
4728                 .max_vid = 4095,
4729                 .port_base_addr = 0x10,
4730                 .phy_base_addr = 0x0,
4731                 .global1_addr = 0x1b,
4732                 .global2_addr = 0x1c,
4733                 .age_time_coeff = 15000,
4734                 .g1_irqs = 9,
4735                 .g2_irqs = 10,
4736                 .atu_move_port_mask = 0xf,
4737                 .pvt = true,
4738                 .multi_chip = true,
4739                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4740                 .ops = &mv88e6172_ops,
4741         },
4742
4743         [MV88E6175] = {
4744                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
4745                 .family = MV88E6XXX_FAMILY_6351,
4746                 .name = "Marvell 88E6175",
4747                 .num_databases = 4096,
4748                 .num_macs = 8192,
4749                 .num_ports = 7,
4750                 .num_internal_phys = 5,
4751                 .max_vid = 4095,
4752                 .port_base_addr = 0x10,
4753                 .phy_base_addr = 0x0,
4754                 .global1_addr = 0x1b,
4755                 .global2_addr = 0x1c,
4756                 .age_time_coeff = 15000,
4757                 .g1_irqs = 9,
4758                 .g2_irqs = 10,
4759                 .atu_move_port_mask = 0xf,
4760                 .pvt = true,
4761                 .multi_chip = true,
4762                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4763                 .ops = &mv88e6175_ops,
4764         },
4765
4766         [MV88E6176] = {
4767                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
4768                 .family = MV88E6XXX_FAMILY_6352,
4769                 .name = "Marvell 88E6176",
4770                 .num_databases = 4096,
4771                 .num_macs = 8192,
4772                 .num_ports = 7,
4773                 .num_internal_phys = 5,
4774                 .num_gpio = 15,
4775                 .max_vid = 4095,
4776                 .port_base_addr = 0x10,
4777                 .phy_base_addr = 0x0,
4778                 .global1_addr = 0x1b,
4779                 .global2_addr = 0x1c,
4780                 .age_time_coeff = 15000,
4781                 .g1_irqs = 9,
4782                 .g2_irqs = 10,
4783                 .atu_move_port_mask = 0xf,
4784                 .pvt = true,
4785                 .multi_chip = true,
4786                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4787                 .ops = &mv88e6176_ops,
4788         },
4789
4790         [MV88E6185] = {
4791                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
4792                 .family = MV88E6XXX_FAMILY_6185,
4793                 .name = "Marvell 88E6185",
4794                 .num_databases = 256,
4795                 .num_macs = 8192,
4796                 .num_ports = 10,
4797                 .num_internal_phys = 0,
4798                 .max_vid = 4095,
4799                 .port_base_addr = 0x10,
4800                 .phy_base_addr = 0x0,
4801                 .global1_addr = 0x1b,
4802                 .global2_addr = 0x1c,
4803                 .age_time_coeff = 15000,
4804                 .g1_irqs = 8,
4805                 .atu_move_port_mask = 0xf,
4806                 .multi_chip = true,
4807                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4808                 .ops = &mv88e6185_ops,
4809         },
4810
4811         [MV88E6190] = {
4812                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
4813                 .family = MV88E6XXX_FAMILY_6390,
4814                 .name = "Marvell 88E6190",
4815                 .num_databases = 4096,
4816                 .num_macs = 16384,
4817                 .num_ports = 11,        /* 10 + Z80 */
4818                 .num_internal_phys = 9,
4819                 .num_gpio = 16,
4820                 .max_vid = 8191,
4821                 .port_base_addr = 0x0,
4822                 .phy_base_addr = 0x0,
4823                 .global1_addr = 0x1b,
4824                 .global2_addr = 0x1c,
4825                 .tag_protocol = DSA_TAG_PROTO_DSA,
4826                 .age_time_coeff = 3750,
4827                 .g1_irqs = 9,
4828                 .g2_irqs = 14,
4829                 .pvt = true,
4830                 .multi_chip = true,
4831                 .atu_move_port_mask = 0x1f,
4832                 .ops = &mv88e6190_ops,
4833         },
4834
4835         [MV88E6190X] = {
4836                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
4837                 .family = MV88E6XXX_FAMILY_6390,
4838                 .name = "Marvell 88E6190X",
4839                 .num_databases = 4096,
4840                 .num_macs = 16384,
4841                 .num_ports = 11,        /* 10 + Z80 */
4842                 .num_internal_phys = 9,
4843                 .num_gpio = 16,
4844                 .max_vid = 8191,
4845                 .port_base_addr = 0x0,
4846                 .phy_base_addr = 0x0,
4847                 .global1_addr = 0x1b,
4848                 .global2_addr = 0x1c,
4849                 .age_time_coeff = 3750,
4850                 .g1_irqs = 9,
4851                 .g2_irqs = 14,
4852                 .atu_move_port_mask = 0x1f,
4853                 .pvt = true,
4854                 .multi_chip = true,
4855                 .tag_protocol = DSA_TAG_PROTO_DSA,
4856                 .ops = &mv88e6190x_ops,
4857         },
4858
4859         [MV88E6191] = {
4860                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
4861                 .family = MV88E6XXX_FAMILY_6390,
4862                 .name = "Marvell 88E6191",
4863                 .num_databases = 4096,
4864                 .num_macs = 16384,
4865                 .num_ports = 11,        /* 10 + Z80 */
4866                 .num_internal_phys = 9,
4867                 .max_vid = 8191,
4868                 .port_base_addr = 0x0,
4869                 .phy_base_addr = 0x0,
4870                 .global1_addr = 0x1b,
4871                 .global2_addr = 0x1c,
4872                 .age_time_coeff = 3750,
4873                 .g1_irqs = 9,
4874                 .g2_irqs = 14,
4875                 .atu_move_port_mask = 0x1f,
4876                 .pvt = true,
4877                 .multi_chip = true,
4878                 .tag_protocol = DSA_TAG_PROTO_DSA,
4879                 .ptp_support = true,
4880                 .ops = &mv88e6191_ops,
4881         },
4882
4883         [MV88E6220] = {
4884                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
4885                 .family = MV88E6XXX_FAMILY_6250,
4886                 .name = "Marvell 88E6220",
4887                 .num_databases = 64,
4888
4889                 /* Ports 2-4 are not routed to pins
4890                  * => usable ports 0, 1, 5, 6
4891                  */
4892                 .num_ports = 7,
4893                 .num_internal_phys = 2,
4894                 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
4895                 .max_vid = 4095,
4896                 .port_base_addr = 0x08,
4897                 .phy_base_addr = 0x00,
4898                 .global1_addr = 0x0f,
4899                 .global2_addr = 0x07,
4900                 .age_time_coeff = 15000,
4901                 .g1_irqs = 9,
4902                 .g2_irqs = 10,
4903                 .atu_move_port_mask = 0xf,
4904                 .dual_chip = true,
4905                 .tag_protocol = DSA_TAG_PROTO_DSA,
4906                 .ptp_support = true,
4907                 .ops = &mv88e6250_ops,
4908         },
4909
4910         [MV88E6240] = {
4911                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
4912                 .family = MV88E6XXX_FAMILY_6352,
4913                 .name = "Marvell 88E6240",
4914                 .num_databases = 4096,
4915                 .num_macs = 8192,
4916                 .num_ports = 7,
4917                 .num_internal_phys = 5,
4918                 .num_gpio = 15,
4919                 .max_vid = 4095,
4920                 .port_base_addr = 0x10,
4921                 .phy_base_addr = 0x0,
4922                 .global1_addr = 0x1b,
4923                 .global2_addr = 0x1c,
4924                 .age_time_coeff = 15000,
4925                 .g1_irqs = 9,
4926                 .g2_irqs = 10,
4927                 .atu_move_port_mask = 0xf,
4928                 .pvt = true,
4929                 .multi_chip = true,
4930                 .tag_protocol = DSA_TAG_PROTO_EDSA,
4931                 .ptp_support = true,
4932                 .ops = &mv88e6240_ops,
4933         },
4934
4935         [MV88E6250] = {
4936                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
4937                 .family = MV88E6XXX_FAMILY_6250,
4938                 .name = "Marvell 88E6250",
4939                 .num_databases = 64,
4940                 .num_ports = 7,
4941                 .num_internal_phys = 5,
4942                 .max_vid = 4095,
4943                 .port_base_addr = 0x08,
4944                 .phy_base_addr = 0x00,
4945                 .global1_addr = 0x0f,
4946                 .global2_addr = 0x07,
4947                 .age_time_coeff = 15000,
4948                 .g1_irqs = 9,
4949                 .g2_irqs = 10,
4950                 .atu_move_port_mask = 0xf,
4951                 .dual_chip = true,
4952                 .tag_protocol = DSA_TAG_PROTO_DSA,
4953                 .ptp_support = true,
4954                 .ops = &mv88e6250_ops,
4955         },
4956
4957         [MV88E6290] = {
4958                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
4959                 .family = MV88E6XXX_FAMILY_6390,
4960                 .name = "Marvell 88E6290",
4961                 .num_databases = 4096,
4962                 .num_ports = 11,        /* 10 + Z80 */
4963                 .num_internal_phys = 9,
4964                 .num_gpio = 16,
4965                 .max_vid = 8191,
4966                 .port_base_addr = 0x0,
4967                 .phy_base_addr = 0x0,
4968                 .global1_addr = 0x1b,
4969                 .global2_addr = 0x1c,
4970                 .age_time_coeff = 3750,
4971                 .g1_irqs = 9,
4972                 .g2_irqs = 14,
4973                 .atu_move_port_mask = 0x1f,
4974                 .pvt = true,
4975                 .multi_chip = true,
4976                 .tag_protocol = DSA_TAG_PROTO_DSA,
4977                 .ptp_support = true,
4978                 .ops = &mv88e6290_ops,
4979         },
4980
4981         [MV88E6320] = {
4982                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
4983                 .family = MV88E6XXX_FAMILY_6320,
4984                 .name = "Marvell 88E6320",
4985                 .num_databases = 4096,
4986                 .num_macs = 8192,
4987                 .num_ports = 7,
4988                 .num_internal_phys = 5,
4989                 .num_gpio = 15,
4990                 .max_vid = 4095,
4991                 .port_base_addr = 0x10,
4992                 .phy_base_addr = 0x0,
4993                 .global1_addr = 0x1b,
4994                 .global2_addr = 0x1c,
4995                 .age_time_coeff = 15000,
4996                 .g1_irqs = 8,
4997                 .g2_irqs = 10,
4998                 .atu_move_port_mask = 0xf,
4999                 .pvt = true,
5000                 .multi_chip = true,
5001                 .tag_protocol = DSA_TAG_PROTO_EDSA,
5002                 .ptp_support = true,
5003                 .ops = &mv88e6320_ops,
5004         },
5005
5006         [MV88E6321] = {
5007                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
5008                 .family = MV88E6XXX_FAMILY_6320,
5009                 .name = "Marvell 88E6321",
5010                 .num_databases = 4096,
5011                 .num_macs = 8192,
5012                 .num_ports = 7,
5013                 .num_internal_phys = 5,
5014                 .num_gpio = 15,
5015                 .max_vid = 4095,
5016                 .port_base_addr = 0x10,
5017                 .phy_base_addr = 0x0,
5018                 .global1_addr = 0x1b,
5019                 .global2_addr = 0x1c,
5020                 .age_time_coeff = 15000,
5021                 .g1_irqs = 8,
5022                 .g2_irqs = 10,
5023                 .atu_move_port_mask = 0xf,
5024                 .multi_chip = true,
5025                 .tag_protocol = DSA_TAG_PROTO_EDSA,
5026                 .ptp_support = true,
5027                 .ops = &mv88e6321_ops,
5028         },
5029
5030         [MV88E6341] = {
5031                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
5032                 .family = MV88E6XXX_FAMILY_6341,
5033                 .name = "Marvell 88E6341",
5034                 .num_databases = 4096,
5035                 .num_macs = 2048,
5036                 .num_internal_phys = 5,
5037                 .num_ports = 6,
5038                 .num_gpio = 11,
5039                 .max_vid = 4095,
5040                 .port_base_addr = 0x10,
5041                 .phy_base_addr = 0x10,
5042                 .global1_addr = 0x1b,
5043                 .global2_addr = 0x1c,
5044                 .age_time_coeff = 3750,
5045                 .atu_move_port_mask = 0x1f,
5046                 .g1_irqs = 9,
5047                 .g2_irqs = 10,
5048                 .pvt = true,
5049                 .multi_chip = true,
5050                 .tag_protocol = DSA_TAG_PROTO_EDSA,
5051                 .ptp_support = true,
5052                 .ops = &mv88e6341_ops,
5053         },
5054
5055         [MV88E6350] = {
5056                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
5057                 .family = MV88E6XXX_FAMILY_6351,
5058                 .name = "Marvell 88E6350",
5059                 .num_databases = 4096,
5060                 .num_macs = 8192,
5061                 .num_ports = 7,
5062                 .num_internal_phys = 5,
5063                 .max_vid = 4095,
5064                 .port_base_addr = 0x10,
5065                 .phy_base_addr = 0x0,
5066                 .global1_addr = 0x1b,
5067                 .global2_addr = 0x1c,
5068                 .age_time_coeff = 15000,
5069                 .g1_irqs = 9,
5070                 .g2_irqs = 10,
5071                 .atu_move_port_mask = 0xf,
5072                 .pvt = true,
5073                 .multi_chip = true,
5074                 .tag_protocol = DSA_TAG_PROTO_EDSA,
5075                 .ops = &mv88e6350_ops,
5076         },
5077
5078         [MV88E6351] = {
5079                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
5080                 .family = MV88E6XXX_FAMILY_6351,
5081                 .name = "Marvell 88E6351",
5082                 .num_databases = 4096,
5083                 .num_macs = 8192,
5084                 .num_ports = 7,
5085                 .num_internal_phys = 5,
5086                 .max_vid = 4095,
5087                 .port_base_addr = 0x10,
5088                 .phy_base_addr = 0x0,
5089                 .global1_addr = 0x1b,
5090                 .global2_addr = 0x1c,
5091                 .age_time_coeff = 15000,
5092                 .g1_irqs = 9,
5093                 .g2_irqs = 10,
5094                 .atu_move_port_mask = 0xf,
5095                 .pvt = true,
5096                 .multi_chip = true,
5097                 .tag_protocol = DSA_TAG_PROTO_EDSA,
5098                 .ops = &mv88e6351_ops,
5099         },
5100
5101         [MV88E6352] = {
5102                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
5103                 .family = MV88E6XXX_FAMILY_6352,
5104                 .name = "Marvell 88E6352",
5105                 .num_databases = 4096,
5106                 .num_macs = 8192,
5107                 .num_ports = 7,
5108                 .num_internal_phys = 5,
5109                 .num_gpio = 15,
5110                 .max_vid = 4095,
5111                 .port_base_addr = 0x10,
5112                 .phy_base_addr = 0x0,
5113                 .global1_addr = 0x1b,
5114                 .global2_addr = 0x1c,
5115                 .age_time_coeff = 15000,
5116                 .g1_irqs = 9,
5117                 .g2_irqs = 10,
5118                 .atu_move_port_mask = 0xf,
5119                 .pvt = true,
5120                 .multi_chip = true,
5121                 .tag_protocol = DSA_TAG_PROTO_EDSA,
5122                 .ptp_support = true,
5123                 .ops = &mv88e6352_ops,
5124         },
5125         [MV88E6390] = {
5126                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
5127                 .family = MV88E6XXX_FAMILY_6390,
5128                 .name = "Marvell 88E6390",
5129                 .num_databases = 4096,
5130                 .num_macs = 16384,
5131                 .num_ports = 11,        /* 10 + Z80 */
5132                 .num_internal_phys = 9,
5133                 .num_gpio = 16,
5134                 .max_vid = 8191,
5135                 .port_base_addr = 0x0,
5136                 .phy_base_addr = 0x0,
5137                 .global1_addr = 0x1b,
5138                 .global2_addr = 0x1c,
5139                 .age_time_coeff = 3750,
5140                 .g1_irqs = 9,
5141                 .g2_irqs = 14,
5142                 .atu_move_port_mask = 0x1f,
5143                 .pvt = true,
5144                 .multi_chip = true,
5145                 .tag_protocol = DSA_TAG_PROTO_DSA,
5146                 .ptp_support = true,
5147                 .ops = &mv88e6390_ops,
5148         },
5149         [MV88E6390X] = {
5150                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
5151                 .family = MV88E6XXX_FAMILY_6390,
5152                 .name = "Marvell 88E6390X",
5153                 .num_databases = 4096,
5154                 .num_macs = 16384,
5155                 .num_ports = 11,        /* 10 + Z80 */
5156                 .num_internal_phys = 9,
5157                 .num_gpio = 16,
5158                 .max_vid = 8191,
5159                 .port_base_addr = 0x0,
5160                 .phy_base_addr = 0x0,
5161                 .global1_addr = 0x1b,
5162                 .global2_addr = 0x1c,
5163                 .age_time_coeff = 3750,
5164                 .g1_irqs = 9,
5165                 .g2_irqs = 14,
5166                 .atu_move_port_mask = 0x1f,
5167                 .pvt = true,
5168                 .multi_chip = true,
5169                 .tag_protocol = DSA_TAG_PROTO_DSA,
5170                 .ptp_support = true,
5171                 .ops = &mv88e6390x_ops,
5172         },
5173 };
5174
5175 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
5176 {
5177         int i;
5178
5179         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
5180                 if (mv88e6xxx_table[i].prod_num == prod_num)
5181                         return &mv88e6xxx_table[i];
5182
5183         return NULL;
5184 }
5185
5186 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
5187 {
5188         const struct mv88e6xxx_info *info;
5189         unsigned int prod_num, rev;
5190         u16 id;
5191         int err;
5192
5193         mv88e6xxx_reg_lock(chip);
5194         err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
5195         mv88e6xxx_reg_unlock(chip);
5196         if (err)
5197                 return err;
5198
5199         prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
5200         rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
5201
5202         info = mv88e6xxx_lookup_info(prod_num);
5203         if (!info)
5204                 return -ENODEV;
5205
5206         /* Update the compatible info with the probed one */
5207         chip->info = info;
5208
5209         err = mv88e6xxx_g2_require(chip);
5210         if (err)
5211                 return err;
5212
5213         dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
5214                  chip->info->prod_num, chip->info->name, rev);
5215
5216         return 0;
5217 }
5218
5219 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
5220 {
5221         struct mv88e6xxx_chip *chip;
5222
5223         chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
5224         if (!chip)
5225                 return NULL;
5226
5227         chip->dev = dev;
5228
5229         mutex_init(&chip->reg_lock);
5230         INIT_LIST_HEAD(&chip->mdios);
5231         idr_init(&chip->policies);
5232
5233         return chip;
5234 }
5235
5236 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
5237                                                         int port,
5238                                                         enum dsa_tag_protocol m)
5239 {
5240         struct mv88e6xxx_chip *chip = ds->priv;
5241
5242         return chip->info->tag_protocol;
5243 }
5244
5245 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
5246                                       const struct switchdev_obj_port_mdb *mdb)
5247 {
5248         /* We don't need any dynamic resource from the kernel (yet),
5249          * so skip the prepare phase.
5250          */
5251
5252         return 0;
5253 }
5254
5255 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
5256                                    const struct switchdev_obj_port_mdb *mdb)
5257 {
5258         struct mv88e6xxx_chip *chip = ds->priv;
5259
5260         mv88e6xxx_reg_lock(chip);
5261         if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
5262                                          MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
5263                 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
5264                         port);
5265         mv88e6xxx_reg_unlock(chip);
5266 }
5267
5268 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
5269                                   const struct switchdev_obj_port_mdb *mdb)
5270 {
5271         struct mv88e6xxx_chip *chip = ds->priv;
5272         int err;
5273
5274         mv88e6xxx_reg_lock(chip);
5275         err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
5276         mv88e6xxx_reg_unlock(chip);
5277
5278         return err;
5279 }
5280
5281 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
5282                                      struct dsa_mall_mirror_tc_entry *mirror,
5283                                      bool ingress)
5284 {
5285         enum mv88e6xxx_egress_direction direction = ingress ?
5286                                                 MV88E6XXX_EGRESS_DIR_INGRESS :
5287                                                 MV88E6XXX_EGRESS_DIR_EGRESS;
5288         struct mv88e6xxx_chip *chip = ds->priv;
5289         bool other_mirrors = false;
5290         int i;
5291         int err;
5292
5293         if (!chip->info->ops->set_egress_port)
5294                 return -EOPNOTSUPP;
5295
5296         mutex_lock(&chip->reg_lock);
5297         if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
5298             mirror->to_local_port) {
5299                 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5300                         other_mirrors |= ingress ?
5301                                          chip->ports[i].mirror_ingress :
5302                                          chip->ports[i].mirror_egress;
5303
5304                 /* Can't change egress port when other mirror is active */
5305                 if (other_mirrors) {
5306                         err = -EBUSY;
5307                         goto out;
5308                 }
5309
5310                 err = chip->info->ops->set_egress_port(chip,
5311                                                        direction,
5312                                                        mirror->to_local_port);
5313                 if (err)
5314                         goto out;
5315         }
5316
5317         err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
5318 out:
5319         mutex_unlock(&chip->reg_lock);
5320
5321         return err;
5322 }
5323
5324 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
5325                                       struct dsa_mall_mirror_tc_entry *mirror)
5326 {
5327         enum mv88e6xxx_egress_direction direction = mirror->ingress ?
5328                                                 MV88E6XXX_EGRESS_DIR_INGRESS :
5329                                                 MV88E6XXX_EGRESS_DIR_EGRESS;
5330         struct mv88e6xxx_chip *chip = ds->priv;
5331         bool other_mirrors = false;
5332         int i;
5333
5334         mutex_lock(&chip->reg_lock);
5335         if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
5336                 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
5337
5338         for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
5339                 other_mirrors |= mirror->ingress ?
5340                                  chip->ports[i].mirror_ingress :
5341                                  chip->ports[i].mirror_egress;
5342
5343         /* Reset egress port when no other mirror is active */
5344         if (!other_mirrors) {
5345                 if (chip->info->ops->set_egress_port(chip,
5346                                                      direction,
5347                                                      dsa_upstream_port(ds,
5348                                                                        port)))
5349                         dev_err(ds->dev, "failed to set egress port\n");
5350         }
5351
5352         mutex_unlock(&chip->reg_lock);
5353 }
5354
5355 static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port,
5356                                          bool unicast, bool multicast)
5357 {
5358         struct mv88e6xxx_chip *chip = ds->priv;
5359         int err = -EOPNOTSUPP;
5360
5361         mv88e6xxx_reg_lock(chip);
5362         if (chip->info->ops->port_set_egress_floods)
5363                 err = chip->info->ops->port_set_egress_floods(chip, port,
5364                                                               unicast,
5365                                                               multicast);
5366         mv88e6xxx_reg_unlock(chip);
5367
5368         return err;
5369 }
5370
5371 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
5372         .get_tag_protocol       = mv88e6xxx_get_tag_protocol,
5373         .setup                  = mv88e6xxx_setup,
5374         .teardown               = mv88e6xxx_teardown,
5375         .phylink_validate       = mv88e6xxx_validate,
5376         .phylink_mac_link_state = mv88e6xxx_link_state,
5377         .phylink_mac_config     = mv88e6xxx_mac_config,
5378         .phylink_mac_link_down  = mv88e6xxx_mac_link_down,
5379         .phylink_mac_link_up    = mv88e6xxx_mac_link_up,
5380         .get_strings            = mv88e6xxx_get_strings,
5381         .get_ethtool_stats      = mv88e6xxx_get_ethtool_stats,
5382         .get_sset_count         = mv88e6xxx_get_sset_count,
5383         .port_enable            = mv88e6xxx_port_enable,
5384         .port_disable           = mv88e6xxx_port_disable,
5385         .get_mac_eee            = mv88e6xxx_get_mac_eee,
5386         .set_mac_eee            = mv88e6xxx_set_mac_eee,
5387         .get_eeprom_len         = mv88e6xxx_get_eeprom_len,
5388         .get_eeprom             = mv88e6xxx_get_eeprom,
5389         .set_eeprom             = mv88e6xxx_set_eeprom,
5390         .get_regs_len           = mv88e6xxx_get_regs_len,
5391         .get_regs               = mv88e6xxx_get_regs,
5392         .get_rxnfc              = mv88e6xxx_get_rxnfc,
5393         .set_rxnfc              = mv88e6xxx_set_rxnfc,
5394         .set_ageing_time        = mv88e6xxx_set_ageing_time,
5395         .port_bridge_join       = mv88e6xxx_port_bridge_join,
5396         .port_bridge_leave      = mv88e6xxx_port_bridge_leave,
5397         .port_egress_floods     = mv88e6xxx_port_egress_floods,
5398         .port_stp_state_set     = mv88e6xxx_port_stp_state_set,
5399         .port_fast_age          = mv88e6xxx_port_fast_age,
5400         .port_vlan_filtering    = mv88e6xxx_port_vlan_filtering,
5401         .port_vlan_prepare      = mv88e6xxx_port_vlan_prepare,
5402         .port_vlan_add          = mv88e6xxx_port_vlan_add,
5403         .port_vlan_del          = mv88e6xxx_port_vlan_del,
5404         .port_fdb_add           = mv88e6xxx_port_fdb_add,
5405         .port_fdb_del           = mv88e6xxx_port_fdb_del,
5406         .port_fdb_dump          = mv88e6xxx_port_fdb_dump,
5407         .port_mdb_prepare       = mv88e6xxx_port_mdb_prepare,
5408         .port_mdb_add           = mv88e6xxx_port_mdb_add,
5409         .port_mdb_del           = mv88e6xxx_port_mdb_del,
5410         .port_mirror_add        = mv88e6xxx_port_mirror_add,
5411         .port_mirror_del        = mv88e6xxx_port_mirror_del,
5412         .crosschip_bridge_join  = mv88e6xxx_crosschip_bridge_join,
5413         .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
5414         .port_hwtstamp_set      = mv88e6xxx_port_hwtstamp_set,
5415         .port_hwtstamp_get      = mv88e6xxx_port_hwtstamp_get,
5416         .port_txtstamp          = mv88e6xxx_port_txtstamp,
5417         .port_rxtstamp          = mv88e6xxx_port_rxtstamp,
5418         .get_ts_info            = mv88e6xxx_get_ts_info,
5419         .devlink_param_get      = mv88e6xxx_devlink_param_get,
5420         .devlink_param_set      = mv88e6xxx_devlink_param_set,
5421 };
5422
5423 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
5424 {
5425         struct device *dev = chip->dev;
5426         struct dsa_switch *ds;
5427
5428         ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
5429         if (!ds)
5430                 return -ENOMEM;
5431
5432         ds->dev = dev;
5433         ds->num_ports = mv88e6xxx_num_ports(chip);
5434         ds->priv = chip;
5435         ds->dev = dev;
5436         ds->ops = &mv88e6xxx_switch_ops;
5437         ds->ageing_time_min = chip->info->age_time_coeff;
5438         ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
5439
5440         dev_set_drvdata(dev, ds);
5441
5442         return dsa_register_switch(ds);
5443 }
5444
5445 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
5446 {
5447         dsa_unregister_switch(chip->ds);
5448 }
5449
5450 static const void *pdata_device_get_match_data(struct device *dev)
5451 {
5452         const struct of_device_id *matches = dev->driver->of_match_table;
5453         const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
5454
5455         for (; matches->name[0] || matches->type[0] || matches->compatible[0];
5456              matches++) {
5457                 if (!strcmp(pdata->compatible, matches->compatible))
5458                         return matches->data;
5459         }
5460         return NULL;
5461 }
5462
5463 /* There is no suspend to RAM support at DSA level yet, the switch configuration
5464  * would be lost after a power cycle so prevent it to be suspended.
5465  */
5466 static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
5467 {
5468         return -EOPNOTSUPP;
5469 }
5470
5471 static int __maybe_unused mv88e6xxx_resume(struct device *dev)
5472 {
5473         return 0;
5474 }
5475
5476 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
5477
5478 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
5479 {
5480         struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
5481         const struct mv88e6xxx_info *compat_info = NULL;
5482         struct device *dev = &mdiodev->dev;
5483         struct device_node *np = dev->of_node;
5484         struct mv88e6xxx_chip *chip;
5485         int port;
5486         int err;
5487
5488         if (!np && !pdata)
5489                 return -EINVAL;
5490
5491         if (np)
5492                 compat_info = of_device_get_match_data(dev);
5493
5494         if (pdata) {
5495                 compat_info = pdata_device_get_match_data(dev);
5496
5497                 if (!pdata->netdev)
5498                         return -EINVAL;
5499
5500                 for (port = 0; port < DSA_MAX_PORTS; port++) {
5501                         if (!(pdata->enabled_ports & (1 << port)))
5502                                 continue;
5503                         if (strcmp(pdata->cd.port_names[port], "cpu"))
5504                                 continue;
5505                         pdata->cd.netdev[port] = &pdata->netdev->dev;
5506                         break;
5507                 }
5508         }
5509
5510         if (!compat_info)
5511                 return -EINVAL;
5512
5513         chip = mv88e6xxx_alloc_chip(dev);
5514         if (!chip) {
5515                 err = -ENOMEM;
5516                 goto out;
5517         }
5518
5519         chip->info = compat_info;
5520
5521         err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
5522         if (err)
5523                 goto out;
5524
5525         chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
5526         if (IS_ERR(chip->reset)) {
5527                 err = PTR_ERR(chip->reset);
5528                 goto out;
5529         }
5530         if (chip->reset)
5531                 usleep_range(1000, 2000);
5532
5533         err = mv88e6xxx_detect(chip);
5534         if (err)
5535                 goto out;
5536
5537         mv88e6xxx_phy_init(chip);
5538
5539         if (chip->info->ops->get_eeprom) {
5540                 if (np)
5541                         of_property_read_u32(np, "eeprom-length",
5542                                              &chip->eeprom_len);
5543                 else
5544                         chip->eeprom_len = pdata->eeprom_len;
5545         }
5546
5547         mv88e6xxx_reg_lock(chip);
5548         err = mv88e6xxx_switch_reset(chip);
5549         mv88e6xxx_reg_unlock(chip);
5550         if (err)
5551                 goto out;
5552
5553         if (np) {
5554                 chip->irq = of_irq_get(np, 0);
5555                 if (chip->irq == -EPROBE_DEFER) {
5556                         err = chip->irq;
5557                         goto out;
5558                 }
5559         }
5560
5561         if (pdata)
5562                 chip->irq = pdata->irq;
5563
5564         /* Has to be performed before the MDIO bus is created, because
5565          * the PHYs will link their interrupts to these interrupt
5566          * controllers
5567          */
5568         mv88e6xxx_reg_lock(chip);
5569         if (chip->irq > 0)
5570                 err = mv88e6xxx_g1_irq_setup(chip);
5571         else
5572                 err = mv88e6xxx_irq_poll_setup(chip);
5573         mv88e6xxx_reg_unlock(chip);
5574
5575         if (err)
5576                 goto out;
5577
5578         if (chip->info->g2_irqs > 0) {
5579                 err = mv88e6xxx_g2_irq_setup(chip);
5580                 if (err)
5581                         goto out_g1_irq;
5582         }
5583
5584         err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
5585         if (err)
5586                 goto out_g2_irq;
5587
5588         err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
5589         if (err)
5590                 goto out_g1_atu_prob_irq;
5591
5592         err = mv88e6xxx_mdios_register(chip, np);
5593         if (err)
5594                 goto out_g1_vtu_prob_irq;
5595
5596         err = mv88e6xxx_register_switch(chip);
5597         if (err)
5598                 goto out_mdio;
5599
5600         return 0;
5601
5602 out_mdio:
5603         mv88e6xxx_mdios_unregister(chip);
5604 out_g1_vtu_prob_irq:
5605         mv88e6xxx_g1_vtu_prob_irq_free(chip);
5606 out_g1_atu_prob_irq:
5607         mv88e6xxx_g1_atu_prob_irq_free(chip);
5608 out_g2_irq:
5609         if (chip->info->g2_irqs > 0)
5610                 mv88e6xxx_g2_irq_free(chip);
5611 out_g1_irq:
5612         if (chip->irq > 0)
5613                 mv88e6xxx_g1_irq_free(chip);
5614         else
5615                 mv88e6xxx_irq_poll_free(chip);
5616 out:
5617         if (pdata)
5618                 dev_put(pdata->netdev);
5619
5620         return err;
5621 }
5622
5623 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
5624 {
5625         struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
5626         struct mv88e6xxx_chip *chip = ds->priv;
5627
5628         if (chip->info->ptp_support) {
5629                 mv88e6xxx_hwtstamp_free(chip);
5630                 mv88e6xxx_ptp_free(chip);
5631         }
5632
5633         mv88e6xxx_phy_destroy(chip);
5634         mv88e6xxx_unregister_switch(chip);
5635         mv88e6xxx_mdios_unregister(chip);
5636
5637         mv88e6xxx_g1_vtu_prob_irq_free(chip);
5638         mv88e6xxx_g1_atu_prob_irq_free(chip);
5639
5640         if (chip->info->g2_irqs > 0)
5641                 mv88e6xxx_g2_irq_free(chip);
5642
5643         if (chip->irq > 0)
5644                 mv88e6xxx_g1_irq_free(chip);
5645         else
5646                 mv88e6xxx_irq_poll_free(chip);
5647 }
5648
5649 static const struct of_device_id mv88e6xxx_of_match[] = {
5650         {
5651                 .compatible = "marvell,mv88e6085",
5652                 .data = &mv88e6xxx_table[MV88E6085],
5653         },
5654         {
5655                 .compatible = "marvell,mv88e6190",
5656                 .data = &mv88e6xxx_table[MV88E6190],
5657         },
5658         {
5659                 .compatible = "marvell,mv88e6250",
5660                 .data = &mv88e6xxx_table[MV88E6250],
5661         },
5662         { /* sentinel */ },
5663 };
5664
5665 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
5666
5667 static struct mdio_driver mv88e6xxx_driver = {
5668         .probe  = mv88e6xxx_probe,
5669         .remove = mv88e6xxx_remove,
5670         .mdiodrv.driver = {
5671                 .name = "mv88e6085",
5672                 .of_match_table = mv88e6xxx_of_match,
5673                 .pm = &mv88e6xxx_pm_ops,
5674         },
5675 };
5676
5677 mdio_module_driver(mv88e6xxx_driver);
5678
5679 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
5680 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
5681 MODULE_LICENSE("GPL");