drivers/net/dsa/mv88e6xxx/chip.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Marvell 88e6xxx Ethernet switch single-chip support
   4  *
   5  * Copyright (c) 2008 Marvell Semiconductor
   6  *
   7  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
   8  *
   9  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
  10  *      Vivien Didelot <vivien.didelot@savoirfairelinux.com>
  11  */
  12
  13 #include <linux/bitfield.h>
  14 #include <linux/delay.h>
  15 #include <linux/dsa/mv88e6xxx.h>
  16 #include <linux/etherdevice.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/if_bridge.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/irq.h>
  21 #include <linux/irqdomain.h>
  22 #include <linux/jiffies.h>
  23 #include <linux/list.h>
  24 #include <linux/mdio.h>
  25 #include <linux/module.h>
  26 #include <linux/of_device.h>
  27 #include <linux/of_irq.h>
  28 #include <linux/of_mdio.h>
  29 #include <linux/platform_data/mv88e6xxx.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/gpio/consumer.h>
  32 #include <linux/phylink.h>
  33 #include <net/dsa.h>
  34
  35 #include "chip.h"
  36 #include "devlink.h"
  37 #include "global1.h"
  38 #include "global2.h"
  39 #include "hwtstamp.h"
  40 #include "phy.h"
  41 #include "port.h"
  42 #include "ptp.h"
  43 #include "serdes.h"
  44 #include "smi.h"
  45
  46 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
  47 {
  48         if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
  49                 dev_err(chip->dev, "Switch registers lock not held!\n");
  50                 dump_stack();
  51         }
  52 }
  53
  54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
  55 {
  56         int err;
  57
  58         assert_reg_lock(chip);
  59
  60         err = mv88e6xxx_smi_read(chip, addr, reg, val);
  61         if (err)
  62                 return err;
  63
  64         dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
  65                 addr, reg, *val);
  66
  67         return 0;
  68 }
  69
  70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
  71 {
  72         int err;
  73
  74         assert_reg_lock(chip);
  75
  76         err = mv88e6xxx_smi_write(chip, addr, reg, val);
  77         if (err)
  78                 return err;
  79
  80         dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
  81                 addr, reg, val);
  82
  83         return 0;
  84 }
  85
  86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
  87                         u16 mask, u16 val)
  88 {
  89         const unsigned long timeout = jiffies + msecs_to_jiffies(50);
  90         u16 data;
  91         int err;
  92         int i;
  93
  94         /* There's no bus specific operation to wait for a mask. Even
  95          * if the initial poll takes longer than 50ms, always do at
  96          * least one more attempt.
  97          */
  98         for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) {
  99                 err = mv88e6xxx_read(chip, addr, reg, &data);
 100                 if (err)
 101                         return err;
 102
 103                 if ((data & mask) == val)
 104                         return 0;
 105
 106                 if (i < 2)
 107                         cpu_relax();
 108                 else
 109                         usleep_range(1000, 2000);
 110         }
 111
 112         dev_err(chip->dev, "Timeout while waiting for switch\n");
 113         return -ETIMEDOUT;
 114 }
 115
 116 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
 117                        int bit, int val)
 118 {
 119         return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
 120                                    val ? BIT(bit) : 0x0000);
 121 }
 122
 123 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
 124 {
 125         struct mv88e6xxx_mdio_bus *mdio_bus;
 126
 127         mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
 128                                     list);
 129         if (!mdio_bus)
 130                 return NULL;
 131
 132         return mdio_bus->bus;
 133 }
 134
 135 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
 136 {
 137         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 138         unsigned int n = d->hwirq;
 139
 140         chip->g1_irq.masked |= (1 << n);
 141 }
 142
 143 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
 144 {
 145         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 146         unsigned int n = d->hwirq;
 147
 148         chip->g1_irq.masked &= ~(1 << n);
 149 }
 150
 151 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
 152 {
 153         unsigned int nhandled = 0;
 154         unsigned int sub_irq;
 155         unsigned int n;
 156         u16 reg;
 157         u16 ctl1;
 158         int err;
 159
 160         mv88e6xxx_reg_lock(chip);
 161         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 162         mv88e6xxx_reg_unlock(chip);
 163
 164         if (err)
 165                 goto out;
 166
 167         do {
 168                 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
 169                         if (reg & (1 << n)) {
 170                                 sub_irq = irq_find_mapping(chip->g1_irq.domain,
 171                                                            n);
 172                                 handle_nested_irq(sub_irq);
 173                                 ++nhandled;
 174                         }
 175                 }
 176
 177                 mv88e6xxx_reg_lock(chip);
 178                 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
 179                 if (err)
 180                         goto unlock;
 181                 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 182 unlock:
 183                 mv88e6xxx_reg_unlock(chip);
 184                 if (err)
 185                         goto out;
 186                 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
 187         } while (reg & ctl1);
 188
 189 out:
 190         return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
 191 }
 192
 193 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
 194 {
 195         struct mv88e6xxx_chip *chip = dev_id;
 196
 197         return mv88e6xxx_g1_irq_thread_work(chip);
 198 }
 199
 200 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
 201 {
 202         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 203
 204         mv88e6xxx_reg_lock(chip);
 205 }
 206
 207 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
 208 {
 209         struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
 210         u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
 211         u16 reg;
 212         int err;
 213
 214         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
 215         if (err)
 216                 goto out;
 217
 218         reg &= ~mask;
 219         reg |= (~chip->g1_irq.masked & mask);
 220
 221         err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
 222         if (err)
 223                 goto out;
 224
 225 out:
 226         mv88e6xxx_reg_unlock(chip);
 227 }
 228
 229 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
 230         .name                   = "mv88e6xxx-g1",
 231         .irq_mask               = mv88e6xxx_g1_irq_mask,
 232         .irq_unmask             = mv88e6xxx_g1_irq_unmask,
 233         .irq_bus_lock           = mv88e6xxx_g1_irq_bus_lock,
 234         .irq_bus_sync_unlock    = mv88e6xxx_g1_irq_bus_sync_unlock,
 235 };
 236
 237 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
 238                                        unsigned int irq,
 239                                        irq_hw_number_t hwirq)
 240 {
 241         struct mv88e6xxx_chip *chip = d->host_data;
 242
 243         irq_set_chip_data(irq, d->host_data);
 244         irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
 245         irq_set_noprobe(irq);
 246
 247         return 0;
 248 }
 249
 250 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
 251         .map    = mv88e6xxx_g1_irq_domain_map,
 252         .xlate  = irq_domain_xlate_twocell,
 253 };
 254
 255 /* To be called with reg_lock held */
 256 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
 257 {
 258         int irq, virq;
 259         u16 mask;
 260
 261         mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
 262         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 263         mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 264
 265         for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
 266                 virq = irq_find_mapping(chip->g1_irq.domain, irq);
 267                 irq_dispose_mapping(virq);
 268         }
 269
 270         irq_domain_remove(chip->g1_irq.domain);
 271 }
 272
 273 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
 274 {
 275         /*
 276          * free_irq must be called without reg_lock taken because the irq
 277          * handler takes this lock, too.
 278          */
 279         free_irq(chip->irq, chip);
 280
 281         mv88e6xxx_reg_lock(chip);
 282         mv88e6xxx_g1_irq_free_common(chip);
 283         mv88e6xxx_reg_unlock(chip);
 284 }
 285
 286 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
 287 {
 288         int err, irq, virq;
 289         u16 reg, mask;
 290
 291         chip->g1_irq.nirqs = chip->info->g1_irqs;
 292         chip->g1_irq.domain = irq_domain_add_simple(
 293                 NULL, chip->g1_irq.nirqs, 0,
 294                 &mv88e6xxx_g1_irq_domain_ops, chip);
 295         if (!chip->g1_irq.domain)
 296                 return -ENOMEM;
 297
 298         for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
 299                 irq_create_mapping(chip->g1_irq.domain, irq);
 300
 301         chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
 302         chip->g1_irq.masked = ~0;
 303
 304         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
 305         if (err)
 306                 goto out_mapping;
 307
 308         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 309
 310         err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 311         if (err)
 312                 goto out_disable;
 313
 314         /* Reading the interrupt status clears (most of) them */
 315         err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
 316         if (err)
 317                 goto out_disable;
 318
 319         return 0;
 320
 321 out_disable:
 322         mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
 323         mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
 324
 325 out_mapping:
 326         for (irq = 0; irq < 16; irq++) {
 327                 virq = irq_find_mapping(chip->g1_irq.domain, irq);
 328                 irq_dispose_mapping(virq);
 329         }
 330
 331         irq_domain_remove(chip->g1_irq.domain);
 332
 333         return err;
 334 }
 335
 336 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
 337 {
 338         static struct lock_class_key lock_key;
 339         static struct lock_class_key request_key;
 340         int err;
 341
 342         err = mv88e6xxx_g1_irq_setup_common(chip);
 343         if (err)
 344                 return err;
 345
 346         /* These lock classes tells lockdep that global 1 irqs are in
 347          * a different category than their parent GPIO, so it won't
 348          * report false recursion.
 349          */
 350         irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
 351
 352         snprintf(chip->irq_name, sizeof(chip->irq_name),
 353                  "mv88e6xxx-%s", dev_name(chip->dev));
 354
 355         mv88e6xxx_reg_unlock(chip);
 356         err = request_threaded_irq(chip->irq, NULL,
 357                                    mv88e6xxx_g1_irq_thread_fn,
 358                                    IRQF_ONESHOT | IRQF_SHARED,
 359                                    chip->irq_name, chip);
 360         mv88e6xxx_reg_lock(chip);
 361         if (err)
 362                 mv88e6xxx_g1_irq_free_common(chip);
 363
 364         return err;
 365 }
 366
 367 static void mv88e6xxx_irq_poll(struct kthread_work *work)
 368 {
 369         struct mv88e6xxx_chip *chip = container_of(work,
 370                                                    struct mv88e6xxx_chip,
 371                                                    irq_poll_work.work);
 372         mv88e6xxx_g1_irq_thread_work(chip);
 373
 374         kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
 375                                    msecs_to_jiffies(100));
 376 }
 377
 378 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
 379 {
 380         int err;
 381
 382         err = mv88e6xxx_g1_irq_setup_common(chip);
 383         if (err)
 384                 return err;
 385
 386         kthread_init_delayed_work(&chip->irq_poll_work,
 387                                   mv88e6xxx_irq_poll);
 388
 389         chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
 390         if (IS_ERR(chip->kworker))
 391                 return PTR_ERR(chip->kworker);
 392
 393         kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
 394                                    msecs_to_jiffies(100));
 395
 396         return 0;
 397 }
 398
 399 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
 400 {
 401         kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
 402         kthread_destroy_worker(chip->kworker);
 403
 404         mv88e6xxx_reg_lock(chip);
 405         mv88e6xxx_g1_irq_free_common(chip);
 406         mv88e6xxx_reg_unlock(chip);
 407 }
 408
 409 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
 410                                            int port, phy_interface_t interface)
 411 {
 412         int err;
 413
 414         if (chip->info->ops->port_set_rgmii_delay) {
 415                 err = chip->info->ops->port_set_rgmii_delay(chip, port,
 416                                                             interface);
 417                 if (err && err != -EOPNOTSUPP)
 418                         return err;
 419         }
 420
 421         if (chip->info->ops->port_set_cmode) {
 422                 err = chip->info->ops->port_set_cmode(chip, port,
 423                                                       interface);
 424                 if (err && err != -EOPNOTSUPP)
 425                         return err;
 426         }
 427
 428         return 0;
 429 }
 430
 431 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
 432                                     int link, int speed, int duplex, int pause,
 433                                     phy_interface_t mode)
 434 {
 435         int err;
 436
 437         if (!chip->info->ops->port_set_link)
 438                 return 0;
 439
 440         /* Port's MAC control must not be changed unless the link is down */
 441         err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
 442         if (err)
 443                 return err;
 444
 445         if (chip->info->ops->port_set_speed_duplex) {
 446                 err = chip->info->ops->port_set_speed_duplex(chip, port,
 447                                                              speed, duplex);
 448                 if (err && err != -EOPNOTSUPP)
 449                         goto restore_link;
 450         }
 451
 452         if (chip->info->ops->port_set_pause) {
 453                 err = chip->info->ops->port_set_pause(chip, port, pause);
 454                 if (err)
 455                         goto restore_link;
 456         }
 457
 458         err = mv88e6xxx_port_config_interface(chip, port, mode);
 459 restore_link:
 460         if (chip->info->ops->port_set_link(chip, port, link))
 461                 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
 462
 463         return err;
 464 }
 465
 466 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
 467 {
 468         struct mv88e6xxx_chip *chip = ds->priv;
 469
 470         return port < chip->info->num_internal_phys;
 471 }
 472
 473 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
 474 {
 475         u16 reg;
 476         int err;
 477
 478         /* The 88e6250 family does not have the PHY detect bit. Instead,
 479          * report whether the port is internal.
 480          */
 481         if (chip->info->family == MV88E6XXX_FAMILY_6250)
 482                 return port < chip->info->num_internal_phys;
 483
 484         err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
 485         if (err) {
 486                 dev_err(chip->dev,
 487                         "p%d: %s: failed to read port status\n",
 488                         port, __func__);
 489                 return err;
 490         }
 491
 492         return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
 493 }
 494
 495 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port,
 496                                           struct phylink_link_state *state)
 497 {
 498         struct mv88e6xxx_chip *chip = ds->priv;
 499         int lane;
 500         int err;
 501
 502         mv88e6xxx_reg_lock(chip);
 503         lane = mv88e6xxx_serdes_get_lane(chip, port);
 504         if (lane >= 0 && chip->info->ops->serdes_pcs_get_state)
 505                 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane,
 506                                                             state);
 507         else
 508                 err = -EOPNOTSUPP;
 509         mv88e6xxx_reg_unlock(chip);
 510
 511         return err;
 512 }
 513
 514 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
 515                                        unsigned int mode,
 516                                        phy_interface_t interface,
 517                                        const unsigned long *advertise)
 518 {
 519         const struct mv88e6xxx_ops *ops = chip->info->ops;
 520         int lane;
 521
 522         if (ops->serdes_pcs_config) {
 523                 lane = mv88e6xxx_serdes_get_lane(chip, port);
 524                 if (lane >= 0)
 525                         return ops->serdes_pcs_config(chip, port, lane, mode,
 526                                                       interface, advertise);
 527         }
 528
 529         return 0;
 530 }
 531
 532 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port)
 533 {
 534         struct mv88e6xxx_chip *chip = ds->priv;
 535         const struct mv88e6xxx_ops *ops;
 536         int err = 0;
 537         int lane;
 538
 539         ops = chip->info->ops;
 540
 541         if (ops->serdes_pcs_an_restart) {
 542                 mv88e6xxx_reg_lock(chip);
 543                 lane = mv88e6xxx_serdes_get_lane(chip, port);
 544                 if (lane >= 0)
 545                         err = ops->serdes_pcs_an_restart(chip, port, lane);
 546                 mv88e6xxx_reg_unlock(chip);
 547
 548                 if (err)
 549                         dev_err(ds->dev, "p%d: failed to restart AN\n", port);
 550         }
 551 }
 552
 553 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
 554                                         unsigned int mode,
 555                                         int speed, int duplex)
 556 {
 557         const struct mv88e6xxx_ops *ops = chip->info->ops;
 558         int lane;
 559
 560         if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) {
 561                 lane = mv88e6xxx_serdes_get_lane(chip, port);
 562                 if (lane >= 0)
 563                         return ops->serdes_pcs_link_up(chip, port, lane,
 564                                                        speed, duplex);
 565         }
 566
 567         return 0;
 568 }
 569
 570 static const u8 mv88e6185_phy_interface_modes[] = {
 571         [MV88E6185_PORT_STS_CMODE_GMII_FD]       = PHY_INTERFACE_MODE_GMII,
 572         [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII,
 573         [MV88E6185_PORT_STS_CMODE_MII_100]       = PHY_INTERFACE_MODE_MII,
 574         [MV88E6185_PORT_STS_CMODE_MII_10]        = PHY_INTERFACE_MODE_MII,
 575         [MV88E6185_PORT_STS_CMODE_SERDES]        = PHY_INTERFACE_MODE_1000BASEX,
 576         [MV88E6185_PORT_STS_CMODE_1000BASE_X]    = PHY_INTERFACE_MODE_1000BASEX,
 577         [MV88E6185_PORT_STS_CMODE_PHY]           = PHY_INTERFACE_MODE_SGMII,
 578 };
 579
 580 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 581                                        struct phylink_config *config)
 582 {
 583         u8 cmode = chip->ports[port].cmode;
 584
 585         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
 586
 587         if (mv88e6xxx_phy_is_internal(chip->ds, port)) {
 588                 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
 589         } else {
 590                 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
 591                     mv88e6185_phy_interface_modes[cmode])
 592                         __set_bit(mv88e6185_phy_interface_modes[cmode],
 593                                   config->supported_interfaces);
 594
 595                 config->mac_capabilities |= MAC_1000FD;
 596         }
 597 }
 598
 599 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 600                                        struct phylink_config *config)
 601 {
 602         u8 cmode = chip->ports[port].cmode;
 603
 604         if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
 605             mv88e6185_phy_interface_modes[cmode])
 606                 __set_bit(mv88e6185_phy_interface_modes[cmode],
 607                           config->supported_interfaces);
 608
 609         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
 610                                    MAC_1000FD;
 611 }
 612
 613 static const u8 mv88e6xxx_phy_interface_modes[] = {
 614         [MV88E6XXX_PORT_STS_CMODE_MII_PHY]      = PHY_INTERFACE_MODE_MII,
 615         [MV88E6XXX_PORT_STS_CMODE_MII]          = PHY_INTERFACE_MODE_MII,
 616         [MV88E6XXX_PORT_STS_CMODE_GMII]         = PHY_INTERFACE_MODE_GMII,
 617         [MV88E6XXX_PORT_STS_CMODE_RMII_PHY]     = PHY_INTERFACE_MODE_RMII,
 618         [MV88E6XXX_PORT_STS_CMODE_RMII]         = PHY_INTERFACE_MODE_RMII,
 619         [MV88E6XXX_PORT_STS_CMODE_100BASEX]     = PHY_INTERFACE_MODE_100BASEX,
 620         [MV88E6XXX_PORT_STS_CMODE_1000BASEX]    = PHY_INTERFACE_MODE_1000BASEX,
 621         [MV88E6XXX_PORT_STS_CMODE_SGMII]        = PHY_INTERFACE_MODE_SGMII,
 622         /* higher interface modes are not needed here, since ports supporting
 623          * them are writable, and so the supported interfaces are filled in the
 624          * corresponding .phylink_set_interfaces() implementation below
 625          */
 626 };
 627
 628 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported)
 629 {
 630         if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) &&
 631             mv88e6xxx_phy_interface_modes[cmode])
 632                 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported);
 633         else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII)
 634                 phy_interface_set_rgmii(supported);
 635 }
 636
 637 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 638                                        struct phylink_config *config)
 639 {
 640         unsigned long *supported = config->supported_interfaces;
 641
 642         /* Translate the default cmode */
 643         mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
 644
 645         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
 646 }
 647
 648 static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip)
 649 {
 650         u16 reg, val;
 651         int err;
 652
 653         err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &reg);
 654         if (err)
 655                 return err;
 656
 657         /* If PHY_DETECT is zero, then we are not in auto-media mode */
 658         if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT))
 659                 return 0xf;
 660
 661         val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT;
 662         err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, val);
 663         if (err)
 664                 return err;
 665
 666         err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &val);
 667         if (err)
 668                 return err;
 669
 670         /* Restore PHY_DETECT value */
 671         err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, reg);
 672         if (err)
 673                 return err;
 674
 675         return val & MV88E6XXX_PORT_STS_CMODE_MASK;
 676 }
 677
 678 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 679                                        struct phylink_config *config)
 680 {
 681         unsigned long *supported = config->supported_interfaces;
 682         int err, cmode;
 683
 684         /* Translate the default cmode */
 685         mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
 686
 687         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
 688                                    MAC_1000FD;
 689
 690         /* Port 4 supports automedia if the serdes is associated with it. */
 691         if (port == 4) {
 692                 err = mv88e6352_g2_scratch_port_has_serdes(chip, port);
 693                 if (err < 0)
 694                         dev_err(chip->dev, "p%d: failed to read scratch\n",
 695                                 port);
 696                 if (err <= 0)
 697                         return;
 698
 699                 cmode = mv88e6352_get_port4_serdes_cmode(chip);
 700                 if (cmode < 0)
 701                         dev_err(chip->dev, "p%d: failed to read serdes cmode\n",
 702                                 port);
 703                 else
 704                         mv88e6xxx_translate_cmode(cmode, supported);
 705         }
 706 }
 707
 708 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 709                                        struct phylink_config *config)
 710 {
 711         unsigned long *supported = config->supported_interfaces;
 712
 713         /* Translate the default cmode */
 714         mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
 715
 716         /* No ethtool bits for 200Mbps */
 717         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
 718                                    MAC_1000FD;
 719
 720         /* The C_Mode field is programmable on port 5 */
 721         if (port == 5) {
 722                 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
 723                 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
 724                 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
 725
 726                 config->mac_capabilities |= MAC_2500FD;
 727         }
 728 }
 729
 730 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 731                                        struct phylink_config *config)
 732 {
 733         unsigned long *supported = config->supported_interfaces;
 734
 735         /* Translate the default cmode */
 736         mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
 737
 738         /* No ethtool bits for 200Mbps */
 739         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
 740                                    MAC_1000FD;
 741
 742         /* The C_Mode field is programmable on ports 9 and 10 */
 743         if (port == 9 || port == 10) {
 744                 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
 745                 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
 746                 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
 747
 748                 config->mac_capabilities |= MAC_2500FD;
 749         }
 750 }
 751
 752 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 753                                         struct phylink_config *config)
 754 {
 755         unsigned long *supported = config->supported_interfaces;
 756
 757         mv88e6390_phylink_get_caps(chip, port, config);
 758
 759         /* For the 6x90X, ports 2-7 can be in automedia mode.
 760          * (Note that 6x90 doesn't support RXAUI nor XAUI).
 761          *
 762          * Port 2 can also support 1000BASE-X in automedia mode if port 9 is
 763          * configured for 1000BASE-X, SGMII or 2500BASE-X.
 764          * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is
 765          * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
 766          *
 767          * Port 5 can also support 1000BASE-X in automedia mode if port 10 is
 768          * configured for 1000BASE-X, SGMII or 2500BASE-X.
 769          * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is
 770          * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
 771          *
 772          * For now, be permissive (as the old code was) and allow 1000BASE-X
 773          * on ports 2..7.
 774          */
 775         if (port >= 2 && port <= 7)
 776                 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
 777
 778         /* The C_Mode field can also be programmed for 10G speeds */
 779         if (port == 9 || port == 10) {
 780                 __set_bit(PHY_INTERFACE_MODE_XAUI, supported);
 781                 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported);
 782
 783                 config->mac_capabilities |= MAC_10000FD;
 784         }
 785 }
 786
 787 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
 788                                         struct phylink_config *config)
 789 {
 790         unsigned long *supported = config->supported_interfaces;
 791         bool is_6191x =
 792                 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
 793
 794         mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
 795
 796         config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
 797                                    MAC_1000FD;
 798
 799         /* The C_Mode field can be programmed for ports 0, 9 and 10 */
 800         if (port == 0 || port == 9 || port == 10) {
 801                 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
 802                 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
 803
 804                 /* 6191X supports >1G modes only on port 10 */
 805                 if (!is_6191x || port == 10) {
 806                         __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
 807                         __set_bit(PHY_INTERFACE_MODE_5GBASER, supported);
 808                         __set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
 809                         /* FIXME: USXGMII is not supported yet */
 810                         /* __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); */
 811
 812                         config->mac_capabilities |= MAC_2500FD | MAC_5000FD |
 813                                 MAC_10000FD;
 814                 }
 815         }
 816
 817         if (port == 0) {
 818                 __set_bit(PHY_INTERFACE_MODE_RMII, supported);
 819                 __set_bit(PHY_INTERFACE_MODE_RGMII, supported);
 820                 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported);
 821                 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported);
 822                 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported);
 823         }
 824 }
 825
 826 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port,
 827                                struct phylink_config *config)
 828 {
 829         struct mv88e6xxx_chip *chip = ds->priv;
 830
 831         mv88e6xxx_reg_lock(chip);
 832         chip->info->ops->phylink_get_caps(chip, port, config);
 833         mv88e6xxx_reg_unlock(chip);
 834
 835         if (mv88e6xxx_phy_is_internal(ds, port)) {
 836                 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
 837                           config->supported_interfaces);
 838                 /* Internal ports with no phy-mode need GMII for PHYLIB */
 839                 __set_bit(PHY_INTERFACE_MODE_GMII,
 840                           config->supported_interfaces);
 841         }
 842 }
 843
 844 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
 845                                  unsigned int mode,
 846                                  const struct phylink_link_state *state)
 847 {
 848         struct mv88e6xxx_chip *chip = ds->priv;
 849         struct mv88e6xxx_port *p;
 850         int err = 0;
 851
 852         p = &chip->ports[port];
 853
 854         mv88e6xxx_reg_lock(chip);
 855
 856         if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(ds, port)) {
 857                 /* In inband mode, the link may come up at any time while the
 858                  * link is not forced down. Force the link down while we
 859                  * reconfigure the interface mode.
 860                  */
 861                 if (mode == MLO_AN_INBAND &&
 862                     p->interface != state->interface &&
 863                     chip->info->ops->port_set_link)
 864                         chip->info->ops->port_set_link(chip, port,
 865                                                        LINK_FORCED_DOWN);
 866
 867                 err = mv88e6xxx_port_config_interface(chip, port,
 868                                                       state->interface);
 869                 if (err && err != -EOPNOTSUPP)
 870                         goto err_unlock;
 871
 872                 err = mv88e6xxx_serdes_pcs_config(chip, port, mode,
 873                                                   state->interface,
 874                                                   state->advertising);
 875                 /* FIXME: we should restart negotiation if something changed -
 876                  * which is something we get if we convert to using phylinks
 877                  * PCS operations.
 878                  */
 879                 if (err > 0)
 880                         err = 0;
 881         }
 882
 883         /* Undo the forced down state above after completing configuration
 884          * irrespective of its state on entry, which allows the link to come
 885          * up in the in-band case where there is no separate SERDES. Also
 886          * ensure that the link can come up if the PPU is in use and we are
 887          * in PHY mode (we treat the PPU as an effective in-band mechanism.)
 888          */
 889         if (chip->info->ops->port_set_link &&
 890             ((mode == MLO_AN_INBAND && p->interface != state->interface) ||
 891              (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port))))
 892                 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
 893
 894         p->interface = state->interface;
 895
 896 err_unlock:
 897         mv88e6xxx_reg_unlock(chip);
 898
 899         if (err && err != -EOPNOTSUPP)
 900                 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
 901 }
 902
 903 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
 904                                     unsigned int mode,
 905                                     phy_interface_t interface)
 906 {
 907         struct mv88e6xxx_chip *chip = ds->priv;
 908         const struct mv88e6xxx_ops *ops;
 909         int err = 0;
 910
 911         ops = chip->info->ops;
 912
 913         mv88e6xxx_reg_lock(chip);
 914         /* Force the link down if we know the port may not be automatically
 915          * updated by the switch or if we are using fixed-link mode.
 916          */
 917         if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
 918              mode == MLO_AN_FIXED) && ops->port_sync_link)
 919                 err = ops->port_sync_link(chip, port, mode, false);
 920
 921         if (!err && ops->port_set_speed_duplex)
 922                 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED,
 923                                                  DUPLEX_UNFORCED);
 924         mv88e6xxx_reg_unlock(chip);
 925
 926         if (err)
 927                 dev_err(chip->dev,
 928                         "p%d: failed to force MAC link down\n", port);
 929 }
 930
 931 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
 932                                   unsigned int mode, phy_interface_t interface,
 933                                   struct phy_device *phydev,
 934                                   int speed, int duplex,
 935                                   bool tx_pause, bool rx_pause)
 936 {
 937         struct mv88e6xxx_chip *chip = ds->priv;
 938         const struct mv88e6xxx_ops *ops;
 939         int err = 0;
 940
 941         ops = chip->info->ops;
 942
 943         mv88e6xxx_reg_lock(chip);
 944         /* Configure and force the link up if we know that the port may not
 945          * automatically updated by the switch or if we are using fixed-link
 946          * mode.
 947          */
 948         if (!mv88e6xxx_port_ppu_updates(chip, port) ||
 949             mode == MLO_AN_FIXED) {
 950                 /* FIXME: for an automedia port, should we force the link
 951                  * down here - what if the link comes up due to "other" media
 952                  * while we're bringing the port up, how is the exclusivity
 953                  * handled in the Marvell hardware? E.g. port 2 on 88E6390
 954                  * shared between internal PHY and Serdes.
 955                  */
 956                 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed,
 957                                                    duplex);
 958                 if (err)
 959                         goto error;
 960
 961                 if (ops->port_set_speed_duplex) {
 962                         err = ops->port_set_speed_duplex(chip, port,
 963                                                          speed, duplex);
 964                         if (err && err != -EOPNOTSUPP)
 965                                 goto error;
 966                 }
 967
 968                 if (ops->port_sync_link)
 969                         err = ops->port_sync_link(chip, port, mode, true);
 970         }
 971 error:
 972         mv88e6xxx_reg_unlock(chip);
 973
 974         if (err && err != -EOPNOTSUPP)
 975                 dev_err(ds->dev,
 976                         "p%d: failed to configure MAC link up\n", port);
 977 }
 978
 979 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
 980 {
 981         if (!chip->info->ops->stats_snapshot)
 982                 return -EOPNOTSUPP;
 983
 984         return chip->info->ops->stats_snapshot(chip, port);
 985 }
 986
 987 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
 988         { "in_good_octets",             8, 0x00, STATS_TYPE_BANK0, },
 989         { "in_bad_octets",              4, 0x02, STATS_TYPE_BANK0, },
 990         { "in_unicast",                 4, 0x04, STATS_TYPE_BANK0, },
 991         { "in_broadcasts",              4, 0x06, STATS_TYPE_BANK0, },
 992         { "in_multicasts",              4, 0x07, STATS_TYPE_BANK0, },
 993         { "in_pause",                   4, 0x16, STATS_TYPE_BANK0, },
 994         { "in_undersize",               4, 0x18, STATS_TYPE_BANK0, },
 995         { "in_fragments",               4, 0x19, STATS_TYPE_BANK0, },
 996         { "in_oversize",                4, 0x1a, STATS_TYPE_BANK0, },
 997         { "in_jabber",                  4, 0x1b, STATS_TYPE_BANK0, },
 998         { "in_rx_error",                4, 0x1c, STATS_TYPE_BANK0, },
 999         { "in_fcs_error",               4, 0x1d, STATS_TYPE_BANK0, },
1000         { "out_octets",                 8, 0x0e, STATS_TYPE_BANK0, },
1001         { "out_unicast",                4, 0x10, STATS_TYPE_BANK0, },
1002         { "out_broadcasts",             4, 0x13, STATS_TYPE_BANK0, },
1003         { "out_multicasts",             4, 0x12, STATS_TYPE_BANK0, },
1004         { "out_pause",                  4, 0x15, STATS_TYPE_BANK0, },
1005         { "excessive",                  4, 0x11, STATS_TYPE_BANK0, },
1006         { "collisions",                 4, 0x1e, STATS_TYPE_BANK0, },
1007         { "deferred",                   4, 0x05, STATS_TYPE_BANK0, },
1008         { "single",                     4, 0x14, STATS_TYPE_BANK0, },
1009         { "multiple",                   4, 0x17, STATS_TYPE_BANK0, },
1010         { "out_fcs_error",              4, 0x03, STATS_TYPE_BANK0, },
1011         { "late",                       4, 0x1f, STATS_TYPE_BANK0, },
1012         { "hist_64bytes",               4, 0x08, STATS_TYPE_BANK0, },
1013         { "hist_65_127bytes",           4, 0x09, STATS_TYPE_BANK0, },
1014         { "hist_128_255bytes",          4, 0x0a, STATS_TYPE_BANK0, },
1015         { "hist_256_511bytes",          4, 0x0b, STATS_TYPE_BANK0, },
1016         { "hist_512_1023bytes",         4, 0x0c, STATS_TYPE_BANK0, },
1017         { "hist_1024_max_bytes",        4, 0x0d, STATS_TYPE_BANK0, },
1018         { "sw_in_discards",             4, 0x10, STATS_TYPE_PORT, },
1019         { "sw_in_filtered",             2, 0x12, STATS_TYPE_PORT, },
1020         { "sw_out_filtered",            2, 0x13, STATS_TYPE_PORT, },
1021         { "in_discards",                4, 0x00, STATS_TYPE_BANK1, },
1022         { "in_filtered",                4, 0x01, STATS_TYPE_BANK1, },
1023         { "in_accepted",                4, 0x02, STATS_TYPE_BANK1, },
1024         { "in_bad_accepted",            4, 0x03, STATS_TYPE_BANK1, },
1025         { "in_good_avb_class_a",        4, 0x04, STATS_TYPE_BANK1, },
1026         { "in_good_avb_class_b",        4, 0x05, STATS_TYPE_BANK1, },
1027         { "in_bad_avb_class_a",         4, 0x06, STATS_TYPE_BANK1, },
1028         { "in_bad_avb_class_b",         4, 0x07, STATS_TYPE_BANK1, },
1029         { "tcam_counter_0",             4, 0x08, STATS_TYPE_BANK1, },
1030         { "tcam_counter_1",             4, 0x09, STATS_TYPE_BANK1, },
1031         { "tcam_counter_2",             4, 0x0a, STATS_TYPE_BANK1, },
1032         { "tcam_counter_3",             4, 0x0b, STATS_TYPE_BANK1, },
1033         { "in_da_unknown",              4, 0x0e, STATS_TYPE_BANK1, },
1034         { "in_management",              4, 0x0f, STATS_TYPE_BANK1, },
1035         { "out_queue_0",                4, 0x10, STATS_TYPE_BANK1, },
1036         { "out_queue_1",                4, 0x11, STATS_TYPE_BANK1, },
1037         { "out_queue_2",                4, 0x12, STATS_TYPE_BANK1, },
1038         { "out_queue_3",                4, 0x13, STATS_TYPE_BANK1, },
1039         { "out_queue_4",                4, 0x14, STATS_TYPE_BANK1, },
1040         { "out_queue_5",                4, 0x15, STATS_TYPE_BANK1, },
1041         { "out_queue_6",                4, 0x16, STATS_TYPE_BANK1, },
1042         { "out_queue_7",                4, 0x17, STATS_TYPE_BANK1, },
1043         { "out_cut_through",            4, 0x18, STATS_TYPE_BANK1, },
1044         { "out_octets_a",               4, 0x1a, STATS_TYPE_BANK1, },
1045         { "out_octets_b",               4, 0x1b, STATS_TYPE_BANK1, },
1046         { "out_management",             4, 0x1f, STATS_TYPE_BANK1, },
1047 };
1048
1049 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
1050                                             struct mv88e6xxx_hw_stat *s,
1051                                             int port, u16 bank1_select,
1052                                             u16 histogram)
1053 {
1054         u32 low;
1055         u32 high = 0;
1056         u16 reg = 0;
1057         int err;
1058         u64 value;
1059
1060         switch (s->type) {
1061         case STATS_TYPE_PORT:
1062                 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
1063                 if (err)
1064                         return U64_MAX;
1065
1066                 low = reg;
1067                 if (s->size == 4) {
1068                         err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
1069                         if (err)
1070                                 return U64_MAX;
1071                         low |= ((u32)reg) << 16;
1072                 }
1073                 break;
1074         case STATS_TYPE_BANK1:
1075                 reg = bank1_select;
1076                 fallthrough;
1077         case STATS_TYPE_BANK0:
1078                 reg |= s->reg | histogram;
1079                 mv88e6xxx_g1_stats_read(chip, reg, &low);
1080                 if (s->size == 8)
1081                         mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
1082                 break;
1083         default:
1084                 return U64_MAX;
1085         }
1086         value = (((u64)high) << 32) | low;
1087         return value;
1088 }
1089
1090 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
1091                                        uint8_t *data, int types)
1092 {
1093         struct mv88e6xxx_hw_stat *stat;
1094         int i, j;
1095
1096         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1097                 stat = &mv88e6xxx_hw_stats[i];
1098                 if (stat->type & types) {
1099                         memcpy(data + j * ETH_GSTRING_LEN, stat->string,
1100                                ETH_GSTRING_LEN);
1101                         j++;
1102                 }
1103         }
1104
1105         return j;
1106 }
1107
1108 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
1109                                        uint8_t *data)
1110 {
1111         return mv88e6xxx_stats_get_strings(chip, data,
1112                                            STATS_TYPE_BANK0 | STATS_TYPE_PORT);
1113 }
1114
1115 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
1116                                        uint8_t *data)
1117 {
1118         return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
1119 }
1120
1121 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
1122                                        uint8_t *data)
1123 {
1124         return mv88e6xxx_stats_get_strings(chip, data,
1125                                            STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
1126 }
1127
1128 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
1129         "atu_member_violation",
1130         "atu_miss_violation",
1131         "atu_full_violation",
1132         "vtu_member_violation",
1133         "vtu_miss_violation",
1134 };
1135
1136 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
1137 {
1138         unsigned int i;
1139
1140         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
1141                 strscpy(data + i * ETH_GSTRING_LEN,
1142                         mv88e6xxx_atu_vtu_stats_strings[i],
1143                         ETH_GSTRING_LEN);
1144 }
1145
1146 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
1147                                   u32 stringset, uint8_t *data)
1148 {
1149         struct mv88e6xxx_chip *chip = ds->priv;
1150         int count = 0;
1151
1152         if (stringset != ETH_SS_STATS)
1153                 return;
1154
1155         mv88e6xxx_reg_lock(chip);
1156
1157         if (chip->info->ops->stats_get_strings)
1158                 count = chip->info->ops->stats_get_strings(chip, data);
1159
1160         if (chip->info->ops->serdes_get_strings) {
1161                 data += count * ETH_GSTRING_LEN;
1162                 count = chip->info->ops->serdes_get_strings(chip, port, data);
1163         }
1164
1165         data += count * ETH_GSTRING_LEN;
1166         mv88e6xxx_atu_vtu_get_strings(data);
1167
1168         mv88e6xxx_reg_unlock(chip);
1169 }
1170
1171 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
1172                                           int types)
1173 {
1174         struct mv88e6xxx_hw_stat *stat;
1175         int i, j;
1176
1177         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1178                 stat = &mv88e6xxx_hw_stats[i];
1179                 if (stat->type & types)
1180                         j++;
1181         }
1182         return j;
1183 }
1184
1185 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1186 {
1187         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1188                                               STATS_TYPE_PORT);
1189 }
1190
1191 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1192 {
1193         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1194 }
1195
1196 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1197 {
1198         return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1199                                               STATS_TYPE_BANK1);
1200 }
1201
1202 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1203 {
1204         struct mv88e6xxx_chip *chip = ds->priv;
1205         int serdes_count = 0;
1206         int count = 0;
1207
1208         if (sset != ETH_SS_STATS)
1209                 return 0;
1210
1211         mv88e6xxx_reg_lock(chip);
1212         if (chip->info->ops->stats_get_sset_count)
1213                 count = chip->info->ops->stats_get_sset_count(chip);
1214         if (count < 0)
1215                 goto out;
1216
1217         if (chip->info->ops->serdes_get_sset_count)
1218                 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1219                                                                       port);
1220         if (serdes_count < 0) {
1221                 count = serdes_count;
1222                 goto out;
1223         }
1224         count += serdes_count;
1225         count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1226
1227 out:
1228         mv88e6xxx_reg_unlock(chip);
1229
1230         return count;
1231 }
1232
1233 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1234                                      uint64_t *data, int types,
1235                                      u16 bank1_select, u16 histogram)
1236 {
1237         struct mv88e6xxx_hw_stat *stat;
1238         int i, j;
1239
1240         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1241                 stat = &mv88e6xxx_hw_stats[i];
1242                 if (stat->type & types) {
1243                         mv88e6xxx_reg_lock(chip);
1244                         data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1245                                                               bank1_select,
1246                                                               histogram);
1247                         mv88e6xxx_reg_unlock(chip);
1248
1249                         j++;
1250                 }
1251         }
1252         return j;
1253 }
1254
1255 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1256                                      uint64_t *data)
1257 {
1258         return mv88e6xxx_stats_get_stats(chip, port, data,
1259                                          STATS_TYPE_BANK0 | STATS_TYPE_PORT,
1260                                          0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1261 }
1262
1263 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1264                                      uint64_t *data)
1265 {
1266         return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
1267                                          0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1268 }
1269
1270 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1271                                      uint64_t *data)
1272 {
1273         return mv88e6xxx_stats_get_stats(chip, port, data,
1274                                          STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1275                                          MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1276                                          MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1277 }
1278
1279 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1280                                      uint64_t *data)
1281 {
1282         return mv88e6xxx_stats_get_stats(chip, port, data,
1283                                          STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1284                                          MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1285                                          0);
1286 }
1287
1288 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1289                                         uint64_t *data)
1290 {
1291         *data++ = chip->ports[port].atu_member_violation;
1292         *data++ = chip->ports[port].atu_miss_violation;
1293         *data++ = chip->ports[port].atu_full_violation;
1294         *data++ = chip->ports[port].vtu_member_violation;
1295         *data++ = chip->ports[port].vtu_miss_violation;
1296 }
1297
1298 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1299                                 uint64_t *data)
1300 {
1301         int count = 0;
1302
1303         if (chip->info->ops->stats_get_stats)
1304                 count = chip->info->ops->stats_get_stats(chip, port, data);
1305
1306         mv88e6xxx_reg_lock(chip);
1307         if (chip->info->ops->serdes_get_stats) {
1308                 data += count;
1309                 count = chip->info->ops->serdes_get_stats(chip, port, data);
1310         }
1311         data += count;
1312         mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1313         mv88e6xxx_reg_unlock(chip);
1314 }
1315
1316 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1317                                         uint64_t *data)
1318 {
1319         struct mv88e6xxx_chip *chip = ds->priv;
1320         int ret;
1321
1322         mv88e6xxx_reg_lock(chip);
1323
1324         ret = mv88e6xxx_stats_snapshot(chip, port);
1325         mv88e6xxx_reg_unlock(chip);
1326
1327         if (ret < 0)
1328                 return;
1329
1330         mv88e6xxx_get_stats(chip, port, data);
1331
1332 }
1333
1334 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1335 {
1336         struct mv88e6xxx_chip *chip = ds->priv;
1337         int len;
1338
1339         len = 32 * sizeof(u16);
1340         if (chip->info->ops->serdes_get_regs_len)
1341                 len += chip->info->ops->serdes_get_regs_len(chip, port);
1342
1343         return len;
1344 }
1345
1346 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1347                                struct ethtool_regs *regs, void *_p)
1348 {
1349         struct mv88e6xxx_chip *chip = ds->priv;
1350         int err;
1351         u16 reg;
1352         u16 *p = _p;
1353         int i;
1354
1355         regs->version = chip->info->prod_num;
1356
1357         memset(p, 0xff, 32 * sizeof(u16));
1358
1359         mv88e6xxx_reg_lock(chip);
1360
1361         for (i = 0; i < 32; i++) {
1362
1363                 err = mv88e6xxx_port_read(chip, port, i, &reg);
1364                 if (!err)
1365                         p[i] = reg;
1366         }
1367
1368         if (chip->info->ops->serdes_get_regs)
1369                 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1370
1371         mv88e6xxx_reg_unlock(chip);
1372 }
1373
1374 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1375                                  struct ethtool_eee *e)
1376 {
1377         /* Nothing to do on the port's MAC */
1378         return 0;
1379 }
1380
1381 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1382                                  struct ethtool_eee *e)
1383 {
1384         /* Nothing to do on the port's MAC */
1385         return 0;
1386 }
1387
1388 /* Mask of the local ports allowed to receive frames from a given fabric port */
1389 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1390 {
1391         struct dsa_switch *ds = chip->ds;
1392         struct dsa_switch_tree *dst = ds->dst;
1393         struct dsa_port *dp, *other_dp;
1394         bool found = false;
1395         u16 pvlan;
1396
1397         /* dev is a physical switch */
1398         if (dev <= dst->last_switch) {
1399                 list_for_each_entry(dp, &dst->ports, list) {
1400                         if (dp->ds->index == dev && dp->index == port) {
1401                                 /* dp might be a DSA link or a user port, so it
1402                                  * might or might not have a bridge.
1403                                  * Use the "found" variable for both cases.
1404                                  */
1405                                 found = true;
1406                                 break;
1407                         }
1408                 }
1409         /* dev is a virtual bridge */
1410         } else {
1411                 list_for_each_entry(dp, &dst->ports, list) {
1412                         unsigned int bridge_num = dsa_port_bridge_num_get(dp);
1413
1414                         if (!bridge_num)
1415                                 continue;
1416
1417                         if (bridge_num + dst->last_switch != dev)
1418                                 continue;
1419
1420                         found = true;
1421                         break;
1422                 }
1423         }
1424
1425         /* Prevent frames from unknown switch or virtual bridge */
1426         if (!found)
1427                 return 0;
1428
1429         /* Frames from DSA links and CPU ports can egress any local port */
1430         if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1431                 return mv88e6xxx_port_mask(chip);
1432
1433         pvlan = 0;
1434
1435         /* Frames from standalone user ports can only egress on the
1436          * upstream port.
1437          */
1438         if (!dsa_port_bridge_dev_get(dp))
1439                 return BIT(dsa_switch_upstream_port(ds));
1440
1441         /* Frames from bridged user ports can egress any local DSA
1442          * links and CPU ports, as well as any local member of their
1443          * bridge group.
1444          */
1445         dsa_switch_for_each_port(other_dp, ds)
1446                 if (other_dp->type == DSA_PORT_TYPE_CPU ||
1447                     other_dp->type == DSA_PORT_TYPE_DSA ||
1448                     dsa_port_bridge_same(dp, other_dp))
1449                         pvlan |= BIT(other_dp->index);
1450
1451         return pvlan;
1452 }
1453
1454 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1455 {
1456         u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1457
1458         /* prevent frames from going back out of the port they came in on */
1459         output_ports &= ~BIT(port);
1460
1461         return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1462 }
1463
1464 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1465                                          u8 state)
1466 {
1467         struct mv88e6xxx_chip *chip = ds->priv;
1468         int err;
1469
1470         mv88e6xxx_reg_lock(chip);
1471         err = mv88e6xxx_port_set_state(chip, port, state);
1472         mv88e6xxx_reg_unlock(chip);
1473
1474         if (err)
1475                 dev_err(ds->dev, "p%d: failed to update state\n", port);
1476 }
1477
1478 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1479 {
1480         int err;
1481
1482         if (chip->info->ops->ieee_pri_map) {
1483                 err = chip->info->ops->ieee_pri_map(chip);
1484                 if (err)
1485                         return err;
1486         }
1487
1488         if (chip->info->ops->ip_pri_map) {
1489                 err = chip->info->ops->ip_pri_map(chip);
1490                 if (err)
1491                         return err;
1492         }
1493
1494         return 0;
1495 }
1496
1497 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1498 {
1499         struct dsa_switch *ds = chip->ds;
1500         int target, port;
1501         int err;
1502
1503         if (!chip->info->global2_addr)
1504                 return 0;
1505
1506         /* Initialize the routing port to the 32 possible target devices */
1507         for (target = 0; target < 32; target++) {
1508                 port = dsa_routing_port(ds, target);
1509                 if (port == ds->num_ports)
1510                         port = 0x1f;
1511
1512                 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1513                 if (err)
1514                         return err;
1515         }
1516
1517         if (chip->info->ops->set_cascade_port) {
1518                 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1519                 err = chip->info->ops->set_cascade_port(chip, port);
1520                 if (err)
1521                         return err;
1522         }
1523
1524         err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1525         if (err)
1526                 return err;
1527
1528         return 0;
1529 }
1530
1531 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1532 {
1533         /* Clear all trunk masks and mapping */
1534         if (chip->info->global2_addr)
1535                 return mv88e6xxx_g2_trunk_clear(chip);
1536
1537         return 0;
1538 }
1539
1540 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1541 {
1542         if (chip->info->ops->rmu_disable)
1543                 return chip->info->ops->rmu_disable(chip);
1544
1545         return 0;
1546 }
1547
1548 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1549 {
1550         if (chip->info->ops->pot_clear)
1551                 return chip->info->ops->pot_clear(chip);
1552
1553         return 0;
1554 }
1555
1556 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1557 {
1558         if (chip->info->ops->mgmt_rsvd2cpu)
1559                 return chip->info->ops->mgmt_rsvd2cpu(chip);
1560
1561         return 0;
1562 }
1563
1564 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1565 {
1566         int err;
1567
1568         err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1569         if (err)
1570                 return err;
1571
1572         /* The chips that have a "learn2all" bit in Global1, ATU
1573          * Control are precisely those whose port registers have a
1574          * Message Port bit in Port Control 1 and hence implement
1575          * ->port_setup_message_port.
1576          */
1577         if (chip->info->ops->port_setup_message_port) {
1578                 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1579                 if (err)
1580                         return err;
1581         }
1582
1583         return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1584 }
1585
1586 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1587 {
1588         int port;
1589         int err;
1590
1591         if (!chip->info->ops->irl_init_all)
1592                 return 0;
1593
1594         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1595                 /* Disable ingress rate limiting by resetting all per port
1596                  * ingress rate limit resources to their initial state.
1597                  */
1598                 err = chip->info->ops->irl_init_all(chip, port);
1599                 if (err)
1600                         return err;
1601         }
1602
1603         return 0;
1604 }
1605
1606 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1607 {
1608         if (chip->info->ops->set_switch_mac) {
1609                 u8 addr[ETH_ALEN];
1610
1611                 eth_random_addr(addr);
1612
1613                 return chip->info->ops->set_switch_mac(chip, addr);
1614         }
1615
1616         return 0;
1617 }
1618
1619 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1620 {
1621         struct dsa_switch_tree *dst = chip->ds->dst;
1622         struct dsa_switch *ds;
1623         struct dsa_port *dp;
1624         u16 pvlan = 0;
1625
1626         if (!mv88e6xxx_has_pvt(chip))
1627                 return 0;
1628
1629         /* Skip the local source device, which uses in-chip port VLAN */
1630         if (dev != chip->ds->index) {
1631                 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1632
1633                 ds = dsa_switch_find(dst->index, dev);
1634                 dp = ds ? dsa_to_port(ds, port) : NULL;
1635                 if (dp && dp->lag) {
1636                         /* As the PVT is used to limit flooding of
1637                          * FORWARD frames, which use the LAG ID as the
1638                          * source port, we must translate dev/port to
1639                          * the special "LAG device" in the PVT, using
1640                          * the LAG ID (one-based) as the port number
1641                          * (zero-based).
1642                          */
1643                         dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK;
1644                         port = dsa_port_lag_id_get(dp) - 1;
1645                 }
1646         }
1647
1648         return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1649 }
1650
1651 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1652 {
1653         int dev, port;
1654         int err;
1655
1656         if (!mv88e6xxx_has_pvt(chip))
1657                 return 0;
1658
1659         /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1660          * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1661          */
1662         err = mv88e6xxx_g2_misc_4_bit_port(chip);
1663         if (err)
1664                 return err;
1665
1666         for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1667                 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1668                         err = mv88e6xxx_pvt_map(chip, dev, port);
1669                         if (err)
1670                                 return err;
1671                 }
1672         }
1673
1674         return 0;
1675 }
1676
1677 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port,
1678                                        u16 fid)
1679 {
1680         if (dsa_to_port(chip->ds, port)->lag)
1681                 /* Hardware is incapable of fast-aging a LAG through a
1682                  * regular ATU move operation. Until we have something
1683                  * more fancy in place this is a no-op.
1684                  */
1685                 return -EOPNOTSUPP;
1686
1687         return mv88e6xxx_g1_atu_remove(chip, fid, port, false);
1688 }
1689
1690 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1691 {
1692         struct mv88e6xxx_chip *chip = ds->priv;
1693         int err;
1694
1695         mv88e6xxx_reg_lock(chip);
1696         err = mv88e6xxx_port_fast_age_fid(chip, port, 0);
1697         mv88e6xxx_reg_unlock(chip);
1698
1699         if (err)
1700                 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n",
1701                         port, err);
1702 }
1703
1704 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1705 {
1706         if (!mv88e6xxx_max_vid(chip))
1707                 return 0;
1708
1709         return mv88e6xxx_g1_vtu_flush(chip);
1710 }
1711
1712 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1713                              struct mv88e6xxx_vtu_entry *entry)
1714 {
1715         int err;
1716
1717         if (!chip->info->ops->vtu_getnext)
1718                 return -EOPNOTSUPP;
1719
1720         entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip);
1721         entry->valid = false;
1722
1723         err = chip->info->ops->vtu_getnext(chip, entry);
1724
1725         if (entry->vid != vid)
1726                 entry->valid = false;
1727
1728         return err;
1729 }
1730
1731 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
1732                        int (*cb)(struct mv88e6xxx_chip *chip,
1733                                  const struct mv88e6xxx_vtu_entry *entry,
1734                                  void *priv),
1735                        void *priv)
1736 {
1737         struct mv88e6xxx_vtu_entry entry = {
1738                 .vid = mv88e6xxx_max_vid(chip),
1739                 .valid = false,
1740         };
1741         int err;
1742
1743         if (!chip->info->ops->vtu_getnext)
1744                 return -EOPNOTSUPP;
1745
1746         do {
1747                 err = chip->info->ops->vtu_getnext(chip, &entry);
1748                 if (err)
1749                         return err;
1750
1751                 if (!entry.valid)
1752                         break;
1753
1754                 err = cb(chip, &entry, priv);
1755                 if (err)
1756                         return err;
1757         } while (entry.vid < mv88e6xxx_max_vid(chip));
1758
1759         return 0;
1760 }
1761
1762 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1763                                    struct mv88e6xxx_vtu_entry *entry)
1764 {
1765         if (!chip->info->ops->vtu_loadpurge)
1766                 return -EOPNOTSUPP;
1767
1768         return chip->info->ops->vtu_loadpurge(chip, entry);
1769 }
1770
1771 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip,
1772                                   const struct mv88e6xxx_vtu_entry *entry,
1773                                   void *_fid_bitmap)
1774 {
1775         unsigned long *fid_bitmap = _fid_bitmap;
1776
1777         set_bit(entry->fid, fid_bitmap);
1778         return 0;
1779 }
1780
1781 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
1782 {
1783         bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1784
1785         /* Every FID has an associated VID, so walking the VTU
1786          * will discover the full set of FIDs in use.
1787          */
1788         return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap);
1789 }
1790
1791 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1792 {
1793         DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1794         int err;
1795
1796         err = mv88e6xxx_fid_map(chip, fid_bitmap);
1797         if (err)
1798                 return err;
1799
1800         *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID);
1801         if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1802                 return -ENOSPC;
1803
1804         /* Clear the database */
1805         return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1806 }
1807
1808 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1809                                    struct mv88e6xxx_stu_entry *entry)
1810 {
1811         if (!chip->info->ops->stu_loadpurge)
1812                 return -EOPNOTSUPP;
1813
1814         return chip->info->ops->stu_loadpurge(chip, entry);
1815 }
1816
1817 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip)
1818 {
1819         struct mv88e6xxx_stu_entry stu = {
1820                 .valid = true,
1821                 .sid = 0
1822         };
1823
1824         if (!mv88e6xxx_has_stu(chip))
1825                 return 0;
1826
1827         /* Make sure that SID 0 is always valid. This is used by VTU
1828          * entries that do not make use of the STU, e.g. when creating
1829          * a VLAN upper on a port that is also part of a VLAN
1830          * filtering bridge.
1831          */
1832         return mv88e6xxx_stu_loadpurge(chip, &stu);
1833 }
1834
1835 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid)
1836 {
1837         DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 };
1838         struct mv88e6xxx_mst *mst;
1839
1840         __set_bit(0, busy);
1841
1842         list_for_each_entry(mst, &chip->msts, node)
1843                 __set_bit(mst->stu.sid, busy);
1844
1845         *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID);
1846
1847         return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0;
1848 }
1849
1850 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid)
1851 {
1852         struct mv88e6xxx_mst *mst, *tmp;
1853         int err;
1854
1855         if (!sid)
1856                 return 0;
1857
1858         list_for_each_entry_safe(mst, tmp, &chip->msts, node) {
1859                 if (mst->stu.sid != sid)
1860                         continue;
1861
1862                 if (!refcount_dec_and_test(&mst->refcnt))
1863                         return 0;
1864
1865                 mst->stu.valid = false;
1866                 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1867                 if (err) {
1868                         refcount_set(&mst->refcnt, 1);
1869                         return err;
1870                 }
1871
1872                 list_del(&mst->node);
1873                 kfree(mst);
1874                 return 0;
1875         }
1876
1877         return -ENOENT;
1878 }
1879
1880 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br,
1881                              u16 msti, u8 *sid)
1882 {
1883         struct mv88e6xxx_mst *mst;
1884         int err, i;
1885
1886         if (!mv88e6xxx_has_stu(chip)) {
1887                 err = -EOPNOTSUPP;
1888                 goto err;
1889         }
1890
1891         if (!msti) {
1892                 *sid = 0;
1893                 return 0;
1894         }
1895
1896         list_for_each_entry(mst, &chip->msts, node) {
1897                 if (mst->br == br && mst->msti == msti) {
1898                         refcount_inc(&mst->refcnt);
1899                         *sid = mst->stu.sid;
1900                         return 0;
1901                 }
1902         }
1903
1904         err = mv88e6xxx_sid_get(chip, sid);
1905         if (err)
1906                 goto err;
1907
1908         mst = kzalloc(sizeof(*mst), GFP_KERNEL);
1909         if (!mst) {
1910                 err = -ENOMEM;
1911                 goto err;
1912         }
1913
1914         INIT_LIST_HEAD(&mst->node);
1915         refcount_set(&mst->refcnt, 1);
1916         mst->br = br;
1917         mst->msti = msti;
1918         mst->stu.valid = true;
1919         mst->stu.sid = *sid;
1920
1921         /* The bridge starts out all ports in the disabled state. But
1922          * a STU state of disabled means to go by the port-global
1923          * state. So we set all user port's initial state to blocking,
1924          * to match the bridge's behavior.
1925          */
1926         for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
1927                 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ?
1928                         MV88E6XXX_PORT_CTL0_STATE_BLOCKING :
1929                         MV88E6XXX_PORT_CTL0_STATE_DISABLED;
1930
1931         err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1932         if (err)
1933                 goto err_free;
1934
1935         list_add_tail(&mst->node, &chip->msts);
1936         return 0;
1937
1938 err_free:
1939         kfree(mst);
1940 err:
1941         return err;
1942 }
1943
1944 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port,
1945                                         const struct switchdev_mst_state *st)
1946 {
1947         struct dsa_port *dp = dsa_to_port(ds, port);
1948         struct mv88e6xxx_chip *chip = ds->priv;
1949         struct mv88e6xxx_mst *mst;
1950         u8 state;
1951         int err;
1952
1953         if (!mv88e6xxx_has_stu(chip))
1954                 return -EOPNOTSUPP;
1955
1956         switch (st->state) {
1957         case BR_STATE_DISABLED:
1958         case BR_STATE_BLOCKING:
1959         case BR_STATE_LISTENING:
1960                 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
1961                 break;
1962         case BR_STATE_LEARNING:
1963                 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
1964                 break;
1965         case BR_STATE_FORWARDING:
1966                 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
1967                 break;
1968         default:
1969                 return -EINVAL;
1970         }
1971
1972         list_for_each_entry(mst, &chip->msts, node) {
1973                 if (mst->br == dsa_port_bridge_dev_get(dp) &&
1974                     mst->msti == st->msti) {
1975                         if (mst->stu.state[port] == state)
1976                                 return 0;
1977
1978                         mst->stu.state[port] = state;
1979                         mv88e6xxx_reg_lock(chip);
1980                         err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1981                         mv88e6xxx_reg_unlock(chip);
1982                         return err;
1983                 }
1984         }
1985
1986         return -ENOENT;
1987 }
1988
1989 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1990                                         u16 vid)
1991 {
1992         struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
1993         struct mv88e6xxx_chip *chip = ds->priv;
1994         struct mv88e6xxx_vtu_entry vlan;
1995         int err;
1996
1997         /* DSA and CPU ports have to be members of multiple vlans */
1998         if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp))
1999                 return 0;
2000
2001         err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2002         if (err)
2003                 return err;
2004
2005         if (!vlan.valid)
2006                 return 0;
2007
2008         dsa_switch_for_each_user_port(other_dp, ds) {
2009                 struct net_device *other_br;
2010
2011                 if (vlan.member[other_dp->index] ==
2012                     MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2013                         continue;
2014
2015                 if (dsa_port_bridge_same(dp, other_dp))
2016                         break; /* same bridge, check next VLAN */
2017
2018                 other_br = dsa_port_bridge_dev_get(other_dp);
2019                 if (!other_br)
2020                         continue;
2021
2022                 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
2023                         port, vlan.vid, other_dp->index, netdev_name(other_br));
2024                 return -EOPNOTSUPP;
2025         }
2026
2027         return 0;
2028 }
2029
2030 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port)
2031 {
2032         struct dsa_port *dp = dsa_to_port(chip->ds, port);
2033         struct net_device *br = dsa_port_bridge_dev_get(dp);
2034         struct mv88e6xxx_port *p = &chip->ports[port];
2035         u16 pvid = MV88E6XXX_VID_STANDALONE;
2036         bool drop_untagged = false;
2037         int err;
2038
2039         if (br) {
2040                 if (br_vlan_enabled(br)) {
2041                         pvid = p->bridge_pvid.vid;
2042                         drop_untagged = !p->bridge_pvid.valid;
2043                 } else {
2044                         pvid = MV88E6XXX_VID_BRIDGED;
2045                 }
2046         }
2047
2048         err = mv88e6xxx_port_set_pvid(chip, port, pvid);
2049         if (err)
2050                 return err;
2051
2052         return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged);
2053 }
2054
2055 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2056                                          bool vlan_filtering,
2057                                          struct netlink_ext_ack *extack)
2058 {
2059         struct mv88e6xxx_chip *chip = ds->priv;
2060         u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
2061                 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
2062         int err;
2063
2064         if (!mv88e6xxx_max_vid(chip))
2065                 return -EOPNOTSUPP;
2066
2067         mv88e6xxx_reg_lock(chip);
2068
2069         err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
2070         if (err)
2071                 goto unlock;
2072
2073         err = mv88e6xxx_port_commit_pvid(chip, port);
2074         if (err)
2075                 goto unlock;
2076
2077 unlock:
2078         mv88e6xxx_reg_unlock(chip);
2079
2080         return err;
2081 }
2082
2083 static int
2084 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2085                             const struct switchdev_obj_port_vlan *vlan)
2086 {
2087         struct mv88e6xxx_chip *chip = ds->priv;
2088         int err;
2089
2090         if (!mv88e6xxx_max_vid(chip))
2091                 return -EOPNOTSUPP;
2092
2093         /* If the requested port doesn't belong to the same bridge as the VLAN
2094          * members, do not support it (yet) and fallback to software VLAN.
2095          */
2096         mv88e6xxx_reg_lock(chip);
2097         err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid);
2098         mv88e6xxx_reg_unlock(chip);
2099
2100         return err;
2101 }
2102
2103 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2104                                         const unsigned char *addr, u16 vid,
2105                                         u8 state)
2106 {
2107         struct mv88e6xxx_atu_entry entry;
2108         struct mv88e6xxx_vtu_entry vlan;
2109         u16 fid;
2110         int err;
2111
2112         /* Ports have two private address databases: one for when the port is
2113          * standalone and one for when the port is under a bridge and the
2114          * 802.1Q mode is disabled. When the port is standalone, DSA wants its
2115          * address database to remain 100% empty, so we never load an ATU entry
2116          * into a standalone port's database. Therefore, translate the null
2117          * VLAN ID into the port's database used for VLAN-unaware bridging.
2118          */
2119         if (vid == 0) {
2120                 fid = MV88E6XXX_FID_BRIDGED;
2121         } else {
2122                 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2123                 if (err)
2124                         return err;
2125
2126                 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
2127                 if (!vlan.valid)
2128                         return -EOPNOTSUPP;
2129
2130                 fid = vlan.fid;
2131         }
2132
2133         entry.state = 0;
2134         ether_addr_copy(entry.mac, addr);
2135         eth_addr_dec(entry.mac);
2136
2137         err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
2138         if (err)
2139                 return err;
2140
2141         /* Initialize a fresh ATU entry if it isn't found */
2142         if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
2143                 memset(&entry, 0, sizeof(entry));
2144                 ether_addr_copy(entry.mac, addr);
2145         }
2146
2147         /* Purge the ATU entry only if no port is using it anymore */
2148         if (!state) {
2149                 entry.portvec &= ~BIT(port);
2150                 if (!entry.portvec)
2151                         entry.state = 0;
2152         } else {
2153                 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
2154                         entry.portvec = BIT(port);
2155                 else
2156                         entry.portvec |= BIT(port);
2157
2158                 entry.state = state;
2159         }
2160
2161         return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
2162 }
2163
2164 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
2165                                   const struct mv88e6xxx_policy *policy)
2166 {
2167         enum mv88e6xxx_policy_mapping mapping = policy->mapping;
2168         enum mv88e6xxx_policy_action action = policy->action;
2169         const u8 *addr = policy->addr;
2170         u16 vid = policy->vid;
2171         u8 state;
2172         int err;
2173         int id;
2174
2175         if (!chip->info->ops->port_set_policy)
2176                 return -EOPNOTSUPP;
2177
2178         switch (mapping) {
2179         case MV88E6XXX_POLICY_MAPPING_DA:
2180         case MV88E6XXX_POLICY_MAPPING_SA:
2181                 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2182                         state = 0; /* Dissociate the port and address */
2183                 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2184                          is_multicast_ether_addr(addr))
2185                         state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
2186                 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2187                          is_unicast_ether_addr(addr))
2188                         state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
2189                 else
2190                         return -EOPNOTSUPP;
2191
2192                 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2193                                                    state);
2194                 if (err)
2195                         return err;
2196                 break;
2197         default:
2198                 return -EOPNOTSUPP;
2199         }
2200
2201         /* Skip the port's policy clearing if the mapping is still in use */
2202         if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2203                 idr_for_each_entry(&chip->policies, policy, id)
2204                         if (policy->port == port &&
2205                             policy->mapping == mapping &&
2206                             policy->action != action)
2207                                 return 0;
2208
2209         return chip->info->ops->port_set_policy(chip, port, mapping, action);
2210 }
2211
2212 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
2213                                    struct ethtool_rx_flow_spec *fs)
2214 {
2215         struct ethhdr *mac_entry = &fs->h_u.ether_spec;
2216         struct ethhdr *mac_mask = &fs->m_u.ether_spec;
2217         enum mv88e6xxx_policy_mapping mapping;
2218         enum mv88e6xxx_policy_action action;
2219         struct mv88e6xxx_policy *policy;
2220         u16 vid = 0;
2221         u8 *addr;
2222         int err;
2223         int id;
2224
2225         if (fs->location != RX_CLS_LOC_ANY)
2226                 return -EINVAL;
2227
2228         if (fs->ring_cookie == RX_CLS_FLOW_DISC)
2229                 action = MV88E6XXX_POLICY_ACTION_DISCARD;
2230         else
2231                 return -EOPNOTSUPP;
2232
2233         switch (fs->flow_type & ~FLOW_EXT) {
2234         case ETHER_FLOW:
2235                 if (!is_zero_ether_addr(mac_mask->h_dest) &&
2236                     is_zero_ether_addr(mac_mask->h_source)) {
2237                         mapping = MV88E6XXX_POLICY_MAPPING_DA;
2238                         addr = mac_entry->h_dest;
2239                 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
2240                     !is_zero_ether_addr(mac_mask->h_source)) {
2241                         mapping = MV88E6XXX_POLICY_MAPPING_SA;
2242                         addr = mac_entry->h_source;
2243                 } else {
2244                         /* Cannot support DA and SA mapping in the same rule */
2245                         return -EOPNOTSUPP;
2246                 }
2247                 break;
2248         default:
2249                 return -EOPNOTSUPP;
2250         }
2251
2252         if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
2253                 if (fs->m_ext.vlan_tci != htons(0xffff))
2254                         return -EOPNOTSUPP;
2255                 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
2256         }
2257
2258         idr_for_each_entry(&chip->policies, policy, id) {
2259                 if (policy->port == port && policy->mapping == mapping &&
2260                     policy->action == action && policy->vid == vid &&
2261                     ether_addr_equal(policy->addr, addr))
2262                         return -EEXIST;
2263         }
2264
2265         policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
2266         if (!policy)
2267                 return -ENOMEM;
2268
2269         fs->location = 0;
2270         err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
2271                             GFP_KERNEL);
2272         if (err) {
2273                 devm_kfree(chip->dev, policy);
2274                 return err;
2275         }
2276
2277         memcpy(&policy->fs, fs, sizeof(*fs));
2278         ether_addr_copy(policy->addr, addr);
2279         policy->mapping = mapping;
2280         policy->action = action;
2281         policy->port = port;
2282         policy->vid = vid;
2283
2284         err = mv88e6xxx_policy_apply(chip, port, policy);
2285         if (err) {
2286                 idr_remove(&chip->policies, fs->location);
2287                 devm_kfree(chip->dev, policy);
2288                 return err;
2289         }
2290
2291         return 0;
2292 }
2293
2294 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
2295                                struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
2296 {
2297         struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2298         struct mv88e6xxx_chip *chip = ds->priv;
2299         struct mv88e6xxx_policy *policy;
2300         int err;
2301         int id;
2302
2303         mv88e6xxx_reg_lock(chip);
2304
2305         switch (rxnfc->cmd) {
2306         case ETHTOOL_GRXCLSRLCNT:
2307                 rxnfc->data = 0;
2308                 rxnfc->data |= RX_CLS_LOC_SPECIAL;
2309                 rxnfc->rule_cnt = 0;
2310                 idr_for_each_entry(&chip->policies, policy, id)
2311                         if (policy->port == port)
2312                                 rxnfc->rule_cnt++;
2313                 err = 0;
2314                 break;
2315         case ETHTOOL_GRXCLSRULE:
2316                 err = -ENOENT;
2317                 policy = idr_find(&chip->policies, fs->location);
2318                 if (policy) {
2319                         memcpy(fs, &policy->fs, sizeof(*fs));
2320                         err = 0;
2321                 }
2322                 break;
2323         case ETHTOOL_GRXCLSRLALL:
2324                 rxnfc->data = 0;
2325                 rxnfc->rule_cnt = 0;
2326                 idr_for_each_entry(&chip->policies, policy, id)
2327                         if (policy->port == port)
2328                                 rule_locs[rxnfc->rule_cnt++] = id;
2329                 err = 0;
2330                 break;
2331         default:
2332                 err = -EOPNOTSUPP;
2333                 break;
2334         }
2335
2336         mv88e6xxx_reg_unlock(chip);
2337
2338         return err;
2339 }
2340
2341 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
2342                                struct ethtool_rxnfc *rxnfc)
2343 {
2344         struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2345         struct mv88e6xxx_chip *chip = ds->priv;
2346         struct mv88e6xxx_policy *policy;
2347         int err;
2348
2349         mv88e6xxx_reg_lock(chip);
2350
2351         switch (rxnfc->cmd) {
2352         case ETHTOOL_SRXCLSRLINS:
2353                 err = mv88e6xxx_policy_insert(chip, port, fs);
2354                 break;
2355         case ETHTOOL_SRXCLSRLDEL:
2356                 err = -ENOENT;
2357                 policy = idr_remove(&chip->policies, fs->location);
2358                 if (policy) {
2359                         policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
2360                         err = mv88e6xxx_policy_apply(chip, port, policy);
2361                         devm_kfree(chip->dev, policy);
2362                 }
2363                 break;
2364         default:
2365                 err = -EOPNOTSUPP;
2366                 break;
2367         }
2368
2369         mv88e6xxx_reg_unlock(chip);
2370
2371         return err;
2372 }
2373
2374 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
2375                                         u16 vid)
2376 {
2377         u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2378         u8 broadcast[ETH_ALEN];
2379
2380         eth_broadcast_addr(broadcast);
2381
2382         return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
2383 }
2384
2385 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
2386 {
2387         int port;
2388         int err;
2389
2390         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2391                 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2392                 struct net_device *brport;
2393
2394                 if (dsa_is_unused_port(chip->ds, port))
2395                         continue;
2396
2397                 brport = dsa_port_to_bridge_port(dp);
2398                 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD))
2399                         /* Skip bridged user ports where broadcast
2400                          * flooding is disabled.
2401                          */
2402                         continue;
2403
2404                 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
2405                 if (err)
2406                         return err;
2407         }
2408
2409         return 0;
2410 }
2411
2412 struct mv88e6xxx_port_broadcast_sync_ctx {
2413         int port;
2414         bool flood;
2415 };
2416
2417 static int
2418 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip,
2419                                    const struct mv88e6xxx_vtu_entry *vlan,
2420                                    void *_ctx)
2421 {
2422         struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx;
2423         u8 broadcast[ETH_ALEN];
2424         u8 state;
2425
2426         if (ctx->flood)
2427                 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2428         else
2429                 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED;
2430
2431         eth_broadcast_addr(broadcast);
2432
2433         return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast,
2434                                             vlan->vid, state);
2435 }
2436
2437 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port,
2438                                          bool flood)
2439 {
2440         struct mv88e6xxx_port_broadcast_sync_ctx ctx = {
2441                 .port = port,
2442                 .flood = flood,
2443         };
2444         struct mv88e6xxx_vtu_entry vid0 = {
2445                 .vid = 0,
2446         };
2447         int err;
2448
2449         /* Update the port's private database... */
2450         err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx);
2451         if (err)
2452                 return err;
2453
2454         /* ...and the database for all VLANs. */
2455         return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan,
2456                                   &ctx);
2457 }
2458
2459 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
2460                                     u16 vid, u8 member, bool warn)
2461 {
2462         const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2463         struct mv88e6xxx_vtu_entry vlan;
2464         int i, err;
2465
2466         err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2467         if (err)
2468                 return err;
2469
2470         if (!vlan.valid) {
2471                 memset(&vlan, 0, sizeof(vlan));
2472
2473                 if (vid == MV88E6XXX_VID_STANDALONE)
2474                         vlan.policy = true;
2475
2476                 err = mv88e6xxx_atu_new(chip, &vlan.fid);
2477                 if (err)
2478                         return err;
2479
2480                 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2481                         if (i == port)
2482                                 vlan.member[i] = member;
2483                         else
2484                                 vlan.member[i] = non_member;
2485
2486                 vlan.vid = vid;
2487                 vlan.valid = true;
2488
2489                 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2490                 if (err)
2491                         return err;
2492
2493                 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
2494                 if (err)
2495                         return err;
2496         } else if (vlan.member[port] != member) {
2497                 vlan.member[port] = member;
2498
2499                 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2500                 if (err)
2501                         return err;
2502         } else if (warn) {
2503                 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
2504                          port, vid);
2505         }
2506
2507         return 0;
2508 }
2509
2510 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2511                                    const struct switchdev_obj_port_vlan *vlan,
2512                                    struct netlink_ext_ack *extack)
2513 {
2514         struct mv88e6xxx_chip *chip = ds->priv;
2515         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2516         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2517         struct mv88e6xxx_port *p = &chip->ports[port];
2518         bool warn;
2519         u8 member;
2520         int err;
2521
2522         if (!vlan->vid)
2523                 return 0;
2524
2525         err = mv88e6xxx_port_vlan_prepare(ds, port, vlan);
2526         if (err)
2527                 return err;
2528
2529         if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
2530                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
2531         else if (untagged)
2532                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
2533         else
2534                 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
2535
2536         /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port
2537          * and then the CPU port. Do not warn for duplicates for the CPU port.
2538          */
2539         warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2540
2541         mv88e6xxx_reg_lock(chip);
2542
2543         err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn);
2544         if (err) {
2545                 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2546                         vlan->vid, untagged ? 'u' : 't');
2547                 goto out;
2548         }
2549
2550         if (pvid) {
2551                 p->bridge_pvid.vid = vlan->vid;
2552                 p->bridge_pvid.valid = true;
2553
2554                 err = mv88e6xxx_port_commit_pvid(chip, port);
2555                 if (err)
2556                         goto out;
2557         } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) {
2558                 /* The old pvid was reinstalled as a non-pvid VLAN */
2559                 p->bridge_pvid.valid = false;
2560
2561                 err = mv88e6xxx_port_commit_pvid(chip, port);
2562                 if (err)
2563                         goto out;
2564         }
2565
2566 out:
2567         mv88e6xxx_reg_unlock(chip);
2568
2569         return err;
2570 }
2571
2572 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2573                                      int port, u16 vid)
2574 {
2575         struct mv88e6xxx_vtu_entry vlan;
2576         int i, err;
2577
2578         if (!vid)
2579                 return 0;
2580
2581         err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2582         if (err)
2583                 return err;
2584
2585         /* If the VLAN doesn't exist in hardware or the port isn't a member,
2586          * tell switchdev that this VLAN is likely handled in software.
2587          */
2588         if (!vlan.valid ||
2589             vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2590                 return -EOPNOTSUPP;
2591
2592         vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2593
2594         /* keep the VLAN unless all ports are excluded */
2595         vlan.valid = false;
2596         for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2597                 if (vlan.member[i] !=
2598                     MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2599                         vlan.valid = true;
2600                         break;
2601                 }
2602         }
2603
2604         err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2605         if (err)
2606                 return err;
2607
2608         if (!vlan.valid) {
2609                 err = mv88e6xxx_mst_put(chip, vlan.sid);
2610                 if (err)
2611                         return err;
2612         }
2613
2614         return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2615 }
2616
2617 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2618                                    const struct switchdev_obj_port_vlan *vlan)
2619 {
2620         struct mv88e6xxx_chip *chip = ds->priv;
2621         struct mv88e6xxx_port *p = &chip->ports[port];
2622         int err = 0;
2623         u16 pvid;
2624
2625         if (!mv88e6xxx_max_vid(chip))
2626                 return -EOPNOTSUPP;
2627
2628         /* The ATU removal procedure needs the FID to be mapped in the VTU,
2629          * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA
2630          * switchdev workqueue to ensure that all FDB entries are deleted
2631          * before we remove the VLAN.
2632          */
2633         dsa_flush_workqueue();
2634
2635         mv88e6xxx_reg_lock(chip);
2636
2637         err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2638         if (err)
2639                 goto unlock;
2640
2641         err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid);
2642         if (err)
2643                 goto unlock;
2644
2645         if (vlan->vid == pvid) {
2646                 p->bridge_pvid.valid = false;
2647
2648                 err = mv88e6xxx_port_commit_pvid(chip, port);
2649                 if (err)
2650                         goto unlock;
2651         }
2652
2653 unlock:
2654         mv88e6xxx_reg_unlock(chip);
2655
2656         return err;
2657 }
2658
2659 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid)
2660 {
2661         struct mv88e6xxx_chip *chip = ds->priv;
2662         struct mv88e6xxx_vtu_entry vlan;
2663         int err;
2664
2665         mv88e6xxx_reg_lock(chip);
2666
2667         err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2668         if (err)
2669                 goto unlock;
2670
2671         err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid);
2672
2673 unlock:
2674         mv88e6xxx_reg_unlock(chip);
2675
2676         return err;
2677 }
2678
2679 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds,
2680                                    struct dsa_bridge bridge,
2681                                    const struct switchdev_vlan_msti *msti)
2682 {
2683         struct mv88e6xxx_chip *chip = ds->priv;
2684         struct mv88e6xxx_vtu_entry vlan;
2685         u8 old_sid, new_sid;
2686         int err;
2687
2688         if (!mv88e6xxx_has_stu(chip))
2689                 return -EOPNOTSUPP;
2690
2691         mv88e6xxx_reg_lock(chip);
2692
2693         err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan);
2694         if (err)
2695                 goto unlock;
2696
2697         if (!vlan.valid) {
2698                 err = -EINVAL;
2699                 goto unlock;
2700         }
2701
2702         old_sid = vlan.sid;
2703
2704         err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid);
2705         if (err)
2706                 goto unlock;
2707
2708         if (new_sid != old_sid) {
2709                 vlan.sid = new_sid;
2710
2711                 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2712                 if (err) {
2713                         mv88e6xxx_mst_put(chip, new_sid);
2714                         goto unlock;
2715                 }
2716         }
2717
2718         err = mv88e6xxx_mst_put(chip, old_sid);
2719
2720 unlock:
2721         mv88e6xxx_reg_unlock(chip);
2722         return err;
2723 }
2724
2725 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2726                                   const unsigned char *addr, u16 vid,
2727                                   struct dsa_db db)
2728 {
2729         struct mv88e6xxx_chip *chip = ds->priv;
2730         int err;
2731
2732         mv88e6xxx_reg_lock(chip);
2733         err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2734                                            MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2735         mv88e6xxx_reg_unlock(chip);
2736
2737         return err;
2738 }
2739
2740 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2741                                   const unsigned char *addr, u16 vid,
2742                                   struct dsa_db db)
2743 {
2744         struct mv88e6xxx_chip *chip = ds->priv;
2745         int err;
2746
2747         mv88e6xxx_reg_lock(chip);
2748         err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2749         mv88e6xxx_reg_unlock(chip);
2750
2751         return err;
2752 }
2753
2754 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2755                                       u16 fid, u16 vid, int port,
2756                                       dsa_fdb_dump_cb_t *cb, void *data)
2757 {
2758         struct mv88e6xxx_atu_entry addr;
2759         bool is_static;
2760         int err;
2761
2762         addr.state = 0;
2763         eth_broadcast_addr(addr.mac);
2764
2765         do {
2766                 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2767                 if (err)
2768                         return err;
2769
2770                 if (!addr.state)
2771                         break;
2772
2773                 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2774                         continue;
2775
2776                 if (!is_unicast_ether_addr(addr.mac))
2777                         continue;
2778
2779                 is_static = (addr.state ==
2780                              MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2781                 err = cb(addr.mac, vid, is_static, data);
2782                 if (err)
2783                         return err;
2784         } while (!is_broadcast_ether_addr(addr.mac));
2785
2786         return err;
2787 }
2788
2789 struct mv88e6xxx_port_db_dump_vlan_ctx {
2790         int port;
2791         dsa_fdb_dump_cb_t *cb;
2792         void *data;
2793 };
2794
2795 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip,
2796                                        const struct mv88e6xxx_vtu_entry *entry,
2797                                        void *_data)
2798 {
2799         struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data;
2800
2801         return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid,
2802                                           ctx->port, ctx->cb, ctx->data);
2803 }
2804
2805 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2806                                   dsa_fdb_dump_cb_t *cb, void *data)
2807 {
2808         struct mv88e6xxx_port_db_dump_vlan_ctx ctx = {
2809                 .port = port,
2810                 .cb = cb,
2811                 .data = data,
2812         };
2813         u16 fid;
2814         int err;
2815
2816         /* Dump port's default Filtering Information Database (VLAN ID 0) */
2817         err = mv88e6xxx_port_get_fid(chip, port, &fid);
2818         if (err)
2819                 return err;
2820
2821         err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2822         if (err)
2823                 return err;
2824
2825         return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx);
2826 }
2827
2828 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2829                                    dsa_fdb_dump_cb_t *cb, void *data)
2830 {
2831         struct mv88e6xxx_chip *chip = ds->priv;
2832         int err;
2833
2834         mv88e6xxx_reg_lock(chip);
2835         err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2836         mv88e6xxx_reg_unlock(chip);
2837
2838         return err;
2839 }
2840
2841 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2842                                 struct dsa_bridge bridge)
2843 {
2844         struct dsa_switch *ds = chip->ds;
2845         struct dsa_switch_tree *dst = ds->dst;
2846         struct dsa_port *dp;
2847         int err;
2848
2849         list_for_each_entry(dp, &dst->ports, list) {
2850                 if (dsa_port_offloads_bridge(dp, &bridge)) {
2851                         if (dp->ds == ds) {
2852                                 /* This is a local bridge group member,
2853                                  * remap its Port VLAN Map.
2854                                  */
2855                                 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2856                                 if (err)
2857                                         return err;
2858                         } else {
2859                                 /* This is an external bridge group member,
2860                                  * remap its cross-chip Port VLAN Table entry.
2861                                  */
2862                                 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2863                                                         dp->index);
2864                                 if (err)
2865                                         return err;
2866                         }
2867                 }
2868         }
2869
2870         return 0;
2871 }
2872
2873 /* Treat the software bridge as a virtual single-port switch behind the
2874  * CPU and map in the PVT. First dst->last_switch elements are taken by
2875  * physical switches, so start from beyond that range.
2876  */
2877 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds,
2878                                                unsigned int bridge_num)
2879 {
2880         u8 dev = bridge_num + ds->dst->last_switch;
2881         struct mv88e6xxx_chip *chip = ds->priv;
2882
2883         return mv88e6xxx_pvt_map(chip, dev, 0);
2884 }
2885
2886 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2887                                       struct dsa_bridge bridge,
2888                                       bool *tx_fwd_offload,
2889                                       struct netlink_ext_ack *extack)
2890 {
2891         struct mv88e6xxx_chip *chip = ds->priv;
2892         int err;
2893
2894         mv88e6xxx_reg_lock(chip);
2895
2896         err = mv88e6xxx_bridge_map(chip, bridge);
2897         if (err)
2898                 goto unlock;
2899
2900         err = mv88e6xxx_port_set_map_da(chip, port, true);
2901         if (err)
2902                 goto unlock;
2903
2904         err = mv88e6xxx_port_commit_pvid(chip, port);
2905         if (err)
2906                 goto unlock;
2907
2908         if (mv88e6xxx_has_pvt(chip)) {
2909                 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
2910                 if (err)
2911                         goto unlock;
2912
2913                 *tx_fwd_offload = true;
2914         }
2915
2916 unlock:
2917         mv88e6xxx_reg_unlock(chip);
2918
2919         return err;
2920 }
2921
2922 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2923                                         struct dsa_bridge bridge)
2924 {
2925         struct mv88e6xxx_chip *chip = ds->priv;
2926         int err;
2927
2928         mv88e6xxx_reg_lock(chip);
2929
2930         if (bridge.tx_fwd_offload &&
2931             mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
2932                 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2933
2934         if (mv88e6xxx_bridge_map(chip, bridge) ||
2935             mv88e6xxx_port_vlan_map(chip, port))
2936                 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
2937
2938         err = mv88e6xxx_port_set_map_da(chip, port, false);
2939         if (err)
2940                 dev_err(ds->dev,
2941                         "port %d failed to restore map-DA: %pe\n",
2942                         port, ERR_PTR(err));
2943
2944         err = mv88e6xxx_port_commit_pvid(chip, port);
2945         if (err)
2946                 dev_err(ds->dev,
2947                         "port %d failed to restore standalone pvid: %pe\n",
2948                         port, ERR_PTR(err));
2949
2950         mv88e6xxx_reg_unlock(chip);
2951 }
2952
2953 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
2954                                            int tree_index, int sw_index,
2955                                            int port, struct dsa_bridge bridge,
2956                                            struct netlink_ext_ack *extack)
2957 {
2958         struct mv88e6xxx_chip *chip = ds->priv;
2959         int err;
2960
2961         if (tree_index != ds->dst->index)
2962                 return 0;
2963
2964         mv88e6xxx_reg_lock(chip);
2965         err = mv88e6xxx_pvt_map(chip, sw_index, port);
2966         err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
2967         mv88e6xxx_reg_unlock(chip);
2968
2969         return err;
2970 }
2971
2972 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
2973                                              int tree_index, int sw_index,
2974                                              int port, struct dsa_bridge bridge)
2975 {
2976         struct mv88e6xxx_chip *chip = ds->priv;
2977
2978         if (tree_index != ds->dst->index)
2979                 return;
2980
2981         mv88e6xxx_reg_lock(chip);
2982         if (mv88e6xxx_pvt_map(chip, sw_index, port) ||
2983             mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
2984                 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2985         mv88e6xxx_reg_unlock(chip);
2986 }
2987
2988 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2989 {
2990         if (chip->info->ops->reset)
2991                 return chip->info->ops->reset(chip);
2992
2993         return 0;
2994 }
2995
2996 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2997 {
2998         struct gpio_desc *gpiod = chip->reset;
2999
3000         /* If there is a GPIO connected to the reset pin, toggle it */
3001         if (gpiod) {
3002                 gpiod_set_value_cansleep(gpiod, 1);
3003                 usleep_range(10000, 20000);
3004                 gpiod_set_value_cansleep(gpiod, 0);
3005                 usleep_range(10000, 20000);
3006
3007                 mv88e6xxx_g1_wait_eeprom_done(chip);
3008         }
3009 }
3010
3011 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
3012 {
3013         int i, err;
3014
3015         /* Set all ports to the Disabled state */
3016         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3017                 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
3018                 if (err)
3019                         return err;
3020         }
3021
3022         /* Wait for transmit queues to drain,
3023          * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
3024          */
3025         usleep_range(2000, 4000);
3026
3027         return 0;
3028 }
3029
3030 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
3031 {
3032         int err;
3033
3034         err = mv88e6xxx_disable_ports(chip);
3035         if (err)
3036                 return err;
3037
3038         mv88e6xxx_hardware_reset(chip);
3039
3040         return mv88e6xxx_software_reset(chip);
3041 }
3042
3043 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
3044                                    enum mv88e6xxx_frame_mode frame,
3045                                    enum mv88e6xxx_egress_mode egress, u16 etype)
3046 {
3047         int err;
3048
3049         if (!chip->info->ops->port_set_frame_mode)
3050                 return -EOPNOTSUPP;
3051
3052         err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
3053         if (err)
3054                 return err;
3055
3056         err = chip->info->ops->port_set_frame_mode(chip, port, frame);
3057         if (err)
3058                 return err;
3059
3060         if (chip->info->ops->port_set_ether_type)
3061                 return chip->info->ops->port_set_ether_type(chip, port, etype);
3062
3063         return 0;
3064 }
3065
3066 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
3067 {
3068         return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
3069                                        MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3070                                        MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3071 }
3072
3073 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
3074 {
3075         return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
3076                                        MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3077                                        MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3078 }
3079
3080 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
3081 {
3082         return mv88e6xxx_set_port_mode(chip, port,
3083                                        MV88E6XXX_FRAME_MODE_ETHERTYPE,
3084                                        MV88E6XXX_EGRESS_MODE_ETHERTYPE,
3085                                        ETH_P_EDSA);
3086 }
3087
3088 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
3089 {
3090         if (dsa_is_dsa_port(chip->ds, port))
3091                 return mv88e6xxx_set_port_mode_dsa(chip, port);
3092
3093         if (dsa_is_user_port(chip->ds, port))
3094                 return mv88e6xxx_set_port_mode_normal(chip, port);
3095
3096         /* Setup CPU port mode depending on its supported tag format */
3097         if (chip->tag_protocol == DSA_TAG_PROTO_DSA)
3098                 return mv88e6xxx_set_port_mode_dsa(chip, port);
3099
3100         if (chip->tag_protocol == DSA_TAG_PROTO_EDSA)
3101                 return mv88e6xxx_set_port_mode_edsa(chip, port);
3102
3103         return -EINVAL;
3104 }
3105
3106 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
3107 {
3108         bool message = dsa_is_dsa_port(chip->ds, port);
3109
3110         return mv88e6xxx_port_set_message_port(chip, port, message);
3111 }
3112
3113 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
3114 {
3115         int err;
3116
3117         if (chip->info->ops->port_set_ucast_flood) {
3118                 err = chip->info->ops->port_set_ucast_flood(chip, port, true);
3119                 if (err)
3120                         return err;
3121         }
3122         if (chip->info->ops->port_set_mcast_flood) {
3123                 err = chip->info->ops->port_set_mcast_flood(chip, port, true);
3124                 if (err)
3125                         return err;
3126         }
3127
3128         return 0;
3129 }
3130
3131 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id)
3132 {
3133         struct mv88e6xxx_port *mvp = dev_id;
3134         struct mv88e6xxx_chip *chip = mvp->chip;
3135         irqreturn_t ret = IRQ_NONE;
3136         int port = mvp->port;
3137         int lane;
3138
3139         mv88e6xxx_reg_lock(chip);
3140         lane = mv88e6xxx_serdes_get_lane(chip, port);
3141         if (lane >= 0)
3142                 ret = mv88e6xxx_serdes_irq_status(chip, port, lane);
3143         mv88e6xxx_reg_unlock(chip);
3144
3145         return ret;
3146 }
3147
3148 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port,
3149                                         int lane)
3150 {
3151         struct mv88e6xxx_port *dev_id = &chip->ports[port];
3152         unsigned int irq;
3153         int err;
3154
3155         /* Nothing to request if this SERDES port has no IRQ */
3156         irq = mv88e6xxx_serdes_irq_mapping(chip, port);
3157         if (!irq)
3158                 return 0;
3159
3160         snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name),
3161                  "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port);
3162
3163         /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */
3164         mv88e6xxx_reg_unlock(chip);
3165         err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn,
3166                                    IRQF_ONESHOT, dev_id->serdes_irq_name,
3167                                    dev_id);
3168         mv88e6xxx_reg_lock(chip);
3169         if (err)
3170                 return err;
3171
3172         dev_id->serdes_irq = irq;
3173
3174         return mv88e6xxx_serdes_irq_enable(chip, port, lane);
3175 }
3176
3177 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port,
3178                                      int lane)
3179 {
3180         struct mv88e6xxx_port *dev_id = &chip->ports[port];
3181         unsigned int irq = dev_id->serdes_irq;
3182         int err;
3183
3184         /* Nothing to free if no IRQ has been requested */
3185         if (!irq)
3186                 return 0;
3187
3188         err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
3189
3190         /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */
3191         mv88e6xxx_reg_unlock(chip);
3192         free_irq(irq, dev_id);
3193         mv88e6xxx_reg_lock(chip);
3194
3195         dev_id->serdes_irq = 0;
3196
3197         return err;
3198 }
3199
3200 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
3201                                   bool on)
3202 {
3203         int lane;
3204         int err;
3205
3206         lane = mv88e6xxx_serdes_get_lane(chip, port);
3207         if (lane < 0)
3208                 return 0;
3209
3210         if (on) {
3211                 err = mv88e6xxx_serdes_power_up(chip, port, lane);
3212                 if (err)
3213                         return err;
3214
3215                 err = mv88e6xxx_serdes_irq_request(chip, port, lane);
3216         } else {
3217                 err = mv88e6xxx_serdes_irq_free(chip, port, lane);
3218                 if (err)
3219                         return err;
3220
3221                 err = mv88e6xxx_serdes_power_down(chip, port, lane);
3222         }
3223
3224         return err;
3225 }
3226
3227 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,
3228                                      enum mv88e6xxx_egress_direction direction,
3229                                      int port)
3230 {
3231         int err;
3232
3233         if (!chip->info->ops->set_egress_port)
3234                 return -EOPNOTSUPP;
3235
3236         err = chip->info->ops->set_egress_port(chip, direction, port);
3237         if (err)
3238                 return err;
3239
3240         if (direction == MV88E6XXX_EGRESS_DIR_INGRESS)
3241                 chip->ingress_dest_port = port;
3242         else
3243                 chip->egress_dest_port = port;
3244
3245         return 0;
3246 }
3247
3248 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
3249 {
3250         struct dsa_switch *ds = chip->ds;
3251         int upstream_port;
3252         int err;
3253
3254         upstream_port = dsa_upstream_port(ds, port);
3255         if (chip->info->ops->port_set_upstream_port) {
3256                 err = chip->info->ops->port_set_upstream_port(chip, port,
3257                                                               upstream_port);
3258                 if (err)
3259                         return err;
3260         }
3261
3262         if (port == upstream_port) {
3263                 if (chip->info->ops->set_cpu_port) {
3264                         err = chip->info->ops->set_cpu_port(chip,
3265                                                             upstream_port);
3266                         if (err)
3267                                 return err;
3268                 }
3269
3270                 err = mv88e6xxx_set_egress_port(chip,
3271                                                 MV88E6XXX_EGRESS_DIR_INGRESS,
3272                                                 upstream_port);
3273                 if (err && err != -EOPNOTSUPP)
3274                         return err;
3275
3276                 err = mv88e6xxx_set_egress_port(chip,
3277                                                 MV88E6XXX_EGRESS_DIR_EGRESS,
3278                                                 upstream_port);
3279                 if (err && err != -EOPNOTSUPP)
3280                         return err;
3281         }
3282
3283         return 0;
3284 }
3285
3286 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
3287 {
3288         struct device_node *phy_handle = NULL;
3289         struct dsa_switch *ds = chip->ds;
3290         phy_interface_t mode;
3291         struct dsa_port *dp;
3292         int tx_amp, speed;
3293         int err;
3294         u16 reg;
3295
3296         chip->ports[port].chip = chip;
3297         chip->ports[port].port = port;
3298
3299         dp = dsa_to_port(ds, port);
3300
3301         /* MAC Forcing register: don't force link, speed, duplex or flow control
3302          * state to any particular values on physical ports, but force the CPU
3303          * port and all DSA ports to their maximum bandwidth and full duplex.
3304          */
3305         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
3306                 struct phylink_config pl_config = {};
3307                 unsigned long caps;
3308
3309                 chip->info->ops->phylink_get_caps(chip, port, &pl_config);
3310
3311                 caps = pl_config.mac_capabilities;
3312
3313                 if (chip->info->ops->port_max_speed_mode)
3314                         mode = chip->info->ops->port_max_speed_mode(port);
3315                 else
3316                         mode = PHY_INTERFACE_MODE_NA;
3317
3318                 if (caps & MAC_10000FD)
3319                         speed = SPEED_10000;
3320                 else if (caps & MAC_5000FD)
3321                         speed = SPEED_5000;
3322                 else if (caps & MAC_2500FD)
3323                         speed = SPEED_2500;
3324                 else if (caps & MAC_1000)
3325                         speed = SPEED_1000;
3326                 else if (caps & MAC_100)
3327                         speed = SPEED_100;
3328                 else
3329                         speed = SPEED_10;
3330
3331                 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
3332                                                speed, DUPLEX_FULL,
3333                                                PAUSE_OFF, mode);
3334         } else {
3335                 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
3336                                                SPEED_UNFORCED, DUPLEX_UNFORCED,
3337                                                PAUSE_ON,
3338                                                PHY_INTERFACE_MODE_NA);
3339         }
3340         if (err)
3341                 return err;
3342
3343         /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
3344          * disable Header mode, enable IGMP/MLD snooping, disable VLAN
3345          * tunneling, determine priority by looking at 802.1p and IP
3346          * priority fields (IP prio has precedence), and set STP state
3347          * to Forwarding.
3348          *
3349          * If this is the CPU link, use DSA or EDSA tagging depending
3350          * on which tagging mode was configured.
3351          *
3352          * If this is a link to another switch, use DSA tagging mode.
3353          *
3354          * If this is the upstream port for this switch, enable
3355          * forwarding of unknown unicasts and multicasts.
3356          */
3357         reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
3358                 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
3359         /* Forward any IPv4 IGMP or IPv6 MLD frames received
3360          * by a USER port to the CPU port to allow snooping.
3361          */
3362         if (dsa_is_user_port(ds, port))
3363                 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP;
3364
3365         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
3366         if (err)
3367                 return err;
3368
3369         err = mv88e6xxx_setup_port_mode(chip, port);
3370         if (err)
3371                 return err;
3372
3373         err = mv88e6xxx_setup_egress_floods(chip, port);
3374         if (err)
3375                 return err;
3376
3377         /* Port Control 2: don't force a good FCS, set the MTU size to
3378          * 10222 bytes, disable 802.1q tags checking, don't discard
3379          * tagged or untagged frames on this port, skip destination
3380          * address lookup on user ports, disable ARP mirroring and don't
3381          * send a copy of all transmitted/received frames on this port
3382          * to the CPU.
3383          */
3384         err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port));
3385         if (err)
3386                 return err;
3387
3388         err = mv88e6xxx_setup_upstream_port(chip, port);
3389         if (err)
3390                 return err;
3391
3392         /* On chips that support it, set all downstream DSA ports'
3393          * VLAN policy to TRAP. In combination with loading
3394          * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this
3395          * provides a better isolation barrier between standalone
3396          * ports, as the ATU is bypassed on any intermediate switches
3397          * between the incoming port and the CPU.
3398          */
3399         if (dsa_is_downstream_port(ds, port) &&
3400             chip->info->ops->port_set_policy) {
3401                 err = chip->info->ops->port_set_policy(chip, port,
3402                                                 MV88E6XXX_POLICY_MAPPING_VTU,
3403                                                 MV88E6XXX_POLICY_ACTION_TRAP);
3404                 if (err)
3405                         return err;
3406         }
3407
3408         /* User ports start out in standalone mode and 802.1Q is
3409          * therefore disabled. On DSA ports, all valid VIDs are always
3410          * loaded in the VTU - therefore, enable 802.1Q in order to take
3411          * advantage of VLAN policy on chips that supports it.
3412          */
3413         err = mv88e6xxx_port_set_8021q_mode(chip, port,
3414                                 dsa_is_user_port(ds, port) ?
3415                                 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED :
3416                                 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE);
3417         if (err)
3418                 return err;
3419
3420         /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by
3421          * virtue of the fact that mv88e6xxx_atu_new() will pick it as
3422          * the first free FID. This will be used as the private PVID for
3423          * unbridged ports. Shared (DSA and CPU) ports must also be
3424          * members of this VID, in order to trap all frames assigned to
3425          * it to the CPU.
3426          */
3427         err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE,
3428                                        MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3429                                        false);
3430         if (err)
3431                 return err;
3432
3433         /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the
3434          * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as
3435          * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used
3436          * as the private PVID on ports under a VLAN-unaware bridge.
3437          * Shared (DSA and CPU) ports must also be members of it, to translate
3438          * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of
3439          * relying on their port default FID.
3440          */
3441         err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED,
3442                                        MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3443                                        false);
3444         if (err)
3445                 return err;
3446
3447         if (chip->info->ops->port_set_jumbo_size) {
3448                 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
3449                 if (err)
3450                         return err;
3451         }
3452
3453         /* Port Association Vector: disable automatic address learning
3454          * on all user ports since they start out in standalone
3455          * mode. When joining a bridge, learning will be configured to
3456          * match the bridge port settings. Enable learning on all
3457          * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the
3458          * learning process.
3459          *
3460          * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData,
3461          * and RefreshLocked. I.e. setup standard automatic learning.
3462          */
3463         if (dsa_is_user_port(ds, port))
3464                 reg = 0;
3465         else
3466                 reg = 1 << port;
3467
3468         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
3469                                    reg);
3470         if (err)
3471                 return err;
3472
3473         /* Egress rate control 2: disable egress rate control. */
3474         err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
3475                                    0x0000);
3476         if (err)
3477                 return err;
3478
3479         if (chip->info->ops->port_pause_limit) {
3480                 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
3481                 if (err)
3482                         return err;
3483         }
3484
3485         if (chip->info->ops->port_disable_learn_limit) {
3486                 err = chip->info->ops->port_disable_learn_limit(chip, port);
3487                 if (err)
3488                         return err;
3489         }
3490
3491         if (chip->info->ops->port_disable_pri_override) {
3492                 err = chip->info->ops->port_disable_pri_override(chip, port);
3493                 if (err)
3494                         return err;
3495         }
3496
3497         if (chip->info->ops->port_tag_remap) {
3498                 err = chip->info->ops->port_tag_remap(chip, port);
3499                 if (err)
3500                         return err;
3501         }
3502
3503         if (chip->info->ops->port_egress_rate_limiting) {
3504                 err = chip->info->ops->port_egress_rate_limiting(chip, port);
3505                 if (err)
3506                         return err;
3507         }
3508
3509         if (chip->info->ops->port_setup_message_port) {
3510                 err = chip->info->ops->port_setup_message_port(chip, port);
3511                 if (err)
3512                         return err;
3513         }
3514
3515         if (chip->info->ops->serdes_set_tx_amplitude) {
3516                 if (dp)
3517                         phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0);
3518
3519                 if (phy_handle && !of_property_read_u32(phy_handle,
3520                                                         "tx-p2p-microvolt",
3521                                                         &tx_amp))
3522                         err = chip->info->ops->serdes_set_tx_amplitude(chip,
3523                                                                 port, tx_amp);
3524                 if (phy_handle) {
3525                         of_node_put(phy_handle);
3526                         if (err)
3527                                 return err;
3528                 }
3529         }
3530
3531         /* Port based VLAN map: give each port the same default address
3532          * database, and allow bidirectional communication between the
3533          * CPU and DSA port(s), and the other ports.
3534          */
3535         err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE);
3536         if (err)
3537                 return err;
3538
3539         err = mv88e6xxx_port_vlan_map(chip, port);
3540         if (err)
3541                 return err;
3542
3543         /* Default VLAN ID and priority: don't set a default VLAN
3544          * ID, and set the default packet priority to zero.
3545          */
3546         return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
3547 }
3548
3549 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
3550 {
3551         struct mv88e6xxx_chip *chip = ds->priv;
3552
3553         if (chip->info->ops->port_set_jumbo_size)
3554                 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3555         else if (chip->info->ops->set_max_frame_size)
3556                 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3557         return ETH_DATA_LEN;
3558 }
3559
3560 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
3561 {
3562         struct mv88e6xxx_chip *chip = ds->priv;
3563         int ret = 0;
3564
3565         /* For families where we don't know how to alter the MTU,
3566          * just accept any value up to ETH_DATA_LEN
3567          */
3568         if (!chip->info->ops->port_set_jumbo_size &&
3569             !chip->info->ops->set_max_frame_size) {
3570                 if (new_mtu > ETH_DATA_LEN)
3571                         return -EINVAL;
3572
3573                 return 0;
3574         }
3575
3576         if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
3577                 new_mtu += EDSA_HLEN;
3578
3579         mv88e6xxx_reg_lock(chip);
3580         if (chip->info->ops->port_set_jumbo_size)
3581                 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
3582         else if (chip->info->ops->set_max_frame_size)
3583                 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
3584         mv88e6xxx_reg_unlock(chip);
3585
3586         return ret;
3587 }
3588
3589 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
3590                                  struct phy_device *phydev)
3591 {
3592         struct mv88e6xxx_chip *chip = ds->priv;
3593         int err;
3594
3595         mv88e6xxx_reg_lock(chip);
3596         err = mv88e6xxx_serdes_power(chip, port, true);
3597         mv88e6xxx_reg_unlock(chip);
3598
3599         return err;
3600 }
3601
3602 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
3603 {
3604         struct mv88e6xxx_chip *chip = ds->priv;
3605
3606         mv88e6xxx_reg_lock(chip);
3607         if (mv88e6xxx_serdes_power(chip, port, false))
3608                 dev_err(chip->dev, "failed to power off SERDES\n");
3609         mv88e6xxx_reg_unlock(chip);
3610 }
3611
3612 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
3613                                      unsigned int ageing_time)
3614 {
3615         struct mv88e6xxx_chip *chip = ds->priv;
3616         int err;
3617
3618         mv88e6xxx_reg_lock(chip);
3619         err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
3620         mv88e6xxx_reg_unlock(chip);
3621
3622         return err;
3623 }
3624
3625 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
3626 {
3627         int err;
3628
3629         /* Initialize the statistics unit */
3630         if (chip->info->ops->stats_set_histogram) {
3631                 err = chip->info->ops->stats_set_histogram(chip);
3632                 if (err)
3633                         return err;
3634         }
3635
3636         return mv88e6xxx_g1_stats_clear(chip);
3637 }
3638
3639 /* Check if the errata has already been applied. */
3640 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
3641 {
3642         int port;
3643         int err;
3644         u16 val;
3645
3646         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3647                 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
3648                 if (err) {
3649                         dev_err(chip->dev,
3650                                 "Error reading hidden register: %d\n", err);
3651                         return false;
3652                 }
3653                 if (val != 0x01c0)
3654                         return false;
3655         }
3656
3657         return true;
3658 }
3659
3660 /* The 6390 copper ports have an errata which require poking magic
3661  * values into undocumented hidden registers and then performing a
3662  * software reset.
3663  */
3664 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
3665 {
3666         int port;
3667         int err;
3668
3669         if (mv88e6390_setup_errata_applied(chip))
3670                 return 0;
3671
3672         /* Set the ports into blocking mode */
3673         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3674                 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
3675                 if (err)
3676                         return err;
3677         }
3678
3679         for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3680                 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
3681                 if (err)
3682                         return err;
3683         }
3684
3685         return mv88e6xxx_software_reset(chip);
3686 }
3687
3688 static void mv88e6xxx_teardown(struct dsa_switch *ds)
3689 {
3690         mv88e6xxx_teardown_devlink_params(ds);
3691         dsa_devlink_resources_unregister(ds);
3692         mv88e6xxx_teardown_devlink_regions_global(ds);
3693 }
3694
3695 static int mv88e6xxx_setup(struct dsa_switch *ds)
3696 {
3697         struct mv88e6xxx_chip *chip = ds->priv;
3698         u8 cmode;
3699         int err;
3700         int i;
3701
3702         chip->ds = ds;
3703         ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
3704
3705         /* Since virtual bridges are mapped in the PVT, the number we support
3706          * depends on the physical switch topology. We need to let DSA figure
3707          * that out and therefore we cannot set this at dsa_register_switch()
3708          * time.
3709          */
3710         if (mv88e6xxx_has_pvt(chip))
3711                 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES -
3712                                       ds->dst->last_switch - 1;
3713
3714         mv88e6xxx_reg_lock(chip);
3715
3716         if (chip->info->ops->setup_errata) {
3717                 err = chip->info->ops->setup_errata(chip);
3718                 if (err)
3719                         goto unlock;
3720         }
3721
3722         /* Cache the cmode of each port. */
3723         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3724                 if (chip->info->ops->port_get_cmode) {
3725                         err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3726                         if (err)
3727                                 goto unlock;
3728
3729                         chip->ports[i].cmode = cmode;
3730                 }
3731         }
3732
3733         err = mv88e6xxx_vtu_setup(chip);
3734         if (err)
3735                 goto unlock;
3736
3737         /* Must be called after mv88e6xxx_vtu_setup (which flushes the
3738          * VTU, thereby also flushing the STU).
3739          */
3740         err = mv88e6xxx_stu_setup(chip);
3741         if (err)
3742                 goto unlock;
3743
3744         /* Setup Switch Port Registers */
3745         for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3746                 if (dsa_is_unused_port(ds, i))
3747                         continue;
3748
3749                 /* Prevent the use of an invalid port. */
3750                 if (mv88e6xxx_is_invalid_port(chip, i)) {
3751                         dev_err(chip->dev, "port %d is invalid\n", i);
3752                         err = -EINVAL;
3753                         goto unlock;
3754                 }
3755
3756                 err = mv88e6xxx_setup_port(chip, i);
3757                 if (err)
3758                         goto unlock;
3759         }
3760
3761         err = mv88e6xxx_irl_setup(chip);
3762         if (err)
3763                 goto unlock;
3764
3765         err = mv88e6xxx_mac_setup(chip);
3766         if (err)
3767                 goto unlock;
3768
3769         err = mv88e6xxx_phy_setup(chip);
3770         if (err)
3771                 goto unlock;
3772
3773         err = mv88e6xxx_pvt_setup(chip);
3774         if (err)
3775                 goto unlock;
3776
3777         err = mv88e6xxx_atu_setup(chip);
3778         if (err)
3779                 goto unlock;
3780
3781         err = mv88e6xxx_broadcast_setup(chip, 0);
3782         if (err)
3783                 goto unlock;
3784
3785         err = mv88e6xxx_pot_setup(chip);
3786         if (err)
3787                 goto unlock;
3788
3789         err = mv88e6xxx_rmu_setup(chip);
3790         if (err)
3791                 goto unlock;
3792
3793         err = mv88e6xxx_rsvd2cpu_setup(chip);
3794         if (err)
3795                 goto unlock;
3796
3797         err = mv88e6xxx_trunk_setup(chip);
3798         if (err)
3799                 goto unlock;
3800
3801         err = mv88e6xxx_devmap_setup(chip);
3802         if (err)
3803                 goto unlock;
3804
3805         err = mv88e6xxx_pri_setup(chip);
3806         if (err)
3807                 goto unlock;
3808
3809         /* Setup PTP Hardware Clock and timestamping */
3810         if (chip->info->ptp_support) {
3811                 err = mv88e6xxx_ptp_setup(chip);
3812                 if (err)
3813                         goto unlock;
3814
3815                 err = mv88e6xxx_hwtstamp_setup(chip);
3816                 if (err)
3817                         goto unlock;
3818         }
3819
3820         err = mv88e6xxx_stats_setup(chip);
3821         if (err)
3822                 goto unlock;
3823
3824 unlock:
3825         mv88e6xxx_reg_unlock(chip);
3826
3827         if (err)
3828                 return err;
3829
3830         /* Have to be called without holding the register lock, since
3831          * they take the devlink lock, and we later take the locks in
3832          * the reverse order when getting/setting parameters or
3833          * resource occupancy.
3834          */
3835         err = mv88e6xxx_setup_devlink_resources(ds);
3836         if (err)
3837                 return err;
3838
3839         err = mv88e6xxx_setup_devlink_params(ds);
3840         if (err)
3841                 goto out_resources;
3842
3843         err = mv88e6xxx_setup_devlink_regions_global(ds);
3844         if (err)
3845                 goto out_params;
3846
3847         return 0;
3848
3849 out_params:
3850         mv88e6xxx_teardown_devlink_params(ds);
3851 out_resources:
3852         dsa_devlink_resources_unregister(ds);
3853
3854         return err;
3855 }
3856
3857 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port)
3858 {
3859         return mv88e6xxx_setup_devlink_regions_port(ds, port);
3860 }
3861
3862 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port)
3863 {
3864         mv88e6xxx_teardown_devlink_regions_port(ds, port);
3865 }
3866
3867 /* prod_id for switch families which do not have a PHY model number */
3868 static const u16 family_prod_id_table[] = {
3869         [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3870         [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3871         [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
3872 };
3873
3874 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3875 {
3876         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3877         struct mv88e6xxx_chip *chip = mdio_bus->chip;
3878         u16 prod_id;
3879         u16 val;
3880         int err;
3881
3882         if (!chip->info->ops->phy_read)
3883                 return -EOPNOTSUPP;
3884
3885         mv88e6xxx_reg_lock(chip);
3886         err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3887         mv88e6xxx_reg_unlock(chip);
3888
3889         /* Some internal PHYs don't have a model number. */
3890         if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
3891             chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3892                 prod_id = family_prod_id_table[chip->info->family];
3893                 if (prod_id)
3894                         val |= prod_id >> 4;
3895         }
3896
3897         return err ? err : val;
3898 }
3899
3900 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad,
3901                                    int reg)
3902 {
3903         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3904         struct mv88e6xxx_chip *chip = mdio_bus->chip;
3905         u16 val;
3906         int err;
3907
3908         if (!chip->info->ops->phy_read_c45)
3909                 return -EOPNOTSUPP;
3910
3911         mv88e6xxx_reg_lock(chip);
3912         err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val);
3913         mv88e6xxx_reg_unlock(chip);
3914
3915         return err ? err : val;
3916 }
3917
3918 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3919 {
3920         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3921         struct mv88e6xxx_chip *chip = mdio_bus->chip;
3922         int err;
3923
3924         if (!chip->info->ops->phy_write)
3925                 return -EOPNOTSUPP;
3926
3927         mv88e6xxx_reg_lock(chip);
3928         err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3929         mv88e6xxx_reg_unlock(chip);
3930
3931         return err;
3932 }
3933
3934 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad,
3935                                     int reg, u16 val)
3936 {
3937         struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3938         struct mv88e6xxx_chip *chip = mdio_bus->chip;
3939         int err;
3940
3941         if (!chip->info->ops->phy_write_c45)
3942                 return -EOPNOTSUPP;
3943
3944         mv88e6xxx_reg_lock(chip);
3945         err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val);
3946         mv88e6xxx_reg_unlock(chip);
3947
3948         return err;
3949 }
3950
3951 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3952                                    struct device_node *np,
3953                                    bool external)
3954 {
3955         static int index;
3956         struct mv88e6xxx_mdio_bus *mdio_bus;
3957         struct mii_bus *bus;
3958         int err;
3959
3960         if (external) {
3961                 mv88e6xxx_reg_lock(chip);
3962                 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
3963                 mv88e6xxx_reg_unlock(chip);
3964
3965                 if (err)
3966                         return err;
3967         }
3968
3969         bus = mdiobus_alloc_size(sizeof(*mdio_bus));
3970         if (!bus)
3971                 return -ENOMEM;
3972
3973         mdio_bus = bus->priv;
3974         mdio_bus->bus = bus;
3975         mdio_bus->chip = chip;
3976         INIT_LIST_HEAD(&mdio_bus->list);
3977         mdio_bus->external = external;
3978
3979         if (np) {
3980                 bus->name = np->full_name;
3981                 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3982         } else {
3983                 bus->name = "mv88e6xxx SMI";
3984                 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3985         }
3986
3987         bus->read = mv88e6xxx_mdio_read;
3988         bus->write = mv88e6xxx_mdio_write;
3989         bus->read_c45 = mv88e6xxx_mdio_read_c45;
3990         bus->write_c45 = mv88e6xxx_mdio_write_c45;
3991         bus->parent = chip->dev;
3992
3993         if (!external) {
3994                 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3995                 if (err)
3996                         goto out;
3997         }
3998
3999         err = of_mdiobus_register(bus, np);
4000         if (err) {
4001                 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
4002                 mv88e6xxx_g2_irq_mdio_free(chip, bus);
4003                 goto out;
4004         }
4005
4006         if (external)
4007                 list_add_tail(&mdio_bus->list, &chip->mdios);
4008         else
4009                 list_add(&mdio_bus->list, &chip->mdios);
4010
4011         return 0;
4012
4013 out:
4014         mdiobus_free(bus);
4015         return err;
4016 }
4017
4018 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
4019
4020 {
4021         struct mv88e6xxx_mdio_bus *mdio_bus, *p;
4022         struct mii_bus *bus;
4023
4024         list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) {
4025                 bus = mdio_bus->bus;
4026
4027                 if (!mdio_bus->external)
4028                         mv88e6xxx_g2_irq_mdio_free(chip, bus);
4029
4030                 mdiobus_unregister(bus);
4031                 mdiobus_free(bus);
4032         }
4033 }
4034
4035 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
4036                                     struct device_node *np)
4037 {
4038         struct device_node *child;
4039         int err;
4040
4041         /* Always register one mdio bus for the internal/default mdio
4042          * bus. This maybe represented in the device tree, but is
4043          * optional.
4044          */
4045         child = of_get_child_by_name(np, "mdio");
4046         err = mv88e6xxx_mdio_register(chip, child, false);
4047         of_node_put(child);
4048         if (err)
4049                 return err;
4050
4051         /* Walk the device tree, and see if there are any other nodes
4052          * which say they are compatible with the external mdio
4053          * bus.
4054          */
4055         for_each_available_child_of_node(np, child) {
4056                 if (of_device_is_compatible(
4057                             child, "marvell,mv88e6xxx-mdio-external")) {
4058                         err = mv88e6xxx_mdio_register(chip, child, true);
4059                         if (err) {
4060                                 mv88e6xxx_mdios_unregister(chip);
4061                                 of_node_put(child);
4062                                 return err;
4063                         }
4064                 }
4065         }
4066
4067         return 0;
4068 }
4069
4070 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
4071 {
4072         struct mv88e6xxx_chip *chip = ds->priv;
4073
4074         return chip->eeprom_len;
4075 }
4076
4077 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
4078                                 struct ethtool_eeprom *eeprom, u8 *data)
4079 {
4080         struct mv88e6xxx_chip *chip = ds->priv;
4081         int err;
4082
4083         if (!chip->info->ops->get_eeprom)
4084                 return -EOPNOTSUPP;
4085
4086         mv88e6xxx_reg_lock(chip);
4087         err = chip->info->ops->get_eeprom(chip, eeprom, data);
4088         mv88e6xxx_reg_unlock(chip);
4089
4090         if (err)
4091                 return err;
4092
4093         eeprom->magic = 0xc3ec4951;
4094
4095         return 0;
4096 }
4097
4098 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
4099                                 struct ethtool_eeprom *eeprom, u8 *data)
4100 {
4101         struct mv88e6xxx_chip *chip = ds->priv;
4102         int err;
4103
4104         if (!chip->info->ops->set_eeprom)
4105                 return -EOPNOTSUPP;
4106
4107         if (eeprom->magic != 0xc3ec4951)
4108                 return -EINVAL;
4109
4110         mv88e6xxx_reg_lock(chip);
4111         err = chip->info->ops->set_eeprom(chip, eeprom, data);
4112         mv88e6xxx_reg_unlock(chip);
4113
4114         return err;
4115 }
4116
4117 static const struct mv88e6xxx_ops mv88e6085_ops = {
4118         /* MV88E6XXX_FAMILY_6097 */
4119         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4120         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4121         .irl_init_all = mv88e6352_g2_irl_init_all,
4122         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4123         .phy_read = mv88e6185_phy_ppu_read,
4124         .phy_write = mv88e6185_phy_ppu_write,
4125         .port_set_link = mv88e6xxx_port_set_link,
4126         .port_sync_link = mv88e6xxx_port_sync_link,
4127         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4128         .port_tag_remap = mv88e6095_port_tag_remap,
4129         .port_set_policy = mv88e6352_port_set_policy,
4130         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4131         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4132         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4133         .port_set_ether_type = mv88e6351_port_set_ether_type,
4134         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4135         .port_pause_limit = mv88e6097_port_pause_limit,
4136         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4137         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4138         .port_get_cmode = mv88e6185_port_get_cmode,
4139         .port_setup_message_port = mv88e6xxx_setup_message_port,
4140         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4141         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4142         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4143         .stats_get_strings = mv88e6095_stats_get_strings,
4144         .stats_get_stats = mv88e6095_stats_get_stats,
4145         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4146         .set_egress_port = mv88e6095_g1_set_egress_port,
4147         .watchdog_ops = &mv88e6097_watchdog_ops,
4148         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4149         .pot_clear = mv88e6xxx_g2_pot_clear,
4150         .ppu_enable = mv88e6185_g1_ppu_enable,
4151         .ppu_disable = mv88e6185_g1_ppu_disable,
4152         .reset = mv88e6185_g1_reset,
4153         .rmu_disable = mv88e6085_g1_rmu_disable,
4154         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4155         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4156         .stu_getnext = mv88e6352_g1_stu_getnext,
4157         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4158         .phylink_get_caps = mv88e6185_phylink_get_caps,
4159         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4160 };
4161
4162 static const struct mv88e6xxx_ops mv88e6095_ops = {
4163         /* MV88E6XXX_FAMILY_6095 */
4164         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4165         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4166         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4167         .phy_read = mv88e6185_phy_ppu_read,
4168         .phy_write = mv88e6185_phy_ppu_write,
4169         .port_set_link = mv88e6xxx_port_set_link,
4170         .port_sync_link = mv88e6185_port_sync_link,
4171         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4172         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4173         .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4174         .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4175         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4176         .port_get_cmode = mv88e6185_port_get_cmode,
4177         .port_setup_message_port = mv88e6xxx_setup_message_port,
4178         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4179         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4180         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4181         .stats_get_strings = mv88e6095_stats_get_strings,
4182         .stats_get_stats = mv88e6095_stats_get_stats,
4183         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4184         .serdes_power = mv88e6185_serdes_power,
4185         .serdes_get_lane = mv88e6185_serdes_get_lane,
4186         .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
4187         .ppu_enable = mv88e6185_g1_ppu_enable,
4188         .ppu_disable = mv88e6185_g1_ppu_disable,
4189         .reset = mv88e6185_g1_reset,
4190         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4191         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4192         .phylink_get_caps = mv88e6095_phylink_get_caps,
4193         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4194 };
4195
4196 static const struct mv88e6xxx_ops mv88e6097_ops = {
4197         /* MV88E6XXX_FAMILY_6097 */
4198         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4199         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4200         .irl_init_all = mv88e6352_g2_irl_init_all,
4201         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4202         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4203         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4204         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4205         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4206         .port_set_link = mv88e6xxx_port_set_link,
4207         .port_sync_link = mv88e6185_port_sync_link,
4208         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4209         .port_tag_remap = mv88e6095_port_tag_remap,
4210         .port_set_policy = mv88e6352_port_set_policy,
4211         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4212         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4213         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4214         .port_set_ether_type = mv88e6351_port_set_ether_type,
4215         .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4216         .port_pause_limit = mv88e6097_port_pause_limit,
4217         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4218         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4219         .port_get_cmode = mv88e6185_port_get_cmode,
4220         .port_setup_message_port = mv88e6xxx_setup_message_port,
4221         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4222         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4223         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4224         .stats_get_strings = mv88e6095_stats_get_strings,
4225         .stats_get_stats = mv88e6095_stats_get_stats,
4226         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4227         .set_egress_port = mv88e6095_g1_set_egress_port,
4228         .watchdog_ops = &mv88e6097_watchdog_ops,
4229         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4230         .serdes_power = mv88e6185_serdes_power,
4231         .serdes_get_lane = mv88e6185_serdes_get_lane,
4232         .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
4233         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4234         .serdes_irq_enable = mv88e6097_serdes_irq_enable,
4235         .serdes_irq_status = mv88e6097_serdes_irq_status,
4236         .pot_clear = mv88e6xxx_g2_pot_clear,
4237         .reset = mv88e6352_g1_reset,
4238         .rmu_disable = mv88e6085_g1_rmu_disable,
4239         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4240         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4241         .phylink_get_caps = mv88e6095_phylink_get_caps,
4242         .stu_getnext = mv88e6352_g1_stu_getnext,
4243         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4244         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4245 };
4246
4247 static const struct mv88e6xxx_ops mv88e6123_ops = {
4248         /* MV88E6XXX_FAMILY_6165 */
4249         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4250         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4251         .irl_init_all = mv88e6352_g2_irl_init_all,
4252         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4253         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4254         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4255         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4256         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4257         .port_set_link = mv88e6xxx_port_set_link,
4258         .port_sync_link = mv88e6xxx_port_sync_link,
4259         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4260         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4261         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4262         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4263         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4264         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4265         .port_get_cmode = mv88e6185_port_get_cmode,
4266         .port_setup_message_port = mv88e6xxx_setup_message_port,
4267         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4268         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4269         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4270         .stats_get_strings = mv88e6095_stats_get_strings,
4271         .stats_get_stats = mv88e6095_stats_get_stats,
4272         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4273         .set_egress_port = mv88e6095_g1_set_egress_port,
4274         .watchdog_ops = &mv88e6097_watchdog_ops,
4275         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4276         .pot_clear = mv88e6xxx_g2_pot_clear,
4277         .reset = mv88e6352_g1_reset,
4278         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4279         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4280         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4281         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4282         .stu_getnext = mv88e6352_g1_stu_getnext,
4283         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4284         .phylink_get_caps = mv88e6185_phylink_get_caps,
4285         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4286 };
4287
4288 static const struct mv88e6xxx_ops mv88e6131_ops = {
4289         /* MV88E6XXX_FAMILY_6185 */
4290         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4291         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4292         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4293         .phy_read = mv88e6185_phy_ppu_read,
4294         .phy_write = mv88e6185_phy_ppu_write,
4295         .port_set_link = mv88e6xxx_port_set_link,
4296         .port_sync_link = mv88e6xxx_port_sync_link,
4297         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4298         .port_tag_remap = mv88e6095_port_tag_remap,
4299         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4300         .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4301         .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4302         .port_set_ether_type = mv88e6351_port_set_ether_type,
4303         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4304         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4305         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4306         .port_pause_limit = mv88e6097_port_pause_limit,
4307         .port_set_pause = mv88e6185_port_set_pause,
4308         .port_get_cmode = mv88e6185_port_get_cmode,
4309         .port_setup_message_port = mv88e6xxx_setup_message_port,
4310         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4311         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4312         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4313         .stats_get_strings = mv88e6095_stats_get_strings,
4314         .stats_get_stats = mv88e6095_stats_get_stats,
4315         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4316         .set_egress_port = mv88e6095_g1_set_egress_port,
4317         .watchdog_ops = &mv88e6097_watchdog_ops,
4318         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4319         .ppu_enable = mv88e6185_g1_ppu_enable,
4320         .set_cascade_port = mv88e6185_g1_set_cascade_port,
4321         .ppu_disable = mv88e6185_g1_ppu_disable,
4322         .reset = mv88e6185_g1_reset,
4323         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4324         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4325         .phylink_get_caps = mv88e6185_phylink_get_caps,
4326 };
4327
4328 static const struct mv88e6xxx_ops mv88e6141_ops = {
4329         /* MV88E6XXX_FAMILY_6341 */
4330         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4331         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4332         .irl_init_all = mv88e6352_g2_irl_init_all,
4333         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4334         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4335         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4336         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4337         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4338         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4339         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4340         .port_set_link = mv88e6xxx_port_set_link,
4341         .port_sync_link = mv88e6xxx_port_sync_link,
4342         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4343         .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
4344         .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4345         .port_tag_remap = mv88e6095_port_tag_remap,
4346         .port_set_policy = mv88e6352_port_set_policy,
4347         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4348         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4349         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4350         .port_set_ether_type = mv88e6351_port_set_ether_type,
4351         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4352         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4353         .port_pause_limit = mv88e6097_port_pause_limit,
4354         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4355         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4356         .port_get_cmode = mv88e6352_port_get_cmode,
4357         .port_set_cmode = mv88e6341_port_set_cmode,
4358         .port_setup_message_port = mv88e6xxx_setup_message_port,
4359         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4360         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4361         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4362         .stats_get_strings = mv88e6320_stats_get_strings,
4363         .stats_get_stats = mv88e6390_stats_get_stats,
4364         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4365         .set_egress_port = mv88e6390_g1_set_egress_port,
4366         .watchdog_ops = &mv88e6390_watchdog_ops,
4367         .mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
4368         .pot_clear = mv88e6xxx_g2_pot_clear,
4369         .reset = mv88e6352_g1_reset,
4370         .rmu_disable = mv88e6390_g1_rmu_disable,
4371         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4372         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4373         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4374         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4375         .stu_getnext = mv88e6352_g1_stu_getnext,
4376         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4377         .serdes_power = mv88e6390_serdes_power,
4378         .serdes_get_lane = mv88e6341_serdes_get_lane,
4379         /* Check status register pause & lpa register */
4380         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4381         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4382         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4383         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4384         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4385         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4386         .serdes_irq_status = mv88e6390_serdes_irq_status,
4387         .gpio_ops = &mv88e6352_gpio_ops,
4388         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4389         .serdes_get_strings = mv88e6390_serdes_get_strings,
4390         .serdes_get_stats = mv88e6390_serdes_get_stats,
4391         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4392         .serdes_get_regs = mv88e6390_serdes_get_regs,
4393         .phylink_get_caps = mv88e6341_phylink_get_caps,
4394 };
4395
4396 static const struct mv88e6xxx_ops mv88e6161_ops = {
4397         /* MV88E6XXX_FAMILY_6165 */
4398         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4399         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4400         .irl_init_all = mv88e6352_g2_irl_init_all,
4401         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4402         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4403         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4404         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4405         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4406         .port_set_link = mv88e6xxx_port_set_link,
4407         .port_sync_link = mv88e6xxx_port_sync_link,
4408         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4409         .port_tag_remap = mv88e6095_port_tag_remap,
4410         .port_set_policy = mv88e6352_port_set_policy,
4411         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4412         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4413         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4414         .port_set_ether_type = mv88e6351_port_set_ether_type,
4415         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4416         .port_pause_limit = mv88e6097_port_pause_limit,
4417         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4418         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4419         .port_get_cmode = mv88e6185_port_get_cmode,
4420         .port_setup_message_port = mv88e6xxx_setup_message_port,
4421         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4422         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4423         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4424         .stats_get_strings = mv88e6095_stats_get_strings,
4425         .stats_get_stats = mv88e6095_stats_get_stats,
4426         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4427         .set_egress_port = mv88e6095_g1_set_egress_port,
4428         .watchdog_ops = &mv88e6097_watchdog_ops,
4429         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4430         .pot_clear = mv88e6xxx_g2_pot_clear,
4431         .reset = mv88e6352_g1_reset,
4432         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4433         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4434         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4435         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4436         .stu_getnext = mv88e6352_g1_stu_getnext,
4437         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4438         .avb_ops = &mv88e6165_avb_ops,
4439         .ptp_ops = &mv88e6165_ptp_ops,
4440         .phylink_get_caps = mv88e6185_phylink_get_caps,
4441         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4442 };
4443
4444 static const struct mv88e6xxx_ops mv88e6165_ops = {
4445         /* MV88E6XXX_FAMILY_6165 */
4446         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4447         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4448         .irl_init_all = mv88e6352_g2_irl_init_all,
4449         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4450         .phy_read = mv88e6165_phy_read,
4451         .phy_write = mv88e6165_phy_write,
4452         .port_set_link = mv88e6xxx_port_set_link,
4453         .port_sync_link = mv88e6xxx_port_sync_link,
4454         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4455         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4456         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4457         .port_get_cmode = mv88e6185_port_get_cmode,
4458         .port_setup_message_port = mv88e6xxx_setup_message_port,
4459         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4460         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4461         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4462         .stats_get_strings = mv88e6095_stats_get_strings,
4463         .stats_get_stats = mv88e6095_stats_get_stats,
4464         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4465         .set_egress_port = mv88e6095_g1_set_egress_port,
4466         .watchdog_ops = &mv88e6097_watchdog_ops,
4467         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4468         .pot_clear = mv88e6xxx_g2_pot_clear,
4469         .reset = mv88e6352_g1_reset,
4470         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4471         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4472         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4473         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4474         .stu_getnext = mv88e6352_g1_stu_getnext,
4475         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4476         .avb_ops = &mv88e6165_avb_ops,
4477         .ptp_ops = &mv88e6165_ptp_ops,
4478         .phylink_get_caps = mv88e6185_phylink_get_caps,
4479 };
4480
4481 static const struct mv88e6xxx_ops mv88e6171_ops = {
4482         /* MV88E6XXX_FAMILY_6351 */
4483         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4484         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4485         .irl_init_all = mv88e6352_g2_irl_init_all,
4486         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4487         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4488         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4489         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4490         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4491         .port_set_link = mv88e6xxx_port_set_link,
4492         .port_sync_link = mv88e6xxx_port_sync_link,
4493         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4494         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4495         .port_tag_remap = mv88e6095_port_tag_remap,
4496         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4497         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4498         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4499         .port_set_ether_type = mv88e6351_port_set_ether_type,
4500         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4501         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4502         .port_pause_limit = mv88e6097_port_pause_limit,
4503         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4504         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4505         .port_get_cmode = mv88e6352_port_get_cmode,
4506         .port_setup_message_port = mv88e6xxx_setup_message_port,
4507         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4508         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4509         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4510         .stats_get_strings = mv88e6095_stats_get_strings,
4511         .stats_get_stats = mv88e6095_stats_get_stats,
4512         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4513         .set_egress_port = mv88e6095_g1_set_egress_port,
4514         .watchdog_ops = &mv88e6097_watchdog_ops,
4515         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4516         .pot_clear = mv88e6xxx_g2_pot_clear,
4517         .reset = mv88e6352_g1_reset,
4518         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4519         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4520         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4521         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4522         .stu_getnext = mv88e6352_g1_stu_getnext,
4523         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4524         .phylink_get_caps = mv88e6185_phylink_get_caps,
4525 };
4526
4527 static const struct mv88e6xxx_ops mv88e6172_ops = {
4528         /* MV88E6XXX_FAMILY_6352 */
4529         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4530         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4531         .irl_init_all = mv88e6352_g2_irl_init_all,
4532         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4533         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4534         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4535         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4536         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4537         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4538         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4539         .port_set_link = mv88e6xxx_port_set_link,
4540         .port_sync_link = mv88e6xxx_port_sync_link,
4541         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4542         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4543         .port_tag_remap = mv88e6095_port_tag_remap,
4544         .port_set_policy = mv88e6352_port_set_policy,
4545         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4546         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4547         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4548         .port_set_ether_type = mv88e6351_port_set_ether_type,
4549         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4550         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4551         .port_pause_limit = mv88e6097_port_pause_limit,
4552         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4553         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4554         .port_get_cmode = mv88e6352_port_get_cmode,
4555         .port_setup_message_port = mv88e6xxx_setup_message_port,
4556         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4557         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4558         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4559         .stats_get_strings = mv88e6095_stats_get_strings,
4560         .stats_get_stats = mv88e6095_stats_get_stats,
4561         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4562         .set_egress_port = mv88e6095_g1_set_egress_port,
4563         .watchdog_ops = &mv88e6097_watchdog_ops,
4564         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4565         .pot_clear = mv88e6xxx_g2_pot_clear,
4566         .reset = mv88e6352_g1_reset,
4567         .rmu_disable = mv88e6352_g1_rmu_disable,
4568         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4569         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4570         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4571         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4572         .stu_getnext = mv88e6352_g1_stu_getnext,
4573         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4574         .serdes_get_lane = mv88e6352_serdes_get_lane,
4575         .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4576         .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4577         .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4578         .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4579         .serdes_power = mv88e6352_serdes_power,
4580         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4581         .serdes_get_regs = mv88e6352_serdes_get_regs,
4582         .gpio_ops = &mv88e6352_gpio_ops,
4583         .phylink_get_caps = mv88e6352_phylink_get_caps,
4584 };
4585
4586 static const struct mv88e6xxx_ops mv88e6175_ops = {
4587         /* MV88E6XXX_FAMILY_6351 */
4588         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4589         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4590         .irl_init_all = mv88e6352_g2_irl_init_all,
4591         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4592         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4593         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4594         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4595         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4596         .port_set_link = mv88e6xxx_port_set_link,
4597         .port_sync_link = mv88e6xxx_port_sync_link,
4598         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4599         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4600         .port_tag_remap = mv88e6095_port_tag_remap,
4601         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4602         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4603         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4604         .port_set_ether_type = mv88e6351_port_set_ether_type,
4605         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4606         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4607         .port_pause_limit = mv88e6097_port_pause_limit,
4608         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4609         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4610         .port_get_cmode = mv88e6352_port_get_cmode,
4611         .port_setup_message_port = mv88e6xxx_setup_message_port,
4612         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4613         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4614         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4615         .stats_get_strings = mv88e6095_stats_get_strings,
4616         .stats_get_stats = mv88e6095_stats_get_stats,
4617         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4618         .set_egress_port = mv88e6095_g1_set_egress_port,
4619         .watchdog_ops = &mv88e6097_watchdog_ops,
4620         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4621         .pot_clear = mv88e6xxx_g2_pot_clear,
4622         .reset = mv88e6352_g1_reset,
4623         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4624         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4625         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4626         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4627         .stu_getnext = mv88e6352_g1_stu_getnext,
4628         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4629         .phylink_get_caps = mv88e6185_phylink_get_caps,
4630 };
4631
4632 static const struct mv88e6xxx_ops mv88e6176_ops = {
4633         /* MV88E6XXX_FAMILY_6352 */
4634         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4635         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4636         .irl_init_all = mv88e6352_g2_irl_init_all,
4637         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4638         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4639         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4640         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4641         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4642         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4643         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4644         .port_set_link = mv88e6xxx_port_set_link,
4645         .port_sync_link = mv88e6xxx_port_sync_link,
4646         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4647         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4648         .port_tag_remap = mv88e6095_port_tag_remap,
4649         .port_set_policy = mv88e6352_port_set_policy,
4650         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4651         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4652         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4653         .port_set_ether_type = mv88e6351_port_set_ether_type,
4654         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4655         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4656         .port_pause_limit = mv88e6097_port_pause_limit,
4657         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4658         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4659         .port_get_cmode = mv88e6352_port_get_cmode,
4660         .port_setup_message_port = mv88e6xxx_setup_message_port,
4661         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4662         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4663         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4664         .stats_get_strings = mv88e6095_stats_get_strings,
4665         .stats_get_stats = mv88e6095_stats_get_stats,
4666         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4667         .set_egress_port = mv88e6095_g1_set_egress_port,
4668         .watchdog_ops = &mv88e6097_watchdog_ops,
4669         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4670         .pot_clear = mv88e6xxx_g2_pot_clear,
4671         .reset = mv88e6352_g1_reset,
4672         .rmu_disable = mv88e6352_g1_rmu_disable,
4673         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4674         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4675         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4676         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4677         .stu_getnext = mv88e6352_g1_stu_getnext,
4678         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4679         .serdes_get_lane = mv88e6352_serdes_get_lane,
4680         .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4681         .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4682         .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4683         .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4684         .serdes_power = mv88e6352_serdes_power,
4685         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4686         .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4687         .serdes_irq_status = mv88e6352_serdes_irq_status,
4688         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4689         .serdes_get_regs = mv88e6352_serdes_get_regs,
4690         .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4691         .gpio_ops = &mv88e6352_gpio_ops,
4692         .phylink_get_caps = mv88e6352_phylink_get_caps,
4693 };
4694
4695 static const struct mv88e6xxx_ops mv88e6185_ops = {
4696         /* MV88E6XXX_FAMILY_6185 */
4697         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4698         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4699         .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4700         .phy_read = mv88e6185_phy_ppu_read,
4701         .phy_write = mv88e6185_phy_ppu_write,
4702         .port_set_link = mv88e6xxx_port_set_link,
4703         .port_sync_link = mv88e6185_port_sync_link,
4704         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4705         .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4706         .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4707         .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4708         .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4709         .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4710         .port_set_pause = mv88e6185_port_set_pause,
4711         .port_get_cmode = mv88e6185_port_get_cmode,
4712         .port_setup_message_port = mv88e6xxx_setup_message_port,
4713         .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4714         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4715         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4716         .stats_get_strings = mv88e6095_stats_get_strings,
4717         .stats_get_stats = mv88e6095_stats_get_stats,
4718         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4719         .set_egress_port = mv88e6095_g1_set_egress_port,
4720         .watchdog_ops = &mv88e6097_watchdog_ops,
4721         .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4722         .serdes_power = mv88e6185_serdes_power,
4723         .serdes_get_lane = mv88e6185_serdes_get_lane,
4724         .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
4725         .set_cascade_port = mv88e6185_g1_set_cascade_port,
4726         .ppu_enable = mv88e6185_g1_ppu_enable,
4727         .ppu_disable = mv88e6185_g1_ppu_disable,
4728         .reset = mv88e6185_g1_reset,
4729         .vtu_getnext = mv88e6185_g1_vtu_getnext,
4730         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4731         .phylink_get_caps = mv88e6185_phylink_get_caps,
4732         .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4733 };
4734
4735 static const struct mv88e6xxx_ops mv88e6190_ops = {
4736         /* MV88E6XXX_FAMILY_6390 */
4737         .setup_errata = mv88e6390_setup_errata,
4738         .irl_init_all = mv88e6390_g2_irl_init_all,
4739         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4740         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4741         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4742         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4743         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4744         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4745         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4746         .port_set_link = mv88e6xxx_port_set_link,
4747         .port_sync_link = mv88e6xxx_port_sync_link,
4748         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4749         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4750         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4751         .port_tag_remap = mv88e6390_port_tag_remap,
4752         .port_set_policy = mv88e6352_port_set_policy,
4753         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4754         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4755         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4756         .port_set_ether_type = mv88e6351_port_set_ether_type,
4757         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4758         .port_pause_limit = mv88e6390_port_pause_limit,
4759         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4760         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4761         .port_get_cmode = mv88e6352_port_get_cmode,
4762         .port_set_cmode = mv88e6390_port_set_cmode,
4763         .port_setup_message_port = mv88e6xxx_setup_message_port,
4764         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4765         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4766         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4767         .stats_get_strings = mv88e6320_stats_get_strings,
4768         .stats_get_stats = mv88e6390_stats_get_stats,
4769         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4770         .set_egress_port = mv88e6390_g1_set_egress_port,
4771         .watchdog_ops = &mv88e6390_watchdog_ops,
4772         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4773         .pot_clear = mv88e6xxx_g2_pot_clear,
4774         .reset = mv88e6352_g1_reset,
4775         .rmu_disable = mv88e6390_g1_rmu_disable,
4776         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4777         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4778         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4779         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4780         .stu_getnext = mv88e6390_g1_stu_getnext,
4781         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4782         .serdes_power = mv88e6390_serdes_power,
4783         .serdes_get_lane = mv88e6390_serdes_get_lane,
4784         /* Check status register pause & lpa register */
4785         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4786         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4787         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4788         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4789         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4790         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4791         .serdes_irq_status = mv88e6390_serdes_irq_status,
4792         .serdes_get_strings = mv88e6390_serdes_get_strings,
4793         .serdes_get_stats = mv88e6390_serdes_get_stats,
4794         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4795         .serdes_get_regs = mv88e6390_serdes_get_regs,
4796         .gpio_ops = &mv88e6352_gpio_ops,
4797         .phylink_get_caps = mv88e6390_phylink_get_caps,
4798 };
4799
4800 static const struct mv88e6xxx_ops mv88e6190x_ops = {
4801         /* MV88E6XXX_FAMILY_6390 */
4802         .setup_errata = mv88e6390_setup_errata,
4803         .irl_init_all = mv88e6390_g2_irl_init_all,
4804         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4805         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4806         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4807         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4808         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4809         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4810         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4811         .port_set_link = mv88e6xxx_port_set_link,
4812         .port_sync_link = mv88e6xxx_port_sync_link,
4813         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4814         .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4815         .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4816         .port_tag_remap = mv88e6390_port_tag_remap,
4817         .port_set_policy = mv88e6352_port_set_policy,
4818         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4819         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4820         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4821         .port_set_ether_type = mv88e6351_port_set_ether_type,
4822         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4823         .port_pause_limit = mv88e6390_port_pause_limit,
4824         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4825         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4826         .port_get_cmode = mv88e6352_port_get_cmode,
4827         .port_set_cmode = mv88e6390x_port_set_cmode,
4828         .port_setup_message_port = mv88e6xxx_setup_message_port,
4829         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4830         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4831         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4832         .stats_get_strings = mv88e6320_stats_get_strings,
4833         .stats_get_stats = mv88e6390_stats_get_stats,
4834         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4835         .set_egress_port = mv88e6390_g1_set_egress_port,
4836         .watchdog_ops = &mv88e6390_watchdog_ops,
4837         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4838         .pot_clear = mv88e6xxx_g2_pot_clear,
4839         .reset = mv88e6352_g1_reset,
4840         .rmu_disable = mv88e6390_g1_rmu_disable,
4841         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4842         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4843         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4844         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4845         .stu_getnext = mv88e6390_g1_stu_getnext,
4846         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4847         .serdes_power = mv88e6390_serdes_power,
4848         .serdes_get_lane = mv88e6390x_serdes_get_lane,
4849         /* Check status register pause & lpa register */
4850         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4851         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4852         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4853         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4854         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4855         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4856         .serdes_irq_status = mv88e6390_serdes_irq_status,
4857         .serdes_get_strings = mv88e6390_serdes_get_strings,
4858         .serdes_get_stats = mv88e6390_serdes_get_stats,
4859         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4860         .serdes_get_regs = mv88e6390_serdes_get_regs,
4861         .gpio_ops = &mv88e6352_gpio_ops,
4862         .phylink_get_caps = mv88e6390x_phylink_get_caps,
4863 };
4864
4865 static const struct mv88e6xxx_ops mv88e6191_ops = {
4866         /* MV88E6XXX_FAMILY_6390 */
4867         .setup_errata = mv88e6390_setup_errata,
4868         .irl_init_all = mv88e6390_g2_irl_init_all,
4869         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4870         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4871         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4872         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4873         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4874         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4875         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4876         .port_set_link = mv88e6xxx_port_set_link,
4877         .port_sync_link = mv88e6xxx_port_sync_link,
4878         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4879         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4880         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4881         .port_tag_remap = mv88e6390_port_tag_remap,
4882         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4883         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4884         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4885         .port_set_ether_type = mv88e6351_port_set_ether_type,
4886         .port_pause_limit = mv88e6390_port_pause_limit,
4887         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4888         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4889         .port_get_cmode = mv88e6352_port_get_cmode,
4890         .port_set_cmode = mv88e6390_port_set_cmode,
4891         .port_setup_message_port = mv88e6xxx_setup_message_port,
4892         .stats_snapshot = mv88e6390_g1_stats_snapshot,
4893         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4894         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4895         .stats_get_strings = mv88e6320_stats_get_strings,
4896         .stats_get_stats = mv88e6390_stats_get_stats,
4897         .set_cpu_port = mv88e6390_g1_set_cpu_port,
4898         .set_egress_port = mv88e6390_g1_set_egress_port,
4899         .watchdog_ops = &mv88e6390_watchdog_ops,
4900         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4901         .pot_clear = mv88e6xxx_g2_pot_clear,
4902         .reset = mv88e6352_g1_reset,
4903         .rmu_disable = mv88e6390_g1_rmu_disable,
4904         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4905         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4906         .vtu_getnext = mv88e6390_g1_vtu_getnext,
4907         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4908         .stu_getnext = mv88e6390_g1_stu_getnext,
4909         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4910         .serdes_power = mv88e6390_serdes_power,
4911         .serdes_get_lane = mv88e6390_serdes_get_lane,
4912         /* Check status register pause & lpa register */
4913         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4914         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4915         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4916         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4917         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4918         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4919         .serdes_irq_status = mv88e6390_serdes_irq_status,
4920         .serdes_get_strings = mv88e6390_serdes_get_strings,
4921         .serdes_get_stats = mv88e6390_serdes_get_stats,
4922         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4923         .serdes_get_regs = mv88e6390_serdes_get_regs,
4924         .avb_ops = &mv88e6390_avb_ops,
4925         .ptp_ops = &mv88e6352_ptp_ops,
4926         .phylink_get_caps = mv88e6390_phylink_get_caps,
4927 };
4928
4929 static const struct mv88e6xxx_ops mv88e6240_ops = {
4930         /* MV88E6XXX_FAMILY_6352 */
4931         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4932         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4933         .irl_init_all = mv88e6352_g2_irl_init_all,
4934         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4935         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4936         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4937         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
4938         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
4939         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
4940         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
4941         .port_set_link = mv88e6xxx_port_set_link,
4942         .port_sync_link = mv88e6xxx_port_sync_link,
4943         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4944         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4945         .port_tag_remap = mv88e6095_port_tag_remap,
4946         .port_set_policy = mv88e6352_port_set_policy,
4947         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4948         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4949         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4950         .port_set_ether_type = mv88e6351_port_set_ether_type,
4951         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4952         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4953         .port_pause_limit = mv88e6097_port_pause_limit,
4954         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4955         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4956         .port_get_cmode = mv88e6352_port_get_cmode,
4957         .port_setup_message_port = mv88e6xxx_setup_message_port,
4958         .stats_snapshot = mv88e6320_g1_stats_snapshot,
4959         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4960         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4961         .stats_get_strings = mv88e6095_stats_get_strings,
4962         .stats_get_stats = mv88e6095_stats_get_stats,
4963         .set_cpu_port = mv88e6095_g1_set_cpu_port,
4964         .set_egress_port = mv88e6095_g1_set_egress_port,
4965         .watchdog_ops = &mv88e6097_watchdog_ops,
4966         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4967         .pot_clear = mv88e6xxx_g2_pot_clear,
4968         .reset = mv88e6352_g1_reset,
4969         .rmu_disable = mv88e6352_g1_rmu_disable,
4970         .atu_get_hash = mv88e6165_g1_atu_get_hash,
4971         .atu_set_hash = mv88e6165_g1_atu_set_hash,
4972         .vtu_getnext = mv88e6352_g1_vtu_getnext,
4973         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4974         .stu_getnext = mv88e6352_g1_stu_getnext,
4975         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4976         .serdes_get_lane = mv88e6352_serdes_get_lane,
4977         .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4978         .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4979         .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4980         .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4981         .serdes_power = mv88e6352_serdes_power,
4982         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4983         .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4984         .serdes_irq_status = mv88e6352_serdes_irq_status,
4985         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4986         .serdes_get_regs = mv88e6352_serdes_get_regs,
4987         .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4988         .gpio_ops = &mv88e6352_gpio_ops,
4989         .avb_ops = &mv88e6352_avb_ops,
4990         .ptp_ops = &mv88e6352_ptp_ops,
4991         .phylink_get_caps = mv88e6352_phylink_get_caps,
4992 };
4993
4994 static const struct mv88e6xxx_ops mv88e6250_ops = {
4995         /* MV88E6XXX_FAMILY_6250 */
4996         .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
4997         .ip_pri_map = mv88e6085_g1_ip_pri_map,
4998         .irl_init_all = mv88e6352_g2_irl_init_all,
4999         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5000         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5001         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5002         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5003         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5004         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5005         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5006         .port_set_link = mv88e6xxx_port_set_link,
5007         .port_sync_link = mv88e6xxx_port_sync_link,
5008         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5009         .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
5010         .port_tag_remap = mv88e6095_port_tag_remap,
5011         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5012         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5013         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5014         .port_set_ether_type = mv88e6351_port_set_ether_type,
5015         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5016         .port_pause_limit = mv88e6097_port_pause_limit,
5017         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5018         .stats_snapshot = mv88e6320_g1_stats_snapshot,
5019         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5020         .stats_get_sset_count = mv88e6250_stats_get_sset_count,
5021         .stats_get_strings = mv88e6250_stats_get_strings,
5022         .stats_get_stats = mv88e6250_stats_get_stats,
5023         .set_cpu_port = mv88e6095_g1_set_cpu_port,
5024         .set_egress_port = mv88e6095_g1_set_egress_port,
5025         .watchdog_ops = &mv88e6250_watchdog_ops,
5026         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5027         .pot_clear = mv88e6xxx_g2_pot_clear,
5028         .reset = mv88e6250_g1_reset,
5029         .vtu_getnext = mv88e6185_g1_vtu_getnext,
5030         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5031         .avb_ops = &mv88e6352_avb_ops,
5032         .ptp_ops = &mv88e6250_ptp_ops,
5033         .phylink_get_caps = mv88e6250_phylink_get_caps,
5034 };
5035
5036 static const struct mv88e6xxx_ops mv88e6290_ops = {
5037         /* MV88E6XXX_FAMILY_6390 */
5038         .setup_errata = mv88e6390_setup_errata,
5039         .irl_init_all = mv88e6390_g2_irl_init_all,
5040         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5041         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5042         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5043         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5044         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5045         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5046         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5047         .port_set_link = mv88e6xxx_port_set_link,
5048         .port_sync_link = mv88e6xxx_port_sync_link,
5049         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5050         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
5051         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
5052         .port_tag_remap = mv88e6390_port_tag_remap,
5053         .port_set_policy = mv88e6352_port_set_policy,
5054         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5055         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5056         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5057         .port_set_ether_type = mv88e6351_port_set_ether_type,
5058         .port_pause_limit = mv88e6390_port_pause_limit,
5059         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5060         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5061         .port_get_cmode = mv88e6352_port_get_cmode,
5062         .port_set_cmode = mv88e6390_port_set_cmode,
5063         .port_setup_message_port = mv88e6xxx_setup_message_port,
5064         .stats_snapshot = mv88e6390_g1_stats_snapshot,
5065         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5066         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5067         .stats_get_strings = mv88e6320_stats_get_strings,
5068         .stats_get_stats = mv88e6390_stats_get_stats,
5069         .set_cpu_port = mv88e6390_g1_set_cpu_port,
5070         .set_egress_port = mv88e6390_g1_set_egress_port,
5071         .watchdog_ops = &mv88e6390_watchdog_ops,
5072         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5073         .pot_clear = mv88e6xxx_g2_pot_clear,
5074         .reset = mv88e6352_g1_reset,
5075         .rmu_disable = mv88e6390_g1_rmu_disable,
5076         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5077         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5078         .vtu_getnext = mv88e6390_g1_vtu_getnext,
5079         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5080         .stu_getnext = mv88e6390_g1_stu_getnext,
5081         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5082         .serdes_power = mv88e6390_serdes_power,
5083         .serdes_get_lane = mv88e6390_serdes_get_lane,
5084         /* Check status register pause & lpa register */
5085         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
5086         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
5087         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
5088         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
5089         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5090         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
5091         .serdes_irq_status = mv88e6390_serdes_irq_status,
5092         .serdes_get_strings = mv88e6390_serdes_get_strings,
5093         .serdes_get_stats = mv88e6390_serdes_get_stats,
5094         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5095         .serdes_get_regs = mv88e6390_serdes_get_regs,
5096         .gpio_ops = &mv88e6352_gpio_ops,
5097         .avb_ops = &mv88e6390_avb_ops,
5098         .ptp_ops = &mv88e6390_ptp_ops,
5099         .phylink_get_caps = mv88e6390_phylink_get_caps,
5100 };
5101
5102 static const struct mv88e6xxx_ops mv88e6320_ops = {
5103         /* MV88E6XXX_FAMILY_6320 */
5104         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5105         .ip_pri_map = mv88e6085_g1_ip_pri_map,
5106         .irl_init_all = mv88e6352_g2_irl_init_all,
5107         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5108         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5109         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5110         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5111         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5112         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5113         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5114         .port_set_link = mv88e6xxx_port_set_link,
5115         .port_sync_link = mv88e6xxx_port_sync_link,
5116         .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5117         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5118         .port_tag_remap = mv88e6095_port_tag_remap,
5119         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5120         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5121         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5122         .port_set_ether_type = mv88e6351_port_set_ether_type,
5123         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5124         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5125         .port_pause_limit = mv88e6097_port_pause_limit,
5126         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5127         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5128         .port_get_cmode = mv88e6352_port_get_cmode,
5129         .port_setup_message_port = mv88e6xxx_setup_message_port,
5130         .stats_snapshot = mv88e6320_g1_stats_snapshot,
5131         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5132         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5133         .stats_get_strings = mv88e6320_stats_get_strings,
5134         .stats_get_stats = mv88e6320_stats_get_stats,
5135         .set_cpu_port = mv88e6095_g1_set_cpu_port,
5136         .set_egress_port = mv88e6095_g1_set_egress_port,
5137         .watchdog_ops = &mv88e6390_watchdog_ops,
5138         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5139         .pot_clear = mv88e6xxx_g2_pot_clear,
5140         .reset = mv88e6352_g1_reset,
5141         .vtu_getnext = mv88e6185_g1_vtu_getnext,
5142         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5143         .gpio_ops = &mv88e6352_gpio_ops,
5144         .avb_ops = &mv88e6352_avb_ops,
5145         .ptp_ops = &mv88e6352_ptp_ops,
5146         .phylink_get_caps = mv88e6185_phylink_get_caps,
5147 };
5148
5149 static const struct mv88e6xxx_ops mv88e6321_ops = {
5150         /* MV88E6XXX_FAMILY_6320 */
5151         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5152         .ip_pri_map = mv88e6085_g1_ip_pri_map,
5153         .irl_init_all = mv88e6352_g2_irl_init_all,
5154         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5155         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5156         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5157         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5158         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5159         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5160         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5161         .port_set_link = mv88e6xxx_port_set_link,
5162         .port_sync_link = mv88e6xxx_port_sync_link,
5163         .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5164         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5165         .port_tag_remap = mv88e6095_port_tag_remap,
5166         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5167         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5168         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5169         .port_set_ether_type = mv88e6351_port_set_ether_type,
5170         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5171         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5172         .port_pause_limit = mv88e6097_port_pause_limit,
5173         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5174         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5175         .port_get_cmode = mv88e6352_port_get_cmode,
5176         .port_setup_message_port = mv88e6xxx_setup_message_port,
5177         .stats_snapshot = mv88e6320_g1_stats_snapshot,
5178         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5179         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5180         .stats_get_strings = mv88e6320_stats_get_strings,
5181         .stats_get_stats = mv88e6320_stats_get_stats,
5182         .set_cpu_port = mv88e6095_g1_set_cpu_port,
5183         .set_egress_port = mv88e6095_g1_set_egress_port,
5184         .watchdog_ops = &mv88e6390_watchdog_ops,
5185         .reset = mv88e6352_g1_reset,
5186         .vtu_getnext = mv88e6185_g1_vtu_getnext,
5187         .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5188         .gpio_ops = &mv88e6352_gpio_ops,
5189         .avb_ops = &mv88e6352_avb_ops,
5190         .ptp_ops = &mv88e6352_ptp_ops,
5191         .phylink_get_caps = mv88e6185_phylink_get_caps,
5192 };
5193
5194 static const struct mv88e6xxx_ops mv88e6341_ops = {
5195         /* MV88E6XXX_FAMILY_6341 */
5196         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5197         .ip_pri_map = mv88e6085_g1_ip_pri_map,
5198         .irl_init_all = mv88e6352_g2_irl_init_all,
5199         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5200         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5201         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5202         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5203         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5204         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5205         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5206         .port_set_link = mv88e6xxx_port_set_link,
5207         .port_sync_link = mv88e6xxx_port_sync_link,
5208         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5209         .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
5210         .port_max_speed_mode = mv88e6341_port_max_speed_mode,
5211         .port_tag_remap = mv88e6095_port_tag_remap,
5212         .port_set_policy = mv88e6352_port_set_policy,
5213         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5214         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5215         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5216         .port_set_ether_type = mv88e6351_port_set_ether_type,
5217         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5218         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5219         .port_pause_limit = mv88e6097_port_pause_limit,
5220         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5221         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5222         .port_get_cmode = mv88e6352_port_get_cmode,
5223         .port_set_cmode = mv88e6341_port_set_cmode,
5224         .port_setup_message_port = mv88e6xxx_setup_message_port,
5225         .stats_snapshot = mv88e6390_g1_stats_snapshot,
5226         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5227         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5228         .stats_get_strings = mv88e6320_stats_get_strings,
5229         .stats_get_stats = mv88e6390_stats_get_stats,
5230         .set_cpu_port = mv88e6390_g1_set_cpu_port,
5231         .set_egress_port = mv88e6390_g1_set_egress_port,
5232         .watchdog_ops = &mv88e6390_watchdog_ops,
5233         .mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
5234         .pot_clear = mv88e6xxx_g2_pot_clear,
5235         .reset = mv88e6352_g1_reset,
5236         .rmu_disable = mv88e6390_g1_rmu_disable,
5237         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5238         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5239         .vtu_getnext = mv88e6352_g1_vtu_getnext,
5240         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5241         .stu_getnext = mv88e6352_g1_stu_getnext,
5242         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5243         .serdes_power = mv88e6390_serdes_power,
5244         .serdes_get_lane = mv88e6341_serdes_get_lane,
5245         /* Check status register pause & lpa register */
5246         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
5247         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
5248         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
5249         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
5250         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5251         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
5252         .serdes_irq_status = mv88e6390_serdes_irq_status,
5253         .gpio_ops = &mv88e6352_gpio_ops,
5254         .avb_ops = &mv88e6390_avb_ops,
5255         .ptp_ops = &mv88e6352_ptp_ops,
5256         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5257         .serdes_get_strings = mv88e6390_serdes_get_strings,
5258         .serdes_get_stats = mv88e6390_serdes_get_stats,
5259         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5260         .serdes_get_regs = mv88e6390_serdes_get_regs,
5261         .phylink_get_caps = mv88e6341_phylink_get_caps,
5262 };
5263
5264 static const struct mv88e6xxx_ops mv88e6350_ops = {
5265         /* MV88E6XXX_FAMILY_6351 */
5266         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5267         .ip_pri_map = mv88e6085_g1_ip_pri_map,
5268         .irl_init_all = mv88e6352_g2_irl_init_all,
5269         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5270         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5271         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5272         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5273         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5274         .port_set_link = mv88e6xxx_port_set_link,
5275         .port_sync_link = mv88e6xxx_port_sync_link,
5276         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5277         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5278         .port_tag_remap = mv88e6095_port_tag_remap,
5279         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5280         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5281         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5282         .port_set_ether_type = mv88e6351_port_set_ether_type,
5283         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5284         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5285         .port_pause_limit = mv88e6097_port_pause_limit,
5286         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5287         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5288         .port_get_cmode = mv88e6352_port_get_cmode,
5289         .port_setup_message_port = mv88e6xxx_setup_message_port,
5290         .stats_snapshot = mv88e6320_g1_stats_snapshot,
5291         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5292         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5293         .stats_get_strings = mv88e6095_stats_get_strings,
5294         .stats_get_stats = mv88e6095_stats_get_stats,
5295         .set_cpu_port = mv88e6095_g1_set_cpu_port,
5296         .set_egress_port = mv88e6095_g1_set_egress_port,
5297         .watchdog_ops = &mv88e6097_watchdog_ops,
5298         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5299         .pot_clear = mv88e6xxx_g2_pot_clear,
5300         .reset = mv88e6352_g1_reset,
5301         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5302         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5303         .vtu_getnext = mv88e6352_g1_vtu_getnext,
5304         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5305         .stu_getnext = mv88e6352_g1_stu_getnext,
5306         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5307         .phylink_get_caps = mv88e6185_phylink_get_caps,
5308 };
5309
5310 static const struct mv88e6xxx_ops mv88e6351_ops = {
5311         /* MV88E6XXX_FAMILY_6351 */
5312         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5313         .ip_pri_map = mv88e6085_g1_ip_pri_map,
5314         .irl_init_all = mv88e6352_g2_irl_init_all,
5315         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5316         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5317         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5318         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5319         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5320         .port_set_link = mv88e6xxx_port_set_link,
5321         .port_sync_link = mv88e6xxx_port_sync_link,
5322         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5323         .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5324         .port_tag_remap = mv88e6095_port_tag_remap,
5325         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5326         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5327         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5328         .port_set_ether_type = mv88e6351_port_set_ether_type,
5329         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5330         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5331         .port_pause_limit = mv88e6097_port_pause_limit,
5332         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5333         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5334         .port_get_cmode = mv88e6352_port_get_cmode,
5335         .port_setup_message_port = mv88e6xxx_setup_message_port,
5336         .stats_snapshot = mv88e6320_g1_stats_snapshot,
5337         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5338         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5339         .stats_get_strings = mv88e6095_stats_get_strings,
5340         .stats_get_stats = mv88e6095_stats_get_stats,
5341         .set_cpu_port = mv88e6095_g1_set_cpu_port,
5342         .set_egress_port = mv88e6095_g1_set_egress_port,
5343         .watchdog_ops = &mv88e6097_watchdog_ops,
5344         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5345         .pot_clear = mv88e6xxx_g2_pot_clear,
5346         .reset = mv88e6352_g1_reset,
5347         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5348         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5349         .vtu_getnext = mv88e6352_g1_vtu_getnext,
5350         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5351         .stu_getnext = mv88e6352_g1_stu_getnext,
5352         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5353         .avb_ops = &mv88e6352_avb_ops,
5354         .ptp_ops = &mv88e6352_ptp_ops,
5355         .phylink_get_caps = mv88e6185_phylink_get_caps,
5356 };
5357
5358 static const struct mv88e6xxx_ops mv88e6352_ops = {
5359         /* MV88E6XXX_FAMILY_6352 */
5360         .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5361         .ip_pri_map = mv88e6085_g1_ip_pri_map,
5362         .irl_init_all = mv88e6352_g2_irl_init_all,
5363         .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5364         .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5365         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5366         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5367         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5368         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5369         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5370         .port_set_link = mv88e6xxx_port_set_link,
5371         .port_sync_link = mv88e6xxx_port_sync_link,
5372         .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5373         .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
5374         .port_tag_remap = mv88e6095_port_tag_remap,
5375         .port_set_policy = mv88e6352_port_set_policy,
5376         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5377         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5378         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5379         .port_set_ether_type = mv88e6351_port_set_ether_type,
5380         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5381         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5382         .port_pause_limit = mv88e6097_port_pause_limit,
5383         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5384         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5385         .port_get_cmode = mv88e6352_port_get_cmode,
5386         .port_setup_message_port = mv88e6xxx_setup_message_port,
5387         .stats_snapshot = mv88e6320_g1_stats_snapshot,
5388         .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5389         .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5390         .stats_get_strings = mv88e6095_stats_get_strings,
5391         .stats_get_stats = mv88e6095_stats_get_stats,
5392         .set_cpu_port = mv88e6095_g1_set_cpu_port,
5393         .set_egress_port = mv88e6095_g1_set_egress_port,
5394         .watchdog_ops = &mv88e6097_watchdog_ops,
5395         .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5396         .pot_clear = mv88e6xxx_g2_pot_clear,
5397         .reset = mv88e6352_g1_reset,
5398         .rmu_disable = mv88e6352_g1_rmu_disable,
5399         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5400         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5401         .vtu_getnext = mv88e6352_g1_vtu_getnext,
5402         .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5403         .stu_getnext = mv88e6352_g1_stu_getnext,
5404         .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5405         .serdes_get_lane = mv88e6352_serdes_get_lane,
5406         .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
5407         .serdes_pcs_config = mv88e6352_serdes_pcs_config,
5408         .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
5409         .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
5410         .serdes_power = mv88e6352_serdes_power,
5411         .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
5412         .serdes_irq_enable = mv88e6352_serdes_irq_enable,
5413         .serdes_irq_status = mv88e6352_serdes_irq_status,
5414         .gpio_ops = &mv88e6352_gpio_ops,
5415         .avb_ops = &mv88e6352_avb_ops,
5416         .ptp_ops = &mv88e6352_ptp_ops,
5417         .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
5418         .serdes_get_strings = mv88e6352_serdes_get_strings,
5419         .serdes_get_stats = mv88e6352_serdes_get_stats,
5420         .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
5421         .serdes_get_regs = mv88e6352_serdes_get_regs,
5422         .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
5423         .phylink_get_caps = mv88e6352_phylink_get_caps,
5424 };
5425
5426 static const struct mv88e6xxx_ops mv88e6390_ops = {
5427         /* MV88E6XXX_FAMILY_6390 */
5428         .setup_errata = mv88e6390_setup_errata,
5429         .irl_init_all = mv88e6390_g2_irl_init_all,
5430         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5431         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5432         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5433         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5434         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5435         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5436         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5437         .port_set_link = mv88e6xxx_port_set_link,
5438         .port_sync_link = mv88e6xxx_port_sync_link,
5439         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5440         .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
5441         .port_max_speed_mode = mv88e6390_port_max_speed_mode,
5442         .port_tag_remap = mv88e6390_port_tag_remap,
5443         .port_set_policy = mv88e6352_port_set_policy,
5444         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5445         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5446         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5447         .port_set_ether_type = mv88e6351_port_set_ether_type,
5448         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5449         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5450         .port_pause_limit = mv88e6390_port_pause_limit,
5451         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5452         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5453         .port_get_cmode = mv88e6352_port_get_cmode,
5454         .port_set_cmode = mv88e6390_port_set_cmode,
5455         .port_setup_message_port = mv88e6xxx_setup_message_port,
5456         .stats_snapshot = mv88e6390_g1_stats_snapshot,
5457         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5458         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5459         .stats_get_strings = mv88e6320_stats_get_strings,
5460         .stats_get_stats = mv88e6390_stats_get_stats,
5461         .set_cpu_port = mv88e6390_g1_set_cpu_port,
5462         .set_egress_port = mv88e6390_g1_set_egress_port,
5463         .watchdog_ops = &mv88e6390_watchdog_ops,
5464         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5465         .pot_clear = mv88e6xxx_g2_pot_clear,
5466         .reset = mv88e6352_g1_reset,
5467         .rmu_disable = mv88e6390_g1_rmu_disable,
5468         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5469         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5470         .vtu_getnext = mv88e6390_g1_vtu_getnext,
5471         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5472         .stu_getnext = mv88e6390_g1_stu_getnext,
5473         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5474         .serdes_power = mv88e6390_serdes_power,
5475         .serdes_get_lane = mv88e6390_serdes_get_lane,
5476         /* Check status register pause & lpa register */
5477         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
5478         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
5479         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
5480         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
5481         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5482         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
5483         .serdes_irq_status = mv88e6390_serdes_irq_status,
5484         .gpio_ops = &mv88e6352_gpio_ops,
5485         .avb_ops = &mv88e6390_avb_ops,
5486         .ptp_ops = &mv88e6390_ptp_ops,
5487         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5488         .serdes_get_strings = mv88e6390_serdes_get_strings,
5489         .serdes_get_stats = mv88e6390_serdes_get_stats,
5490         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5491         .serdes_get_regs = mv88e6390_serdes_get_regs,
5492         .phylink_get_caps = mv88e6390_phylink_get_caps,
5493 };
5494
5495 static const struct mv88e6xxx_ops mv88e6390x_ops = {
5496         /* MV88E6XXX_FAMILY_6390 */
5497         .setup_errata = mv88e6390_setup_errata,
5498         .irl_init_all = mv88e6390_g2_irl_init_all,
5499         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5500         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5501         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5502         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5503         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5504         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5505         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5506         .port_set_link = mv88e6xxx_port_set_link,
5507         .port_sync_link = mv88e6xxx_port_sync_link,
5508         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5509         .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
5510         .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
5511         .port_tag_remap = mv88e6390_port_tag_remap,
5512         .port_set_policy = mv88e6352_port_set_policy,
5513         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5514         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5515         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5516         .port_set_ether_type = mv88e6351_port_set_ether_type,
5517         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5518         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5519         .port_pause_limit = mv88e6390_port_pause_limit,
5520         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5521         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5522         .port_get_cmode = mv88e6352_port_get_cmode,
5523         .port_set_cmode = mv88e6390x_port_set_cmode,
5524         .port_setup_message_port = mv88e6xxx_setup_message_port,
5525         .stats_snapshot = mv88e6390_g1_stats_snapshot,
5526         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5527         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5528         .stats_get_strings = mv88e6320_stats_get_strings,
5529         .stats_get_stats = mv88e6390_stats_get_stats,
5530         .set_cpu_port = mv88e6390_g1_set_cpu_port,
5531         .set_egress_port = mv88e6390_g1_set_egress_port,
5532         .watchdog_ops = &mv88e6390_watchdog_ops,
5533         .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5534         .pot_clear = mv88e6xxx_g2_pot_clear,
5535         .reset = mv88e6352_g1_reset,
5536         .rmu_disable = mv88e6390_g1_rmu_disable,
5537         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5538         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5539         .vtu_getnext = mv88e6390_g1_vtu_getnext,
5540         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5541         .stu_getnext = mv88e6390_g1_stu_getnext,
5542         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5543         .serdes_power = mv88e6390_serdes_power,
5544         .serdes_get_lane = mv88e6390x_serdes_get_lane,
5545         .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
5546         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
5547         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
5548         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
5549         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5550         .serdes_irq_enable = mv88e6390_serdes_irq_enable,
5551         .serdes_irq_status = mv88e6390_serdes_irq_status,
5552         .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5553         .serdes_get_strings = mv88e6390_serdes_get_strings,
5554         .serdes_get_stats = mv88e6390_serdes_get_stats,
5555         .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5556         .serdes_get_regs = mv88e6390_serdes_get_regs,
5557         .gpio_ops = &mv88e6352_gpio_ops,
5558         .avb_ops = &mv88e6390_avb_ops,
5559         .ptp_ops = &mv88e6390_ptp_ops,
5560         .phylink_get_caps = mv88e6390x_phylink_get_caps,
5561 };
5562
5563 static const struct mv88e6xxx_ops mv88e6393x_ops = {
5564         /* MV88E6XXX_FAMILY_6393 */
5565         .setup_errata = mv88e6393x_serdes_setup_errata,
5566         .irl_init_all = mv88e6390_g2_irl_init_all,
5567         .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5568         .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5569         .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5570         .phy_read = mv88e6xxx_g2_smi_phy_read_c22,
5571         .phy_write = mv88e6xxx_g2_smi_phy_write_c22,
5572         .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45,
5573         .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45,
5574         .port_set_link = mv88e6xxx_port_set_link,
5575         .port_sync_link = mv88e6xxx_port_sync_link,
5576         .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5577         .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
5578         .port_max_speed_mode = mv88e6393x_port_max_speed_mode,
5579         .port_tag_remap = mv88e6390_port_tag_remap,
5580         .port_set_policy = mv88e6393x_port_set_policy,
5581         .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5582         .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5583         .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5584         .port_set_ether_type = mv88e6393x_port_set_ether_type,
5585         .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5586         .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5587         .port_pause_limit = mv88e6390_port_pause_limit,
5588         .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5589         .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5590         .port_get_cmode = mv88e6352_port_get_cmode,
5591         .port_set_cmode = mv88e6393x_port_set_cmode,
5592         .port_setup_message_port = mv88e6xxx_setup_message_port,
5593         .port_set_upstream_port = mv88e6393x_port_set_upstream_port,
5594         .stats_snapshot = mv88e6390_g1_stats_snapshot,
5595         .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5596         .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5597         .stats_get_strings = mv88e6320_stats_get_strings,
5598         .stats_get_stats = mv88e6390_stats_get_stats,
5599         /* .set_cpu_port is missing because this family does not support a global
5600          * CPU port, only per port CPU port which is set via
5601          * .port_set_upstream_port method.
5602          */
5603         .set_egress_port = mv88e6393x_set_egress_port,
5604         .watchdog_ops = &mv88e6393x_watchdog_ops,
5605         .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
5606         .pot_clear = mv88e6xxx_g2_pot_clear,
5607         .reset = mv88e6352_g1_reset,
5608         .rmu_disable = mv88e6390_g1_rmu_disable,
5609         .atu_get_hash = mv88e6165_g1_atu_get_hash,
5610         .atu_set_hash = mv88e6165_g1_atu_set_hash,
5611         .vtu_getnext = mv88e6390_g1_vtu_getnext,
5612         .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5613         .stu_getnext = mv88e6390_g1_stu_getnext,
5614         .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5615         .serdes_power = mv88e6393x_serdes_power,
5616         .serdes_get_lane = mv88e6393x_serdes_get_lane,
5617         .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state,
5618         .serdes_pcs_config = mv88e6390_serdes_pcs_config,
5619         .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
5620         .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
5621         .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5622         .serdes_irq_enable = mv88e6393x_serdes_irq_enable,
5623         .serdes_irq_status = mv88e6393x_serdes_irq_status,
5624         /* TODO: serdes stats */
5625         .gpio_ops = &mv88e6352_gpio_ops,
5626         .avb_ops = &mv88e6390_avb_ops,
5627         .ptp_ops = &mv88e6352_ptp_ops,
5628         .phylink_get_caps = mv88e6393x_phylink_get_caps,
5629 };
5630
5631 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
5632         [MV88E6085] = {
5633                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
5634                 .family = MV88E6XXX_FAMILY_6097,
5635                 .name = "Marvell 88E6085",
5636                 .num_databases = 4096,
5637                 .num_macs = 8192,
5638                 .num_ports = 10,
5639                 .num_internal_phys = 5,
5640                 .max_vid = 4095,
5641                 .max_sid = 63,
5642                 .port_base_addr = 0x10,
5643                 .phy_base_addr = 0x0,
5644                 .global1_addr = 0x1b,
5645                 .global2_addr = 0x1c,
5646                 .age_time_coeff = 15000,
5647                 .g1_irqs = 8,
5648                 .g2_irqs = 10,
5649                 .atu_move_port_mask = 0xf,
5650                 .pvt = true,
5651                 .multi_chip = true,
5652                 .ops = &mv88e6085_ops,
5653         },
5654
5655         [MV88E6095] = {
5656                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
5657                 .family = MV88E6XXX_FAMILY_6095,
5658                 .name = "Marvell 88E6095/88E6095F",
5659                 .num_databases = 256,
5660                 .num_macs = 8192,
5661                 .num_ports = 11,
5662                 .num_internal_phys = 0,
5663                 .max_vid = 4095,
5664                 .port_base_addr = 0x10,
5665                 .phy_base_addr = 0x0,
5666                 .global1_addr = 0x1b,
5667                 .global2_addr = 0x1c,
5668                 .age_time_coeff = 15000,
5669                 .g1_irqs = 8,
5670                 .atu_move_port_mask = 0xf,
5671                 .multi_chip = true,
5672                 .ops = &mv88e6095_ops,
5673         },
5674
5675         [MV88E6097] = {
5676                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
5677                 .family = MV88E6XXX_FAMILY_6097,
5678                 .name = "Marvell 88E6097/88E6097F",
5679                 .num_databases = 4096,
5680                 .num_macs = 8192,
5681                 .num_ports = 11,
5682                 .num_internal_phys = 8,
5683                 .max_vid = 4095,
5684                 .max_sid = 63,
5685                 .port_base_addr = 0x10,
5686                 .phy_base_addr = 0x0,
5687                 .global1_addr = 0x1b,
5688                 .global2_addr = 0x1c,
5689                 .age_time_coeff = 15000,
5690                 .g1_irqs = 8,
5691                 .g2_irqs = 10,
5692                 .atu_move_port_mask = 0xf,
5693                 .pvt = true,
5694                 .multi_chip = true,
5695                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5696                 .ops = &mv88e6097_ops,
5697         },
5698
5699         [MV88E6123] = {
5700                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
5701                 .family = MV88E6XXX_FAMILY_6165,
5702                 .name = "Marvell 88E6123",
5703                 .num_databases = 4096,
5704                 .num_macs = 1024,
5705                 .num_ports = 3,
5706                 .num_internal_phys = 5,
5707                 .max_vid = 4095,
5708                 .max_sid = 63,
5709                 .port_base_addr = 0x10,
5710                 .phy_base_addr = 0x0,
5711                 .global1_addr = 0x1b,
5712                 .global2_addr = 0x1c,
5713                 .age_time_coeff = 15000,
5714                 .g1_irqs = 9,
5715                 .g2_irqs = 10,
5716                 .atu_move_port_mask = 0xf,
5717                 .pvt = true,
5718                 .multi_chip = true,
5719                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5720                 .ops = &mv88e6123_ops,
5721         },
5722
5723         [MV88E6131] = {
5724                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
5725                 .family = MV88E6XXX_FAMILY_6185,
5726                 .name = "Marvell 88E6131",
5727                 .num_databases = 256,
5728                 .num_macs = 8192,
5729                 .num_ports = 8,
5730                 .num_internal_phys = 0,
5731                 .max_vid = 4095,
5732                 .port_base_addr = 0x10,
5733                 .phy_base_addr = 0x0,
5734                 .global1_addr = 0x1b,
5735                 .global2_addr = 0x1c,
5736                 .age_time_coeff = 15000,
5737                 .g1_irqs = 9,
5738                 .atu_move_port_mask = 0xf,
5739                 .multi_chip = true,
5740                 .ops = &mv88e6131_ops,
5741         },
5742
5743         [MV88E6141] = {
5744                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
5745                 .family = MV88E6XXX_FAMILY_6341,
5746                 .name = "Marvell 88E6141",
5747                 .num_databases = 4096,
5748                 .num_macs = 2048,
5749                 .num_ports = 6,
5750                 .num_internal_phys = 5,
5751                 .num_gpio = 11,
5752                 .max_vid = 4095,
5753                 .max_sid = 63,
5754                 .port_base_addr = 0x10,
5755                 .phy_base_addr = 0x10,
5756                 .global1_addr = 0x1b,
5757                 .global2_addr = 0x1c,
5758                 .age_time_coeff = 3750,
5759                 .atu_move_port_mask = 0x1f,
5760                 .g1_irqs = 9,
5761                 .g2_irqs = 10,
5762                 .pvt = true,
5763                 .multi_chip = true,
5764                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5765                 .ops = &mv88e6141_ops,
5766         },
5767
5768         [MV88E6161] = {
5769                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
5770                 .family = MV88E6XXX_FAMILY_6165,
5771                 .name = "Marvell 88E6161",
5772                 .num_databases = 4096,
5773                 .num_macs = 1024,
5774                 .num_ports = 6,
5775                 .num_internal_phys = 5,
5776                 .max_vid = 4095,
5777                 .max_sid = 63,
5778                 .port_base_addr = 0x10,
5779                 .phy_base_addr = 0x0,
5780                 .global1_addr = 0x1b,
5781                 .global2_addr = 0x1c,
5782                 .age_time_coeff = 15000,
5783                 .g1_irqs = 9,
5784                 .g2_irqs = 10,
5785                 .atu_move_port_mask = 0xf,
5786                 .pvt = true,
5787                 .multi_chip = true,
5788                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5789                 .ptp_support = true,
5790                 .ops = &mv88e6161_ops,
5791         },
5792
5793         [MV88E6165] = {
5794                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
5795                 .family = MV88E6XXX_FAMILY_6165,
5796                 .name = "Marvell 88E6165",
5797                 .num_databases = 4096,
5798                 .num_macs = 8192,
5799                 .num_ports = 6,
5800                 .num_internal_phys = 0,
5801                 .max_vid = 4095,
5802                 .max_sid = 63,
5803                 .port_base_addr = 0x10,
5804                 .phy_base_addr = 0x0,
5805                 .global1_addr = 0x1b,
5806                 .global2_addr = 0x1c,
5807                 .age_time_coeff = 15000,
5808                 .g1_irqs = 9,
5809                 .g2_irqs = 10,
5810                 .atu_move_port_mask = 0xf,
5811                 .pvt = true,
5812                 .multi_chip = true,
5813                 .ptp_support = true,
5814                 .ops = &mv88e6165_ops,
5815         },
5816
5817         [MV88E6171] = {
5818                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
5819                 .family = MV88E6XXX_FAMILY_6351,
5820                 .name = "Marvell 88E6171",
5821                 .num_databases = 4096,
5822                 .num_macs = 8192,
5823                 .num_ports = 7,
5824                 .num_internal_phys = 5,
5825                 .max_vid = 4095,
5826                 .max_sid = 63,
5827                 .port_base_addr = 0x10,
5828                 .phy_base_addr = 0x0,
5829                 .global1_addr = 0x1b,
5830                 .global2_addr = 0x1c,
5831                 .age_time_coeff = 15000,
5832                 .g1_irqs = 9,
5833                 .g2_irqs = 10,
5834                 .atu_move_port_mask = 0xf,
5835                 .pvt = true,
5836                 .multi_chip = true,
5837                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5838                 .ops = &mv88e6171_ops,
5839         },
5840
5841         [MV88E6172] = {
5842                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
5843                 .family = MV88E6XXX_FAMILY_6352,
5844                 .name = "Marvell 88E6172",
5845                 .num_databases = 4096,
5846                 .num_macs = 8192,
5847                 .num_ports = 7,
5848                 .num_internal_phys = 5,
5849                 .num_gpio = 15,
5850                 .max_vid = 4095,
5851                 .max_sid = 63,
5852                 .port_base_addr = 0x10,
5853                 .phy_base_addr = 0x0,
5854                 .global1_addr = 0x1b,
5855                 .global2_addr = 0x1c,
5856                 .age_time_coeff = 15000,
5857                 .g1_irqs = 9,
5858                 .g2_irqs = 10,
5859                 .atu_move_port_mask = 0xf,
5860                 .pvt = true,
5861                 .multi_chip = true,
5862                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5863                 .ops = &mv88e6172_ops,
5864         },
5865
5866         [MV88E6175] = {
5867                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
5868                 .family = MV88E6XXX_FAMILY_6351,
5869                 .name = "Marvell 88E6175",
5870                 .num_databases = 4096,
5871                 .num_macs = 8192,
5872                 .num_ports = 7,
5873                 .num_internal_phys = 5,
5874                 .max_vid = 4095,
5875                 .max_sid = 63,
5876                 .port_base_addr = 0x10,
5877                 .phy_base_addr = 0x0,
5878                 .global1_addr = 0x1b,
5879                 .global2_addr = 0x1c,
5880                 .age_time_coeff = 15000,
5881                 .g1_irqs = 9,
5882                 .g2_irqs = 10,
5883                 .atu_move_port_mask = 0xf,
5884                 .pvt = true,
5885                 .multi_chip = true,
5886                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5887                 .ops = &mv88e6175_ops,
5888         },
5889
5890         [MV88E6176] = {
5891                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
5892                 .family = MV88E6XXX_FAMILY_6352,
5893                 .name = "Marvell 88E6176",
5894                 .num_databases = 4096,
5895                 .num_macs = 8192,
5896                 .num_ports = 7,
5897                 .num_internal_phys = 5,
5898                 .num_gpio = 15,
5899                 .max_vid = 4095,
5900                 .max_sid = 63,
5901                 .port_base_addr = 0x10,
5902                 .phy_base_addr = 0x0,
5903                 .global1_addr = 0x1b,
5904                 .global2_addr = 0x1c,
5905                 .age_time_coeff = 15000,
5906                 .g1_irqs = 9,
5907                 .g2_irqs = 10,
5908                 .atu_move_port_mask = 0xf,
5909                 .pvt = true,
5910                 .multi_chip = true,
5911                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5912                 .ops = &mv88e6176_ops,
5913         },
5914
5915         [MV88E6185] = {
5916                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
5917                 .family = MV88E6XXX_FAMILY_6185,
5918                 .name = "Marvell 88E6185",
5919                 .num_databases = 256,
5920                 .num_macs = 8192,
5921                 .num_ports = 10,
5922                 .num_internal_phys = 0,
5923                 .max_vid = 4095,
5924                 .port_base_addr = 0x10,
5925                 .phy_base_addr = 0x0,
5926                 .global1_addr = 0x1b,
5927                 .global2_addr = 0x1c,
5928                 .age_time_coeff = 15000,
5929                 .g1_irqs = 8,
5930                 .atu_move_port_mask = 0xf,
5931                 .multi_chip = true,
5932                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5933                 .ops = &mv88e6185_ops,
5934         },
5935
5936         [MV88E6190] = {
5937                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
5938                 .family = MV88E6XXX_FAMILY_6390,
5939                 .name = "Marvell 88E6190",
5940                 .num_databases = 4096,
5941                 .num_macs = 16384,
5942                 .num_ports = 11,        /* 10 + Z80 */
5943                 .num_internal_phys = 9,
5944                 .num_gpio = 16,
5945                 .max_vid = 8191,
5946                 .max_sid = 63,
5947                 .port_base_addr = 0x0,
5948                 .phy_base_addr = 0x0,
5949                 .global1_addr = 0x1b,
5950                 .global2_addr = 0x1c,
5951                 .age_time_coeff = 3750,
5952                 .g1_irqs = 9,
5953                 .g2_irqs = 14,
5954                 .pvt = true,
5955                 .multi_chip = true,
5956                 .atu_move_port_mask = 0x1f,
5957                 .ops = &mv88e6190_ops,
5958         },
5959
5960         [MV88E6190X] = {
5961                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
5962                 .family = MV88E6XXX_FAMILY_6390,
5963                 .name = "Marvell 88E6190X",
5964                 .num_databases = 4096,
5965                 .num_macs = 16384,
5966                 .num_ports = 11,        /* 10 + Z80 */
5967                 .num_internal_phys = 9,
5968                 .num_gpio = 16,
5969                 .max_vid = 8191,
5970                 .max_sid = 63,
5971                 .port_base_addr = 0x0,
5972                 .phy_base_addr = 0x0,
5973                 .global1_addr = 0x1b,
5974                 .global2_addr = 0x1c,
5975                 .age_time_coeff = 3750,
5976                 .g1_irqs = 9,
5977                 .g2_irqs = 14,
5978                 .atu_move_port_mask = 0x1f,
5979                 .pvt = true,
5980                 .multi_chip = true,
5981                 .ops = &mv88e6190x_ops,
5982         },
5983
5984         [MV88E6191] = {
5985                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
5986                 .family = MV88E6XXX_FAMILY_6390,
5987                 .name = "Marvell 88E6191",
5988                 .num_databases = 4096,
5989                 .num_macs = 16384,
5990                 .num_ports = 11,        /* 10 + Z80 */
5991                 .num_internal_phys = 9,
5992                 .max_vid = 8191,
5993                 .max_sid = 63,
5994                 .port_base_addr = 0x0,
5995                 .phy_base_addr = 0x0,
5996                 .global1_addr = 0x1b,
5997                 .global2_addr = 0x1c,
5998                 .age_time_coeff = 3750,
5999                 .g1_irqs = 9,
6000                 .g2_irqs = 14,
6001                 .atu_move_port_mask = 0x1f,
6002                 .pvt = true,
6003                 .multi_chip = true,
6004                 .ptp_support = true,
6005                 .ops = &mv88e6191_ops,
6006         },
6007
6008         [MV88E6191X] = {
6009                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,
6010                 .family = MV88E6XXX_FAMILY_6393,
6011                 .name = "Marvell 88E6191X",
6012                 .num_databases = 4096,
6013                 .num_ports = 11,        /* 10 + Z80 */
6014                 .num_internal_phys = 9,
6015                 .max_vid = 8191,
6016                 .max_sid = 63,
6017                 .port_base_addr = 0x0,
6018                 .phy_base_addr = 0x0,
6019                 .global1_addr = 0x1b,
6020                 .global2_addr = 0x1c,
6021                 .age_time_coeff = 3750,
6022                 .g1_irqs = 10,
6023                 .g2_irqs = 14,
6024                 .atu_move_port_mask = 0x1f,
6025                 .pvt = true,
6026                 .multi_chip = true,
6027                 .ptp_support = true,
6028                 .ops = &mv88e6393x_ops,
6029         },
6030
6031         [MV88E6193X] = {
6032                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,
6033                 .family = MV88E6XXX_FAMILY_6393,
6034                 .name = "Marvell 88E6193X",
6035                 .num_databases = 4096,
6036                 .num_ports = 11,        /* 10 + Z80 */
6037                 .num_internal_phys = 9,
6038                 .max_vid = 8191,
6039                 .max_sid = 63,
6040                 .port_base_addr = 0x0,
6041                 .phy_base_addr = 0x0,
6042                 .global1_addr = 0x1b,
6043                 .global2_addr = 0x1c,
6044                 .age_time_coeff = 3750,
6045                 .g1_irqs = 10,
6046                 .g2_irqs = 14,
6047                 .atu_move_port_mask = 0x1f,
6048                 .pvt = true,
6049                 .multi_chip = true,
6050                 .ptp_support = true,
6051                 .ops = &mv88e6393x_ops,
6052         },
6053
6054         [MV88E6220] = {
6055                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
6056                 .family = MV88E6XXX_FAMILY_6250,
6057                 .name = "Marvell 88E6220",
6058                 .num_databases = 64,
6059
6060                 /* Ports 2-4 are not routed to pins
6061                  * => usable ports 0, 1, 5, 6
6062                  */
6063                 .num_ports = 7,
6064                 .num_internal_phys = 2,
6065                 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
6066                 .max_vid = 4095,
6067                 .port_base_addr = 0x08,
6068                 .phy_base_addr = 0x00,
6069                 .global1_addr = 0x0f,
6070                 .global2_addr = 0x07,
6071                 .age_time_coeff = 15000,
6072                 .g1_irqs = 9,
6073                 .g2_irqs = 10,
6074                 .atu_move_port_mask = 0xf,
6075                 .dual_chip = true,
6076                 .ptp_support = true,
6077                 .ops = &mv88e6250_ops,
6078         },
6079
6080         [MV88E6240] = {
6081                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
6082                 .family = MV88E6XXX_FAMILY_6352,
6083                 .name = "Marvell 88E6240",
6084                 .num_databases = 4096,
6085                 .num_macs = 8192,
6086                 .num_ports = 7,
6087                 .num_internal_phys = 5,
6088                 .num_gpio = 15,
6089                 .max_vid = 4095,
6090                 .max_sid = 63,
6091                 .port_base_addr = 0x10,
6092                 .phy_base_addr = 0x0,
6093                 .global1_addr = 0x1b,
6094                 .global2_addr = 0x1c,
6095                 .age_time_coeff = 15000,
6096                 .g1_irqs = 9,
6097                 .g2_irqs = 10,
6098                 .atu_move_port_mask = 0xf,
6099                 .pvt = true,
6100                 .multi_chip = true,
6101                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6102                 .ptp_support = true,
6103                 .ops = &mv88e6240_ops,
6104         },
6105
6106         [MV88E6250] = {
6107                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
6108                 .family = MV88E6XXX_FAMILY_6250,
6109                 .name = "Marvell 88E6250",
6110                 .num_databases = 64,
6111                 .num_ports = 7,
6112                 .num_internal_phys = 5,
6113                 .max_vid = 4095,
6114                 .port_base_addr = 0x08,
6115                 .phy_base_addr = 0x00,
6116                 .global1_addr = 0x0f,
6117                 .global2_addr = 0x07,
6118                 .age_time_coeff = 15000,
6119                 .g1_irqs = 9,
6120                 .g2_irqs = 10,
6121                 .atu_move_port_mask = 0xf,
6122                 .dual_chip = true,
6123                 .ptp_support = true,
6124                 .ops = &mv88e6250_ops,
6125         },
6126
6127         [MV88E6290] = {
6128                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
6129                 .family = MV88E6XXX_FAMILY_6390,
6130                 .name = "Marvell 88E6290",
6131                 .num_databases = 4096,
6132                 .num_ports = 11,        /* 10 + Z80 */
6133                 .num_internal_phys = 9,
6134                 .num_gpio = 16,
6135                 .max_vid = 8191,
6136                 .max_sid = 63,
6137                 .port_base_addr = 0x0,
6138                 .phy_base_addr = 0x0,
6139                 .global1_addr = 0x1b,
6140                 .global2_addr = 0x1c,
6141                 .age_time_coeff = 3750,
6142                 .g1_irqs = 9,
6143                 .g2_irqs = 14,
6144                 .atu_move_port_mask = 0x1f,
6145                 .pvt = true,
6146                 .multi_chip = true,
6147                 .ptp_support = true,
6148                 .ops = &mv88e6290_ops,
6149         },
6150
6151         [MV88E6320] = {
6152                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
6153                 .family = MV88E6XXX_FAMILY_6320,
6154                 .name = "Marvell 88E6320",
6155                 .num_databases = 4096,
6156                 .num_macs = 8192,
6157                 .num_ports = 7,
6158                 .num_internal_phys = 5,
6159                 .num_gpio = 15,
6160                 .max_vid = 4095,
6161                 .port_base_addr = 0x10,
6162                 .phy_base_addr = 0x0,
6163                 .global1_addr = 0x1b,
6164                 .global2_addr = 0x1c,
6165                 .age_time_coeff = 15000,
6166                 .g1_irqs = 8,
6167                 .g2_irqs = 10,
6168                 .atu_move_port_mask = 0xf,
6169                 .pvt = true,
6170                 .multi_chip = true,
6171                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6172                 .ptp_support = true,
6173                 .ops = &mv88e6320_ops,
6174         },
6175
6176         [MV88E6321] = {
6177                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
6178                 .family = MV88E6XXX_FAMILY_6320,
6179                 .name = "Marvell 88E6321",
6180                 .num_databases = 4096,
6181                 .num_macs = 8192,
6182                 .num_ports = 7,
6183                 .num_internal_phys = 5,
6184                 .num_gpio = 15,
6185                 .max_vid = 4095,
6186                 .port_base_addr = 0x10,
6187                 .phy_base_addr = 0x0,
6188                 .global1_addr = 0x1b,
6189                 .global2_addr = 0x1c,
6190                 .age_time_coeff = 15000,
6191                 .g1_irqs = 8,
6192                 .g2_irqs = 10,
6193                 .atu_move_port_mask = 0xf,
6194                 .multi_chip = true,
6195                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6196                 .ptp_support = true,
6197                 .ops = &mv88e6321_ops,
6198         },
6199
6200         [MV88E6341] = {
6201                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
6202                 .family = MV88E6XXX_FAMILY_6341,
6203                 .name = "Marvell 88E6341",
6204                 .num_databases = 4096,
6205                 .num_macs = 2048,
6206                 .num_internal_phys = 5,
6207                 .num_ports = 6,
6208                 .num_gpio = 11,
6209                 .max_vid = 4095,
6210                 .max_sid = 63,
6211                 .port_base_addr = 0x10,
6212                 .phy_base_addr = 0x10,
6213                 .global1_addr = 0x1b,
6214                 .global2_addr = 0x1c,
6215                 .age_time_coeff = 3750,
6216                 .atu_move_port_mask = 0x1f,
6217                 .g1_irqs = 9,
6218                 .g2_irqs = 10,
6219                 .pvt = true,
6220                 .multi_chip = true,
6221                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6222                 .ptp_support = true,
6223                 .ops = &mv88e6341_ops,
6224         },
6225
6226         [MV88E6350] = {
6227                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
6228                 .family = MV88E6XXX_FAMILY_6351,
6229                 .name = "Marvell 88E6350",
6230                 .num_databases = 4096,
6231                 .num_macs = 8192,
6232                 .num_ports = 7,
6233                 .num_internal_phys = 5,
6234                 .max_vid = 4095,
6235                 .max_sid = 63,
6236                 .port_base_addr = 0x10,
6237                 .phy_base_addr = 0x0,
6238                 .global1_addr = 0x1b,
6239                 .global2_addr = 0x1c,
6240                 .age_time_coeff = 15000,
6241                 .g1_irqs = 9,
6242                 .g2_irqs = 10,
6243                 .atu_move_port_mask = 0xf,
6244                 .pvt = true,
6245                 .multi_chip = true,
6246                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6247                 .ops = &mv88e6350_ops,
6248         },
6249
6250         [MV88E6351] = {
6251                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
6252                 .family = MV88E6XXX_FAMILY_6351,
6253                 .name = "Marvell 88E6351",
6254                 .num_databases = 4096,
6255                 .num_macs = 8192,
6256                 .num_ports = 7,
6257                 .num_internal_phys = 5,
6258                 .max_vid = 4095,
6259                 .max_sid = 63,
6260                 .port_base_addr = 0x10,
6261                 .phy_base_addr = 0x0,
6262                 .global1_addr = 0x1b,
6263                 .global2_addr = 0x1c,
6264                 .age_time_coeff = 15000,
6265                 .g1_irqs = 9,
6266                 .g2_irqs = 10,
6267                 .atu_move_port_mask = 0xf,
6268                 .pvt = true,
6269                 .multi_chip = true,
6270                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6271                 .ops = &mv88e6351_ops,
6272         },
6273
6274         [MV88E6352] = {
6275                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
6276                 .family = MV88E6XXX_FAMILY_6352,
6277                 .name = "Marvell 88E6352",
6278                 .num_databases = 4096,
6279                 .num_macs = 8192,
6280                 .num_ports = 7,
6281                 .num_internal_phys = 5,
6282                 .num_gpio = 15,
6283                 .max_vid = 4095,
6284                 .max_sid = 63,
6285                 .port_base_addr = 0x10,
6286                 .phy_base_addr = 0x0,
6287                 .global1_addr = 0x1b,
6288                 .global2_addr = 0x1c,
6289                 .age_time_coeff = 15000,
6290                 .g1_irqs = 9,
6291                 .g2_irqs = 10,
6292                 .atu_move_port_mask = 0xf,
6293                 .pvt = true,
6294                 .multi_chip = true,
6295                 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6296                 .ptp_support = true,
6297                 .ops = &mv88e6352_ops,
6298         },
6299         [MV88E6390] = {
6300                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
6301                 .family = MV88E6XXX_FAMILY_6390,
6302                 .name = "Marvell 88E6390",
6303                 .num_databases = 4096,
6304                 .num_macs = 16384,
6305                 .num_ports = 11,        /* 10 + Z80 */
6306                 .num_internal_phys = 9,
6307                 .num_gpio = 16,
6308                 .max_vid = 8191,
6309                 .max_sid = 63,
6310                 .port_base_addr = 0x0,
6311                 .phy_base_addr = 0x0,
6312                 .global1_addr = 0x1b,
6313                 .global2_addr = 0x1c,
6314                 .age_time_coeff = 3750,
6315                 .g1_irqs = 9,
6316                 .g2_irqs = 14,
6317                 .atu_move_port_mask = 0x1f,
6318                 .pvt = true,
6319                 .multi_chip = true,
6320                 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6321                 .ptp_support = true,
6322                 .ops = &mv88e6390_ops,
6323         },
6324         [MV88E6390X] = {
6325                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
6326                 .family = MV88E6XXX_FAMILY_6390,
6327                 .name = "Marvell 88E6390X",
6328                 .num_databases = 4096,
6329                 .num_macs = 16384,
6330                 .num_ports = 11,        /* 10 + Z80 */
6331                 .num_internal_phys = 9,
6332                 .num_gpio = 16,
6333                 .max_vid = 8191,
6334                 .max_sid = 63,
6335                 .port_base_addr = 0x0,
6336                 .phy_base_addr = 0x0,
6337                 .global1_addr = 0x1b,
6338                 .global2_addr = 0x1c,
6339                 .age_time_coeff = 3750,
6340                 .g1_irqs = 9,
6341                 .g2_irqs = 14,
6342                 .atu_move_port_mask = 0x1f,
6343                 .pvt = true,
6344                 .multi_chip = true,
6345                 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6346                 .ptp_support = true,
6347                 .ops = &mv88e6390x_ops,
6348         },
6349
6350         [MV88E6393X] = {
6351                 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
6352                 .family = MV88E6XXX_FAMILY_6393,
6353                 .name = "Marvell 88E6393X",
6354                 .num_databases = 4096,
6355                 .num_ports = 11,        /* 10 + Z80 */
6356                 .num_internal_phys = 9,
6357                 .max_vid = 8191,
6358                 .max_sid = 63,
6359                 .port_base_addr = 0x0,
6360                 .phy_base_addr = 0x0,
6361                 .global1_addr = 0x1b,
6362                 .global2_addr = 0x1c,
6363                 .age_time_coeff = 3750,
6364                 .g1_irqs = 10,
6365                 .g2_irqs = 14,
6366                 .atu_move_port_mask = 0x1f,
6367                 .pvt = true,
6368                 .multi_chip = true,
6369                 .ptp_support = true,
6370                 .ops = &mv88e6393x_ops,
6371         },
6372 };
6373
6374 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
6375 {
6376         int i;
6377
6378         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
6379                 if (mv88e6xxx_table[i].prod_num == prod_num)
6380                         return &mv88e6xxx_table[i];
6381
6382         return NULL;
6383 }
6384
6385 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
6386 {
6387         const struct mv88e6xxx_info *info;
6388         unsigned int prod_num, rev;
6389         u16 id;
6390         int err;
6391
6392         mv88e6xxx_reg_lock(chip);
6393         err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
6394         mv88e6xxx_reg_unlock(chip);
6395         if (err)
6396                 return err;
6397
6398         prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
6399         rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
6400
6401         info = mv88e6xxx_lookup_info(prod_num);
6402         if (!info)
6403                 return -ENODEV;
6404
6405         /* Update the compatible info with the probed one */
6406         chip->info = info;
6407
6408         dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
6409                  chip->info->prod_num, chip->info->name, rev);
6410
6411         return 0;
6412 }
6413
6414 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip,
6415                                         struct mdio_device *mdiodev)
6416 {
6417         int err;
6418
6419         /* dual_chip takes precedence over single/multi-chip modes */
6420         if (chip->info->dual_chip)
6421                 return -EINVAL;
6422
6423         /* If the mdio addr is 16 indicating the first port address of a switch
6424          * (e.g. mv88e6*41) in single chip addressing mode the device may be
6425          * configured in single chip addressing mode. Setup the smi access as
6426          * single chip addressing mode and attempt to detect the model of the
6427          * switch, if this fails the device is not configured in single chip
6428          * addressing mode.
6429          */
6430         if (mdiodev->addr != 16)
6431                 return -EINVAL;
6432
6433         err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0);
6434         if (err)
6435                 return err;
6436
6437         return mv88e6xxx_detect(chip);
6438 }
6439
6440 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
6441 {
6442         struct mv88e6xxx_chip *chip;
6443
6444         chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
6445         if (!chip)
6446                 return NULL;
6447
6448         chip->dev = dev;
6449
6450         mutex_init(&chip->reg_lock);
6451         INIT_LIST_HEAD(&chip->mdios);
6452         idr_init(&chip->policies);
6453         INIT_LIST_HEAD(&chip->msts);
6454
6455         return chip;
6456 }
6457
6458 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
6459                                                         int port,
6460                                                         enum dsa_tag_protocol m)
6461 {
6462         struct mv88e6xxx_chip *chip = ds->priv;
6463
6464         return chip->tag_protocol;
6465 }
6466
6467 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds,
6468                                          enum dsa_tag_protocol proto)
6469 {
6470         struct mv88e6xxx_chip *chip = ds->priv;
6471         enum dsa_tag_protocol old_protocol;
6472         struct dsa_port *cpu_dp;
6473         int err;
6474
6475         switch (proto) {
6476         case DSA_TAG_PROTO_EDSA:
6477                 switch (chip->info->edsa_support) {
6478                 case MV88E6XXX_EDSA_UNSUPPORTED:
6479                         return -EPROTONOSUPPORT;
6480                 case MV88E6XXX_EDSA_UNDOCUMENTED:
6481                         dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n");
6482                         fallthrough;
6483                 case MV88E6XXX_EDSA_SUPPORTED:
6484                         break;
6485                 }
6486                 break;
6487         case DSA_TAG_PROTO_DSA:
6488                 break;
6489         default:
6490                 return -EPROTONOSUPPORT;
6491         }
6492
6493         old_protocol = chip->tag_protocol;
6494         chip->tag_protocol = proto;
6495
6496         mv88e6xxx_reg_lock(chip);
6497         dsa_switch_for_each_cpu_port(cpu_dp, ds) {
6498                 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6499                 if (err) {
6500                         mv88e6xxx_reg_unlock(chip);
6501                         goto unwind;
6502                 }
6503         }
6504         mv88e6xxx_reg_unlock(chip);
6505
6506         return 0;
6507
6508 unwind:
6509         chip->tag_protocol = old_protocol;
6510
6511         mv88e6xxx_reg_lock(chip);
6512         dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds)
6513                 mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6514         mv88e6xxx_reg_unlock(chip);
6515
6516         return err;
6517 }
6518
6519 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
6520                                   const struct switchdev_obj_port_mdb *mdb,
6521                                   struct dsa_db db)
6522 {
6523         struct mv88e6xxx_chip *chip = ds->priv;
6524         int err;
6525
6526         mv88e6xxx_reg_lock(chip);
6527         err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
6528                                            MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC);
6529         mv88e6xxx_reg_unlock(chip);
6530
6531         return err;
6532 }
6533
6534 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
6535                                   const struct switchdev_obj_port_mdb *mdb,
6536                                   struct dsa_db db)
6537 {
6538         struct mv88e6xxx_chip *chip = ds->priv;
6539         int err;
6540
6541         mv88e6xxx_reg_lock(chip);
6542         err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
6543         mv88e6xxx_reg_unlock(chip);
6544
6545         return err;
6546 }
6547
6548 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
6549                                      struct dsa_mall_mirror_tc_entry *mirror,
6550                                      bool ingress,
6551                                      struct netlink_ext_ack *extack)
6552 {
6553         enum mv88e6xxx_egress_direction direction = ingress ?
6554                                                 MV88E6XXX_EGRESS_DIR_INGRESS :
6555                                                 MV88E6XXX_EGRESS_DIR_EGRESS;
6556         struct mv88e6xxx_chip *chip = ds->priv;
6557         bool other_mirrors = false;
6558         int i;
6559         int err;
6560
6561         mutex_lock(&chip->reg_lock);
6562         if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
6563             mirror->to_local_port) {
6564                 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6565                         other_mirrors |= ingress ?
6566                                          chip->ports[i].mirror_ingress :
6567                                          chip->ports[i].mirror_egress;
6568
6569                 /* Can't change egress port when other mirror is active */
6570                 if (other_mirrors) {
6571                         err = -EBUSY;
6572                         goto out;
6573                 }
6574
6575                 err = mv88e6xxx_set_egress_port(chip, direction,
6576                                                 mirror->to_local_port);
6577                 if (err)
6578                         goto out;
6579         }
6580
6581         err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
6582 out:
6583         mutex_unlock(&chip->reg_lock);
6584
6585         return err;
6586 }
6587
6588 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
6589                                       struct dsa_mall_mirror_tc_entry *mirror)
6590 {
6591         enum mv88e6xxx_egress_direction direction = mirror->ingress ?
6592                                                 MV88E6XXX_EGRESS_DIR_INGRESS :
6593                                                 MV88E6XXX_EGRESS_DIR_EGRESS;
6594         struct mv88e6xxx_chip *chip = ds->priv;
6595         bool other_mirrors = false;
6596         int i;
6597
6598         mutex_lock(&chip->reg_lock);
6599         if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
6600                 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
6601
6602         for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6603                 other_mirrors |= mirror->ingress ?
6604                                  chip->ports[i].mirror_ingress :
6605                                  chip->ports[i].mirror_egress;
6606
6607         /* Reset egress port when no other mirror is active */
6608         if (!other_mirrors) {
6609                 if (mv88e6xxx_set_egress_port(chip, direction,
6610                                               dsa_upstream_port(ds, port)))
6611                         dev_err(ds->dev, "failed to set egress port\n");
6612         }
6613
6614         mutex_unlock(&chip->reg_lock);
6615 }
6616
6617 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port,
6618                                            struct switchdev_brport_flags flags,
6619                                            struct netlink_ext_ack *extack)
6620 {
6621         struct mv88e6xxx_chip *chip = ds->priv;
6622         const struct mv88e6xxx_ops *ops;
6623
6624         if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
6625                            BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB))
6626                 return -EINVAL;
6627
6628         ops = chip->info->ops;
6629
6630         if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)
6631                 return -EINVAL;
6632
6633         if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)
6634                 return -EINVAL;
6635
6636         return 0;
6637 }
6638
6639 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port,
6640                                        struct switchdev_brport_flags flags,
6641                                        struct netlink_ext_ack *extack)
6642 {
6643         struct mv88e6xxx_chip *chip = ds->priv;
6644         int err = 0;
6645
6646         mv88e6xxx_reg_lock(chip);
6647
6648         if (flags.mask & BR_LEARNING) {
6649                 bool learning = !!(flags.val & BR_LEARNING);
6650                 u16 pav = learning ? (1 << port) : 0;
6651
6652                 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav);
6653                 if (err)
6654                         goto out;
6655         }
6656
6657         if (flags.mask & BR_FLOOD) {
6658                 bool unicast = !!(flags.val & BR_FLOOD);
6659
6660                 err = chip->info->ops->port_set_ucast_flood(chip, port,
6661                                                             unicast);
6662                 if (err)
6663                         goto out;
6664         }
6665
6666         if (flags.mask & BR_MCAST_FLOOD) {
6667                 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
6668
6669                 err = chip->info->ops->port_set_mcast_flood(chip, port,
6670                                                             multicast);
6671                 if (err)
6672                         goto out;
6673         }
6674
6675         if (flags.mask & BR_BCAST_FLOOD) {
6676                 bool broadcast = !!(flags.val & BR_BCAST_FLOOD);
6677
6678                 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast);
6679                 if (err)
6680                         goto out;
6681         }
6682
6683         if (flags.mask & BR_PORT_MAB) {
6684                 bool mab = !!(flags.val & BR_PORT_MAB);
6685
6686                 mv88e6xxx_port_set_mab(chip, port, mab);
6687         }
6688
6689         if (flags.mask & BR_PORT_LOCKED) {
6690                 bool locked = !!(flags.val & BR_PORT_LOCKED);
6691
6692                 err = mv88e6xxx_port_set_lock(chip, port, locked);
6693                 if (err)
6694                         goto out;
6695         }
6696 out:
6697         mv88e6xxx_reg_unlock(chip);
6698
6699         return err;
6700 }
6701
6702 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds,
6703                                       struct dsa_lag lag,
6704                                       struct netdev_lag_upper_info *info,
6705                                       struct netlink_ext_ack *extack)
6706 {
6707         struct mv88e6xxx_chip *chip = ds->priv;
6708         struct dsa_port *dp;
6709         int members = 0;
6710
6711         if (!mv88e6xxx_has_lag(chip)) {
6712                 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload");
6713                 return false;
6714         }
6715
6716         if (!lag.id)
6717                 return false;
6718
6719         dsa_lag_foreach_port(dp, ds->dst, &lag)
6720                 /* Includes the port joining the LAG */
6721                 members++;
6722
6723         if (members > 8) {
6724                 NL_SET_ERR_MSG_MOD(extack,
6725                                    "Cannot offload more than 8 LAG ports");
6726                 return false;
6727         }
6728
6729         /* We could potentially relax this to include active
6730          * backup in the future.
6731          */
6732         if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
6733                 NL_SET_ERR_MSG_MOD(extack,
6734                                    "Can only offload LAG using hash TX type");
6735                 return false;
6736         }
6737
6738         /* Ideally we would also validate that the hash type matches
6739          * the hardware. Alas, this is always set to unknown on team
6740          * interfaces.
6741          */
6742         return true;
6743 }
6744
6745 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag)
6746 {
6747         struct mv88e6xxx_chip *chip = ds->priv;
6748         struct dsa_port *dp;
6749         u16 map = 0;
6750         int id;
6751
6752         /* DSA LAG IDs are one-based, hardware is zero-based */
6753         id = lag.id - 1;
6754
6755         /* Build the map of all ports to distribute flows destined for
6756          * this LAG. This can be either a local user port, or a DSA
6757          * port if the LAG port is on a remote chip.
6758          */
6759         dsa_lag_foreach_port(dp, ds->dst, &lag)
6760                 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index));
6761
6762         return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
6763 }
6764
6765 static const u8 mv88e6xxx_lag_mask_table[8][8] = {
6766         /* Row number corresponds to the number of active members in a
6767          * LAG. Each column states which of the eight hash buckets are
6768          * mapped to the column:th port in the LAG.
6769          *
6770          * Example: In a LAG with three active ports, the second port
6771          * ([2][1]) would be selected for traffic mapped to buckets
6772          * 3,4,5 (0x38).
6773          */
6774         { 0xff,    0,    0,    0,    0,    0,    0,    0 },
6775         { 0x0f, 0xf0,    0,    0,    0,    0,    0,    0 },
6776         { 0x07, 0x38, 0xc0,    0,    0,    0,    0,    0 },
6777         { 0x03, 0x0c, 0x30, 0xc0,    0,    0,    0,    0 },
6778         { 0x03, 0x0c, 0x30, 0x40, 0x80,    0,    0,    0 },
6779         { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80,    0,    0 },
6780         { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80,    0 },
6781         { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
6782 };
6783
6784 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port,
6785                                         int num_tx, int nth)
6786 {
6787         u8 active = 0;
6788         int i;
6789
6790         num_tx = num_tx <= 8 ? num_tx : 8;
6791         if (nth < num_tx)
6792                 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth];
6793
6794         for (i = 0; i < 8; i++) {
6795                 if (BIT(i) & active)
6796                         mask[i] |= BIT(port);
6797         }
6798 }
6799
6800 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds)
6801 {
6802         struct mv88e6xxx_chip *chip = ds->priv;
6803         unsigned int id, num_tx;
6804         struct dsa_port *dp;
6805         struct dsa_lag *lag;
6806         int i, err, nth;
6807         u16 mask[8];
6808         u16 ivec;
6809
6810         /* Assume no port is a member of any LAG. */
6811         ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
6812
6813         /* Disable all masks for ports that _are_ members of a LAG. */
6814         dsa_switch_for_each_port(dp, ds) {
6815                 if (!dp->lag)
6816                         continue;
6817
6818                 ivec &= ~BIT(dp->index);
6819         }
6820
6821         for (i = 0; i < 8; i++)
6822                 mask[i] = ivec;
6823
6824         /* Enable the correct subset of masks for all LAG ports that
6825          * are in the Tx set.
6826          */
6827         dsa_lags_foreach_id(id, ds->dst) {
6828                 lag = dsa_lag_by_id(ds->dst, id);
6829                 if (!lag)
6830                         continue;
6831
6832                 num_tx = 0;
6833                 dsa_lag_foreach_port(dp, ds->dst, lag) {
6834                         if (dp->lag_tx_enabled)
6835                                 num_tx++;
6836                 }
6837
6838                 if (!num_tx)
6839                         continue;
6840
6841                 nth = 0;
6842                 dsa_lag_foreach_port(dp, ds->dst, lag) {
6843                         if (!dp->lag_tx_enabled)
6844                                 continue;
6845
6846                         if (dp->ds == ds)
6847                                 mv88e6xxx_lag_set_port_mask(mask, dp->index,
6848                                                             num_tx, nth);
6849
6850                         nth++;
6851                 }
6852         }
6853
6854         for (i = 0; i < 8; i++) {
6855                 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
6856                 if (err)
6857                         return err;
6858         }
6859
6860         return 0;
6861 }
6862
6863 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds,
6864                                         struct dsa_lag lag)
6865 {
6866         int err;
6867
6868         err = mv88e6xxx_lag_sync_masks(ds);
6869
6870         if (!err)
6871                 err = mv88e6xxx_lag_sync_map(ds, lag);
6872
6873         return err;
6874 }
6875
6876 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port)
6877 {
6878         struct mv88e6xxx_chip *chip = ds->priv;
6879         int err;
6880
6881         mv88e6xxx_reg_lock(chip);
6882         err = mv88e6xxx_lag_sync_masks(ds);
6883         mv88e6xxx_reg_unlock(chip);
6884         return err;
6885 }
6886
6887 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port,
6888                                    struct dsa_lag lag,
6889                                    struct netdev_lag_upper_info *info,
6890                                    struct netlink_ext_ack *extack)
6891 {
6892         struct mv88e6xxx_chip *chip = ds->priv;
6893         int err, id;
6894
6895         if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
6896                 return -EOPNOTSUPP;
6897
6898         /* DSA LAG IDs are one-based */
6899         id = lag.id - 1;
6900
6901         mv88e6xxx_reg_lock(chip);
6902
6903         err = mv88e6xxx_port_set_trunk(chip, port, true, id);
6904         if (err)
6905                 goto err_unlock;
6906
6907         err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6908         if (err)
6909                 goto err_clear_trunk;
6910
6911         mv88e6xxx_reg_unlock(chip);
6912         return 0;
6913
6914 err_clear_trunk:
6915         mv88e6xxx_port_set_trunk(chip, port, false, 0);
6916 err_unlock:
6917         mv88e6xxx_reg_unlock(chip);
6918         return err;
6919 }
6920
6921 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port,
6922                                     struct dsa_lag lag)
6923 {
6924         struct mv88e6xxx_chip *chip = ds->priv;
6925         int err_sync, err_trunk;
6926
6927         mv88e6xxx_reg_lock(chip);
6928         err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6929         err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
6930         mv88e6xxx_reg_unlock(chip);
6931         return err_sync ? : err_trunk;
6932 }
6933
6934 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index,
6935                                           int port)
6936 {
6937         struct mv88e6xxx_chip *chip = ds->priv;
6938         int err;
6939
6940         mv88e6xxx_reg_lock(chip);
6941         err = mv88e6xxx_lag_sync_masks(ds);
6942         mv88e6xxx_reg_unlock(chip);
6943         return err;
6944 }
6945
6946 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index,
6947                                         int port, struct dsa_lag lag,
6948                                         struct netdev_lag_upper_info *info,
6949                                         struct netlink_ext_ack *extack)
6950 {
6951         struct mv88e6xxx_chip *chip = ds->priv;
6952         int err;
6953
6954         if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
6955                 return -EOPNOTSUPP;
6956
6957         mv88e6xxx_reg_lock(chip);
6958
6959         err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6960         if (err)
6961                 goto unlock;
6962
6963         err = mv88e6xxx_pvt_map(chip, sw_index, port);
6964
6965 unlock:
6966         mv88e6xxx_reg_unlock(chip);
6967         return err;
6968 }
6969
6970 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index,
6971                                          int port, struct dsa_lag lag)
6972 {
6973         struct mv88e6xxx_chip *chip = ds->priv;
6974         int err_sync, err_pvt;
6975
6976         mv88e6xxx_reg_lock(chip);
6977         err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6978         err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
6979         mv88e6xxx_reg_unlock(chip);
6980         return err_sync ? : err_pvt;
6981 }
6982
6983 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
6984         .get_tag_protocol       = mv88e6xxx_get_tag_protocol,
6985         .change_tag_protocol    = mv88e6xxx_change_tag_protocol,
6986         .setup                  = mv88e6xxx_setup,
6987         .teardown               = mv88e6xxx_teardown,
6988         .port_setup             = mv88e6xxx_port_setup,
6989         .port_teardown          = mv88e6xxx_port_teardown,
6990         .phylink_get_caps       = mv88e6xxx_get_caps,
6991         .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state,
6992         .phylink_mac_config     = mv88e6xxx_mac_config,
6993         .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart,
6994         .phylink_mac_link_down  = mv88e6xxx_mac_link_down,
6995         .phylink_mac_link_up    = mv88e6xxx_mac_link_up,
6996         .get_strings            = mv88e6xxx_get_strings,
6997         .get_ethtool_stats      = mv88e6xxx_get_ethtool_stats,
6998         .get_sset_count         = mv88e6xxx_get_sset_count,
6999         .port_enable            = mv88e6xxx_port_enable,
7000         .port_disable           = mv88e6xxx_port_disable,
7001         .port_max_mtu           = mv88e6xxx_get_max_mtu,
7002         .port_change_mtu        = mv88e6xxx_change_mtu,
7003         .get_mac_eee            = mv88e6xxx_get_mac_eee,
7004         .set_mac_eee            = mv88e6xxx_set_mac_eee,
7005         .get_eeprom_len         = mv88e6xxx_get_eeprom_len,
7006         .get_eeprom             = mv88e6xxx_get_eeprom,
7007         .set_eeprom             = mv88e6xxx_set_eeprom,
7008         .get_regs_len           = mv88e6xxx_get_regs_len,
7009         .get_regs               = mv88e6xxx_get_regs,
7010         .get_rxnfc              = mv88e6xxx_get_rxnfc,
7011         .set_rxnfc              = mv88e6xxx_set_rxnfc,
7012         .set_ageing_time        = mv88e6xxx_set_ageing_time,
7013         .port_bridge_join       = mv88e6xxx_port_bridge_join,
7014         .port_bridge_leave      = mv88e6xxx_port_bridge_leave,
7015         .port_pre_bridge_flags  = mv88e6xxx_port_pre_bridge_flags,
7016         .port_bridge_flags      = mv88e6xxx_port_bridge_flags,
7017         .port_stp_state_set     = mv88e6xxx_port_stp_state_set,
7018         .port_mst_state_set     = mv88e6xxx_port_mst_state_set,
7019         .port_fast_age          = mv88e6xxx_port_fast_age,
7020         .port_vlan_fast_age     = mv88e6xxx_port_vlan_fast_age,
7021         .port_vlan_filtering    = mv88e6xxx_port_vlan_filtering,
7022         .port_vlan_add          = mv88e6xxx_port_vlan_add,
7023         .port_vlan_del          = mv88e6xxx_port_vlan_del,
7024         .vlan_msti_set          = mv88e6xxx_vlan_msti_set,
7025         .port_fdb_add           = mv88e6xxx_port_fdb_add,
7026         .port_fdb_del           = mv88e6xxx_port_fdb_del,
7027         .port_fdb_dump          = mv88e6xxx_port_fdb_dump,
7028         .port_mdb_add           = mv88e6xxx_port_mdb_add,
7029         .port_mdb_del           = mv88e6xxx_port_mdb_del,
7030         .port_mirror_add        = mv88e6xxx_port_mirror_add,
7031         .port_mirror_del        = mv88e6xxx_port_mirror_del,
7032         .crosschip_bridge_join  = mv88e6xxx_crosschip_bridge_join,
7033         .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
7034         .port_hwtstamp_set      = mv88e6xxx_port_hwtstamp_set,
7035         .port_hwtstamp_get      = mv88e6xxx_port_hwtstamp_get,
7036         .port_txtstamp          = mv88e6xxx_port_txtstamp,
7037         .port_rxtstamp          = mv88e6xxx_port_rxtstamp,
7038         .get_ts_info            = mv88e6xxx_get_ts_info,
7039         .devlink_param_get      = mv88e6xxx_devlink_param_get,
7040         .devlink_param_set      = mv88e6xxx_devlink_param_set,
7041         .devlink_info_get       = mv88e6xxx_devlink_info_get,
7042         .port_lag_change        = mv88e6xxx_port_lag_change,
7043         .port_lag_join          = mv88e6xxx_port_lag_join,
7044         .port_lag_leave         = mv88e6xxx_port_lag_leave,
7045         .crosschip_lag_change   = mv88e6xxx_crosschip_lag_change,
7046         .crosschip_lag_join     = mv88e6xxx_crosschip_lag_join,
7047         .crosschip_lag_leave    = mv88e6xxx_crosschip_lag_leave,
7048 };
7049
7050 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
7051 {
7052         struct device *dev = chip->dev;
7053         struct dsa_switch *ds;
7054
7055         ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
7056         if (!ds)
7057                 return -ENOMEM;
7058
7059         ds->dev = dev;
7060         ds->num_ports = mv88e6xxx_num_ports(chip);
7061         ds->priv = chip;
7062         ds->dev = dev;
7063         ds->ops = &mv88e6xxx_switch_ops;
7064         ds->ageing_time_min = chip->info->age_time_coeff;
7065         ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
7066
7067         /* Some chips support up to 32, but that requires enabling the
7068          * 5-bit port mode, which we do not support. 640k^W16 ought to
7069          * be enough for anyone.
7070          */
7071         ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0;
7072
7073         dev_set_drvdata(dev, ds);
7074
7075         return dsa_register_switch(ds);
7076 }
7077
7078 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
7079 {
7080         dsa_unregister_switch(chip->ds);
7081 }
7082
7083 static const void *pdata_device_get_match_data(struct device *dev)
7084 {
7085         const struct of_device_id *matches = dev->driver->of_match_table;
7086         const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
7087
7088         for (; matches->name[0] || matches->type[0] || matches->compatible[0];
7089              matches++) {
7090                 if (!strcmp(pdata->compatible, matches->compatible))
7091                         return matches->data;
7092         }
7093         return NULL;
7094 }
7095
7096 /* There is no suspend to RAM support at DSA level yet, the switch configuration
7097  * would be lost after a power cycle so prevent it to be suspended.
7098  */
7099 static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
7100 {
7101         return -EOPNOTSUPP;
7102 }
7103
7104 static int __maybe_unused mv88e6xxx_resume(struct device *dev)
7105 {
7106         return 0;
7107 }
7108
7109 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
7110
7111 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
7112 {
7113         struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
7114         const struct mv88e6xxx_info *compat_info = NULL;
7115         struct device *dev = &mdiodev->dev;
7116         struct device_node *np = dev->of_node;
7117         struct mv88e6xxx_chip *chip;
7118         int port;
7119         int err;
7120
7121         if (!np && !pdata)
7122                 return -EINVAL;
7123
7124         if (np)
7125                 compat_info = of_device_get_match_data(dev);
7126
7127         if (pdata) {
7128                 compat_info = pdata_device_get_match_data(dev);
7129
7130                 if (!pdata->netdev)
7131                         return -EINVAL;
7132
7133                 for (port = 0; port < DSA_MAX_PORTS; port++) {
7134                         if (!(pdata->enabled_ports & (1 << port)))
7135                                 continue;
7136                         if (strcmp(pdata->cd.port_names[port], "cpu"))
7137                                 continue;
7138                         pdata->cd.netdev[port] = &pdata->netdev->dev;
7139                         break;
7140                 }
7141         }
7142
7143         if (!compat_info)
7144                 return -EINVAL;
7145
7146         chip = mv88e6xxx_alloc_chip(dev);
7147         if (!chip) {
7148                 err = -ENOMEM;
7149                 goto out;
7150         }
7151
7152         chip->info = compat_info;
7153
7154         chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
7155         if (IS_ERR(chip->reset)) {
7156                 err = PTR_ERR(chip->reset);
7157                 goto out;
7158         }
7159         if (chip->reset)
7160                 usleep_range(1000, 2000);
7161
7162         /* Detect if the device is configured in single chip addressing mode,
7163          * otherwise continue with address specific smi init/detection.
7164          */
7165         err = mv88e6xxx_single_chip_detect(chip, mdiodev);
7166         if (err) {
7167                 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
7168                 if (err)
7169                         goto out;
7170
7171                 err = mv88e6xxx_detect(chip);
7172                 if (err)
7173                         goto out;
7174         }
7175
7176         if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED)
7177                 chip->tag_protocol = DSA_TAG_PROTO_EDSA;
7178         else
7179                 chip->tag_protocol = DSA_TAG_PROTO_DSA;
7180
7181         mv88e6xxx_phy_init(chip);
7182
7183         if (chip->info->ops->get_eeprom) {
7184                 if (np)
7185                         of_property_read_u32(np, "eeprom-length",
7186                                              &chip->eeprom_len);
7187                 else
7188                         chip->eeprom_len = pdata->eeprom_len;
7189         }
7190
7191         mv88e6xxx_reg_lock(chip);
7192         err = mv88e6xxx_switch_reset(chip);
7193         mv88e6xxx_reg_unlock(chip);
7194         if (err)
7195                 goto out;
7196
7197         if (np) {
7198                 chip->irq = of_irq_get(np, 0);
7199                 if (chip->irq == -EPROBE_DEFER) {
7200                         err = chip->irq;
7201                         goto out;
7202                 }
7203         }
7204
7205         if (pdata)
7206                 chip->irq = pdata->irq;
7207
7208         /* Has to be performed before the MDIO bus is created, because
7209          * the PHYs will link their interrupts to these interrupt
7210          * controllers
7211          */
7212         mv88e6xxx_reg_lock(chip);
7213         if (chip->irq > 0)
7214                 err = mv88e6xxx_g1_irq_setup(chip);
7215         else
7216                 err = mv88e6xxx_irq_poll_setup(chip);
7217         mv88e6xxx_reg_unlock(chip);
7218
7219         if (err)
7220                 goto out;
7221
7222         if (chip->info->g2_irqs > 0) {
7223                 err = mv88e6xxx_g2_irq_setup(chip);
7224                 if (err)
7225                         goto out_g1_irq;
7226         }
7227
7228         err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
7229         if (err)
7230                 goto out_g2_irq;
7231
7232         err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
7233         if (err)
7234                 goto out_g1_atu_prob_irq;
7235
7236         err = mv88e6xxx_mdios_register(chip, np);
7237         if (err)
7238                 goto out_g1_vtu_prob_irq;
7239
7240         err = mv88e6xxx_register_switch(chip);
7241         if (err)
7242                 goto out_mdio;
7243
7244         return 0;
7245
7246 out_mdio:
7247         mv88e6xxx_mdios_unregister(chip);
7248 out_g1_vtu_prob_irq:
7249         mv88e6xxx_g1_vtu_prob_irq_free(chip);
7250 out_g1_atu_prob_irq:
7251         mv88e6xxx_g1_atu_prob_irq_free(chip);
7252 out_g2_irq:
7253         if (chip->info->g2_irqs > 0)
7254                 mv88e6xxx_g2_irq_free(chip);
7255 out_g1_irq:
7256         if (chip->irq > 0)
7257                 mv88e6xxx_g1_irq_free(chip);
7258         else
7259                 mv88e6xxx_irq_poll_free(chip);
7260 out:
7261         if (pdata)
7262                 dev_put(pdata->netdev);
7263
7264         return err;
7265 }
7266
7267 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
7268 {
7269         struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7270         struct mv88e6xxx_chip *chip;
7271
7272         if (!ds)
7273                 return;
7274
7275         chip = ds->priv;
7276
7277         if (chip->info->ptp_support) {
7278                 mv88e6xxx_hwtstamp_free(chip);
7279                 mv88e6xxx_ptp_free(chip);
7280         }
7281
7282         mv88e6xxx_phy_destroy(chip);
7283         mv88e6xxx_unregister_switch(chip);
7284         mv88e6xxx_mdios_unregister(chip);
7285
7286         mv88e6xxx_g1_vtu_prob_irq_free(chip);
7287         mv88e6xxx_g1_atu_prob_irq_free(chip);
7288
7289         if (chip->info->g2_irqs > 0)
7290                 mv88e6xxx_g2_irq_free(chip);
7291
7292         if (chip->irq > 0)
7293                 mv88e6xxx_g1_irq_free(chip);
7294         else
7295                 mv88e6xxx_irq_poll_free(chip);
7296 }
7297
7298 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev)
7299 {
7300         struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7301
7302         if (!ds)
7303                 return;
7304
7305         dsa_switch_shutdown(ds);
7306
7307         dev_set_drvdata(&mdiodev->dev, NULL);
7308 }
7309
7310 static const struct of_device_id mv88e6xxx_of_match[] = {
7311         {
7312                 .compatible = "marvell,mv88e6085",
7313                 .data = &mv88e6xxx_table[MV88E6085],
7314         },
7315         {
7316                 .compatible = "marvell,mv88e6190",
7317                 .data = &mv88e6xxx_table[MV88E6190],
7318         },
7319         {
7320                 .compatible = "marvell,mv88e6250",
7321                 .data = &mv88e6xxx_table[MV88E6250],
7322         },
7323         { /* sentinel */ },
7324 };
7325
7326 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
7327
7328 static struct mdio_driver mv88e6xxx_driver = {
7329         .probe  = mv88e6xxx_probe,
7330         .remove = mv88e6xxx_remove,
7331         .shutdown = mv88e6xxx_shutdown,
7332         .mdiodrv.driver = {
7333                 .name = "mv88e6085",
7334                 .of_match_table = mv88e6xxx_of_match,
7335                 .pm = &mv88e6xxx_pm_ops,
7336         },
7337 };
7338
7339 mdio_module_driver(mv88e6xxx_driver);
7340
7341 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
7342 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
7343 MODULE_LICENSE("GPL");