drivers/net/dsa/qca8k.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
   4  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   5  * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved.
   6  * Copyright (c) 2016 John Crispin <john@phrozen.org>
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/phy.h>
  11 #include <linux/netdevice.h>
  12 #include <linux/bitfield.h>
  13 #include <linux/regmap.h>
  14 #include <net/dsa.h>
  15 #include <linux/of_net.h>
  16 #include <linux/of_mdio.h>
  17 #include <linux/of_platform.h>
  18 #include <linux/if_bridge.h>
  19 #include <linux/mdio.h>
  20 #include <linux/phylink.h>
  21 #include <linux/gpio/consumer.h>
  22 #include <linux/etherdevice.h>
  23
  24 #include "qca8k.h"
  25
  26 #define MIB_DESC(_s, _o, _n)    \
  27         {                       \
  28                 .size = (_s),   \
  29                 .offset = (_o), \
  30                 .name = (_n),   \
  31         }
  32
  33 static const struct qca8k_mib_desc ar8327_mib[] = {
  34         MIB_DESC(1, 0x00, "RxBroad"),
  35         MIB_DESC(1, 0x04, "RxPause"),
  36         MIB_DESC(1, 0x08, "RxMulti"),
  37         MIB_DESC(1, 0x0c, "RxFcsErr"),
  38         MIB_DESC(1, 0x10, "RxAlignErr"),
  39         MIB_DESC(1, 0x14, "RxRunt"),
  40         MIB_DESC(1, 0x18, "RxFragment"),
  41         MIB_DESC(1, 0x1c, "Rx64Byte"),
  42         MIB_DESC(1, 0x20, "Rx128Byte"),
  43         MIB_DESC(1, 0x24, "Rx256Byte"),
  44         MIB_DESC(1, 0x28, "Rx512Byte"),
  45         MIB_DESC(1, 0x2c, "Rx1024Byte"),
  46         MIB_DESC(1, 0x30, "Rx1518Byte"),
  47         MIB_DESC(1, 0x34, "RxMaxByte"),
  48         MIB_DESC(1, 0x38, "RxTooLong"),
  49         MIB_DESC(2, 0x3c, "RxGoodByte"),
  50         MIB_DESC(2, 0x44, "RxBadByte"),
  51         MIB_DESC(1, 0x4c, "RxOverFlow"),
  52         MIB_DESC(1, 0x50, "Filtered"),
  53         MIB_DESC(1, 0x54, "TxBroad"),
  54         MIB_DESC(1, 0x58, "TxPause"),
  55         MIB_DESC(1, 0x5c, "TxMulti"),
  56         MIB_DESC(1, 0x60, "TxUnderRun"),
  57         MIB_DESC(1, 0x64, "Tx64Byte"),
  58         MIB_DESC(1, 0x68, "Tx128Byte"),
  59         MIB_DESC(1, 0x6c, "Tx256Byte"),
  60         MIB_DESC(1, 0x70, "Tx512Byte"),
  61         MIB_DESC(1, 0x74, "Tx1024Byte"),
  62         MIB_DESC(1, 0x78, "Tx1518Byte"),
  63         MIB_DESC(1, 0x7c, "TxMaxByte"),
  64         MIB_DESC(1, 0x80, "TxOverSize"),
  65         MIB_DESC(2, 0x84, "TxByte"),
  66         MIB_DESC(1, 0x8c, "TxCollision"),
  67         MIB_DESC(1, 0x90, "TxAbortCol"),
  68         MIB_DESC(1, 0x94, "TxMultiCol"),
  69         MIB_DESC(1, 0x98, "TxSingleCol"),
  70         MIB_DESC(1, 0x9c, "TxExcDefer"),
  71         MIB_DESC(1, 0xa0, "TxDefer"),
  72         MIB_DESC(1, 0xa4, "TxLateCol"),
  73         MIB_DESC(1, 0xa8, "RXUnicast"),
  74         MIB_DESC(1, 0xac, "TXUnicast"),
  75 };
  76
  77 /* The 32bit switch registers are accessed indirectly. To achieve this we need
  78  * to set the page of the register. Track the last page that was set to reduce
  79  * mdio writes
  80  */
  81 static u16 qca8k_current_page = 0xffff;
  82
  83 static void
  84 qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
  85 {
  86         regaddr >>= 1;
  87         *r1 = regaddr & 0x1e;
  88
  89         regaddr >>= 5;
  90         *r2 = regaddr & 0x7;
  91
  92         regaddr >>= 3;
  93         *page = regaddr & 0x3ff;
  94 }
  95
  96 static int
  97 qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
  98 {
  99         int ret;
 100
 101         ret = bus->read(bus, phy_id, regnum);
 102         if (ret >= 0) {
 103                 *val = ret;
 104                 ret = bus->read(bus, phy_id, regnum + 1);
 105                 *val |= ret << 16;
 106         }
 107
 108         if (ret < 0) {
 109                 dev_err_ratelimited(&bus->dev,
 110                                     "failed to read qca8k 32bit register\n");
 111                 *val = 0;
 112                 return ret;
 113         }
 114
 115         return 0;
 116 }
 117
 118 static void
 119 qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
 120 {
 121         u16 lo, hi;
 122         int ret;
 123
 124         lo = val & 0xffff;
 125         hi = (u16)(val >> 16);
 126
 127         ret = bus->write(bus, phy_id, regnum, lo);
 128         if (ret >= 0)
 129                 ret = bus->write(bus, phy_id, regnum + 1, hi);
 130         if (ret < 0)
 131                 dev_err_ratelimited(&bus->dev,
 132                                     "failed to write qca8k 32bit register\n");
 133 }
 134
 135 static int
 136 qca8k_set_page(struct mii_bus *bus, u16 page)
 137 {
 138         int ret;
 139
 140         if (page == qca8k_current_page)
 141                 return 0;
 142
 143         ret = bus->write(bus, 0x18, 0, page);
 144         if (ret < 0) {
 145                 dev_err_ratelimited(&bus->dev,
 146                                     "failed to set qca8k page\n");
 147                 return ret;
 148         }
 149
 150         qca8k_current_page = page;
 151         usleep_range(1000, 2000);
 152         return 0;
 153 }
 154
 155 static int
 156 qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)
 157 {
 158         return regmap_read(priv->regmap, reg, val);
 159 }
 160
 161 static int
 162 qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
 163 {
 164         return regmap_write(priv->regmap, reg, val);
 165 }
 166
 167 static int
 168 qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
 169 {
 170         return regmap_update_bits(priv->regmap, reg, mask, write_val);
 171 }
 172
 173 static int
 174 qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
 175 {
 176         struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
 177         struct mii_bus *bus = priv->bus;
 178         u16 r1, r2, page;
 179         int ret;
 180
 181         qca8k_split_addr(reg, &r1, &r2, &page);
 182
 183         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 184
 185         ret = qca8k_set_page(bus, page);
 186         if (ret < 0)
 187                 goto exit;
 188
 189         ret = qca8k_mii_read32(bus, 0x10 | r2, r1, val);
 190
 191 exit:
 192         mutex_unlock(&bus->mdio_lock);
 193         return ret;
 194 }
 195
 196 static int
 197 qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val)
 198 {
 199         struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
 200         struct mii_bus *bus = priv->bus;
 201         u16 r1, r2, page;
 202         int ret;
 203
 204         qca8k_split_addr(reg, &r1, &r2, &page);
 205
 206         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 207
 208         ret = qca8k_set_page(bus, page);
 209         if (ret < 0)
 210                 goto exit;
 211
 212         qca8k_mii_write32(bus, 0x10 | r2, r1, val);
 213
 214 exit:
 215         mutex_unlock(&bus->mdio_lock);
 216         return ret;
 217 }
 218
 219 static int
 220 qca8k_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask, uint32_t write_val)
 221 {
 222         struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
 223         struct mii_bus *bus = priv->bus;
 224         u16 r1, r2, page;
 225         u32 val;
 226         int ret;
 227
 228         qca8k_split_addr(reg, &r1, &r2, &page);
 229
 230         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 231
 232         ret = qca8k_set_page(bus, page);
 233         if (ret < 0)
 234                 goto exit;
 235
 236         ret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val);
 237         if (ret < 0)
 238                 goto exit;
 239
 240         val &= ~mask;
 241         val |= write_val;
 242         qca8k_mii_write32(bus, 0x10 | r2, r1, val);
 243
 244 exit:
 245         mutex_unlock(&bus->mdio_lock);
 246
 247         return ret;
 248 }
 249
 250 static const struct regmap_range qca8k_readable_ranges[] = {
 251         regmap_reg_range(0x0000, 0x00e4), /* Global control */
 252         regmap_reg_range(0x0100, 0x0168), /* EEE control */
 253         regmap_reg_range(0x0200, 0x0270), /* Parser control */
 254         regmap_reg_range(0x0400, 0x0454), /* ACL */
 255         regmap_reg_range(0x0600, 0x0718), /* Lookup */
 256         regmap_reg_range(0x0800, 0x0b70), /* QM */
 257         regmap_reg_range(0x0c00, 0x0c80), /* PKT */
 258         regmap_reg_range(0x0e00, 0x0e98), /* L3 */
 259         regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
 260         regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
 261         regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
 262         regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
 263         regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
 264         regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
 265         regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
 266
 267 };
 268
 269 static const struct regmap_access_table qca8k_readable_table = {
 270         .yes_ranges = qca8k_readable_ranges,
 271         .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
 272 };
 273
 274 static struct regmap_config qca8k_regmap_config = {
 275         .reg_bits = 16,
 276         .val_bits = 32,
 277         .reg_stride = 4,
 278         .max_register = 0x16ac, /* end MIB - Port6 range */
 279         .reg_read = qca8k_regmap_read,
 280         .reg_write = qca8k_regmap_write,
 281         .reg_update_bits = qca8k_regmap_update_bits,
 282         .rd_table = &qca8k_readable_table,
 283         .disable_locking = true, /* Locking is handled by qca8k read/write */
 284         .cache_type = REGCACHE_NONE, /* Explicitly disable CACHE */
 285 };
 286
 287 static int
 288 qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
 289 {
 290         u32 val;
 291
 292         return regmap_read_poll_timeout(priv->regmap, reg, val, !(val & mask), 0,
 293                                        QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC);
 294 }
 295
 296 static int
 297 qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)
 298 {
 299         u32 reg[4], val;
 300         int i, ret;
 301
 302         /* load the ARL table into an array */
 303         for (i = 0; i < 4; i++) {
 304                 ret = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4), &val);
 305                 if (ret < 0)
 306                         return ret;
 307
 308                 reg[i] = val;
 309         }
 310
 311         /* vid - 83:72 */
 312         fdb->vid = FIELD_GET(QCA8K_ATU_VID_MASK, reg[2]);
 313         /* aging - 67:64 */
 314         fdb->aging = FIELD_GET(QCA8K_ATU_STATUS_MASK, reg[2]);
 315         /* portmask - 54:48 */
 316         fdb->port_mask = FIELD_GET(QCA8K_ATU_PORT_MASK, reg[1]);
 317         /* mac - 47:0 */
 318         fdb->mac[0] = FIELD_GET(QCA8K_ATU_ADDR0_MASK, reg[1]);
 319         fdb->mac[1] = FIELD_GET(QCA8K_ATU_ADDR1_MASK, reg[1]);
 320         fdb->mac[2] = FIELD_GET(QCA8K_ATU_ADDR2_MASK, reg[0]);
 321         fdb->mac[3] = FIELD_GET(QCA8K_ATU_ADDR3_MASK, reg[0]);
 322         fdb->mac[4] = FIELD_GET(QCA8K_ATU_ADDR4_MASK, reg[0]);
 323         fdb->mac[5] = FIELD_GET(QCA8K_ATU_ADDR5_MASK, reg[0]);
 324
 325         return 0;
 326 }
 327
 328 static void
 329 qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 port_mask, const u8 *mac,
 330                 u8 aging)
 331 {
 332         u32 reg[3] = { 0 };
 333         int i;
 334
 335         /* vid - 83:72 */
 336         reg[2] = FIELD_PREP(QCA8K_ATU_VID_MASK, vid);
 337         /* aging - 67:64 */
 338         reg[2] |= FIELD_PREP(QCA8K_ATU_STATUS_MASK, aging);
 339         /* portmask - 54:48 */
 340         reg[1] = FIELD_PREP(QCA8K_ATU_PORT_MASK, port_mask);
 341         /* mac - 47:0 */
 342         reg[1] |= FIELD_PREP(QCA8K_ATU_ADDR0_MASK, mac[0]);
 343         reg[1] |= FIELD_PREP(QCA8K_ATU_ADDR1_MASK, mac[1]);
 344         reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR2_MASK, mac[2]);
 345         reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR3_MASK, mac[3]);
 346         reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR4_MASK, mac[4]);
 347         reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR5_MASK, mac[5]);
 348
 349         /* load the array into the ARL table */
 350         for (i = 0; i < 3; i++)
 351                 qca8k_write(priv, QCA8K_REG_ATU_DATA0 + (i * 4), reg[i]);
 352 }
 353
 354 static int
 355 qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port)
 356 {
 357         u32 reg;
 358         int ret;
 359
 360         /* Set the command and FDB index */
 361         reg = QCA8K_ATU_FUNC_BUSY;
 362         reg |= cmd;
 363         if (port >= 0) {
 364                 reg |= QCA8K_ATU_FUNC_PORT_EN;
 365                 reg |= FIELD_PREP(QCA8K_ATU_FUNC_PORT_MASK, port);
 366         }
 367
 368         /* Write the function register triggering the table access */
 369         ret = qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);
 370         if (ret)
 371                 return ret;
 372
 373         /* wait for completion */
 374         ret = qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY);
 375         if (ret)
 376                 return ret;
 377
 378         /* Check for table full violation when adding an entry */
 379         if (cmd == QCA8K_FDB_LOAD) {
 380                 ret = qca8k_read(priv, QCA8K_REG_ATU_FUNC, &reg);
 381                 if (ret < 0)
 382                         return ret;
 383                 if (reg & QCA8K_ATU_FUNC_FULL)
 384                         return -1;
 385         }
 386
 387         return 0;
 388 }
 389
 390 static int
 391 qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb, int port)
 392 {
 393         int ret;
 394
 395         qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging);
 396         ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port);
 397         if (ret < 0)
 398                 return ret;
 399
 400         return qca8k_fdb_read(priv, fdb);
 401 }
 402
 403 static int
 404 qca8k_fdb_add(struct qca8k_priv *priv, const u8 *mac, u16 port_mask,
 405               u16 vid, u8 aging)
 406 {
 407         int ret;
 408
 409         mutex_lock(&priv->reg_mutex);
 410         qca8k_fdb_write(priv, vid, port_mask, mac, aging);
 411         ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
 412         mutex_unlock(&priv->reg_mutex);
 413
 414         return ret;
 415 }
 416
 417 static int
 418 qca8k_fdb_del(struct qca8k_priv *priv, const u8 *mac, u16 port_mask, u16 vid)
 419 {
 420         int ret;
 421
 422         mutex_lock(&priv->reg_mutex);
 423         qca8k_fdb_write(priv, vid, port_mask, mac, 0);
 424         ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
 425         mutex_unlock(&priv->reg_mutex);
 426
 427         return ret;
 428 }
 429
 430 static void
 431 qca8k_fdb_flush(struct qca8k_priv *priv)
 432 {
 433         mutex_lock(&priv->reg_mutex);
 434         qca8k_fdb_access(priv, QCA8K_FDB_FLUSH, -1);
 435         mutex_unlock(&priv->reg_mutex);
 436 }
 437
 438 static int
 439 qca8k_fdb_search_and_insert(struct qca8k_priv *priv, u8 port_mask,
 440                             const u8 *mac, u16 vid)
 441 {
 442         struct qca8k_fdb fdb = { 0 };
 443         int ret;
 444
 445         mutex_lock(&priv->reg_mutex);
 446
 447         qca8k_fdb_write(priv, vid, 0, mac, 0);
 448         ret = qca8k_fdb_access(priv, QCA8K_FDB_SEARCH, -1);
 449         if (ret < 0)
 450                 goto exit;
 451
 452         ret = qca8k_fdb_read(priv, &fdb);
 453         if (ret < 0)
 454                 goto exit;
 455
 456         /* Rule exist. Delete first */
 457         if (!fdb.aging) {
 458                 ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
 459                 if (ret)
 460                         goto exit;
 461         }
 462
 463         /* Add port to fdb portmask */
 464         fdb.port_mask |= port_mask;
 465
 466         qca8k_fdb_write(priv, vid, fdb.port_mask, mac, fdb.aging);
 467         ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
 468
 469 exit:
 470         mutex_unlock(&priv->reg_mutex);
 471         return ret;
 472 }
 473
 474 static int
 475 qca8k_fdb_search_and_del(struct qca8k_priv *priv, u8 port_mask,
 476                          const u8 *mac, u16 vid)
 477 {
 478         struct qca8k_fdb fdb = { 0 };
 479         int ret;
 480
 481         mutex_lock(&priv->reg_mutex);
 482
 483         qca8k_fdb_write(priv, vid, 0, mac, 0);
 484         ret = qca8k_fdb_access(priv, QCA8K_FDB_SEARCH, -1);
 485         if (ret < 0)
 486                 goto exit;
 487
 488         /* Rule doesn't exist. Why delete? */
 489         if (!fdb.aging) {
 490                 ret = -EINVAL;
 491                 goto exit;
 492         }
 493
 494         ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
 495         if (ret)
 496                 goto exit;
 497
 498         /* Only port in the rule is this port. Don't re insert */
 499         if (fdb.port_mask == port_mask)
 500                 goto exit;
 501
 502         /* Remove port from port mask */
 503         fdb.port_mask &= ~port_mask;
 504
 505         qca8k_fdb_write(priv, vid, fdb.port_mask, mac, fdb.aging);
 506         ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
 507
 508 exit:
 509         mutex_unlock(&priv->reg_mutex);
 510         return ret;
 511 }
 512
 513 static int
 514 qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid)
 515 {
 516         u32 reg;
 517         int ret;
 518
 519         /* Set the command and VLAN index */
 520         reg = QCA8K_VTU_FUNC1_BUSY;
 521         reg |= cmd;
 522         reg |= FIELD_PREP(QCA8K_VTU_FUNC1_VID_MASK, vid);
 523
 524         /* Write the function register triggering the table access */
 525         ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg);
 526         if (ret)
 527                 return ret;
 528
 529         /* wait for completion */
 530         ret = qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY);
 531         if (ret)
 532                 return ret;
 533
 534         /* Check for table full violation when adding an entry */
 535         if (cmd == QCA8K_VLAN_LOAD) {
 536                 ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC1, &reg);
 537                 if (ret < 0)
 538                         return ret;
 539                 if (reg & QCA8K_VTU_FUNC1_FULL)
 540                         return -ENOMEM;
 541         }
 542
 543         return 0;
 544 }
 545
 546 static int
 547 qca8k_vlan_add(struct qca8k_priv *priv, u8 port, u16 vid, bool untagged)
 548 {
 549         u32 reg;
 550         int ret;
 551
 552         /*
 553            We do the right thing with VLAN 0 and treat it as untagged while
 554            preserving the tag on egress.
 555          */
 556         if (vid == 0)
 557                 return 0;
 558
 559         mutex_lock(&priv->reg_mutex);
 560         ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid);
 561         if (ret < 0)
 562                 goto out;
 563
 564         ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, &reg);
 565         if (ret < 0)
 566                 goto out;
 567         reg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN;
 568         reg &= ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port);
 569         if (untagged)
 570                 reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(port);
 571         else
 572                 reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(port);
 573
 574         ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
 575         if (ret)
 576                 goto out;
 577         ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
 578
 579 out:
 580         mutex_unlock(&priv->reg_mutex);
 581
 582         return ret;
 583 }
 584
 585 static int
 586 qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid)
 587 {
 588         u32 reg, mask;
 589         int ret, i;
 590         bool del;
 591
 592         mutex_lock(&priv->reg_mutex);
 593         ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid);
 594         if (ret < 0)
 595                 goto out;
 596
 597         ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, &reg);
 598         if (ret < 0)
 599                 goto out;
 600         reg &= ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port);
 601         reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(port);
 602
 603         /* Check if we're the last member to be removed */
 604         del = true;
 605         for (i = 0; i < QCA8K_NUM_PORTS; i++) {
 606                 mask = QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(i);
 607
 608                 if ((reg & mask) != mask) {
 609                         del = false;
 610                         break;
 611                 }
 612         }
 613
 614         if (del) {
 615                 ret = qca8k_vlan_access(priv, QCA8K_VLAN_PURGE, vid);
 616         } else {
 617                 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
 618                 if (ret)
 619                         goto out;
 620                 ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
 621         }
 622
 623 out:
 624         mutex_unlock(&priv->reg_mutex);
 625
 626         return ret;
 627 }
 628
 629 static int
 630 qca8k_mib_init(struct qca8k_priv *priv)
 631 {
 632         int ret;
 633
 634         mutex_lock(&priv->reg_mutex);
 635         ret = regmap_set_bits(priv->regmap, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);
 636         if (ret)
 637                 goto exit;
 638
 639         ret = qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);
 640         if (ret)
 641                 goto exit;
 642
 643         ret = regmap_set_bits(priv->regmap, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
 644         if (ret)
 645                 goto exit;
 646
 647         ret = qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
 648
 649 exit:
 650         mutex_unlock(&priv->reg_mutex);
 651         return ret;
 652 }
 653
 654 static void
 655 qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
 656 {
 657         u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
 658
 659         /* Port 0 and 6 have no internal PHY */
 660         if (port > 0 && port < 6)
 661                 mask |= QCA8K_PORT_STATUS_LINK_AUTO;
 662
 663         if (enable)
 664                 regmap_set_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask);
 665         else
 666                 regmap_clear_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask);
 667 }
 668
 669 static u32
 670 qca8k_port_to_phy(int port)
 671 {
 672         /* From Andrew Lunn:
 673          * Port 0 has no internal phy.
 674          * Port 1 has an internal PHY at MDIO address 0.
 675          * Port 2 has an internal PHY at MDIO address 1.
 676          * ...
 677          * Port 5 has an internal PHY at MDIO address 4.
 678          * Port 6 has no internal PHY.
 679          */
 680
 681         return port - 1;
 682 }
 683
 684 static int
 685 qca8k_mdio_busy_wait(struct mii_bus *bus, u32 reg, u32 mask)
 686 {
 687         u16 r1, r2, page;
 688         u32 val;
 689         int ret, ret1;
 690
 691         qca8k_split_addr(reg, &r1, &r2, &page);
 692
 693         ret = read_poll_timeout(qca8k_mii_read32, ret1, !(val & mask), 0,
 694                                 QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
 695                                 bus, 0x10 | r2, r1, &val);
 696
 697         /* Check if qca8k_read has failed for a different reason
 698          * before returnting -ETIMEDOUT
 699          */
 700         if (ret < 0 && ret1 < 0)
 701                 return ret1;
 702
 703         return ret;
 704 }
 705
 706 static int
 707 qca8k_mdio_write(struct mii_bus *bus, int phy, int regnum, u16 data)
 708 {
 709         u16 r1, r2, page;
 710         u32 val;
 711         int ret;
 712
 713         if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
 714                 return -EINVAL;
 715
 716         val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
 717               QCA8K_MDIO_MASTER_WRITE | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
 718               QCA8K_MDIO_MASTER_REG_ADDR(regnum) |
 719               QCA8K_MDIO_MASTER_DATA(data);
 720
 721         qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page);
 722
 723         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 724
 725         ret = qca8k_set_page(bus, page);
 726         if (ret)
 727                 goto exit;
 728
 729         qca8k_mii_write32(bus, 0x10 | r2, r1, val);
 730
 731         ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
 732                                    QCA8K_MDIO_MASTER_BUSY);
 733
 734 exit:
 735         /* even if the busy_wait timeouts try to clear the MASTER_EN */
 736         qca8k_mii_write32(bus, 0x10 | r2, r1, 0);
 737
 738         mutex_unlock(&bus->mdio_lock);
 739
 740         return ret;
 741 }
 742
 743 static int
 744 qca8k_mdio_read(struct mii_bus *bus, int phy, int regnum)
 745 {
 746         u16 r1, r2, page;
 747         u32 val;
 748         int ret;
 749
 750         if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
 751                 return -EINVAL;
 752
 753         val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
 754               QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
 755               QCA8K_MDIO_MASTER_REG_ADDR(regnum);
 756
 757         qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page);
 758
 759         mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
 760
 761         ret = qca8k_set_page(bus, page);
 762         if (ret)
 763                 goto exit;
 764
 765         qca8k_mii_write32(bus, 0x10 | r2, r1, val);
 766
 767         ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
 768                                    QCA8K_MDIO_MASTER_BUSY);
 769         if (ret)
 770                 goto exit;
 771
 772         ret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val);
 773
 774 exit:
 775         /* even if the busy_wait timeouts try to clear the MASTER_EN */
 776         qca8k_mii_write32(bus, 0x10 | r2, r1, 0);
 777
 778         mutex_unlock(&bus->mdio_lock);
 779
 780         if (ret >= 0)
 781                 ret = val & QCA8K_MDIO_MASTER_DATA_MASK;
 782
 783         return ret;
 784 }
 785
 786 static int
 787 qca8k_internal_mdio_write(struct mii_bus *slave_bus, int phy, int regnum, u16 data)
 788 {
 789         struct qca8k_priv *priv = slave_bus->priv;
 790         struct mii_bus *bus = priv->bus;
 791
 792         return qca8k_mdio_write(bus, phy, regnum, data);
 793 }
 794
 795 static int
 796 qca8k_internal_mdio_read(struct mii_bus *slave_bus, int phy, int regnum)
 797 {
 798         struct qca8k_priv *priv = slave_bus->priv;
 799         struct mii_bus *bus = priv->bus;
 800
 801         return qca8k_mdio_read(bus, phy, regnum);
 802 }
 803
 804 static int
 805 qca8k_phy_write(struct dsa_switch *ds, int port, int regnum, u16 data)
 806 {
 807         struct qca8k_priv *priv = ds->priv;
 808
 809         /* Check if the legacy mapping should be used and the
 810          * port is not correctly mapped to the right PHY in the
 811          * devicetree
 812          */
 813         if (priv->legacy_phy_port_mapping)
 814                 port = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
 815
 816         return qca8k_mdio_write(priv->bus, port, regnum, data);
 817 }
 818
 819 static int
 820 qca8k_phy_read(struct dsa_switch *ds, int port, int regnum)
 821 {
 822         struct qca8k_priv *priv = ds->priv;
 823         int ret;
 824
 825         /* Check if the legacy mapping should be used and the
 826          * port is not correctly mapped to the right PHY in the
 827          * devicetree
 828          */
 829         if (priv->legacy_phy_port_mapping)
 830                 port = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
 831
 832         ret = qca8k_mdio_read(priv->bus, port, regnum);
 833
 834         if (ret < 0)
 835                 return 0xffff;
 836
 837         return ret;
 838 }
 839
 840 static int
 841 qca8k_mdio_register(struct qca8k_priv *priv, struct device_node *mdio)
 842 {
 843         struct dsa_switch *ds = priv->ds;
 844         struct mii_bus *bus;
 845
 846         bus = devm_mdiobus_alloc(ds->dev);
 847
 848         if (!bus)
 849                 return -ENOMEM;
 850
 851         bus->priv = (void *)priv;
 852         bus->name = "qca8k slave mii";
 853         bus->read = qca8k_internal_mdio_read;
 854         bus->write = qca8k_internal_mdio_write;
 855         snprintf(bus->id, MII_BUS_ID_SIZE, "qca8k-%d",
 856                  ds->index);
 857
 858         bus->parent = ds->dev;
 859         bus->phy_mask = ~ds->phys_mii_mask;
 860
 861         ds->slave_mii_bus = bus;
 862
 863         return devm_of_mdiobus_register(priv->dev, bus, mdio);
 864 }
 865
 866 static int
 867 qca8k_setup_mdio_bus(struct qca8k_priv *priv)
 868 {
 869         u32 internal_mdio_mask = 0, external_mdio_mask = 0, reg;
 870         struct device_node *ports, *port, *mdio;
 871         phy_interface_t mode;
 872         int err;
 873
 874         ports = of_get_child_by_name(priv->dev->of_node, "ports");
 875         if (!ports)
 876                 ports = of_get_child_by_name(priv->dev->of_node, "ethernet-ports");
 877
 878         if (!ports)
 879                 return -EINVAL;
 880
 881         for_each_available_child_of_node(ports, port) {
 882                 err = of_property_read_u32(port, "reg", &reg);
 883                 if (err) {
 884                         of_node_put(port);
 885                         of_node_put(ports);
 886                         return err;
 887                 }
 888
 889                 if (!dsa_is_user_port(priv->ds, reg))
 890                         continue;
 891
 892                 of_get_phy_mode(port, &mode);
 893
 894                 if (of_property_read_bool(port, "phy-handle") &&
 895                     mode != PHY_INTERFACE_MODE_INTERNAL)
 896                         external_mdio_mask |= BIT(reg);
 897                 else
 898                         internal_mdio_mask |= BIT(reg);
 899         }
 900
 901         of_node_put(ports);
 902         if (!external_mdio_mask && !internal_mdio_mask) {
 903                 dev_err(priv->dev, "no PHYs are defined.\n");
 904                 return -EINVAL;
 905         }
 906
 907         /* The QCA8K_MDIO_MASTER_EN Bit, which grants access to PHYs through
 908          * the MDIO_MASTER register also _disconnects_ the external MDC
 909          * passthrough to the internal PHYs. It's not possible to use both
 910          * configurations at the same time!
 911          *
 912          * Because this came up during the review process:
 913          * If the external mdio-bus driver is capable magically disabling
 914          * the QCA8K_MDIO_MASTER_EN and mutex/spin-locking out the qca8k's
 915          * accessors for the time being, it would be possible to pull this
 916          * off.
 917          */
 918         if (!!external_mdio_mask && !!internal_mdio_mask) {
 919                 dev_err(priv->dev, "either internal or external mdio bus configuration is supported.\n");
 920                 return -EINVAL;
 921         }
 922
 923         if (external_mdio_mask) {
 924                 /* Make sure to disable the internal mdio bus in cases
 925                  * a dt-overlay and driver reload changed the configuration
 926                  */
 927
 928                 return regmap_clear_bits(priv->regmap, QCA8K_MDIO_MASTER_CTRL,
 929                                          QCA8K_MDIO_MASTER_EN);
 930         }
 931
 932         /* Check if the devicetree declare the port:phy mapping */
 933         mdio = of_get_child_by_name(priv->dev->of_node, "mdio");
 934         if (of_device_is_available(mdio)) {
 935                 err = qca8k_mdio_register(priv, mdio);
 936                 if (err)
 937                         of_node_put(mdio);
 938
 939                 return err;
 940         }
 941
 942         /* If a mapping can't be found the legacy mapping is used,
 943          * using the qca8k_port_to_phy function
 944          */
 945         priv->legacy_phy_port_mapping = true;
 946         priv->ops.phy_read = qca8k_phy_read;
 947         priv->ops.phy_write = qca8k_phy_write;
 948
 949         return 0;
 950 }
 951
 952 static int
 953 qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv)
 954 {
 955         u32 mask = 0;
 956         int ret = 0;
 957
 958         /* SoC specific settings for ipq8064.
 959          * If more device require this consider adding
 960          * a dedicated binding.
 961          */
 962         if (of_machine_is_compatible("qcom,ipq8064"))
 963                 mask |= QCA8K_MAC_PWR_RGMII0_1_8V;
 964
 965         /* SoC specific settings for ipq8065 */
 966         if (of_machine_is_compatible("qcom,ipq8065"))
 967                 mask |= QCA8K_MAC_PWR_RGMII1_1_8V;
 968
 969         if (mask) {
 970                 ret = qca8k_rmw(priv, QCA8K_REG_MAC_PWR_SEL,
 971                                 QCA8K_MAC_PWR_RGMII0_1_8V |
 972                                 QCA8K_MAC_PWR_RGMII1_1_8V,
 973                                 mask);
 974         }
 975
 976         return ret;
 977 }
 978
 979 static int qca8k_find_cpu_port(struct dsa_switch *ds)
 980 {
 981         struct qca8k_priv *priv = ds->priv;
 982
 983         /* Find the connected cpu port. Valid port are 0 or 6 */
 984         if (dsa_is_cpu_port(ds, 0))
 985                 return 0;
 986
 987         dev_dbg(priv->dev, "port 0 is not the CPU port. Checking port 6");
 988
 989         if (dsa_is_cpu_port(ds, 6))
 990                 return 6;
 991
 992         return -EINVAL;
 993 }
 994
 995 static int
 996 qca8k_setup_of_pws_reg(struct qca8k_priv *priv)
 997 {
 998         struct device_node *node = priv->dev->of_node;
 999         const struct qca8k_match_data *data;
1000         u32 val = 0;
1001         int ret;
1002
1003         /* QCA8327 require to set to the correct mode.
1004          * His bigger brother QCA8328 have the 172 pin layout.
1005          * Should be applied by default but we set this just to make sure.
1006          */
1007         if (priv->switch_id == QCA8K_ID_QCA8327) {
1008                 data = of_device_get_match_data(priv->dev);
1009
1010                 /* Set the correct package of 148 pin for QCA8327 */
1011                 if (data->reduced_package)
1012                         val |= QCA8327_PWS_PACKAGE148_EN;
1013
1014                 ret = qca8k_rmw(priv, QCA8K_REG_PWS, QCA8327_PWS_PACKAGE148_EN,
1015                                 val);
1016                 if (ret)
1017                         return ret;
1018         }
1019
1020         if (of_property_read_bool(node, "qca,ignore-power-on-sel"))
1021                 val |= QCA8K_PWS_POWER_ON_SEL;
1022
1023         if (of_property_read_bool(node, "qca,led-open-drain")) {
1024                 if (!(val & QCA8K_PWS_POWER_ON_SEL)) {
1025                         dev_err(priv->dev, "qca,led-open-drain require qca,ignore-power-on-sel to be set.");
1026                         return -EINVAL;
1027                 }
1028
1029                 val |= QCA8K_PWS_LED_OPEN_EN_CSR;
1030         }
1031
1032         return qca8k_rmw(priv, QCA8K_REG_PWS,
1033                         QCA8K_PWS_LED_OPEN_EN_CSR | QCA8K_PWS_POWER_ON_SEL,
1034                         val);
1035 }
1036
1037 static int
1038 qca8k_parse_port_config(struct qca8k_priv *priv)
1039 {
1040         int port, cpu_port_index = -1, ret;
1041         struct device_node *port_dn;
1042         phy_interface_t mode;
1043         struct dsa_port *dp;
1044         u32 delay;
1045
1046         /* We have 2 CPU port. Check them */
1047         for (port = 0; port < QCA8K_NUM_PORTS; port++) {
1048                 /* Skip every other port */
1049                 if (port != 0 && port != 6)
1050                         continue;
1051
1052                 dp = dsa_to_port(priv->ds, port);
1053                 port_dn = dp->dn;
1054                 cpu_port_index++;
1055
1056                 if (!of_device_is_available(port_dn))
1057                         continue;
1058
1059                 ret = of_get_phy_mode(port_dn, &mode);
1060                 if (ret)
1061                         continue;
1062
1063                 switch (mode) {
1064                 case PHY_INTERFACE_MODE_RGMII:
1065                 case PHY_INTERFACE_MODE_RGMII_ID:
1066                 case PHY_INTERFACE_MODE_RGMII_TXID:
1067                 case PHY_INTERFACE_MODE_RGMII_RXID:
1068                 case PHY_INTERFACE_MODE_SGMII:
1069                         delay = 0;
1070
1071                         if (!of_property_read_u32(port_dn, "tx-internal-delay-ps", &delay))
1072                                 /* Switch regs accept value in ns, convert ps to ns */
1073                                 delay = delay / 1000;
1074                         else if (mode == PHY_INTERFACE_MODE_RGMII_ID ||
1075                                  mode == PHY_INTERFACE_MODE_RGMII_TXID)
1076                                 delay = 1;
1077
1078                         if (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK, delay)) {
1079                                 dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value");
1080                                 delay = 3;
1081                         }
1082
1083                         priv->ports_config.rgmii_tx_delay[cpu_port_index] = delay;
1084
1085                         delay = 0;
1086
1087                         if (!of_property_read_u32(port_dn, "rx-internal-delay-ps", &delay))
1088                                 /* Switch regs accept value in ns, convert ps to ns */
1089                                 delay = delay / 1000;
1090                         else if (mode == PHY_INTERFACE_MODE_RGMII_ID ||
1091                                  mode == PHY_INTERFACE_MODE_RGMII_RXID)
1092                                 delay = 2;
1093
1094                         if (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK, delay)) {
1095                                 dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value");
1096                                 delay = 3;
1097                         }
1098
1099                         priv->ports_config.rgmii_rx_delay[cpu_port_index] = delay;
1100
1101                         /* Skip sgmii parsing for rgmii* mode */
1102                         if (mode == PHY_INTERFACE_MODE_RGMII ||
1103                             mode == PHY_INTERFACE_MODE_RGMII_ID ||
1104                             mode == PHY_INTERFACE_MODE_RGMII_TXID ||
1105                             mode == PHY_INTERFACE_MODE_RGMII_RXID)
1106                                 break;
1107
1108                         if (of_property_read_bool(port_dn, "qca,sgmii-txclk-falling-edge"))
1109                                 priv->ports_config.sgmii_tx_clk_falling_edge = true;
1110
1111                         if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge"))
1112                                 priv->ports_config.sgmii_rx_clk_falling_edge = true;
1113
1114                         if (of_property_read_bool(port_dn, "qca,sgmii-enable-pll")) {
1115                                 priv->ports_config.sgmii_enable_pll = true;
1116
1117                                 if (priv->switch_id == QCA8K_ID_QCA8327) {
1118                                         dev_err(priv->dev, "SGMII PLL should NOT be enabled for qca8327. Aborting enabling");
1119                                         priv->ports_config.sgmii_enable_pll = false;
1120                                 }
1121
1122                                 if (priv->switch_revision < 2)
1123                                         dev_warn(priv->dev, "SGMII PLL should NOT be enabled for qca8337 with revision 2 or more.");
1124                         }
1125
1126                         break;
1127                 default:
1128                         continue;
1129                 }
1130         }
1131
1132         return 0;
1133 }
1134
1135 static int
1136 qca8k_setup(struct dsa_switch *ds)
1137 {
1138         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1139         int cpu_port, ret, i;
1140         u32 mask;
1141
1142         cpu_port = qca8k_find_cpu_port(ds);
1143         if (cpu_port < 0) {
1144                 dev_err(priv->dev, "No cpu port configured in both cpu port0 and port6");
1145                 return cpu_port;
1146         }
1147
1148         /* Parse CPU port config to be later used in phy_link mac_config */
1149         ret = qca8k_parse_port_config(priv);
1150         if (ret)
1151                 return ret;
1152
1153         ret = qca8k_setup_mdio_bus(priv);
1154         if (ret)
1155                 return ret;
1156
1157         ret = qca8k_setup_of_pws_reg(priv);
1158         if (ret)
1159                 return ret;
1160
1161         ret = qca8k_setup_mac_pwr_sel(priv);
1162         if (ret)
1163                 return ret;
1164
1165         /* Make sure MAC06 is disabled */
1166         ret = regmap_clear_bits(priv->regmap, QCA8K_REG_PORT0_PAD_CTRL,
1167                                 QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN);
1168         if (ret) {
1169                 dev_err(priv->dev, "failed disabling MAC06 exchange");
1170                 return ret;
1171         }
1172
1173         /* Enable CPU Port */
1174         ret = regmap_set_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
1175                               QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
1176         if (ret) {
1177                 dev_err(priv->dev, "failed enabling CPU port");
1178                 return ret;
1179         }
1180
1181         /* Enable MIB counters */
1182         ret = qca8k_mib_init(priv);
1183         if (ret)
1184                 dev_warn(priv->dev, "mib init failed");
1185
1186         /* Initial setup of all ports */
1187         for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1188                 /* Disable forwarding by default on all ports */
1189                 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
1190                                 QCA8K_PORT_LOOKUP_MEMBER, 0);
1191                 if (ret)
1192                         return ret;
1193
1194                 /* Enable QCA header mode on all cpu ports */
1195                 if (dsa_is_cpu_port(ds, i)) {
1196                         ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(i),
1197                                           FIELD_PREP(QCA8K_PORT_HDR_CTRL_TX_MASK, QCA8K_PORT_HDR_CTRL_ALL) |
1198                                           FIELD_PREP(QCA8K_PORT_HDR_CTRL_RX_MASK, QCA8K_PORT_HDR_CTRL_ALL));
1199                         if (ret) {
1200                                 dev_err(priv->dev, "failed enabling QCA header mode");
1201                                 return ret;
1202                         }
1203                 }
1204
1205                 /* Disable MAC by default on all user ports */
1206                 if (dsa_is_user_port(ds, i))
1207                         qca8k_port_set_status(priv, i, 0);
1208         }
1209
1210         /* Forward all unknown frames to CPU port for Linux processing
1211          * Notice that in multi-cpu config only one port should be set
1212          * for igmp, unknown, multicast and broadcast packet
1213          */
1214         ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
1215                           FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK, BIT(cpu_port)) |
1216                           FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK, BIT(cpu_port)) |
1217                           FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK, BIT(cpu_port)) |
1218                           FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK, BIT(cpu_port)));
1219         if (ret)
1220                 return ret;
1221
1222         /* Setup connection between CPU port & user ports
1223          * Configure specific switch configuration for ports
1224          */
1225         for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1226                 /* CPU port gets connected to all user ports of the switch */
1227                 if (dsa_is_cpu_port(ds, i)) {
1228                         ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
1229                                         QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
1230                         if (ret)
1231                                 return ret;
1232                 }
1233
1234                 /* Individual user ports get connected to CPU port only */
1235                 if (dsa_is_user_port(ds, i)) {
1236                         ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
1237                                         QCA8K_PORT_LOOKUP_MEMBER,
1238                                         BIT(cpu_port));
1239                         if (ret)
1240                                 return ret;
1241
1242                         /* Enable ARP Auto-learning by default */
1243                         ret = regmap_set_bits(priv->regmap, QCA8K_PORT_LOOKUP_CTRL(i),
1244                                               QCA8K_PORT_LOOKUP_LEARN);
1245                         if (ret)
1246                                 return ret;
1247
1248                         /* For port based vlans to work we need to set the
1249                          * default egress vid
1250                          */
1251                         ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
1252                                         QCA8K_EGREES_VLAN_PORT_MASK(i),
1253                                         QCA8K_EGREES_VLAN_PORT(i, QCA8K_PORT_VID_DEF));
1254                         if (ret)
1255                                 return ret;
1256
1257                         ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
1258                                           QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |
1259                                           QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));
1260                         if (ret)
1261                                 return ret;
1262                 }
1263
1264                 /* The port 5 of the qca8337 have some problem in flood condition. The
1265                  * original legacy driver had some specific buffer and priority settings
1266                  * for the different port suggested by the QCA switch team. Add this
1267                  * missing settings to improve switch stability under load condition.
1268                  * This problem is limited to qca8337 and other qca8k switch are not affected.
1269                  */
1270                 if (priv->switch_id == QCA8K_ID_QCA8337) {
1271                         switch (i) {
1272                         /* The 2 CPU port and port 5 requires some different
1273                          * priority than any other ports.
1274                          */
1275                         case 0:
1276                         case 5:
1277                         case 6:
1278                                 mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
1279                                         QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
1280                                         QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) |
1281                                         QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) |
1282                                         QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) |
1283                                         QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) |
1284                                         QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e);
1285                                 break;
1286                         default:
1287                                 mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
1288                                         QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
1289                                         QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) |
1290                                         QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) |
1291                                         QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19);
1292                         }
1293                         qca8k_write(priv, QCA8K_REG_PORT_HOL_CTRL0(i), mask);
1294
1295                         mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) |
1296                         QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
1297                         QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
1298                         QCA8K_PORT_HOL_CTRL1_WRED_EN;
1299                         qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i),
1300                                   QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK |
1301                                   QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
1302                                   QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
1303                                   QCA8K_PORT_HOL_CTRL1_WRED_EN,
1304                                   mask);
1305                 }
1306
1307                 /* Set initial MTU for every port.
1308                  * We have only have a general MTU setting. So track
1309                  * every port and set the max across all port.
1310                  * Set per port MTU to 1500 as the MTU change function
1311                  * will add the overhead and if its set to 1518 then it
1312                  * will apply the overhead again and we will end up with
1313                  * MTU of 1536 instead of 1518
1314                  */
1315                 priv->port_mtu[i] = ETH_DATA_LEN;
1316         }
1317
1318         /* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */
1319         if (priv->switch_id == QCA8K_ID_QCA8327) {
1320                 mask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) |
1321                        QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496);
1322                 qca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH,
1323                           QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK |
1324                           QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK,
1325                           mask);
1326         }
1327
1328         /* Setup our port MTUs to match power on defaults */
1329         ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);
1330         if (ret)
1331                 dev_warn(priv->dev, "failed setting MTU settings");
1332
1333         /* Flush the FDB table */
1334         qca8k_fdb_flush(priv);
1335
1336         /* We don't have interrupts for link changes, so we need to poll */
1337         ds->pcs_poll = true;
1338
1339         /* Set min a max ageing value supported */
1340         ds->ageing_time_min = 7000;
1341         ds->ageing_time_max = 458745000;
1342
1343         /* Set max number of LAGs supported */
1344         ds->num_lag_ids = QCA8K_NUM_LAGS;
1345
1346         return 0;
1347 }
1348
1349 static void
1350 qca8k_mac_config_setup_internal_delay(struct qca8k_priv *priv, int cpu_port_index,
1351                                       u32 reg)
1352 {
1353         u32 delay, val = 0;
1354         int ret;
1355
1356         /* Delay can be declared in 3 different way.
1357          * Mode to rgmii and internal-delay standard binding defined
1358          * rgmii-id or rgmii-tx/rx phy mode set.
1359          * The parse logic set a delay different than 0 only when one
1360          * of the 3 different way is used. In all other case delay is
1361          * not enabled. With ID or TX/RXID delay is enabled and set
1362          * to the default and recommended value.
1363          */
1364         if (priv->ports_config.rgmii_tx_delay[cpu_port_index]) {
1365                 delay = priv->ports_config.rgmii_tx_delay[cpu_port_index];
1366
1367                 val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |
1368                         QCA8K_PORT_PAD_RGMII_TX_DELAY_EN;
1369         }
1370
1371         if (priv->ports_config.rgmii_rx_delay[cpu_port_index]) {
1372                 delay = priv->ports_config.rgmii_rx_delay[cpu_port_index];
1373
1374                 val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |
1375                         QCA8K_PORT_PAD_RGMII_RX_DELAY_EN;
1376         }
1377
1378         /* Set RGMII delay based on the selected values */
1379         ret = qca8k_rmw(priv, reg,
1380                         QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK |
1381                         QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK |
1382                         QCA8K_PORT_PAD_RGMII_TX_DELAY_EN |
1383                         QCA8K_PORT_PAD_RGMII_RX_DELAY_EN,
1384                         val);
1385         if (ret)
1386                 dev_err(priv->dev, "Failed to set internal delay for CPU port%d",
1387                         cpu_port_index == QCA8K_CPU_PORT0 ? 0 : 6);
1388 }
1389
1390 static void
1391 qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
1392                          const struct phylink_link_state *state)
1393 {
1394         struct qca8k_priv *priv = ds->priv;
1395         int cpu_port_index, ret;
1396         u32 reg, val;
1397
1398         switch (port) {
1399         case 0: /* 1st CPU port */
1400                 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
1401                     state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
1402                     state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1403                     state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
1404                     state->interface != PHY_INTERFACE_MODE_SGMII)
1405                         return;
1406
1407                 reg = QCA8K_REG_PORT0_PAD_CTRL;
1408                 cpu_port_index = QCA8K_CPU_PORT0;
1409                 break;
1410         case 1:
1411         case 2:
1412         case 3:
1413         case 4:
1414         case 5:
1415                 /* Internal PHY, nothing to do */
1416                 return;
1417         case 6: /* 2nd CPU port / external PHY */
1418                 if (state->interface != PHY_INTERFACE_MODE_RGMII &&
1419                     state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
1420                     state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1421                     state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
1422                     state->interface != PHY_INTERFACE_MODE_SGMII &&
1423                     state->interface != PHY_INTERFACE_MODE_1000BASEX)
1424                         return;
1425
1426                 reg = QCA8K_REG_PORT6_PAD_CTRL;
1427                 cpu_port_index = QCA8K_CPU_PORT6;
1428                 break;
1429         default:
1430                 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
1431                 return;
1432         }
1433
1434         if (port != 6 && phylink_autoneg_inband(mode)) {
1435                 dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
1436                         __func__);
1437                 return;
1438         }
1439
1440         switch (state->interface) {
1441         case PHY_INTERFACE_MODE_RGMII:
1442         case PHY_INTERFACE_MODE_RGMII_ID:
1443         case PHY_INTERFACE_MODE_RGMII_TXID:
1444         case PHY_INTERFACE_MODE_RGMII_RXID:
1445                 qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN);
1446
1447                 /* Configure rgmii delay */
1448                 qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
1449
1450                 /* QCA8337 requires to set rgmii rx delay for all ports.
1451                  * This is enabled through PORT5_PAD_CTRL for all ports,
1452                  * rather than individual port registers.
1453                  */
1454                 if (priv->switch_id == QCA8K_ID_QCA8337)
1455                         qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
1456                                     QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
1457                 break;
1458         case PHY_INTERFACE_MODE_SGMII:
1459         case PHY_INTERFACE_MODE_1000BASEX:
1460                 /* Enable SGMII on the port */
1461                 qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
1462
1463                 /* Enable/disable SerDes auto-negotiation as necessary */
1464                 ret = qca8k_read(priv, QCA8K_REG_PWS, &val);
1465                 if (ret)
1466                         return;
1467                 if (phylink_autoneg_inband(mode))
1468                         val &= ~QCA8K_PWS_SERDES_AEN_DIS;
1469                 else
1470                         val |= QCA8K_PWS_SERDES_AEN_DIS;
1471                 qca8k_write(priv, QCA8K_REG_PWS, val);
1472
1473                 /* Configure the SGMII parameters */
1474                 ret = qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);
1475                 if (ret)
1476                         return;
1477
1478                 val |= QCA8K_SGMII_EN_SD;
1479
1480                 if (priv->ports_config.sgmii_enable_pll)
1481                         val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
1482                                QCA8K_SGMII_EN_TX;
1483
1484                 if (dsa_is_cpu_port(ds, port)) {
1485                         /* CPU port, we're talking to the CPU MAC, be a PHY */
1486                         val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1487                         val |= QCA8K_SGMII_MODE_CTRL_PHY;
1488                 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
1489                         val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1490                         val |= QCA8K_SGMII_MODE_CTRL_MAC;
1491                 } else if (state->interface == PHY_INTERFACE_MODE_1000BASEX) {
1492                         val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
1493                         val |= QCA8K_SGMII_MODE_CTRL_BASEX;
1494                 }
1495
1496                 qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
1497
1498                 /* From original code is reported port instability as SGMII also
1499                  * require delay set. Apply advised values here or take them from DT.
1500                  */
1501                 if (state->interface == PHY_INTERFACE_MODE_SGMII)
1502                         qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
1503
1504                 /* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and
1505                  * falling edge is set writing in the PORT0 PAD reg
1506                  */
1507                 if (priv->switch_id == QCA8K_ID_QCA8327 ||
1508                     priv->switch_id == QCA8K_ID_QCA8337)
1509                         reg = QCA8K_REG_PORT0_PAD_CTRL;
1510
1511                 val = 0;
1512
1513                 /* SGMII Clock phase configuration */
1514                 if (priv->ports_config.sgmii_rx_clk_falling_edge)
1515                         val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
1516
1517                 if (priv->ports_config.sgmii_tx_clk_falling_edge)
1518                         val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
1519
1520                 if (val)
1521                         ret = qca8k_rmw(priv, reg,
1522                                         QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
1523                                         QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
1524                                         val);
1525
1526                 break;
1527         default:
1528                 dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
1529                         phy_modes(state->interface), port);
1530                 return;
1531         }
1532 }
1533
1534 static void
1535 qca8k_phylink_validate(struct dsa_switch *ds, int port,
1536                        unsigned long *supported,
1537                        struct phylink_link_state *state)
1538 {
1539         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1540
1541         switch (port) {
1542         case 0: /* 1st CPU port */
1543                 if (state->interface != PHY_INTERFACE_MODE_NA &&
1544                     state->interface != PHY_INTERFACE_MODE_RGMII &&
1545                     state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
1546                     state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1547                     state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
1548                     state->interface != PHY_INTERFACE_MODE_SGMII)
1549                         goto unsupported;
1550                 break;
1551         case 1:
1552         case 2:
1553         case 3:
1554         case 4:
1555         case 5:
1556                 /* Internal PHY */
1557                 if (state->interface != PHY_INTERFACE_MODE_NA &&
1558                     state->interface != PHY_INTERFACE_MODE_GMII &&
1559                     state->interface != PHY_INTERFACE_MODE_INTERNAL)
1560                         goto unsupported;
1561                 break;
1562         case 6: /* 2nd CPU port / external PHY */
1563                 if (state->interface != PHY_INTERFACE_MODE_NA &&
1564                     state->interface != PHY_INTERFACE_MODE_RGMII &&
1565                     state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
1566                     state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1567                     state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
1568                     state->interface != PHY_INTERFACE_MODE_SGMII &&
1569                     state->interface != PHY_INTERFACE_MODE_1000BASEX)
1570                         goto unsupported;
1571                 break;
1572         default:
1573 unsupported:
1574                 linkmode_zero(supported);
1575                 return;
1576         }
1577
1578         phylink_set_port_modes(mask);
1579         phylink_set(mask, Autoneg);
1580
1581         phylink_set(mask, 1000baseT_Full);
1582         phylink_set(mask, 10baseT_Half);
1583         phylink_set(mask, 10baseT_Full);
1584         phylink_set(mask, 100baseT_Half);
1585         phylink_set(mask, 100baseT_Full);
1586
1587         if (state->interface == PHY_INTERFACE_MODE_1000BASEX)
1588                 phylink_set(mask, 1000baseX_Full);
1589
1590         phylink_set(mask, Pause);
1591         phylink_set(mask, Asym_Pause);
1592
1593         linkmode_and(supported, supported, mask);
1594         linkmode_and(state->advertising, state->advertising, mask);
1595 }
1596
1597 static int
1598 qca8k_phylink_mac_link_state(struct dsa_switch *ds, int port,
1599                              struct phylink_link_state *state)
1600 {
1601         struct qca8k_priv *priv = ds->priv;
1602         u32 reg;
1603         int ret;
1604
1605         ret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), &reg);
1606         if (ret < 0)
1607                 return ret;
1608
1609         state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP);
1610         state->an_complete = state->link;
1611         state->an_enabled = !!(reg & QCA8K_PORT_STATUS_LINK_AUTO);
1612         state->duplex = (reg & QCA8K_PORT_STATUS_DUPLEX) ? DUPLEX_FULL :
1613                                                            DUPLEX_HALF;
1614
1615         switch (reg & QCA8K_PORT_STATUS_SPEED) {
1616         case QCA8K_PORT_STATUS_SPEED_10:
1617                 state->speed = SPEED_10;
1618                 break;
1619         case QCA8K_PORT_STATUS_SPEED_100:
1620                 state->speed = SPEED_100;
1621                 break;
1622         case QCA8K_PORT_STATUS_SPEED_1000:
1623                 state->speed = SPEED_1000;
1624                 break;
1625         default:
1626                 state->speed = SPEED_UNKNOWN;
1627                 break;
1628         }
1629
1630         state->pause = MLO_PAUSE_NONE;
1631         if (reg & QCA8K_PORT_STATUS_RXFLOW)
1632                 state->pause |= MLO_PAUSE_RX;
1633         if (reg & QCA8K_PORT_STATUS_TXFLOW)
1634                 state->pause |= MLO_PAUSE_TX;
1635
1636         return 1;
1637 }
1638
1639 static void
1640 qca8k_phylink_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode,
1641                             phy_interface_t interface)
1642 {
1643         struct qca8k_priv *priv = ds->priv;
1644
1645         qca8k_port_set_status(priv, port, 0);
1646 }
1647
1648 static void
1649 qca8k_phylink_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode,
1650                           phy_interface_t interface, struct phy_device *phydev,
1651                           int speed, int duplex, bool tx_pause, bool rx_pause)
1652 {
1653         struct qca8k_priv *priv = ds->priv;
1654         u32 reg;
1655
1656         if (phylink_autoneg_inband(mode)) {
1657                 reg = QCA8K_PORT_STATUS_LINK_AUTO;
1658         } else {
1659                 switch (speed) {
1660                 case SPEED_10:
1661                         reg = QCA8K_PORT_STATUS_SPEED_10;
1662                         break;
1663                 case SPEED_100:
1664                         reg = QCA8K_PORT_STATUS_SPEED_100;
1665                         break;
1666                 case SPEED_1000:
1667                         reg = QCA8K_PORT_STATUS_SPEED_1000;
1668                         break;
1669                 default:
1670                         reg = QCA8K_PORT_STATUS_LINK_AUTO;
1671                         break;
1672                 }
1673
1674                 if (duplex == DUPLEX_FULL)
1675                         reg |= QCA8K_PORT_STATUS_DUPLEX;
1676
1677                 if (rx_pause || dsa_is_cpu_port(ds, port))
1678                         reg |= QCA8K_PORT_STATUS_RXFLOW;
1679
1680                 if (tx_pause || dsa_is_cpu_port(ds, port))
1681                         reg |= QCA8K_PORT_STATUS_TXFLOW;
1682         }
1683
1684         reg |= QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
1685
1686         qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
1687 }
1688
1689 static void
1690 qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data)
1691 {
1692         const struct qca8k_match_data *match_data;
1693         struct qca8k_priv *priv = ds->priv;
1694         int i;
1695
1696         if (stringset != ETH_SS_STATS)
1697                 return;
1698
1699         match_data = of_device_get_match_data(priv->dev);
1700
1701         for (i = 0; i < match_data->mib_count; i++)
1702                 strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,
1703                         ETH_GSTRING_LEN);
1704 }
1705
1706 static void
1707 qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,
1708                         uint64_t *data)
1709 {
1710         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1711         const struct qca8k_match_data *match_data;
1712         const struct qca8k_mib_desc *mib;
1713         u32 reg, i, val;
1714         u32 hi = 0;
1715         int ret;
1716
1717         match_data = of_device_get_match_data(priv->dev);
1718
1719         for (i = 0; i < match_data->mib_count; i++) {
1720                 mib = &ar8327_mib[i];
1721                 reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;
1722
1723                 ret = qca8k_read(priv, reg, &val);
1724                 if (ret < 0)
1725                         continue;
1726
1727                 if (mib->size == 2) {
1728                         ret = qca8k_read(priv, reg + 4, &hi);
1729                         if (ret < 0)
1730                                 continue;
1731                 }
1732
1733                 data[i] = val;
1734                 if (mib->size == 2)
1735                         data[i] |= (u64)hi << 32;
1736         }
1737 }
1738
1739 static int
1740 qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset)
1741 {
1742         const struct qca8k_match_data *match_data;
1743         struct qca8k_priv *priv = ds->priv;
1744
1745         if (sset != ETH_SS_STATS)
1746                 return 0;
1747
1748         match_data = of_device_get_match_data(priv->dev);
1749
1750         return match_data->mib_count;
1751 }
1752
1753 static int
1754 qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee)
1755 {
1756         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1757         u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port);
1758         u32 reg;
1759         int ret;
1760
1761         mutex_lock(&priv->reg_mutex);
1762         ret = qca8k_read(priv, QCA8K_REG_EEE_CTRL, &reg);
1763         if (ret < 0)
1764                 goto exit;
1765
1766         if (eee->eee_enabled)
1767                 reg |= lpi_en;
1768         else
1769                 reg &= ~lpi_en;
1770         ret = qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
1771
1772 exit:
1773         mutex_unlock(&priv->reg_mutex);
1774         return ret;
1775 }
1776
1777 static int
1778 qca8k_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1779 {
1780         /* Nothing to do on the port's MAC */
1781         return 0;
1782 }
1783
1784 static void
1785 qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1786 {
1787         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1788         u32 stp_state;
1789
1790         switch (state) {
1791         case BR_STATE_DISABLED:
1792                 stp_state = QCA8K_PORT_LOOKUP_STATE_DISABLED;
1793                 break;
1794         case BR_STATE_BLOCKING:
1795                 stp_state = QCA8K_PORT_LOOKUP_STATE_BLOCKING;
1796                 break;
1797         case BR_STATE_LISTENING:
1798                 stp_state = QCA8K_PORT_LOOKUP_STATE_LISTENING;
1799                 break;
1800         case BR_STATE_LEARNING:
1801                 stp_state = QCA8K_PORT_LOOKUP_STATE_LEARNING;
1802                 break;
1803         case BR_STATE_FORWARDING:
1804         default:
1805                 stp_state = QCA8K_PORT_LOOKUP_STATE_FORWARD;
1806                 break;
1807         }
1808
1809         qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1810                   QCA8K_PORT_LOOKUP_STATE_MASK, stp_state);
1811 }
1812
1813 static int qca8k_port_bridge_join(struct dsa_switch *ds, int port,
1814                                   struct dsa_bridge bridge,
1815                                   bool *tx_fwd_offload)
1816 {
1817         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1818         int port_mask, cpu_port;
1819         int i, ret;
1820
1821         cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1822         port_mask = BIT(cpu_port);
1823
1824         for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1825                 if (dsa_is_cpu_port(ds, i))
1826                         continue;
1827                 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1828                         continue;
1829                 /* Add this port to the portvlan mask of the other ports
1830                  * in the bridge
1831                  */
1832                 ret = regmap_set_bits(priv->regmap,
1833                                       QCA8K_PORT_LOOKUP_CTRL(i),
1834                                       BIT(port));
1835                 if (ret)
1836                         return ret;
1837                 if (i != port)
1838                         port_mask |= BIT(i);
1839         }
1840
1841         /* Add all other ports to this ports portvlan mask */
1842         ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1843                         QCA8K_PORT_LOOKUP_MEMBER, port_mask);
1844
1845         return ret;
1846 }
1847
1848 static void qca8k_port_bridge_leave(struct dsa_switch *ds, int port,
1849                                     struct dsa_bridge bridge)
1850 {
1851         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1852         int cpu_port, i;
1853
1854         cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1855
1856         for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1857                 if (dsa_is_cpu_port(ds, i))
1858                         continue;
1859                 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1860                         continue;
1861                 /* Remove this port to the portvlan mask of the other ports
1862                  * in the bridge
1863                  */
1864                 regmap_clear_bits(priv->regmap,
1865                                   QCA8K_PORT_LOOKUP_CTRL(i),
1866                                   BIT(port));
1867         }
1868
1869         /* Set the cpu port to be the only one in the portvlan mask of
1870          * this port
1871          */
1872         qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
1873                   QCA8K_PORT_LOOKUP_MEMBER, BIT(cpu_port));
1874 }
1875
1876 static void
1877 qca8k_port_fast_age(struct dsa_switch *ds, int port)
1878 {
1879         struct qca8k_priv *priv = ds->priv;
1880
1881         mutex_lock(&priv->reg_mutex);
1882         qca8k_fdb_access(priv, QCA8K_FDB_FLUSH_PORT, port);
1883         mutex_unlock(&priv->reg_mutex);
1884 }
1885
1886 static int
1887 qca8k_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
1888 {
1889         struct qca8k_priv *priv = ds->priv;
1890         unsigned int secs = msecs / 1000;
1891         u32 val;
1892
1893         /* AGE_TIME reg is set in 7s step */
1894         val = secs / 7;
1895
1896         /* Handle case with 0 as val to NOT disable
1897          * learning
1898          */
1899         if (!val)
1900                 val = 1;
1901
1902         return regmap_update_bits(priv->regmap, QCA8K_REG_ATU_CTRL, QCA8K_ATU_AGE_TIME_MASK,
1903                                   QCA8K_ATU_AGE_TIME(val));
1904 }
1905
1906 static int
1907 qca8k_port_enable(struct dsa_switch *ds, int port,
1908                   struct phy_device *phy)
1909 {
1910         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1911
1912         qca8k_port_set_status(priv, port, 1);
1913         priv->port_sts[port].enabled = 1;
1914
1915         if (dsa_is_user_port(ds, port))
1916                 phy_support_asym_pause(phy);
1917
1918         return 0;
1919 }
1920
1921 static void
1922 qca8k_port_disable(struct dsa_switch *ds, int port)
1923 {
1924         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1925
1926         qca8k_port_set_status(priv, port, 0);
1927         priv->port_sts[port].enabled = 0;
1928 }
1929
1930 static int
1931 qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1932 {
1933         struct qca8k_priv *priv = ds->priv;
1934         int i, mtu = 0;
1935
1936         priv->port_mtu[port] = new_mtu;
1937
1938         for (i = 0; i < QCA8K_NUM_PORTS; i++)
1939                 if (priv->port_mtu[i] > mtu)
1940                         mtu = priv->port_mtu[i];
1941
1942         /* Include L2 header / FCS length */
1943         return qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, mtu + ETH_HLEN + ETH_FCS_LEN);
1944 }
1945
1946 static int
1947 qca8k_port_max_mtu(struct dsa_switch *ds, int port)
1948 {
1949         return QCA8K_MAX_MTU;
1950 }
1951
1952 static int
1953 qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr,
1954                       u16 port_mask, u16 vid)
1955 {
1956         /* Set the vid to the port vlan id if no vid is set */
1957         if (!vid)
1958                 vid = QCA8K_PORT_VID_DEF;
1959
1960         return qca8k_fdb_add(priv, addr, port_mask, vid,
1961                              QCA8K_ATU_STATUS_STATIC);
1962 }
1963
1964 static int
1965 qca8k_port_fdb_add(struct dsa_switch *ds, int port,
1966                    const unsigned char *addr, u16 vid)
1967 {
1968         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1969         u16 port_mask = BIT(port);
1970
1971         return qca8k_port_fdb_insert(priv, addr, port_mask, vid);
1972 }
1973
1974 static int
1975 qca8k_port_fdb_del(struct dsa_switch *ds, int port,
1976                    const unsigned char *addr, u16 vid)
1977 {
1978         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1979         u16 port_mask = BIT(port);
1980
1981         if (!vid)
1982                 vid = QCA8K_PORT_VID_DEF;
1983
1984         return qca8k_fdb_del(priv, addr, port_mask, vid);
1985 }
1986
1987 static int
1988 qca8k_port_fdb_dump(struct dsa_switch *ds, int port,
1989                     dsa_fdb_dump_cb_t *cb, void *data)
1990 {
1991         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1992         struct qca8k_fdb _fdb = { 0 };
1993         int cnt = QCA8K_NUM_FDB_RECORDS;
1994         bool is_static;
1995         int ret = 0;
1996
1997         mutex_lock(&priv->reg_mutex);
1998         while (cnt-- && !qca8k_fdb_next(priv, &_fdb, port)) {
1999                 if (!_fdb.aging)
2000                         break;
2001                 is_static = (_fdb.aging == QCA8K_ATU_STATUS_STATIC);
2002                 ret = cb(_fdb.mac, _fdb.vid, is_static, data);
2003                 if (ret)
2004                         break;
2005         }
2006         mutex_unlock(&priv->reg_mutex);
2007
2008         return 0;
2009 }
2010
2011 static int
2012 qca8k_port_mdb_add(struct dsa_switch *ds, int port,
2013                    const struct switchdev_obj_port_mdb *mdb)
2014 {
2015         struct qca8k_priv *priv = ds->priv;
2016         const u8 *addr = mdb->addr;
2017         u16 vid = mdb->vid;
2018
2019         return qca8k_fdb_search_and_insert(priv, BIT(port), addr, vid);
2020 }
2021
2022 static int
2023 qca8k_port_mdb_del(struct dsa_switch *ds, int port,
2024                    const struct switchdev_obj_port_mdb *mdb)
2025 {
2026         struct qca8k_priv *priv = ds->priv;
2027         const u8 *addr = mdb->addr;
2028         u16 vid = mdb->vid;
2029
2030         return qca8k_fdb_search_and_del(priv, BIT(port), addr, vid);
2031 }
2032
2033 static int
2034 qca8k_port_mirror_add(struct dsa_switch *ds, int port,
2035                       struct dsa_mall_mirror_tc_entry *mirror,
2036                       bool ingress)
2037 {
2038         struct qca8k_priv *priv = ds->priv;
2039         int monitor_port, ret;
2040         u32 reg, val;
2041
2042         /* Check for existent entry */
2043         if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
2044                 return -EEXIST;
2045
2046         ret = regmap_read(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0, &val);
2047         if (ret)
2048                 return ret;
2049
2050         /* QCA83xx can have only one port set to mirror mode.
2051          * Check that the correct port is requested and return error otherwise.
2052          * When no mirror port is set, the values is set to 0xF
2053          */
2054         monitor_port = FIELD_GET(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val);
2055         if (monitor_port != 0xF && monitor_port != mirror->to_local_port)
2056                 return -EEXIST;
2057
2058         /* Set the monitor port */
2059         val = FIELD_PREP(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM,
2060                          mirror->to_local_port);
2061         ret = regmap_update_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
2062                                  QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val);
2063         if (ret)
2064                 return ret;
2065
2066         if (ingress) {
2067                 reg = QCA8K_PORT_LOOKUP_CTRL(port);
2068                 val = QCA8K_PORT_LOOKUP_ING_MIRROR_EN;
2069         } else {
2070                 reg = QCA8K_REG_PORT_HOL_CTRL1(port);
2071                 val = QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN;
2072         }
2073
2074         ret = regmap_update_bits(priv->regmap, reg, val, val);
2075         if (ret)
2076                 return ret;
2077
2078         /* Track mirror port for tx and rx to decide when the
2079          * mirror port has to be disabled.
2080          */
2081         if (ingress)
2082                 priv->mirror_rx |= BIT(port);
2083         else
2084                 priv->mirror_tx |= BIT(port);
2085
2086         return 0;
2087 }
2088
2089 static void
2090 qca8k_port_mirror_del(struct dsa_switch *ds, int port,
2091                       struct dsa_mall_mirror_tc_entry *mirror)
2092 {
2093         struct qca8k_priv *priv = ds->priv;
2094         u32 reg, val;
2095         int ret;
2096
2097         if (mirror->ingress) {
2098                 reg = QCA8K_PORT_LOOKUP_CTRL(port);
2099                 val = QCA8K_PORT_LOOKUP_ING_MIRROR_EN;
2100         } else {
2101                 reg = QCA8K_REG_PORT_HOL_CTRL1(port);
2102                 val = QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN;
2103         }
2104
2105         ret = regmap_clear_bits(priv->regmap, reg, val);
2106         if (ret)
2107                 goto err;
2108
2109         if (mirror->ingress)
2110                 priv->mirror_rx &= ~BIT(port);
2111         else
2112                 priv->mirror_tx &= ~BIT(port);
2113
2114         /* No port set to send packet to mirror port. Disable mirror port */
2115         if (!priv->mirror_rx && !priv->mirror_tx) {
2116                 val = FIELD_PREP(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, 0xF);
2117                 ret = regmap_update_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
2118                                          QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val);
2119                 if (ret)
2120                         goto err;
2121         }
2122 err:
2123         dev_err(priv->dev, "Failed to del mirror port from %d", port);
2124 }
2125
2126 static int
2127 qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
2128                           struct netlink_ext_ack *extack)
2129 {
2130         struct qca8k_priv *priv = ds->priv;
2131         int ret;
2132
2133         if (vlan_filtering) {
2134                 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
2135                                 QCA8K_PORT_LOOKUP_VLAN_MODE_MASK,
2136                                 QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE);
2137         } else {
2138                 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
2139                                 QCA8K_PORT_LOOKUP_VLAN_MODE_MASK,
2140                                 QCA8K_PORT_LOOKUP_VLAN_MODE_NONE);
2141         }
2142
2143         return ret;
2144 }
2145
2146 static int
2147 qca8k_port_vlan_add(struct dsa_switch *ds, int port,
2148                     const struct switchdev_obj_port_vlan *vlan,
2149                     struct netlink_ext_ack *extack)
2150 {
2151         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2152         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2153         struct qca8k_priv *priv = ds->priv;
2154         int ret;
2155
2156         ret = qca8k_vlan_add(priv, port, vlan->vid, untagged);
2157         if (ret) {
2158                 dev_err(priv->dev, "Failed to add VLAN to port %d (%d)", port, ret);
2159                 return ret;
2160         }
2161
2162         if (pvid) {
2163                 ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),
2164                                 QCA8K_EGREES_VLAN_PORT_MASK(port),
2165                                 QCA8K_EGREES_VLAN_PORT(port, vlan->vid));
2166                 if (ret)
2167                         return ret;
2168
2169                 ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port),
2170                                   QCA8K_PORT_VLAN_CVID(vlan->vid) |
2171                                   QCA8K_PORT_VLAN_SVID(vlan->vid));
2172         }
2173
2174         return ret;
2175 }
2176
2177 static int
2178 qca8k_port_vlan_del(struct dsa_switch *ds, int port,
2179                     const struct switchdev_obj_port_vlan *vlan)
2180 {
2181         struct qca8k_priv *priv = ds->priv;
2182         int ret;
2183
2184         ret = qca8k_vlan_del(priv, port, vlan->vid);
2185         if (ret)
2186                 dev_err(priv->dev, "Failed to delete VLAN from port %d (%d)", port, ret);
2187
2188         return ret;
2189 }
2190
2191 static u32 qca8k_get_phy_flags(struct dsa_switch *ds, int port)
2192 {
2193         struct qca8k_priv *priv = ds->priv;
2194
2195         /* Communicate to the phy internal driver the switch revision.
2196          * Based on the switch revision different values needs to be
2197          * set to the dbg and mmd reg on the phy.
2198          * The first 2 bit are used to communicate the switch revision
2199          * to the phy driver.
2200          */
2201         if (port > 0 && port < 6)
2202                 return priv->switch_revision;
2203
2204         return 0;
2205 }
2206
2207 static enum dsa_tag_protocol
2208 qca8k_get_tag_protocol(struct dsa_switch *ds, int port,
2209                        enum dsa_tag_protocol mp)
2210 {
2211         return DSA_TAG_PROTO_QCA;
2212 }
2213
2214 static bool
2215 qca8k_lag_can_offload(struct dsa_switch *ds,
2216                       struct net_device *lag,
2217                       struct netdev_lag_upper_info *info)
2218 {
2219         struct dsa_port *dp;
2220         int id, members = 0;
2221
2222         id = dsa_lag_id(ds->dst, lag);
2223         if (id < 0 || id >= ds->num_lag_ids)
2224                 return false;
2225
2226         dsa_lag_foreach_port(dp, ds->dst, lag)
2227                 /* Includes the port joining the LAG */
2228                 members++;
2229
2230         if (members > QCA8K_NUM_PORTS_FOR_LAG)
2231                 return false;
2232
2233         if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
2234                 return false;
2235
2236         if (info->hash_type != NETDEV_LAG_HASH_L2 &&
2237             info->hash_type != NETDEV_LAG_HASH_L23)
2238                 return false;
2239
2240         return true;
2241 }
2242
2243 static int
2244 qca8k_lag_setup_hash(struct dsa_switch *ds,
2245                      struct net_device *lag,
2246                      struct netdev_lag_upper_info *info)
2247 {
2248         struct qca8k_priv *priv = ds->priv;
2249         bool unique_lag = true;
2250         u32 hash = 0;
2251         int i, id;
2252
2253         id = dsa_lag_id(ds->dst, lag);
2254
2255         switch (info->hash_type) {
2256         case NETDEV_LAG_HASH_L23:
2257                 hash |= QCA8K_TRUNK_HASH_SIP_EN;
2258                 hash |= QCA8K_TRUNK_HASH_DIP_EN;
2259                 fallthrough;
2260         case NETDEV_LAG_HASH_L2:
2261                 hash |= QCA8K_TRUNK_HASH_SA_EN;
2262                 hash |= QCA8K_TRUNK_HASH_DA_EN;
2263                 break;
2264         default: /* We should NEVER reach this */
2265                 return -EOPNOTSUPP;
2266         }
2267
2268         /* Check if we are the unique configured LAG */
2269         dsa_lags_foreach_id(i, ds->dst)
2270                 if (i != id && dsa_lag_dev(ds->dst, i)) {
2271                         unique_lag = false;
2272                         break;
2273                 }
2274
2275         /* Hash Mode is global. Make sure the same Hash Mode
2276          * is set to all the 4 possible lag.
2277          * If we are the unique LAG we can set whatever hash
2278          * mode we want.
2279          * To change hash mode it's needed to remove all LAG
2280          * and change the mode with the latest.
2281          */
2282         if (unique_lag) {
2283                 priv->lag_hash_mode = hash;
2284         } else if (priv->lag_hash_mode != hash) {
2285                 netdev_err(lag, "Error: Mismatched Hash Mode across different lag is not supported\n");
2286                 return -EOPNOTSUPP;
2287         }
2288
2289         return regmap_update_bits(priv->regmap, QCA8K_TRUNK_HASH_EN_CTRL,
2290                                   QCA8K_TRUNK_HASH_MASK, hash);
2291 }
2292
2293 static int
2294 qca8k_lag_refresh_portmap(struct dsa_switch *ds, int port,
2295                           struct net_device *lag, bool delete)
2296 {
2297         struct qca8k_priv *priv = ds->priv;
2298         int ret, id, i;
2299         u32 val;
2300
2301         id = dsa_lag_id(ds->dst, lag);
2302
2303         /* Read current port member */
2304         ret = regmap_read(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL0, &val);
2305         if (ret)
2306                 return ret;
2307
2308         /* Shift val to the correct trunk */
2309         val >>= QCA8K_REG_GOL_TRUNK_SHIFT(id);
2310         val &= QCA8K_REG_GOL_TRUNK_MEMBER_MASK;
2311         if (delete)
2312                 val &= ~BIT(port);
2313         else
2314                 val |= BIT(port);
2315
2316         /* Update port member. With empty portmap disable trunk */
2317         ret = regmap_update_bits(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL0,
2318                                  QCA8K_REG_GOL_TRUNK_MEMBER(id) |
2319                                  QCA8K_REG_GOL_TRUNK_EN(id),
2320                                  !val << QCA8K_REG_GOL_TRUNK_SHIFT(id) |
2321                                  val << QCA8K_REG_GOL_TRUNK_SHIFT(id));
2322
2323         /* Search empty member if adding or port on deleting */
2324         for (i = 0; i < QCA8K_NUM_PORTS_FOR_LAG; i++) {
2325                 ret = regmap_read(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL(id), &val);
2326                 if (ret)
2327                         return ret;
2328
2329                 val >>= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i);
2330                 val &= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_MASK;
2331
2332                 if (delete) {
2333                         /* If port flagged to be disabled assume this member is
2334                          * empty
2335                          */
2336                         if (val != QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK)
2337                                 continue;
2338
2339                         val &= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK;
2340                         if (val != port)
2341                                 continue;
2342                 } else {
2343                         /* If port flagged to be enabled assume this member is
2344                          * already set
2345                          */
2346                         if (val == QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK)
2347                                 continue;
2348                 }
2349
2350                 /* We have found the member to add/remove */
2351                 break;
2352         }
2353
2354         /* Set port in the correct port mask or disable port if in delete mode */
2355         return regmap_update_bits(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL(id),
2356                                   QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN(id, i) |
2357                                   QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT(id, i),
2358                                   !delete << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i) |
2359                                   port << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i));
2360 }
2361
2362 static int
2363 qca8k_port_lag_join(struct dsa_switch *ds, int port,
2364                     struct net_device *lag,
2365                     struct netdev_lag_upper_info *info)
2366 {
2367         int ret;
2368
2369         if (!qca8k_lag_can_offload(ds, lag, info))
2370                 return -EOPNOTSUPP;
2371
2372         ret = qca8k_lag_setup_hash(ds, lag, info);
2373         if (ret)
2374                 return ret;
2375
2376         return qca8k_lag_refresh_portmap(ds, port, lag, false);
2377 }
2378
2379 static int
2380 qca8k_port_lag_leave(struct dsa_switch *ds, int port,
2381                      struct net_device *lag)
2382 {
2383         return qca8k_lag_refresh_portmap(ds, port, lag, true);
2384 }
2385
2386 static const struct dsa_switch_ops qca8k_switch_ops = {
2387         .get_tag_protocol       = qca8k_get_tag_protocol,
2388         .setup                  = qca8k_setup,
2389         .get_strings            = qca8k_get_strings,
2390         .get_ethtool_stats      = qca8k_get_ethtool_stats,
2391         .get_sset_count         = qca8k_get_sset_count,
2392         .set_ageing_time        = qca8k_set_ageing_time,
2393         .get_mac_eee            = qca8k_get_mac_eee,
2394         .set_mac_eee            = qca8k_set_mac_eee,
2395         .port_enable            = qca8k_port_enable,
2396         .port_disable           = qca8k_port_disable,
2397         .port_change_mtu        = qca8k_port_change_mtu,
2398         .port_max_mtu           = qca8k_port_max_mtu,
2399         .port_stp_state_set     = qca8k_port_stp_state_set,
2400         .port_bridge_join       = qca8k_port_bridge_join,
2401         .port_bridge_leave      = qca8k_port_bridge_leave,
2402         .port_fast_age          = qca8k_port_fast_age,
2403         .port_fdb_add           = qca8k_port_fdb_add,
2404         .port_fdb_del           = qca8k_port_fdb_del,
2405         .port_fdb_dump          = qca8k_port_fdb_dump,
2406         .port_mdb_add           = qca8k_port_mdb_add,
2407         .port_mdb_del           = qca8k_port_mdb_del,
2408         .port_mirror_add        = qca8k_port_mirror_add,
2409         .port_mirror_del        = qca8k_port_mirror_del,
2410         .port_vlan_filtering    = qca8k_port_vlan_filtering,
2411         .port_vlan_add          = qca8k_port_vlan_add,
2412         .port_vlan_del          = qca8k_port_vlan_del,
2413         .phylink_validate       = qca8k_phylink_validate,
2414         .phylink_mac_link_state = qca8k_phylink_mac_link_state,
2415         .phylink_mac_config     = qca8k_phylink_mac_config,
2416         .phylink_mac_link_down  = qca8k_phylink_mac_link_down,
2417         .phylink_mac_link_up    = qca8k_phylink_mac_link_up,
2418         .get_phy_flags          = qca8k_get_phy_flags,
2419         .port_lag_join          = qca8k_port_lag_join,
2420         .port_lag_leave         = qca8k_port_lag_leave,
2421 };
2422
2423 static int qca8k_read_switch_id(struct qca8k_priv *priv)
2424 {
2425         const struct qca8k_match_data *data;
2426         u32 val;
2427         u8 id;
2428         int ret;
2429
2430         /* get the switches ID from the compatible */
2431         data = of_device_get_match_data(priv->dev);
2432         if (!data)
2433                 return -ENODEV;
2434
2435         ret = qca8k_read(priv, QCA8K_REG_MASK_CTRL, &val);
2436         if (ret < 0)
2437                 return -ENODEV;
2438
2439         id = QCA8K_MASK_CTRL_DEVICE_ID(val);
2440         if (id != data->id) {
2441                 dev_err(priv->dev, "Switch id detected %x but expected %x", id, data->id);
2442                 return -ENODEV;
2443         }
2444
2445         priv->switch_id = id;
2446
2447         /* Save revision to communicate to the internal PHY driver */
2448         priv->switch_revision = QCA8K_MASK_CTRL_REV_ID(val);
2449
2450         return 0;
2451 }
2452
2453 static int
2454 qca8k_sw_probe(struct mdio_device *mdiodev)
2455 {
2456         struct qca8k_priv *priv;
2457         int ret;
2458
2459         /* allocate the private data struct so that we can probe the switches
2460          * ID register
2461          */
2462         priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
2463         if (!priv)
2464                 return -ENOMEM;
2465
2466         priv->bus = mdiodev->bus;
2467         priv->dev = &mdiodev->dev;
2468
2469         priv->reset_gpio = devm_gpiod_get_optional(priv->dev, "reset",
2470                                                    GPIOD_ASIS);
2471         if (IS_ERR(priv->reset_gpio))
2472                 return PTR_ERR(priv->reset_gpio);
2473
2474         if (priv->reset_gpio) {
2475                 gpiod_set_value_cansleep(priv->reset_gpio, 1);
2476                 /* The active low duration must be greater than 10 ms
2477                  * and checkpatch.pl wants 20 ms.
2478                  */
2479                 msleep(20);
2480                 gpiod_set_value_cansleep(priv->reset_gpio, 0);
2481         }
2482
2483         /* Start by setting up the register mapping */
2484         priv->regmap = devm_regmap_init(&mdiodev->dev, NULL, priv,
2485                                         &qca8k_regmap_config);
2486         if (IS_ERR(priv->regmap)) {
2487                 dev_err(priv->dev, "regmap initialization failed");
2488                 return PTR_ERR(priv->regmap);
2489         }
2490
2491         /* Check the detected switch id */
2492         ret = qca8k_read_switch_id(priv);
2493         if (ret)
2494                 return ret;
2495
2496         priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
2497         if (!priv->ds)
2498                 return -ENOMEM;
2499
2500         priv->ds->dev = &mdiodev->dev;
2501         priv->ds->num_ports = QCA8K_NUM_PORTS;
2502         priv->ds->priv = priv;
2503         priv->ops = qca8k_switch_ops;
2504         priv->ds->ops = &priv->ops;
2505         mutex_init(&priv->reg_mutex);
2506         dev_set_drvdata(&mdiodev->dev, priv);
2507
2508         return dsa_register_switch(priv->ds);
2509 }
2510
2511 static void
2512 qca8k_sw_remove(struct mdio_device *mdiodev)
2513 {
2514         struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
2515         int i;
2516
2517         if (!priv)
2518                 return;
2519
2520         for (i = 0; i < QCA8K_NUM_PORTS; i++)
2521                 qca8k_port_set_status(priv, i, 0);
2522
2523         dsa_unregister_switch(priv->ds);
2524
2525         dev_set_drvdata(&mdiodev->dev, NULL);
2526 }
2527
2528 static void qca8k_sw_shutdown(struct mdio_device *mdiodev)
2529 {
2530         struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
2531
2532         if (!priv)
2533                 return;
2534
2535         dsa_switch_shutdown(priv->ds);
2536
2537         dev_set_drvdata(&mdiodev->dev, NULL);
2538 }
2539
2540 #ifdef CONFIG_PM_SLEEP
2541 static void
2542 qca8k_set_pm(struct qca8k_priv *priv, int enable)
2543 {
2544         int i;
2545
2546         for (i = 0; i < QCA8K_NUM_PORTS; i++) {
2547                 if (!priv->port_sts[i].enabled)
2548                         continue;
2549
2550                 qca8k_port_set_status(priv, i, enable);
2551         }
2552 }
2553
2554 static int qca8k_suspend(struct device *dev)
2555 {
2556         struct qca8k_priv *priv = dev_get_drvdata(dev);
2557
2558         qca8k_set_pm(priv, 0);
2559
2560         return dsa_switch_suspend(priv->ds);
2561 }
2562
2563 static int qca8k_resume(struct device *dev)
2564 {
2565         struct qca8k_priv *priv = dev_get_drvdata(dev);
2566
2567         qca8k_set_pm(priv, 1);
2568
2569         return dsa_switch_resume(priv->ds);
2570 }
2571 #endif /* CONFIG_PM_SLEEP */
2572
2573 static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
2574                          qca8k_suspend, qca8k_resume);
2575
2576 static const struct qca8k_match_data qca8327 = {
2577         .id = QCA8K_ID_QCA8327,
2578         .reduced_package = true,
2579         .mib_count = QCA8K_QCA832X_MIB_COUNT,
2580 };
2581
2582 static const struct qca8k_match_data qca8328 = {
2583         .id = QCA8K_ID_QCA8327,
2584         .mib_count = QCA8K_QCA832X_MIB_COUNT,
2585 };
2586
2587 static const struct qca8k_match_data qca833x = {
2588         .id = QCA8K_ID_QCA8337,
2589         .mib_count = QCA8K_QCA833X_MIB_COUNT,
2590 };
2591
2592 static const struct of_device_id qca8k_of_match[] = {
2593         { .compatible = "qca,qca8327", .data = &qca8327 },
2594         { .compatible = "qca,qca8328", .data = &qca8328 },
2595         { .compatible = "qca,qca8334", .data = &qca833x },
2596         { .compatible = "qca,qca8337", .data = &qca833x },
2597         { /* sentinel */ },
2598 };
2599
2600 static struct mdio_driver qca8kmdio_driver = {
2601         .probe  = qca8k_sw_probe,
2602         .remove = qca8k_sw_remove,
2603         .shutdown = qca8k_sw_shutdown,
2604         .mdiodrv.driver = {
2605                 .name = "qca8k",
2606                 .of_match_table = qca8k_of_match,
2607                 .pm = &qca8k_pm_ops,
2608         },
2609 };
2610
2611 mdio_module_driver(qca8kmdio_driver);
2612
2613 MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
2614 MODULE_DESCRIPTION("Driver for QCA8K ethernet switch family");
2615 MODULE_LICENSE("GPL v2");
2616 MODULE_ALIAS("platform:qca8k");