drivers/net/dsa/sja1105/sja1105_main.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
   3  * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
   4  */
   5
   6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   7
   8 #include <linux/delay.h>
   9 #include <linux/module.h>
  10 #include <linux/printk.h>
  11 #include <linux/spi/spi.h>
  12 #include <linux/errno.h>
  13 #include <linux/gpio/consumer.h>
  14 #include <linux/phylink.h>
  15 #include <linux/of.h>
  16 #include <linux/of_net.h>
  17 #include <linux/of_mdio.h>
  18 #include <linux/of_device.h>
  19 #include <linux/pcs/pcs-xpcs.h>
  20 #include <linux/netdev_features.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/if_bridge.h>
  23 #include <linux/if_ether.h>
  24 #include <linux/dsa/8021q.h>
  25 #include "sja1105.h"
  26 #include "sja1105_tas.h"
  27
  28 #define SJA1105_UNKNOWN_MULTICAST       0x010000000000ull
  29
  30 /* Configure the optional reset pin and bring up switch */
  31 static int sja1105_hw_reset(struct device *dev, unsigned int pulse_len,
  32                             unsigned int startup_delay)
  33 {
  34         struct gpio_desc *gpio;
  35
  36         gpio = gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
  37         if (IS_ERR(gpio))
  38                 return PTR_ERR(gpio);
  39
  40         if (!gpio)
  41                 return 0;
  42
  43         gpiod_set_value_cansleep(gpio, 1);
  44         /* Wait for minimum reset pulse length */
  45         msleep(pulse_len);
  46         gpiod_set_value_cansleep(gpio, 0);
  47         /* Wait until chip is ready after reset */
  48         msleep(startup_delay);
  49
  50         gpiod_put(gpio);
  51
  52         return 0;
  53 }
  54
  55 static void
  56 sja1105_port_allow_traffic(struct sja1105_l2_forwarding_entry *l2_fwd,
  57                            int from, int to, bool allow)
  58 {
  59         if (allow)
  60                 l2_fwd[from].reach_port |= BIT(to);
  61         else
  62                 l2_fwd[from].reach_port &= ~BIT(to);
  63 }
  64
  65 static bool sja1105_can_forward(struct sja1105_l2_forwarding_entry *l2_fwd,
  66                                 int from, int to)
  67 {
  68         return !!(l2_fwd[from].reach_port & BIT(to));
  69 }
  70
  71 static int sja1105_is_vlan_configured(struct sja1105_private *priv, u16 vid)
  72 {
  73         struct sja1105_vlan_lookup_entry *vlan;
  74         int count, i;
  75
  76         vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries;
  77         count = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entry_count;
  78
  79         for (i = 0; i < count; i++)
  80                 if (vlan[i].vlanid == vid)
  81                         return i;
  82
  83         /* Return an invalid entry index if not found */
  84         return -1;
  85 }
  86
  87 static int sja1105_drop_untagged(struct dsa_switch *ds, int port, bool drop)
  88 {
  89         struct sja1105_private *priv = ds->priv;
  90         struct sja1105_mac_config_entry *mac;
  91
  92         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
  93
  94         if (mac[port].drpuntag == drop)
  95                 return 0;
  96
  97         mac[port].drpuntag = drop;
  98
  99         return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
 100                                             &mac[port], true);
 101 }
 102
 103 static int sja1105_pvid_apply(struct sja1105_private *priv, int port, u16 pvid)
 104 {
 105         struct sja1105_mac_config_entry *mac;
 106
 107         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
 108
 109         if (mac[port].vlanid == pvid)
 110                 return 0;
 111
 112         mac[port].vlanid = pvid;
 113
 114         return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
 115                                             &mac[port], true);
 116 }
 117
 118 static int sja1105_commit_pvid(struct dsa_switch *ds, int port)
 119 {
 120         struct dsa_port *dp = dsa_to_port(ds, port);
 121         struct net_device *br = dsa_port_bridge_dev_get(dp);
 122         struct sja1105_private *priv = ds->priv;
 123         struct sja1105_vlan_lookup_entry *vlan;
 124         bool drop_untagged = false;
 125         int match, rc;
 126         u16 pvid;
 127
 128         if (br && br_vlan_enabled(br))
 129                 pvid = priv->bridge_pvid[port];
 130         else
 131                 pvid = priv->tag_8021q_pvid[port];
 132
 133         rc = sja1105_pvid_apply(priv, port, pvid);
 134         if (rc)
 135                 return rc;
 136
 137         /* Only force dropping of untagged packets when the port is under a
 138          * VLAN-aware bridge. When the tag_8021q pvid is used, we are
 139          * deliberately removing the RX VLAN from the port's VMEMB_PORT list,
 140          * to prevent DSA tag spoofing from the link partner. Untagged packets
 141          * are the only ones that should be received with tag_8021q, so
 142          * definitely don't drop them.
 143          */
 144         if (pvid == priv->bridge_pvid[port]) {
 145                 vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries;
 146
 147                 match = sja1105_is_vlan_configured(priv, pvid);
 148
 149                 if (match < 0 || !(vlan[match].vmemb_port & BIT(port)))
 150                         drop_untagged = true;
 151         }
 152
 153         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
 154                 drop_untagged = true;
 155
 156         return sja1105_drop_untagged(ds, port, drop_untagged);
 157 }
 158
 159 static int sja1105_init_mac_settings(struct sja1105_private *priv)
 160 {
 161         struct sja1105_mac_config_entry default_mac = {
 162                 /* Enable all 8 priority queues on egress.
 163                  * Every queue i holds top[i] - base[i] frames.
 164                  * Sum of top[i] - base[i] is 511 (max hardware limit).
 165                  */
 166                 .top  = {0x3F, 0x7F, 0xBF, 0xFF, 0x13F, 0x17F, 0x1BF, 0x1FF},
 167                 .base = {0x0, 0x40, 0x80, 0xC0, 0x100, 0x140, 0x180, 0x1C0},
 168                 .enabled = {true, true, true, true, true, true, true, true},
 169                 /* Keep standard IFG of 12 bytes on egress. */
 170                 .ifg = 0,
 171                 /* Always put the MAC speed in automatic mode, where it can be
 172                  * adjusted at runtime by PHYLINK.
 173                  */
 174                 .speed = priv->info->port_speed[SJA1105_SPEED_AUTO],
 175                 /* No static correction for 1-step 1588 events */
 176                 .tp_delin = 0,
 177                 .tp_delout = 0,
 178                 /* Disable aging for critical TTEthernet traffic */
 179                 .maxage = 0xFF,
 180                 /* Internal VLAN (pvid) to apply to untagged ingress */
 181                 .vlanprio = 0,
 182                 .vlanid = 1,
 183                 .ing_mirr = false,
 184                 .egr_mirr = false,
 185                 /* Don't drop traffic with other EtherType than ETH_P_IP */
 186                 .drpnona664 = false,
 187                 /* Don't drop double-tagged traffic */
 188                 .drpdtag = false,
 189                 /* Don't drop untagged traffic */
 190                 .drpuntag = false,
 191                 /* Don't retag 802.1p (VID 0) traffic with the pvid */
 192                 .retag = false,
 193                 /* Disable learning and I/O on user ports by default -
 194                  * STP will enable it.
 195                  */
 196                 .dyn_learn = false,
 197                 .egress = false,
 198                 .ingress = false,
 199         };
 200         struct sja1105_mac_config_entry *mac;
 201         struct dsa_switch *ds = priv->ds;
 202         struct sja1105_table *table;
 203         struct dsa_port *dp;
 204
 205         table = &priv->static_config.tables[BLK_IDX_MAC_CONFIG];
 206
 207         /* Discard previous MAC Configuration Table */
 208         if (table->entry_count) {
 209                 kfree(table->entries);
 210                 table->entry_count = 0;
 211         }
 212
 213         table->entries = kcalloc(table->ops->max_entry_count,
 214                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 215         if (!table->entries)
 216                 return -ENOMEM;
 217
 218         table->entry_count = table->ops->max_entry_count;
 219
 220         mac = table->entries;
 221
 222         list_for_each_entry(dp, &ds->dst->ports, list) {
 223                 if (dp->ds != ds)
 224                         continue;
 225
 226                 mac[dp->index] = default_mac;
 227
 228                 /* Let sja1105_bridge_stp_state_set() keep address learning
 229                  * enabled for the DSA ports. CPU ports use software-assisted
 230                  * learning to ensure that only FDB entries belonging to the
 231                  * bridge are learned, and that they are learned towards all
 232                  * CPU ports in a cross-chip topology if multiple CPU ports
 233                  * exist.
 234                  */
 235                 if (dsa_port_is_dsa(dp))
 236                         dp->learning = true;
 237
 238                 /* Disallow untagged packets from being received on the
 239                  * CPU and DSA ports.
 240                  */
 241                 if (dsa_port_is_cpu(dp) || dsa_port_is_dsa(dp))
 242                         mac[dp->index].drpuntag = true;
 243         }
 244
 245         return 0;
 246 }
 247
 248 static int sja1105_init_mii_settings(struct sja1105_private *priv)
 249 {
 250         struct device *dev = &priv->spidev->dev;
 251         struct sja1105_xmii_params_entry *mii;
 252         struct dsa_switch *ds = priv->ds;
 253         struct sja1105_table *table;
 254         int i;
 255
 256         table = &priv->static_config.tables[BLK_IDX_XMII_PARAMS];
 257
 258         /* Discard previous xMII Mode Parameters Table */
 259         if (table->entry_count) {
 260                 kfree(table->entries);
 261                 table->entry_count = 0;
 262         }
 263
 264         table->entries = kcalloc(table->ops->max_entry_count,
 265                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 266         if (!table->entries)
 267                 return -ENOMEM;
 268
 269         /* Override table based on PHYLINK DT bindings */
 270         table->entry_count = table->ops->max_entry_count;
 271
 272         mii = table->entries;
 273
 274         for (i = 0; i < ds->num_ports; i++) {
 275                 sja1105_mii_role_t role = XMII_MAC;
 276
 277                 if (dsa_is_unused_port(priv->ds, i))
 278                         continue;
 279
 280                 switch (priv->phy_mode[i]) {
 281                 case PHY_INTERFACE_MODE_INTERNAL:
 282                         if (priv->info->internal_phy[i] == SJA1105_NO_PHY)
 283                                 goto unsupported;
 284
 285                         mii->xmii_mode[i] = XMII_MODE_MII;
 286                         if (priv->info->internal_phy[i] == SJA1105_PHY_BASE_TX)
 287                                 mii->special[i] = true;
 288
 289                         break;
 290                 case PHY_INTERFACE_MODE_REVMII:
 291                         role = XMII_PHY;
 292                         fallthrough;
 293                 case PHY_INTERFACE_MODE_MII:
 294                         if (!priv->info->supports_mii[i])
 295                                 goto unsupported;
 296
 297                         mii->xmii_mode[i] = XMII_MODE_MII;
 298                         break;
 299                 case PHY_INTERFACE_MODE_REVRMII:
 300                         role = XMII_PHY;
 301                         fallthrough;
 302                 case PHY_INTERFACE_MODE_RMII:
 303                         if (!priv->info->supports_rmii[i])
 304                                 goto unsupported;
 305
 306                         mii->xmii_mode[i] = XMII_MODE_RMII;
 307                         break;
 308                 case PHY_INTERFACE_MODE_RGMII:
 309                 case PHY_INTERFACE_MODE_RGMII_ID:
 310                 case PHY_INTERFACE_MODE_RGMII_RXID:
 311                 case PHY_INTERFACE_MODE_RGMII_TXID:
 312                         if (!priv->info->supports_rgmii[i])
 313                                 goto unsupported;
 314
 315                         mii->xmii_mode[i] = XMII_MODE_RGMII;
 316                         break;
 317                 case PHY_INTERFACE_MODE_SGMII:
 318                         if (!priv->info->supports_sgmii[i])
 319                                 goto unsupported;
 320
 321                         mii->xmii_mode[i] = XMII_MODE_SGMII;
 322                         mii->special[i] = true;
 323                         break;
 324                 case PHY_INTERFACE_MODE_2500BASEX:
 325                         if (!priv->info->supports_2500basex[i])
 326                                 goto unsupported;
 327
 328                         mii->xmii_mode[i] = XMII_MODE_SGMII;
 329                         mii->special[i] = true;
 330                         break;
 331 unsupported:
 332                 default:
 333                         dev_err(dev, "Unsupported PHY mode %s on port %d!\n",
 334                                 phy_modes(priv->phy_mode[i]), i);
 335                         return -EINVAL;
 336                 }
 337
 338                 mii->phy_mac[i] = role;
 339         }
 340         return 0;
 341 }
 342
 343 static int sja1105_init_static_fdb(struct sja1105_private *priv)
 344 {
 345         struct sja1105_l2_lookup_entry *l2_lookup;
 346         struct sja1105_table *table;
 347         int port;
 348
 349         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
 350
 351         /* We only populate the FDB table through dynamic L2 Address Lookup
 352          * entries, except for a special entry at the end which is a catch-all
 353          * for unknown multicast and will be used to control flooding domain.
 354          */
 355         if (table->entry_count) {
 356                 kfree(table->entries);
 357                 table->entry_count = 0;
 358         }
 359
 360         if (!priv->info->can_limit_mcast_flood)
 361                 return 0;
 362
 363         table->entries = kcalloc(1, table->ops->unpacked_entry_size,
 364                                  GFP_KERNEL);
 365         if (!table->entries)
 366                 return -ENOMEM;
 367
 368         table->entry_count = 1;
 369         l2_lookup = table->entries;
 370
 371         /* All L2 multicast addresses have an odd first octet */
 372         l2_lookup[0].macaddr = SJA1105_UNKNOWN_MULTICAST;
 373         l2_lookup[0].mask_macaddr = SJA1105_UNKNOWN_MULTICAST;
 374         l2_lookup[0].lockeds = true;
 375         l2_lookup[0].index = SJA1105_MAX_L2_LOOKUP_COUNT - 1;
 376
 377         /* Flood multicast to every port by default */
 378         for (port = 0; port < priv->ds->num_ports; port++)
 379                 if (!dsa_is_unused_port(priv->ds, port))
 380                         l2_lookup[0].destports |= BIT(port);
 381
 382         return 0;
 383 }
 384
 385 static int sja1105_init_l2_lookup_params(struct sja1105_private *priv)
 386 {
 387         struct sja1105_l2_lookup_params_entry default_l2_lookup_params = {
 388                 /* Learned FDB entries are forgotten after 300 seconds */
 389                 .maxage = SJA1105_AGEING_TIME_MS(300000),
 390                 /* All entries within a FDB bin are available for learning */
 391                 .dyn_tbsz = SJA1105ET_FDB_BIN_SIZE,
 392                 /* And the P/Q/R/S equivalent setting: */
 393                 .start_dynspc = 0,
 394                 /* 2^8 + 2^5 + 2^3 + 2^2 + 2^1 + 1 in Koopman notation */
 395                 .poly = 0x97,
 396                 /* This selects between Independent VLAN Learning (IVL) and
 397                  * Shared VLAN Learning (SVL)
 398                  */
 399                 .shared_learn = true,
 400                 /* Don't discard management traffic based on ENFPORT -
 401                  * we don't perform SMAC port enforcement anyway, so
 402                  * what we are setting here doesn't matter.
 403                  */
 404                 .no_enf_hostprt = false,
 405                 /* Don't learn SMAC for mac_fltres1 and mac_fltres0.
 406                  * Maybe correlate with no_linklocal_learn from bridge driver?
 407                  */
 408                 .no_mgmt_learn = true,
 409                 /* P/Q/R/S only */
 410                 .use_static = true,
 411                 /* Dynamically learned FDB entries can overwrite other (older)
 412                  * dynamic FDB entries
 413                  */
 414                 .owr_dyn = true,
 415                 .drpnolearn = true,
 416         };
 417         struct dsa_switch *ds = priv->ds;
 418         int port, num_used_ports = 0;
 419         struct sja1105_table *table;
 420         u64 max_fdb_entries;
 421
 422         for (port = 0; port < ds->num_ports; port++)
 423                 if (!dsa_is_unused_port(ds, port))
 424                         num_used_ports++;
 425
 426         max_fdb_entries = SJA1105_MAX_L2_LOOKUP_COUNT / num_used_ports;
 427
 428         for (port = 0; port < ds->num_ports; port++) {
 429                 if (dsa_is_unused_port(ds, port))
 430                         continue;
 431
 432                 default_l2_lookup_params.maxaddrp[port] = max_fdb_entries;
 433         }
 434
 435         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS];
 436
 437         if (table->entry_count) {
 438                 kfree(table->entries);
 439                 table->entry_count = 0;
 440         }
 441
 442         table->entries = kcalloc(table->ops->max_entry_count,
 443                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 444         if (!table->entries)
 445                 return -ENOMEM;
 446
 447         table->entry_count = table->ops->max_entry_count;
 448
 449         /* This table only has a single entry */
 450         ((struct sja1105_l2_lookup_params_entry *)table->entries)[0] =
 451                                 default_l2_lookup_params;
 452
 453         return 0;
 454 }
 455
 456 /* Set up a default VLAN for untagged traffic injected from the CPU
 457  * using management routes (e.g. STP, PTP) as opposed to tag_8021q.
 458  * All DT-defined ports are members of this VLAN, and there are no
 459  * restrictions on forwarding (since the CPU selects the destination).
 460  * Frames from this VLAN will always be transmitted as untagged, and
 461  * neither the bridge nor the 8021q module cannot create this VLAN ID.
 462  */
 463 static int sja1105_init_static_vlan(struct sja1105_private *priv)
 464 {
 465         struct sja1105_table *table;
 466         struct sja1105_vlan_lookup_entry pvid = {
 467                 .type_entry = SJA1110_VLAN_D_TAG,
 468                 .ving_mirr = 0,
 469                 .vegr_mirr = 0,
 470                 .vmemb_port = 0,
 471                 .vlan_bc = 0,
 472                 .tag_port = 0,
 473                 .vlanid = SJA1105_DEFAULT_VLAN,
 474         };
 475         struct dsa_switch *ds = priv->ds;
 476         int port;
 477
 478         table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
 479
 480         if (table->entry_count) {
 481                 kfree(table->entries);
 482                 table->entry_count = 0;
 483         }
 484
 485         table->entries = kzalloc(table->ops->unpacked_entry_size,
 486                                  GFP_KERNEL);
 487         if (!table->entries)
 488                 return -ENOMEM;
 489
 490         table->entry_count = 1;
 491
 492         for (port = 0; port < ds->num_ports; port++) {
 493                 if (dsa_is_unused_port(ds, port))
 494                         continue;
 495
 496                 pvid.vmemb_port |= BIT(port);
 497                 pvid.vlan_bc |= BIT(port);
 498                 pvid.tag_port &= ~BIT(port);
 499
 500                 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
 501                         priv->tag_8021q_pvid[port] = SJA1105_DEFAULT_VLAN;
 502                         priv->bridge_pvid[port] = SJA1105_DEFAULT_VLAN;
 503                 }
 504         }
 505
 506         ((struct sja1105_vlan_lookup_entry *)table->entries)[0] = pvid;
 507         return 0;
 508 }
 509
 510 static int sja1105_init_l2_forwarding(struct sja1105_private *priv)
 511 {
 512         struct sja1105_l2_forwarding_entry *l2fwd;
 513         struct dsa_switch *ds = priv->ds;
 514         struct dsa_switch_tree *dst;
 515         struct sja1105_table *table;
 516         struct dsa_link *dl;
 517         int port, tc;
 518         int from, to;
 519
 520         table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING];
 521
 522         if (table->entry_count) {
 523                 kfree(table->entries);
 524                 table->entry_count = 0;
 525         }
 526
 527         table->entries = kcalloc(table->ops->max_entry_count,
 528                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 529         if (!table->entries)
 530                 return -ENOMEM;
 531
 532         table->entry_count = table->ops->max_entry_count;
 533
 534         l2fwd = table->entries;
 535
 536         /* First 5 entries in the L2 Forwarding Table define the forwarding
 537          * rules and the VLAN PCP to ingress queue mapping.
 538          * Set up the ingress queue mapping first.
 539          */
 540         for (port = 0; port < ds->num_ports; port++) {
 541                 if (dsa_is_unused_port(ds, port))
 542                         continue;
 543
 544                 for (tc = 0; tc < SJA1105_NUM_TC; tc++)
 545                         l2fwd[port].vlan_pmap[tc] = tc;
 546         }
 547
 548         /* Then manage the forwarding domain for user ports. These can forward
 549          * only to the always-on domain (CPU port and DSA links)
 550          */
 551         for (from = 0; from < ds->num_ports; from++) {
 552                 if (!dsa_is_user_port(ds, from))
 553                         continue;
 554
 555                 for (to = 0; to < ds->num_ports; to++) {
 556                         if (!dsa_is_cpu_port(ds, to) &&
 557                             !dsa_is_dsa_port(ds, to))
 558                                 continue;
 559
 560                         l2fwd[from].bc_domain |= BIT(to);
 561                         l2fwd[from].fl_domain |= BIT(to);
 562
 563                         sja1105_port_allow_traffic(l2fwd, from, to, true);
 564                 }
 565         }
 566
 567         /* Then manage the forwarding domain for DSA links and CPU ports (the
 568          * always-on domain). These can send packets to any enabled port except
 569          * themselves.
 570          */
 571         for (from = 0; from < ds->num_ports; from++) {
 572                 if (!dsa_is_cpu_port(ds, from) && !dsa_is_dsa_port(ds, from))
 573                         continue;
 574
 575                 for (to = 0; to < ds->num_ports; to++) {
 576                         if (dsa_is_unused_port(ds, to))
 577                                 continue;
 578
 579                         if (from == to)
 580                                 continue;
 581
 582                         l2fwd[from].bc_domain |= BIT(to);
 583                         l2fwd[from].fl_domain |= BIT(to);
 584
 585                         sja1105_port_allow_traffic(l2fwd, from, to, true);
 586                 }
 587         }
 588
 589         /* In odd topologies ("H" connections where there is a DSA link to
 590          * another switch which also has its own CPU port), TX packets can loop
 591          * back into the system (they are flooded from CPU port 1 to the DSA
 592          * link, and from there to CPU port 2). Prevent this from happening by
 593          * cutting RX from DSA links towards our CPU port, if the remote switch
 594          * has its own CPU port and therefore doesn't need ours for network
 595          * stack termination.
 596          */
 597         dst = ds->dst;
 598
 599         list_for_each_entry(dl, &dst->rtable, list) {
 600                 if (dl->dp->ds != ds || dl->link_dp->cpu_dp == dl->dp->cpu_dp)
 601                         continue;
 602
 603                 from = dl->dp->index;
 604                 to = dsa_upstream_port(ds, from);
 605
 606                 dev_warn(ds->dev,
 607                          "H topology detected, cutting RX from DSA link %d to CPU port %d to prevent TX packet loops\n",
 608                          from, to);
 609
 610                 sja1105_port_allow_traffic(l2fwd, from, to, false);
 611
 612                 l2fwd[from].bc_domain &= ~BIT(to);
 613                 l2fwd[from].fl_domain &= ~BIT(to);
 614         }
 615
 616         /* Finally, manage the egress flooding domain. All ports start up with
 617          * flooding enabled, including the CPU port and DSA links.
 618          */
 619         for (port = 0; port < ds->num_ports; port++) {
 620                 if (dsa_is_unused_port(ds, port))
 621                         continue;
 622
 623                 priv->ucast_egress_floods |= BIT(port);
 624                 priv->bcast_egress_floods |= BIT(port);
 625         }
 626
 627         /* Next 8 entries define VLAN PCP mapping from ingress to egress.
 628          * Create a one-to-one mapping.
 629          */
 630         for (tc = 0; tc < SJA1105_NUM_TC; tc++) {
 631                 for (port = 0; port < ds->num_ports; port++) {
 632                         if (dsa_is_unused_port(ds, port))
 633                                 continue;
 634
 635                         l2fwd[ds->num_ports + tc].vlan_pmap[port] = tc;
 636                 }
 637
 638                 l2fwd[ds->num_ports + tc].type_egrpcp2outputq = true;
 639         }
 640
 641         return 0;
 642 }
 643
 644 static int sja1110_init_pcp_remapping(struct sja1105_private *priv)
 645 {
 646         struct sja1110_pcp_remapping_entry *pcp_remap;
 647         struct dsa_switch *ds = priv->ds;
 648         struct sja1105_table *table;
 649         int port, tc;
 650
 651         table = &priv->static_config.tables[BLK_IDX_PCP_REMAPPING];
 652
 653         /* Nothing to do for SJA1105 */
 654         if (!table->ops->max_entry_count)
 655                 return 0;
 656
 657         if (table->entry_count) {
 658                 kfree(table->entries);
 659                 table->entry_count = 0;
 660         }
 661
 662         table->entries = kcalloc(table->ops->max_entry_count,
 663                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 664         if (!table->entries)
 665                 return -ENOMEM;
 666
 667         table->entry_count = table->ops->max_entry_count;
 668
 669         pcp_remap = table->entries;
 670
 671         /* Repeat the configuration done for vlan_pmap */
 672         for (port = 0; port < ds->num_ports; port++) {
 673                 if (dsa_is_unused_port(ds, port))
 674                         continue;
 675
 676                 for (tc = 0; tc < SJA1105_NUM_TC; tc++)
 677                         pcp_remap[port].egrpcp[tc] = tc;
 678         }
 679
 680         return 0;
 681 }
 682
 683 static int sja1105_init_l2_forwarding_params(struct sja1105_private *priv)
 684 {
 685         struct sja1105_l2_forwarding_params_entry *l2fwd_params;
 686         struct sja1105_table *table;
 687
 688         table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS];
 689
 690         if (table->entry_count) {
 691                 kfree(table->entries);
 692                 table->entry_count = 0;
 693         }
 694
 695         table->entries = kcalloc(table->ops->max_entry_count,
 696                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 697         if (!table->entries)
 698                 return -ENOMEM;
 699
 700         table->entry_count = table->ops->max_entry_count;
 701
 702         /* This table only has a single entry */
 703         l2fwd_params = table->entries;
 704
 705         /* Disallow dynamic reconfiguration of vlan_pmap */
 706         l2fwd_params->max_dynp = 0;
 707         /* Use a single memory partition for all ingress queues */
 708         l2fwd_params->part_spc[0] = priv->info->max_frame_mem;
 709
 710         return 0;
 711 }
 712
 713 void sja1105_frame_memory_partitioning(struct sja1105_private *priv)
 714 {
 715         struct sja1105_l2_forwarding_params_entry *l2_fwd_params;
 716         struct sja1105_vl_forwarding_params_entry *vl_fwd_params;
 717         struct sja1105_table *table;
 718
 719         table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS];
 720         l2_fwd_params = table->entries;
 721         l2_fwd_params->part_spc[0] = SJA1105_MAX_FRAME_MEMORY;
 722
 723         /* If we have any critical-traffic virtual links, we need to reserve
 724          * some frame buffer memory for them. At the moment, hardcode the value
 725          * at 100 blocks of 128 bytes of memory each. This leaves 829 blocks
 726          * remaining for best-effort traffic. TODO: figure out a more flexible
 727          * way to perform the frame buffer partitioning.
 728          */
 729         if (!priv->static_config.tables[BLK_IDX_VL_FORWARDING].entry_count)
 730                 return;
 731
 732         table = &priv->static_config.tables[BLK_IDX_VL_FORWARDING_PARAMS];
 733         vl_fwd_params = table->entries;
 734
 735         l2_fwd_params->part_spc[0] -= SJA1105_VL_FRAME_MEMORY;
 736         vl_fwd_params->partspc[0] = SJA1105_VL_FRAME_MEMORY;
 737 }
 738
 739 /* SJA1110 TDMACONFIGIDX values:
 740  *
 741  *      | 100 Mbps ports |  1Gbps ports  | 2.5Gbps ports | Disabled ports
 742  * -----+----------------+---------------+---------------+---------------
 743  *   0  |   0, [5:10]    |     [1:2]     |     [3:4]     |     retag
 744  *   1  |0, [5:10], retag|     [1:2]     |     [3:4]     |       -
 745  *   2  |   0, [5:10]    |  [1:3], retag |       4       |       -
 746  *   3  |   0, [5:10]    |[1:2], 4, retag|       3       |       -
 747  *   4  |  0, 2, [5:10]  |    1, retag   |     [3:4]     |       -
 748  *   5  |  0, 1, [5:10]  |    2, retag   |     [3:4]     |       -
 749  *  14  |   0, [5:10]    | [1:4], retag  |       -       |       -
 750  *  15  |     [5:10]     | [0:4], retag  |       -       |       -
 751  */
 752 static void sja1110_select_tdmaconfigidx(struct sja1105_private *priv)
 753 {
 754         struct sja1105_general_params_entry *general_params;
 755         struct sja1105_table *table;
 756         bool port_1_is_base_tx;
 757         bool port_3_is_2500;
 758         bool port_4_is_2500;
 759         u64 tdmaconfigidx;
 760
 761         if (priv->info->device_id != SJA1110_DEVICE_ID)
 762                 return;
 763
 764         table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
 765         general_params = table->entries;
 766
 767         /* All the settings below are "as opposed to SGMII", which is the
 768          * other pinmuxing option.
 769          */
 770         port_1_is_base_tx = priv->phy_mode[1] == PHY_INTERFACE_MODE_INTERNAL;
 771         port_3_is_2500 = priv->phy_mode[3] == PHY_INTERFACE_MODE_2500BASEX;
 772         port_4_is_2500 = priv->phy_mode[4] == PHY_INTERFACE_MODE_2500BASEX;
 773
 774         if (port_1_is_base_tx)
 775                 /* Retagging port will operate at 1 Gbps */
 776                 tdmaconfigidx = 5;
 777         else if (port_3_is_2500 && port_4_is_2500)
 778                 /* Retagging port will operate at 100 Mbps */
 779                 tdmaconfigidx = 1;
 780         else if (port_3_is_2500)
 781                 /* Retagging port will operate at 1 Gbps */
 782                 tdmaconfigidx = 3;
 783         else if (port_4_is_2500)
 784                 /* Retagging port will operate at 1 Gbps */
 785                 tdmaconfigidx = 2;
 786         else
 787                 /* Retagging port will operate at 1 Gbps */
 788                 tdmaconfigidx = 14;
 789
 790         general_params->tdmaconfigidx = tdmaconfigidx;
 791 }
 792
 793 static int sja1105_init_topology(struct sja1105_private *priv,
 794                                  struct sja1105_general_params_entry *general_params)
 795 {
 796         struct dsa_switch *ds = priv->ds;
 797         int port;
 798
 799         /* The host port is the destination for traffic matching mac_fltres1
 800          * and mac_fltres0 on all ports except itself. Default to an invalid
 801          * value.
 802          */
 803         general_params->host_port = ds->num_ports;
 804
 805         /* Link-local traffic received on casc_port will be forwarded
 806          * to host_port without embedding the source port and device ID
 807          * info in the destination MAC address, and no RX timestamps will be
 808          * taken either (presumably because it is a cascaded port and a
 809          * downstream SJA switch already did that).
 810          * To disable the feature, we need to do different things depending on
 811          * switch generation. On SJA1105 we need to set an invalid port, while
 812          * on SJA1110 which support multiple cascaded ports, this field is a
 813          * bitmask so it must be left zero.
 814          */
 815         if (!priv->info->multiple_cascade_ports)
 816                 general_params->casc_port = ds->num_ports;
 817
 818         for (port = 0; port < ds->num_ports; port++) {
 819                 bool is_upstream = dsa_is_upstream_port(ds, port);
 820                 bool is_dsa_link = dsa_is_dsa_port(ds, port);
 821
 822                 /* Upstream ports can be dedicated CPU ports or
 823                  * upstream-facing DSA links
 824                  */
 825                 if (is_upstream) {
 826                         if (general_params->host_port == ds->num_ports) {
 827                                 general_params->host_port = port;
 828                         } else {
 829                                 dev_err(ds->dev,
 830                                         "Port %llu is already a host port, configuring %d as one too is not supported\n",
 831                                         general_params->host_port, port);
 832                                 return -EINVAL;
 833                         }
 834                 }
 835
 836                 /* Cascade ports are downstream-facing DSA links */
 837                 if (is_dsa_link && !is_upstream) {
 838                         if (priv->info->multiple_cascade_ports) {
 839                                 general_params->casc_port |= BIT(port);
 840                         } else if (general_params->casc_port == ds->num_ports) {
 841                                 general_params->casc_port = port;
 842                         } else {
 843                                 dev_err(ds->dev,
 844                                         "Port %llu is already a cascade port, configuring %d as one too is not supported\n",
 845                                         general_params->casc_port, port);
 846                                 return -EINVAL;
 847                         }
 848                 }
 849         }
 850
 851         if (general_params->host_port == ds->num_ports) {
 852                 dev_err(ds->dev, "No host port configured\n");
 853                 return -EINVAL;
 854         }
 855
 856         return 0;
 857 }
 858
 859 static int sja1105_init_general_params(struct sja1105_private *priv)
 860 {
 861         struct sja1105_general_params_entry default_general_params = {
 862                 /* Allow dynamic changing of the mirror port */
 863                 .mirr_ptacu = true,
 864                 .switchid = priv->ds->index,
 865                 /* Priority queue for link-local management frames
 866                  * (both ingress to and egress from CPU - PTP, STP etc)
 867                  */
 868                 .hostprio = 7,
 869                 .mac_fltres1 = SJA1105_LINKLOCAL_FILTER_A,
 870                 .mac_flt1    = SJA1105_LINKLOCAL_FILTER_A_MASK,
 871                 .incl_srcpt1 = false,
 872                 .send_meta1  = false,
 873                 .mac_fltres0 = SJA1105_LINKLOCAL_FILTER_B,
 874                 .mac_flt0    = SJA1105_LINKLOCAL_FILTER_B_MASK,
 875                 .incl_srcpt0 = false,
 876                 .send_meta0  = false,
 877                 /* Default to an invalid value */
 878                 .mirr_port = priv->ds->num_ports,
 879                 /* No TTEthernet */
 880                 .vllupformat = SJA1105_VL_FORMAT_PSFP,
 881                 .vlmarker = 0,
 882                 .vlmask = 0,
 883                 /* Only update correctionField for 1-step PTP (L2 transport) */
 884                 .ignore2stf = 0,
 885                 /* Forcefully disable VLAN filtering by telling
 886                  * the switch that VLAN has a different EtherType.
 887                  */
 888                 .tpid = ETH_P_SJA1105,
 889                 .tpid2 = ETH_P_SJA1105,
 890                 /* Enable the TTEthernet engine on SJA1110 */
 891                 .tte_en = true,
 892                 /* Set up the EtherType for control packets on SJA1110 */
 893                 .header_type = ETH_P_SJA1110,
 894         };
 895         struct sja1105_general_params_entry *general_params;
 896         struct sja1105_table *table;
 897         int rc;
 898
 899         rc = sja1105_init_topology(priv, &default_general_params);
 900         if (rc)
 901                 return rc;
 902
 903         table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
 904
 905         if (table->entry_count) {
 906                 kfree(table->entries);
 907                 table->entry_count = 0;
 908         }
 909
 910         table->entries = kcalloc(table->ops->max_entry_count,
 911                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 912         if (!table->entries)
 913                 return -ENOMEM;
 914
 915         table->entry_count = table->ops->max_entry_count;
 916
 917         general_params = table->entries;
 918
 919         /* This table only has a single entry */
 920         general_params[0] = default_general_params;
 921
 922         sja1110_select_tdmaconfigidx(priv);
 923
 924         return 0;
 925 }
 926
 927 static int sja1105_init_avb_params(struct sja1105_private *priv)
 928 {
 929         struct sja1105_avb_params_entry *avb;
 930         struct sja1105_table *table;
 931
 932         table = &priv->static_config.tables[BLK_IDX_AVB_PARAMS];
 933
 934         /* Discard previous AVB Parameters Table */
 935         if (table->entry_count) {
 936                 kfree(table->entries);
 937                 table->entry_count = 0;
 938         }
 939
 940         table->entries = kcalloc(table->ops->max_entry_count,
 941                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 942         if (!table->entries)
 943                 return -ENOMEM;
 944
 945         table->entry_count = table->ops->max_entry_count;
 946
 947         avb = table->entries;
 948
 949         /* Configure the MAC addresses for meta frames */
 950         avb->destmeta = SJA1105_META_DMAC;
 951         avb->srcmeta  = SJA1105_META_SMAC;
 952         /* On P/Q/R/S, configure the direction of the PTP_CLK pin as input by
 953          * default. This is because there might be boards with a hardware
 954          * layout where enabling the pin as output might cause an electrical
 955          * clash. On E/T the pin is always an output, which the board designers
 956          * probably already knew, so even if there are going to be electrical
 957          * issues, there's nothing we can do.
 958          */
 959         avb->cas_master = false;
 960
 961         return 0;
 962 }
 963
 964 /* The L2 policing table is 2-stage. The table is looked up for each frame
 965  * according to the ingress port, whether it was broadcast or not, and the
 966  * classified traffic class (given by VLAN PCP). This portion of the lookup is
 967  * fixed, and gives access to the SHARINDX, an indirection register pointing
 968  * within the policing table itself, which is used to resolve the policer that
 969  * will be used for this frame.
 970  *
 971  *  Stage 1                              Stage 2
 972  * +------------+--------+              +---------------------------------+
 973  * |Port 0 TC 0 |SHARINDX|              | Policer 0: Rate, Burst, MTU     |
 974  * +------------+--------+              +---------------------------------+
 975  * |Port 0 TC 1 |SHARINDX|              | Policer 1: Rate, Burst, MTU     |
 976  * +------------+--------+              +---------------------------------+
 977  *    ...                               | Policer 2: Rate, Burst, MTU     |
 978  * +------------+--------+              +---------------------------------+
 979  * |Port 0 TC 7 |SHARINDX|              | Policer 3: Rate, Burst, MTU     |
 980  * +------------+--------+              +---------------------------------+
 981  * |Port 1 TC 0 |SHARINDX|              | Policer 4: Rate, Burst, MTU     |
 982  * +------------+--------+              +---------------------------------+
 983  *    ...                               | Policer 5: Rate, Burst, MTU     |
 984  * +------------+--------+              +---------------------------------+
 985  * |Port 1 TC 7 |SHARINDX|              | Policer 6: Rate, Burst, MTU     |
 986  * +------------+--------+              +---------------------------------+
 987  *    ...                               | Policer 7: Rate, Burst, MTU     |
 988  * +------------+--------+              +---------------------------------+
 989  * |Port 4 TC 7 |SHARINDX|                 ...
 990  * +------------+--------+
 991  * |Port 0 BCAST|SHARINDX|                 ...
 992  * +------------+--------+
 993  * |Port 1 BCAST|SHARINDX|                 ...
 994  * +------------+--------+
 995  *    ...                                  ...
 996  * +------------+--------+              +---------------------------------+
 997  * |Port 4 BCAST|SHARINDX|              | Policer 44: Rate, Burst, MTU    |
 998  * +------------+--------+              +---------------------------------+
 999  *
1000  * In this driver, we shall use policers 0-4 as statically alocated port
1001  * (matchall) policers. So we need to make the SHARINDX for all lookups
1002  * corresponding to this ingress port (8 VLAN PCP lookups and 1 broadcast
1003  * lookup) equal.
1004  * The remaining policers (40) shall be dynamically allocated for flower
1005  * policers, where the key is either vlan_prio or dst_mac ff:ff:ff:ff:ff:ff.
1006  */
1007 #define SJA1105_RATE_MBPS(speed) (((speed) * 64000) / 1000)
1008
1009 static int sja1105_init_l2_policing(struct sja1105_private *priv)
1010 {
1011         struct sja1105_l2_policing_entry *policing;
1012         struct dsa_switch *ds = priv->ds;
1013         struct sja1105_table *table;
1014         int port, tc;
1015
1016         table = &priv->static_config.tables[BLK_IDX_L2_POLICING];
1017
1018         /* Discard previous L2 Policing Table */
1019         if (table->entry_count) {
1020                 kfree(table->entries);
1021                 table->entry_count = 0;
1022         }
1023
1024         table->entries = kcalloc(table->ops->max_entry_count,
1025                                  table->ops->unpacked_entry_size, GFP_KERNEL);
1026         if (!table->entries)
1027                 return -ENOMEM;
1028
1029         table->entry_count = table->ops->max_entry_count;
1030
1031         policing = table->entries;
1032
1033         /* Setup shared indices for the matchall policers */
1034         for (port = 0; port < ds->num_ports; port++) {
1035                 int mcast = (ds->num_ports * (SJA1105_NUM_TC + 1)) + port;
1036                 int bcast = (ds->num_ports * SJA1105_NUM_TC) + port;
1037
1038                 for (tc = 0; tc < SJA1105_NUM_TC; tc++)
1039                         policing[port * SJA1105_NUM_TC + tc].sharindx = port;
1040
1041                 policing[bcast].sharindx = port;
1042                 /* Only SJA1110 has multicast policers */
1043                 if (mcast <= table->ops->max_entry_count)
1044                         policing[mcast].sharindx = port;
1045         }
1046
1047         /* Setup the matchall policer parameters */
1048         for (port = 0; port < ds->num_ports; port++) {
1049                 int mtu = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1050
1051                 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1052                         mtu += VLAN_HLEN;
1053
1054                 policing[port].smax = 65535; /* Burst size in bytes */
1055                 policing[port].rate = SJA1105_RATE_MBPS(1000);
1056                 policing[port].maxlen = mtu;
1057                 policing[port].partition = 0;
1058         }
1059
1060         return 0;
1061 }
1062
1063 static int sja1105_static_config_load(struct sja1105_private *priv)
1064 {
1065         int rc;
1066
1067         sja1105_static_config_free(&priv->static_config);
1068         rc = sja1105_static_config_init(&priv->static_config,
1069                                         priv->info->static_ops,
1070                                         priv->info->device_id);
1071         if (rc)
1072                 return rc;
1073
1074         /* Build static configuration */
1075         rc = sja1105_init_mac_settings(priv);
1076         if (rc < 0)
1077                 return rc;
1078         rc = sja1105_init_mii_settings(priv);
1079         if (rc < 0)
1080                 return rc;
1081         rc = sja1105_init_static_fdb(priv);
1082         if (rc < 0)
1083                 return rc;
1084         rc = sja1105_init_static_vlan(priv);
1085         if (rc < 0)
1086                 return rc;
1087         rc = sja1105_init_l2_lookup_params(priv);
1088         if (rc < 0)
1089                 return rc;
1090         rc = sja1105_init_l2_forwarding(priv);
1091         if (rc < 0)
1092                 return rc;
1093         rc = sja1105_init_l2_forwarding_params(priv);
1094         if (rc < 0)
1095                 return rc;
1096         rc = sja1105_init_l2_policing(priv);
1097         if (rc < 0)
1098                 return rc;
1099         rc = sja1105_init_general_params(priv);
1100         if (rc < 0)
1101                 return rc;
1102         rc = sja1105_init_avb_params(priv);
1103         if (rc < 0)
1104                 return rc;
1105         rc = sja1110_init_pcp_remapping(priv);
1106         if (rc < 0)
1107                 return rc;
1108
1109         /* Send initial configuration to hardware via SPI */
1110         return sja1105_static_config_upload(priv);
1111 }
1112
1113 /* This is the "new way" for a MAC driver to configure its RGMII delay lines,
1114  * based on the explicit "rx-internal-delay-ps" and "tx-internal-delay-ps"
1115  * properties. It has the advantage of working with fixed links and with PHYs
1116  * that apply RGMII delays too, and the MAC driver needs not perform any
1117  * special checks.
1118  *
1119  * Previously we were acting upon the "phy-mode" property when we were
1120  * operating in fixed-link, basically acting as a PHY, but with a reversed
1121  * interpretation: PHY_INTERFACE_MODE_RGMII_TXID means that the MAC should
1122  * behave as if it is connected to a PHY which has applied RGMII delays in the
1123  * TX direction. So if anything, RX delays should have been added by the MAC,
1124  * but we were adding TX delays.
1125  *
1126  * If the "{rx,tx}-internal-delay-ps" properties are not specified, we fall
1127  * back to the legacy behavior and apply delays on fixed-link ports based on
1128  * the reverse interpretation of the phy-mode. This is a deviation from the
1129  * expected default behavior which is to simply apply no delays. To achieve
1130  * that behavior with the new bindings, it is mandatory to specify
1131  * "{rx,tx}-internal-delay-ps" with a value of 0.
1132  */
1133 static int sja1105_parse_rgmii_delays(struct sja1105_private *priv, int port,
1134                                       struct device_node *port_dn)
1135 {
1136         phy_interface_t phy_mode = priv->phy_mode[port];
1137         struct device *dev = &priv->spidev->dev;
1138         int rx_delay = -1, tx_delay = -1;
1139
1140         if (!phy_interface_mode_is_rgmii(phy_mode))
1141                 return 0;
1142
1143         of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);
1144         of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);
1145
1146         if (rx_delay == -1 && tx_delay == -1 && priv->fixed_link[port]) {
1147                 dev_warn(dev,
1148                          "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
1149                          "please update device tree to specify \"rx-internal-delay-ps\" and "
1150                          "\"tx-internal-delay-ps\"",
1151                          port);
1152
1153                 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
1154                     phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
1155                         rx_delay = 2000;
1156
1157                 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
1158                     phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
1159                         tx_delay = 2000;
1160         }
1161
1162         if (rx_delay < 0)
1163                 rx_delay = 0;
1164         if (tx_delay < 0)
1165                 tx_delay = 0;
1166
1167         if ((rx_delay || tx_delay) && !priv->info->setup_rgmii_delay) {
1168                 dev_err(dev, "Chip cannot apply RGMII delays\n");
1169                 return -EINVAL;
1170         }
1171
1172         if ((rx_delay && rx_delay < SJA1105_RGMII_DELAY_MIN_PS) ||
1173             (tx_delay && tx_delay < SJA1105_RGMII_DELAY_MIN_PS) ||
1174             (rx_delay > SJA1105_RGMII_DELAY_MAX_PS) ||
1175             (tx_delay > SJA1105_RGMII_DELAY_MAX_PS)) {
1176                 dev_err(dev,
1177                         "port %d RGMII delay values out of range, must be between %d and %d ps\n",
1178                         port, SJA1105_RGMII_DELAY_MIN_PS, SJA1105_RGMII_DELAY_MAX_PS);
1179                 return -ERANGE;
1180         }
1181
1182         priv->rgmii_rx_delay_ps[port] = rx_delay;
1183         priv->rgmii_tx_delay_ps[port] = tx_delay;
1184
1185         return 0;
1186 }
1187
1188 static int sja1105_parse_ports_node(struct sja1105_private *priv,
1189                                     struct device_node *ports_node)
1190 {
1191         struct device *dev = &priv->spidev->dev;
1192         struct device_node *child;
1193
1194         for_each_available_child_of_node(ports_node, child) {
1195                 struct device_node *phy_node;
1196                 phy_interface_t phy_mode;
1197                 u32 index;
1198                 int err;
1199
1200                 /* Get switch port number from DT */
1201                 if (of_property_read_u32(child, "reg", &index) < 0) {
1202                         dev_err(dev, "Port number not defined in device tree "
1203                                 "(property \"reg\")\n");
1204                         of_node_put(child);
1205                         return -ENODEV;
1206                 }
1207
1208                 /* Get PHY mode from DT */
1209                 err = of_get_phy_mode(child, &phy_mode);
1210                 if (err) {
1211                         dev_err(dev, "Failed to read phy-mode or "
1212                                 "phy-interface-type property for port %d\n",
1213                                 index);
1214                         of_node_put(child);
1215                         return -ENODEV;
1216                 }
1217
1218                 phy_node = of_parse_phandle(child, "phy-handle", 0);
1219                 if (!phy_node) {
1220                         if (!of_phy_is_fixed_link(child)) {
1221                                 dev_err(dev, "phy-handle or fixed-link "
1222                                         "properties missing!\n");
1223                                 of_node_put(child);
1224                                 return -ENODEV;
1225                         }
1226                         /* phy-handle is missing, but fixed-link isn't.
1227                          * So it's a fixed link. Default to PHY role.
1228                          */
1229                         priv->fixed_link[index] = true;
1230                 } else {
1231                         of_node_put(phy_node);
1232                 }
1233
1234                 priv->phy_mode[index] = phy_mode;
1235
1236                 err = sja1105_parse_rgmii_delays(priv, index, child);
1237                 if (err) {
1238                         of_node_put(child);
1239                         return err;
1240                 }
1241         }
1242
1243         return 0;
1244 }
1245
1246 static int sja1105_parse_dt(struct sja1105_private *priv)
1247 {
1248         struct device *dev = &priv->spidev->dev;
1249         struct device_node *switch_node = dev->of_node;
1250         struct device_node *ports_node;
1251         int rc;
1252
1253         ports_node = of_get_child_by_name(switch_node, "ports");
1254         if (!ports_node)
1255                 ports_node = of_get_child_by_name(switch_node, "ethernet-ports");
1256         if (!ports_node) {
1257                 dev_err(dev, "Incorrect bindings: absent \"ports\" node\n");
1258                 return -ENODEV;
1259         }
1260
1261         rc = sja1105_parse_ports_node(priv, ports_node);
1262         of_node_put(ports_node);
1263
1264         return rc;
1265 }
1266
1267 /* Convert link speed from SJA1105 to ethtool encoding */
1268 static int sja1105_port_speed_to_ethtool(struct sja1105_private *priv,
1269                                          u64 speed)
1270 {
1271         if (speed == priv->info->port_speed[SJA1105_SPEED_10MBPS])
1272                 return SPEED_10;
1273         if (speed == priv->info->port_speed[SJA1105_SPEED_100MBPS])
1274                 return SPEED_100;
1275         if (speed == priv->info->port_speed[SJA1105_SPEED_1000MBPS])
1276                 return SPEED_1000;
1277         if (speed == priv->info->port_speed[SJA1105_SPEED_2500MBPS])
1278                 return SPEED_2500;
1279         return SPEED_UNKNOWN;
1280 }
1281
1282 /* Set link speed in the MAC configuration for a specific port. */
1283 static int sja1105_adjust_port_config(struct sja1105_private *priv, int port,
1284                                       int speed_mbps)
1285 {
1286         struct sja1105_mac_config_entry *mac;
1287         struct device *dev = priv->ds->dev;
1288         u64 speed;
1289         int rc;
1290
1291         /* On P/Q/R/S, one can read from the device via the MAC reconfiguration
1292          * tables. On E/T, MAC reconfig tables are not readable, only writable.
1293          * We have to *know* what the MAC looks like.  For the sake of keeping
1294          * the code common, we'll use the static configuration tables as a
1295          * reasonable approximation for both E/T and P/Q/R/S.
1296          */
1297         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
1298
1299         switch (speed_mbps) {
1300         case SPEED_UNKNOWN:
1301                 /* PHYLINK called sja1105_mac_config() to inform us about
1302                  * the state->interface, but AN has not completed and the
1303                  * speed is not yet valid. UM10944.pdf says that setting
1304                  * SJA1105_SPEED_AUTO at runtime disables the port, so that is
1305                  * ok for power consumption in case AN will never complete -
1306                  * otherwise PHYLINK should come back with a new update.
1307                  */
1308                 speed = priv->info->port_speed[SJA1105_SPEED_AUTO];
1309                 break;
1310         case SPEED_10:
1311                 speed = priv->info->port_speed[SJA1105_SPEED_10MBPS];
1312                 break;
1313         case SPEED_100:
1314                 speed = priv->info->port_speed[SJA1105_SPEED_100MBPS];
1315                 break;
1316         case SPEED_1000:
1317                 speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS];
1318                 break;
1319         case SPEED_2500:
1320                 speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS];
1321                 break;
1322         default:
1323                 dev_err(dev, "Invalid speed %iMbps\n", speed_mbps);
1324                 return -EINVAL;
1325         }
1326
1327         /* Overwrite SJA1105_SPEED_AUTO from the static MAC configuration
1328          * table, since this will be used for the clocking setup, and we no
1329          * longer need to store it in the static config (already told hardware
1330          * we want auto during upload phase).
1331          * Actually for the SGMII port, the MAC is fixed at 1 Gbps and
1332          * we need to configure the PCS only (if even that).
1333          */
1334         if (priv->phy_mode[port] == PHY_INTERFACE_MODE_SGMII)
1335                 mac[port].speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS];
1336         else if (priv->phy_mode[port] == PHY_INTERFACE_MODE_2500BASEX)
1337                 mac[port].speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS];
1338         else
1339                 mac[port].speed = speed;
1340
1341         /* Write to the dynamic reconfiguration tables */
1342         rc = sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
1343                                           &mac[port], true);
1344         if (rc < 0) {
1345                 dev_err(dev, "Failed to write MAC config: %d\n", rc);
1346                 return rc;
1347         }
1348
1349         /* Reconfigure the PLLs for the RGMII interfaces (required 125 MHz at
1350          * gigabit, 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps). For MII and
1351          * RMII no change of the clock setup is required. Actually, changing
1352          * the clock setup does interrupt the clock signal for a certain time
1353          * which causes trouble for all PHYs relying on this signal.
1354          */
1355         if (!phy_interface_mode_is_rgmii(priv->phy_mode[port]))
1356                 return 0;
1357
1358         return sja1105_clocking_setup_port(priv, port);
1359 }
1360
1361 static struct phylink_pcs *
1362 sja1105_mac_select_pcs(struct dsa_switch *ds, int port, phy_interface_t iface)
1363 {
1364         struct sja1105_private *priv = ds->priv;
1365         struct dw_xpcs *xpcs = priv->xpcs[port];
1366
1367         if (xpcs)
1368                 return &xpcs->pcs;
1369
1370         return NULL;
1371 }
1372
1373 static void sja1105_mac_link_down(struct dsa_switch *ds, int port,
1374                                   unsigned int mode,
1375                                   phy_interface_t interface)
1376 {
1377         sja1105_inhibit_tx(ds->priv, BIT(port), true);
1378 }
1379
1380 static void sja1105_mac_link_up(struct dsa_switch *ds, int port,
1381                                 unsigned int mode,
1382                                 phy_interface_t interface,
1383                                 struct phy_device *phydev,
1384                                 int speed, int duplex,
1385                                 bool tx_pause, bool rx_pause)
1386 {
1387         struct sja1105_private *priv = ds->priv;
1388
1389         sja1105_adjust_port_config(priv, port, speed);
1390
1391         sja1105_inhibit_tx(priv, BIT(port), false);
1392 }
1393
1394 static void sja1105_phylink_get_caps(struct dsa_switch *ds, int port,
1395                                      struct phylink_config *config)
1396 {
1397         struct sja1105_private *priv = ds->priv;
1398
1399         /* The SJA1105 MAC programming model is through the static config
1400          * (the xMII Mode table cannot be dynamically reconfigured), and
1401          * we have to program that early.
1402          */
1403         __set_bit(priv->phy_mode[port], config->supported_interfaces);
1404 }
1405
1406 static void sja1105_phylink_validate(struct dsa_switch *ds, int port,
1407                                      unsigned long *supported,
1408                                      struct phylink_link_state *state)
1409 {
1410         /* Construct a new mask which exhaustively contains all link features
1411          * supported by the MAC, and then apply that (logical AND) to what will
1412          * be sent to the PHY for "marketing".
1413          */
1414         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1415         struct sja1105_private *priv = ds->priv;
1416         struct sja1105_xmii_params_entry *mii;
1417
1418         mii = priv->static_config.tables[BLK_IDX_XMII_PARAMS].entries;
1419
1420         /* The MAC does not support pause frames, and also doesn't
1421          * support half-duplex traffic modes.
1422          */
1423         phylink_set(mask, Autoneg);
1424         phylink_set(mask, MII);
1425         phylink_set(mask, 10baseT_Full);
1426         phylink_set(mask, 100baseT_Full);
1427         phylink_set(mask, 100baseT1_Full);
1428         if (mii->xmii_mode[port] == XMII_MODE_RGMII ||
1429             mii->xmii_mode[port] == XMII_MODE_SGMII)
1430                 phylink_set(mask, 1000baseT_Full);
1431         if (priv->info->supports_2500basex[port]) {
1432                 phylink_set(mask, 2500baseT_Full);
1433                 phylink_set(mask, 2500baseX_Full);
1434         }
1435
1436         linkmode_and(supported, supported, mask);
1437         linkmode_and(state->advertising, state->advertising, mask);
1438 }
1439
1440 static int
1441 sja1105_find_static_fdb_entry(struct sja1105_private *priv, int port,
1442                               const struct sja1105_l2_lookup_entry *requested)
1443 {
1444         struct sja1105_l2_lookup_entry *l2_lookup;
1445         struct sja1105_table *table;
1446         int i;
1447
1448         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
1449         l2_lookup = table->entries;
1450
1451         for (i = 0; i < table->entry_count; i++)
1452                 if (l2_lookup[i].macaddr == requested->macaddr &&
1453                     l2_lookup[i].vlanid == requested->vlanid &&
1454                     l2_lookup[i].destports & BIT(port))
1455                         return i;
1456
1457         return -1;
1458 }
1459
1460 /* We want FDB entries added statically through the bridge command to persist
1461  * across switch resets, which are a common thing during normal SJA1105
1462  * operation. So we have to back them up in the static configuration tables
1463  * and hence apply them on next static config upload... yay!
1464  */
1465 static int
1466 sja1105_static_fdb_change(struct sja1105_private *priv, int port,
1467                           const struct sja1105_l2_lookup_entry *requested,
1468                           bool keep)
1469 {
1470         struct sja1105_l2_lookup_entry *l2_lookup;
1471         struct sja1105_table *table;
1472         int rc, match;
1473
1474         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
1475
1476         match = sja1105_find_static_fdb_entry(priv, port, requested);
1477         if (match < 0) {
1478                 /* Can't delete a missing entry. */
1479                 if (!keep)
1480                         return 0;
1481
1482                 /* No match => new entry */
1483                 rc = sja1105_table_resize(table, table->entry_count + 1);
1484                 if (rc)
1485                         return rc;
1486
1487                 match = table->entry_count - 1;
1488         }
1489
1490         /* Assign pointer after the resize (it may be new memory) */
1491         l2_lookup = table->entries;
1492
1493         /* We have a match.
1494          * If the job was to add this FDB entry, it's already done (mostly
1495          * anyway, since the port forwarding mask may have changed, case in
1496          * which we update it).
1497          * Otherwise we have to delete it.
1498          */
1499         if (keep) {
1500                 l2_lookup[match] = *requested;
1501                 return 0;
1502         }
1503
1504         /* To remove, the strategy is to overwrite the element with
1505          * the last one, and then reduce the array size by 1
1506          */
1507         l2_lookup[match] = l2_lookup[table->entry_count - 1];
1508         return sja1105_table_resize(table, table->entry_count - 1);
1509 }
1510
1511 /* First-generation switches have a 4-way set associative TCAM that
1512  * holds the FDB entries. An FDB index spans from 0 to 1023 and is comprised of
1513  * a "bin" (grouping of 4 entries) and a "way" (an entry within a bin).
1514  * For the placement of a newly learnt FDB entry, the switch selects the bin
1515  * based on a hash function, and the way within that bin incrementally.
1516  */
1517 static int sja1105et_fdb_index(int bin, int way)
1518 {
1519         return bin * SJA1105ET_FDB_BIN_SIZE + way;
1520 }
1521
1522 static int sja1105et_is_fdb_entry_in_bin(struct sja1105_private *priv, int bin,
1523                                          const u8 *addr, u16 vid,
1524                                          struct sja1105_l2_lookup_entry *match,
1525                                          int *last_unused)
1526 {
1527         int way;
1528
1529         for (way = 0; way < SJA1105ET_FDB_BIN_SIZE; way++) {
1530                 struct sja1105_l2_lookup_entry l2_lookup = {0};
1531                 int index = sja1105et_fdb_index(bin, way);
1532
1533                 /* Skip unused entries, optionally marking them
1534                  * into the return value
1535                  */
1536                 if (sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1537                                                 index, &l2_lookup)) {
1538                         if (last_unused)
1539                                 *last_unused = way;
1540                         continue;
1541                 }
1542
1543                 if (l2_lookup.macaddr == ether_addr_to_u64(addr) &&
1544                     l2_lookup.vlanid == vid) {
1545                         if (match)
1546                                 *match = l2_lookup;
1547                         return way;
1548                 }
1549         }
1550         /* Return an invalid entry index if not found */
1551         return -1;
1552 }
1553
1554 int sja1105et_fdb_add(struct dsa_switch *ds, int port,
1555                       const unsigned char *addr, u16 vid)
1556 {
1557         struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp;
1558         struct sja1105_private *priv = ds->priv;
1559         struct device *dev = ds->dev;
1560         int last_unused = -1;
1561         int start, end, i;
1562         int bin, way, rc;
1563
1564         bin = sja1105et_fdb_hash(priv, addr, vid);
1565
1566         way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid,
1567                                             &l2_lookup, &last_unused);
1568         if (way >= 0) {
1569                 /* We have an FDB entry. Is our port in the destination
1570                  * mask? If yes, we need to do nothing. If not, we need
1571                  * to rewrite the entry by adding this port to it.
1572                  */
1573                 if ((l2_lookup.destports & BIT(port)) && l2_lookup.lockeds)
1574                         return 0;
1575                 l2_lookup.destports |= BIT(port);
1576         } else {
1577                 int index = sja1105et_fdb_index(bin, way);
1578
1579                 /* We don't have an FDB entry. We construct a new one and
1580                  * try to find a place for it within the FDB table.
1581                  */
1582                 l2_lookup.macaddr = ether_addr_to_u64(addr);
1583                 l2_lookup.destports = BIT(port);
1584                 l2_lookup.vlanid = vid;
1585
1586                 if (last_unused >= 0) {
1587                         way = last_unused;
1588                 } else {
1589                         /* Bin is full, need to evict somebody.
1590                          * Choose victim at random. If you get these messages
1591                          * often, you may need to consider changing the
1592                          * distribution function:
1593                          * static_config[BLK_IDX_L2_LOOKUP_PARAMS].entries->poly
1594                          */
1595                         get_random_bytes(&way, sizeof(u8));
1596                         way %= SJA1105ET_FDB_BIN_SIZE;
1597                         dev_warn(dev, "Warning, FDB bin %d full while adding entry for %pM. Evicting entry %u.\n",
1598                                  bin, addr, way);
1599                         /* Evict entry */
1600                         sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1601                                                      index, NULL, false);
1602                 }
1603         }
1604         l2_lookup.lockeds = true;
1605         l2_lookup.index = sja1105et_fdb_index(bin, way);
1606
1607         rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1608                                           l2_lookup.index, &l2_lookup,
1609                                           true);
1610         if (rc < 0)
1611                 return rc;
1612
1613         /* Invalidate a dynamically learned entry if that exists */
1614         start = sja1105et_fdb_index(bin, 0);
1615         end = sja1105et_fdb_index(bin, way);
1616
1617         for (i = start; i < end; i++) {
1618                 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1619                                                  i, &tmp);
1620                 if (rc == -ENOENT)
1621                         continue;
1622                 if (rc)
1623                         return rc;
1624
1625                 if (tmp.macaddr != ether_addr_to_u64(addr) || tmp.vlanid != vid)
1626                         continue;
1627
1628                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1629                                                   i, NULL, false);
1630                 if (rc)
1631                         return rc;
1632
1633                 break;
1634         }
1635
1636         return sja1105_static_fdb_change(priv, port, &l2_lookup, true);
1637 }
1638
1639 int sja1105et_fdb_del(struct dsa_switch *ds, int port,
1640                       const unsigned char *addr, u16 vid)
1641 {
1642         struct sja1105_l2_lookup_entry l2_lookup = {0};
1643         struct sja1105_private *priv = ds->priv;
1644         int index, bin, way, rc;
1645         bool keep;
1646
1647         bin = sja1105et_fdb_hash(priv, addr, vid);
1648         way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid,
1649                                             &l2_lookup, NULL);
1650         if (way < 0)
1651                 return 0;
1652         index = sja1105et_fdb_index(bin, way);
1653
1654         /* We have an FDB entry. Is our port in the destination mask? If yes,
1655          * we need to remove it. If the resulting port mask becomes empty, we
1656          * need to completely evict the FDB entry.
1657          * Otherwise we just write it back.
1658          */
1659         l2_lookup.destports &= ~BIT(port);
1660
1661         if (l2_lookup.destports)
1662                 keep = true;
1663         else
1664                 keep = false;
1665
1666         rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1667                                           index, &l2_lookup, keep);
1668         if (rc < 0)
1669                 return rc;
1670
1671         return sja1105_static_fdb_change(priv, port, &l2_lookup, keep);
1672 }
1673
1674 int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port,
1675                         const unsigned char *addr, u16 vid)
1676 {
1677         struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp;
1678         struct sja1105_private *priv = ds->priv;
1679         int rc, i;
1680
1681         /* Search for an existing entry in the FDB table */
1682         l2_lookup.macaddr = ether_addr_to_u64(addr);
1683         l2_lookup.vlanid = vid;
1684         l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0);
1685         l2_lookup.mask_vlanid = VLAN_VID_MASK;
1686         l2_lookup.destports = BIT(port);
1687
1688         tmp = l2_lookup;
1689
1690         rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1691                                          SJA1105_SEARCH, &tmp);
1692         if (rc == 0 && tmp.index != SJA1105_MAX_L2_LOOKUP_COUNT - 1) {
1693                 /* Found a static entry and this port is already in the entry's
1694                  * port mask => job done
1695                  */
1696                 if ((tmp.destports & BIT(port)) && tmp.lockeds)
1697                         return 0;
1698
1699                 l2_lookup = tmp;
1700
1701                 /* l2_lookup.index is populated by the switch in case it
1702                  * found something.
1703                  */
1704                 l2_lookup.destports |= BIT(port);
1705                 goto skip_finding_an_index;
1706         }
1707
1708         /* Not found, so try to find an unused spot in the FDB.
1709          * This is slightly inefficient because the strategy is knock-knock at
1710          * every possible position from 0 to 1023.
1711          */
1712         for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1713                 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1714                                                  i, NULL);
1715                 if (rc < 0)
1716                         break;
1717         }
1718         if (i == SJA1105_MAX_L2_LOOKUP_COUNT) {
1719                 dev_err(ds->dev, "FDB is full, cannot add entry.\n");
1720                 return -EINVAL;
1721         }
1722         l2_lookup.index = i;
1723
1724 skip_finding_an_index:
1725         l2_lookup.lockeds = true;
1726
1727         rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1728                                           l2_lookup.index, &l2_lookup,
1729                                           true);
1730         if (rc < 0)
1731                 return rc;
1732
1733         /* The switch learns dynamic entries and looks up the FDB left to
1734          * right. It is possible that our addition was concurrent with the
1735          * dynamic learning of the same address, so now that the static entry
1736          * has been installed, we are certain that address learning for this
1737          * particular address has been turned off, so the dynamic entry either
1738          * is in the FDB at an index smaller than the static one, or isn't (it
1739          * can also be at a larger index, but in that case it is inactive
1740          * because the static FDB entry will match first, and the dynamic one
1741          * will eventually age out). Search for a dynamically learned address
1742          * prior to our static one and invalidate it.
1743          */
1744         tmp = l2_lookup;
1745
1746         rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1747                                          SJA1105_SEARCH, &tmp);
1748         if (rc < 0) {
1749                 dev_err(ds->dev,
1750                         "port %d failed to read back entry for %pM vid %d: %pe\n",
1751                         port, addr, vid, ERR_PTR(rc));
1752                 return rc;
1753         }
1754
1755         if (tmp.index < l2_lookup.index) {
1756                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1757                                                   tmp.index, NULL, false);
1758                 if (rc < 0)
1759                         return rc;
1760         }
1761
1762         return sja1105_static_fdb_change(priv, port, &l2_lookup, true);
1763 }
1764
1765 int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port,
1766                         const unsigned char *addr, u16 vid)
1767 {
1768         struct sja1105_l2_lookup_entry l2_lookup = {0};
1769         struct sja1105_private *priv = ds->priv;
1770         bool keep;
1771         int rc;
1772
1773         l2_lookup.macaddr = ether_addr_to_u64(addr);
1774         l2_lookup.vlanid = vid;
1775         l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0);
1776         l2_lookup.mask_vlanid = VLAN_VID_MASK;
1777         l2_lookup.destports = BIT(port);
1778
1779         rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1780                                          SJA1105_SEARCH, &l2_lookup);
1781         if (rc < 0)
1782                 return 0;
1783
1784         l2_lookup.destports &= ~BIT(port);
1785
1786         /* Decide whether we remove just this port from the FDB entry,
1787          * or if we remove it completely.
1788          */
1789         if (l2_lookup.destports)
1790                 keep = true;
1791         else
1792                 keep = false;
1793
1794         rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1795                                           l2_lookup.index, &l2_lookup, keep);
1796         if (rc < 0)
1797                 return rc;
1798
1799         return sja1105_static_fdb_change(priv, port, &l2_lookup, keep);
1800 }
1801
1802 static int sja1105_fdb_add(struct dsa_switch *ds, int port,
1803                            const unsigned char *addr, u16 vid)
1804 {
1805         struct sja1105_private *priv = ds->priv;
1806
1807         return priv->info->fdb_add_cmd(ds, port, addr, vid);
1808 }
1809
1810 static int sja1105_fdb_del(struct dsa_switch *ds, int port,
1811                            const unsigned char *addr, u16 vid)
1812 {
1813         struct sja1105_private *priv = ds->priv;
1814
1815         return priv->info->fdb_del_cmd(ds, port, addr, vid);
1816 }
1817
1818 static int sja1105_fdb_dump(struct dsa_switch *ds, int port,
1819                             dsa_fdb_dump_cb_t *cb, void *data)
1820 {
1821         struct dsa_port *dp = dsa_to_port(ds, port);
1822         struct sja1105_private *priv = ds->priv;
1823         struct device *dev = ds->dev;
1824         int i;
1825
1826         for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1827                 struct sja1105_l2_lookup_entry l2_lookup = {0};
1828                 u8 macaddr[ETH_ALEN];
1829                 int rc;
1830
1831                 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1832                                                  i, &l2_lookup);
1833                 /* No fdb entry at i, not an issue */
1834                 if (rc == -ENOENT)
1835                         continue;
1836                 if (rc) {
1837                         dev_err(dev, "Failed to dump FDB: %d\n", rc);
1838                         return rc;
1839                 }
1840
1841                 /* FDB dump callback is per port. This means we have to
1842                  * disregard a valid entry if it's not for this port, even if
1843                  * only to revisit it later. This is inefficient because the
1844                  * 1024-sized FDB table needs to be traversed 4 times through
1845                  * SPI during a 'bridge fdb show' command.
1846                  */
1847                 if (!(l2_lookup.destports & BIT(port)))
1848                         continue;
1849
1850                 /* We need to hide the FDB entry for unknown multicast */
1851                 if (l2_lookup.macaddr == SJA1105_UNKNOWN_MULTICAST &&
1852                     l2_lookup.mask_macaddr == SJA1105_UNKNOWN_MULTICAST)
1853                         continue;
1854
1855                 u64_to_ether_addr(l2_lookup.macaddr, macaddr);
1856
1857                 /* We need to hide the dsa_8021q VLANs from the user. */
1858                 if (!dsa_port_is_vlan_filtering(dp))
1859                         l2_lookup.vlanid = 0;
1860                 rc = cb(macaddr, l2_lookup.vlanid, l2_lookup.lockeds, data);
1861                 if (rc)
1862                         return rc;
1863         }
1864         return 0;
1865 }
1866
1867 static void sja1105_fast_age(struct dsa_switch *ds, int port)
1868 {
1869         struct sja1105_private *priv = ds->priv;
1870         int i;
1871
1872         for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1873                 struct sja1105_l2_lookup_entry l2_lookup = {0};
1874                 u8 macaddr[ETH_ALEN];
1875                 int rc;
1876
1877                 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1878                                                  i, &l2_lookup);
1879                 /* No fdb entry at i, not an issue */
1880                 if (rc == -ENOENT)
1881                         continue;
1882                 if (rc) {
1883                         dev_err(ds->dev, "Failed to read FDB: %pe\n",
1884                                 ERR_PTR(rc));
1885                         return;
1886                 }
1887
1888                 if (!(l2_lookup.destports & BIT(port)))
1889                         continue;
1890
1891                 /* Don't delete static FDB entries */
1892                 if (l2_lookup.lockeds)
1893                         continue;
1894
1895                 u64_to_ether_addr(l2_lookup.macaddr, macaddr);
1896
1897                 rc = sja1105_fdb_del(ds, port, macaddr, l2_lookup.vlanid);
1898                 if (rc) {
1899                         dev_err(ds->dev,
1900                                 "Failed to delete FDB entry %pM vid %lld: %pe\n",
1901                                 macaddr, l2_lookup.vlanid, ERR_PTR(rc));
1902                         return;
1903                 }
1904         }
1905 }
1906
1907 static int sja1105_mdb_add(struct dsa_switch *ds, int port,
1908                            const struct switchdev_obj_port_mdb *mdb)
1909 {
1910         return sja1105_fdb_add(ds, port, mdb->addr, mdb->vid);
1911 }
1912
1913 static int sja1105_mdb_del(struct dsa_switch *ds, int port,
1914                            const struct switchdev_obj_port_mdb *mdb)
1915 {
1916         return sja1105_fdb_del(ds, port, mdb->addr, mdb->vid);
1917 }
1918
1919 /* Common function for unicast and broadcast flood configuration.
1920  * Flooding is configured between each {ingress, egress} port pair, and since
1921  * the bridge's semantics are those of "egress flooding", it means we must
1922  * enable flooding towards this port from all ingress ports that are in the
1923  * same forwarding domain.
1924  */
1925 static int sja1105_manage_flood_domains(struct sja1105_private *priv)
1926 {
1927         struct sja1105_l2_forwarding_entry *l2_fwd;
1928         struct dsa_switch *ds = priv->ds;
1929         int from, to, rc;
1930
1931         l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries;
1932
1933         for (from = 0; from < ds->num_ports; from++) {
1934                 u64 fl_domain = 0, bc_domain = 0;
1935
1936                 for (to = 0; to < priv->ds->num_ports; to++) {
1937                         if (!sja1105_can_forward(l2_fwd, from, to))
1938                                 continue;
1939
1940                         if (priv->ucast_egress_floods & BIT(to))
1941                                 fl_domain |= BIT(to);
1942                         if (priv->bcast_egress_floods & BIT(to))
1943                                 bc_domain |= BIT(to);
1944                 }
1945
1946                 /* Nothing changed, nothing to do */
1947                 if (l2_fwd[from].fl_domain == fl_domain &&
1948                     l2_fwd[from].bc_domain == bc_domain)
1949                         continue;
1950
1951                 l2_fwd[from].fl_domain = fl_domain;
1952                 l2_fwd[from].bc_domain = bc_domain;
1953
1954                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
1955                                                   from, &l2_fwd[from], true);
1956                 if (rc < 0)
1957                         return rc;
1958         }
1959
1960         return 0;
1961 }
1962
1963 static int sja1105_bridge_member(struct dsa_switch *ds, int port,
1964                                  struct dsa_bridge bridge, bool member)
1965 {
1966         struct sja1105_l2_forwarding_entry *l2_fwd;
1967         struct sja1105_private *priv = ds->priv;
1968         int i, rc;
1969
1970         l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries;
1971
1972         for (i = 0; i < ds->num_ports; i++) {
1973                 /* Add this port to the forwarding matrix of the
1974                  * other ports in the same bridge, and viceversa.
1975                  */
1976                 if (!dsa_is_user_port(ds, i))
1977                         continue;
1978                 /* For the ports already under the bridge, only one thing needs
1979                  * to be done, and that is to add this port to their
1980                  * reachability domain. So we can perform the SPI write for
1981                  * them immediately. However, for this port itself (the one
1982                  * that is new to the bridge), we need to add all other ports
1983                  * to its reachability domain. So we do that incrementally in
1984                  * this loop, and perform the SPI write only at the end, once
1985                  * the domain contains all other bridge ports.
1986                  */
1987                 if (i == port)
1988                         continue;
1989                 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1990                         continue;
1991                 sja1105_port_allow_traffic(l2_fwd, i, port, member);
1992                 sja1105_port_allow_traffic(l2_fwd, port, i, member);
1993
1994                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
1995                                                   i, &l2_fwd[i], true);
1996                 if (rc < 0)
1997                         return rc;
1998         }
1999
2000         rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
2001                                           port, &l2_fwd[port], true);
2002         if (rc)
2003                 return rc;
2004
2005         rc = sja1105_commit_pvid(ds, port);
2006         if (rc)
2007                 return rc;
2008
2009         return sja1105_manage_flood_domains(priv);
2010 }
2011
2012 static void sja1105_bridge_stp_state_set(struct dsa_switch *ds, int port,
2013                                          u8 state)
2014 {
2015         struct dsa_port *dp = dsa_to_port(ds, port);
2016         struct sja1105_private *priv = ds->priv;
2017         struct sja1105_mac_config_entry *mac;
2018
2019         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2020
2021         switch (state) {
2022         case BR_STATE_DISABLED:
2023         case BR_STATE_BLOCKING:
2024                 /* From UM10944 description of DRPDTAG (why put this there?):
2025                  * "Management traffic flows to the port regardless of the state
2026                  * of the INGRESS flag". So BPDUs are still be allowed to pass.
2027                  * At the moment no difference between DISABLED and BLOCKING.
2028                  */
2029                 mac[port].ingress   = false;
2030                 mac[port].egress    = false;
2031                 mac[port].dyn_learn = false;
2032                 break;
2033         case BR_STATE_LISTENING:
2034                 mac[port].ingress   = true;
2035                 mac[port].egress    = false;
2036                 mac[port].dyn_learn = false;
2037                 break;
2038         case BR_STATE_LEARNING:
2039                 mac[port].ingress   = true;
2040                 mac[port].egress    = false;
2041                 mac[port].dyn_learn = dp->learning;
2042                 break;
2043         case BR_STATE_FORWARDING:
2044                 mac[port].ingress   = true;
2045                 mac[port].egress    = true;
2046                 mac[port].dyn_learn = dp->learning;
2047                 break;
2048         default:
2049                 dev_err(ds->dev, "invalid STP state: %d\n", state);
2050                 return;
2051         }
2052
2053         sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
2054                                      &mac[port], true);
2055 }
2056
2057 static int sja1105_bridge_join(struct dsa_switch *ds, int port,
2058                                struct dsa_bridge bridge,
2059                                bool *tx_fwd_offload)
2060 {
2061         int rc;
2062
2063         rc = sja1105_bridge_member(ds, port, bridge, true);
2064         if (rc)
2065                 return rc;
2066
2067         rc = dsa_tag_8021q_bridge_tx_fwd_offload(ds, port, bridge);
2068         if (rc) {
2069                 sja1105_bridge_member(ds, port, bridge, false);
2070                 return rc;
2071         }
2072
2073         *tx_fwd_offload = true;
2074
2075         return 0;
2076 }
2077
2078 static void sja1105_bridge_leave(struct dsa_switch *ds, int port,
2079                                  struct dsa_bridge bridge)
2080 {
2081         dsa_tag_8021q_bridge_tx_fwd_unoffload(ds, port, bridge);
2082         sja1105_bridge_member(ds, port, bridge, false);
2083 }
2084
2085 #define BYTES_PER_KBIT (1000LL / 8)
2086
2087 static int sja1105_find_unused_cbs_shaper(struct sja1105_private *priv)
2088 {
2089         int i;
2090
2091         for (i = 0; i < priv->info->num_cbs_shapers; i++)
2092                 if (!priv->cbs[i].idle_slope && !priv->cbs[i].send_slope)
2093                         return i;
2094
2095         return -1;
2096 }
2097
2098 static int sja1105_delete_cbs_shaper(struct sja1105_private *priv, int port,
2099                                      int prio)
2100 {
2101         int i;
2102
2103         for (i = 0; i < priv->info->num_cbs_shapers; i++) {
2104                 struct sja1105_cbs_entry *cbs = &priv->cbs[i];
2105
2106                 if (cbs->port == port && cbs->prio == prio) {
2107                         memset(cbs, 0, sizeof(*cbs));
2108                         return sja1105_dynamic_config_write(priv, BLK_IDX_CBS,
2109                                                             i, cbs, true);
2110                 }
2111         }
2112
2113         return 0;
2114 }
2115
2116 static int sja1105_setup_tc_cbs(struct dsa_switch *ds, int port,
2117                                 struct tc_cbs_qopt_offload *offload)
2118 {
2119         struct sja1105_private *priv = ds->priv;
2120         struct sja1105_cbs_entry *cbs;
2121         int index;
2122
2123         if (!offload->enable)
2124                 return sja1105_delete_cbs_shaper(priv, port, offload->queue);
2125
2126         index = sja1105_find_unused_cbs_shaper(priv);
2127         if (index < 0)
2128                 return -ENOSPC;
2129
2130         cbs = &priv->cbs[index];
2131         cbs->port = port;
2132         cbs->prio = offload->queue;
2133         /* locredit and sendslope are negative by definition. In hardware,
2134          * positive values must be provided, and the negative sign is implicit.
2135          */
2136         cbs->credit_hi = offload->hicredit;
2137         cbs->credit_lo = abs(offload->locredit);
2138         /* User space is in kbits/sec, hardware in bytes/sec */
2139         cbs->idle_slope = offload->idleslope * BYTES_PER_KBIT;
2140         cbs->send_slope = abs(offload->sendslope * BYTES_PER_KBIT);
2141         /* Convert the negative values from 64-bit 2's complement
2142          * to 32-bit 2's complement (for the case of 0x80000000 whose
2143          * negative is still negative).
2144          */
2145         cbs->credit_lo &= GENMASK_ULL(31, 0);
2146         cbs->send_slope &= GENMASK_ULL(31, 0);
2147
2148         return sja1105_dynamic_config_write(priv, BLK_IDX_CBS, index, cbs,
2149                                             true);
2150 }
2151
2152 static int sja1105_reload_cbs(struct sja1105_private *priv)
2153 {
2154         int rc = 0, i;
2155
2156         /* The credit based shapers are only allocated if
2157          * CONFIG_NET_SCH_CBS is enabled.
2158          */
2159         if (!priv->cbs)
2160                 return 0;
2161
2162         for (i = 0; i < priv->info->num_cbs_shapers; i++) {
2163                 struct sja1105_cbs_entry *cbs = &priv->cbs[i];
2164
2165                 if (!cbs->idle_slope && !cbs->send_slope)
2166                         continue;
2167
2168                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_CBS, i, cbs,
2169                                                   true);
2170                 if (rc)
2171                         break;
2172         }
2173
2174         return rc;
2175 }
2176
2177 static const char * const sja1105_reset_reasons[] = {
2178         [SJA1105_VLAN_FILTERING] = "VLAN filtering",
2179         [SJA1105_RX_HWTSTAMPING] = "RX timestamping",
2180         [SJA1105_AGEING_TIME] = "Ageing time",
2181         [SJA1105_SCHEDULING] = "Time-aware scheduling",
2182         [SJA1105_BEST_EFFORT_POLICING] = "Best-effort policing",
2183         [SJA1105_VIRTUAL_LINKS] = "Virtual links",
2184 };
2185
2186 /* For situations where we need to change a setting at runtime that is only
2187  * available through the static configuration, resetting the switch in order
2188  * to upload the new static config is unavoidable. Back up the settings we
2189  * modify at runtime (currently only MAC) and restore them after uploading,
2190  * such that this operation is relatively seamless.
2191  */
2192 int sja1105_static_config_reload(struct sja1105_private *priv,
2193                                  enum sja1105_reset_reason reason)
2194 {
2195         struct ptp_system_timestamp ptp_sts_before;
2196         struct ptp_system_timestamp ptp_sts_after;
2197         int speed_mbps[SJA1105_MAX_NUM_PORTS];
2198         u16 bmcr[SJA1105_MAX_NUM_PORTS] = {0};
2199         struct sja1105_mac_config_entry *mac;
2200         struct dsa_switch *ds = priv->ds;
2201         s64 t1, t2, t3, t4;
2202         s64 t12, t34;
2203         int rc, i;
2204         s64 now;
2205
2206         mutex_lock(&priv->mgmt_lock);
2207
2208         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2209
2210         /* Back up the dynamic link speed changed by sja1105_adjust_port_config
2211          * in order to temporarily restore it to SJA1105_SPEED_AUTO - which the
2212          * switch wants to see in the static config in order to allow us to
2213          * change it through the dynamic interface later.
2214          */
2215         for (i = 0; i < ds->num_ports; i++) {
2216                 u32 reg_addr = mdiobus_c45_addr(MDIO_MMD_VEND2, MDIO_CTRL1);
2217
2218                 speed_mbps[i] = sja1105_port_speed_to_ethtool(priv,
2219                                                               mac[i].speed);
2220                 mac[i].speed = priv->info->port_speed[SJA1105_SPEED_AUTO];
2221
2222                 if (priv->xpcs[i])
2223                         bmcr[i] = mdiobus_read(priv->mdio_pcs, i, reg_addr);
2224         }
2225
2226         /* No PTP operations can run right now */
2227         mutex_lock(&priv->ptp_data.lock);
2228
2229         rc = __sja1105_ptp_gettimex(ds, &now, &ptp_sts_before);
2230         if (rc < 0) {
2231                 mutex_unlock(&priv->ptp_data.lock);
2232                 goto out;
2233         }
2234
2235         /* Reset switch and send updated static configuration */
2236         rc = sja1105_static_config_upload(priv);
2237         if (rc < 0) {
2238                 mutex_unlock(&priv->ptp_data.lock);
2239                 goto out;
2240         }
2241
2242         rc = __sja1105_ptp_settime(ds, 0, &ptp_sts_after);
2243         if (rc < 0) {
2244                 mutex_unlock(&priv->ptp_data.lock);
2245                 goto out;
2246         }
2247
2248         t1 = timespec64_to_ns(&ptp_sts_before.pre_ts);
2249         t2 = timespec64_to_ns(&ptp_sts_before.post_ts);
2250         t3 = timespec64_to_ns(&ptp_sts_after.pre_ts);
2251         t4 = timespec64_to_ns(&ptp_sts_after.post_ts);
2252         /* Mid point, corresponds to pre-reset PTPCLKVAL */
2253         t12 = t1 + (t2 - t1) / 2;
2254         /* Mid point, corresponds to post-reset PTPCLKVAL, aka 0 */
2255         t34 = t3 + (t4 - t3) / 2;
2256         /* Advance PTPCLKVAL by the time it took since its readout */
2257         now += (t34 - t12);
2258
2259         __sja1105_ptp_adjtime(ds, now);
2260
2261         mutex_unlock(&priv->ptp_data.lock);
2262
2263         dev_info(priv->ds->dev,
2264                  "Reset switch and programmed static config. Reason: %s\n",
2265                  sja1105_reset_reasons[reason]);
2266
2267         /* Configure the CGU (PLLs) for MII and RMII PHYs.
2268          * For these interfaces there is no dynamic configuration
2269          * needed, since PLLs have same settings at all speeds.
2270          */
2271         if (priv->info->clocking_setup) {
2272                 rc = priv->info->clocking_setup(priv);
2273                 if (rc < 0)
2274                         goto out;
2275         }
2276
2277         for (i = 0; i < ds->num_ports; i++) {
2278                 struct dw_xpcs *xpcs = priv->xpcs[i];
2279                 unsigned int mode;
2280
2281                 rc = sja1105_adjust_port_config(priv, i, speed_mbps[i]);
2282                 if (rc < 0)
2283                         goto out;
2284
2285                 if (!xpcs)
2286                         continue;
2287
2288                 if (bmcr[i] & BMCR_ANENABLE)
2289                         mode = MLO_AN_INBAND;
2290                 else if (priv->fixed_link[i])
2291                         mode = MLO_AN_FIXED;
2292                 else
2293                         mode = MLO_AN_PHY;
2294
2295                 rc = xpcs_do_config(xpcs, priv->phy_mode[i], mode);
2296                 if (rc < 0)
2297                         goto out;
2298
2299                 if (!phylink_autoneg_inband(mode)) {
2300                         int speed = SPEED_UNKNOWN;
2301
2302                         if (priv->phy_mode[i] == PHY_INTERFACE_MODE_2500BASEX)
2303                                 speed = SPEED_2500;
2304                         else if (bmcr[i] & BMCR_SPEED1000)
2305                                 speed = SPEED_1000;
2306                         else if (bmcr[i] & BMCR_SPEED100)
2307                                 speed = SPEED_100;
2308                         else
2309                                 speed = SPEED_10;
2310
2311                         xpcs_link_up(&xpcs->pcs, mode, priv->phy_mode[i],
2312                                      speed, DUPLEX_FULL);
2313                 }
2314         }
2315
2316         rc = sja1105_reload_cbs(priv);
2317         if (rc < 0)
2318                 goto out;
2319 out:
2320         mutex_unlock(&priv->mgmt_lock);
2321
2322         return rc;
2323 }
2324
2325 static enum dsa_tag_protocol
2326 sja1105_get_tag_protocol(struct dsa_switch *ds, int port,
2327                          enum dsa_tag_protocol mp)
2328 {
2329         struct sja1105_private *priv = ds->priv;
2330
2331         return priv->info->tag_proto;
2332 }
2333
2334 /* The TPID setting belongs to the General Parameters table,
2335  * which can only be partially reconfigured at runtime (and not the TPID).
2336  * So a switch reset is required.
2337  */
2338 int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled,
2339                            struct netlink_ext_ack *extack)
2340 {
2341         struct sja1105_l2_lookup_params_entry *l2_lookup_params;
2342         struct sja1105_general_params_entry *general_params;
2343         struct sja1105_private *priv = ds->priv;
2344         struct sja1105_table *table;
2345         struct sja1105_rule *rule;
2346         u16 tpid, tpid2;
2347         int rc;
2348
2349         list_for_each_entry(rule, &priv->flow_block.rules, list) {
2350                 if (rule->type == SJA1105_RULE_VL) {
2351                         NL_SET_ERR_MSG_MOD(extack,
2352                                            "Cannot change VLAN filtering with active VL rules");
2353                         return -EBUSY;
2354                 }
2355         }
2356
2357         if (enabled) {
2358                 /* Enable VLAN filtering. */
2359                 tpid  = ETH_P_8021Q;
2360                 tpid2 = ETH_P_8021AD;
2361         } else {
2362                 /* Disable VLAN filtering. */
2363                 tpid  = ETH_P_SJA1105;
2364                 tpid2 = ETH_P_SJA1105;
2365         }
2366
2367         table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
2368         general_params = table->entries;
2369         /* EtherType used to identify inner tagged (C-tag) VLAN traffic */
2370         general_params->tpid = tpid;
2371         /* EtherType used to identify outer tagged (S-tag) VLAN traffic */
2372         general_params->tpid2 = tpid2;
2373         /* When VLAN filtering is on, we need to at least be able to
2374          * decode management traffic through the "backup plan".
2375          */
2376         general_params->incl_srcpt1 = enabled;
2377         general_params->incl_srcpt0 = enabled;
2378
2379         /* VLAN filtering => independent VLAN learning.
2380          * No VLAN filtering (or best effort) => shared VLAN learning.
2381          *
2382          * In shared VLAN learning mode, untagged traffic still gets
2383          * pvid-tagged, and the FDB table gets populated with entries
2384          * containing the "real" (pvid or from VLAN tag) VLAN ID.
2385          * However the switch performs a masked L2 lookup in the FDB,
2386          * effectively only looking up a frame's DMAC (and not VID) for the
2387          * forwarding decision.
2388          *
2389          * This is extremely convenient for us, because in modes with
2390          * vlan_filtering=0, dsa_8021q actually installs unique pvid's into
2391          * each front panel port. This is good for identification but breaks
2392          * learning badly - the VID of the learnt FDB entry is unique, aka
2393          * no frames coming from any other port are going to have it. So
2394          * for forwarding purposes, this is as though learning was broken
2395          * (all frames get flooded).
2396          */
2397         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS];
2398         l2_lookup_params = table->entries;
2399         l2_lookup_params->shared_learn = !enabled;
2400
2401         for (port = 0; port < ds->num_ports; port++) {
2402                 if (dsa_is_unused_port(ds, port))
2403                         continue;
2404
2405                 rc = sja1105_commit_pvid(ds, port);
2406                 if (rc)
2407                         return rc;
2408         }
2409
2410         rc = sja1105_static_config_reload(priv, SJA1105_VLAN_FILTERING);
2411         if (rc)
2412                 NL_SET_ERR_MSG_MOD(extack, "Failed to change VLAN Ethertype");
2413
2414         return rc;
2415 }
2416
2417 static int sja1105_vlan_add(struct sja1105_private *priv, int port, u16 vid,
2418                             u16 flags, bool allowed_ingress)
2419 {
2420         struct sja1105_vlan_lookup_entry *vlan;
2421         struct sja1105_table *table;
2422         int match, rc;
2423
2424         table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
2425
2426         match = sja1105_is_vlan_configured(priv, vid);
2427         if (match < 0) {
2428                 rc = sja1105_table_resize(table, table->entry_count + 1);
2429                 if (rc)
2430                         return rc;
2431                 match = table->entry_count - 1;
2432         }
2433
2434         /* Assign pointer after the resize (it's new memory) */
2435         vlan = table->entries;
2436
2437         vlan[match].type_entry = SJA1110_VLAN_D_TAG;
2438         vlan[match].vlanid = vid;
2439         vlan[match].vlan_bc |= BIT(port);
2440
2441         if (allowed_ingress)
2442                 vlan[match].vmemb_port |= BIT(port);
2443         else
2444                 vlan[match].vmemb_port &= ~BIT(port);
2445
2446         if (flags & BRIDGE_VLAN_INFO_UNTAGGED)
2447                 vlan[match].tag_port &= ~BIT(port);
2448         else
2449                 vlan[match].tag_port |= BIT(port);
2450
2451         return sja1105_dynamic_config_write(priv, BLK_IDX_VLAN_LOOKUP, vid,
2452                                             &vlan[match], true);
2453 }
2454
2455 static int sja1105_vlan_del(struct sja1105_private *priv, int port, u16 vid)
2456 {
2457         struct sja1105_vlan_lookup_entry *vlan;
2458         struct sja1105_table *table;
2459         bool keep = true;
2460         int match, rc;
2461
2462         table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
2463
2464         match = sja1105_is_vlan_configured(priv, vid);
2465         /* Can't delete a missing entry. */
2466         if (match < 0)
2467                 return 0;
2468
2469         /* Assign pointer after the resize (it's new memory) */
2470         vlan = table->entries;
2471
2472         vlan[match].vlanid = vid;
2473         vlan[match].vlan_bc &= ~BIT(port);
2474         vlan[match].vmemb_port &= ~BIT(port);
2475         /* Also unset tag_port, just so we don't have a confusing bitmap
2476          * (no practical purpose).
2477          */
2478         vlan[match].tag_port &= ~BIT(port);
2479
2480         /* If there's no port left as member of this VLAN,
2481          * it's time for it to go.
2482          */
2483         if (!vlan[match].vmemb_port)
2484                 keep = false;
2485
2486         rc = sja1105_dynamic_config_write(priv, BLK_IDX_VLAN_LOOKUP, vid,
2487                                           &vlan[match], keep);
2488         if (rc < 0)
2489                 return rc;
2490
2491         if (!keep)
2492                 return sja1105_table_delete_entry(table, match);
2493
2494         return 0;
2495 }
2496
2497 static int sja1105_bridge_vlan_add(struct dsa_switch *ds, int port,
2498                                    const struct switchdev_obj_port_vlan *vlan,
2499                                    struct netlink_ext_ack *extack)
2500 {
2501         struct sja1105_private *priv = ds->priv;
2502         u16 flags = vlan->flags;
2503         int rc;
2504
2505         /* Be sure to deny alterations to the configuration done by tag_8021q.
2506          */
2507         if (vid_is_dsa_8021q(vlan->vid)) {
2508                 NL_SET_ERR_MSG_MOD(extack,
2509                                    "Range 1024-3071 reserved for dsa_8021q operation");
2510                 return -EBUSY;
2511         }
2512
2513         /* Always install bridge VLANs as egress-tagged on CPU and DSA ports */
2514         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2515                 flags = 0;
2516
2517         rc = sja1105_vlan_add(priv, port, vlan->vid, flags, true);
2518         if (rc)
2519                 return rc;
2520
2521         if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
2522                 priv->bridge_pvid[port] = vlan->vid;
2523
2524         return sja1105_commit_pvid(ds, port);
2525 }
2526
2527 static int sja1105_bridge_vlan_del(struct dsa_switch *ds, int port,
2528                                    const struct switchdev_obj_port_vlan *vlan)
2529 {
2530         struct sja1105_private *priv = ds->priv;
2531         int rc;
2532
2533         rc = sja1105_vlan_del(priv, port, vlan->vid);
2534         if (rc)
2535                 return rc;
2536
2537         /* In case the pvid was deleted, make sure that untagged packets will
2538          * be dropped.
2539          */
2540         return sja1105_commit_pvid(ds, port);
2541 }
2542
2543 static int sja1105_dsa_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid,
2544                                       u16 flags)
2545 {
2546         struct sja1105_private *priv = ds->priv;
2547         bool allowed_ingress = true;
2548         int rc;
2549
2550         /* Prevent attackers from trying to inject a DSA tag from
2551          * the outside world.
2552          */
2553         if (dsa_is_user_port(ds, port))
2554                 allowed_ingress = false;
2555
2556         rc = sja1105_vlan_add(priv, port, vid, flags, allowed_ingress);
2557         if (rc)
2558                 return rc;
2559
2560         if (flags & BRIDGE_VLAN_INFO_PVID)
2561                 priv->tag_8021q_pvid[port] = vid;
2562
2563         return sja1105_commit_pvid(ds, port);
2564 }
2565
2566 static int sja1105_dsa_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid)
2567 {
2568         struct sja1105_private *priv = ds->priv;
2569
2570         return sja1105_vlan_del(priv, port, vid);
2571 }
2572
2573 static int sja1105_prechangeupper(struct dsa_switch *ds, int port,
2574                                   struct netdev_notifier_changeupper_info *info)
2575 {
2576         struct netlink_ext_ack *extack = info->info.extack;
2577         struct net_device *upper = info->upper_dev;
2578         struct dsa_switch_tree *dst = ds->dst;
2579         struct dsa_port *dp;
2580
2581         if (is_vlan_dev(upper)) {
2582                 NL_SET_ERR_MSG_MOD(extack, "8021q uppers are not supported");
2583                 return -EBUSY;
2584         }
2585
2586         if (netif_is_bridge_master(upper)) {
2587                 list_for_each_entry(dp, &dst->ports, list) {
2588                         struct net_device *br = dsa_port_bridge_dev_get(dp);
2589
2590                         if (br && br != upper && br_vlan_enabled(br)) {
2591                                 NL_SET_ERR_MSG_MOD(extack,
2592                                                    "Only one VLAN-aware bridge is supported");
2593                                 return -EBUSY;
2594                         }
2595                 }
2596         }
2597
2598         return 0;
2599 }
2600
2601 static int sja1105_mgmt_xmit(struct dsa_switch *ds, int port, int slot,
2602                              struct sk_buff *skb, bool takets)
2603 {
2604         struct sja1105_mgmt_entry mgmt_route = {0};
2605         struct sja1105_private *priv = ds->priv;
2606         struct ethhdr *hdr;
2607         int timeout = 10;
2608         int rc;
2609
2610         hdr = eth_hdr(skb);
2611
2612         mgmt_route.macaddr = ether_addr_to_u64(hdr->h_dest);
2613         mgmt_route.destports = BIT(port);
2614         mgmt_route.enfport = 1;
2615         mgmt_route.tsreg = 0;
2616         mgmt_route.takets = takets;
2617
2618         rc = sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE,
2619                                           slot, &mgmt_route, true);
2620         if (rc < 0) {
2621                 kfree_skb(skb);
2622                 return rc;
2623         }
2624
2625         /* Transfer skb to the host port. */
2626         dsa_enqueue_skb(skb, dsa_to_port(ds, port)->slave);
2627
2628         /* Wait until the switch has processed the frame */
2629         do {
2630                 rc = sja1105_dynamic_config_read(priv, BLK_IDX_MGMT_ROUTE,
2631                                                  slot, &mgmt_route);
2632                 if (rc < 0) {
2633                         dev_err_ratelimited(priv->ds->dev,
2634                                             "failed to poll for mgmt route\n");
2635                         continue;
2636                 }
2637
2638                 /* UM10944: The ENFPORT flag of the respective entry is
2639                  * cleared when a match is found. The host can use this
2640                  * flag as an acknowledgment.
2641                  */
2642                 cpu_relax();
2643         } while (mgmt_route.enfport && --timeout);
2644
2645         if (!timeout) {
2646                 /* Clean up the management route so that a follow-up
2647                  * frame may not match on it by mistake.
2648                  * This is only hardware supported on P/Q/R/S - on E/T it is
2649                  * a no-op and we are silently discarding the -EOPNOTSUPP.
2650                  */
2651                 sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE,
2652                                              slot, &mgmt_route, false);
2653                 dev_err_ratelimited(priv->ds->dev, "xmit timed out\n");
2654         }
2655
2656         return NETDEV_TX_OK;
2657 }
2658
2659 #define work_to_xmit_work(w) \
2660                 container_of((w), struct sja1105_deferred_xmit_work, work)
2661
2662 /* Deferred work is unfortunately necessary because setting up the management
2663  * route cannot be done from atomit context (SPI transfer takes a sleepable
2664  * lock on the bus)
2665  */
2666 static void sja1105_port_deferred_xmit(struct kthread_work *work)
2667 {
2668         struct sja1105_deferred_xmit_work *xmit_work = work_to_xmit_work(work);
2669         struct sk_buff *clone, *skb = xmit_work->skb;
2670         struct dsa_switch *ds = xmit_work->dp->ds;
2671         struct sja1105_private *priv = ds->priv;
2672         int port = xmit_work->dp->index;
2673
2674         clone = SJA1105_SKB_CB(skb)->clone;
2675
2676         mutex_lock(&priv->mgmt_lock);
2677
2678         sja1105_mgmt_xmit(ds, port, 0, skb, !!clone);
2679
2680         /* The clone, if there, was made by dsa_skb_tx_timestamp */
2681         if (clone)
2682                 sja1105_ptp_txtstamp_skb(ds, port, clone);
2683
2684         mutex_unlock(&priv->mgmt_lock);
2685
2686         kfree(xmit_work);
2687 }
2688
2689 static int sja1105_connect_tag_protocol(struct dsa_switch *ds,
2690                                         enum dsa_tag_protocol proto)
2691 {
2692         struct sja1105_private *priv = ds->priv;
2693         struct sja1105_tagger_data *tagger_data;
2694
2695         if (proto != priv->info->tag_proto)
2696                 return -EPROTONOSUPPORT;
2697
2698         tagger_data = sja1105_tagger_data(ds);
2699         tagger_data->xmit_work_fn = sja1105_port_deferred_xmit;
2700         tagger_data->meta_tstamp_handler = sja1110_process_meta_tstamp;
2701
2702         return 0;
2703 }
2704
2705 /* The MAXAGE setting belongs to the L2 Forwarding Parameters table,
2706  * which cannot be reconfigured at runtime. So a switch reset is required.
2707  */
2708 static int sja1105_set_ageing_time(struct dsa_switch *ds,
2709                                    unsigned int ageing_time)
2710 {
2711         struct sja1105_l2_lookup_params_entry *l2_lookup_params;
2712         struct sja1105_private *priv = ds->priv;
2713         struct sja1105_table *table;
2714         unsigned int maxage;
2715
2716         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS];
2717         l2_lookup_params = table->entries;
2718
2719         maxage = SJA1105_AGEING_TIME_MS(ageing_time);
2720
2721         if (l2_lookup_params->maxage == maxage)
2722                 return 0;
2723
2724         l2_lookup_params->maxage = maxage;
2725
2726         return sja1105_static_config_reload(priv, SJA1105_AGEING_TIME);
2727 }
2728
2729 static int sja1105_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
2730 {
2731         struct sja1105_l2_policing_entry *policing;
2732         struct sja1105_private *priv = ds->priv;
2733
2734         new_mtu += VLAN_ETH_HLEN + ETH_FCS_LEN;
2735
2736         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2737                 new_mtu += VLAN_HLEN;
2738
2739         policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2740
2741         if (policing[port].maxlen == new_mtu)
2742                 return 0;
2743
2744         policing[port].maxlen = new_mtu;
2745
2746         return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2747 }
2748
2749 static int sja1105_get_max_mtu(struct dsa_switch *ds, int port)
2750 {
2751         return 2043 - VLAN_ETH_HLEN - ETH_FCS_LEN;
2752 }
2753
2754 static int sja1105_port_setup_tc(struct dsa_switch *ds, int port,
2755                                  enum tc_setup_type type,
2756                                  void *type_data)
2757 {
2758         switch (type) {
2759         case TC_SETUP_QDISC_TAPRIO:
2760                 return sja1105_setup_tc_taprio(ds, port, type_data);
2761         case TC_SETUP_QDISC_CBS:
2762                 return sja1105_setup_tc_cbs(ds, port, type_data);
2763         default:
2764                 return -EOPNOTSUPP;
2765         }
2766 }
2767
2768 /* We have a single mirror (@to) port, but can configure ingress and egress
2769  * mirroring on all other (@from) ports.
2770  * We need to allow mirroring rules only as long as the @to port is always the
2771  * same, and we need to unset the @to port from mirr_port only when there is no
2772  * mirroring rule that references it.
2773  */
2774 static int sja1105_mirror_apply(struct sja1105_private *priv, int from, int to,
2775                                 bool ingress, bool enabled)
2776 {
2777         struct sja1105_general_params_entry *general_params;
2778         struct sja1105_mac_config_entry *mac;
2779         struct dsa_switch *ds = priv->ds;
2780         struct sja1105_table *table;
2781         bool already_enabled;
2782         u64 new_mirr_port;
2783         int rc;
2784
2785         table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
2786         general_params = table->entries;
2787
2788         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2789
2790         already_enabled = (general_params->mirr_port != ds->num_ports);
2791         if (already_enabled && enabled && general_params->mirr_port != to) {
2792                 dev_err(priv->ds->dev,
2793                         "Delete mirroring rules towards port %llu first\n",
2794                         general_params->mirr_port);
2795                 return -EBUSY;
2796         }
2797
2798         new_mirr_port = to;
2799         if (!enabled) {
2800                 bool keep = false;
2801                 int port;
2802
2803                 /* Anybody still referencing mirr_port? */
2804                 for (port = 0; port < ds->num_ports; port++) {
2805                         if (mac[port].ing_mirr || mac[port].egr_mirr) {
2806                                 keep = true;
2807                                 break;
2808                         }
2809                 }
2810                 /* Unset already_enabled for next time */
2811                 if (!keep)
2812                         new_mirr_port = ds->num_ports;
2813         }
2814         if (new_mirr_port != general_params->mirr_port) {
2815                 general_params->mirr_port = new_mirr_port;
2816
2817                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_GENERAL_PARAMS,
2818                                                   0, general_params, true);
2819                 if (rc < 0)
2820                         return rc;
2821         }
2822
2823         if (ingress)
2824                 mac[from].ing_mirr = enabled;
2825         else
2826                 mac[from].egr_mirr = enabled;
2827
2828         return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, from,
2829                                             &mac[from], true);
2830 }
2831
2832 static int sja1105_mirror_add(struct dsa_switch *ds, int port,
2833                               struct dsa_mall_mirror_tc_entry *mirror,
2834                               bool ingress)
2835 {
2836         return sja1105_mirror_apply(ds->priv, port, mirror->to_local_port,
2837                                     ingress, true);
2838 }
2839
2840 static void sja1105_mirror_del(struct dsa_switch *ds, int port,
2841                                struct dsa_mall_mirror_tc_entry *mirror)
2842 {
2843         sja1105_mirror_apply(ds->priv, port, mirror->to_local_port,
2844                              mirror->ingress, false);
2845 }
2846
2847 static int sja1105_port_policer_add(struct dsa_switch *ds, int port,
2848                                     struct dsa_mall_policer_tc_entry *policer)
2849 {
2850         struct sja1105_l2_policing_entry *policing;
2851         struct sja1105_private *priv = ds->priv;
2852
2853         policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2854
2855         /* In hardware, every 8 microseconds the credit level is incremented by
2856          * the value of RATE bytes divided by 64, up to a maximum of SMAX
2857          * bytes.
2858          */
2859         policing[port].rate = div_u64(512 * policer->rate_bytes_per_sec,
2860                                       1000000);
2861         policing[port].smax = policer->burst;
2862
2863         return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2864 }
2865
2866 static void sja1105_port_policer_del(struct dsa_switch *ds, int port)
2867 {
2868         struct sja1105_l2_policing_entry *policing;
2869         struct sja1105_private *priv = ds->priv;
2870
2871         policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2872
2873         policing[port].rate = SJA1105_RATE_MBPS(1000);
2874         policing[port].smax = 65535;
2875
2876         sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2877 }
2878
2879 static int sja1105_port_set_learning(struct sja1105_private *priv, int port,
2880                                      bool enabled)
2881 {
2882         struct sja1105_mac_config_entry *mac;
2883
2884         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2885
2886         mac[port].dyn_learn = enabled;
2887
2888         return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
2889                                             &mac[port], true);
2890 }
2891
2892 static int sja1105_port_ucast_bcast_flood(struct sja1105_private *priv, int to,
2893                                           struct switchdev_brport_flags flags)
2894 {
2895         if (flags.mask & BR_FLOOD) {
2896                 if (flags.val & BR_FLOOD)
2897                         priv->ucast_egress_floods |= BIT(to);
2898                 else
2899                         priv->ucast_egress_floods &= ~BIT(to);
2900         }
2901
2902         if (flags.mask & BR_BCAST_FLOOD) {
2903                 if (flags.val & BR_BCAST_FLOOD)
2904                         priv->bcast_egress_floods |= BIT(to);
2905                 else
2906                         priv->bcast_egress_floods &= ~BIT(to);
2907         }
2908
2909         return sja1105_manage_flood_domains(priv);
2910 }
2911
2912 static int sja1105_port_mcast_flood(struct sja1105_private *priv, int to,
2913                                     struct switchdev_brport_flags flags,
2914                                     struct netlink_ext_ack *extack)
2915 {
2916         struct sja1105_l2_lookup_entry *l2_lookup;
2917         struct sja1105_table *table;
2918         int match;
2919
2920         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
2921         l2_lookup = table->entries;
2922
2923         for (match = 0; match < table->entry_count; match++)
2924                 if (l2_lookup[match].macaddr == SJA1105_UNKNOWN_MULTICAST &&
2925                     l2_lookup[match].mask_macaddr == SJA1105_UNKNOWN_MULTICAST)
2926                         break;
2927
2928         if (match == table->entry_count) {
2929                 NL_SET_ERR_MSG_MOD(extack,
2930                                    "Could not find FDB entry for unknown multicast");
2931                 return -ENOSPC;
2932         }
2933
2934         if (flags.val & BR_MCAST_FLOOD)
2935                 l2_lookup[match].destports |= BIT(to);
2936         else
2937                 l2_lookup[match].destports &= ~BIT(to);
2938
2939         return sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
2940                                             l2_lookup[match].index,
2941                                             &l2_lookup[match],
2942                                             true);
2943 }
2944
2945 static int sja1105_port_pre_bridge_flags(struct dsa_switch *ds, int port,
2946                                          struct switchdev_brport_flags flags,
2947                                          struct netlink_ext_ack *extack)
2948 {
2949         struct sja1105_private *priv = ds->priv;
2950
2951         if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
2952                            BR_BCAST_FLOOD))
2953                 return -EINVAL;
2954
2955         if (flags.mask & (BR_FLOOD | BR_MCAST_FLOOD) &&
2956             !priv->info->can_limit_mcast_flood) {
2957                 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
2958                 bool unicast = !!(flags.val & BR_FLOOD);
2959
2960                 if (unicast != multicast) {
2961                         NL_SET_ERR_MSG_MOD(extack,
2962                                            "This chip cannot configure multicast flooding independently of unicast");
2963                         return -EINVAL;
2964                 }
2965         }
2966
2967         return 0;
2968 }
2969
2970 static int sja1105_port_bridge_flags(struct dsa_switch *ds, int port,
2971                                      struct switchdev_brport_flags flags,
2972                                      struct netlink_ext_ack *extack)
2973 {
2974         struct sja1105_private *priv = ds->priv;
2975         int rc;
2976
2977         if (flags.mask & BR_LEARNING) {
2978                 bool learn_ena = !!(flags.val & BR_LEARNING);
2979
2980                 rc = sja1105_port_set_learning(priv, port, learn_ena);
2981                 if (rc)
2982                         return rc;
2983         }
2984
2985         if (flags.mask & (BR_FLOOD | BR_BCAST_FLOOD)) {
2986                 rc = sja1105_port_ucast_bcast_flood(priv, port, flags);
2987                 if (rc)
2988                         return rc;
2989         }
2990
2991         /* For chips that can't offload BR_MCAST_FLOOD independently, there
2992          * is nothing to do here, we ensured the configuration is in sync by
2993          * offloading BR_FLOOD.
2994          */
2995         if (flags.mask & BR_MCAST_FLOOD && priv->info->can_limit_mcast_flood) {
2996                 rc = sja1105_port_mcast_flood(priv, port, flags,
2997                                               extack);
2998                 if (rc)
2999                         return rc;
3000         }
3001
3002         return 0;
3003 }
3004
3005 /* The programming model for the SJA1105 switch is "all-at-once" via static
3006  * configuration tables. Some of these can be dynamically modified at runtime,
3007  * but not the xMII mode parameters table.
3008  * Furthermode, some PHYs may not have crystals for generating their clocks
3009  * (e.g. RMII). Instead, their 50MHz clock is supplied via the SJA1105 port's
3010  * ref_clk pin. So port clocking needs to be initialized early, before
3011  * connecting to PHYs is attempted, otherwise they won't respond through MDIO.
3012  * Setting correct PHY link speed does not matter now.
3013  * But dsa_slave_phy_setup is called later than sja1105_setup, so the PHY
3014  * bindings are not yet parsed by DSA core. We need to parse early so that we
3015  * can populate the xMII mode parameters table.
3016  */
3017 static int sja1105_setup(struct dsa_switch *ds)
3018 {
3019         struct sja1105_private *priv = ds->priv;
3020         int rc;
3021
3022         if (priv->info->disable_microcontroller) {
3023                 rc = priv->info->disable_microcontroller(priv);
3024                 if (rc < 0) {
3025                         dev_err(ds->dev,
3026                                 "Failed to disable microcontroller: %pe\n",
3027                                 ERR_PTR(rc));
3028                         return rc;
3029                 }
3030         }
3031
3032         /* Create and send configuration down to device */
3033         rc = sja1105_static_config_load(priv);
3034         if (rc < 0) {
3035                 dev_err(ds->dev, "Failed to load static config: %d\n", rc);
3036                 return rc;
3037         }
3038
3039         /* Configure the CGU (PHY link modes and speeds) */
3040         if (priv->info->clocking_setup) {
3041                 rc = priv->info->clocking_setup(priv);
3042                 if (rc < 0) {
3043                         dev_err(ds->dev,
3044                                 "Failed to configure MII clocking: %pe\n",
3045                                 ERR_PTR(rc));
3046                         goto out_static_config_free;
3047                 }
3048         }
3049
3050         sja1105_tas_setup(ds);
3051         sja1105_flower_setup(ds);
3052
3053         rc = sja1105_ptp_clock_register(ds);
3054         if (rc < 0) {
3055                 dev_err(ds->dev, "Failed to register PTP clock: %d\n", rc);
3056                 goto out_flower_teardown;
3057         }
3058
3059         rc = sja1105_mdiobus_register(ds);
3060         if (rc < 0) {
3061                 dev_err(ds->dev, "Failed to register MDIO bus: %pe\n",
3062                         ERR_PTR(rc));
3063                 goto out_ptp_clock_unregister;
3064         }
3065
3066         rc = sja1105_devlink_setup(ds);
3067         if (rc < 0)
3068                 goto out_mdiobus_unregister;
3069
3070         rtnl_lock();
3071         rc = dsa_tag_8021q_register(ds, htons(ETH_P_8021Q));
3072         rtnl_unlock();
3073         if (rc)
3074                 goto out_devlink_teardown;
3075
3076         /* On SJA1105, VLAN filtering per se is always enabled in hardware.
3077          * The only thing we can do to disable it is lie about what the 802.1Q
3078          * EtherType is.
3079          * So it will still try to apply VLAN filtering, but all ingress
3080          * traffic (except frames received with EtherType of ETH_P_SJA1105)
3081          * will be internally tagged with a distorted VLAN header where the
3082          * TPID is ETH_P_SJA1105, and the VLAN ID is the port pvid.
3083          */
3084         ds->vlan_filtering_is_global = true;
3085         ds->untag_bridge_pvid = true;
3086         /* tag_8021q has 3 bits for the VBID, and the value 0 is reserved */
3087         ds->max_num_bridges = 7;
3088
3089         /* Advertise the 8 egress queues */
3090         ds->num_tx_queues = SJA1105_NUM_TC;
3091
3092         ds->mtu_enforcement_ingress = true;
3093         ds->assisted_learning_on_cpu_port = true;
3094
3095         return 0;
3096
3097 out_devlink_teardown:
3098         sja1105_devlink_teardown(ds);
3099 out_mdiobus_unregister:
3100         sja1105_mdiobus_unregister(ds);
3101 out_ptp_clock_unregister:
3102         sja1105_ptp_clock_unregister(ds);
3103 out_flower_teardown:
3104         sja1105_flower_teardown(ds);
3105         sja1105_tas_teardown(ds);
3106 out_static_config_free:
3107         sja1105_static_config_free(&priv->static_config);
3108
3109         return rc;
3110 }
3111
3112 static void sja1105_teardown(struct dsa_switch *ds)
3113 {
3114         struct sja1105_private *priv = ds->priv;
3115
3116         rtnl_lock();
3117         dsa_tag_8021q_unregister(ds);
3118         rtnl_unlock();
3119
3120         sja1105_devlink_teardown(ds);
3121         sja1105_mdiobus_unregister(ds);
3122         sja1105_ptp_clock_unregister(ds);
3123         sja1105_flower_teardown(ds);
3124         sja1105_tas_teardown(ds);
3125         sja1105_static_config_free(&priv->static_config);
3126 }
3127
3128 static const struct dsa_switch_ops sja1105_switch_ops = {
3129         .get_tag_protocol       = sja1105_get_tag_protocol,
3130         .connect_tag_protocol   = sja1105_connect_tag_protocol,
3131         .setup                  = sja1105_setup,
3132         .teardown               = sja1105_teardown,
3133         .set_ageing_time        = sja1105_set_ageing_time,
3134         .port_change_mtu        = sja1105_change_mtu,
3135         .port_max_mtu           = sja1105_get_max_mtu,
3136         .phylink_get_caps       = sja1105_phylink_get_caps,
3137         .phylink_validate       = sja1105_phylink_validate,
3138         .phylink_mac_select_pcs = sja1105_mac_select_pcs,
3139         .phylink_mac_link_up    = sja1105_mac_link_up,
3140         .phylink_mac_link_down  = sja1105_mac_link_down,
3141         .get_strings            = sja1105_get_strings,
3142         .get_ethtool_stats      = sja1105_get_ethtool_stats,
3143         .get_sset_count         = sja1105_get_sset_count,
3144         .get_ts_info            = sja1105_get_ts_info,
3145         .port_fdb_dump          = sja1105_fdb_dump,
3146         .port_fdb_add           = sja1105_fdb_add,
3147         .port_fdb_del           = sja1105_fdb_del,
3148         .port_fast_age          = sja1105_fast_age,
3149         .port_bridge_join       = sja1105_bridge_join,
3150         .port_bridge_leave      = sja1105_bridge_leave,
3151         .port_pre_bridge_flags  = sja1105_port_pre_bridge_flags,
3152         .port_bridge_flags      = sja1105_port_bridge_flags,
3153         .port_stp_state_set     = sja1105_bridge_stp_state_set,
3154         .port_vlan_filtering    = sja1105_vlan_filtering,
3155         .port_vlan_add          = sja1105_bridge_vlan_add,
3156         .port_vlan_del          = sja1105_bridge_vlan_del,
3157         .port_mdb_add           = sja1105_mdb_add,
3158         .port_mdb_del           = sja1105_mdb_del,
3159         .port_hwtstamp_get      = sja1105_hwtstamp_get,
3160         .port_hwtstamp_set      = sja1105_hwtstamp_set,
3161         .port_rxtstamp          = sja1105_port_rxtstamp,
3162         .port_txtstamp          = sja1105_port_txtstamp,
3163         .port_setup_tc          = sja1105_port_setup_tc,
3164         .port_mirror_add        = sja1105_mirror_add,
3165         .port_mirror_del        = sja1105_mirror_del,
3166         .port_policer_add       = sja1105_port_policer_add,
3167         .port_policer_del       = sja1105_port_policer_del,
3168         .cls_flower_add         = sja1105_cls_flower_add,
3169         .cls_flower_del         = sja1105_cls_flower_del,
3170         .cls_flower_stats       = sja1105_cls_flower_stats,
3171         .devlink_info_get       = sja1105_devlink_info_get,
3172         .tag_8021q_vlan_add     = sja1105_dsa_8021q_vlan_add,
3173         .tag_8021q_vlan_del     = sja1105_dsa_8021q_vlan_del,
3174         .port_prechangeupper    = sja1105_prechangeupper,
3175 };
3176
3177 static const struct of_device_id sja1105_dt_ids[];
3178
3179 static int sja1105_check_device_id(struct sja1105_private *priv)
3180 {
3181         const struct sja1105_regs *regs = priv->info->regs;
3182         u8 prod_id[SJA1105_SIZE_DEVICE_ID] = {0};
3183         struct device *dev = &priv->spidev->dev;
3184         const struct of_device_id *match;
3185         u32 device_id;
3186         u64 part_no;
3187         int rc;
3188
3189         rc = sja1105_xfer_u32(priv, SPI_READ, regs->device_id, &device_id,
3190                               NULL);
3191         if (rc < 0)
3192                 return rc;
3193
3194         rc = sja1105_xfer_buf(priv, SPI_READ, regs->prod_id, prod_id,
3195                               SJA1105_SIZE_DEVICE_ID);
3196         if (rc < 0)
3197                 return rc;
3198
3199         sja1105_unpack(prod_id, &part_no, 19, 4, SJA1105_SIZE_DEVICE_ID);
3200
3201         for (match = sja1105_dt_ids; match->compatible[0]; match++) {
3202                 const struct sja1105_info *info = match->data;
3203
3204                 /* Is what's been probed in our match table at all? */
3205                 if (info->device_id != device_id || info->part_no != part_no)
3206                         continue;
3207
3208                 /* But is it what's in the device tree? */
3209                 if (priv->info->device_id != device_id ||
3210                     priv->info->part_no != part_no) {
3211                         dev_warn(dev, "Device tree specifies chip %s but found %s, please fix it!\n",
3212                                  priv->info->name, info->name);
3213                         /* It isn't. No problem, pick that up. */
3214                         priv->info = info;
3215                 }
3216
3217                 return 0;
3218         }
3219
3220         dev_err(dev, "Unexpected {device ID, part number}: 0x%x 0x%llx\n",
3221                 device_id, part_no);
3222
3223         return -ENODEV;
3224 }
3225
3226 static int sja1105_probe(struct spi_device *spi)
3227 {
3228         struct device *dev = &spi->dev;
3229         struct sja1105_private *priv;
3230         size_t max_xfer, max_msg;
3231         struct dsa_switch *ds;
3232         int rc;
3233
3234         if (!dev->of_node) {
3235                 dev_err(dev, "No DTS bindings for SJA1105 driver\n");
3236                 return -EINVAL;
3237         }
3238
3239         rc = sja1105_hw_reset(dev, 1, 1);
3240         if (rc)
3241                 return rc;
3242
3243         priv = devm_kzalloc(dev, sizeof(struct sja1105_private), GFP_KERNEL);
3244         if (!priv)
3245                 return -ENOMEM;
3246
3247         /* Populate our driver private structure (priv) based on
3248          * the device tree node that was probed (spi)
3249          */
3250         priv->spidev = spi;
3251         spi_set_drvdata(spi, priv);
3252
3253         /* Configure the SPI bus */
3254         spi->bits_per_word = 8;
3255         rc = spi_setup(spi);
3256         if (rc < 0) {
3257                 dev_err(dev, "Could not init SPI\n");
3258                 return rc;
3259         }
3260
3261         /* In sja1105_xfer, we send spi_messages composed of two spi_transfers:
3262          * a small one for the message header and another one for the current
3263          * chunk of the packed buffer.
3264          * Check that the restrictions imposed by the SPI controller are
3265          * respected: the chunk buffer is smaller than the max transfer size,
3266          * and the total length of the chunk plus its message header is smaller
3267          * than the max message size.
3268          * We do that during probe time since the maximum transfer size is a
3269          * runtime invariant.
3270          */
3271         max_xfer = spi_max_transfer_size(spi);
3272         max_msg = spi_max_message_size(spi);
3273
3274         /* We need to send at least one 64-bit word of SPI payload per message
3275          * in order to be able to make useful progress.
3276          */
3277         if (max_msg < SJA1105_SIZE_SPI_MSG_HEADER + 8) {
3278                 dev_err(dev, "SPI master cannot send large enough buffers, aborting\n");
3279                 return -EINVAL;
3280         }
3281
3282         priv->max_xfer_len = SJA1105_SIZE_SPI_MSG_MAXLEN;
3283         if (priv->max_xfer_len > max_xfer)
3284                 priv->max_xfer_len = max_xfer;
3285         if (priv->max_xfer_len > max_msg - SJA1105_SIZE_SPI_MSG_HEADER)
3286                 priv->max_xfer_len = max_msg - SJA1105_SIZE_SPI_MSG_HEADER;
3287
3288         priv->info = of_device_get_match_data(dev);
3289
3290         /* Detect hardware device */
3291         rc = sja1105_check_device_id(priv);
3292         if (rc < 0) {
3293                 dev_err(dev, "Device ID check failed: %d\n", rc);
3294                 return rc;
3295         }
3296
3297         dev_info(dev, "Probed switch chip: %s\n", priv->info->name);
3298
3299         ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3300         if (!ds)
3301                 return -ENOMEM;
3302
3303         ds->dev = dev;
3304         ds->num_ports = priv->info->num_ports;
3305         ds->ops = &sja1105_switch_ops;
3306         ds->priv = priv;
3307         priv->ds = ds;
3308
3309         mutex_init(&priv->ptp_data.lock);
3310         mutex_init(&priv->dynamic_config_lock);
3311         mutex_init(&priv->mgmt_lock);
3312         spin_lock_init(&priv->ts_id_lock);
3313
3314         rc = sja1105_parse_dt(priv);
3315         if (rc < 0) {
3316                 dev_err(ds->dev, "Failed to parse DT: %d\n", rc);
3317                 return rc;
3318         }
3319
3320         if (IS_ENABLED(CONFIG_NET_SCH_CBS)) {
3321                 priv->cbs = devm_kcalloc(dev, priv->info->num_cbs_shapers,
3322                                          sizeof(struct sja1105_cbs_entry),
3323                                          GFP_KERNEL);
3324                 if (!priv->cbs)
3325                         return -ENOMEM;
3326         }
3327
3328         return dsa_register_switch(priv->ds);
3329 }
3330
3331 static int sja1105_remove(struct spi_device *spi)
3332 {
3333         struct sja1105_private *priv = spi_get_drvdata(spi);
3334
3335         if (!priv)
3336                 return 0;
3337
3338         dsa_unregister_switch(priv->ds);
3339
3340         spi_set_drvdata(spi, NULL);
3341
3342         return 0;
3343 }
3344
3345 static void sja1105_shutdown(struct spi_device *spi)
3346 {
3347         struct sja1105_private *priv = spi_get_drvdata(spi);
3348
3349         if (!priv)
3350                 return;
3351
3352         dsa_switch_shutdown(priv->ds);
3353
3354         spi_set_drvdata(spi, NULL);
3355 }
3356
3357 static const struct of_device_id sja1105_dt_ids[] = {
3358         { .compatible = "nxp,sja1105e", .data = &sja1105e_info },
3359         { .compatible = "nxp,sja1105t", .data = &sja1105t_info },
3360         { .compatible = "nxp,sja1105p", .data = &sja1105p_info },
3361         { .compatible = "nxp,sja1105q", .data = &sja1105q_info },
3362         { .compatible = "nxp,sja1105r", .data = &sja1105r_info },
3363         { .compatible = "nxp,sja1105s", .data = &sja1105s_info },
3364         { .compatible = "nxp,sja1110a", .data = &sja1110a_info },
3365         { .compatible = "nxp,sja1110b", .data = &sja1110b_info },
3366         { .compatible = "nxp,sja1110c", .data = &sja1110c_info },
3367         { .compatible = "nxp,sja1110d", .data = &sja1110d_info },
3368         { /* sentinel */ },
3369 };
3370 MODULE_DEVICE_TABLE(of, sja1105_dt_ids);
3371
3372 static struct spi_driver sja1105_driver = {
3373         .driver = {
3374                 .name  = "sja1105",
3375                 .owner = THIS_MODULE,
3376                 .of_match_table = of_match_ptr(sja1105_dt_ids),
3377         },
3378         .probe  = sja1105_probe,
3379         .remove = sja1105_remove,
3380         .shutdown = sja1105_shutdown,
3381 };
3382
3383 module_spi_driver(sja1105_driver);
3384
3385 MODULE_AUTHOR("Vladimir Oltean <olteanv@gmail.com>");
3386 MODULE_AUTHOR("Georg Waibel <georg.waibel@sensor-technik.de>");
3387 MODULE_DESCRIPTION("SJA1105 Driver");
3388 MODULE_LICENSE("GPL v2");