drivers/net/dsa/sja1105/sja1105_main.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
   3  * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
   4  */
   5
   6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   7
   8 #include <linux/delay.h>
   9 #include <linux/module.h>
  10 #include <linux/printk.h>
  11 #include <linux/spi/spi.h>
  12 #include <linux/errno.h>
  13 #include <linux/gpio/consumer.h>
  14 #include <linux/phylink.h>
  15 #include <linux/of.h>
  16 #include <linux/of_net.h>
  17 #include <linux/of_mdio.h>
  18 #include <linux/of_device.h>
  19 #include <linux/pcs/pcs-xpcs.h>
  20 #include <linux/netdev_features.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/if_bridge.h>
  23 #include <linux/if_ether.h>
  24 #include <linux/dsa/8021q.h>
  25 #include "sja1105.h"
  26 #include "sja1105_tas.h"
  27
  28 #define SJA1105_UNKNOWN_MULTICAST       0x010000000000ull
  29
  30 /* Configure the optional reset pin and bring up switch */
  31 static int sja1105_hw_reset(struct device *dev, unsigned int pulse_len,
  32                             unsigned int startup_delay)
  33 {
  34         struct gpio_desc *gpio;
  35
  36         gpio = gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
  37         if (IS_ERR(gpio))
  38                 return PTR_ERR(gpio);
  39
  40         if (!gpio)
  41                 return 0;
  42
  43         gpiod_set_value_cansleep(gpio, 1);
  44         /* Wait for minimum reset pulse length */
  45         msleep(pulse_len);
  46         gpiod_set_value_cansleep(gpio, 0);
  47         /* Wait until chip is ready after reset */
  48         msleep(startup_delay);
  49
  50         gpiod_put(gpio);
  51
  52         return 0;
  53 }
  54
  55 static void
  56 sja1105_port_allow_traffic(struct sja1105_l2_forwarding_entry *l2_fwd,
  57                            int from, int to, bool allow)
  58 {
  59         if (allow)
  60                 l2_fwd[from].reach_port |= BIT(to);
  61         else
  62                 l2_fwd[from].reach_port &= ~BIT(to);
  63 }
  64
  65 static bool sja1105_can_forward(struct sja1105_l2_forwarding_entry *l2_fwd,
  66                                 int from, int to)
  67 {
  68         return !!(l2_fwd[from].reach_port & BIT(to));
  69 }
  70
  71 static int sja1105_is_vlan_configured(struct sja1105_private *priv, u16 vid)
  72 {
  73         struct sja1105_vlan_lookup_entry *vlan;
  74         int count, i;
  75
  76         vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries;
  77         count = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entry_count;
  78
  79         for (i = 0; i < count; i++)
  80                 if (vlan[i].vlanid == vid)
  81                         return i;
  82
  83         /* Return an invalid entry index if not found */
  84         return -1;
  85 }
  86
  87 static int sja1105_drop_untagged(struct dsa_switch *ds, int port, bool drop)
  88 {
  89         struct sja1105_private *priv = ds->priv;
  90         struct sja1105_mac_config_entry *mac;
  91
  92         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
  93
  94         if (mac[port].drpuntag == drop)
  95                 return 0;
  96
  97         mac[port].drpuntag = drop;
  98
  99         return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
 100                                             &mac[port], true);
 101 }
 102
 103 static int sja1105_pvid_apply(struct sja1105_private *priv, int port, u16 pvid)
 104 {
 105         struct sja1105_mac_config_entry *mac;
 106
 107         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
 108
 109         if (mac[port].vlanid == pvid)
 110                 return 0;
 111
 112         mac[port].vlanid = pvid;
 113
 114         return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
 115                                             &mac[port], true);
 116 }
 117
 118 static int sja1105_commit_pvid(struct dsa_switch *ds, int port)
 119 {
 120         struct dsa_port *dp = dsa_to_port(ds, port);
 121         struct net_device *br = dsa_port_bridge_dev_get(dp);
 122         struct sja1105_private *priv = ds->priv;
 123         struct sja1105_vlan_lookup_entry *vlan;
 124         bool drop_untagged = false;
 125         int match, rc;
 126         u16 pvid;
 127
 128         if (br && br_vlan_enabled(br))
 129                 pvid = priv->bridge_pvid[port];
 130         else
 131                 pvid = priv->tag_8021q_pvid[port];
 132
 133         rc = sja1105_pvid_apply(priv, port, pvid);
 134         if (rc)
 135                 return rc;
 136
 137         /* Only force dropping of untagged packets when the port is under a
 138          * VLAN-aware bridge. When the tag_8021q pvid is used, we are
 139          * deliberately removing the RX VLAN from the port's VMEMB_PORT list,
 140          * to prevent DSA tag spoofing from the link partner. Untagged packets
 141          * are the only ones that should be received with tag_8021q, so
 142          * definitely don't drop them.
 143          */
 144         if (pvid == priv->bridge_pvid[port]) {
 145                 vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries;
 146
 147                 match = sja1105_is_vlan_configured(priv, pvid);
 148
 149                 if (match < 0 || !(vlan[match].vmemb_port & BIT(port)))
 150                         drop_untagged = true;
 151         }
 152
 153         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
 154                 drop_untagged = true;
 155
 156         return sja1105_drop_untagged(ds, port, drop_untagged);
 157 }
 158
 159 static int sja1105_init_mac_settings(struct sja1105_private *priv)
 160 {
 161         struct sja1105_mac_config_entry default_mac = {
 162                 /* Enable all 8 priority queues on egress.
 163                  * Every queue i holds top[i] - base[i] frames.
 164                  * Sum of top[i] - base[i] is 511 (max hardware limit).
 165                  */
 166                 .top  = {0x3F, 0x7F, 0xBF, 0xFF, 0x13F, 0x17F, 0x1BF, 0x1FF},
 167                 .base = {0x0, 0x40, 0x80, 0xC0, 0x100, 0x140, 0x180, 0x1C0},
 168                 .enabled = {true, true, true, true, true, true, true, true},
 169                 /* Keep standard IFG of 12 bytes on egress. */
 170                 .ifg = 0,
 171                 /* Always put the MAC speed in automatic mode, where it can be
 172                  * adjusted at runtime by PHYLINK.
 173                  */
 174                 .speed = priv->info->port_speed[SJA1105_SPEED_AUTO],
 175                 /* No static correction for 1-step 1588 events */
 176                 .tp_delin = 0,
 177                 .tp_delout = 0,
 178                 /* Disable aging for critical TTEthernet traffic */
 179                 .maxage = 0xFF,
 180                 /* Internal VLAN (pvid) to apply to untagged ingress */
 181                 .vlanprio = 0,
 182                 .vlanid = 1,
 183                 .ing_mirr = false,
 184                 .egr_mirr = false,
 185                 /* Don't drop traffic with other EtherType than ETH_P_IP */
 186                 .drpnona664 = false,
 187                 /* Don't drop double-tagged traffic */
 188                 .drpdtag = false,
 189                 /* Don't drop untagged traffic */
 190                 .drpuntag = false,
 191                 /* Don't retag 802.1p (VID 0) traffic with the pvid */
 192                 .retag = false,
 193                 /* Disable learning and I/O on user ports by default -
 194                  * STP will enable it.
 195                  */
 196                 .dyn_learn = false,
 197                 .egress = false,
 198                 .ingress = false,
 199         };
 200         struct sja1105_mac_config_entry *mac;
 201         struct dsa_switch *ds = priv->ds;
 202         struct sja1105_table *table;
 203         struct dsa_port *dp;
 204
 205         table = &priv->static_config.tables[BLK_IDX_MAC_CONFIG];
 206
 207         /* Discard previous MAC Configuration Table */
 208         if (table->entry_count) {
 209                 kfree(table->entries);
 210                 table->entry_count = 0;
 211         }
 212
 213         table->entries = kcalloc(table->ops->max_entry_count,
 214                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 215         if (!table->entries)
 216                 return -ENOMEM;
 217
 218         table->entry_count = table->ops->max_entry_count;
 219
 220         mac = table->entries;
 221
 222         list_for_each_entry(dp, &ds->dst->ports, list) {
 223                 if (dp->ds != ds)
 224                         continue;
 225
 226                 mac[dp->index] = default_mac;
 227
 228                 /* Let sja1105_bridge_stp_state_set() keep address learning
 229                  * enabled for the DSA ports. CPU ports use software-assisted
 230                  * learning to ensure that only FDB entries belonging to the
 231                  * bridge are learned, and that they are learned towards all
 232                  * CPU ports in a cross-chip topology if multiple CPU ports
 233                  * exist.
 234                  */
 235                 if (dsa_port_is_dsa(dp))
 236                         dp->learning = true;
 237
 238                 /* Disallow untagged packets from being received on the
 239                  * CPU and DSA ports.
 240                  */
 241                 if (dsa_port_is_cpu(dp) || dsa_port_is_dsa(dp))
 242                         mac[dp->index].drpuntag = true;
 243         }
 244
 245         return 0;
 246 }
 247
 248 static int sja1105_init_mii_settings(struct sja1105_private *priv)
 249 {
 250         struct device *dev = &priv->spidev->dev;
 251         struct sja1105_xmii_params_entry *mii;
 252         struct dsa_switch *ds = priv->ds;
 253         struct sja1105_table *table;
 254         int i;
 255
 256         table = &priv->static_config.tables[BLK_IDX_XMII_PARAMS];
 257
 258         /* Discard previous xMII Mode Parameters Table */
 259         if (table->entry_count) {
 260                 kfree(table->entries);
 261                 table->entry_count = 0;
 262         }
 263
 264         table->entries = kcalloc(table->ops->max_entry_count,
 265                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 266         if (!table->entries)
 267                 return -ENOMEM;
 268
 269         /* Override table based on PHYLINK DT bindings */
 270         table->entry_count = table->ops->max_entry_count;
 271
 272         mii = table->entries;
 273
 274         for (i = 0; i < ds->num_ports; i++) {
 275                 sja1105_mii_role_t role = XMII_MAC;
 276
 277                 if (dsa_is_unused_port(priv->ds, i))
 278                         continue;
 279
 280                 switch (priv->phy_mode[i]) {
 281                 case PHY_INTERFACE_MODE_INTERNAL:
 282                         if (priv->info->internal_phy[i] == SJA1105_NO_PHY)
 283                                 goto unsupported;
 284
 285                         mii->xmii_mode[i] = XMII_MODE_MII;
 286                         if (priv->info->internal_phy[i] == SJA1105_PHY_BASE_TX)
 287                                 mii->special[i] = true;
 288
 289                         break;
 290                 case PHY_INTERFACE_MODE_REVMII:
 291                         role = XMII_PHY;
 292                         fallthrough;
 293                 case PHY_INTERFACE_MODE_MII:
 294                         if (!priv->info->supports_mii[i])
 295                                 goto unsupported;
 296
 297                         mii->xmii_mode[i] = XMII_MODE_MII;
 298                         break;
 299                 case PHY_INTERFACE_MODE_REVRMII:
 300                         role = XMII_PHY;
 301                         fallthrough;
 302                 case PHY_INTERFACE_MODE_RMII:
 303                         if (!priv->info->supports_rmii[i])
 304                                 goto unsupported;
 305
 306                         mii->xmii_mode[i] = XMII_MODE_RMII;
 307                         break;
 308                 case PHY_INTERFACE_MODE_RGMII:
 309                 case PHY_INTERFACE_MODE_RGMII_ID:
 310                 case PHY_INTERFACE_MODE_RGMII_RXID:
 311                 case PHY_INTERFACE_MODE_RGMII_TXID:
 312                         if (!priv->info->supports_rgmii[i])
 313                                 goto unsupported;
 314
 315                         mii->xmii_mode[i] = XMII_MODE_RGMII;
 316                         break;
 317                 case PHY_INTERFACE_MODE_SGMII:
 318                         if (!priv->info->supports_sgmii[i])
 319                                 goto unsupported;
 320
 321                         mii->xmii_mode[i] = XMII_MODE_SGMII;
 322                         mii->special[i] = true;
 323                         break;
 324                 case PHY_INTERFACE_MODE_2500BASEX:
 325                         if (!priv->info->supports_2500basex[i])
 326                                 goto unsupported;
 327
 328                         mii->xmii_mode[i] = XMII_MODE_SGMII;
 329                         mii->special[i] = true;
 330                         break;
 331 unsupported:
 332                 default:
 333                         dev_err(dev, "Unsupported PHY mode %s on port %d!\n",
 334                                 phy_modes(priv->phy_mode[i]), i);
 335                         return -EINVAL;
 336                 }
 337
 338                 mii->phy_mac[i] = role;
 339         }
 340         return 0;
 341 }
 342
 343 static int sja1105_init_static_fdb(struct sja1105_private *priv)
 344 {
 345         struct sja1105_l2_lookup_entry *l2_lookup;
 346         struct sja1105_table *table;
 347         int port;
 348
 349         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
 350
 351         /* We only populate the FDB table through dynamic L2 Address Lookup
 352          * entries, except for a special entry at the end which is a catch-all
 353          * for unknown multicast and will be used to control flooding domain.
 354          */
 355         if (table->entry_count) {
 356                 kfree(table->entries);
 357                 table->entry_count = 0;
 358         }
 359
 360         if (!priv->info->can_limit_mcast_flood)
 361                 return 0;
 362
 363         table->entries = kcalloc(1, table->ops->unpacked_entry_size,
 364                                  GFP_KERNEL);
 365         if (!table->entries)
 366                 return -ENOMEM;
 367
 368         table->entry_count = 1;
 369         l2_lookup = table->entries;
 370
 371         /* All L2 multicast addresses have an odd first octet */
 372         l2_lookup[0].macaddr = SJA1105_UNKNOWN_MULTICAST;
 373         l2_lookup[0].mask_macaddr = SJA1105_UNKNOWN_MULTICAST;
 374         l2_lookup[0].lockeds = true;
 375         l2_lookup[0].index = SJA1105_MAX_L2_LOOKUP_COUNT - 1;
 376
 377         /* Flood multicast to every port by default */
 378         for (port = 0; port < priv->ds->num_ports; port++)
 379                 if (!dsa_is_unused_port(priv->ds, port))
 380                         l2_lookup[0].destports |= BIT(port);
 381
 382         return 0;
 383 }
 384
 385 static int sja1105_init_l2_lookup_params(struct sja1105_private *priv)
 386 {
 387         struct sja1105_l2_lookup_params_entry default_l2_lookup_params = {
 388                 /* Learned FDB entries are forgotten after 300 seconds */
 389                 .maxage = SJA1105_AGEING_TIME_MS(300000),
 390                 /* All entries within a FDB bin are available for learning */
 391                 .dyn_tbsz = SJA1105ET_FDB_BIN_SIZE,
 392                 /* And the P/Q/R/S equivalent setting: */
 393                 .start_dynspc = 0,
 394                 /* 2^8 + 2^5 + 2^3 + 2^2 + 2^1 + 1 in Koopman notation */
 395                 .poly = 0x97,
 396                 /* This selects between Independent VLAN Learning (IVL) and
 397                  * Shared VLAN Learning (SVL)
 398                  */
 399                 .shared_learn = true,
 400                 /* Don't discard management traffic based on ENFPORT -
 401                  * we don't perform SMAC port enforcement anyway, so
 402                  * what we are setting here doesn't matter.
 403                  */
 404                 .no_enf_hostprt = false,
 405                 /* Don't learn SMAC for mac_fltres1 and mac_fltres0.
 406                  * Maybe correlate with no_linklocal_learn from bridge driver?
 407                  */
 408                 .no_mgmt_learn = true,
 409                 /* P/Q/R/S only */
 410                 .use_static = true,
 411                 /* Dynamically learned FDB entries can overwrite other (older)
 412                  * dynamic FDB entries
 413                  */
 414                 .owr_dyn = true,
 415                 .drpnolearn = true,
 416         };
 417         struct dsa_switch *ds = priv->ds;
 418         int port, num_used_ports = 0;
 419         struct sja1105_table *table;
 420         u64 max_fdb_entries;
 421
 422         for (port = 0; port < ds->num_ports; port++)
 423                 if (!dsa_is_unused_port(ds, port))
 424                         num_used_ports++;
 425
 426         max_fdb_entries = SJA1105_MAX_L2_LOOKUP_COUNT / num_used_ports;
 427
 428         for (port = 0; port < ds->num_ports; port++) {
 429                 if (dsa_is_unused_port(ds, port))
 430                         continue;
 431
 432                 default_l2_lookup_params.maxaddrp[port] = max_fdb_entries;
 433         }
 434
 435         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS];
 436
 437         if (table->entry_count) {
 438                 kfree(table->entries);
 439                 table->entry_count = 0;
 440         }
 441
 442         table->entries = kcalloc(table->ops->max_entry_count,
 443                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 444         if (!table->entries)
 445                 return -ENOMEM;
 446
 447         table->entry_count = table->ops->max_entry_count;
 448
 449         /* This table only has a single entry */
 450         ((struct sja1105_l2_lookup_params_entry *)table->entries)[0] =
 451                                 default_l2_lookup_params;
 452
 453         return 0;
 454 }
 455
 456 /* Set up a default VLAN for untagged traffic injected from the CPU
 457  * using management routes (e.g. STP, PTP) as opposed to tag_8021q.
 458  * All DT-defined ports are members of this VLAN, and there are no
 459  * restrictions on forwarding (since the CPU selects the destination).
 460  * Frames from this VLAN will always be transmitted as untagged, and
 461  * neither the bridge nor the 8021q module cannot create this VLAN ID.
 462  */
 463 static int sja1105_init_static_vlan(struct sja1105_private *priv)
 464 {
 465         struct sja1105_table *table;
 466         struct sja1105_vlan_lookup_entry pvid = {
 467                 .type_entry = SJA1110_VLAN_D_TAG,
 468                 .ving_mirr = 0,
 469                 .vegr_mirr = 0,
 470                 .vmemb_port = 0,
 471                 .vlan_bc = 0,
 472                 .tag_port = 0,
 473                 .vlanid = SJA1105_DEFAULT_VLAN,
 474         };
 475         struct dsa_switch *ds = priv->ds;
 476         int port;
 477
 478         table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
 479
 480         if (table->entry_count) {
 481                 kfree(table->entries);
 482                 table->entry_count = 0;
 483         }
 484
 485         table->entries = kzalloc(table->ops->unpacked_entry_size,
 486                                  GFP_KERNEL);
 487         if (!table->entries)
 488                 return -ENOMEM;
 489
 490         table->entry_count = 1;
 491
 492         for (port = 0; port < ds->num_ports; port++) {
 493                 if (dsa_is_unused_port(ds, port))
 494                         continue;
 495
 496                 pvid.vmemb_port |= BIT(port);
 497                 pvid.vlan_bc |= BIT(port);
 498                 pvid.tag_port &= ~BIT(port);
 499
 500                 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
 501                         priv->tag_8021q_pvid[port] = SJA1105_DEFAULT_VLAN;
 502                         priv->bridge_pvid[port] = SJA1105_DEFAULT_VLAN;
 503                 }
 504         }
 505
 506         ((struct sja1105_vlan_lookup_entry *)table->entries)[0] = pvid;
 507         return 0;
 508 }
 509
 510 static int sja1105_init_l2_forwarding(struct sja1105_private *priv)
 511 {
 512         struct sja1105_l2_forwarding_entry *l2fwd;
 513         struct dsa_switch *ds = priv->ds;
 514         struct dsa_switch_tree *dst;
 515         struct sja1105_table *table;
 516         struct dsa_link *dl;
 517         int port, tc;
 518         int from, to;
 519
 520         table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING];
 521
 522         if (table->entry_count) {
 523                 kfree(table->entries);
 524                 table->entry_count = 0;
 525         }
 526
 527         table->entries = kcalloc(table->ops->max_entry_count,
 528                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 529         if (!table->entries)
 530                 return -ENOMEM;
 531
 532         table->entry_count = table->ops->max_entry_count;
 533
 534         l2fwd = table->entries;
 535
 536         /* First 5 entries in the L2 Forwarding Table define the forwarding
 537          * rules and the VLAN PCP to ingress queue mapping.
 538          * Set up the ingress queue mapping first.
 539          */
 540         for (port = 0; port < ds->num_ports; port++) {
 541                 if (dsa_is_unused_port(ds, port))
 542                         continue;
 543
 544                 for (tc = 0; tc < SJA1105_NUM_TC; tc++)
 545                         l2fwd[port].vlan_pmap[tc] = tc;
 546         }
 547
 548         /* Then manage the forwarding domain for user ports. These can forward
 549          * only to the always-on domain (CPU port and DSA links)
 550          */
 551         for (from = 0; from < ds->num_ports; from++) {
 552                 if (!dsa_is_user_port(ds, from))
 553                         continue;
 554
 555                 for (to = 0; to < ds->num_ports; to++) {
 556                         if (!dsa_is_cpu_port(ds, to) &&
 557                             !dsa_is_dsa_port(ds, to))
 558                                 continue;
 559
 560                         l2fwd[from].bc_domain |= BIT(to);
 561                         l2fwd[from].fl_domain |= BIT(to);
 562
 563                         sja1105_port_allow_traffic(l2fwd, from, to, true);
 564                 }
 565         }
 566
 567         /* Then manage the forwarding domain for DSA links and CPU ports (the
 568          * always-on domain). These can send packets to any enabled port except
 569          * themselves.
 570          */
 571         for (from = 0; from < ds->num_ports; from++) {
 572                 if (!dsa_is_cpu_port(ds, from) && !dsa_is_dsa_port(ds, from))
 573                         continue;
 574
 575                 for (to = 0; to < ds->num_ports; to++) {
 576                         if (dsa_is_unused_port(ds, to))
 577                                 continue;
 578
 579                         if (from == to)
 580                                 continue;
 581
 582                         l2fwd[from].bc_domain |= BIT(to);
 583                         l2fwd[from].fl_domain |= BIT(to);
 584
 585                         sja1105_port_allow_traffic(l2fwd, from, to, true);
 586                 }
 587         }
 588
 589         /* In odd topologies ("H" connections where there is a DSA link to
 590          * another switch which also has its own CPU port), TX packets can loop
 591          * back into the system (they are flooded from CPU port 1 to the DSA
 592          * link, and from there to CPU port 2). Prevent this from happening by
 593          * cutting RX from DSA links towards our CPU port, if the remote switch
 594          * has its own CPU port and therefore doesn't need ours for network
 595          * stack termination.
 596          */
 597         dst = ds->dst;
 598
 599         list_for_each_entry(dl, &dst->rtable, list) {
 600                 if (dl->dp->ds != ds || dl->link_dp->cpu_dp == dl->dp->cpu_dp)
 601                         continue;
 602
 603                 from = dl->dp->index;
 604                 to = dsa_upstream_port(ds, from);
 605
 606                 dev_warn(ds->dev,
 607                          "H topology detected, cutting RX from DSA link %d to CPU port %d to prevent TX packet loops\n",
 608                          from, to);
 609
 610                 sja1105_port_allow_traffic(l2fwd, from, to, false);
 611
 612                 l2fwd[from].bc_domain &= ~BIT(to);
 613                 l2fwd[from].fl_domain &= ~BIT(to);
 614         }
 615
 616         /* Finally, manage the egress flooding domain. All ports start up with
 617          * flooding enabled, including the CPU port and DSA links.
 618          */
 619         for (port = 0; port < ds->num_ports; port++) {
 620                 if (dsa_is_unused_port(ds, port))
 621                         continue;
 622
 623                 priv->ucast_egress_floods |= BIT(port);
 624                 priv->bcast_egress_floods |= BIT(port);
 625         }
 626
 627         /* Next 8 entries define VLAN PCP mapping from ingress to egress.
 628          * Create a one-to-one mapping.
 629          */
 630         for (tc = 0; tc < SJA1105_NUM_TC; tc++) {
 631                 for (port = 0; port < ds->num_ports; port++) {
 632                         if (dsa_is_unused_port(ds, port))
 633                                 continue;
 634
 635                         l2fwd[ds->num_ports + tc].vlan_pmap[port] = tc;
 636                 }
 637
 638                 l2fwd[ds->num_ports + tc].type_egrpcp2outputq = true;
 639         }
 640
 641         return 0;
 642 }
 643
 644 static int sja1110_init_pcp_remapping(struct sja1105_private *priv)
 645 {
 646         struct sja1110_pcp_remapping_entry *pcp_remap;
 647         struct dsa_switch *ds = priv->ds;
 648         struct sja1105_table *table;
 649         int port, tc;
 650
 651         table = &priv->static_config.tables[BLK_IDX_PCP_REMAPPING];
 652
 653         /* Nothing to do for SJA1105 */
 654         if (!table->ops->max_entry_count)
 655                 return 0;
 656
 657         if (table->entry_count) {
 658                 kfree(table->entries);
 659                 table->entry_count = 0;
 660         }
 661
 662         table->entries = kcalloc(table->ops->max_entry_count,
 663                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 664         if (!table->entries)
 665                 return -ENOMEM;
 666
 667         table->entry_count = table->ops->max_entry_count;
 668
 669         pcp_remap = table->entries;
 670
 671         /* Repeat the configuration done for vlan_pmap */
 672         for (port = 0; port < ds->num_ports; port++) {
 673                 if (dsa_is_unused_port(ds, port))
 674                         continue;
 675
 676                 for (tc = 0; tc < SJA1105_NUM_TC; tc++)
 677                         pcp_remap[port].egrpcp[tc] = tc;
 678         }
 679
 680         return 0;
 681 }
 682
 683 static int sja1105_init_l2_forwarding_params(struct sja1105_private *priv)
 684 {
 685         struct sja1105_l2_forwarding_params_entry *l2fwd_params;
 686         struct sja1105_table *table;
 687
 688         table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS];
 689
 690         if (table->entry_count) {
 691                 kfree(table->entries);
 692                 table->entry_count = 0;
 693         }
 694
 695         table->entries = kcalloc(table->ops->max_entry_count,
 696                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 697         if (!table->entries)
 698                 return -ENOMEM;
 699
 700         table->entry_count = table->ops->max_entry_count;
 701
 702         /* This table only has a single entry */
 703         l2fwd_params = table->entries;
 704
 705         /* Disallow dynamic reconfiguration of vlan_pmap */
 706         l2fwd_params->max_dynp = 0;
 707         /* Use a single memory partition for all ingress queues */
 708         l2fwd_params->part_spc[0] = priv->info->max_frame_mem;
 709
 710         return 0;
 711 }
 712
 713 void sja1105_frame_memory_partitioning(struct sja1105_private *priv)
 714 {
 715         struct sja1105_l2_forwarding_params_entry *l2_fwd_params;
 716         struct sja1105_vl_forwarding_params_entry *vl_fwd_params;
 717         struct sja1105_table *table;
 718
 719         table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS];
 720         l2_fwd_params = table->entries;
 721         l2_fwd_params->part_spc[0] = SJA1105_MAX_FRAME_MEMORY;
 722
 723         /* If we have any critical-traffic virtual links, we need to reserve
 724          * some frame buffer memory for them. At the moment, hardcode the value
 725          * at 100 blocks of 128 bytes of memory each. This leaves 829 blocks
 726          * remaining for best-effort traffic. TODO: figure out a more flexible
 727          * way to perform the frame buffer partitioning.
 728          */
 729         if (!priv->static_config.tables[BLK_IDX_VL_FORWARDING].entry_count)
 730                 return;
 731
 732         table = &priv->static_config.tables[BLK_IDX_VL_FORWARDING_PARAMS];
 733         vl_fwd_params = table->entries;
 734
 735         l2_fwd_params->part_spc[0] -= SJA1105_VL_FRAME_MEMORY;
 736         vl_fwd_params->partspc[0] = SJA1105_VL_FRAME_MEMORY;
 737 }
 738
 739 /* SJA1110 TDMACONFIGIDX values:
 740  *
 741  *      | 100 Mbps ports |  1Gbps ports  | 2.5Gbps ports | Disabled ports
 742  * -----+----------------+---------------+---------------+---------------
 743  *   0  |   0, [5:10]    |     [1:2]     |     [3:4]     |     retag
 744  *   1  |0, [5:10], retag|     [1:2]     |     [3:4]     |       -
 745  *   2  |   0, [5:10]    |  [1:3], retag |       4       |       -
 746  *   3  |   0, [5:10]    |[1:2], 4, retag|       3       |       -
 747  *   4  |  0, 2, [5:10]  |    1, retag   |     [3:4]     |       -
 748  *   5  |  0, 1, [5:10]  |    2, retag   |     [3:4]     |       -
 749  *  14  |   0, [5:10]    | [1:4], retag  |       -       |       -
 750  *  15  |     [5:10]     | [0:4], retag  |       -       |       -
 751  */
 752 static void sja1110_select_tdmaconfigidx(struct sja1105_private *priv)
 753 {
 754         struct sja1105_general_params_entry *general_params;
 755         struct sja1105_table *table;
 756         bool port_1_is_base_tx;
 757         bool port_3_is_2500;
 758         bool port_4_is_2500;
 759         u64 tdmaconfigidx;
 760
 761         if (priv->info->device_id != SJA1110_DEVICE_ID)
 762                 return;
 763
 764         table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
 765         general_params = table->entries;
 766
 767         /* All the settings below are "as opposed to SGMII", which is the
 768          * other pinmuxing option.
 769          */
 770         port_1_is_base_tx = priv->phy_mode[1] == PHY_INTERFACE_MODE_INTERNAL;
 771         port_3_is_2500 = priv->phy_mode[3] == PHY_INTERFACE_MODE_2500BASEX;
 772         port_4_is_2500 = priv->phy_mode[4] == PHY_INTERFACE_MODE_2500BASEX;
 773
 774         if (port_1_is_base_tx)
 775                 /* Retagging port will operate at 1 Gbps */
 776                 tdmaconfigidx = 5;
 777         else if (port_3_is_2500 && port_4_is_2500)
 778                 /* Retagging port will operate at 100 Mbps */
 779                 tdmaconfigidx = 1;
 780         else if (port_3_is_2500)
 781                 /* Retagging port will operate at 1 Gbps */
 782                 tdmaconfigidx = 3;
 783         else if (port_4_is_2500)
 784                 /* Retagging port will operate at 1 Gbps */
 785                 tdmaconfigidx = 2;
 786         else
 787                 /* Retagging port will operate at 1 Gbps */
 788                 tdmaconfigidx = 14;
 789
 790         general_params->tdmaconfigidx = tdmaconfigidx;
 791 }
 792
 793 static int sja1105_init_topology(struct sja1105_private *priv,
 794                                  struct sja1105_general_params_entry *general_params)
 795 {
 796         struct dsa_switch *ds = priv->ds;
 797         int port;
 798
 799         /* The host port is the destination for traffic matching mac_fltres1
 800          * and mac_fltres0 on all ports except itself. Default to an invalid
 801          * value.
 802          */
 803         general_params->host_port = ds->num_ports;
 804
 805         /* Link-local traffic received on casc_port will be forwarded
 806          * to host_port without embedding the source port and device ID
 807          * info in the destination MAC address, and no RX timestamps will be
 808          * taken either (presumably because it is a cascaded port and a
 809          * downstream SJA switch already did that).
 810          * To disable the feature, we need to do different things depending on
 811          * switch generation. On SJA1105 we need to set an invalid port, while
 812          * on SJA1110 which support multiple cascaded ports, this field is a
 813          * bitmask so it must be left zero.
 814          */
 815         if (!priv->info->multiple_cascade_ports)
 816                 general_params->casc_port = ds->num_ports;
 817
 818         for (port = 0; port < ds->num_ports; port++) {
 819                 bool is_upstream = dsa_is_upstream_port(ds, port);
 820                 bool is_dsa_link = dsa_is_dsa_port(ds, port);
 821
 822                 /* Upstream ports can be dedicated CPU ports or
 823                  * upstream-facing DSA links
 824                  */
 825                 if (is_upstream) {
 826                         if (general_params->host_port == ds->num_ports) {
 827                                 general_params->host_port = port;
 828                         } else {
 829                                 dev_err(ds->dev,
 830                                         "Port %llu is already a host port, configuring %d as one too is not supported\n",
 831                                         general_params->host_port, port);
 832                                 return -EINVAL;
 833                         }
 834                 }
 835
 836                 /* Cascade ports are downstream-facing DSA links */
 837                 if (is_dsa_link && !is_upstream) {
 838                         if (priv->info->multiple_cascade_ports) {
 839                                 general_params->casc_port |= BIT(port);
 840                         } else if (general_params->casc_port == ds->num_ports) {
 841                                 general_params->casc_port = port;
 842                         } else {
 843                                 dev_err(ds->dev,
 844                                         "Port %llu is already a cascade port, configuring %d as one too is not supported\n",
 845                                         general_params->casc_port, port);
 846                                 return -EINVAL;
 847                         }
 848                 }
 849         }
 850
 851         if (general_params->host_port == ds->num_ports) {
 852                 dev_err(ds->dev, "No host port configured\n");
 853                 return -EINVAL;
 854         }
 855
 856         return 0;
 857 }
 858
 859 static int sja1105_init_general_params(struct sja1105_private *priv)
 860 {
 861         struct sja1105_general_params_entry default_general_params = {
 862                 /* Allow dynamic changing of the mirror port */
 863                 .mirr_ptacu = true,
 864                 .switchid = priv->ds->index,
 865                 /* Priority queue for link-local management frames
 866                  * (both ingress to and egress from CPU - PTP, STP etc)
 867                  */
 868                 .hostprio = 7,
 869                 .mac_fltres1 = SJA1105_LINKLOCAL_FILTER_A,
 870                 .mac_flt1    = SJA1105_LINKLOCAL_FILTER_A_MASK,
 871                 .incl_srcpt1 = false,
 872                 .send_meta1  = false,
 873                 .mac_fltres0 = SJA1105_LINKLOCAL_FILTER_B,
 874                 .mac_flt0    = SJA1105_LINKLOCAL_FILTER_B_MASK,
 875                 .incl_srcpt0 = false,
 876                 .send_meta0  = false,
 877                 /* Default to an invalid value */
 878                 .mirr_port = priv->ds->num_ports,
 879                 /* No TTEthernet */
 880                 .vllupformat = SJA1105_VL_FORMAT_PSFP,
 881                 .vlmarker = 0,
 882                 .vlmask = 0,
 883                 /* Only update correctionField for 1-step PTP (L2 transport) */
 884                 .ignore2stf = 0,
 885                 /* Forcefully disable VLAN filtering by telling
 886                  * the switch that VLAN has a different EtherType.
 887                  */
 888                 .tpid = ETH_P_SJA1105,
 889                 .tpid2 = ETH_P_SJA1105,
 890                 /* Enable the TTEthernet engine on SJA1110 */
 891                 .tte_en = true,
 892                 /* Set up the EtherType for control packets on SJA1110 */
 893                 .header_type = ETH_P_SJA1110,
 894         };
 895         struct sja1105_general_params_entry *general_params;
 896         struct sja1105_table *table;
 897         int rc;
 898
 899         rc = sja1105_init_topology(priv, &default_general_params);
 900         if (rc)
 901                 return rc;
 902
 903         table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
 904
 905         if (table->entry_count) {
 906                 kfree(table->entries);
 907                 table->entry_count = 0;
 908         }
 909
 910         table->entries = kcalloc(table->ops->max_entry_count,
 911                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 912         if (!table->entries)
 913                 return -ENOMEM;
 914
 915         table->entry_count = table->ops->max_entry_count;
 916
 917         general_params = table->entries;
 918
 919         /* This table only has a single entry */
 920         general_params[0] = default_general_params;
 921
 922         sja1110_select_tdmaconfigidx(priv);
 923
 924         return 0;
 925 }
 926
 927 static int sja1105_init_avb_params(struct sja1105_private *priv)
 928 {
 929         struct sja1105_avb_params_entry *avb;
 930         struct sja1105_table *table;
 931
 932         table = &priv->static_config.tables[BLK_IDX_AVB_PARAMS];
 933
 934         /* Discard previous AVB Parameters Table */
 935         if (table->entry_count) {
 936                 kfree(table->entries);
 937                 table->entry_count = 0;
 938         }
 939
 940         table->entries = kcalloc(table->ops->max_entry_count,
 941                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 942         if (!table->entries)
 943                 return -ENOMEM;
 944
 945         table->entry_count = table->ops->max_entry_count;
 946
 947         avb = table->entries;
 948
 949         /* Configure the MAC addresses for meta frames */
 950         avb->destmeta = SJA1105_META_DMAC;
 951         avb->srcmeta  = SJA1105_META_SMAC;
 952         /* On P/Q/R/S, configure the direction of the PTP_CLK pin as input by
 953          * default. This is because there might be boards with a hardware
 954          * layout where enabling the pin as output might cause an electrical
 955          * clash. On E/T the pin is always an output, which the board designers
 956          * probably already knew, so even if there are going to be electrical
 957          * issues, there's nothing we can do.
 958          */
 959         avb->cas_master = false;
 960
 961         return 0;
 962 }
 963
 964 /* The L2 policing table is 2-stage. The table is looked up for each frame
 965  * according to the ingress port, whether it was broadcast or not, and the
 966  * classified traffic class (given by VLAN PCP). This portion of the lookup is
 967  * fixed, and gives access to the SHARINDX, an indirection register pointing
 968  * within the policing table itself, which is used to resolve the policer that
 969  * will be used for this frame.
 970  *
 971  *  Stage 1                              Stage 2
 972  * +------------+--------+              +---------------------------------+
 973  * |Port 0 TC 0 |SHARINDX|              | Policer 0: Rate, Burst, MTU     |
 974  * +------------+--------+              +---------------------------------+
 975  * |Port 0 TC 1 |SHARINDX|              | Policer 1: Rate, Burst, MTU     |
 976  * +------------+--------+              +---------------------------------+
 977  *    ...                               | Policer 2: Rate, Burst, MTU     |
 978  * +------------+--------+              +---------------------------------+
 979  * |Port 0 TC 7 |SHARINDX|              | Policer 3: Rate, Burst, MTU     |
 980  * +------------+--------+              +---------------------------------+
 981  * |Port 1 TC 0 |SHARINDX|              | Policer 4: Rate, Burst, MTU     |
 982  * +------------+--------+              +---------------------------------+
 983  *    ...                               | Policer 5: Rate, Burst, MTU     |
 984  * +------------+--------+              +---------------------------------+
 985  * |Port 1 TC 7 |SHARINDX|              | Policer 6: Rate, Burst, MTU     |
 986  * +------------+--------+              +---------------------------------+
 987  *    ...                               | Policer 7: Rate, Burst, MTU     |
 988  * +------------+--------+              +---------------------------------+
 989  * |Port 4 TC 7 |SHARINDX|                 ...
 990  * +------------+--------+
 991  * |Port 0 BCAST|SHARINDX|                 ...
 992  * +------------+--------+
 993  * |Port 1 BCAST|SHARINDX|                 ...
 994  * +------------+--------+
 995  *    ...                                  ...
 996  * +------------+--------+              +---------------------------------+
 997  * |Port 4 BCAST|SHARINDX|              | Policer 44: Rate, Burst, MTU    |
 998  * +------------+--------+              +---------------------------------+
 999  *
1000  * In this driver, we shall use policers 0-4 as statically alocated port
1001  * (matchall) policers. So we need to make the SHARINDX for all lookups
1002  * corresponding to this ingress port (8 VLAN PCP lookups and 1 broadcast
1003  * lookup) equal.
1004  * The remaining policers (40) shall be dynamically allocated for flower
1005  * policers, where the key is either vlan_prio or dst_mac ff:ff:ff:ff:ff:ff.
1006  */
1007 #define SJA1105_RATE_MBPS(speed) (((speed) * 64000) / 1000)
1008
1009 static int sja1105_init_l2_policing(struct sja1105_private *priv)
1010 {
1011         struct sja1105_l2_policing_entry *policing;
1012         struct dsa_switch *ds = priv->ds;
1013         struct sja1105_table *table;
1014         int port, tc;
1015
1016         table = &priv->static_config.tables[BLK_IDX_L2_POLICING];
1017
1018         /* Discard previous L2 Policing Table */
1019         if (table->entry_count) {
1020                 kfree(table->entries);
1021                 table->entry_count = 0;
1022         }
1023
1024         table->entries = kcalloc(table->ops->max_entry_count,
1025                                  table->ops->unpacked_entry_size, GFP_KERNEL);
1026         if (!table->entries)
1027                 return -ENOMEM;
1028
1029         table->entry_count = table->ops->max_entry_count;
1030
1031         policing = table->entries;
1032
1033         /* Setup shared indices for the matchall policers */
1034         for (port = 0; port < ds->num_ports; port++) {
1035                 int mcast = (ds->num_ports * (SJA1105_NUM_TC + 1)) + port;
1036                 int bcast = (ds->num_ports * SJA1105_NUM_TC) + port;
1037
1038                 for (tc = 0; tc < SJA1105_NUM_TC; tc++)
1039                         policing[port * SJA1105_NUM_TC + tc].sharindx = port;
1040
1041                 policing[bcast].sharindx = port;
1042                 /* Only SJA1110 has multicast policers */
1043                 if (mcast <= table->ops->max_entry_count)
1044                         policing[mcast].sharindx = port;
1045         }
1046
1047         /* Setup the matchall policer parameters */
1048         for (port = 0; port < ds->num_ports; port++) {
1049                 int mtu = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1050
1051                 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1052                         mtu += VLAN_HLEN;
1053
1054                 policing[port].smax = 65535; /* Burst size in bytes */
1055                 policing[port].rate = SJA1105_RATE_MBPS(1000);
1056                 policing[port].maxlen = mtu;
1057                 policing[port].partition = 0;
1058         }
1059
1060         return 0;
1061 }
1062
1063 static int sja1105_static_config_load(struct sja1105_private *priv)
1064 {
1065         int rc;
1066
1067         sja1105_static_config_free(&priv->static_config);
1068         rc = sja1105_static_config_init(&priv->static_config,
1069                                         priv->info->static_ops,
1070                                         priv->info->device_id);
1071         if (rc)
1072                 return rc;
1073
1074         /* Build static configuration */
1075         rc = sja1105_init_mac_settings(priv);
1076         if (rc < 0)
1077                 return rc;
1078         rc = sja1105_init_mii_settings(priv);
1079         if (rc < 0)
1080                 return rc;
1081         rc = sja1105_init_static_fdb(priv);
1082         if (rc < 0)
1083                 return rc;
1084         rc = sja1105_init_static_vlan(priv);
1085         if (rc < 0)
1086                 return rc;
1087         rc = sja1105_init_l2_lookup_params(priv);
1088         if (rc < 0)
1089                 return rc;
1090         rc = sja1105_init_l2_forwarding(priv);
1091         if (rc < 0)
1092                 return rc;
1093         rc = sja1105_init_l2_forwarding_params(priv);
1094         if (rc < 0)
1095                 return rc;
1096         rc = sja1105_init_l2_policing(priv);
1097         if (rc < 0)
1098                 return rc;
1099         rc = sja1105_init_general_params(priv);
1100         if (rc < 0)
1101                 return rc;
1102         rc = sja1105_init_avb_params(priv);
1103         if (rc < 0)
1104                 return rc;
1105         rc = sja1110_init_pcp_remapping(priv);
1106         if (rc < 0)
1107                 return rc;
1108
1109         /* Send initial configuration to hardware via SPI */
1110         return sja1105_static_config_upload(priv);
1111 }
1112
1113 /* This is the "new way" for a MAC driver to configure its RGMII delay lines,
1114  * based on the explicit "rx-internal-delay-ps" and "tx-internal-delay-ps"
1115  * properties. It has the advantage of working with fixed links and with PHYs
1116  * that apply RGMII delays too, and the MAC driver needs not perform any
1117  * special checks.
1118  *
1119  * Previously we were acting upon the "phy-mode" property when we were
1120  * operating in fixed-link, basically acting as a PHY, but with a reversed
1121  * interpretation: PHY_INTERFACE_MODE_RGMII_TXID means that the MAC should
1122  * behave as if it is connected to a PHY which has applied RGMII delays in the
1123  * TX direction. So if anything, RX delays should have been added by the MAC,
1124  * but we were adding TX delays.
1125  *
1126  * If the "{rx,tx}-internal-delay-ps" properties are not specified, we fall
1127  * back to the legacy behavior and apply delays on fixed-link ports based on
1128  * the reverse interpretation of the phy-mode. This is a deviation from the
1129  * expected default behavior which is to simply apply no delays. To achieve
1130  * that behavior with the new bindings, it is mandatory to specify
1131  * "{rx,tx}-internal-delay-ps" with a value of 0.
1132  */
1133 static int sja1105_parse_rgmii_delays(struct sja1105_private *priv, int port,
1134                                       struct device_node *port_dn)
1135 {
1136         phy_interface_t phy_mode = priv->phy_mode[port];
1137         struct device *dev = &priv->spidev->dev;
1138         int rx_delay = -1, tx_delay = -1;
1139
1140         if (!phy_interface_mode_is_rgmii(phy_mode))
1141                 return 0;
1142
1143         of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);
1144         of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);
1145
1146         if (rx_delay == -1 && tx_delay == -1 && priv->fixed_link[port]) {
1147                 dev_warn(dev,
1148                          "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
1149                          "please update device tree to specify \"rx-internal-delay-ps\" and "
1150                          "\"tx-internal-delay-ps\"",
1151                          port);
1152
1153                 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
1154                     phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
1155                         rx_delay = 2000;
1156
1157                 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
1158                     phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
1159                         tx_delay = 2000;
1160         }
1161
1162         if (rx_delay < 0)
1163                 rx_delay = 0;
1164         if (tx_delay < 0)
1165                 tx_delay = 0;
1166
1167         if ((rx_delay || tx_delay) && !priv->info->setup_rgmii_delay) {
1168                 dev_err(dev, "Chip cannot apply RGMII delays\n");
1169                 return -EINVAL;
1170         }
1171
1172         if ((rx_delay && rx_delay < SJA1105_RGMII_DELAY_MIN_PS) ||
1173             (tx_delay && tx_delay < SJA1105_RGMII_DELAY_MIN_PS) ||
1174             (rx_delay > SJA1105_RGMII_DELAY_MAX_PS) ||
1175             (tx_delay > SJA1105_RGMII_DELAY_MAX_PS)) {
1176                 dev_err(dev,
1177                         "port %d RGMII delay values out of range, must be between %d and %d ps\n",
1178                         port, SJA1105_RGMII_DELAY_MIN_PS, SJA1105_RGMII_DELAY_MAX_PS);
1179                 return -ERANGE;
1180         }
1181
1182         priv->rgmii_rx_delay_ps[port] = rx_delay;
1183         priv->rgmii_tx_delay_ps[port] = tx_delay;
1184
1185         return 0;
1186 }
1187
1188 static int sja1105_parse_ports_node(struct sja1105_private *priv,
1189                                     struct device_node *ports_node)
1190 {
1191         struct device *dev = &priv->spidev->dev;
1192         struct device_node *child;
1193
1194         for_each_available_child_of_node(ports_node, child) {
1195                 struct device_node *phy_node;
1196                 phy_interface_t phy_mode;
1197                 u32 index;
1198                 int err;
1199
1200                 /* Get switch port number from DT */
1201                 if (of_property_read_u32(child, "reg", &index) < 0) {
1202                         dev_err(dev, "Port number not defined in device tree "
1203                                 "(property \"reg\")\n");
1204                         of_node_put(child);
1205                         return -ENODEV;
1206                 }
1207
1208                 /* Get PHY mode from DT */
1209                 err = of_get_phy_mode(child, &phy_mode);
1210                 if (err) {
1211                         dev_err(dev, "Failed to read phy-mode or "
1212                                 "phy-interface-type property for port %d\n",
1213                                 index);
1214                         of_node_put(child);
1215                         return -ENODEV;
1216                 }
1217
1218                 phy_node = of_parse_phandle(child, "phy-handle", 0);
1219                 if (!phy_node) {
1220                         if (!of_phy_is_fixed_link(child)) {
1221                                 dev_err(dev, "phy-handle or fixed-link "
1222                                         "properties missing!\n");
1223                                 of_node_put(child);
1224                                 return -ENODEV;
1225                         }
1226                         /* phy-handle is missing, but fixed-link isn't.
1227                          * So it's a fixed link. Default to PHY role.
1228                          */
1229                         priv->fixed_link[index] = true;
1230                 } else {
1231                         of_node_put(phy_node);
1232                 }
1233
1234                 priv->phy_mode[index] = phy_mode;
1235
1236                 err = sja1105_parse_rgmii_delays(priv, index, child);
1237                 if (err) {
1238                         of_node_put(child);
1239                         return err;
1240                 }
1241         }
1242
1243         return 0;
1244 }
1245
1246 static int sja1105_parse_dt(struct sja1105_private *priv)
1247 {
1248         struct device *dev = &priv->spidev->dev;
1249         struct device_node *switch_node = dev->of_node;
1250         struct device_node *ports_node;
1251         int rc;
1252
1253         ports_node = of_get_child_by_name(switch_node, "ports");
1254         if (!ports_node)
1255                 ports_node = of_get_child_by_name(switch_node, "ethernet-ports");
1256         if (!ports_node) {
1257                 dev_err(dev, "Incorrect bindings: absent \"ports\" node\n");
1258                 return -ENODEV;
1259         }
1260
1261         rc = sja1105_parse_ports_node(priv, ports_node);
1262         of_node_put(ports_node);
1263
1264         return rc;
1265 }
1266
1267 /* Convert link speed from SJA1105 to ethtool encoding */
1268 static int sja1105_port_speed_to_ethtool(struct sja1105_private *priv,
1269                                          u64 speed)
1270 {
1271         if (speed == priv->info->port_speed[SJA1105_SPEED_10MBPS])
1272                 return SPEED_10;
1273         if (speed == priv->info->port_speed[SJA1105_SPEED_100MBPS])
1274                 return SPEED_100;
1275         if (speed == priv->info->port_speed[SJA1105_SPEED_1000MBPS])
1276                 return SPEED_1000;
1277         if (speed == priv->info->port_speed[SJA1105_SPEED_2500MBPS])
1278                 return SPEED_2500;
1279         return SPEED_UNKNOWN;
1280 }
1281
1282 /* Set link speed in the MAC configuration for a specific port. */
1283 static int sja1105_adjust_port_config(struct sja1105_private *priv, int port,
1284                                       int speed_mbps)
1285 {
1286         struct sja1105_mac_config_entry *mac;
1287         struct device *dev = priv->ds->dev;
1288         u64 speed;
1289         int rc;
1290
1291         /* On P/Q/R/S, one can read from the device via the MAC reconfiguration
1292          * tables. On E/T, MAC reconfig tables are not readable, only writable.
1293          * We have to *know* what the MAC looks like.  For the sake of keeping
1294          * the code common, we'll use the static configuration tables as a
1295          * reasonable approximation for both E/T and P/Q/R/S.
1296          */
1297         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
1298
1299         switch (speed_mbps) {
1300         case SPEED_UNKNOWN:
1301                 /* PHYLINK called sja1105_mac_config() to inform us about
1302                  * the state->interface, but AN has not completed and the
1303                  * speed is not yet valid. UM10944.pdf says that setting
1304                  * SJA1105_SPEED_AUTO at runtime disables the port, so that is
1305                  * ok for power consumption in case AN will never complete -
1306                  * otherwise PHYLINK should come back with a new update.
1307                  */
1308                 speed = priv->info->port_speed[SJA1105_SPEED_AUTO];
1309                 break;
1310         case SPEED_10:
1311                 speed = priv->info->port_speed[SJA1105_SPEED_10MBPS];
1312                 break;
1313         case SPEED_100:
1314                 speed = priv->info->port_speed[SJA1105_SPEED_100MBPS];
1315                 break;
1316         case SPEED_1000:
1317                 speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS];
1318                 break;
1319         case SPEED_2500:
1320                 speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS];
1321                 break;
1322         default:
1323                 dev_err(dev, "Invalid speed %iMbps\n", speed_mbps);
1324                 return -EINVAL;
1325         }
1326
1327         /* Overwrite SJA1105_SPEED_AUTO from the static MAC configuration
1328          * table, since this will be used for the clocking setup, and we no
1329          * longer need to store it in the static config (already told hardware
1330          * we want auto during upload phase).
1331          * Actually for the SGMII port, the MAC is fixed at 1 Gbps and
1332          * we need to configure the PCS only (if even that).
1333          */
1334         if (priv->phy_mode[port] == PHY_INTERFACE_MODE_SGMII)
1335                 mac[port].speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS];
1336         else if (priv->phy_mode[port] == PHY_INTERFACE_MODE_2500BASEX)
1337                 mac[port].speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS];
1338         else
1339                 mac[port].speed = speed;
1340
1341         /* Write to the dynamic reconfiguration tables */
1342         rc = sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
1343                                           &mac[port], true);
1344         if (rc < 0) {
1345                 dev_err(dev, "Failed to write MAC config: %d\n", rc);
1346                 return rc;
1347         }
1348
1349         /* Reconfigure the PLLs for the RGMII interfaces (required 125 MHz at
1350          * gigabit, 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps). For MII and
1351          * RMII no change of the clock setup is required. Actually, changing
1352          * the clock setup does interrupt the clock signal for a certain time
1353          * which causes trouble for all PHYs relying on this signal.
1354          */
1355         if (!phy_interface_mode_is_rgmii(priv->phy_mode[port]))
1356                 return 0;
1357
1358         return sja1105_clocking_setup_port(priv, port);
1359 }
1360
1361 /* The SJA1105 MAC programming model is through the static config (the xMII
1362  * Mode table cannot be dynamically reconfigured), and we have to program
1363  * that early (earlier than PHYLINK calls us, anyway).
1364  * So just error out in case the connected PHY attempts to change the initial
1365  * system interface MII protocol from what is defined in the DT, at least for
1366  * now.
1367  */
1368 static bool sja1105_phy_mode_mismatch(struct sja1105_private *priv, int port,
1369                                       phy_interface_t interface)
1370 {
1371         return priv->phy_mode[port] != interface;
1372 }
1373
1374 static void sja1105_mac_config(struct dsa_switch *ds, int port,
1375                                unsigned int mode,
1376                                const struct phylink_link_state *state)
1377 {
1378         struct dsa_port *dp = dsa_to_port(ds, port);
1379         struct sja1105_private *priv = ds->priv;
1380         struct dw_xpcs *xpcs;
1381
1382         if (sja1105_phy_mode_mismatch(priv, port, state->interface)) {
1383                 dev_err(ds->dev, "Changing PHY mode to %s not supported!\n",
1384                         phy_modes(state->interface));
1385                 return;
1386         }
1387
1388         xpcs = priv->xpcs[port];
1389
1390         if (xpcs)
1391                 phylink_set_pcs(dp->pl, &xpcs->pcs);
1392 }
1393
1394 static void sja1105_mac_link_down(struct dsa_switch *ds, int port,
1395                                   unsigned int mode,
1396                                   phy_interface_t interface)
1397 {
1398         sja1105_inhibit_tx(ds->priv, BIT(port), true);
1399 }
1400
1401 static void sja1105_mac_link_up(struct dsa_switch *ds, int port,
1402                                 unsigned int mode,
1403                                 phy_interface_t interface,
1404                                 struct phy_device *phydev,
1405                                 int speed, int duplex,
1406                                 bool tx_pause, bool rx_pause)
1407 {
1408         struct sja1105_private *priv = ds->priv;
1409
1410         sja1105_adjust_port_config(priv, port, speed);
1411
1412         sja1105_inhibit_tx(priv, BIT(port), false);
1413 }
1414
1415 static void sja1105_phylink_validate(struct dsa_switch *ds, int port,
1416                                      unsigned long *supported,
1417                                      struct phylink_link_state *state)
1418 {
1419         /* Construct a new mask which exhaustively contains all link features
1420          * supported by the MAC, and then apply that (logical AND) to what will
1421          * be sent to the PHY for "marketing".
1422          */
1423         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1424         struct sja1105_private *priv = ds->priv;
1425         struct sja1105_xmii_params_entry *mii;
1426
1427         mii = priv->static_config.tables[BLK_IDX_XMII_PARAMS].entries;
1428
1429         /* include/linux/phylink.h says:
1430          *     When @state->interface is %PHY_INTERFACE_MODE_NA, phylink
1431          *     expects the MAC driver to return all supported link modes.
1432          */
1433         if (state->interface != PHY_INTERFACE_MODE_NA &&
1434             sja1105_phy_mode_mismatch(priv, port, state->interface)) {
1435                 linkmode_zero(supported);
1436                 return;
1437         }
1438
1439         /* The MAC does not support pause frames, and also doesn't
1440          * support half-duplex traffic modes.
1441          */
1442         phylink_set(mask, Autoneg);
1443         phylink_set(mask, MII);
1444         phylink_set(mask, 10baseT_Full);
1445         phylink_set(mask, 100baseT_Full);
1446         phylink_set(mask, 100baseT1_Full);
1447         if (mii->xmii_mode[port] == XMII_MODE_RGMII ||
1448             mii->xmii_mode[port] == XMII_MODE_SGMII)
1449                 phylink_set(mask, 1000baseT_Full);
1450         if (priv->info->supports_2500basex[port]) {
1451                 phylink_set(mask, 2500baseT_Full);
1452                 phylink_set(mask, 2500baseX_Full);
1453         }
1454
1455         linkmode_and(supported, supported, mask);
1456         linkmode_and(state->advertising, state->advertising, mask);
1457 }
1458
1459 static int
1460 sja1105_find_static_fdb_entry(struct sja1105_private *priv, int port,
1461                               const struct sja1105_l2_lookup_entry *requested)
1462 {
1463         struct sja1105_l2_lookup_entry *l2_lookup;
1464         struct sja1105_table *table;
1465         int i;
1466
1467         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
1468         l2_lookup = table->entries;
1469
1470         for (i = 0; i < table->entry_count; i++)
1471                 if (l2_lookup[i].macaddr == requested->macaddr &&
1472                     l2_lookup[i].vlanid == requested->vlanid &&
1473                     l2_lookup[i].destports & BIT(port))
1474                         return i;
1475
1476         return -1;
1477 }
1478
1479 /* We want FDB entries added statically through the bridge command to persist
1480  * across switch resets, which are a common thing during normal SJA1105
1481  * operation. So we have to back them up in the static configuration tables
1482  * and hence apply them on next static config upload... yay!
1483  */
1484 static int
1485 sja1105_static_fdb_change(struct sja1105_private *priv, int port,
1486                           const struct sja1105_l2_lookup_entry *requested,
1487                           bool keep)
1488 {
1489         struct sja1105_l2_lookup_entry *l2_lookup;
1490         struct sja1105_table *table;
1491         int rc, match;
1492
1493         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
1494
1495         match = sja1105_find_static_fdb_entry(priv, port, requested);
1496         if (match < 0) {
1497                 /* Can't delete a missing entry. */
1498                 if (!keep)
1499                         return 0;
1500
1501                 /* No match => new entry */
1502                 rc = sja1105_table_resize(table, table->entry_count + 1);
1503                 if (rc)
1504                         return rc;
1505
1506                 match = table->entry_count - 1;
1507         }
1508
1509         /* Assign pointer after the resize (it may be new memory) */
1510         l2_lookup = table->entries;
1511
1512         /* We have a match.
1513          * If the job was to add this FDB entry, it's already done (mostly
1514          * anyway, since the port forwarding mask may have changed, case in
1515          * which we update it).
1516          * Otherwise we have to delete it.
1517          */
1518         if (keep) {
1519                 l2_lookup[match] = *requested;
1520                 return 0;
1521         }
1522
1523         /* To remove, the strategy is to overwrite the element with
1524          * the last one, and then reduce the array size by 1
1525          */
1526         l2_lookup[match] = l2_lookup[table->entry_count - 1];
1527         return sja1105_table_resize(table, table->entry_count - 1);
1528 }
1529
1530 /* First-generation switches have a 4-way set associative TCAM that
1531  * holds the FDB entries. An FDB index spans from 0 to 1023 and is comprised of
1532  * a "bin" (grouping of 4 entries) and a "way" (an entry within a bin).
1533  * For the placement of a newly learnt FDB entry, the switch selects the bin
1534  * based on a hash function, and the way within that bin incrementally.
1535  */
1536 static int sja1105et_fdb_index(int bin, int way)
1537 {
1538         return bin * SJA1105ET_FDB_BIN_SIZE + way;
1539 }
1540
1541 static int sja1105et_is_fdb_entry_in_bin(struct sja1105_private *priv, int bin,
1542                                          const u8 *addr, u16 vid,
1543                                          struct sja1105_l2_lookup_entry *match,
1544                                          int *last_unused)
1545 {
1546         int way;
1547
1548         for (way = 0; way < SJA1105ET_FDB_BIN_SIZE; way++) {
1549                 struct sja1105_l2_lookup_entry l2_lookup = {0};
1550                 int index = sja1105et_fdb_index(bin, way);
1551
1552                 /* Skip unused entries, optionally marking them
1553                  * into the return value
1554                  */
1555                 if (sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1556                                                 index, &l2_lookup)) {
1557                         if (last_unused)
1558                                 *last_unused = way;
1559                         continue;
1560                 }
1561
1562                 if (l2_lookup.macaddr == ether_addr_to_u64(addr) &&
1563                     l2_lookup.vlanid == vid) {
1564                         if (match)
1565                                 *match = l2_lookup;
1566                         return way;
1567                 }
1568         }
1569         /* Return an invalid entry index if not found */
1570         return -1;
1571 }
1572
1573 int sja1105et_fdb_add(struct dsa_switch *ds, int port,
1574                       const unsigned char *addr, u16 vid)
1575 {
1576         struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp;
1577         struct sja1105_private *priv = ds->priv;
1578         struct device *dev = ds->dev;
1579         int last_unused = -1;
1580         int start, end, i;
1581         int bin, way, rc;
1582
1583         bin = sja1105et_fdb_hash(priv, addr, vid);
1584
1585         way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid,
1586                                             &l2_lookup, &last_unused);
1587         if (way >= 0) {
1588                 /* We have an FDB entry. Is our port in the destination
1589                  * mask? If yes, we need to do nothing. If not, we need
1590                  * to rewrite the entry by adding this port to it.
1591                  */
1592                 if ((l2_lookup.destports & BIT(port)) && l2_lookup.lockeds)
1593                         return 0;
1594                 l2_lookup.destports |= BIT(port);
1595         } else {
1596                 int index = sja1105et_fdb_index(bin, way);
1597
1598                 /* We don't have an FDB entry. We construct a new one and
1599                  * try to find a place for it within the FDB table.
1600                  */
1601                 l2_lookup.macaddr = ether_addr_to_u64(addr);
1602                 l2_lookup.destports = BIT(port);
1603                 l2_lookup.vlanid = vid;
1604
1605                 if (last_unused >= 0) {
1606                         way = last_unused;
1607                 } else {
1608                         /* Bin is full, need to evict somebody.
1609                          * Choose victim at random. If you get these messages
1610                          * often, you may need to consider changing the
1611                          * distribution function:
1612                          * static_config[BLK_IDX_L2_LOOKUP_PARAMS].entries->poly
1613                          */
1614                         get_random_bytes(&way, sizeof(u8));
1615                         way %= SJA1105ET_FDB_BIN_SIZE;
1616                         dev_warn(dev, "Warning, FDB bin %d full while adding entry for %pM. Evicting entry %u.\n",
1617                                  bin, addr, way);
1618                         /* Evict entry */
1619                         sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1620                                                      index, NULL, false);
1621                 }
1622         }
1623         l2_lookup.lockeds = true;
1624         l2_lookup.index = sja1105et_fdb_index(bin, way);
1625
1626         rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1627                                           l2_lookup.index, &l2_lookup,
1628                                           true);
1629         if (rc < 0)
1630                 return rc;
1631
1632         /* Invalidate a dynamically learned entry if that exists */
1633         start = sja1105et_fdb_index(bin, 0);
1634         end = sja1105et_fdb_index(bin, way);
1635
1636         for (i = start; i < end; i++) {
1637                 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1638                                                  i, &tmp);
1639                 if (rc == -ENOENT)
1640                         continue;
1641                 if (rc)
1642                         return rc;
1643
1644                 if (tmp.macaddr != ether_addr_to_u64(addr) || tmp.vlanid != vid)
1645                         continue;
1646
1647                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1648                                                   i, NULL, false);
1649                 if (rc)
1650                         return rc;
1651
1652                 break;
1653         }
1654
1655         return sja1105_static_fdb_change(priv, port, &l2_lookup, true);
1656 }
1657
1658 int sja1105et_fdb_del(struct dsa_switch *ds, int port,
1659                       const unsigned char *addr, u16 vid)
1660 {
1661         struct sja1105_l2_lookup_entry l2_lookup = {0};
1662         struct sja1105_private *priv = ds->priv;
1663         int index, bin, way, rc;
1664         bool keep;
1665
1666         bin = sja1105et_fdb_hash(priv, addr, vid);
1667         way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid,
1668                                             &l2_lookup, NULL);
1669         if (way < 0)
1670                 return 0;
1671         index = sja1105et_fdb_index(bin, way);
1672
1673         /* We have an FDB entry. Is our port in the destination mask? If yes,
1674          * we need to remove it. If the resulting port mask becomes empty, we
1675          * need to completely evict the FDB entry.
1676          * Otherwise we just write it back.
1677          */
1678         l2_lookup.destports &= ~BIT(port);
1679
1680         if (l2_lookup.destports)
1681                 keep = true;
1682         else
1683                 keep = false;
1684
1685         rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1686                                           index, &l2_lookup, keep);
1687         if (rc < 0)
1688                 return rc;
1689
1690         return sja1105_static_fdb_change(priv, port, &l2_lookup, keep);
1691 }
1692
1693 int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port,
1694                         const unsigned char *addr, u16 vid)
1695 {
1696         struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp;
1697         struct sja1105_private *priv = ds->priv;
1698         int rc, i;
1699
1700         /* Search for an existing entry in the FDB table */
1701         l2_lookup.macaddr = ether_addr_to_u64(addr);
1702         l2_lookup.vlanid = vid;
1703         l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0);
1704         l2_lookup.mask_vlanid = VLAN_VID_MASK;
1705         l2_lookup.destports = BIT(port);
1706
1707         tmp = l2_lookup;
1708
1709         rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1710                                          SJA1105_SEARCH, &tmp);
1711         if (rc == 0 && tmp.index != SJA1105_MAX_L2_LOOKUP_COUNT - 1) {
1712                 /* Found a static entry and this port is already in the entry's
1713                  * port mask => job done
1714                  */
1715                 if ((tmp.destports & BIT(port)) && tmp.lockeds)
1716                         return 0;
1717
1718                 l2_lookup = tmp;
1719
1720                 /* l2_lookup.index is populated by the switch in case it
1721                  * found something.
1722                  */
1723                 l2_lookup.destports |= BIT(port);
1724                 goto skip_finding_an_index;
1725         }
1726
1727         /* Not found, so try to find an unused spot in the FDB.
1728          * This is slightly inefficient because the strategy is knock-knock at
1729          * every possible position from 0 to 1023.
1730          */
1731         for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1732                 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1733                                                  i, NULL);
1734                 if (rc < 0)
1735                         break;
1736         }
1737         if (i == SJA1105_MAX_L2_LOOKUP_COUNT) {
1738                 dev_err(ds->dev, "FDB is full, cannot add entry.\n");
1739                 return -EINVAL;
1740         }
1741         l2_lookup.index = i;
1742
1743 skip_finding_an_index:
1744         l2_lookup.lockeds = true;
1745
1746         rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1747                                           l2_lookup.index, &l2_lookup,
1748                                           true);
1749         if (rc < 0)
1750                 return rc;
1751
1752         /* The switch learns dynamic entries and looks up the FDB left to
1753          * right. It is possible that our addition was concurrent with the
1754          * dynamic learning of the same address, so now that the static entry
1755          * has been installed, we are certain that address learning for this
1756          * particular address has been turned off, so the dynamic entry either
1757          * is in the FDB at an index smaller than the static one, or isn't (it
1758          * can also be at a larger index, but in that case it is inactive
1759          * because the static FDB entry will match first, and the dynamic one
1760          * will eventually age out). Search for a dynamically learned address
1761          * prior to our static one and invalidate it.
1762          */
1763         tmp = l2_lookup;
1764
1765         rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1766                                          SJA1105_SEARCH, &tmp);
1767         if (rc < 0) {
1768                 dev_err(ds->dev,
1769                         "port %d failed to read back entry for %pM vid %d: %pe\n",
1770                         port, addr, vid, ERR_PTR(rc));
1771                 return rc;
1772         }
1773
1774         if (tmp.index < l2_lookup.index) {
1775                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1776                                                   tmp.index, NULL, false);
1777                 if (rc < 0)
1778                         return rc;
1779         }
1780
1781         return sja1105_static_fdb_change(priv, port, &l2_lookup, true);
1782 }
1783
1784 int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port,
1785                         const unsigned char *addr, u16 vid)
1786 {
1787         struct sja1105_l2_lookup_entry l2_lookup = {0};
1788         struct sja1105_private *priv = ds->priv;
1789         bool keep;
1790         int rc;
1791
1792         l2_lookup.macaddr = ether_addr_to_u64(addr);
1793         l2_lookup.vlanid = vid;
1794         l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0);
1795         l2_lookup.mask_vlanid = VLAN_VID_MASK;
1796         l2_lookup.destports = BIT(port);
1797
1798         rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1799                                          SJA1105_SEARCH, &l2_lookup);
1800         if (rc < 0)
1801                 return 0;
1802
1803         l2_lookup.destports &= ~BIT(port);
1804
1805         /* Decide whether we remove just this port from the FDB entry,
1806          * or if we remove it completely.
1807          */
1808         if (l2_lookup.destports)
1809                 keep = true;
1810         else
1811                 keep = false;
1812
1813         rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1814                                           l2_lookup.index, &l2_lookup, keep);
1815         if (rc < 0)
1816                 return rc;
1817
1818         return sja1105_static_fdb_change(priv, port, &l2_lookup, keep);
1819 }
1820
1821 static int sja1105_fdb_add(struct dsa_switch *ds, int port,
1822                            const unsigned char *addr, u16 vid)
1823 {
1824         struct sja1105_private *priv = ds->priv;
1825
1826         return priv->info->fdb_add_cmd(ds, port, addr, vid);
1827 }
1828
1829 static int sja1105_fdb_del(struct dsa_switch *ds, int port,
1830                            const unsigned char *addr, u16 vid)
1831 {
1832         struct sja1105_private *priv = ds->priv;
1833
1834         return priv->info->fdb_del_cmd(ds, port, addr, vid);
1835 }
1836
1837 static int sja1105_fdb_dump(struct dsa_switch *ds, int port,
1838                             dsa_fdb_dump_cb_t *cb, void *data)
1839 {
1840         struct dsa_port *dp = dsa_to_port(ds, port);
1841         struct sja1105_private *priv = ds->priv;
1842         struct device *dev = ds->dev;
1843         int i;
1844
1845         for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1846                 struct sja1105_l2_lookup_entry l2_lookup = {0};
1847                 u8 macaddr[ETH_ALEN];
1848                 int rc;
1849
1850                 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1851                                                  i, &l2_lookup);
1852                 /* No fdb entry at i, not an issue */
1853                 if (rc == -ENOENT)
1854                         continue;
1855                 if (rc) {
1856                         dev_err(dev, "Failed to dump FDB: %d\n", rc);
1857                         return rc;
1858                 }
1859
1860                 /* FDB dump callback is per port. This means we have to
1861                  * disregard a valid entry if it's not for this port, even if
1862                  * only to revisit it later. This is inefficient because the
1863                  * 1024-sized FDB table needs to be traversed 4 times through
1864                  * SPI during a 'bridge fdb show' command.
1865                  */
1866                 if (!(l2_lookup.destports & BIT(port)))
1867                         continue;
1868
1869                 /* We need to hide the FDB entry for unknown multicast */
1870                 if (l2_lookup.macaddr == SJA1105_UNKNOWN_MULTICAST &&
1871                     l2_lookup.mask_macaddr == SJA1105_UNKNOWN_MULTICAST)
1872                         continue;
1873
1874                 u64_to_ether_addr(l2_lookup.macaddr, macaddr);
1875
1876                 /* We need to hide the dsa_8021q VLANs from the user. */
1877                 if (!dsa_port_is_vlan_filtering(dp))
1878                         l2_lookup.vlanid = 0;
1879                 rc = cb(macaddr, l2_lookup.vlanid, l2_lookup.lockeds, data);
1880                 if (rc)
1881                         return rc;
1882         }
1883         return 0;
1884 }
1885
1886 static void sja1105_fast_age(struct dsa_switch *ds, int port)
1887 {
1888         struct sja1105_private *priv = ds->priv;
1889         int i;
1890
1891         for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1892                 struct sja1105_l2_lookup_entry l2_lookup = {0};
1893                 u8 macaddr[ETH_ALEN];
1894                 int rc;
1895
1896                 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1897                                                  i, &l2_lookup);
1898                 /* No fdb entry at i, not an issue */
1899                 if (rc == -ENOENT)
1900                         continue;
1901                 if (rc) {
1902                         dev_err(ds->dev, "Failed to read FDB: %pe\n",
1903                                 ERR_PTR(rc));
1904                         return;
1905                 }
1906
1907                 if (!(l2_lookup.destports & BIT(port)))
1908                         continue;
1909
1910                 /* Don't delete static FDB entries */
1911                 if (l2_lookup.lockeds)
1912                         continue;
1913
1914                 u64_to_ether_addr(l2_lookup.macaddr, macaddr);
1915
1916                 rc = sja1105_fdb_del(ds, port, macaddr, l2_lookup.vlanid);
1917                 if (rc) {
1918                         dev_err(ds->dev,
1919                                 "Failed to delete FDB entry %pM vid %lld: %pe\n",
1920                                 macaddr, l2_lookup.vlanid, ERR_PTR(rc));
1921                         return;
1922                 }
1923         }
1924 }
1925
1926 static int sja1105_mdb_add(struct dsa_switch *ds, int port,
1927                            const struct switchdev_obj_port_mdb *mdb)
1928 {
1929         return sja1105_fdb_add(ds, port, mdb->addr, mdb->vid);
1930 }
1931
1932 static int sja1105_mdb_del(struct dsa_switch *ds, int port,
1933                            const struct switchdev_obj_port_mdb *mdb)
1934 {
1935         return sja1105_fdb_del(ds, port, mdb->addr, mdb->vid);
1936 }
1937
1938 /* Common function for unicast and broadcast flood configuration.
1939  * Flooding is configured between each {ingress, egress} port pair, and since
1940  * the bridge's semantics are those of "egress flooding", it means we must
1941  * enable flooding towards this port from all ingress ports that are in the
1942  * same forwarding domain.
1943  */
1944 static int sja1105_manage_flood_domains(struct sja1105_private *priv)
1945 {
1946         struct sja1105_l2_forwarding_entry *l2_fwd;
1947         struct dsa_switch *ds = priv->ds;
1948         int from, to, rc;
1949
1950         l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries;
1951
1952         for (from = 0; from < ds->num_ports; from++) {
1953                 u64 fl_domain = 0, bc_domain = 0;
1954
1955                 for (to = 0; to < priv->ds->num_ports; to++) {
1956                         if (!sja1105_can_forward(l2_fwd, from, to))
1957                                 continue;
1958
1959                         if (priv->ucast_egress_floods & BIT(to))
1960                                 fl_domain |= BIT(to);
1961                         if (priv->bcast_egress_floods & BIT(to))
1962                                 bc_domain |= BIT(to);
1963                 }
1964
1965                 /* Nothing changed, nothing to do */
1966                 if (l2_fwd[from].fl_domain == fl_domain &&
1967                     l2_fwd[from].bc_domain == bc_domain)
1968                         continue;
1969
1970                 l2_fwd[from].fl_domain = fl_domain;
1971                 l2_fwd[from].bc_domain = bc_domain;
1972
1973                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
1974                                                   from, &l2_fwd[from], true);
1975                 if (rc < 0)
1976                         return rc;
1977         }
1978
1979         return 0;
1980 }
1981
1982 static int sja1105_bridge_member(struct dsa_switch *ds, int port,
1983                                  struct dsa_bridge bridge, bool member)
1984 {
1985         struct sja1105_l2_forwarding_entry *l2_fwd;
1986         struct sja1105_private *priv = ds->priv;
1987         int i, rc;
1988
1989         l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries;
1990
1991         for (i = 0; i < ds->num_ports; i++) {
1992                 /* Add this port to the forwarding matrix of the
1993                  * other ports in the same bridge, and viceversa.
1994                  */
1995                 if (!dsa_is_user_port(ds, i))
1996                         continue;
1997                 /* For the ports already under the bridge, only one thing needs
1998                  * to be done, and that is to add this port to their
1999                  * reachability domain. So we can perform the SPI write for
2000                  * them immediately. However, for this port itself (the one
2001                  * that is new to the bridge), we need to add all other ports
2002                  * to its reachability domain. So we do that incrementally in
2003                  * this loop, and perform the SPI write only at the end, once
2004                  * the domain contains all other bridge ports.
2005                  */
2006                 if (i == port)
2007                         continue;
2008                 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
2009                         continue;
2010                 sja1105_port_allow_traffic(l2_fwd, i, port, member);
2011                 sja1105_port_allow_traffic(l2_fwd, port, i, member);
2012
2013                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
2014                                                   i, &l2_fwd[i], true);
2015                 if (rc < 0)
2016                         return rc;
2017         }
2018
2019         rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
2020                                           port, &l2_fwd[port], true);
2021         if (rc)
2022                 return rc;
2023
2024         rc = sja1105_commit_pvid(ds, port);
2025         if (rc)
2026                 return rc;
2027
2028         return sja1105_manage_flood_domains(priv);
2029 }
2030
2031 static void sja1105_bridge_stp_state_set(struct dsa_switch *ds, int port,
2032                                          u8 state)
2033 {
2034         struct dsa_port *dp = dsa_to_port(ds, port);
2035         struct sja1105_private *priv = ds->priv;
2036         struct sja1105_mac_config_entry *mac;
2037
2038         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2039
2040         switch (state) {
2041         case BR_STATE_DISABLED:
2042         case BR_STATE_BLOCKING:
2043                 /* From UM10944 description of DRPDTAG (why put this there?):
2044                  * "Management traffic flows to the port regardless of the state
2045                  * of the INGRESS flag". So BPDUs are still be allowed to pass.
2046                  * At the moment no difference between DISABLED and BLOCKING.
2047                  */
2048                 mac[port].ingress   = false;
2049                 mac[port].egress    = false;
2050                 mac[port].dyn_learn = false;
2051                 break;
2052         case BR_STATE_LISTENING:
2053                 mac[port].ingress   = true;
2054                 mac[port].egress    = false;
2055                 mac[port].dyn_learn = false;
2056                 break;
2057         case BR_STATE_LEARNING:
2058                 mac[port].ingress   = true;
2059                 mac[port].egress    = false;
2060                 mac[port].dyn_learn = dp->learning;
2061                 break;
2062         case BR_STATE_FORWARDING:
2063                 mac[port].ingress   = true;
2064                 mac[port].egress    = true;
2065                 mac[port].dyn_learn = dp->learning;
2066                 break;
2067         default:
2068                 dev_err(ds->dev, "invalid STP state: %d\n", state);
2069                 return;
2070         }
2071
2072         sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
2073                                      &mac[port], true);
2074 }
2075
2076 static int sja1105_bridge_join(struct dsa_switch *ds, int port,
2077                                struct dsa_bridge bridge,
2078                                bool *tx_fwd_offload)
2079 {
2080         int rc;
2081
2082         rc = sja1105_bridge_member(ds, port, bridge, true);
2083         if (rc)
2084                 return rc;
2085
2086         rc = dsa_tag_8021q_bridge_tx_fwd_offload(ds, port, bridge);
2087         if (rc) {
2088                 sja1105_bridge_member(ds, port, bridge, false);
2089                 return rc;
2090         }
2091
2092         *tx_fwd_offload = true;
2093
2094         return 0;
2095 }
2096
2097 static void sja1105_bridge_leave(struct dsa_switch *ds, int port,
2098                                  struct dsa_bridge bridge)
2099 {
2100         dsa_tag_8021q_bridge_tx_fwd_unoffload(ds, port, bridge);
2101         sja1105_bridge_member(ds, port, bridge, false);
2102 }
2103
2104 #define BYTES_PER_KBIT (1000LL / 8)
2105
2106 static int sja1105_find_unused_cbs_shaper(struct sja1105_private *priv)
2107 {
2108         int i;
2109
2110         for (i = 0; i < priv->info->num_cbs_shapers; i++)
2111                 if (!priv->cbs[i].idle_slope && !priv->cbs[i].send_slope)
2112                         return i;
2113
2114         return -1;
2115 }
2116
2117 static int sja1105_delete_cbs_shaper(struct sja1105_private *priv, int port,
2118                                      int prio)
2119 {
2120         int i;
2121
2122         for (i = 0; i < priv->info->num_cbs_shapers; i++) {
2123                 struct sja1105_cbs_entry *cbs = &priv->cbs[i];
2124
2125                 if (cbs->port == port && cbs->prio == prio) {
2126                         memset(cbs, 0, sizeof(*cbs));
2127                         return sja1105_dynamic_config_write(priv, BLK_IDX_CBS,
2128                                                             i, cbs, true);
2129                 }
2130         }
2131
2132         return 0;
2133 }
2134
2135 static int sja1105_setup_tc_cbs(struct dsa_switch *ds, int port,
2136                                 struct tc_cbs_qopt_offload *offload)
2137 {
2138         struct sja1105_private *priv = ds->priv;
2139         struct sja1105_cbs_entry *cbs;
2140         int index;
2141
2142         if (!offload->enable)
2143                 return sja1105_delete_cbs_shaper(priv, port, offload->queue);
2144
2145         index = sja1105_find_unused_cbs_shaper(priv);
2146         if (index < 0)
2147                 return -ENOSPC;
2148
2149         cbs = &priv->cbs[index];
2150         cbs->port = port;
2151         cbs->prio = offload->queue;
2152         /* locredit and sendslope are negative by definition. In hardware,
2153          * positive values must be provided, and the negative sign is implicit.
2154          */
2155         cbs->credit_hi = offload->hicredit;
2156         cbs->credit_lo = abs(offload->locredit);
2157         /* User space is in kbits/sec, hardware in bytes/sec */
2158         cbs->idle_slope = offload->idleslope * BYTES_PER_KBIT;
2159         cbs->send_slope = abs(offload->sendslope * BYTES_PER_KBIT);
2160         /* Convert the negative values from 64-bit 2's complement
2161          * to 32-bit 2's complement (for the case of 0x80000000 whose
2162          * negative is still negative).
2163          */
2164         cbs->credit_lo &= GENMASK_ULL(31, 0);
2165         cbs->send_slope &= GENMASK_ULL(31, 0);
2166
2167         return sja1105_dynamic_config_write(priv, BLK_IDX_CBS, index, cbs,
2168                                             true);
2169 }
2170
2171 static int sja1105_reload_cbs(struct sja1105_private *priv)
2172 {
2173         int rc = 0, i;
2174
2175         /* The credit based shapers are only allocated if
2176          * CONFIG_NET_SCH_CBS is enabled.
2177          */
2178         if (!priv->cbs)
2179                 return 0;
2180
2181         for (i = 0; i < priv->info->num_cbs_shapers; i++) {
2182                 struct sja1105_cbs_entry *cbs = &priv->cbs[i];
2183
2184                 if (!cbs->idle_slope && !cbs->send_slope)
2185                         continue;
2186
2187                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_CBS, i, cbs,
2188                                                   true);
2189                 if (rc)
2190                         break;
2191         }
2192
2193         return rc;
2194 }
2195
2196 static const char * const sja1105_reset_reasons[] = {
2197         [SJA1105_VLAN_FILTERING] = "VLAN filtering",
2198         [SJA1105_RX_HWTSTAMPING] = "RX timestamping",
2199         [SJA1105_AGEING_TIME] = "Ageing time",
2200         [SJA1105_SCHEDULING] = "Time-aware scheduling",
2201         [SJA1105_BEST_EFFORT_POLICING] = "Best-effort policing",
2202         [SJA1105_VIRTUAL_LINKS] = "Virtual links",
2203 };
2204
2205 /* For situations where we need to change a setting at runtime that is only
2206  * available through the static configuration, resetting the switch in order
2207  * to upload the new static config is unavoidable. Back up the settings we
2208  * modify at runtime (currently only MAC) and restore them after uploading,
2209  * such that this operation is relatively seamless.
2210  */
2211 int sja1105_static_config_reload(struct sja1105_private *priv,
2212                                  enum sja1105_reset_reason reason)
2213 {
2214         struct ptp_system_timestamp ptp_sts_before;
2215         struct ptp_system_timestamp ptp_sts_after;
2216         int speed_mbps[SJA1105_MAX_NUM_PORTS];
2217         u16 bmcr[SJA1105_MAX_NUM_PORTS] = {0};
2218         struct sja1105_mac_config_entry *mac;
2219         struct dsa_switch *ds = priv->ds;
2220         s64 t1, t2, t3, t4;
2221         s64 t12, t34;
2222         int rc, i;
2223         s64 now;
2224
2225         mutex_lock(&priv->mgmt_lock);
2226
2227         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2228
2229         /* Back up the dynamic link speed changed by sja1105_adjust_port_config
2230          * in order to temporarily restore it to SJA1105_SPEED_AUTO - which the
2231          * switch wants to see in the static config in order to allow us to
2232          * change it through the dynamic interface later.
2233          */
2234         for (i = 0; i < ds->num_ports; i++) {
2235                 u32 reg_addr = mdiobus_c45_addr(MDIO_MMD_VEND2, MDIO_CTRL1);
2236
2237                 speed_mbps[i] = sja1105_port_speed_to_ethtool(priv,
2238                                                               mac[i].speed);
2239                 mac[i].speed = priv->info->port_speed[SJA1105_SPEED_AUTO];
2240
2241                 if (priv->xpcs[i])
2242                         bmcr[i] = mdiobus_read(priv->mdio_pcs, i, reg_addr);
2243         }
2244
2245         /* No PTP operations can run right now */
2246         mutex_lock(&priv->ptp_data.lock);
2247
2248         rc = __sja1105_ptp_gettimex(ds, &now, &ptp_sts_before);
2249         if (rc < 0) {
2250                 mutex_unlock(&priv->ptp_data.lock);
2251                 goto out;
2252         }
2253
2254         /* Reset switch and send updated static configuration */
2255         rc = sja1105_static_config_upload(priv);
2256         if (rc < 0) {
2257                 mutex_unlock(&priv->ptp_data.lock);
2258                 goto out;
2259         }
2260
2261         rc = __sja1105_ptp_settime(ds, 0, &ptp_sts_after);
2262         if (rc < 0) {
2263                 mutex_unlock(&priv->ptp_data.lock);
2264                 goto out;
2265         }
2266
2267         t1 = timespec64_to_ns(&ptp_sts_before.pre_ts);
2268         t2 = timespec64_to_ns(&ptp_sts_before.post_ts);
2269         t3 = timespec64_to_ns(&ptp_sts_after.pre_ts);
2270         t4 = timespec64_to_ns(&ptp_sts_after.post_ts);
2271         /* Mid point, corresponds to pre-reset PTPCLKVAL */
2272         t12 = t1 + (t2 - t1) / 2;
2273         /* Mid point, corresponds to post-reset PTPCLKVAL, aka 0 */
2274         t34 = t3 + (t4 - t3) / 2;
2275         /* Advance PTPCLKVAL by the time it took since its readout */
2276         now += (t34 - t12);
2277
2278         __sja1105_ptp_adjtime(ds, now);
2279
2280         mutex_unlock(&priv->ptp_data.lock);
2281
2282         dev_info(priv->ds->dev,
2283                  "Reset switch and programmed static config. Reason: %s\n",
2284                  sja1105_reset_reasons[reason]);
2285
2286         /* Configure the CGU (PLLs) for MII and RMII PHYs.
2287          * For these interfaces there is no dynamic configuration
2288          * needed, since PLLs have same settings at all speeds.
2289          */
2290         if (priv->info->clocking_setup) {
2291                 rc = priv->info->clocking_setup(priv);
2292                 if (rc < 0)
2293                         goto out;
2294         }
2295
2296         for (i = 0; i < ds->num_ports; i++) {
2297                 struct dw_xpcs *xpcs = priv->xpcs[i];
2298                 unsigned int mode;
2299
2300                 rc = sja1105_adjust_port_config(priv, i, speed_mbps[i]);
2301                 if (rc < 0)
2302                         goto out;
2303
2304                 if (!xpcs)
2305                         continue;
2306
2307                 if (bmcr[i] & BMCR_ANENABLE)
2308                         mode = MLO_AN_INBAND;
2309                 else if (priv->fixed_link[i])
2310                         mode = MLO_AN_FIXED;
2311                 else
2312                         mode = MLO_AN_PHY;
2313
2314                 rc = xpcs_do_config(xpcs, priv->phy_mode[i], mode);
2315                 if (rc < 0)
2316                         goto out;
2317
2318                 if (!phylink_autoneg_inband(mode)) {
2319                         int speed = SPEED_UNKNOWN;
2320
2321                         if (priv->phy_mode[i] == PHY_INTERFACE_MODE_2500BASEX)
2322                                 speed = SPEED_2500;
2323                         else if (bmcr[i] & BMCR_SPEED1000)
2324                                 speed = SPEED_1000;
2325                         else if (bmcr[i] & BMCR_SPEED100)
2326                                 speed = SPEED_100;
2327                         else
2328                                 speed = SPEED_10;
2329
2330                         xpcs_link_up(&xpcs->pcs, mode, priv->phy_mode[i],
2331                                      speed, DUPLEX_FULL);
2332                 }
2333         }
2334
2335         rc = sja1105_reload_cbs(priv);
2336         if (rc < 0)
2337                 goto out;
2338 out:
2339         mutex_unlock(&priv->mgmt_lock);
2340
2341         return rc;
2342 }
2343
2344 static enum dsa_tag_protocol
2345 sja1105_get_tag_protocol(struct dsa_switch *ds, int port,
2346                          enum dsa_tag_protocol mp)
2347 {
2348         struct sja1105_private *priv = ds->priv;
2349
2350         return priv->info->tag_proto;
2351 }
2352
2353 /* The TPID setting belongs to the General Parameters table,
2354  * which can only be partially reconfigured at runtime (and not the TPID).
2355  * So a switch reset is required.
2356  */
2357 int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled,
2358                            struct netlink_ext_ack *extack)
2359 {
2360         struct sja1105_l2_lookup_params_entry *l2_lookup_params;
2361         struct sja1105_general_params_entry *general_params;
2362         struct sja1105_private *priv = ds->priv;
2363         struct sja1105_table *table;
2364         struct sja1105_rule *rule;
2365         u16 tpid, tpid2;
2366         int rc;
2367
2368         list_for_each_entry(rule, &priv->flow_block.rules, list) {
2369                 if (rule->type == SJA1105_RULE_VL) {
2370                         NL_SET_ERR_MSG_MOD(extack,
2371                                            "Cannot change VLAN filtering with active VL rules");
2372                         return -EBUSY;
2373                 }
2374         }
2375
2376         if (enabled) {
2377                 /* Enable VLAN filtering. */
2378                 tpid  = ETH_P_8021Q;
2379                 tpid2 = ETH_P_8021AD;
2380         } else {
2381                 /* Disable VLAN filtering. */
2382                 tpid  = ETH_P_SJA1105;
2383                 tpid2 = ETH_P_SJA1105;
2384         }
2385
2386         table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
2387         general_params = table->entries;
2388         /* EtherType used to identify inner tagged (C-tag) VLAN traffic */
2389         general_params->tpid = tpid;
2390         /* EtherType used to identify outer tagged (S-tag) VLAN traffic */
2391         general_params->tpid2 = tpid2;
2392         /* When VLAN filtering is on, we need to at least be able to
2393          * decode management traffic through the "backup plan".
2394          */
2395         general_params->incl_srcpt1 = enabled;
2396         general_params->incl_srcpt0 = enabled;
2397
2398         /* VLAN filtering => independent VLAN learning.
2399          * No VLAN filtering (or best effort) => shared VLAN learning.
2400          *
2401          * In shared VLAN learning mode, untagged traffic still gets
2402          * pvid-tagged, and the FDB table gets populated with entries
2403          * containing the "real" (pvid or from VLAN tag) VLAN ID.
2404          * However the switch performs a masked L2 lookup in the FDB,
2405          * effectively only looking up a frame's DMAC (and not VID) for the
2406          * forwarding decision.
2407          *
2408          * This is extremely convenient for us, because in modes with
2409          * vlan_filtering=0, dsa_8021q actually installs unique pvid's into
2410          * each front panel port. This is good for identification but breaks
2411          * learning badly - the VID of the learnt FDB entry is unique, aka
2412          * no frames coming from any other port are going to have it. So
2413          * for forwarding purposes, this is as though learning was broken
2414          * (all frames get flooded).
2415          */
2416         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS];
2417         l2_lookup_params = table->entries;
2418         l2_lookup_params->shared_learn = !enabled;
2419
2420         for (port = 0; port < ds->num_ports; port++) {
2421                 if (dsa_is_unused_port(ds, port))
2422                         continue;
2423
2424                 rc = sja1105_commit_pvid(ds, port);
2425                 if (rc)
2426                         return rc;
2427         }
2428
2429         rc = sja1105_static_config_reload(priv, SJA1105_VLAN_FILTERING);
2430         if (rc)
2431                 NL_SET_ERR_MSG_MOD(extack, "Failed to change VLAN Ethertype");
2432
2433         return rc;
2434 }
2435
2436 static int sja1105_vlan_add(struct sja1105_private *priv, int port, u16 vid,
2437                             u16 flags, bool allowed_ingress)
2438 {
2439         struct sja1105_vlan_lookup_entry *vlan;
2440         struct sja1105_table *table;
2441         int match, rc;
2442
2443         table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
2444
2445         match = sja1105_is_vlan_configured(priv, vid);
2446         if (match < 0) {
2447                 rc = sja1105_table_resize(table, table->entry_count + 1);
2448                 if (rc)
2449                         return rc;
2450                 match = table->entry_count - 1;
2451         }
2452
2453         /* Assign pointer after the resize (it's new memory) */
2454         vlan = table->entries;
2455
2456         vlan[match].type_entry = SJA1110_VLAN_D_TAG;
2457         vlan[match].vlanid = vid;
2458         vlan[match].vlan_bc |= BIT(port);
2459
2460         if (allowed_ingress)
2461                 vlan[match].vmemb_port |= BIT(port);
2462         else
2463                 vlan[match].vmemb_port &= ~BIT(port);
2464
2465         if (flags & BRIDGE_VLAN_INFO_UNTAGGED)
2466                 vlan[match].tag_port &= ~BIT(port);
2467         else
2468                 vlan[match].tag_port |= BIT(port);
2469
2470         return sja1105_dynamic_config_write(priv, BLK_IDX_VLAN_LOOKUP, vid,
2471                                             &vlan[match], true);
2472 }
2473
2474 static int sja1105_vlan_del(struct sja1105_private *priv, int port, u16 vid)
2475 {
2476         struct sja1105_vlan_lookup_entry *vlan;
2477         struct sja1105_table *table;
2478         bool keep = true;
2479         int match, rc;
2480
2481         table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
2482
2483         match = sja1105_is_vlan_configured(priv, vid);
2484         /* Can't delete a missing entry. */
2485         if (match < 0)
2486                 return 0;
2487
2488         /* Assign pointer after the resize (it's new memory) */
2489         vlan = table->entries;
2490
2491         vlan[match].vlanid = vid;
2492         vlan[match].vlan_bc &= ~BIT(port);
2493         vlan[match].vmemb_port &= ~BIT(port);
2494         /* Also unset tag_port, just so we don't have a confusing bitmap
2495          * (no practical purpose).
2496          */
2497         vlan[match].tag_port &= ~BIT(port);
2498
2499         /* If there's no port left as member of this VLAN,
2500          * it's time for it to go.
2501          */
2502         if (!vlan[match].vmemb_port)
2503                 keep = false;
2504
2505         rc = sja1105_dynamic_config_write(priv, BLK_IDX_VLAN_LOOKUP, vid,
2506                                           &vlan[match], keep);
2507         if (rc < 0)
2508                 return rc;
2509
2510         if (!keep)
2511                 return sja1105_table_delete_entry(table, match);
2512
2513         return 0;
2514 }
2515
2516 static int sja1105_bridge_vlan_add(struct dsa_switch *ds, int port,
2517                                    const struct switchdev_obj_port_vlan *vlan,
2518                                    struct netlink_ext_ack *extack)
2519 {
2520         struct sja1105_private *priv = ds->priv;
2521         u16 flags = vlan->flags;
2522         int rc;
2523
2524         /* Be sure to deny alterations to the configuration done by tag_8021q.
2525          */
2526         if (vid_is_dsa_8021q(vlan->vid)) {
2527                 NL_SET_ERR_MSG_MOD(extack,
2528                                    "Range 1024-3071 reserved for dsa_8021q operation");
2529                 return -EBUSY;
2530         }
2531
2532         /* Always install bridge VLANs as egress-tagged on CPU and DSA ports */
2533         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2534                 flags = 0;
2535
2536         rc = sja1105_vlan_add(priv, port, vlan->vid, flags, true);
2537         if (rc)
2538                 return rc;
2539
2540         if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
2541                 priv->bridge_pvid[port] = vlan->vid;
2542
2543         return sja1105_commit_pvid(ds, port);
2544 }
2545
2546 static int sja1105_bridge_vlan_del(struct dsa_switch *ds, int port,
2547                                    const struct switchdev_obj_port_vlan *vlan)
2548 {
2549         struct sja1105_private *priv = ds->priv;
2550         int rc;
2551
2552         rc = sja1105_vlan_del(priv, port, vlan->vid);
2553         if (rc)
2554                 return rc;
2555
2556         /* In case the pvid was deleted, make sure that untagged packets will
2557          * be dropped.
2558          */
2559         return sja1105_commit_pvid(ds, port);
2560 }
2561
2562 static int sja1105_dsa_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid,
2563                                       u16 flags)
2564 {
2565         struct sja1105_private *priv = ds->priv;
2566         bool allowed_ingress = true;
2567         int rc;
2568
2569         /* Prevent attackers from trying to inject a DSA tag from
2570          * the outside world.
2571          */
2572         if (dsa_is_user_port(ds, port))
2573                 allowed_ingress = false;
2574
2575         rc = sja1105_vlan_add(priv, port, vid, flags, allowed_ingress);
2576         if (rc)
2577                 return rc;
2578
2579         if (flags & BRIDGE_VLAN_INFO_PVID)
2580                 priv->tag_8021q_pvid[port] = vid;
2581
2582         return sja1105_commit_pvid(ds, port);
2583 }
2584
2585 static int sja1105_dsa_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid)
2586 {
2587         struct sja1105_private *priv = ds->priv;
2588
2589         return sja1105_vlan_del(priv, port, vid);
2590 }
2591
2592 static int sja1105_prechangeupper(struct dsa_switch *ds, int port,
2593                                   struct netdev_notifier_changeupper_info *info)
2594 {
2595         struct netlink_ext_ack *extack = info->info.extack;
2596         struct net_device *upper = info->upper_dev;
2597         struct dsa_switch_tree *dst = ds->dst;
2598         struct dsa_port *dp;
2599
2600         if (is_vlan_dev(upper)) {
2601                 NL_SET_ERR_MSG_MOD(extack, "8021q uppers are not supported");
2602                 return -EBUSY;
2603         }
2604
2605         if (netif_is_bridge_master(upper)) {
2606                 list_for_each_entry(dp, &dst->ports, list) {
2607                         struct net_device *br = dsa_port_bridge_dev_get(dp);
2608
2609                         if (br && br != upper && br_vlan_enabled(br)) {
2610                                 NL_SET_ERR_MSG_MOD(extack,
2611                                                    "Only one VLAN-aware bridge is supported");
2612                                 return -EBUSY;
2613                         }
2614                 }
2615         }
2616
2617         return 0;
2618 }
2619
2620 static int sja1105_mgmt_xmit(struct dsa_switch *ds, int port, int slot,
2621                              struct sk_buff *skb, bool takets)
2622 {
2623         struct sja1105_mgmt_entry mgmt_route = {0};
2624         struct sja1105_private *priv = ds->priv;
2625         struct ethhdr *hdr;
2626         int timeout = 10;
2627         int rc;
2628
2629         hdr = eth_hdr(skb);
2630
2631         mgmt_route.macaddr = ether_addr_to_u64(hdr->h_dest);
2632         mgmt_route.destports = BIT(port);
2633         mgmt_route.enfport = 1;
2634         mgmt_route.tsreg = 0;
2635         mgmt_route.takets = takets;
2636
2637         rc = sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE,
2638                                           slot, &mgmt_route, true);
2639         if (rc < 0) {
2640                 kfree_skb(skb);
2641                 return rc;
2642         }
2643
2644         /* Transfer skb to the host port. */
2645         dsa_enqueue_skb(skb, dsa_to_port(ds, port)->slave);
2646
2647         /* Wait until the switch has processed the frame */
2648         do {
2649                 rc = sja1105_dynamic_config_read(priv, BLK_IDX_MGMT_ROUTE,
2650                                                  slot, &mgmt_route);
2651                 if (rc < 0) {
2652                         dev_err_ratelimited(priv->ds->dev,
2653                                             "failed to poll for mgmt route\n");
2654                         continue;
2655                 }
2656
2657                 /* UM10944: The ENFPORT flag of the respective entry is
2658                  * cleared when a match is found. The host can use this
2659                  * flag as an acknowledgment.
2660                  */
2661                 cpu_relax();
2662         } while (mgmt_route.enfport && --timeout);
2663
2664         if (!timeout) {
2665                 /* Clean up the management route so that a follow-up
2666                  * frame may not match on it by mistake.
2667                  * This is only hardware supported on P/Q/R/S - on E/T it is
2668                  * a no-op and we are silently discarding the -EOPNOTSUPP.
2669                  */
2670                 sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE,
2671                                              slot, &mgmt_route, false);
2672                 dev_err_ratelimited(priv->ds->dev, "xmit timed out\n");
2673         }
2674
2675         return NETDEV_TX_OK;
2676 }
2677
2678 #define work_to_xmit_work(w) \
2679                 container_of((w), struct sja1105_deferred_xmit_work, work)
2680
2681 /* Deferred work is unfortunately necessary because setting up the management
2682  * route cannot be done from atomit context (SPI transfer takes a sleepable
2683  * lock on the bus)
2684  */
2685 static void sja1105_port_deferred_xmit(struct kthread_work *work)
2686 {
2687         struct sja1105_deferred_xmit_work *xmit_work = work_to_xmit_work(work);
2688         struct sk_buff *clone, *skb = xmit_work->skb;
2689         struct dsa_switch *ds = xmit_work->dp->ds;
2690         struct sja1105_private *priv = ds->priv;
2691         int port = xmit_work->dp->index;
2692
2693         clone = SJA1105_SKB_CB(skb)->clone;
2694
2695         mutex_lock(&priv->mgmt_lock);
2696
2697         sja1105_mgmt_xmit(ds, port, 0, skb, !!clone);
2698
2699         /* The clone, if there, was made by dsa_skb_tx_timestamp */
2700         if (clone)
2701                 sja1105_ptp_txtstamp_skb(ds, port, clone);
2702
2703         mutex_unlock(&priv->mgmt_lock);
2704
2705         kfree(xmit_work);
2706 }
2707
2708 static int sja1105_connect_tag_protocol(struct dsa_switch *ds,
2709                                         enum dsa_tag_protocol proto)
2710 {
2711         struct sja1105_private *priv = ds->priv;
2712         struct sja1105_tagger_data *tagger_data;
2713
2714         if (proto != priv->info->tag_proto)
2715                 return -EPROTONOSUPPORT;
2716
2717         tagger_data = sja1105_tagger_data(ds);
2718         tagger_data->xmit_work_fn = sja1105_port_deferred_xmit;
2719         tagger_data->meta_tstamp_handler = sja1110_process_meta_tstamp;
2720
2721         return 0;
2722 }
2723
2724 /* The MAXAGE setting belongs to the L2 Forwarding Parameters table,
2725  * which cannot be reconfigured at runtime. So a switch reset is required.
2726  */
2727 static int sja1105_set_ageing_time(struct dsa_switch *ds,
2728                                    unsigned int ageing_time)
2729 {
2730         struct sja1105_l2_lookup_params_entry *l2_lookup_params;
2731         struct sja1105_private *priv = ds->priv;
2732         struct sja1105_table *table;
2733         unsigned int maxage;
2734
2735         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS];
2736         l2_lookup_params = table->entries;
2737
2738         maxage = SJA1105_AGEING_TIME_MS(ageing_time);
2739
2740         if (l2_lookup_params->maxage == maxage)
2741                 return 0;
2742
2743         l2_lookup_params->maxage = maxage;
2744
2745         return sja1105_static_config_reload(priv, SJA1105_AGEING_TIME);
2746 }
2747
2748 static int sja1105_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
2749 {
2750         struct sja1105_l2_policing_entry *policing;
2751         struct sja1105_private *priv = ds->priv;
2752
2753         new_mtu += VLAN_ETH_HLEN + ETH_FCS_LEN;
2754
2755         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2756                 new_mtu += VLAN_HLEN;
2757
2758         policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2759
2760         if (policing[port].maxlen == new_mtu)
2761                 return 0;
2762
2763         policing[port].maxlen = new_mtu;
2764
2765         return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2766 }
2767
2768 static int sja1105_get_max_mtu(struct dsa_switch *ds, int port)
2769 {
2770         return 2043 - VLAN_ETH_HLEN - ETH_FCS_LEN;
2771 }
2772
2773 static int sja1105_port_setup_tc(struct dsa_switch *ds, int port,
2774                                  enum tc_setup_type type,
2775                                  void *type_data)
2776 {
2777         switch (type) {
2778         case TC_SETUP_QDISC_TAPRIO:
2779                 return sja1105_setup_tc_taprio(ds, port, type_data);
2780         case TC_SETUP_QDISC_CBS:
2781                 return sja1105_setup_tc_cbs(ds, port, type_data);
2782         default:
2783                 return -EOPNOTSUPP;
2784         }
2785 }
2786
2787 /* We have a single mirror (@to) port, but can configure ingress and egress
2788  * mirroring on all other (@from) ports.
2789  * We need to allow mirroring rules only as long as the @to port is always the
2790  * same, and we need to unset the @to port from mirr_port only when there is no
2791  * mirroring rule that references it.
2792  */
2793 static int sja1105_mirror_apply(struct sja1105_private *priv, int from, int to,
2794                                 bool ingress, bool enabled)
2795 {
2796         struct sja1105_general_params_entry *general_params;
2797         struct sja1105_mac_config_entry *mac;
2798         struct dsa_switch *ds = priv->ds;
2799         struct sja1105_table *table;
2800         bool already_enabled;
2801         u64 new_mirr_port;
2802         int rc;
2803
2804         table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
2805         general_params = table->entries;
2806
2807         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2808
2809         already_enabled = (general_params->mirr_port != ds->num_ports);
2810         if (already_enabled && enabled && general_params->mirr_port != to) {
2811                 dev_err(priv->ds->dev,
2812                         "Delete mirroring rules towards port %llu first\n",
2813                         general_params->mirr_port);
2814                 return -EBUSY;
2815         }
2816
2817         new_mirr_port = to;
2818         if (!enabled) {
2819                 bool keep = false;
2820                 int port;
2821
2822                 /* Anybody still referencing mirr_port? */
2823                 for (port = 0; port < ds->num_ports; port++) {
2824                         if (mac[port].ing_mirr || mac[port].egr_mirr) {
2825                                 keep = true;
2826                                 break;
2827                         }
2828                 }
2829                 /* Unset already_enabled for next time */
2830                 if (!keep)
2831                         new_mirr_port = ds->num_ports;
2832         }
2833         if (new_mirr_port != general_params->mirr_port) {
2834                 general_params->mirr_port = new_mirr_port;
2835
2836                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_GENERAL_PARAMS,
2837                                                   0, general_params, true);
2838                 if (rc < 0)
2839                         return rc;
2840         }
2841
2842         if (ingress)
2843                 mac[from].ing_mirr = enabled;
2844         else
2845                 mac[from].egr_mirr = enabled;
2846
2847         return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, from,
2848                                             &mac[from], true);
2849 }
2850
2851 static int sja1105_mirror_add(struct dsa_switch *ds, int port,
2852                               struct dsa_mall_mirror_tc_entry *mirror,
2853                               bool ingress)
2854 {
2855         return sja1105_mirror_apply(ds->priv, port, mirror->to_local_port,
2856                                     ingress, true);
2857 }
2858
2859 static void sja1105_mirror_del(struct dsa_switch *ds, int port,
2860                                struct dsa_mall_mirror_tc_entry *mirror)
2861 {
2862         sja1105_mirror_apply(ds->priv, port, mirror->to_local_port,
2863                              mirror->ingress, false);
2864 }
2865
2866 static int sja1105_port_policer_add(struct dsa_switch *ds, int port,
2867                                     struct dsa_mall_policer_tc_entry *policer)
2868 {
2869         struct sja1105_l2_policing_entry *policing;
2870         struct sja1105_private *priv = ds->priv;
2871
2872         policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2873
2874         /* In hardware, every 8 microseconds the credit level is incremented by
2875          * the value of RATE bytes divided by 64, up to a maximum of SMAX
2876          * bytes.
2877          */
2878         policing[port].rate = div_u64(512 * policer->rate_bytes_per_sec,
2879                                       1000000);
2880         policing[port].smax = policer->burst;
2881
2882         return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2883 }
2884
2885 static void sja1105_port_policer_del(struct dsa_switch *ds, int port)
2886 {
2887         struct sja1105_l2_policing_entry *policing;
2888         struct sja1105_private *priv = ds->priv;
2889
2890         policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2891
2892         policing[port].rate = SJA1105_RATE_MBPS(1000);
2893         policing[port].smax = 65535;
2894
2895         sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2896 }
2897
2898 static int sja1105_port_set_learning(struct sja1105_private *priv, int port,
2899                                      bool enabled)
2900 {
2901         struct sja1105_mac_config_entry *mac;
2902
2903         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2904
2905         mac[port].dyn_learn = enabled;
2906
2907         return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
2908                                             &mac[port], true);
2909 }
2910
2911 static int sja1105_port_ucast_bcast_flood(struct sja1105_private *priv, int to,
2912                                           struct switchdev_brport_flags flags)
2913 {
2914         if (flags.mask & BR_FLOOD) {
2915                 if (flags.val & BR_FLOOD)
2916                         priv->ucast_egress_floods |= BIT(to);
2917                 else
2918                         priv->ucast_egress_floods &= ~BIT(to);
2919         }
2920
2921         if (flags.mask & BR_BCAST_FLOOD) {
2922                 if (flags.val & BR_BCAST_FLOOD)
2923                         priv->bcast_egress_floods |= BIT(to);
2924                 else
2925                         priv->bcast_egress_floods &= ~BIT(to);
2926         }
2927
2928         return sja1105_manage_flood_domains(priv);
2929 }
2930
2931 static int sja1105_port_mcast_flood(struct sja1105_private *priv, int to,
2932                                     struct switchdev_brport_flags flags,
2933                                     struct netlink_ext_ack *extack)
2934 {
2935         struct sja1105_l2_lookup_entry *l2_lookup;
2936         struct sja1105_table *table;
2937         int match;
2938
2939         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
2940         l2_lookup = table->entries;
2941
2942         for (match = 0; match < table->entry_count; match++)
2943                 if (l2_lookup[match].macaddr == SJA1105_UNKNOWN_MULTICAST &&
2944                     l2_lookup[match].mask_macaddr == SJA1105_UNKNOWN_MULTICAST)
2945                         break;
2946
2947         if (match == table->entry_count) {
2948                 NL_SET_ERR_MSG_MOD(extack,
2949                                    "Could not find FDB entry for unknown multicast");
2950                 return -ENOSPC;
2951         }
2952
2953         if (flags.val & BR_MCAST_FLOOD)
2954                 l2_lookup[match].destports |= BIT(to);
2955         else
2956                 l2_lookup[match].destports &= ~BIT(to);
2957
2958         return sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
2959                                             l2_lookup[match].index,
2960                                             &l2_lookup[match],
2961                                             true);
2962 }
2963
2964 static int sja1105_port_pre_bridge_flags(struct dsa_switch *ds, int port,
2965                                          struct switchdev_brport_flags flags,
2966                                          struct netlink_ext_ack *extack)
2967 {
2968         struct sja1105_private *priv = ds->priv;
2969
2970         if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
2971                            BR_BCAST_FLOOD))
2972                 return -EINVAL;
2973
2974         if (flags.mask & (BR_FLOOD | BR_MCAST_FLOOD) &&
2975             !priv->info->can_limit_mcast_flood) {
2976                 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
2977                 bool unicast = !!(flags.val & BR_FLOOD);
2978
2979                 if (unicast != multicast) {
2980                         NL_SET_ERR_MSG_MOD(extack,
2981                                            "This chip cannot configure multicast flooding independently of unicast");
2982                         return -EINVAL;
2983                 }
2984         }
2985
2986         return 0;
2987 }
2988
2989 static int sja1105_port_bridge_flags(struct dsa_switch *ds, int port,
2990                                      struct switchdev_brport_flags flags,
2991                                      struct netlink_ext_ack *extack)
2992 {
2993         struct sja1105_private *priv = ds->priv;
2994         int rc;
2995
2996         if (flags.mask & BR_LEARNING) {
2997                 bool learn_ena = !!(flags.val & BR_LEARNING);
2998
2999                 rc = sja1105_port_set_learning(priv, port, learn_ena);
3000                 if (rc)
3001                         return rc;
3002         }
3003
3004         if (flags.mask & (BR_FLOOD | BR_BCAST_FLOOD)) {
3005                 rc = sja1105_port_ucast_bcast_flood(priv, port, flags);
3006                 if (rc)
3007                         return rc;
3008         }
3009
3010         /* For chips that can't offload BR_MCAST_FLOOD independently, there
3011          * is nothing to do here, we ensured the configuration is in sync by
3012          * offloading BR_FLOOD.
3013          */
3014         if (flags.mask & BR_MCAST_FLOOD && priv->info->can_limit_mcast_flood) {
3015                 rc = sja1105_port_mcast_flood(priv, port, flags,
3016                                               extack);
3017                 if (rc)
3018                         return rc;
3019         }
3020
3021         return 0;
3022 }
3023
3024 /* The programming model for the SJA1105 switch is "all-at-once" via static
3025  * configuration tables. Some of these can be dynamically modified at runtime,
3026  * but not the xMII mode parameters table.
3027  * Furthermode, some PHYs may not have crystals for generating their clocks
3028  * (e.g. RMII). Instead, their 50MHz clock is supplied via the SJA1105 port's
3029  * ref_clk pin. So port clocking needs to be initialized early, before
3030  * connecting to PHYs is attempted, otherwise they won't respond through MDIO.
3031  * Setting correct PHY link speed does not matter now.
3032  * But dsa_slave_phy_setup is called later than sja1105_setup, so the PHY
3033  * bindings are not yet parsed by DSA core. We need to parse early so that we
3034  * can populate the xMII mode parameters table.
3035  */
3036 static int sja1105_setup(struct dsa_switch *ds)
3037 {
3038         struct sja1105_private *priv = ds->priv;
3039         int rc;
3040
3041         if (priv->info->disable_microcontroller) {
3042                 rc = priv->info->disable_microcontroller(priv);
3043                 if (rc < 0) {
3044                         dev_err(ds->dev,
3045                                 "Failed to disable microcontroller: %pe\n",
3046                                 ERR_PTR(rc));
3047                         return rc;
3048                 }
3049         }
3050
3051         /* Create and send configuration down to device */
3052         rc = sja1105_static_config_load(priv);
3053         if (rc < 0) {
3054                 dev_err(ds->dev, "Failed to load static config: %d\n", rc);
3055                 return rc;
3056         }
3057
3058         /* Configure the CGU (PHY link modes and speeds) */
3059         if (priv->info->clocking_setup) {
3060                 rc = priv->info->clocking_setup(priv);
3061                 if (rc < 0) {
3062                         dev_err(ds->dev,
3063                                 "Failed to configure MII clocking: %pe\n",
3064                                 ERR_PTR(rc));
3065                         goto out_static_config_free;
3066                 }
3067         }
3068
3069         sja1105_tas_setup(ds);
3070         sja1105_flower_setup(ds);
3071
3072         rc = sja1105_ptp_clock_register(ds);
3073         if (rc < 0) {
3074                 dev_err(ds->dev, "Failed to register PTP clock: %d\n", rc);
3075                 goto out_flower_teardown;
3076         }
3077
3078         rc = sja1105_mdiobus_register(ds);
3079         if (rc < 0) {
3080                 dev_err(ds->dev, "Failed to register MDIO bus: %pe\n",
3081                         ERR_PTR(rc));
3082                 goto out_ptp_clock_unregister;
3083         }
3084
3085         rc = sja1105_devlink_setup(ds);
3086         if (rc < 0)
3087                 goto out_mdiobus_unregister;
3088
3089         rtnl_lock();
3090         rc = dsa_tag_8021q_register(ds, htons(ETH_P_8021Q));
3091         rtnl_unlock();
3092         if (rc)
3093                 goto out_devlink_teardown;
3094
3095         /* On SJA1105, VLAN filtering per se is always enabled in hardware.
3096          * The only thing we can do to disable it is lie about what the 802.1Q
3097          * EtherType is.
3098          * So it will still try to apply VLAN filtering, but all ingress
3099          * traffic (except frames received with EtherType of ETH_P_SJA1105)
3100          * will be internally tagged with a distorted VLAN header where the
3101          * TPID is ETH_P_SJA1105, and the VLAN ID is the port pvid.
3102          */
3103         ds->vlan_filtering_is_global = true;
3104         ds->untag_bridge_pvid = true;
3105         /* tag_8021q has 3 bits for the VBID, and the value 0 is reserved */
3106         ds->max_num_bridges = 7;
3107
3108         /* Advertise the 8 egress queues */
3109         ds->num_tx_queues = SJA1105_NUM_TC;
3110
3111         ds->mtu_enforcement_ingress = true;
3112         ds->assisted_learning_on_cpu_port = true;
3113
3114         return 0;
3115
3116 out_devlink_teardown:
3117         sja1105_devlink_teardown(ds);
3118 out_mdiobus_unregister:
3119         sja1105_mdiobus_unregister(ds);
3120 out_ptp_clock_unregister:
3121         sja1105_ptp_clock_unregister(ds);
3122 out_flower_teardown:
3123         sja1105_flower_teardown(ds);
3124         sja1105_tas_teardown(ds);
3125 out_static_config_free:
3126         sja1105_static_config_free(&priv->static_config);
3127
3128         return rc;
3129 }
3130
3131 static void sja1105_teardown(struct dsa_switch *ds)
3132 {
3133         struct sja1105_private *priv = ds->priv;
3134
3135         rtnl_lock();
3136         dsa_tag_8021q_unregister(ds);
3137         rtnl_unlock();
3138
3139         sja1105_devlink_teardown(ds);
3140         sja1105_mdiobus_unregister(ds);
3141         sja1105_ptp_clock_unregister(ds);
3142         sja1105_flower_teardown(ds);
3143         sja1105_tas_teardown(ds);
3144         sja1105_static_config_free(&priv->static_config);
3145 }
3146
3147 static const struct dsa_switch_ops sja1105_switch_ops = {
3148         .get_tag_protocol       = sja1105_get_tag_protocol,
3149         .connect_tag_protocol   = sja1105_connect_tag_protocol,
3150         .setup                  = sja1105_setup,
3151         .teardown               = sja1105_teardown,
3152         .set_ageing_time        = sja1105_set_ageing_time,
3153         .port_change_mtu        = sja1105_change_mtu,
3154         .port_max_mtu           = sja1105_get_max_mtu,
3155         .phylink_validate       = sja1105_phylink_validate,
3156         .phylink_mac_config     = sja1105_mac_config,
3157         .phylink_mac_link_up    = sja1105_mac_link_up,
3158         .phylink_mac_link_down  = sja1105_mac_link_down,
3159         .get_strings            = sja1105_get_strings,
3160         .get_ethtool_stats      = sja1105_get_ethtool_stats,
3161         .get_sset_count         = sja1105_get_sset_count,
3162         .get_ts_info            = sja1105_get_ts_info,
3163         .port_fdb_dump          = sja1105_fdb_dump,
3164         .port_fdb_add           = sja1105_fdb_add,
3165         .port_fdb_del           = sja1105_fdb_del,
3166         .port_fast_age          = sja1105_fast_age,
3167         .port_bridge_join       = sja1105_bridge_join,
3168         .port_bridge_leave      = sja1105_bridge_leave,
3169         .port_pre_bridge_flags  = sja1105_port_pre_bridge_flags,
3170         .port_bridge_flags      = sja1105_port_bridge_flags,
3171         .port_stp_state_set     = sja1105_bridge_stp_state_set,
3172         .port_vlan_filtering    = sja1105_vlan_filtering,
3173         .port_vlan_add          = sja1105_bridge_vlan_add,
3174         .port_vlan_del          = sja1105_bridge_vlan_del,
3175         .port_mdb_add           = sja1105_mdb_add,
3176         .port_mdb_del           = sja1105_mdb_del,
3177         .port_hwtstamp_get      = sja1105_hwtstamp_get,
3178         .port_hwtstamp_set      = sja1105_hwtstamp_set,
3179         .port_rxtstamp          = sja1105_port_rxtstamp,
3180         .port_txtstamp          = sja1105_port_txtstamp,
3181         .port_setup_tc          = sja1105_port_setup_tc,
3182         .port_mirror_add        = sja1105_mirror_add,
3183         .port_mirror_del        = sja1105_mirror_del,
3184         .port_policer_add       = sja1105_port_policer_add,
3185         .port_policer_del       = sja1105_port_policer_del,
3186         .cls_flower_add         = sja1105_cls_flower_add,
3187         .cls_flower_del         = sja1105_cls_flower_del,
3188         .cls_flower_stats       = sja1105_cls_flower_stats,
3189         .devlink_info_get       = sja1105_devlink_info_get,
3190         .tag_8021q_vlan_add     = sja1105_dsa_8021q_vlan_add,
3191         .tag_8021q_vlan_del     = sja1105_dsa_8021q_vlan_del,
3192         .port_prechangeupper    = sja1105_prechangeupper,
3193 };
3194
3195 static const struct of_device_id sja1105_dt_ids[];
3196
3197 static int sja1105_check_device_id(struct sja1105_private *priv)
3198 {
3199         const struct sja1105_regs *regs = priv->info->regs;
3200         u8 prod_id[SJA1105_SIZE_DEVICE_ID] = {0};
3201         struct device *dev = &priv->spidev->dev;
3202         const struct of_device_id *match;
3203         u32 device_id;
3204         u64 part_no;
3205         int rc;
3206
3207         rc = sja1105_xfer_u32(priv, SPI_READ, regs->device_id, &device_id,
3208                               NULL);
3209         if (rc < 0)
3210                 return rc;
3211
3212         rc = sja1105_xfer_buf(priv, SPI_READ, regs->prod_id, prod_id,
3213                               SJA1105_SIZE_DEVICE_ID);
3214         if (rc < 0)
3215                 return rc;
3216
3217         sja1105_unpack(prod_id, &part_no, 19, 4, SJA1105_SIZE_DEVICE_ID);
3218
3219         for (match = sja1105_dt_ids; match->compatible[0]; match++) {
3220                 const struct sja1105_info *info = match->data;
3221
3222                 /* Is what's been probed in our match table at all? */
3223                 if (info->device_id != device_id || info->part_no != part_no)
3224                         continue;
3225
3226                 /* But is it what's in the device tree? */
3227                 if (priv->info->device_id != device_id ||
3228                     priv->info->part_no != part_no) {
3229                         dev_warn(dev, "Device tree specifies chip %s but found %s, please fix it!\n",
3230                                  priv->info->name, info->name);
3231                         /* It isn't. No problem, pick that up. */
3232                         priv->info = info;
3233                 }
3234
3235                 return 0;
3236         }
3237
3238         dev_err(dev, "Unexpected {device ID, part number}: 0x%x 0x%llx\n",
3239                 device_id, part_no);
3240
3241         return -ENODEV;
3242 }
3243
3244 static int sja1105_probe(struct spi_device *spi)
3245 {
3246         struct device *dev = &spi->dev;
3247         struct sja1105_private *priv;
3248         size_t max_xfer, max_msg;
3249         struct dsa_switch *ds;
3250         int rc;
3251
3252         if (!dev->of_node) {
3253                 dev_err(dev, "No DTS bindings for SJA1105 driver\n");
3254                 return -EINVAL;
3255         }
3256
3257         rc = sja1105_hw_reset(dev, 1, 1);
3258         if (rc)
3259                 return rc;
3260
3261         priv = devm_kzalloc(dev, sizeof(struct sja1105_private), GFP_KERNEL);
3262         if (!priv)
3263                 return -ENOMEM;
3264
3265         /* Populate our driver private structure (priv) based on
3266          * the device tree node that was probed (spi)
3267          */
3268         priv->spidev = spi;
3269         spi_set_drvdata(spi, priv);
3270
3271         /* Configure the SPI bus */
3272         spi->bits_per_word = 8;
3273         rc = spi_setup(spi);
3274         if (rc < 0) {
3275                 dev_err(dev, "Could not init SPI\n");
3276                 return rc;
3277         }
3278
3279         /* In sja1105_xfer, we send spi_messages composed of two spi_transfers:
3280          * a small one for the message header and another one for the current
3281          * chunk of the packed buffer.
3282          * Check that the restrictions imposed by the SPI controller are
3283          * respected: the chunk buffer is smaller than the max transfer size,
3284          * and the total length of the chunk plus its message header is smaller
3285          * than the max message size.
3286          * We do that during probe time since the maximum transfer size is a
3287          * runtime invariant.
3288          */
3289         max_xfer = spi_max_transfer_size(spi);
3290         max_msg = spi_max_message_size(spi);
3291
3292         /* We need to send at least one 64-bit word of SPI payload per message
3293          * in order to be able to make useful progress.
3294          */
3295         if (max_msg < SJA1105_SIZE_SPI_MSG_HEADER + 8) {
3296                 dev_err(dev, "SPI master cannot send large enough buffers, aborting\n");
3297                 return -EINVAL;
3298         }
3299
3300         priv->max_xfer_len = SJA1105_SIZE_SPI_MSG_MAXLEN;
3301         if (priv->max_xfer_len > max_xfer)
3302                 priv->max_xfer_len = max_xfer;
3303         if (priv->max_xfer_len > max_msg - SJA1105_SIZE_SPI_MSG_HEADER)
3304                 priv->max_xfer_len = max_msg - SJA1105_SIZE_SPI_MSG_HEADER;
3305
3306         priv->info = of_device_get_match_data(dev);
3307
3308         /* Detect hardware device */
3309         rc = sja1105_check_device_id(priv);
3310         if (rc < 0) {
3311                 dev_err(dev, "Device ID check failed: %d\n", rc);
3312                 return rc;
3313         }
3314
3315         dev_info(dev, "Probed switch chip: %s\n", priv->info->name);
3316
3317         ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3318         if (!ds)
3319                 return -ENOMEM;
3320
3321         ds->dev = dev;
3322         ds->num_ports = priv->info->num_ports;
3323         ds->ops = &sja1105_switch_ops;
3324         ds->priv = priv;
3325         priv->ds = ds;
3326
3327         mutex_init(&priv->ptp_data.lock);
3328         mutex_init(&priv->dynamic_config_lock);
3329         mutex_init(&priv->mgmt_lock);
3330         spin_lock_init(&priv->ts_id_lock);
3331
3332         rc = sja1105_parse_dt(priv);
3333         if (rc < 0) {
3334                 dev_err(ds->dev, "Failed to parse DT: %d\n", rc);
3335                 return rc;
3336         }
3337
3338         if (IS_ENABLED(CONFIG_NET_SCH_CBS)) {
3339                 priv->cbs = devm_kcalloc(dev, priv->info->num_cbs_shapers,
3340                                          sizeof(struct sja1105_cbs_entry),
3341                                          GFP_KERNEL);
3342                 if (!priv->cbs)
3343                         return -ENOMEM;
3344         }
3345
3346         return dsa_register_switch(priv->ds);
3347 }
3348
3349 static int sja1105_remove(struct spi_device *spi)
3350 {
3351         struct sja1105_private *priv = spi_get_drvdata(spi);
3352
3353         if (!priv)
3354                 return 0;
3355
3356         dsa_unregister_switch(priv->ds);
3357
3358         spi_set_drvdata(spi, NULL);
3359
3360         return 0;
3361 }
3362
3363 static void sja1105_shutdown(struct spi_device *spi)
3364 {
3365         struct sja1105_private *priv = spi_get_drvdata(spi);
3366
3367         if (!priv)
3368                 return;
3369
3370         dsa_switch_shutdown(priv->ds);
3371
3372         spi_set_drvdata(spi, NULL);
3373 }
3374
3375 static const struct of_device_id sja1105_dt_ids[] = {
3376         { .compatible = "nxp,sja1105e", .data = &sja1105e_info },
3377         { .compatible = "nxp,sja1105t", .data = &sja1105t_info },
3378         { .compatible = "nxp,sja1105p", .data = &sja1105p_info },
3379         { .compatible = "nxp,sja1105q", .data = &sja1105q_info },
3380         { .compatible = "nxp,sja1105r", .data = &sja1105r_info },
3381         { .compatible = "nxp,sja1105s", .data = &sja1105s_info },
3382         { .compatible = "nxp,sja1110a", .data = &sja1110a_info },
3383         { .compatible = "nxp,sja1110b", .data = &sja1110b_info },
3384         { .compatible = "nxp,sja1110c", .data = &sja1110c_info },
3385         { .compatible = "nxp,sja1110d", .data = &sja1110d_info },
3386         { /* sentinel */ },
3387 };
3388 MODULE_DEVICE_TABLE(of, sja1105_dt_ids);
3389
3390 static struct spi_driver sja1105_driver = {
3391         .driver = {
3392                 .name  = "sja1105",
3393                 .owner = THIS_MODULE,
3394                 .of_match_table = of_match_ptr(sja1105_dt_ids),
3395         },
3396         .probe  = sja1105_probe,
3397         .remove = sja1105_remove,
3398         .shutdown = sja1105_shutdown,
3399 };
3400
3401 module_spi_driver(sja1105_driver);
3402
3403 MODULE_AUTHOR("Vladimir Oltean <olteanv@gmail.com>");
3404 MODULE_AUTHOR("Georg Waibel <georg.waibel@sensor-technik.de>");
3405 MODULE_DESCRIPTION("SJA1105 Driver");
3406 MODULE_LICENSE("GPL v2");