drivers/net/e1000e/82571.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82571EB Gigabit Ethernet Controller
  31  * 82571EB Gigabit Ethernet Controller (Copper)
  32  * 82571EB Gigabit Ethernet Controller (Fiber)
  33  * 82571EB Dual Port Gigabit Mezzanine Adapter
  34  * 82571EB Quad Port Gigabit Mezzanine Adapter
  35  * 82571PT Gigabit PT Quad Port Server ExpressModule
  36  * 82572EI Gigabit Ethernet Controller (Copper)
  37  * 82572EI Gigabit Ethernet Controller (Fiber)
  38  * 82572EI Gigabit Ethernet Controller
  39  * 82573V Gigabit Ethernet Controller (Copper)
  40  * 82573E Gigabit Ethernet Controller (Copper)
  41  * 82573L Gigabit Ethernet Controller
  42  * 82574L Gigabit Network Connection
  43  * 82583V Gigabit Network Connection
  44  */
  45
  46 #include <linux/netdevice.h>
  47 #include <linux/delay.h>
  48 #include <linux/pci.h>
  49
  50 #include "e1000.h"
  51
  52 #define ID_LED_RESERVED_F746 0xF746
  53 #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
  54                               (ID_LED_OFF1_ON2  <<  8) | \
  55                               (ID_LED_DEF1_DEF2 <<  4) | \
  56                               (ID_LED_DEF1_DEF2))
  57
  58 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
  59
  60 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
  61
  62 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
  63 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
  64 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
  65 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
  66 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
  67                                       u16 words, u16 *data);
  68 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
  69 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
  70 static s32 e1000_setup_link_82571(struct e1000_hw *hw);
  71 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
  72 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
  73 static s32 e1000_led_on_82574(struct e1000_hw *hw);
  74
  75 /**
  76  *  e1000_init_phy_params_82571 - Init PHY func ptrs.
  77  *  @hw: pointer to the HW structure
  78  *
  79  *  This is a function pointer entry point called by the api module.
  80  **/
  81 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
  82 {
  83         struct e1000_phy_info *phy = &hw->phy;
  84         s32 ret_val;
  85
  86         if (hw->phy.media_type != e1000_media_type_copper) {
  87                 phy->type = e1000_phy_none;
  88                 return 0;
  89         }
  90
  91         phy->addr                        = 1;
  92         phy->autoneg_mask                = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  93         phy->reset_delay_us              = 100;
  94
  95         switch (hw->mac.type) {
  96         case e1000_82571:
  97         case e1000_82572:
  98                 phy->type                = e1000_phy_igp_2;
  99                 break;
 100         case e1000_82573:
 101                 phy->type                = e1000_phy_m88;
 102                 break;
 103         case e1000_82574:
 104         case e1000_82583:
 105                 phy->type                = e1000_phy_bm;
 106                 break;
 107         default:
 108                 return -E1000_ERR_PHY;
 109                 break;
 110         }
 111
 112         /* This can only be done after all function pointers are setup. */
 113         ret_val = e1000_get_phy_id_82571(hw);
 114
 115         /* Verify phy id */
 116         switch (hw->mac.type) {
 117         case e1000_82571:
 118         case e1000_82572:
 119                 if (phy->id != IGP01E1000_I_PHY_ID)
 120                         return -E1000_ERR_PHY;
 121                 break;
 122         case e1000_82573:
 123                 if (phy->id != M88E1111_I_PHY_ID)
 124                         return -E1000_ERR_PHY;
 125                 break;
 126         case e1000_82574:
 127         case e1000_82583:
 128                 if (phy->id != BME1000_E_PHY_ID_R2)
 129                         return -E1000_ERR_PHY;
 130                 break;
 131         default:
 132                 return -E1000_ERR_PHY;
 133                 break;
 134         }
 135
 136         return 0;
 137 }
 138
 139 /**
 140  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
 141  *  @hw: pointer to the HW structure
 142  *
 143  *  This is a function pointer entry point called by the api module.
 144  **/
 145 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
 146 {
 147         struct e1000_nvm_info *nvm = &hw->nvm;
 148         u32 eecd = er32(EECD);
 149         u16 size;
 150
 151         nvm->opcode_bits = 8;
 152         nvm->delay_usec = 1;
 153         switch (nvm->override) {
 154         case e1000_nvm_override_spi_large:
 155                 nvm->page_size = 32;
 156                 nvm->address_bits = 16;
 157                 break;
 158         case e1000_nvm_override_spi_small:
 159                 nvm->page_size = 8;
 160                 nvm->address_bits = 8;
 161                 break;
 162         default:
 163                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 164                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 165                 break;
 166         }
 167
 168         switch (hw->mac.type) {
 169         case e1000_82573:
 170         case e1000_82574:
 171         case e1000_82583:
 172                 if (((eecd >> 15) & 0x3) == 0x3) {
 173                         nvm->type = e1000_nvm_flash_hw;
 174                         nvm->word_size = 2048;
 175                         /*
 176                          * Autonomous Flash update bit must be cleared due
 177                          * to Flash update issue.
 178                          */
 179                         eecd &= ~E1000_EECD_AUPDEN;
 180                         ew32(EECD, eecd);
 181                         break;
 182                 }
 183                 /* Fall Through */
 184         default:
 185                 nvm->type = e1000_nvm_eeprom_spi;
 186                 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 187                                   E1000_EECD_SIZE_EX_SHIFT);
 188                 /*
 189                  * Added to a constant, "size" becomes the left-shift value
 190                  * for setting word_size.
 191                  */
 192                 size += NVM_WORD_SIZE_BASE_SHIFT;
 193
 194                 /* EEPROM access above 16k is unsupported */
 195                 if (size > 14)
 196                         size = 14;
 197                 nvm->word_size  = 1 << size;
 198                 break;
 199         }
 200
 201         return 0;
 202 }
 203
 204 /**
 205  *  e1000_init_mac_params_82571 - Init MAC func ptrs.
 206  *  @hw: pointer to the HW structure
 207  *
 208  *  This is a function pointer entry point called by the api module.
 209  **/
 210 static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter)
 211 {
 212         struct e1000_hw *hw = &adapter->hw;
 213         struct e1000_mac_info *mac = &hw->mac;
 214         struct e1000_mac_operations *func = &mac->ops;
 215
 216         /* Set media type */
 217         switch (adapter->pdev->device) {
 218         case E1000_DEV_ID_82571EB_FIBER:
 219         case E1000_DEV_ID_82572EI_FIBER:
 220         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 221                 hw->phy.media_type = e1000_media_type_fiber;
 222                 break;
 223         case E1000_DEV_ID_82571EB_SERDES:
 224         case E1000_DEV_ID_82572EI_SERDES:
 225         case E1000_DEV_ID_82571EB_SERDES_DUAL:
 226         case E1000_DEV_ID_82571EB_SERDES_QUAD:
 227                 hw->phy.media_type = e1000_media_type_internal_serdes;
 228                 break;
 229         default:
 230                 hw->phy.media_type = e1000_media_type_copper;
 231                 break;
 232         }
 233
 234         /* Set mta register count */
 235         mac->mta_reg_count = 128;
 236         /* Set rar entry count */
 237         mac->rar_entry_count = E1000_RAR_ENTRIES;
 238         /* Set if manageability features are enabled. */
 239         mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0;
 240
 241         /* check for link */
 242         switch (hw->phy.media_type) {
 243         case e1000_media_type_copper:
 244                 func->setup_physical_interface = e1000_setup_copper_link_82571;
 245                 func->check_for_link = e1000e_check_for_copper_link;
 246                 func->get_link_up_info = e1000e_get_speed_and_duplex_copper;
 247                 break;
 248         case e1000_media_type_fiber:
 249                 func->setup_physical_interface =
 250                         e1000_setup_fiber_serdes_link_82571;
 251                 func->check_for_link = e1000e_check_for_fiber_link;
 252                 func->get_link_up_info =
 253                         e1000e_get_speed_and_duplex_fiber_serdes;
 254                 break;
 255         case e1000_media_type_internal_serdes:
 256                 func->setup_physical_interface =
 257                         e1000_setup_fiber_serdes_link_82571;
 258                 func->check_for_link = e1000_check_for_serdes_link_82571;
 259                 func->get_link_up_info =
 260                         e1000e_get_speed_and_duplex_fiber_serdes;
 261                 break;
 262         default:
 263                 return -E1000_ERR_CONFIG;
 264                 break;
 265         }
 266
 267         switch (hw->mac.type) {
 268         case e1000_82574:
 269         case e1000_82583:
 270                 func->check_mng_mode = e1000_check_mng_mode_82574;
 271                 func->led_on = e1000_led_on_82574;
 272                 break;
 273         default:
 274                 func->check_mng_mode = e1000e_check_mng_mode_generic;
 275                 func->led_on = e1000e_led_on_generic;
 276                 break;
 277         }
 278
 279         return 0;
 280 }
 281
 282 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
 283 {
 284         struct e1000_hw *hw = &adapter->hw;
 285         static int global_quad_port_a; /* global port a indication */
 286         struct pci_dev *pdev = adapter->pdev;
 287         u16 eeprom_data = 0;
 288         int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
 289         s32 rc;
 290
 291         rc = e1000_init_mac_params_82571(adapter);
 292         if (rc)
 293                 return rc;
 294
 295         rc = e1000_init_nvm_params_82571(hw);
 296         if (rc)
 297                 return rc;
 298
 299         rc = e1000_init_phy_params_82571(hw);
 300         if (rc)
 301                 return rc;
 302
 303         /* tag quad port adapters first, it's used below */
 304         switch (pdev->device) {
 305         case E1000_DEV_ID_82571EB_QUAD_COPPER:
 306         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 307         case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
 308         case E1000_DEV_ID_82571PT_QUAD_COPPER:
 309                 adapter->flags |= FLAG_IS_QUAD_PORT;
 310                 /* mark the first port */
 311                 if (global_quad_port_a == 0)
 312                         adapter->flags |= FLAG_IS_QUAD_PORT_A;
 313                 /* Reset for multiple quad port adapters */
 314                 global_quad_port_a++;
 315                 if (global_quad_port_a == 4)
 316                         global_quad_port_a = 0;
 317                 break;
 318         default:
 319                 break;
 320         }
 321
 322         switch (adapter->hw.mac.type) {
 323         case e1000_82571:
 324                 /* these dual ports don't have WoL on port B at all */
 325                 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
 326                      (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
 327                      (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
 328                     (is_port_b))
 329                         adapter->flags &= ~FLAG_HAS_WOL;
 330                 /* quad ports only support WoL on port A */
 331                 if (adapter->flags & FLAG_IS_QUAD_PORT &&
 332                     (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
 333                         adapter->flags &= ~FLAG_HAS_WOL;
 334                 /* Does not support WoL on any port */
 335                 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
 336                         adapter->flags &= ~FLAG_HAS_WOL;
 337                 break;
 338
 339         case e1000_82573:
 340                 if (pdev->device == E1000_DEV_ID_82573L) {
 341                         if (e1000_read_nvm(&adapter->hw, NVM_INIT_3GIO_3, 1,
 342                                        &eeprom_data) < 0)
 343                                 break;
 344                         if (eeprom_data & NVM_WORD1A_ASPM_MASK)
 345                                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 346                 }
 347                 break;
 348         default:
 349                 break;
 350         }
 351
 352         return 0;
 353 }
 354
 355 /**
 356  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
 357  *  @hw: pointer to the HW structure
 358  *
 359  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
 360  *  revision in the hardware structure.
 361  **/
 362 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
 363 {
 364         struct e1000_phy_info *phy = &hw->phy;
 365         s32 ret_val;
 366         u16 phy_id = 0;
 367
 368         switch (hw->mac.type) {
 369         case e1000_82571:
 370         case e1000_82572:
 371                 /*
 372                  * The 82571 firmware may still be configuring the PHY.
 373                  * In this case, we cannot access the PHY until the
 374                  * configuration is done.  So we explicitly set the
 375                  * PHY ID.
 376                  */
 377                 phy->id = IGP01E1000_I_PHY_ID;
 378                 break;
 379         case e1000_82573:
 380                 return e1000e_get_phy_id(hw);
 381                 break;
 382         case e1000_82574:
 383         case e1000_82583:
 384                 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
 385                 if (ret_val)
 386                         return ret_val;
 387
 388                 phy->id = (u32)(phy_id << 16);
 389                 udelay(20);
 390                 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
 391                 if (ret_val)
 392                         return ret_val;
 393
 394                 phy->id |= (u32)(phy_id);
 395                 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
 396                 break;
 397         default:
 398                 return -E1000_ERR_PHY;
 399                 break;
 400         }
 401
 402         return 0;
 403 }
 404
 405 /**
 406  *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
 407  *  @hw: pointer to the HW structure
 408  *
 409  *  Acquire the HW semaphore to access the PHY or NVM
 410  **/
 411 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
 412 {
 413         u32 swsm;
 414         s32 timeout = hw->nvm.word_size + 1;
 415         s32 i = 0;
 416
 417         /* Get the FW semaphore. */
 418         for (i = 0; i < timeout; i++) {
 419                 swsm = er32(SWSM);
 420                 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
 421
 422                 /* Semaphore acquired if bit latched */
 423                 if (er32(SWSM) & E1000_SWSM_SWESMBI)
 424                         break;
 425
 426                 udelay(50);
 427         }
 428
 429         if (i == timeout) {
 430                 /* Release semaphores */
 431                 e1000e_put_hw_semaphore(hw);
 432                 hw_dbg(hw, "Driver can't access the NVM\n");
 433                 return -E1000_ERR_NVM;
 434         }
 435
 436         return 0;
 437 }
 438
 439 /**
 440  *  e1000_put_hw_semaphore_82571 - Release hardware semaphore
 441  *  @hw: pointer to the HW structure
 442  *
 443  *  Release hardware semaphore used to access the PHY or NVM
 444  **/
 445 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
 446 {
 447         u32 swsm;
 448
 449         swsm = er32(SWSM);
 450
 451         swsm &= ~E1000_SWSM_SWESMBI;
 452
 453         ew32(SWSM, swsm);
 454 }
 455
 456 /**
 457  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
 458  *  @hw: pointer to the HW structure
 459  *
 460  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
 461  *  Then for non-82573 hardware, set the EEPROM access request bit and wait
 462  *  for EEPROM access grant bit.  If the access grant bit is not set, release
 463  *  hardware semaphore.
 464  **/
 465 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
 466 {
 467         s32 ret_val;
 468
 469         ret_val = e1000_get_hw_semaphore_82571(hw);
 470         if (ret_val)
 471                 return ret_val;
 472
 473         switch (hw->mac.type) {
 474         case e1000_82573:
 475         case e1000_82574:
 476         case e1000_82583:
 477                 break;
 478         default:
 479                 ret_val = e1000e_acquire_nvm(hw);
 480                 break;
 481         }
 482
 483         if (ret_val)
 484                 e1000_put_hw_semaphore_82571(hw);
 485
 486         return ret_val;
 487 }
 488
 489 /**
 490  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
 491  *  @hw: pointer to the HW structure
 492  *
 493  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 494  **/
 495 static void e1000_release_nvm_82571(struct e1000_hw *hw)
 496 {
 497         e1000e_release_nvm(hw);
 498         e1000_put_hw_semaphore_82571(hw);
 499 }
 500
 501 /**
 502  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
 503  *  @hw: pointer to the HW structure
 504  *  @offset: offset within the EEPROM to be written to
 505  *  @words: number of words to write
 506  *  @data: 16 bit word(s) to be written to the EEPROM
 507  *
 508  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
 509  *
 510  *  If e1000e_update_nvm_checksum is not called after this function, the
 511  *  EEPROM will most likely contain an invalid checksum.
 512  **/
 513 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
 514                                  u16 *data)
 515 {
 516         s32 ret_val;
 517
 518         switch (hw->mac.type) {
 519         case e1000_82573:
 520         case e1000_82574:
 521         case e1000_82583:
 522                 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
 523                 break;
 524         case e1000_82571:
 525         case e1000_82572:
 526                 ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
 527                 break;
 528         default:
 529                 ret_val = -E1000_ERR_NVM;
 530                 break;
 531         }
 532
 533         return ret_val;
 534 }
 535
 536 /**
 537  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
 538  *  @hw: pointer to the HW structure
 539  *
 540  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 541  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 542  *  value to the EEPROM.
 543  **/
 544 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
 545 {
 546         u32 eecd;
 547         s32 ret_val;
 548         u16 i;
 549
 550         ret_val = e1000e_update_nvm_checksum_generic(hw);
 551         if (ret_val)
 552                 return ret_val;
 553
 554         /*
 555          * If our nvm is an EEPROM, then we're done
 556          * otherwise, commit the checksum to the flash NVM.
 557          */
 558         if (hw->nvm.type != e1000_nvm_flash_hw)
 559                 return ret_val;
 560
 561         /* Check for pending operations. */
 562         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 563                 msleep(1);
 564                 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
 565                         break;
 566         }
 567
 568         if (i == E1000_FLASH_UPDATES)
 569                 return -E1000_ERR_NVM;
 570
 571         /* Reset the firmware if using STM opcode. */
 572         if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
 573                 /*
 574                  * The enabling of and the actual reset must be done
 575                  * in two write cycles.
 576                  */
 577                 ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
 578                 e1e_flush();
 579                 ew32(HICR, E1000_HICR_FW_RESET);
 580         }
 581
 582         /* Commit the write to flash */
 583         eecd = er32(EECD) | E1000_EECD_FLUPD;
 584         ew32(EECD, eecd);
 585
 586         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 587                 msleep(1);
 588                 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
 589                         break;
 590         }
 591
 592         if (i == E1000_FLASH_UPDATES)
 593                 return -E1000_ERR_NVM;
 594
 595         return 0;
 596 }
 597
 598 /**
 599  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
 600  *  @hw: pointer to the HW structure
 601  *
 602  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
 603  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
 604  **/
 605 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
 606 {
 607         if (hw->nvm.type == e1000_nvm_flash_hw)
 608                 e1000_fix_nvm_checksum_82571(hw);
 609
 610         return e1000e_validate_nvm_checksum_generic(hw);
 611 }
 612
 613 /**
 614  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
 615  *  @hw: pointer to the HW structure
 616  *  @offset: offset within the EEPROM to be written to
 617  *  @words: number of words to write
 618  *  @data: 16 bit word(s) to be written to the EEPROM
 619  *
 620  *  After checking for invalid values, poll the EEPROM to ensure the previous
 621  *  command has completed before trying to write the next word.  After write
 622  *  poll for completion.
 623  *
 624  *  If e1000e_update_nvm_checksum is not called after this function, the
 625  *  EEPROM will most likely contain an invalid checksum.
 626  **/
 627 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
 628                                       u16 words, u16 *data)
 629 {
 630         struct e1000_nvm_info *nvm = &hw->nvm;
 631         u32 i;
 632         u32 eewr = 0;
 633         s32 ret_val = 0;
 634
 635         /*
 636          * A check for invalid values:  offset too large, too many words,
 637          * and not enough words.
 638          */
 639         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 640             (words == 0)) {
 641                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
 642                 return -E1000_ERR_NVM;
 643         }
 644
 645         for (i = 0; i < words; i++) {
 646                 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
 647                        ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
 648                        E1000_NVM_RW_REG_START;
 649
 650                 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 651                 if (ret_val)
 652                         break;
 653
 654                 ew32(EEWR, eewr);
 655
 656                 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 657                 if (ret_val)
 658                         break;
 659         }
 660
 661         return ret_val;
 662 }
 663
 664 /**
 665  *  e1000_get_cfg_done_82571 - Poll for configuration done
 666  *  @hw: pointer to the HW structure
 667  *
 668  *  Reads the management control register for the config done bit to be set.
 669  **/
 670 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
 671 {
 672         s32 timeout = PHY_CFG_TIMEOUT;
 673
 674         while (timeout) {
 675                 if (er32(EEMNGCTL) &
 676                     E1000_NVM_CFG_DONE_PORT_0)
 677                         break;
 678                 msleep(1);
 679                 timeout--;
 680         }
 681         if (!timeout) {
 682                 hw_dbg(hw, "MNG configuration cycle has not completed.\n");
 683                 return -E1000_ERR_RESET;
 684         }
 685
 686         return 0;
 687 }
 688
 689 /**
 690  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
 691  *  @hw: pointer to the HW structure
 692  *  @active: TRUE to enable LPLU, FALSE to disable
 693  *
 694  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
 695  *  this function also disables smart speed and vice versa.  LPLU will not be
 696  *  activated unless the device autonegotiation advertisement meets standards
 697  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
 698  *  pointer entry point only called by PHY setup routines.
 699  **/
 700 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
 701 {
 702         struct e1000_phy_info *phy = &hw->phy;
 703         s32 ret_val;
 704         u16 data;
 705
 706         ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 707         if (ret_val)
 708                 return ret_val;
 709
 710         if (active) {
 711                 data |= IGP02E1000_PM_D0_LPLU;
 712                 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
 713                 if (ret_val)
 714                         return ret_val;
 715
 716                 /* When LPLU is enabled, we should disable SmartSpeed */
 717                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
 718                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 719                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
 720                 if (ret_val)
 721                         return ret_val;
 722         } else {
 723                 data &= ~IGP02E1000_PM_D0_LPLU;
 724                 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
 725                 /*
 726                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 727                  * during Dx states where the power conservation is most
 728                  * important.  During driver activity we should enable
 729                  * SmartSpeed, so performance is maintained.
 730                  */
 731                 if (phy->smart_speed == e1000_smart_speed_on) {
 732                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 733                                            &data);
 734                         if (ret_val)
 735                                 return ret_val;
 736
 737                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 738                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 739                                            data);
 740                         if (ret_val)
 741                                 return ret_val;
 742                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 743                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 744                                            &data);
 745                         if (ret_val)
 746                                 return ret_val;
 747
 748                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 749                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 750                                            data);
 751                         if (ret_val)
 752                                 return ret_val;
 753                 }
 754         }
 755
 756         return 0;
 757 }
 758
 759 /**
 760  *  e1000_reset_hw_82571 - Reset hardware
 761  *  @hw: pointer to the HW structure
 762  *
 763  *  This resets the hardware into a known state.  This is a
 764  *  function pointer entry point called by the api module.
 765  **/
 766 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
 767 {
 768         u32 ctrl;
 769         u32 extcnf_ctrl;
 770         u32 ctrl_ext;
 771         u32 icr;
 772         s32 ret_val;
 773         u16 i = 0;
 774
 775         /*
 776          * Prevent the PCI-E bus from sticking if there is no TLP connection
 777          * on the last TLP read/write transaction when MAC is reset.
 778          */
 779         ret_val = e1000e_disable_pcie_master(hw);
 780         if (ret_val)
 781                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
 782
 783         hw_dbg(hw, "Masking off all interrupts\n");
 784         ew32(IMC, 0xffffffff);
 785
 786         ew32(RCTL, 0);
 787         ew32(TCTL, E1000_TCTL_PSP);
 788         e1e_flush();
 789
 790         msleep(10);
 791
 792         /*
 793          * Must acquire the MDIO ownership before MAC reset.
 794          * Ownership defaults to firmware after a reset.
 795          */
 796         switch (hw->mac.type) {
 797         case e1000_82573:
 798         case e1000_82574:
 799         case e1000_82583:
 800                 extcnf_ctrl = er32(EXTCNF_CTRL);
 801                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 802
 803                 do {
 804                         ew32(EXTCNF_CTRL, extcnf_ctrl);
 805                         extcnf_ctrl = er32(EXTCNF_CTRL);
 806
 807                         if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
 808                                 break;
 809
 810                         extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 811
 812                         msleep(2);
 813                         i++;
 814                 } while (i < MDIO_OWNERSHIP_TIMEOUT);
 815                 break;
 816         default:
 817                 break;
 818         }
 819
 820         ctrl = er32(CTRL);
 821
 822         hw_dbg(hw, "Issuing a global reset to MAC\n");
 823         ew32(CTRL, ctrl | E1000_CTRL_RST);
 824
 825         if (hw->nvm.type == e1000_nvm_flash_hw) {
 826                 udelay(10);
 827                 ctrl_ext = er32(CTRL_EXT);
 828                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
 829                 ew32(CTRL_EXT, ctrl_ext);
 830                 e1e_flush();
 831         }
 832
 833         ret_val = e1000e_get_auto_rd_done(hw);
 834         if (ret_val)
 835                 /* We don't want to continue accessing MAC registers. */
 836                 return ret_val;
 837
 838         /*
 839          * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
 840          * Need to wait for Phy configuration completion before accessing
 841          * NVM and Phy.
 842          */
 843
 844         switch (hw->mac.type) {
 845         case e1000_82573:
 846         case e1000_82574:
 847         case e1000_82583:
 848                 msleep(25);
 849                 break;
 850         default:
 851                 break;
 852         }
 853
 854         /* Clear any pending interrupt events. */
 855         ew32(IMC, 0xffffffff);
 856         icr = er32(ICR);
 857
 858         if (hw->mac.type == e1000_82571 &&
 859                 hw->dev_spec.e82571.alt_mac_addr_is_present)
 860                         e1000e_set_laa_state_82571(hw, true);
 861
 862         /* Reinitialize the 82571 serdes link state machine */
 863         if (hw->phy.media_type == e1000_media_type_internal_serdes)
 864                 hw->mac.serdes_link_state = e1000_serdes_link_down;
 865
 866         return 0;
 867 }
 868
 869 /**
 870  *  e1000_init_hw_82571 - Initialize hardware
 871  *  @hw: pointer to the HW structure
 872  *
 873  *  This inits the hardware readying it for operation.
 874  **/
 875 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
 876 {
 877         struct e1000_mac_info *mac = &hw->mac;
 878         u32 reg_data;
 879         s32 ret_val;
 880         u16 i;
 881         u16 rar_count = mac->rar_entry_count;
 882
 883         e1000_initialize_hw_bits_82571(hw);
 884
 885         /* Initialize identification LED */
 886         ret_val = e1000e_id_led_init(hw);
 887         if (ret_val) {
 888                 hw_dbg(hw, "Error initializing identification LED\n");
 889                 return ret_val;
 890         }
 891
 892         /* Disabling VLAN filtering */
 893         hw_dbg(hw, "Initializing the IEEE VLAN\n");
 894         e1000e_clear_vfta(hw);
 895
 896         /* Setup the receive address. */
 897         /*
 898          * If, however, a locally administered address was assigned to the
 899          * 82571, we must reserve a RAR for it to work around an issue where
 900          * resetting one port will reload the MAC on the other port.
 901          */
 902         if (e1000e_get_laa_state_82571(hw))
 903                 rar_count--;
 904         e1000e_init_rx_addrs(hw, rar_count);
 905
 906         /* Zero out the Multicast HASH table */
 907         hw_dbg(hw, "Zeroing the MTA\n");
 908         for (i = 0; i < mac->mta_reg_count; i++)
 909                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 910
 911         /* Setup link and flow control */
 912         ret_val = e1000_setup_link_82571(hw);
 913
 914         /* Set the transmit descriptor write-back policy */
 915         reg_data = er32(TXDCTL(0));
 916         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 917                    E1000_TXDCTL_FULL_TX_DESC_WB |
 918                    E1000_TXDCTL_COUNT_DESC;
 919         ew32(TXDCTL(0), reg_data);
 920
 921         /* ...for both queues. */
 922         switch (mac->type) {
 923         case e1000_82573:
 924         case e1000_82574:
 925         case e1000_82583:
 926                 e1000e_enable_tx_pkt_filtering(hw);
 927                 reg_data = er32(GCR);
 928                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
 929                 ew32(GCR, reg_data);
 930                 break;
 931         default:
 932                 reg_data = er32(TXDCTL(1));
 933                 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 934                            E1000_TXDCTL_FULL_TX_DESC_WB |
 935                            E1000_TXDCTL_COUNT_DESC;
 936                 ew32(TXDCTL(1), reg_data);
 937                 break;
 938         }
 939
 940         /*
 941          * Clear all of the statistics registers (clear on read).  It is
 942          * important that we do this after we have tried to establish link
 943          * because the symbol error count will increment wildly if there
 944          * is no link.
 945          */
 946         e1000_clear_hw_cntrs_82571(hw);
 947
 948         return ret_val;
 949 }
 950
 951 /**
 952  *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
 953  *  @hw: pointer to the HW structure
 954  *
 955  *  Initializes required hardware-dependent bits needed for normal operation.
 956  **/
 957 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
 958 {
 959         u32 reg;
 960
 961         /* Transmit Descriptor Control 0 */
 962         reg = er32(TXDCTL(0));
 963         reg |= (1 << 22);
 964         ew32(TXDCTL(0), reg);
 965
 966         /* Transmit Descriptor Control 1 */
 967         reg = er32(TXDCTL(1));
 968         reg |= (1 << 22);
 969         ew32(TXDCTL(1), reg);
 970
 971         /* Transmit Arbitration Control 0 */
 972         reg = er32(TARC(0));
 973         reg &= ~(0xF << 27); /* 30:27 */
 974         switch (hw->mac.type) {
 975         case e1000_82571:
 976         case e1000_82572:
 977                 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
 978                 break;
 979         default:
 980                 break;
 981         }
 982         ew32(TARC(0), reg);
 983
 984         /* Transmit Arbitration Control 1 */
 985         reg = er32(TARC(1));
 986         switch (hw->mac.type) {
 987         case e1000_82571:
 988         case e1000_82572:
 989                 reg &= ~((1 << 29) | (1 << 30));
 990                 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
 991                 if (er32(TCTL) & E1000_TCTL_MULR)
 992                         reg &= ~(1 << 28);
 993                 else
 994                         reg |= (1 << 28);
 995                 ew32(TARC(1), reg);
 996                 break;
 997         default:
 998                 break;
 999         }
1000
1001         /* Device Control */
1002         switch (hw->mac.type) {
1003         case e1000_82573:
1004         case e1000_82574:
1005         case e1000_82583:
1006                 reg = er32(CTRL);
1007                 reg &= ~(1 << 29);
1008                 ew32(CTRL, reg);
1009                 break;
1010         default:
1011                 break;
1012         }
1013
1014         /* Extended Device Control */
1015         switch (hw->mac.type) {
1016         case e1000_82573:
1017         case e1000_82574:
1018         case e1000_82583:
1019                 reg = er32(CTRL_EXT);
1020                 reg &= ~(1 << 23);
1021                 reg |= (1 << 22);
1022                 ew32(CTRL_EXT, reg);
1023                 break;
1024         default:
1025                 break;
1026         }
1027
1028         if (hw->mac.type == e1000_82571) {
1029                 reg = er32(PBA_ECC);
1030                 reg |= E1000_PBA_ECC_CORR_EN;
1031                 ew32(PBA_ECC, reg);
1032         }
1033         /*
1034          * Workaround for hardware errata.
1035          * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1036          */
1037
1038         if ((hw->mac.type == e1000_82571) ||
1039            (hw->mac.type == e1000_82572)) {
1040                 reg = er32(CTRL_EXT);
1041                 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1042                 ew32(CTRL_EXT, reg);
1043         }
1044
1045
1046         /* PCI-Ex Control Registers */
1047         switch (hw->mac.type) {
1048         case e1000_82574:
1049         case e1000_82583:
1050                 reg = er32(GCR);
1051                 reg |= (1 << 22);
1052                 ew32(GCR, reg);
1053
1054                 reg = er32(GCR2);
1055                 reg |= 1;
1056                 ew32(GCR2, reg);
1057                 break;
1058         default:
1059                 break;
1060         }
1061
1062         return;
1063 }
1064
1065 /**
1066  *  e1000e_clear_vfta - Clear VLAN filter table
1067  *  @hw: pointer to the HW structure
1068  *
1069  *  Clears the register array which contains the VLAN filter table by
1070  *  setting all the values to 0.
1071  **/
1072 void e1000e_clear_vfta(struct e1000_hw *hw)
1073 {
1074         u32 offset;
1075         u32 vfta_value = 0;
1076         u32 vfta_offset = 0;
1077         u32 vfta_bit_in_reg = 0;
1078
1079         switch (hw->mac.type) {
1080         case e1000_82573:
1081         case e1000_82574:
1082         case e1000_82583:
1083                 if (hw->mng_cookie.vlan_id != 0) {
1084                         /*
1085                          * The VFTA is a 4096b bit-field, each identifying
1086                          * a single VLAN ID.  The following operations
1087                          * determine which 32b entry (i.e. offset) into the
1088                          * array we want to set the VLAN ID (i.e. bit) of
1089                          * the manageability unit.
1090                          */
1091                         vfta_offset = (hw->mng_cookie.vlan_id >>
1092                                        E1000_VFTA_ENTRY_SHIFT) &
1093                                       E1000_VFTA_ENTRY_MASK;
1094                         vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
1095                                                E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1096                 }
1097                 break;
1098         default:
1099                 break;
1100         }
1101         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1102                 /*
1103                  * If the offset we want to clear is the same offset of the
1104                  * manageability VLAN ID, then clear all bits except that of
1105                  * the manageability unit.
1106                  */
1107                 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1108                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1109                 e1e_flush();
1110         }
1111 }
1112
1113 /**
1114  *  e1000_check_mng_mode_82574 - Check manageability is enabled
1115  *  @hw: pointer to the HW structure
1116  *
1117  *  Reads the NVM Initialization Control Word 2 and returns true
1118  *  (>0) if any manageability is enabled, else false (0).
1119  **/
1120 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1121 {
1122         u16 data;
1123
1124         e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1125         return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1126 }
1127
1128 /**
1129  *  e1000_led_on_82574 - Turn LED on
1130  *  @hw: pointer to the HW structure
1131  *
1132  *  Turn LED on.
1133  **/
1134 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1135 {
1136         u32 ctrl;
1137         u32 i;
1138
1139         ctrl = hw->mac.ledctl_mode2;
1140         if (!(E1000_STATUS_LU & er32(STATUS))) {
1141                 /*
1142                  * If no link, then turn LED on by setting the invert bit
1143                  * for each LED that's "on" (0x0E) in ledctl_mode2.
1144                  */
1145                 for (i = 0; i < 4; i++)
1146                         if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1147                             E1000_LEDCTL_MODE_LED_ON)
1148                                 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1149         }
1150         ew32(LEDCTL, ctrl);
1151
1152         return 0;
1153 }
1154
1155 /**
1156  *  e1000_update_mc_addr_list_82571 - Update Multicast addresses
1157  *  @hw: pointer to the HW structure
1158  *  @mc_addr_list: array of multicast addresses to program
1159  *  @mc_addr_count: number of multicast addresses to program
1160  *  @rar_used_count: the first RAR register free to program
1161  *  @rar_count: total number of supported Receive Address Registers
1162  *
1163  *  Updates the Receive Address Registers and Multicast Table Array.
1164  *  The caller must have a packed mc_addr_list of multicast addresses.
1165  *  The parameter rar_count will usually be hw->mac.rar_entry_count
1166  *  unless there are workarounds that change this.
1167  **/
1168 static void e1000_update_mc_addr_list_82571(struct e1000_hw *hw,
1169                                             u8 *mc_addr_list,
1170                                             u32 mc_addr_count,
1171                                             u32 rar_used_count,
1172                                             u32 rar_count)
1173 {
1174         if (e1000e_get_laa_state_82571(hw))
1175                 rar_count--;
1176
1177         e1000e_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count,
1178                                            rar_used_count, rar_count);
1179 }
1180
1181 /**
1182  *  e1000_setup_link_82571 - Setup flow control and link settings
1183  *  @hw: pointer to the HW structure
1184  *
1185  *  Determines which flow control settings to use, then configures flow
1186  *  control.  Calls the appropriate media-specific link configuration
1187  *  function.  Assuming the adapter has a valid link partner, a valid link
1188  *  should be established.  Assumes the hardware has previously been reset
1189  *  and the transmitter and receiver are not enabled.
1190  **/
1191 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1192 {
1193         /*
1194          * 82573 does not have a word in the NVM to determine
1195          * the default flow control setting, so we explicitly
1196          * set it to full.
1197          */
1198         switch (hw->mac.type) {
1199         case e1000_82573:
1200         case e1000_82574:
1201         case e1000_82583:
1202                 if (hw->fc.requested_mode == e1000_fc_default)
1203                         hw->fc.requested_mode = e1000_fc_full;
1204                 break;
1205         default:
1206                 break;
1207         }
1208
1209         return e1000e_setup_link(hw);
1210 }
1211
1212 /**
1213  *  e1000_setup_copper_link_82571 - Configure copper link settings
1214  *  @hw: pointer to the HW structure
1215  *
1216  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1217  *  for link, once link is established calls to configure collision distance
1218  *  and flow control are called.
1219  **/
1220 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1221 {
1222         u32 ctrl;
1223         u32 led_ctrl;
1224         s32 ret_val;
1225
1226         ctrl = er32(CTRL);
1227         ctrl |= E1000_CTRL_SLU;
1228         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1229         ew32(CTRL, ctrl);
1230
1231         switch (hw->phy.type) {
1232         case e1000_phy_m88:
1233         case e1000_phy_bm:
1234                 ret_val = e1000e_copper_link_setup_m88(hw);
1235                 break;
1236         case e1000_phy_igp_2:
1237                 ret_val = e1000e_copper_link_setup_igp(hw);
1238                 /* Setup activity LED */
1239                 led_ctrl = er32(LEDCTL);
1240                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1241                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1242                 ew32(LEDCTL, led_ctrl);
1243                 break;
1244         default:
1245                 return -E1000_ERR_PHY;
1246                 break;
1247         }
1248
1249         if (ret_val)
1250                 return ret_val;
1251
1252         ret_val = e1000e_setup_copper_link(hw);
1253
1254         return ret_val;
1255 }
1256
1257 /**
1258  *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1259  *  @hw: pointer to the HW structure
1260  *
1261  *  Configures collision distance and flow control for fiber and serdes links.
1262  *  Upon successful setup, poll for link.
1263  **/
1264 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1265 {
1266         switch (hw->mac.type) {
1267         case e1000_82571:
1268         case e1000_82572:
1269                 /*
1270                  * If SerDes loopback mode is entered, there is no form
1271                  * of reset to take the adapter out of that mode.  So we
1272                  * have to explicitly take the adapter out of loopback
1273                  * mode.  This prevents drivers from twiddling their thumbs
1274                  * if another tool failed to take it out of loopback mode.
1275                  */
1276                 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1277                 break;
1278         default:
1279                 break;
1280         }
1281
1282         return e1000e_setup_fiber_serdes_link(hw);
1283 }
1284
1285 /**
1286  *  e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1287  *  @hw: pointer to the HW structure
1288  *
1289  *  Checks for link up on the hardware.  If link is not up and we have
1290  *  a signal, then we need to force link up.
1291  **/
1292 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1293 {
1294         struct e1000_mac_info *mac = &hw->mac;
1295         u32 rxcw;
1296         u32 ctrl;
1297         u32 status;
1298         s32 ret_val = 0;
1299
1300         ctrl = er32(CTRL);
1301         status = er32(STATUS);
1302         rxcw = er32(RXCW);
1303
1304         if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1305
1306                 /* Receiver is synchronized with no invalid bits.  */
1307                 switch (mac->serdes_link_state) {
1308                 case e1000_serdes_link_autoneg_complete:
1309                         if (!(status & E1000_STATUS_LU)) {
1310                                 /*
1311                                  * We have lost link, retry autoneg before
1312                                  * reporting link failure
1313                                  */
1314                                 mac->serdes_link_state =
1315                                     e1000_serdes_link_autoneg_progress;
1316                                 hw_dbg(hw, "AN_UP     -> AN_PROG\n");
1317                         }
1318                 break;
1319
1320                 case e1000_serdes_link_forced_up:
1321                         /*
1322                          * If we are receiving /C/ ordered sets, re-enable
1323                          * auto-negotiation in the TXCW register and disable
1324                          * forced link in the Device Control register in an
1325                          * attempt to auto-negotiate with our link partner.
1326                          */
1327                         if (rxcw & E1000_RXCW_C) {
1328                                 /* Enable autoneg, and unforce link up */
1329                                 ew32(TXCW, mac->txcw);
1330                                 ew32(CTRL,
1331                                     (ctrl & ~E1000_CTRL_SLU));
1332                                 mac->serdes_link_state =
1333                                     e1000_serdes_link_autoneg_progress;
1334                                 hw_dbg(hw, "FORCED_UP -> AN_PROG\n");
1335                         }
1336                         break;
1337
1338                 case e1000_serdes_link_autoneg_progress:
1339                         /*
1340                          * If the LU bit is set in the STATUS register,
1341                          * autoneg has completed sucessfully. If not,
1342                          * try foring the link because the far end may be
1343                          * available but not capable of autonegotiation.
1344                          */
1345                         if (status & E1000_STATUS_LU)  {
1346                                 mac->serdes_link_state =
1347                                     e1000_serdes_link_autoneg_complete;
1348                                 hw_dbg(hw, "AN_PROG   -> AN_UP\n");
1349                         } else {
1350                                 /*
1351                                  * Disable autoneg, force link up and
1352                                  * full duplex, and change state to forced
1353                                  */
1354                                 ew32(TXCW,
1355                                     (mac->txcw & ~E1000_TXCW_ANE));
1356                                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1357                                 ew32(CTRL, ctrl);
1358
1359                                 /* Configure Flow Control after link up. */
1360                                 ret_val =
1361                                     e1000e_config_fc_after_link_up(hw);
1362                                 if (ret_val) {
1363                                         hw_dbg(hw, "Error config flow control\n");
1364                                         break;
1365                                 }
1366                                 mac->serdes_link_state =
1367                                     e1000_serdes_link_forced_up;
1368                                 hw_dbg(hw, "AN_PROG   -> FORCED_UP\n");
1369                         }
1370                         mac->serdes_has_link = true;
1371                         break;
1372
1373                 case e1000_serdes_link_down:
1374                 default:
1375                         /* The link was down but the receiver has now gained
1376                          * valid sync, so lets see if we can bring the link
1377                          * up. */
1378                         ew32(TXCW, mac->txcw);
1379                         ew32(CTRL,
1380                             (ctrl & ~E1000_CTRL_SLU));
1381                         mac->serdes_link_state =
1382                             e1000_serdes_link_autoneg_progress;
1383                         hw_dbg(hw, "DOWN      -> AN_PROG\n");
1384                         break;
1385                 }
1386         } else {
1387                 if (!(rxcw & E1000_RXCW_SYNCH)) {
1388                         mac->serdes_has_link = false;
1389                         mac->serdes_link_state = e1000_serdes_link_down;
1390                         hw_dbg(hw, "ANYSTATE  -> DOWN\n");
1391                 } else {
1392                         /*
1393                          * We have sync, and can tolerate one
1394                          * invalid (IV) codeword before declaring
1395                          * link down, so reread to look again
1396                          */
1397                         udelay(10);
1398                         rxcw = er32(RXCW);
1399                         if (rxcw & E1000_RXCW_IV) {
1400                                 mac->serdes_link_state = e1000_serdes_link_down;
1401                                 mac->serdes_has_link = false;
1402                                 hw_dbg(hw, "ANYSTATE  -> DOWN\n");
1403                         }
1404                 }
1405         }
1406
1407         return ret_val;
1408 }
1409
1410 /**
1411  *  e1000_valid_led_default_82571 - Verify a valid default LED config
1412  *  @hw: pointer to the HW structure
1413  *  @data: pointer to the NVM (EEPROM)
1414  *
1415  *  Read the EEPROM for the current default LED configuration.  If the
1416  *  LED configuration is not valid, set to a valid LED configuration.
1417  **/
1418 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1419 {
1420         s32 ret_val;
1421
1422         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1423         if (ret_val) {
1424                 hw_dbg(hw, "NVM Read Error\n");
1425                 return ret_val;
1426         }
1427
1428         switch (hw->mac.type) {
1429         case e1000_82573:
1430         case e1000_82574:
1431         case e1000_82583:
1432                 if (*data == ID_LED_RESERVED_F746)
1433                         *data = ID_LED_DEFAULT_82573;
1434                 break;
1435         default:
1436                 if (*data == ID_LED_RESERVED_0000 ||
1437                     *data == ID_LED_RESERVED_FFFF)
1438                         *data = ID_LED_DEFAULT;
1439                 break;
1440         }
1441
1442         return 0;
1443 }
1444
1445 /**
1446  *  e1000e_get_laa_state_82571 - Get locally administered address state
1447  *  @hw: pointer to the HW structure
1448  *
1449  *  Retrieve and return the current locally administered address state.
1450  **/
1451 bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1452 {
1453         if (hw->mac.type != e1000_82571)
1454                 return 0;
1455
1456         return hw->dev_spec.e82571.laa_is_present;
1457 }
1458
1459 /**
1460  *  e1000e_set_laa_state_82571 - Set locally administered address state
1461  *  @hw: pointer to the HW structure
1462  *  @state: enable/disable locally administered address
1463  *
1464  *  Enable/Disable the current locally administers address state.
1465  **/
1466 void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1467 {
1468         if (hw->mac.type != e1000_82571)
1469                 return;
1470
1471         hw->dev_spec.e82571.laa_is_present = state;
1472
1473         /* If workaround is activated... */
1474         if (state)
1475                 /*
1476                  * Hold a copy of the LAA in RAR[14] This is done so that
1477                  * between the time RAR[0] gets clobbered and the time it
1478                  * gets fixed, the actual LAA is in one of the RARs and no
1479                  * incoming packets directed to this port are dropped.
1480                  * Eventually the LAA will be in RAR[0] and RAR[14].
1481                  */
1482                 e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1);
1483 }
1484
1485 /**
1486  *  e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1487  *  @hw: pointer to the HW structure
1488  *
1489  *  Verifies that the EEPROM has completed the update.  After updating the
1490  *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
1491  *  the checksum fix is not implemented, we need to set the bit and update
1492  *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
1493  *  we need to return bad checksum.
1494  **/
1495 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1496 {
1497         struct e1000_nvm_info *nvm = &hw->nvm;
1498         s32 ret_val;
1499         u16 data;
1500
1501         if (nvm->type != e1000_nvm_flash_hw)
1502                 return 0;
1503
1504         /*
1505          * Check bit 4 of word 10h.  If it is 0, firmware is done updating
1506          * 10h-12h.  Checksum may need to be fixed.
1507          */
1508         ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
1509         if (ret_val)
1510                 return ret_val;
1511
1512         if (!(data & 0x10)) {
1513                 /*
1514                  * Read 0x23 and check bit 15.  This bit is a 1
1515                  * when the checksum has already been fixed.  If
1516                  * the checksum is still wrong and this bit is a
1517                  * 1, we need to return bad checksum.  Otherwise,
1518                  * we need to set this bit to a 1 and update the
1519                  * checksum.
1520                  */
1521                 ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
1522                 if (ret_val)
1523                         return ret_val;
1524
1525                 if (!(data & 0x8000)) {
1526                         data |= 0x8000;
1527                         ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
1528                         if (ret_val)
1529                                 return ret_val;
1530                         ret_val = e1000e_update_nvm_checksum(hw);
1531                 }
1532         }
1533
1534         return 0;
1535 }
1536
1537 /**
1538  *  e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1539  *  @hw: pointer to the HW structure
1540  *
1541  *  Clears the hardware counters by reading the counter registers.
1542  **/
1543 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1544 {
1545         u32 temp;
1546
1547         e1000e_clear_hw_cntrs_base(hw);
1548
1549         temp = er32(PRC64);
1550         temp = er32(PRC127);
1551         temp = er32(PRC255);
1552         temp = er32(PRC511);
1553         temp = er32(PRC1023);
1554         temp = er32(PRC1522);
1555         temp = er32(PTC64);
1556         temp = er32(PTC127);
1557         temp = er32(PTC255);
1558         temp = er32(PTC511);
1559         temp = er32(PTC1023);
1560         temp = er32(PTC1522);
1561
1562         temp = er32(ALGNERRC);
1563         temp = er32(RXERRC);
1564         temp = er32(TNCRS);
1565         temp = er32(CEXTERR);
1566         temp = er32(TSCTC);
1567         temp = er32(TSCTFC);
1568
1569         temp = er32(MGTPRC);
1570         temp = er32(MGTPDC);
1571         temp = er32(MGTPTC);
1572
1573         temp = er32(IAC);
1574         temp = er32(ICRXOC);
1575
1576         temp = er32(ICRXPTC);
1577         temp = er32(ICRXATC);
1578         temp = er32(ICTXPTC);
1579         temp = er32(ICTXATC);
1580         temp = er32(ICTXQEC);
1581         temp = er32(ICTXQMTC);
1582         temp = er32(ICRXDMTC);
1583 }
1584
1585 static struct e1000_mac_operations e82571_mac_ops = {
1586         /* .check_mng_mode: mac type dependent */
1587         /* .check_for_link: media type dependent */
1588         .cleanup_led            = e1000e_cleanup_led_generic,
1589         .clear_hw_cntrs         = e1000_clear_hw_cntrs_82571,
1590         .get_bus_info           = e1000e_get_bus_info_pcie,
1591         /* .get_link_up_info: media type dependent */
1592         /* .led_on: mac type dependent */
1593         .led_off                = e1000e_led_off_generic,
1594         .update_mc_addr_list    = e1000_update_mc_addr_list_82571,
1595         .reset_hw               = e1000_reset_hw_82571,
1596         .init_hw                = e1000_init_hw_82571,
1597         .setup_link             = e1000_setup_link_82571,
1598         /* .setup_physical_interface: media type dependent */
1599 };
1600
1601 static struct e1000_phy_operations e82_phy_ops_igp = {
1602         .acquire_phy            = e1000_get_hw_semaphore_82571,
1603         .check_reset_block      = e1000e_check_reset_block_generic,
1604         .commit_phy             = NULL,
1605         .force_speed_duplex     = e1000e_phy_force_speed_duplex_igp,
1606         .get_cfg_done           = e1000_get_cfg_done_82571,
1607         .get_cable_length       = e1000e_get_cable_length_igp_2,
1608         .get_phy_info           = e1000e_get_phy_info_igp,
1609         .read_phy_reg           = e1000e_read_phy_reg_igp,
1610         .release_phy            = e1000_put_hw_semaphore_82571,
1611         .reset_phy              = e1000e_phy_hw_reset_generic,
1612         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1613         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1614         .write_phy_reg          = e1000e_write_phy_reg_igp,
1615         .cfg_on_link_up         = NULL,
1616 };
1617
1618 static struct e1000_phy_operations e82_phy_ops_m88 = {
1619         .acquire_phy            = e1000_get_hw_semaphore_82571,
1620         .check_reset_block      = e1000e_check_reset_block_generic,
1621         .commit_phy             = e1000e_phy_sw_reset,
1622         .force_speed_duplex     = e1000e_phy_force_speed_duplex_m88,
1623         .get_cfg_done           = e1000e_get_cfg_done,
1624         .get_cable_length       = e1000e_get_cable_length_m88,
1625         .get_phy_info           = e1000e_get_phy_info_m88,
1626         .read_phy_reg           = e1000e_read_phy_reg_m88,
1627         .release_phy            = e1000_put_hw_semaphore_82571,
1628         .reset_phy              = e1000e_phy_hw_reset_generic,
1629         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1630         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1631         .write_phy_reg          = e1000e_write_phy_reg_m88,
1632         .cfg_on_link_up         = NULL,
1633 };
1634
1635 static struct e1000_phy_operations e82_phy_ops_bm = {
1636         .acquire_phy            = e1000_get_hw_semaphore_82571,
1637         .check_reset_block      = e1000e_check_reset_block_generic,
1638         .commit_phy             = e1000e_phy_sw_reset,
1639         .force_speed_duplex     = e1000e_phy_force_speed_duplex_m88,
1640         .get_cfg_done           = e1000e_get_cfg_done,
1641         .get_cable_length       = e1000e_get_cable_length_m88,
1642         .get_phy_info           = e1000e_get_phy_info_m88,
1643         .read_phy_reg           = e1000e_read_phy_reg_bm2,
1644         .release_phy            = e1000_put_hw_semaphore_82571,
1645         .reset_phy              = e1000e_phy_hw_reset_generic,
1646         .set_d0_lplu_state      = e1000_set_d0_lplu_state_82571,
1647         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1648         .write_phy_reg          = e1000e_write_phy_reg_bm2,
1649         .cfg_on_link_up         = NULL,
1650 };
1651
1652 static struct e1000_nvm_operations e82571_nvm_ops = {
1653         .acquire_nvm            = e1000_acquire_nvm_82571,
1654         .read_nvm               = e1000e_read_nvm_eerd,
1655         .release_nvm            = e1000_release_nvm_82571,
1656         .update_nvm             = e1000_update_nvm_checksum_82571,
1657         .valid_led_default      = e1000_valid_led_default_82571,
1658         .validate_nvm           = e1000_validate_nvm_checksum_82571,
1659         .write_nvm              = e1000_write_nvm_82571,
1660 };
1661
1662 struct e1000_info e1000_82571_info = {
1663         .mac                    = e1000_82571,
1664         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1665                                   | FLAG_HAS_JUMBO_FRAMES
1666                                   | FLAG_HAS_WOL
1667                                   | FLAG_APME_IN_CTRL3
1668                                   | FLAG_RX_CSUM_ENABLED
1669                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1670                                   | FLAG_HAS_SMART_POWER_DOWN
1671                                   | FLAG_RESET_OVERWRITES_LAA /* errata */
1672                                   | FLAG_TARC_SPEED_MODE_BIT /* errata */
1673                                   | FLAG_APME_CHECK_PORT_B,
1674         .pba                    = 38,
1675         .get_variants           = e1000_get_variants_82571,
1676         .mac_ops                = &e82571_mac_ops,
1677         .phy_ops                = &e82_phy_ops_igp,
1678         .nvm_ops                = &e82571_nvm_ops,
1679 };
1680
1681 struct e1000_info e1000_82572_info = {
1682         .mac                    = e1000_82572,
1683         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1684                                   | FLAG_HAS_JUMBO_FRAMES
1685                                   | FLAG_HAS_WOL
1686                                   | FLAG_APME_IN_CTRL3
1687                                   | FLAG_RX_CSUM_ENABLED
1688                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1689                                   | FLAG_TARC_SPEED_MODE_BIT, /* errata */
1690         .pba                    = 38,
1691         .get_variants           = e1000_get_variants_82571,
1692         .mac_ops                = &e82571_mac_ops,
1693         .phy_ops                = &e82_phy_ops_igp,
1694         .nvm_ops                = &e82571_nvm_ops,
1695 };
1696
1697 struct e1000_info e1000_82573_info = {
1698         .mac                    = e1000_82573,
1699         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1700                                   | FLAG_HAS_JUMBO_FRAMES
1701                                   | FLAG_HAS_WOL
1702                                   | FLAG_APME_IN_CTRL3
1703                                   | FLAG_RX_CSUM_ENABLED
1704                                   | FLAG_HAS_SMART_POWER_DOWN
1705                                   | FLAG_HAS_AMT
1706                                   | FLAG_HAS_ERT
1707                                   | FLAG_HAS_SWSM_ON_LOAD,
1708         .pba                    = 20,
1709         .get_variants           = e1000_get_variants_82571,
1710         .mac_ops                = &e82571_mac_ops,
1711         .phy_ops                = &e82_phy_ops_m88,
1712         .nvm_ops                = &e82571_nvm_ops,
1713 };
1714
1715 struct e1000_info e1000_82574_info = {
1716         .mac                    = e1000_82574,
1717         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1718                                   | FLAG_HAS_MSIX
1719                                   | FLAG_HAS_JUMBO_FRAMES
1720                                   | FLAG_HAS_WOL
1721                                   | FLAG_APME_IN_CTRL3
1722                                   | FLAG_RX_CSUM_ENABLED
1723                                   | FLAG_HAS_SMART_POWER_DOWN
1724                                   | FLAG_HAS_AMT
1725                                   | FLAG_HAS_CTRLEXT_ON_LOAD,
1726         .pba                    = 20,
1727         .get_variants           = e1000_get_variants_82571,
1728         .mac_ops                = &e82571_mac_ops,
1729         .phy_ops                = &e82_phy_ops_bm,
1730         .nvm_ops                = &e82571_nvm_ops,
1731 };
1732
1733 struct e1000_info e1000_82583_info = {
1734         .mac                    = e1000_82583,
1735         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1736                                   | FLAG_HAS_WOL
1737                                   | FLAG_APME_IN_CTRL3
1738                                   | FLAG_RX_CSUM_ENABLED
1739                                   | FLAG_HAS_SMART_POWER_DOWN
1740                                   | FLAG_HAS_AMT
1741                                   | FLAG_HAS_CTRLEXT_ON_LOAD,
1742         .pba                    = 20,
1743         .get_variants           = e1000_get_variants_82571,
1744         .mac_ops                = &e82571_mac_ops,
1745         .phy_ops                = &e82_phy_ops_bm,
1746         .nvm_ops                = &e82571_nvm_ops,
1747 };
1748