1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for BCM963xx builtin Ethernet mac
5 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 #include <linux/init.h>
8 #include <linux/interrupt.h>
9 #include <linux/module.h>
10 #include <linux/clk.h>
11 #include <linux/etherdevice.h>
12 #include <linux/slab.h>
13 #include <linux/delay.h>
14 #include <linux/ethtool.h>
15 #include <linux/crc32.h>
16 #include <linux/err.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/platform_device.h>
19 #include <linux/if_vlan.h>
21 #include <bcm63xx_dev_enet.h>
22 #include "bcm63xx_enet.h"
24 static char bcm_enet_driver_name[] = "bcm63xx_enet";
25 static char bcm_enet_driver_version[] = "1.0";
27 static int copybreak __read_mostly = 128;
28 module_param(copybreak, int, 0);
29 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
31 /* io registers memory shared between all devices */
32 static void __iomem *bcm_enet_shared_base[3];
35 * io helpers to access mac registers
37 static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off)
39 return bcm_readl(priv->base + off);
42 static inline void enet_writel(struct bcm_enet_priv *priv,
45 bcm_writel(val, priv->base + off);
49 * io helpers to access switch registers
51 static inline u32 enetsw_readl(struct bcm_enet_priv *priv, u32 off)
53 return bcm_readl(priv->base + off);
56 static inline void enetsw_writel(struct bcm_enet_priv *priv,
59 bcm_writel(val, priv->base + off);
62 static inline u16 enetsw_readw(struct bcm_enet_priv *priv, u32 off)
64 return bcm_readw(priv->base + off);
67 static inline void enetsw_writew(struct bcm_enet_priv *priv,
70 bcm_writew(val, priv->base + off);
73 static inline u8 enetsw_readb(struct bcm_enet_priv *priv, u32 off)
75 return bcm_readb(priv->base + off);
78 static inline void enetsw_writeb(struct bcm_enet_priv *priv,
81 bcm_writeb(val, priv->base + off);
85 /* io helpers to access shared registers */
86 static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
88 return bcm_readl(bcm_enet_shared_base[0] + off);
91 static inline void enet_dma_writel(struct bcm_enet_priv *priv,
94 bcm_writel(val, bcm_enet_shared_base[0] + off);
97 static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off, int chan)
99 return bcm_readl(bcm_enet_shared_base[1] +
100 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
103 static inline void enet_dmac_writel(struct bcm_enet_priv *priv,
104 u32 val, u32 off, int chan)
106 bcm_writel(val, bcm_enet_shared_base[1] +
107 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
110 static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off, int chan)
112 return bcm_readl(bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
115 static inline void enet_dmas_writel(struct bcm_enet_priv *priv,
116 u32 val, u32 off, int chan)
118 bcm_writel(val, bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
122 * write given data into mii register and wait for transfer to end
123 * with timeout (average measured transfer time is 25us)
125 static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data)
129 /* make sure mii interrupt status is cleared */
130 enet_writel(priv, ENET_IR_MII, ENET_IR_REG);
132 enet_writel(priv, data, ENET_MIIDATA_REG);
135 /* busy wait on mii interrupt bit, with timeout */
138 if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII)
141 } while (limit-- > 0);
143 return (limit < 0) ? 1 : 0;
147 * MII internal read callback
149 static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id,
154 tmp = regnum << ENET_MIIDATA_REG_SHIFT;
155 tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
156 tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
157 tmp |= ENET_MIIDATA_OP_READ_MASK;
159 if (do_mdio_op(priv, tmp))
162 val = enet_readl(priv, ENET_MIIDATA_REG);
168 * MII internal write callback
170 static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id,
171 int regnum, u16 value)
175 tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT;
176 tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
177 tmp |= regnum << ENET_MIIDATA_REG_SHIFT;
178 tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
179 tmp |= ENET_MIIDATA_OP_WRITE_MASK;
181 (void)do_mdio_op(priv, tmp);
186 * MII read callback from phylib
188 static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id,
191 return bcm_enet_mdio_read(bus->priv, mii_id, regnum);
195 * MII write callback from phylib
197 static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id,
198 int regnum, u16 value)
200 return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value);
204 * MII read callback from mii core
206 static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id,
209 return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum);
213 * MII write callback from mii core
215 static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id,
216 int regnum, int value)
218 bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value);
224 static int bcm_enet_refill_rx(struct net_device *dev)
226 struct bcm_enet_priv *priv;
228 priv = netdev_priv(dev);
230 while (priv->rx_desc_count < priv->rx_ring_size) {
231 struct bcm_enet_desc *desc;
237 desc_idx = priv->rx_dirty_desc;
238 desc = &priv->rx_desc_cpu[desc_idx];
240 if (!priv->rx_skb[desc_idx]) {
241 skb = netdev_alloc_skb(dev, priv->rx_skb_size);
244 priv->rx_skb[desc_idx] = skb;
245 p = dma_map_single(&priv->pdev->dev, skb->data,
251 len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
252 len_stat |= DMADESC_OWNER_MASK;
253 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
254 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
255 priv->rx_dirty_desc = 0;
257 priv->rx_dirty_desc++;
260 desc->len_stat = len_stat;
262 priv->rx_desc_count++;
264 /* tell dma engine we allocated one buffer */
265 if (priv->dma_has_sram)
266 enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
268 enet_dmac_writel(priv, 1, ENETDMAC_BUFALLOC, priv->rx_chan);
271 /* If rx ring is still empty, set a timer to try allocating
272 * again at a later time. */
273 if (priv->rx_desc_count == 0 && netif_running(dev)) {
274 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
275 priv->rx_timeout.expires = jiffies + HZ;
276 add_timer(&priv->rx_timeout);
283 * timer callback to defer refill rx queue in case we're OOM
285 static void bcm_enet_refill_rx_timer(struct timer_list *t)
287 struct bcm_enet_priv *priv = from_timer(priv, t, rx_timeout);
288 struct net_device *dev = priv->net_dev;
290 spin_lock(&priv->rx_lock);
291 bcm_enet_refill_rx(dev);
292 spin_unlock(&priv->rx_lock);
296 * extract packet from rx queue
298 static int bcm_enet_receive_queue(struct net_device *dev, int budget)
300 struct bcm_enet_priv *priv;
304 priv = netdev_priv(dev);
305 kdev = &priv->pdev->dev;
308 /* don't scan ring further than number of refilled
310 if (budget > priv->rx_desc_count)
311 budget = priv->rx_desc_count;
314 struct bcm_enet_desc *desc;
320 desc_idx = priv->rx_curr_desc;
321 desc = &priv->rx_desc_cpu[desc_idx];
323 /* make sure we actually read the descriptor status at
327 len_stat = desc->len_stat;
329 /* break if dma ownership belongs to hw */
330 if (len_stat & DMADESC_OWNER_MASK)
334 priv->rx_curr_desc++;
335 if (priv->rx_curr_desc == priv->rx_ring_size)
336 priv->rx_curr_desc = 0;
337 priv->rx_desc_count--;
339 /* if the packet does not have start of packet _and_
340 * end of packet flag set, then just recycle it */
341 if ((len_stat & (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) !=
342 (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) {
343 dev->stats.rx_dropped++;
347 /* recycle packet if it's marked as bad */
348 if (!priv->enet_is_sw &&
349 unlikely(len_stat & DMADESC_ERR_MASK)) {
350 dev->stats.rx_errors++;
352 if (len_stat & DMADESC_OVSIZE_MASK)
353 dev->stats.rx_length_errors++;
354 if (len_stat & DMADESC_CRC_MASK)
355 dev->stats.rx_crc_errors++;
356 if (len_stat & DMADESC_UNDER_MASK)
357 dev->stats.rx_frame_errors++;
358 if (len_stat & DMADESC_OV_MASK)
359 dev->stats.rx_fifo_errors++;
364 skb = priv->rx_skb[desc_idx];
365 len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT;
366 /* don't include FCS */
369 if (len < copybreak) {
370 struct sk_buff *nskb;
372 nskb = napi_alloc_skb(&priv->napi, len);
374 /* forget packet, just rearm desc */
375 dev->stats.rx_dropped++;
379 dma_sync_single_for_cpu(kdev, desc->address,
380 len, DMA_FROM_DEVICE);
381 memcpy(nskb->data, skb->data, len);
382 dma_sync_single_for_device(kdev, desc->address,
383 len, DMA_FROM_DEVICE);
386 dma_unmap_single(&priv->pdev->dev, desc->address,
387 priv->rx_skb_size, DMA_FROM_DEVICE);
388 priv->rx_skb[desc_idx] = NULL;
392 skb->protocol = eth_type_trans(skb, dev);
393 dev->stats.rx_packets++;
394 dev->stats.rx_bytes += len;
395 netif_receive_skb(skb);
397 } while (--budget > 0);
399 if (processed || !priv->rx_desc_count) {
400 bcm_enet_refill_rx(dev);
403 enet_dmac_writel(priv, priv->dma_chan_en_mask,
404 ENETDMAC_CHANCFG, priv->rx_chan);
412 * try to or force reclaim of transmitted buffers
414 static int bcm_enet_tx_reclaim(struct net_device *dev, int force)
416 struct bcm_enet_priv *priv;
419 priv = netdev_priv(dev);
422 while (priv->tx_desc_count < priv->tx_ring_size) {
423 struct bcm_enet_desc *desc;
426 /* We run in a bh and fight against start_xmit, which
427 * is called with bh disabled */
428 spin_lock(&priv->tx_lock);
430 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
432 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
433 spin_unlock(&priv->tx_lock);
437 /* ensure other field of the descriptor were not read
438 * before we checked ownership */
441 skb = priv->tx_skb[priv->tx_dirty_desc];
442 priv->tx_skb[priv->tx_dirty_desc] = NULL;
443 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
446 priv->tx_dirty_desc++;
447 if (priv->tx_dirty_desc == priv->tx_ring_size)
448 priv->tx_dirty_desc = 0;
449 priv->tx_desc_count++;
451 spin_unlock(&priv->tx_lock);
453 if (desc->len_stat & DMADESC_UNDER_MASK)
454 dev->stats.tx_errors++;
460 if (netif_queue_stopped(dev) && released)
461 netif_wake_queue(dev);
467 * poll func, called by network core
469 static int bcm_enet_poll(struct napi_struct *napi, int budget)
471 struct bcm_enet_priv *priv;
472 struct net_device *dev;
475 priv = container_of(napi, struct bcm_enet_priv, napi);
479 enet_dmac_writel(priv, priv->dma_chan_int_mask,
480 ENETDMAC_IR, priv->rx_chan);
481 enet_dmac_writel(priv, priv->dma_chan_int_mask,
482 ENETDMAC_IR, priv->tx_chan);
484 /* reclaim sent skb */
485 bcm_enet_tx_reclaim(dev, 0);
487 spin_lock(&priv->rx_lock);
488 rx_work_done = bcm_enet_receive_queue(dev, budget);
489 spin_unlock(&priv->rx_lock);
491 if (rx_work_done >= budget) {
492 /* rx queue is not yet empty/clean */
496 /* no more packet in rx/tx queue, remove device from poll
498 napi_complete_done(napi, rx_work_done);
500 /* restore rx/tx interrupt */
501 enet_dmac_writel(priv, priv->dma_chan_int_mask,
502 ENETDMAC_IRMASK, priv->rx_chan);
503 enet_dmac_writel(priv, priv->dma_chan_int_mask,
504 ENETDMAC_IRMASK, priv->tx_chan);
510 * mac interrupt handler
512 static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id)
514 struct net_device *dev;
515 struct bcm_enet_priv *priv;
519 priv = netdev_priv(dev);
521 stat = enet_readl(priv, ENET_IR_REG);
522 if (!(stat & ENET_IR_MIB))
525 /* clear & mask interrupt */
526 enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
527 enet_writel(priv, 0, ENET_IRMASK_REG);
529 /* read mib registers in workqueue */
530 schedule_work(&priv->mib_update_task);
536 * rx/tx dma interrupt handler
538 static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id)
540 struct net_device *dev;
541 struct bcm_enet_priv *priv;
544 priv = netdev_priv(dev);
546 /* mask rx/tx interrupts */
547 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
548 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
550 napi_schedule(&priv->napi);
556 * tx request callback
559 bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
561 struct bcm_enet_priv *priv;
562 struct bcm_enet_desc *desc;
566 priv = netdev_priv(dev);
568 /* lock against tx reclaim */
569 spin_lock(&priv->tx_lock);
571 /* make sure the tx hw queue is not full, should not happen
572 * since we stop queue before it's the case */
573 if (unlikely(!priv->tx_desc_count)) {
574 netif_stop_queue(dev);
575 dev_err(&priv->pdev->dev, "xmit called with no tx desc "
577 ret = NETDEV_TX_BUSY;
581 /* pad small packets sent on a switch device */
582 if (priv->enet_is_sw && skb->len < 64) {
583 int needed = 64 - skb->len;
586 if (unlikely(skb_tailroom(skb) < needed)) {
587 struct sk_buff *nskb;
589 nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC);
591 ret = NETDEV_TX_BUSY;
597 data = skb_put_zero(skb, needed);
600 /* point to the next available desc */
601 desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
602 priv->tx_skb[priv->tx_curr_desc] = skb;
604 /* fill descriptor */
605 desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
608 len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
609 len_stat |= (DMADESC_ESOP_MASK >> priv->dma_desc_shift) |
613 priv->tx_curr_desc++;
614 if (priv->tx_curr_desc == priv->tx_ring_size) {
615 priv->tx_curr_desc = 0;
616 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
618 priv->tx_desc_count--;
620 /* dma might be already polling, make sure we update desc
621 * fields in correct order */
623 desc->len_stat = len_stat;
627 enet_dmac_writel(priv, priv->dma_chan_en_mask,
628 ENETDMAC_CHANCFG, priv->tx_chan);
630 /* stop queue if no more desc available */
631 if (!priv->tx_desc_count)
632 netif_stop_queue(dev);
634 dev->stats.tx_bytes += skb->len;
635 dev->stats.tx_packets++;
639 spin_unlock(&priv->tx_lock);
644 * Change the interface's mac address.
646 static int bcm_enet_set_mac_address(struct net_device *dev, void *p)
648 struct bcm_enet_priv *priv;
649 struct sockaddr *addr = p;
652 priv = netdev_priv(dev);
653 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
655 /* use perfect match register 0 to store my mac address */
656 val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) |
657 (dev->dev_addr[4] << 8) | dev->dev_addr[5];
658 enet_writel(priv, val, ENET_PML_REG(0));
660 val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]);
661 val |= ENET_PMH_DATAVALID_MASK;
662 enet_writel(priv, val, ENET_PMH_REG(0));
668 * Change rx mode (promiscuous/allmulti) and update multicast list
670 static void bcm_enet_set_multicast_list(struct net_device *dev)
672 struct bcm_enet_priv *priv;
673 struct netdev_hw_addr *ha;
677 priv = netdev_priv(dev);
679 val = enet_readl(priv, ENET_RXCFG_REG);
681 if (dev->flags & IFF_PROMISC)
682 val |= ENET_RXCFG_PROMISC_MASK;
684 val &= ~ENET_RXCFG_PROMISC_MASK;
686 /* only 3 perfect match registers left, first one is used for
688 if ((dev->flags & IFF_ALLMULTI) || netdev_mc_count(dev) > 3)
689 val |= ENET_RXCFG_ALLMCAST_MASK;
691 val &= ~ENET_RXCFG_ALLMCAST_MASK;
693 /* no need to set perfect match registers if we catch all
695 if (val & ENET_RXCFG_ALLMCAST_MASK) {
696 enet_writel(priv, val, ENET_RXCFG_REG);
701 netdev_for_each_mc_addr(ha, dev) {
707 /* update perfect match registers */
709 tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) |
710 (dmi_addr[4] << 8) | dmi_addr[5];
711 enet_writel(priv, tmp, ENET_PML_REG(i + 1));
713 tmp = (dmi_addr[0] << 8 | dmi_addr[1]);
714 tmp |= ENET_PMH_DATAVALID_MASK;
715 enet_writel(priv, tmp, ENET_PMH_REG(i++ + 1));
719 enet_writel(priv, 0, ENET_PML_REG(i + 1));
720 enet_writel(priv, 0, ENET_PMH_REG(i + 1));
723 enet_writel(priv, val, ENET_RXCFG_REG);
727 * set mac duplex parameters
729 static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex)
733 val = enet_readl(priv, ENET_TXCTL_REG);
735 val |= ENET_TXCTL_FD_MASK;
737 val &= ~ENET_TXCTL_FD_MASK;
738 enet_writel(priv, val, ENET_TXCTL_REG);
742 * set mac flow control parameters
744 static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en)
748 /* rx flow control (pause frame handling) */
749 val = enet_readl(priv, ENET_RXCFG_REG);
751 val |= ENET_RXCFG_ENFLOW_MASK;
753 val &= ~ENET_RXCFG_ENFLOW_MASK;
754 enet_writel(priv, val, ENET_RXCFG_REG);
756 if (!priv->dma_has_sram)
759 /* tx flow control (pause frame generation) */
760 val = enet_dma_readl(priv, ENETDMA_CFG_REG);
762 val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
764 val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
765 enet_dma_writel(priv, val, ENETDMA_CFG_REG);
769 * link changed callback (from phylib)
771 static void bcm_enet_adjust_phy_link(struct net_device *dev)
773 struct bcm_enet_priv *priv;
774 struct phy_device *phydev;
777 priv = netdev_priv(dev);
778 phydev = dev->phydev;
781 if (priv->old_link != phydev->link) {
783 priv->old_link = phydev->link;
786 /* reflect duplex change in mac configuration */
787 if (phydev->link && phydev->duplex != priv->old_duplex) {
788 bcm_enet_set_duplex(priv,
789 (phydev->duplex == DUPLEX_FULL) ? 1 : 0);
791 priv->old_duplex = phydev->duplex;
794 /* enable flow control if remote advertise it (trust phylib to
795 * check that duplex is full */
796 if (phydev->link && phydev->pause != priv->old_pause) {
797 int rx_pause_en, tx_pause_en;
800 /* pause was advertised by lpa and us */
803 } else if (!priv->pause_auto) {
804 /* pause setting overridden by user */
805 rx_pause_en = priv->pause_rx;
806 tx_pause_en = priv->pause_tx;
812 bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en);
814 priv->old_pause = phydev->pause;
817 if (status_changed) {
818 pr_info("%s: link %s", dev->name, phydev->link ?
821 pr_cont(" - %d/%s - flow control %s", phydev->speed,
822 DUPLEX_FULL == phydev->duplex ? "full" : "half",
823 phydev->pause == 1 ? "rx&tx" : "off");
830 * link changed callback (if phylib is not used)
832 static void bcm_enet_adjust_link(struct net_device *dev)
834 struct bcm_enet_priv *priv;
836 priv = netdev_priv(dev);
837 bcm_enet_set_duplex(priv, priv->force_duplex_full);
838 bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx);
839 netif_carrier_on(dev);
841 pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n",
843 priv->force_speed_100 ? 100 : 10,
844 priv->force_duplex_full ? "full" : "half",
845 priv->pause_rx ? "rx" : "off",
846 priv->pause_tx ? "tx" : "off");
850 * open callback, allocate dma rings & buffers and start rx operation
852 static int bcm_enet_open(struct net_device *dev)
854 struct bcm_enet_priv *priv;
855 struct sockaddr addr;
857 struct phy_device *phydev;
860 char phy_id[MII_BUS_ID_SIZE + 3];
864 priv = netdev_priv(dev);
865 kdev = &priv->pdev->dev;
869 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
870 priv->mii_bus->id, priv->phy_id);
872 phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link,
873 PHY_INTERFACE_MODE_MII);
875 if (IS_ERR(phydev)) {
876 dev_err(kdev, "could not attach to PHY\n");
877 return PTR_ERR(phydev);
880 /* mask with MAC supported features */
881 phy_support_sym_pause(phydev);
882 phy_set_max_speed(phydev, SPEED_100);
883 phy_set_sym_pause(phydev, priv->pause_rx, priv->pause_rx,
886 phy_attached_info(phydev);
889 priv->old_duplex = -1;
890 priv->old_pause = -1;
895 /* mask all interrupts and request them */
896 enet_writel(priv, 0, ENET_IRMASK_REG);
897 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
898 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
900 ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
902 goto out_phy_disconnect;
904 ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, 0,
909 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
914 /* initialize perfect match registers */
915 for (i = 0; i < 4; i++) {
916 enet_writel(priv, 0, ENET_PML_REG(i));
917 enet_writel(priv, 0, ENET_PMH_REG(i));
920 /* write device mac address */
921 memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN);
922 bcm_enet_set_mac_address(dev, &addr);
924 /* allocate rx dma ring */
925 size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
926 p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
932 priv->rx_desc_alloc_size = size;
933 priv->rx_desc_cpu = p;
935 /* allocate tx dma ring */
936 size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
937 p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
940 goto out_free_rx_ring;
943 priv->tx_desc_alloc_size = size;
944 priv->tx_desc_cpu = p;
946 priv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *),
950 goto out_free_tx_ring;
953 priv->tx_desc_count = priv->tx_ring_size;
954 priv->tx_dirty_desc = 0;
955 priv->tx_curr_desc = 0;
956 spin_lock_init(&priv->tx_lock);
958 /* init & fill rx ring with skbs */
959 priv->rx_skb = kcalloc(priv->rx_ring_size, sizeof(struct sk_buff *),
963 goto out_free_tx_skb;
966 priv->rx_desc_count = 0;
967 priv->rx_dirty_desc = 0;
968 priv->rx_curr_desc = 0;
970 /* initialize flow control buffer allocation */
971 if (priv->dma_has_sram)
972 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
973 ENETDMA_BUFALLOC_REG(priv->rx_chan));
975 enet_dmac_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
976 ENETDMAC_BUFALLOC, priv->rx_chan);
978 if (bcm_enet_refill_rx(dev)) {
979 dev_err(kdev, "cannot allocate rx skb queue\n");
984 /* write rx & tx ring addresses */
985 if (priv->dma_has_sram) {
986 enet_dmas_writel(priv, priv->rx_desc_dma,
987 ENETDMAS_RSTART_REG, priv->rx_chan);
988 enet_dmas_writel(priv, priv->tx_desc_dma,
989 ENETDMAS_RSTART_REG, priv->tx_chan);
991 enet_dmac_writel(priv, priv->rx_desc_dma,
992 ENETDMAC_RSTART, priv->rx_chan);
993 enet_dmac_writel(priv, priv->tx_desc_dma,
994 ENETDMAC_RSTART, priv->tx_chan);
997 /* clear remaining state ram for rx & tx channel */
998 if (priv->dma_has_sram) {
999 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
1000 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
1001 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
1002 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
1003 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
1004 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
1006 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->rx_chan);
1007 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->tx_chan);
1010 /* set max rx/tx length */
1011 enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
1012 enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
1014 /* set dma maximum burst len */
1015 enet_dmac_writel(priv, priv->dma_maxburst,
1016 ENETDMAC_MAXBURST, priv->rx_chan);
1017 enet_dmac_writel(priv, priv->dma_maxburst,
1018 ENETDMAC_MAXBURST, priv->tx_chan);
1020 /* set correct transmit fifo watermark */
1021 enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
1023 /* set flow control low/high threshold to 1/3 / 2/3 */
1024 if (priv->dma_has_sram) {
1025 val = priv->rx_ring_size / 3;
1026 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
1027 val = (priv->rx_ring_size * 2) / 3;
1028 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
1030 enet_dmac_writel(priv, 5, ENETDMAC_FC, priv->rx_chan);
1031 enet_dmac_writel(priv, priv->rx_ring_size, ENETDMAC_LEN, priv->rx_chan);
1032 enet_dmac_writel(priv, priv->tx_ring_size, ENETDMAC_LEN, priv->tx_chan);
1035 /* all set, enable mac and interrupts, start dma engine and
1036 * kick rx dma channel */
1038 val = enet_readl(priv, ENET_CTL_REG);
1039 val |= ENET_CTL_ENABLE_MASK;
1040 enet_writel(priv, val, ENET_CTL_REG);
1041 if (priv->dma_has_sram)
1042 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
1043 enet_dmac_writel(priv, priv->dma_chan_en_mask,
1044 ENETDMAC_CHANCFG, priv->rx_chan);
1046 /* watch "mib counters about to overflow" interrupt */
1047 enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
1048 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1050 /* watch "packet transferred" interrupt in rx and tx */
1051 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1052 ENETDMAC_IR, priv->rx_chan);
1053 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1054 ENETDMAC_IR, priv->tx_chan);
1056 /* make sure we enable napi before rx interrupt */
1057 napi_enable(&priv->napi);
1059 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1060 ENETDMAC_IRMASK, priv->rx_chan);
1061 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1062 ENETDMAC_IRMASK, priv->tx_chan);
1067 bcm_enet_adjust_link(dev);
1069 netif_start_queue(dev);
1073 for (i = 0; i < priv->rx_ring_size; i++) {
1074 struct bcm_enet_desc *desc;
1076 if (!priv->rx_skb[i])
1079 desc = &priv->rx_desc_cpu[i];
1080 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1082 kfree_skb(priv->rx_skb[i]);
1084 kfree(priv->rx_skb);
1087 kfree(priv->tx_skb);
1090 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1091 priv->tx_desc_cpu, priv->tx_desc_dma);
1094 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1095 priv->rx_desc_cpu, priv->rx_desc_dma);
1098 free_irq(priv->irq_tx, dev);
1101 free_irq(priv->irq_rx, dev);
1104 free_irq(dev->irq, dev);
1108 phy_disconnect(phydev);
1116 static void bcm_enet_disable_mac(struct bcm_enet_priv *priv)
1121 val = enet_readl(priv, ENET_CTL_REG);
1122 val |= ENET_CTL_DISABLE_MASK;
1123 enet_writel(priv, val, ENET_CTL_REG);
1129 val = enet_readl(priv, ENET_CTL_REG);
1130 if (!(val & ENET_CTL_DISABLE_MASK))
1137 * disable dma in given channel
1139 static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan)
1143 enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG, chan);
1149 val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan);
1150 if (!(val & ENETDMAC_CHANCFG_EN_MASK))
1159 static int bcm_enet_stop(struct net_device *dev)
1161 struct bcm_enet_priv *priv;
1162 struct device *kdev;
1165 priv = netdev_priv(dev);
1166 kdev = &priv->pdev->dev;
1168 netif_stop_queue(dev);
1169 napi_disable(&priv->napi);
1171 phy_stop(dev->phydev);
1172 del_timer_sync(&priv->rx_timeout);
1174 /* mask all interrupts */
1175 enet_writel(priv, 0, ENET_IRMASK_REG);
1176 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
1177 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
1179 /* make sure no mib update is scheduled */
1180 cancel_work_sync(&priv->mib_update_task);
1182 /* disable dma & mac */
1183 bcm_enet_disable_dma(priv, priv->tx_chan);
1184 bcm_enet_disable_dma(priv, priv->rx_chan);
1185 bcm_enet_disable_mac(priv);
1187 /* force reclaim of all tx buffers */
1188 bcm_enet_tx_reclaim(dev, 1);
1190 /* free the rx skb ring */
1191 for (i = 0; i < priv->rx_ring_size; i++) {
1192 struct bcm_enet_desc *desc;
1194 if (!priv->rx_skb[i])
1197 desc = &priv->rx_desc_cpu[i];
1198 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1200 kfree_skb(priv->rx_skb[i]);
1203 /* free remaining allocated memory */
1204 kfree(priv->rx_skb);
1205 kfree(priv->tx_skb);
1206 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1207 priv->rx_desc_cpu, priv->rx_desc_dma);
1208 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1209 priv->tx_desc_cpu, priv->tx_desc_dma);
1210 free_irq(priv->irq_tx, dev);
1211 free_irq(priv->irq_rx, dev);
1212 free_irq(dev->irq, dev);
1216 phy_disconnect(dev->phydev);
1224 struct bcm_enet_stats {
1225 char stat_string[ETH_GSTRING_LEN];
1231 #define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m), \
1232 offsetof(struct bcm_enet_priv, m)
1233 #define DEV_STAT(m) sizeof(((struct net_device_stats *)0)->m), \
1234 offsetof(struct net_device_stats, m)
1236 static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = {
1237 { "rx_packets", DEV_STAT(rx_packets), -1 },
1238 { "tx_packets", DEV_STAT(tx_packets), -1 },
1239 { "rx_bytes", DEV_STAT(rx_bytes), -1 },
1240 { "tx_bytes", DEV_STAT(tx_bytes), -1 },
1241 { "rx_errors", DEV_STAT(rx_errors), -1 },
1242 { "tx_errors", DEV_STAT(tx_errors), -1 },
1243 { "rx_dropped", DEV_STAT(rx_dropped), -1 },
1244 { "tx_dropped", DEV_STAT(tx_dropped), -1 },
1246 { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS},
1247 { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS },
1248 { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST },
1249 { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT },
1250 { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 },
1251 { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 },
1252 { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 },
1253 { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 },
1254 { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 },
1255 { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX },
1256 { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB },
1257 { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR },
1258 { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG },
1259 { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP },
1260 { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN },
1261 { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND },
1262 { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC },
1263 { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN },
1264 { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM },
1265 { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE },
1266 { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL },
1268 { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS },
1269 { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS },
1270 { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST },
1271 { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT },
1272 { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 },
1273 { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 },
1274 { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 },
1275 { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 },
1276 { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023},
1277 { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX },
1278 { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB },
1279 { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR },
1280 { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG },
1281 { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN },
1282 { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL },
1283 { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL },
1284 { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL },
1285 { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL },
1286 { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE },
1287 { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF },
1288 { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS },
1289 { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE },
1293 #define BCM_ENET_STATS_LEN ARRAY_SIZE(bcm_enet_gstrings_stats)
1295 static const u32 unused_mib_regs[] = {
1296 ETH_MIB_TX_ALL_OCTETS,
1297 ETH_MIB_TX_ALL_PKTS,
1298 ETH_MIB_RX_ALL_OCTETS,
1299 ETH_MIB_RX_ALL_PKTS,
1303 static void bcm_enet_get_drvinfo(struct net_device *netdev,
1304 struct ethtool_drvinfo *drvinfo)
1306 strlcpy(drvinfo->driver, bcm_enet_driver_name, sizeof(drvinfo->driver));
1307 strlcpy(drvinfo->version, bcm_enet_driver_version,
1308 sizeof(drvinfo->version));
1309 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1310 strlcpy(drvinfo->bus_info, "bcm63xx", sizeof(drvinfo->bus_info));
1313 static int bcm_enet_get_sset_count(struct net_device *netdev,
1316 switch (string_set) {
1318 return BCM_ENET_STATS_LEN;
1324 static void bcm_enet_get_strings(struct net_device *netdev,
1325 u32 stringset, u8 *data)
1329 switch (stringset) {
1331 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1332 memcpy(data + i * ETH_GSTRING_LEN,
1333 bcm_enet_gstrings_stats[i].stat_string,
1340 static void update_mib_counters(struct bcm_enet_priv *priv)
1344 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1345 const struct bcm_enet_stats *s;
1349 s = &bcm_enet_gstrings_stats[i];
1350 if (s->mib_reg == -1)
1353 val = enet_readl(priv, ENET_MIB_REG(s->mib_reg));
1354 p = (char *)priv + s->stat_offset;
1356 if (s->sizeof_stat == sizeof(u64))
1362 /* also empty unused mib counters to make sure mib counter
1363 * overflow interrupt is cleared */
1364 for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++)
1365 (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i]));
1368 static void bcm_enet_update_mib_counters_defer(struct work_struct *t)
1370 struct bcm_enet_priv *priv;
1372 priv = container_of(t, struct bcm_enet_priv, mib_update_task);
1373 mutex_lock(&priv->mib_update_lock);
1374 update_mib_counters(priv);
1375 mutex_unlock(&priv->mib_update_lock);
1377 /* reenable mib interrupt */
1378 if (netif_running(priv->net_dev))
1379 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1382 static void bcm_enet_get_ethtool_stats(struct net_device *netdev,
1383 struct ethtool_stats *stats,
1386 struct bcm_enet_priv *priv;
1389 priv = netdev_priv(netdev);
1391 mutex_lock(&priv->mib_update_lock);
1392 update_mib_counters(priv);
1394 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1395 const struct bcm_enet_stats *s;
1398 s = &bcm_enet_gstrings_stats[i];
1399 if (s->mib_reg == -1)
1400 p = (char *)&netdev->stats;
1403 p += s->stat_offset;
1404 data[i] = (s->sizeof_stat == sizeof(u64)) ?
1405 *(u64 *)p : *(u32 *)p;
1407 mutex_unlock(&priv->mib_update_lock);
1410 static int bcm_enet_nway_reset(struct net_device *dev)
1412 struct bcm_enet_priv *priv;
1414 priv = netdev_priv(dev);
1416 return phy_ethtool_nway_reset(dev);
1421 static int bcm_enet_get_link_ksettings(struct net_device *dev,
1422 struct ethtool_link_ksettings *cmd)
1424 struct bcm_enet_priv *priv;
1425 u32 supported, advertising;
1427 priv = netdev_priv(dev);
1429 if (priv->has_phy) {
1433 phy_ethtool_ksettings_get(dev->phydev, cmd);
1437 cmd->base.autoneg = 0;
1438 cmd->base.speed = (priv->force_speed_100) ?
1439 SPEED_100 : SPEED_10;
1440 cmd->base.duplex = (priv->force_duplex_full) ?
1441 DUPLEX_FULL : DUPLEX_HALF;
1442 supported = ADVERTISED_10baseT_Half |
1443 ADVERTISED_10baseT_Full |
1444 ADVERTISED_100baseT_Half |
1445 ADVERTISED_100baseT_Full;
1447 ethtool_convert_legacy_u32_to_link_mode(
1448 cmd->link_modes.supported, supported);
1449 ethtool_convert_legacy_u32_to_link_mode(
1450 cmd->link_modes.advertising, advertising);
1451 cmd->base.port = PORT_MII;
1456 static int bcm_enet_set_link_ksettings(struct net_device *dev,
1457 const struct ethtool_link_ksettings *cmd)
1459 struct bcm_enet_priv *priv;
1461 priv = netdev_priv(dev);
1462 if (priv->has_phy) {
1465 return phy_ethtool_ksettings_set(dev->phydev, cmd);
1468 if (cmd->base.autoneg ||
1469 (cmd->base.speed != SPEED_100 &&
1470 cmd->base.speed != SPEED_10) ||
1471 cmd->base.port != PORT_MII)
1474 priv->force_speed_100 =
1475 (cmd->base.speed == SPEED_100) ? 1 : 0;
1476 priv->force_duplex_full =
1477 (cmd->base.duplex == DUPLEX_FULL) ? 1 : 0;
1479 if (netif_running(dev))
1480 bcm_enet_adjust_link(dev);
1485 static void bcm_enet_get_ringparam(struct net_device *dev,
1486 struct ethtool_ringparam *ering)
1488 struct bcm_enet_priv *priv;
1490 priv = netdev_priv(dev);
1492 /* rx/tx ring is actually only limited by memory */
1493 ering->rx_max_pending = 8192;
1494 ering->tx_max_pending = 8192;
1495 ering->rx_pending = priv->rx_ring_size;
1496 ering->tx_pending = priv->tx_ring_size;
1499 static int bcm_enet_set_ringparam(struct net_device *dev,
1500 struct ethtool_ringparam *ering)
1502 struct bcm_enet_priv *priv;
1505 priv = netdev_priv(dev);
1508 if (netif_running(dev)) {
1513 priv->rx_ring_size = ering->rx_pending;
1514 priv->tx_ring_size = ering->tx_pending;
1519 err = bcm_enet_open(dev);
1523 bcm_enet_set_multicast_list(dev);
1528 static void bcm_enet_get_pauseparam(struct net_device *dev,
1529 struct ethtool_pauseparam *ecmd)
1531 struct bcm_enet_priv *priv;
1533 priv = netdev_priv(dev);
1534 ecmd->autoneg = priv->pause_auto;
1535 ecmd->rx_pause = priv->pause_rx;
1536 ecmd->tx_pause = priv->pause_tx;
1539 static int bcm_enet_set_pauseparam(struct net_device *dev,
1540 struct ethtool_pauseparam *ecmd)
1542 struct bcm_enet_priv *priv;
1544 priv = netdev_priv(dev);
1546 if (priv->has_phy) {
1547 if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) {
1548 /* asymetric pause mode not supported,
1549 * actually possible but integrated PHY has RO
1554 /* no pause autoneg on direct mii connection */
1559 priv->pause_auto = ecmd->autoneg;
1560 priv->pause_rx = ecmd->rx_pause;
1561 priv->pause_tx = ecmd->tx_pause;
1566 static const struct ethtool_ops bcm_enet_ethtool_ops = {
1567 .get_strings = bcm_enet_get_strings,
1568 .get_sset_count = bcm_enet_get_sset_count,
1569 .get_ethtool_stats = bcm_enet_get_ethtool_stats,
1570 .nway_reset = bcm_enet_nway_reset,
1571 .get_drvinfo = bcm_enet_get_drvinfo,
1572 .get_link = ethtool_op_get_link,
1573 .get_ringparam = bcm_enet_get_ringparam,
1574 .set_ringparam = bcm_enet_set_ringparam,
1575 .get_pauseparam = bcm_enet_get_pauseparam,
1576 .set_pauseparam = bcm_enet_set_pauseparam,
1577 .get_link_ksettings = bcm_enet_get_link_ksettings,
1578 .set_link_ksettings = bcm_enet_set_link_ksettings,
1581 static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1583 struct bcm_enet_priv *priv;
1585 priv = netdev_priv(dev);
1586 if (priv->has_phy) {
1589 return phy_mii_ioctl(dev->phydev, rq, cmd);
1591 struct mii_if_info mii;
1594 mii.mdio_read = bcm_enet_mdio_read_mii;
1595 mii.mdio_write = bcm_enet_mdio_write_mii;
1597 mii.phy_id_mask = 0x3f;
1598 mii.reg_num_mask = 0x1f;
1599 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
1604 * adjust mtu, can't be called while device is running
1606 static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu)
1608 struct bcm_enet_priv *priv = netdev_priv(dev);
1609 int actual_mtu = new_mtu;
1611 if (netif_running(dev))
1614 /* add ethernet header + vlan tag size */
1615 actual_mtu += VLAN_ETH_HLEN;
1618 * setup maximum size before we get overflow mark in
1619 * descriptor, note that this will not prevent reception of
1620 * big frames, they will be split into multiple buffers
1623 priv->hw_mtu = actual_mtu;
1626 * align rx buffer size to dma burst len, account FCS since
1629 priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN,
1630 priv->dma_maxburst * 4);
1637 * preinit hardware to allow mii operation while device is down
1639 static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv)
1644 /* make sure mac is disabled */
1645 bcm_enet_disable_mac(priv);
1647 /* soft reset mac */
1648 val = ENET_CTL_SRESET_MASK;
1649 enet_writel(priv, val, ENET_CTL_REG);
1654 val = enet_readl(priv, ENET_CTL_REG);
1655 if (!(val & ENET_CTL_SRESET_MASK))
1660 /* select correct mii interface */
1661 val = enet_readl(priv, ENET_CTL_REG);
1662 if (priv->use_external_mii)
1663 val |= ENET_CTL_EPHYSEL_MASK;
1665 val &= ~ENET_CTL_EPHYSEL_MASK;
1666 enet_writel(priv, val, ENET_CTL_REG);
1668 /* turn on mdc clock */
1669 enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) |
1670 ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG);
1672 /* set mib counters to self-clear when read */
1673 val = enet_readl(priv, ENET_MIBCTL_REG);
1674 val |= ENET_MIBCTL_RDCLEAR_MASK;
1675 enet_writel(priv, val, ENET_MIBCTL_REG);
1678 static const struct net_device_ops bcm_enet_ops = {
1679 .ndo_open = bcm_enet_open,
1680 .ndo_stop = bcm_enet_stop,
1681 .ndo_start_xmit = bcm_enet_start_xmit,
1682 .ndo_set_mac_address = bcm_enet_set_mac_address,
1683 .ndo_set_rx_mode = bcm_enet_set_multicast_list,
1684 .ndo_do_ioctl = bcm_enet_ioctl,
1685 .ndo_change_mtu = bcm_enet_change_mtu,
1689 * allocate netdevice, request register memory and register device.
1691 static int bcm_enet_probe(struct platform_device *pdev)
1693 struct bcm_enet_priv *priv;
1694 struct net_device *dev;
1695 struct bcm63xx_enet_platform_data *pd;
1696 struct resource *res_irq, *res_irq_rx, *res_irq_tx;
1697 struct mii_bus *bus;
1700 if (!bcm_enet_shared_base[0])
1701 return -EPROBE_DEFER;
1703 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1704 res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1705 res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
1706 if (!res_irq || !res_irq_rx || !res_irq_tx)
1710 dev = alloc_etherdev(sizeof(*priv));
1713 priv = netdev_priv(dev);
1715 priv->enet_is_sw = false;
1716 priv->dma_maxburst = BCMENET_DMA_MAXBURST;
1718 ret = bcm_enet_change_mtu(dev, dev->mtu);
1722 priv->base = devm_platform_ioremap_resource(pdev, 0);
1723 if (IS_ERR(priv->base)) {
1724 ret = PTR_ERR(priv->base);
1728 dev->irq = priv->irq = res_irq->start;
1729 priv->irq_rx = res_irq_rx->start;
1730 priv->irq_tx = res_irq_tx->start;
1732 priv->mac_clk = devm_clk_get(&pdev->dev, "enet");
1733 if (IS_ERR(priv->mac_clk)) {
1734 ret = PTR_ERR(priv->mac_clk);
1737 ret = clk_prepare_enable(priv->mac_clk);
1741 /* initialize default and fetch platform data */
1742 priv->rx_ring_size = BCMENET_DEF_RX_DESC;
1743 priv->tx_ring_size = BCMENET_DEF_TX_DESC;
1745 pd = dev_get_platdata(&pdev->dev);
1747 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
1748 priv->has_phy = pd->has_phy;
1749 priv->phy_id = pd->phy_id;
1750 priv->has_phy_interrupt = pd->has_phy_interrupt;
1751 priv->phy_interrupt = pd->phy_interrupt;
1752 priv->use_external_mii = !pd->use_internal_phy;
1753 priv->pause_auto = pd->pause_auto;
1754 priv->pause_rx = pd->pause_rx;
1755 priv->pause_tx = pd->pause_tx;
1756 priv->force_duplex_full = pd->force_duplex_full;
1757 priv->force_speed_100 = pd->force_speed_100;
1758 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
1759 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
1760 priv->dma_chan_width = pd->dma_chan_width;
1761 priv->dma_has_sram = pd->dma_has_sram;
1762 priv->dma_desc_shift = pd->dma_desc_shift;
1763 priv->rx_chan = pd->rx_chan;
1764 priv->tx_chan = pd->tx_chan;
1767 if (priv->has_phy && !priv->use_external_mii) {
1768 /* using internal PHY, enable clock */
1769 priv->phy_clk = devm_clk_get(&pdev->dev, "ephy");
1770 if (IS_ERR(priv->phy_clk)) {
1771 ret = PTR_ERR(priv->phy_clk);
1772 priv->phy_clk = NULL;
1773 goto out_disable_clk_mac;
1775 ret = clk_prepare_enable(priv->phy_clk);
1777 goto out_disable_clk_mac;
1780 /* do minimal hardware init to be able to probe mii bus */
1781 bcm_enet_hw_preinit(priv);
1783 /* MII bus registration */
1784 if (priv->has_phy) {
1786 priv->mii_bus = mdiobus_alloc();
1787 if (!priv->mii_bus) {
1792 bus = priv->mii_bus;
1793 bus->name = "bcm63xx_enet MII bus";
1794 bus->parent = &pdev->dev;
1796 bus->read = bcm_enet_mdio_read_phylib;
1797 bus->write = bcm_enet_mdio_write_phylib;
1798 sprintf(bus->id, "%s-%d", pdev->name, pdev->id);
1800 /* only probe bus where we think the PHY is, because
1801 * the mdio read operation return 0 instead of 0xffff
1802 * if a slave is not present on hw */
1803 bus->phy_mask = ~(1 << priv->phy_id);
1805 if (priv->has_phy_interrupt)
1806 bus->irq[priv->phy_id] = priv->phy_interrupt;
1808 ret = mdiobus_register(bus);
1810 dev_err(&pdev->dev, "unable to register mdio bus\n");
1815 /* run platform code to initialize PHY device */
1816 if (pd && pd->mii_config &&
1817 pd->mii_config(dev, 1, bcm_enet_mdio_read_mii,
1818 bcm_enet_mdio_write_mii)) {
1819 dev_err(&pdev->dev, "unable to configure mdio bus\n");
1824 spin_lock_init(&priv->rx_lock);
1826 /* init rx timeout (used for oom) */
1827 timer_setup(&priv->rx_timeout, bcm_enet_refill_rx_timer, 0);
1829 /* init the mib update lock&work */
1830 mutex_init(&priv->mib_update_lock);
1831 INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer);
1833 /* zero mib counters */
1834 for (i = 0; i < ENET_MIB_REG_COUNT; i++)
1835 enet_writel(priv, 0, ENET_MIB_REG(i));
1837 /* register netdevice */
1838 dev->netdev_ops = &bcm_enet_ops;
1839 netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
1841 dev->ethtool_ops = &bcm_enet_ethtool_ops;
1842 /* MTU range: 46 - 2028 */
1843 dev->min_mtu = ETH_ZLEN - ETH_HLEN;
1844 dev->max_mtu = BCMENET_MAX_MTU - VLAN_ETH_HLEN;
1845 SET_NETDEV_DEV(dev, &pdev->dev);
1847 ret = register_netdev(dev);
1849 goto out_unregister_mdio;
1851 netif_carrier_off(dev);
1852 platform_set_drvdata(pdev, dev);
1854 priv->net_dev = dev;
1858 out_unregister_mdio:
1860 mdiobus_unregister(priv->mii_bus);
1864 mdiobus_free(priv->mii_bus);
1867 /* turn off mdc clock */
1868 enet_writel(priv, 0, ENET_MIISC_REG);
1869 clk_disable_unprepare(priv->phy_clk);
1871 out_disable_clk_mac:
1872 clk_disable_unprepare(priv->mac_clk);
1880 * exit func, stops hardware and unregisters netdevice
1882 static int bcm_enet_remove(struct platform_device *pdev)
1884 struct bcm_enet_priv *priv;
1885 struct net_device *dev;
1887 /* stop netdevice */
1888 dev = platform_get_drvdata(pdev);
1889 priv = netdev_priv(dev);
1890 unregister_netdev(dev);
1892 /* turn off mdc clock */
1893 enet_writel(priv, 0, ENET_MIISC_REG);
1895 if (priv->has_phy) {
1896 mdiobus_unregister(priv->mii_bus);
1897 mdiobus_free(priv->mii_bus);
1899 struct bcm63xx_enet_platform_data *pd;
1901 pd = dev_get_platdata(&pdev->dev);
1902 if (pd && pd->mii_config)
1903 pd->mii_config(dev, 0, bcm_enet_mdio_read_mii,
1904 bcm_enet_mdio_write_mii);
1907 /* disable hw block clocks */
1908 clk_disable_unprepare(priv->phy_clk);
1909 clk_disable_unprepare(priv->mac_clk);
1915 struct platform_driver bcm63xx_enet_driver = {
1916 .probe = bcm_enet_probe,
1917 .remove = bcm_enet_remove,
1919 .name = "bcm63xx_enet",
1920 .owner = THIS_MODULE,
1925 * switch mii access callbacks
1927 static int bcmenet_sw_mdio_read(struct bcm_enet_priv *priv,
1928 int ext, int phy_id, int location)
1933 spin_lock_bh(&priv->enetsw_mdio_lock);
1934 enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
1936 reg = ENETSW_MDIOC_RD_MASK |
1937 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
1938 (location << ENETSW_MDIOC_REG_SHIFT);
1941 reg |= ENETSW_MDIOC_EXT_MASK;
1943 enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
1945 ret = enetsw_readw(priv, ENETSW_MDIOD_REG);
1946 spin_unlock_bh(&priv->enetsw_mdio_lock);
1950 static void bcmenet_sw_mdio_write(struct bcm_enet_priv *priv,
1951 int ext, int phy_id, int location,
1956 spin_lock_bh(&priv->enetsw_mdio_lock);
1957 enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
1959 reg = ENETSW_MDIOC_WR_MASK |
1960 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
1961 (location << ENETSW_MDIOC_REG_SHIFT);
1964 reg |= ENETSW_MDIOC_EXT_MASK;
1968 enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
1970 spin_unlock_bh(&priv->enetsw_mdio_lock);
1973 static inline int bcm_enet_port_is_rgmii(int portid)
1975 return portid >= ENETSW_RGMII_PORT0;
1979 * enet sw PHY polling
1981 static void swphy_poll_timer(struct timer_list *t)
1983 struct bcm_enet_priv *priv = from_timer(priv, t, swphy_poll);
1986 for (i = 0; i < priv->num_ports; i++) {
1987 struct bcm63xx_enetsw_port *port;
1988 int val, j, up, advertise, lpa, speed, duplex, media;
1989 int external_phy = bcm_enet_port_is_rgmii(i);
1992 port = &priv->used_ports[i];
1996 if (port->bypass_link)
1999 /* dummy read to clear */
2000 for (j = 0; j < 2; j++)
2001 val = bcmenet_sw_mdio_read(priv, external_phy,
2002 port->phy_id, MII_BMSR);
2007 up = (val & BMSR_LSTATUS) ? 1 : 0;
2008 if (!(up ^ priv->sw_port_link[i]))
2011 priv->sw_port_link[i] = up;
2015 dev_info(&priv->pdev->dev, "link DOWN on %s\n",
2017 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2018 ENETSW_PORTOV_REG(i));
2019 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2020 ENETSW_PTCTRL_TXDIS_MASK,
2021 ENETSW_PTCTRL_REG(i));
2025 advertise = bcmenet_sw_mdio_read(priv, external_phy,
2026 port->phy_id, MII_ADVERTISE);
2028 lpa = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id,
2031 /* figure out media and duplex from advertise and LPA values */
2032 media = mii_nway_result(lpa & advertise);
2033 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
2035 if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF))
2040 if (val & BMSR_ESTATEN) {
2041 advertise = bcmenet_sw_mdio_read(priv, external_phy,
2042 port->phy_id, MII_CTRL1000);
2044 lpa = bcmenet_sw_mdio_read(priv, external_phy,
2045 port->phy_id, MII_STAT1000);
2047 if (advertise & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)
2048 && lpa & (LPA_1000FULL | LPA_1000HALF)) {
2050 duplex = (lpa & LPA_1000FULL);
2054 dev_info(&priv->pdev->dev,
2055 "link UP on %s, %dMbps, %s-duplex\n",
2056 port->name, speed, duplex ? "full" : "half");
2058 override = ENETSW_PORTOV_ENABLE_MASK |
2059 ENETSW_PORTOV_LINKUP_MASK;
2062 override |= ENETSW_IMPOV_1000_MASK;
2063 else if (speed == 100)
2064 override |= ENETSW_IMPOV_100_MASK;
2066 override |= ENETSW_IMPOV_FDX_MASK;
2068 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2069 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2072 priv->swphy_poll.expires = jiffies + HZ;
2073 add_timer(&priv->swphy_poll);
2077 * open callback, allocate dma rings & buffers and start rx operation
2079 static int bcm_enetsw_open(struct net_device *dev)
2081 struct bcm_enet_priv *priv;
2082 struct device *kdev;
2088 priv = netdev_priv(dev);
2089 kdev = &priv->pdev->dev;
2091 /* mask all interrupts and request them */
2092 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2093 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2095 ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
2100 if (priv->irq_tx != -1) {
2101 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
2104 goto out_freeirq_rx;
2107 /* allocate rx dma ring */
2108 size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
2109 p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
2111 dev_err(kdev, "cannot allocate rx ring %u\n", size);
2113 goto out_freeirq_tx;
2116 priv->rx_desc_alloc_size = size;
2117 priv->rx_desc_cpu = p;
2119 /* allocate tx dma ring */
2120 size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
2121 p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
2123 dev_err(kdev, "cannot allocate tx ring\n");
2125 goto out_free_rx_ring;
2128 priv->tx_desc_alloc_size = size;
2129 priv->tx_desc_cpu = p;
2131 priv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *),
2133 if (!priv->tx_skb) {
2134 dev_err(kdev, "cannot allocate rx skb queue\n");
2136 goto out_free_tx_ring;
2139 priv->tx_desc_count = priv->tx_ring_size;
2140 priv->tx_dirty_desc = 0;
2141 priv->tx_curr_desc = 0;
2142 spin_lock_init(&priv->tx_lock);
2144 /* init & fill rx ring with skbs */
2145 priv->rx_skb = kcalloc(priv->rx_ring_size, sizeof(struct sk_buff *),
2147 if (!priv->rx_skb) {
2148 dev_err(kdev, "cannot allocate rx skb queue\n");
2150 goto out_free_tx_skb;
2153 priv->rx_desc_count = 0;
2154 priv->rx_dirty_desc = 0;
2155 priv->rx_curr_desc = 0;
2157 /* disable all ports */
2158 for (i = 0; i < priv->num_ports; i++) {
2159 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2160 ENETSW_PORTOV_REG(i));
2161 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2162 ENETSW_PTCTRL_TXDIS_MASK,
2163 ENETSW_PTCTRL_REG(i));
2165 priv->sw_port_link[i] = 0;
2169 val = enetsw_readb(priv, ENETSW_GMCR_REG);
2170 val |= ENETSW_GMCR_RST_MIB_MASK;
2171 enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2173 val &= ~ENETSW_GMCR_RST_MIB_MASK;
2174 enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2177 /* force CPU port state */
2178 val = enetsw_readb(priv, ENETSW_IMPOV_REG);
2179 val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK;
2180 enetsw_writeb(priv, val, ENETSW_IMPOV_REG);
2182 /* enable switch forward engine */
2183 val = enetsw_readb(priv, ENETSW_SWMODE_REG);
2184 val |= ENETSW_SWMODE_FWD_EN_MASK;
2185 enetsw_writeb(priv, val, ENETSW_SWMODE_REG);
2187 /* enable jumbo on all ports */
2188 enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG);
2189 enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG);
2191 /* initialize flow control buffer allocation */
2192 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
2193 ENETDMA_BUFALLOC_REG(priv->rx_chan));
2195 if (bcm_enet_refill_rx(dev)) {
2196 dev_err(kdev, "cannot allocate rx skb queue\n");
2201 /* write rx & tx ring addresses */
2202 enet_dmas_writel(priv, priv->rx_desc_dma,
2203 ENETDMAS_RSTART_REG, priv->rx_chan);
2204 enet_dmas_writel(priv, priv->tx_desc_dma,
2205 ENETDMAS_RSTART_REG, priv->tx_chan);
2207 /* clear remaining state ram for rx & tx channel */
2208 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
2209 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
2210 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
2211 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
2212 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
2213 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
2215 /* set dma maximum burst len */
2216 enet_dmac_writel(priv, priv->dma_maxburst,
2217 ENETDMAC_MAXBURST, priv->rx_chan);
2218 enet_dmac_writel(priv, priv->dma_maxburst,
2219 ENETDMAC_MAXBURST, priv->tx_chan);
2221 /* set flow control low/high threshold to 1/3 / 2/3 */
2222 val = priv->rx_ring_size / 3;
2223 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
2224 val = (priv->rx_ring_size * 2) / 3;
2225 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
2227 /* all set, enable mac and interrupts, start dma engine and
2228 * kick rx dma channel
2231 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
2232 enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
2233 ENETDMAC_CHANCFG, priv->rx_chan);
2235 /* watch "packet transferred" interrupt in rx and tx */
2236 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2237 ENETDMAC_IR, priv->rx_chan);
2238 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2239 ENETDMAC_IR, priv->tx_chan);
2241 /* make sure we enable napi before rx interrupt */
2242 napi_enable(&priv->napi);
2244 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2245 ENETDMAC_IRMASK, priv->rx_chan);
2246 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2247 ENETDMAC_IRMASK, priv->tx_chan);
2249 netif_carrier_on(dev);
2250 netif_start_queue(dev);
2252 /* apply override config for bypass_link ports here. */
2253 for (i = 0; i < priv->num_ports; i++) {
2254 struct bcm63xx_enetsw_port *port;
2256 port = &priv->used_ports[i];
2260 if (!port->bypass_link)
2263 override = ENETSW_PORTOV_ENABLE_MASK |
2264 ENETSW_PORTOV_LINKUP_MASK;
2266 switch (port->force_speed) {
2268 override |= ENETSW_IMPOV_1000_MASK;
2271 override |= ENETSW_IMPOV_100_MASK;
2276 pr_warn("invalid forced speed on port %s: assume 10\n",
2281 if (port->force_duplex_full)
2282 override |= ENETSW_IMPOV_FDX_MASK;
2285 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2286 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2289 /* start phy polling timer */
2290 timer_setup(&priv->swphy_poll, swphy_poll_timer, 0);
2291 mod_timer(&priv->swphy_poll, jiffies);
2295 for (i = 0; i < priv->rx_ring_size; i++) {
2296 struct bcm_enet_desc *desc;
2298 if (!priv->rx_skb[i])
2301 desc = &priv->rx_desc_cpu[i];
2302 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2304 kfree_skb(priv->rx_skb[i]);
2306 kfree(priv->rx_skb);
2309 kfree(priv->tx_skb);
2312 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2313 priv->tx_desc_cpu, priv->tx_desc_dma);
2316 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2317 priv->rx_desc_cpu, priv->rx_desc_dma);
2320 if (priv->irq_tx != -1)
2321 free_irq(priv->irq_tx, dev);
2324 free_irq(priv->irq_rx, dev);
2331 static int bcm_enetsw_stop(struct net_device *dev)
2333 struct bcm_enet_priv *priv;
2334 struct device *kdev;
2337 priv = netdev_priv(dev);
2338 kdev = &priv->pdev->dev;
2340 del_timer_sync(&priv->swphy_poll);
2341 netif_stop_queue(dev);
2342 napi_disable(&priv->napi);
2343 del_timer_sync(&priv->rx_timeout);
2345 /* mask all interrupts */
2346 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2347 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2349 /* disable dma & mac */
2350 bcm_enet_disable_dma(priv, priv->tx_chan);
2351 bcm_enet_disable_dma(priv, priv->rx_chan);
2353 /* force reclaim of all tx buffers */
2354 bcm_enet_tx_reclaim(dev, 1);
2356 /* free the rx skb ring */
2357 for (i = 0; i < priv->rx_ring_size; i++) {
2358 struct bcm_enet_desc *desc;
2360 if (!priv->rx_skb[i])
2363 desc = &priv->rx_desc_cpu[i];
2364 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2366 kfree_skb(priv->rx_skb[i]);
2369 /* free remaining allocated memory */
2370 kfree(priv->rx_skb);
2371 kfree(priv->tx_skb);
2372 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2373 priv->rx_desc_cpu, priv->rx_desc_dma);
2374 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2375 priv->tx_desc_cpu, priv->tx_desc_dma);
2376 if (priv->irq_tx != -1)
2377 free_irq(priv->irq_tx, dev);
2378 free_irq(priv->irq_rx, dev);
2383 /* try to sort out phy external status by walking the used_port field
2384 * in the bcm_enet_priv structure. in case the phy address is not
2385 * assigned to any physical port on the switch, assume it is external
2386 * (and yell at the user).
2388 static int bcm_enetsw_phy_is_external(struct bcm_enet_priv *priv, int phy_id)
2392 for (i = 0; i < priv->num_ports; ++i) {
2393 if (!priv->used_ports[i].used)
2395 if (priv->used_ports[i].phy_id == phy_id)
2396 return bcm_enet_port_is_rgmii(i);
2399 printk_once(KERN_WARNING "bcm63xx_enet: could not find a used port with phy_id %i, assuming phy is external\n",
2404 /* can't use bcmenet_sw_mdio_read directly as we need to sort out
2405 * external/internal status of the given phy_id first.
2407 static int bcm_enetsw_mii_mdio_read(struct net_device *dev, int phy_id,
2410 struct bcm_enet_priv *priv;
2412 priv = netdev_priv(dev);
2413 return bcmenet_sw_mdio_read(priv,
2414 bcm_enetsw_phy_is_external(priv, phy_id),
2418 /* can't use bcmenet_sw_mdio_write directly as we need to sort out
2419 * external/internal status of the given phy_id first.
2421 static void bcm_enetsw_mii_mdio_write(struct net_device *dev, int phy_id,
2425 struct bcm_enet_priv *priv;
2427 priv = netdev_priv(dev);
2428 bcmenet_sw_mdio_write(priv, bcm_enetsw_phy_is_external(priv, phy_id),
2429 phy_id, location, val);
2432 static int bcm_enetsw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2434 struct mii_if_info mii;
2437 mii.mdio_read = bcm_enetsw_mii_mdio_read;
2438 mii.mdio_write = bcm_enetsw_mii_mdio_write;
2440 mii.phy_id_mask = 0x3f;
2441 mii.reg_num_mask = 0x1f;
2442 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
2446 static const struct net_device_ops bcm_enetsw_ops = {
2447 .ndo_open = bcm_enetsw_open,
2448 .ndo_stop = bcm_enetsw_stop,
2449 .ndo_start_xmit = bcm_enet_start_xmit,
2450 .ndo_change_mtu = bcm_enet_change_mtu,
2451 .ndo_do_ioctl = bcm_enetsw_ioctl,
2455 static const struct bcm_enet_stats bcm_enetsw_gstrings_stats[] = {
2456 { "rx_packets", DEV_STAT(rx_packets), -1 },
2457 { "tx_packets", DEV_STAT(tx_packets), -1 },
2458 { "rx_bytes", DEV_STAT(rx_bytes), -1 },
2459 { "tx_bytes", DEV_STAT(tx_bytes), -1 },
2460 { "rx_errors", DEV_STAT(rx_errors), -1 },
2461 { "tx_errors", DEV_STAT(tx_errors), -1 },
2462 { "rx_dropped", DEV_STAT(rx_dropped), -1 },
2463 { "tx_dropped", DEV_STAT(tx_dropped), -1 },
2465 { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETHSW_MIB_RX_GD_OCT },
2466 { "tx_unicast", GEN_STAT(mib.tx_unicast), ETHSW_MIB_RX_BRDCAST },
2467 { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETHSW_MIB_RX_BRDCAST },
2468 { "tx_multicast", GEN_STAT(mib.tx_mult), ETHSW_MIB_RX_MULT },
2469 { "tx_64_octets", GEN_STAT(mib.tx_64), ETHSW_MIB_RX_64 },
2470 { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETHSW_MIB_RX_65_127 },
2471 { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETHSW_MIB_RX_128_255 },
2472 { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETHSW_MIB_RX_256_511 },
2473 { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETHSW_MIB_RX_512_1023},
2474 { "tx_1024_1522_oct", GEN_STAT(mib.tx_1024_max),
2475 ETHSW_MIB_RX_1024_1522 },
2476 { "tx_1523_2047_oct", GEN_STAT(mib.tx_1523_2047),
2477 ETHSW_MIB_RX_1523_2047 },
2478 { "tx_2048_4095_oct", GEN_STAT(mib.tx_2048_4095),
2479 ETHSW_MIB_RX_2048_4095 },
2480 { "tx_4096_8191_oct", GEN_STAT(mib.tx_4096_8191),
2481 ETHSW_MIB_RX_4096_8191 },
2482 { "tx_8192_9728_oct", GEN_STAT(mib.tx_8192_9728),
2483 ETHSW_MIB_RX_8192_9728 },
2484 { "tx_oversize", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR },
2485 { "tx_oversize_drop", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR_DISC },
2486 { "tx_dropped", GEN_STAT(mib.tx_drop), ETHSW_MIB_RX_DROP },
2487 { "tx_undersize", GEN_STAT(mib.tx_underrun), ETHSW_MIB_RX_UND },
2488 { "tx_pause", GEN_STAT(mib.tx_pause), ETHSW_MIB_RX_PAUSE },
2490 { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETHSW_MIB_TX_ALL_OCT },
2491 { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETHSW_MIB_TX_BRDCAST },
2492 { "rx_multicast", GEN_STAT(mib.rx_mult), ETHSW_MIB_TX_MULT },
2493 { "rx_unicast", GEN_STAT(mib.rx_unicast), ETHSW_MIB_TX_MULT },
2494 { "rx_pause", GEN_STAT(mib.rx_pause), ETHSW_MIB_TX_PAUSE },
2495 { "rx_dropped", GEN_STAT(mib.rx_drop), ETHSW_MIB_TX_DROP_PKTS },
2499 #define BCM_ENETSW_STATS_LEN \
2500 (sizeof(bcm_enetsw_gstrings_stats) / sizeof(struct bcm_enet_stats))
2502 static void bcm_enetsw_get_strings(struct net_device *netdev,
2503 u32 stringset, u8 *data)
2507 switch (stringset) {
2509 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2510 memcpy(data + i * ETH_GSTRING_LEN,
2511 bcm_enetsw_gstrings_stats[i].stat_string,
2518 static int bcm_enetsw_get_sset_count(struct net_device *netdev,
2521 switch (string_set) {
2523 return BCM_ENETSW_STATS_LEN;
2529 static void bcm_enetsw_get_drvinfo(struct net_device *netdev,
2530 struct ethtool_drvinfo *drvinfo)
2532 strncpy(drvinfo->driver, bcm_enet_driver_name, 32);
2533 strncpy(drvinfo->version, bcm_enet_driver_version, 32);
2534 strncpy(drvinfo->fw_version, "N/A", 32);
2535 strncpy(drvinfo->bus_info, "bcm63xx", 32);
2538 static void bcm_enetsw_get_ethtool_stats(struct net_device *netdev,
2539 struct ethtool_stats *stats,
2542 struct bcm_enet_priv *priv;
2545 priv = netdev_priv(netdev);
2547 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2548 const struct bcm_enet_stats *s;
2553 s = &bcm_enetsw_gstrings_stats[i];
2559 lo = enetsw_readl(priv, ENETSW_MIB_REG(reg));
2560 p = (char *)priv + s->stat_offset;
2562 if (s->sizeof_stat == sizeof(u64)) {
2563 hi = enetsw_readl(priv, ENETSW_MIB_REG(reg + 1));
2564 *(u64 *)p = ((u64)hi << 32 | lo);
2570 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2571 const struct bcm_enet_stats *s;
2574 s = &bcm_enetsw_gstrings_stats[i];
2576 if (s->mib_reg == -1)
2577 p = (char *)&netdev->stats + s->stat_offset;
2579 p = (char *)priv + s->stat_offset;
2581 data[i] = (s->sizeof_stat == sizeof(u64)) ?
2582 *(u64 *)p : *(u32 *)p;
2586 static void bcm_enetsw_get_ringparam(struct net_device *dev,
2587 struct ethtool_ringparam *ering)
2589 struct bcm_enet_priv *priv;
2591 priv = netdev_priv(dev);
2593 /* rx/tx ring is actually only limited by memory */
2594 ering->rx_max_pending = 8192;
2595 ering->tx_max_pending = 8192;
2596 ering->rx_mini_max_pending = 0;
2597 ering->rx_jumbo_max_pending = 0;
2598 ering->rx_pending = priv->rx_ring_size;
2599 ering->tx_pending = priv->tx_ring_size;
2602 static int bcm_enetsw_set_ringparam(struct net_device *dev,
2603 struct ethtool_ringparam *ering)
2605 struct bcm_enet_priv *priv;
2608 priv = netdev_priv(dev);
2611 if (netif_running(dev)) {
2612 bcm_enetsw_stop(dev);
2616 priv->rx_ring_size = ering->rx_pending;
2617 priv->tx_ring_size = ering->tx_pending;
2622 err = bcm_enetsw_open(dev);
2629 static const struct ethtool_ops bcm_enetsw_ethtool_ops = {
2630 .get_strings = bcm_enetsw_get_strings,
2631 .get_sset_count = bcm_enetsw_get_sset_count,
2632 .get_ethtool_stats = bcm_enetsw_get_ethtool_stats,
2633 .get_drvinfo = bcm_enetsw_get_drvinfo,
2634 .get_ringparam = bcm_enetsw_get_ringparam,
2635 .set_ringparam = bcm_enetsw_set_ringparam,
2638 /* allocate netdevice, request register memory and register device. */
2639 static int bcm_enetsw_probe(struct platform_device *pdev)
2641 struct bcm_enet_priv *priv;
2642 struct net_device *dev;
2643 struct bcm63xx_enetsw_platform_data *pd;
2644 struct resource *res_mem;
2645 int ret, irq_rx, irq_tx;
2647 if (!bcm_enet_shared_base[0])
2648 return -EPROBE_DEFER;
2650 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2651 irq_rx = platform_get_irq(pdev, 0);
2652 irq_tx = platform_get_irq(pdev, 1);
2653 if (!res_mem || irq_rx < 0)
2657 dev = alloc_etherdev(sizeof(*priv));
2660 priv = netdev_priv(dev);
2662 /* initialize default and fetch platform data */
2663 priv->enet_is_sw = true;
2664 priv->irq_rx = irq_rx;
2665 priv->irq_tx = irq_tx;
2666 priv->rx_ring_size = BCMENET_DEF_RX_DESC;
2667 priv->tx_ring_size = BCMENET_DEF_TX_DESC;
2668 priv->dma_maxburst = BCMENETSW_DMA_MAXBURST;
2670 pd = dev_get_platdata(&pdev->dev);
2672 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2673 memcpy(priv->used_ports, pd->used_ports,
2674 sizeof(pd->used_ports));
2675 priv->num_ports = pd->num_ports;
2676 priv->dma_has_sram = pd->dma_has_sram;
2677 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
2678 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
2679 priv->dma_chan_width = pd->dma_chan_width;
2682 ret = bcm_enet_change_mtu(dev, dev->mtu);
2686 priv->base = devm_ioremap_resource(&pdev->dev, res_mem);
2687 if (IS_ERR(priv->base)) {
2688 ret = PTR_ERR(priv->base);
2692 priv->mac_clk = devm_clk_get(&pdev->dev, "enetsw");
2693 if (IS_ERR(priv->mac_clk)) {
2694 ret = PTR_ERR(priv->mac_clk);
2697 ret = clk_prepare_enable(priv->mac_clk);
2703 spin_lock_init(&priv->rx_lock);
2705 /* init rx timeout (used for oom) */
2706 timer_setup(&priv->rx_timeout, bcm_enet_refill_rx_timer, 0);
2708 /* register netdevice */
2709 dev->netdev_ops = &bcm_enetsw_ops;
2710 netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
2711 dev->ethtool_ops = &bcm_enetsw_ethtool_ops;
2712 SET_NETDEV_DEV(dev, &pdev->dev);
2714 spin_lock_init(&priv->enetsw_mdio_lock);
2716 ret = register_netdev(dev);
2718 goto out_disable_clk;
2720 netif_carrier_off(dev);
2721 platform_set_drvdata(pdev, dev);
2723 priv->net_dev = dev;
2728 clk_disable_unprepare(priv->mac_clk);
2735 /* exit func, stops hardware and unregisters netdevice */
2736 static int bcm_enetsw_remove(struct platform_device *pdev)
2738 struct bcm_enet_priv *priv;
2739 struct net_device *dev;
2741 /* stop netdevice */
2742 dev = platform_get_drvdata(pdev);
2743 priv = netdev_priv(dev);
2744 unregister_netdev(dev);
2746 clk_disable_unprepare(priv->mac_clk);
2752 struct platform_driver bcm63xx_enetsw_driver = {
2753 .probe = bcm_enetsw_probe,
2754 .remove = bcm_enetsw_remove,
2756 .name = "bcm63xx_enetsw",
2757 .owner = THIS_MODULE,
2761 /* reserve & remap memory space shared between all macs */
2762 static int bcm_enet_shared_probe(struct platform_device *pdev)
2767 memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base));
2769 for (i = 0; i < 3; i++) {
2770 p[i] = devm_platform_ioremap_resource(pdev, i);
2772 return PTR_ERR(p[i]);
2775 memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base));
2780 static int bcm_enet_shared_remove(struct platform_device *pdev)
2785 /* this "shared" driver is needed because both macs share a single
2788 struct platform_driver bcm63xx_enet_shared_driver = {
2789 .probe = bcm_enet_shared_probe,
2790 .remove = bcm_enet_shared_remove,
2792 .name = "bcm63xx_enet_shared",
2793 .owner = THIS_MODULE,
2797 static struct platform_driver * const drivers[] = {
2798 &bcm63xx_enet_shared_driver,
2799 &bcm63xx_enet_driver,
2800 &bcm63xx_enetsw_driver,
2804 static int __init bcm_enet_init(void)
2806 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
2809 static void __exit bcm_enet_exit(void)
2811 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
2815 module_init(bcm_enet_init);
2816 module_exit(bcm_enet_exit);
2818 MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver");
2819 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
2820 MODULE_LICENSE("GPL");