2 * Broadcom BCM7xxx System Port Ethernet MAC driver
4 * Copyright (C) 2014 Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/netdevice.h>
18 #include <linux/etherdevice.h>
19 #include <linux/platform_device.h>
21 #include <linux/of_net.h>
22 #include <linux/of_mdio.h>
23 #include <linux/phy.h>
24 #include <linux/phy_fixed.h>
28 #include "bcmsysport.h"
30 /* I/O accessors register helpers */
31 #define BCM_SYSPORT_IO_MACRO(name, offset) \
32 static inline u32 name##_readl(struct bcm_sysport_priv *priv, u32 off) \
34 u32 reg = __raw_readl(priv->base + offset + off); \
37 static inline void name##_writel(struct bcm_sysport_priv *priv, \
40 __raw_writel(val, priv->base + offset + off); \
43 BCM_SYSPORT_IO_MACRO(intrl2_0, SYS_PORT_INTRL2_0_OFFSET);
44 BCM_SYSPORT_IO_MACRO(intrl2_1, SYS_PORT_INTRL2_1_OFFSET);
45 BCM_SYSPORT_IO_MACRO(umac, SYS_PORT_UMAC_OFFSET);
46 BCM_SYSPORT_IO_MACRO(tdma, SYS_PORT_TDMA_OFFSET);
47 BCM_SYSPORT_IO_MACRO(rdma, SYS_PORT_RDMA_OFFSET);
48 BCM_SYSPORT_IO_MACRO(rxchk, SYS_PORT_RXCHK_OFFSET);
49 BCM_SYSPORT_IO_MACRO(txchk, SYS_PORT_TXCHK_OFFSET);
50 BCM_SYSPORT_IO_MACRO(rbuf, SYS_PORT_RBUF_OFFSET);
51 BCM_SYSPORT_IO_MACRO(tbuf, SYS_PORT_TBUF_OFFSET);
52 BCM_SYSPORT_IO_MACRO(topctrl, SYS_PORT_TOPCTRL_OFFSET);
54 /* L2-interrupt masking/unmasking helpers, does automatic saving of the applied
55 * mask in a software copy to avoid CPU_MASK_STATUS reads in hot-paths.
57 #define BCM_SYSPORT_INTR_L2(which) \
58 static inline void intrl2_##which##_mask_clear(struct bcm_sysport_priv *priv, \
61 intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \
62 priv->irq##which##_mask &= ~(mask); \
64 static inline void intrl2_##which##_mask_set(struct bcm_sysport_priv *priv, \
67 intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \
68 priv->irq##which##_mask |= (mask); \
71 BCM_SYSPORT_INTR_L2(0)
72 BCM_SYSPORT_INTR_L2(1)
74 /* Register accesses to GISB/RBUS registers are expensive (few hundred
75 * nanoseconds), so keep the check for 64-bits explicit here to save
76 * one register write per-packet on 32-bits platforms.
78 static inline void dma_desc_set_addr(struct bcm_sysport_priv *priv,
82 #ifdef CONFIG_PHYS_ADDR_T_64BIT
83 __raw_writel(upper_32_bits(addr) & DESC_ADDR_HI_MASK,
84 d + DESC_ADDR_HI_STATUS_LEN);
86 __raw_writel(lower_32_bits(addr), d + DESC_ADDR_LO);
89 static inline void tdma_port_write_desc_addr(struct bcm_sysport_priv *priv,
90 struct dma_desc *desc,
93 /* Ports are latched, so write upper address first */
94 tdma_writel(priv, desc->addr_status_len, TDMA_WRITE_PORT_HI(port));
95 tdma_writel(priv, desc->addr_lo, TDMA_WRITE_PORT_LO(port));
98 /* Ethtool operations */
99 static int bcm_sysport_set_settings(struct net_device *dev,
100 struct ethtool_cmd *cmd)
102 struct bcm_sysport_priv *priv = netdev_priv(dev);
104 if (!netif_running(dev))
107 return phy_ethtool_sset(priv->phydev, cmd);
110 static int bcm_sysport_get_settings(struct net_device *dev,
111 struct ethtool_cmd *cmd)
113 struct bcm_sysport_priv *priv = netdev_priv(dev);
115 if (!netif_running(dev))
118 return phy_ethtool_gset(priv->phydev, cmd);
121 static int bcm_sysport_set_rx_csum(struct net_device *dev,
122 netdev_features_t wanted)
124 struct bcm_sysport_priv *priv = netdev_priv(dev);
127 priv->rx_chk_en = !!(wanted & NETIF_F_RXCSUM);
128 reg = rxchk_readl(priv, RXCHK_CONTROL);
134 /* If UniMAC forwards CRC, we need to skip over it to get
135 * a valid CHK bit to be set in the per-packet status word
137 if (priv->rx_chk_en && priv->crc_fwd)
138 reg |= RXCHK_SKIP_FCS;
140 reg &= ~RXCHK_SKIP_FCS;
142 /* If Broadcom tags are enabled (e.g: using a switch), make
143 * sure we tell the RXCHK hardware to expect a 4-bytes Broadcom
144 * tag after the Ethernet MAC Source Address.
146 if (netdev_uses_dsa(dev))
147 reg |= RXCHK_BRCM_TAG_EN;
149 reg &= ~RXCHK_BRCM_TAG_EN;
151 rxchk_writel(priv, reg, RXCHK_CONTROL);
156 static int bcm_sysport_set_tx_csum(struct net_device *dev,
157 netdev_features_t wanted)
159 struct bcm_sysport_priv *priv = netdev_priv(dev);
162 /* Hardware transmit checksum requires us to enable the Transmit status
163 * block prepended to the packet contents
165 priv->tsb_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
166 reg = tdma_readl(priv, TDMA_CONTROL);
171 tdma_writel(priv, reg, TDMA_CONTROL);
176 static int bcm_sysport_set_features(struct net_device *dev,
177 netdev_features_t features)
179 netdev_features_t changed = features ^ dev->features;
180 netdev_features_t wanted = dev->wanted_features;
183 if (changed & NETIF_F_RXCSUM)
184 ret = bcm_sysport_set_rx_csum(dev, wanted);
185 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
186 ret = bcm_sysport_set_tx_csum(dev, wanted);
191 /* Hardware counters must be kept in sync because the order/offset
192 * is important here (order in structure declaration = order in hardware)
194 static const struct bcm_sysport_stats bcm_sysport_gstrings_stats[] = {
196 STAT_NETDEV(rx_packets),
197 STAT_NETDEV(tx_packets),
198 STAT_NETDEV(rx_bytes),
199 STAT_NETDEV(tx_bytes),
200 STAT_NETDEV(rx_errors),
201 STAT_NETDEV(tx_errors),
202 STAT_NETDEV(rx_dropped),
203 STAT_NETDEV(tx_dropped),
204 STAT_NETDEV(multicast),
205 /* UniMAC RSV counters */
206 STAT_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
207 STAT_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
208 STAT_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
209 STAT_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
210 STAT_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
211 STAT_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
212 STAT_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
213 STAT_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
214 STAT_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
215 STAT_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
216 STAT_MIB_RX("rx_pkts", mib.rx.pkt),
217 STAT_MIB_RX("rx_bytes", mib.rx.bytes),
218 STAT_MIB_RX("rx_multicast", mib.rx.mca),
219 STAT_MIB_RX("rx_broadcast", mib.rx.bca),
220 STAT_MIB_RX("rx_fcs", mib.rx.fcs),
221 STAT_MIB_RX("rx_control", mib.rx.cf),
222 STAT_MIB_RX("rx_pause", mib.rx.pf),
223 STAT_MIB_RX("rx_unknown", mib.rx.uo),
224 STAT_MIB_RX("rx_align", mib.rx.aln),
225 STAT_MIB_RX("rx_outrange", mib.rx.flr),
226 STAT_MIB_RX("rx_code", mib.rx.cde),
227 STAT_MIB_RX("rx_carrier", mib.rx.fcr),
228 STAT_MIB_RX("rx_oversize", mib.rx.ovr),
229 STAT_MIB_RX("rx_jabber", mib.rx.jbr),
230 STAT_MIB_RX("rx_mtu_err", mib.rx.mtue),
231 STAT_MIB_RX("rx_good_pkts", mib.rx.pok),
232 STAT_MIB_RX("rx_unicast", mib.rx.uc),
233 STAT_MIB_RX("rx_ppp", mib.rx.ppp),
234 STAT_MIB_RX("rx_crc", mib.rx.rcrc),
235 /* UniMAC TSV counters */
236 STAT_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
237 STAT_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
238 STAT_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
239 STAT_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
240 STAT_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
241 STAT_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
242 STAT_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
243 STAT_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
244 STAT_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
245 STAT_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
246 STAT_MIB_TX("tx_pkts", mib.tx.pkts),
247 STAT_MIB_TX("tx_multicast", mib.tx.mca),
248 STAT_MIB_TX("tx_broadcast", mib.tx.bca),
249 STAT_MIB_TX("tx_pause", mib.tx.pf),
250 STAT_MIB_TX("tx_control", mib.tx.cf),
251 STAT_MIB_TX("tx_fcs_err", mib.tx.fcs),
252 STAT_MIB_TX("tx_oversize", mib.tx.ovr),
253 STAT_MIB_TX("tx_defer", mib.tx.drf),
254 STAT_MIB_TX("tx_excess_defer", mib.tx.edf),
255 STAT_MIB_TX("tx_single_col", mib.tx.scl),
256 STAT_MIB_TX("tx_multi_col", mib.tx.mcl),
257 STAT_MIB_TX("tx_late_col", mib.tx.lcl),
258 STAT_MIB_TX("tx_excess_col", mib.tx.ecl),
259 STAT_MIB_TX("tx_frags", mib.tx.frg),
260 STAT_MIB_TX("tx_total_col", mib.tx.ncl),
261 STAT_MIB_TX("tx_jabber", mib.tx.jbr),
262 STAT_MIB_TX("tx_bytes", mib.tx.bytes),
263 STAT_MIB_TX("tx_good_pkts", mib.tx.pok),
264 STAT_MIB_TX("tx_unicast", mib.tx.uc),
265 /* UniMAC RUNT counters */
266 STAT_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
267 STAT_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
268 STAT_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
269 STAT_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
270 /* RXCHK misc statistics */
271 STAT_RXCHK("rxchk_bad_csum", mib.rxchk_bad_csum, RXCHK_BAD_CSUM_CNTR),
272 STAT_RXCHK("rxchk_other_pkt_disc", mib.rxchk_other_pkt_disc,
273 RXCHK_OTHER_DISC_CNTR),
274 /* RBUF misc statistics */
275 STAT_RBUF("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, RBUF_OVFL_DISC_CNTR),
276 STAT_RBUF("rbuf_err_cnt", mib.rbuf_err_cnt, RBUF_ERR_PKT_CNTR),
277 STAT_MIB_SOFT("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
278 STAT_MIB_SOFT("rx_dma_failed", mib.rx_dma_failed),
279 STAT_MIB_SOFT("tx_dma_failed", mib.tx_dma_failed),
282 #define BCM_SYSPORT_STATS_LEN ARRAY_SIZE(bcm_sysport_gstrings_stats)
284 static void bcm_sysport_get_drvinfo(struct net_device *dev,
285 struct ethtool_drvinfo *info)
287 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
288 strlcpy(info->version, "0.1", sizeof(info->version));
289 strlcpy(info->bus_info, "platform", sizeof(info->bus_info));
290 info->n_stats = BCM_SYSPORT_STATS_LEN;
293 static u32 bcm_sysport_get_msglvl(struct net_device *dev)
295 struct bcm_sysport_priv *priv = netdev_priv(dev);
297 return priv->msg_enable;
300 static void bcm_sysport_set_msglvl(struct net_device *dev, u32 enable)
302 struct bcm_sysport_priv *priv = netdev_priv(dev);
304 priv->msg_enable = enable;
307 static int bcm_sysport_get_sset_count(struct net_device *dev, int string_set)
309 switch (string_set) {
311 return BCM_SYSPORT_STATS_LEN;
317 static void bcm_sysport_get_strings(struct net_device *dev,
318 u32 stringset, u8 *data)
324 for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
325 memcpy(data + i * ETH_GSTRING_LEN,
326 bcm_sysport_gstrings_stats[i].stat_string,
335 static void bcm_sysport_update_mib_counters(struct bcm_sysport_priv *priv)
339 for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
340 const struct bcm_sysport_stats *s;
345 s = &bcm_sysport_gstrings_stats[i];
347 case BCM_SYSPORT_STAT_NETDEV:
348 case BCM_SYSPORT_STAT_SOFT:
350 case BCM_SYSPORT_STAT_MIB_RX:
351 case BCM_SYSPORT_STAT_MIB_TX:
352 case BCM_SYSPORT_STAT_RUNT:
353 if (s->type != BCM_SYSPORT_STAT_MIB_RX)
354 offset = UMAC_MIB_STAT_OFFSET;
355 val = umac_readl(priv, UMAC_MIB_START + j + offset);
357 case BCM_SYSPORT_STAT_RXCHK:
358 val = rxchk_readl(priv, s->reg_offset);
360 rxchk_writel(priv, 0, s->reg_offset);
362 case BCM_SYSPORT_STAT_RBUF:
363 val = rbuf_readl(priv, s->reg_offset);
365 rbuf_writel(priv, 0, s->reg_offset);
370 p = (char *)priv + s->stat_offset;
374 netif_dbg(priv, hw, priv->netdev, "updated MIB counters\n");
377 static void bcm_sysport_get_stats(struct net_device *dev,
378 struct ethtool_stats *stats, u64 *data)
380 struct bcm_sysport_priv *priv = netdev_priv(dev);
383 if (netif_running(dev))
384 bcm_sysport_update_mib_counters(priv);
386 for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
387 const struct bcm_sysport_stats *s;
390 s = &bcm_sysport_gstrings_stats[i];
391 if (s->type == BCM_SYSPORT_STAT_NETDEV)
392 p = (char *)&dev->stats;
400 static void bcm_sysport_get_wol(struct net_device *dev,
401 struct ethtool_wolinfo *wol)
403 struct bcm_sysport_priv *priv = netdev_priv(dev);
406 wol->supported = WAKE_MAGIC | WAKE_MAGICSECURE;
407 wol->wolopts = priv->wolopts;
409 if (!(priv->wolopts & WAKE_MAGICSECURE))
412 /* Return the programmed SecureOn password */
413 reg = umac_readl(priv, UMAC_PSW_MS);
414 put_unaligned_be16(reg, &wol->sopass[0]);
415 reg = umac_readl(priv, UMAC_PSW_LS);
416 put_unaligned_be32(reg, &wol->sopass[2]);
419 static int bcm_sysport_set_wol(struct net_device *dev,
420 struct ethtool_wolinfo *wol)
422 struct bcm_sysport_priv *priv = netdev_priv(dev);
423 struct device *kdev = &priv->pdev->dev;
424 u32 supported = WAKE_MAGIC | WAKE_MAGICSECURE;
426 if (!device_can_wakeup(kdev))
429 if (wol->wolopts & ~supported)
432 /* Program the SecureOn password */
433 if (wol->wolopts & WAKE_MAGICSECURE) {
434 umac_writel(priv, get_unaligned_be16(&wol->sopass[0]),
436 umac_writel(priv, get_unaligned_be32(&wol->sopass[2]),
440 /* Flag the device and relevant IRQ as wakeup capable */
442 device_set_wakeup_enable(kdev, 1);
443 if (priv->wol_irq_disabled)
444 enable_irq_wake(priv->wol_irq);
445 priv->wol_irq_disabled = 0;
447 device_set_wakeup_enable(kdev, 0);
448 /* Avoid unbalanced disable_irq_wake calls */
449 if (!priv->wol_irq_disabled)
450 disable_irq_wake(priv->wol_irq);
451 priv->wol_irq_disabled = 1;
454 priv->wolopts = wol->wolopts;
459 static int bcm_sysport_get_coalesce(struct net_device *dev,
460 struct ethtool_coalesce *ec)
462 struct bcm_sysport_priv *priv = netdev_priv(dev);
465 reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(0));
467 ec->tx_coalesce_usecs = (reg >> RING_TIMEOUT_SHIFT) * 8192 / 1000;
468 ec->tx_max_coalesced_frames = reg & RING_INTR_THRESH_MASK;
470 reg = rdma_readl(priv, RDMA_MBDONE_INTR);
472 ec->rx_coalesce_usecs = (reg >> RDMA_TIMEOUT_SHIFT) * 8192 / 1000;
473 ec->rx_max_coalesced_frames = reg & RDMA_INTR_THRESH_MASK;
478 static int bcm_sysport_set_coalesce(struct net_device *dev,
479 struct ethtool_coalesce *ec)
481 struct bcm_sysport_priv *priv = netdev_priv(dev);
485 /* Base system clock is 125Mhz, DMA timeout is this reference clock
486 * divided by 1024, which yield roughly 8.192 us, our maximum value has
487 * to fit in the RING_TIMEOUT_MASK (16 bits).
489 if (ec->tx_max_coalesced_frames > RING_INTR_THRESH_MASK ||
490 ec->tx_coalesce_usecs > (RING_TIMEOUT_MASK * 8) + 1 ||
491 ec->rx_max_coalesced_frames > RDMA_INTR_THRESH_MASK ||
492 ec->rx_coalesce_usecs > (RDMA_TIMEOUT_MASK * 8) + 1)
495 if ((ec->tx_coalesce_usecs == 0 && ec->tx_max_coalesced_frames == 0) ||
496 (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0))
499 for (i = 0; i < dev->num_tx_queues; i++) {
500 reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(i));
501 reg &= ~(RING_INTR_THRESH_MASK |
502 RING_TIMEOUT_MASK << RING_TIMEOUT_SHIFT);
503 reg |= ec->tx_max_coalesced_frames;
504 reg |= DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000, 8192) <<
506 tdma_writel(priv, reg, TDMA_DESC_RING_INTR_CONTROL(i));
509 reg = rdma_readl(priv, RDMA_MBDONE_INTR);
510 reg &= ~(RDMA_INTR_THRESH_MASK |
511 RDMA_TIMEOUT_MASK << RDMA_TIMEOUT_SHIFT);
512 reg |= ec->rx_max_coalesced_frames;
513 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192) <<
515 rdma_writel(priv, reg, RDMA_MBDONE_INTR);
520 static void bcm_sysport_free_cb(struct bcm_sysport_cb *cb)
522 dev_kfree_skb_any(cb->skb);
524 dma_unmap_addr_set(cb, dma_addr, 0);
527 static struct sk_buff *bcm_sysport_rx_refill(struct bcm_sysport_priv *priv,
528 struct bcm_sysport_cb *cb)
530 struct device *kdev = &priv->pdev->dev;
531 struct net_device *ndev = priv->netdev;
532 struct sk_buff *skb, *rx_skb;
535 /* Allocate a new SKB for a new packet */
536 skb = netdev_alloc_skb(priv->netdev, RX_BUF_LENGTH);
538 priv->mib.alloc_rx_buff_failed++;
539 netif_err(priv, rx_err, ndev, "SKB alloc failed\n");
543 mapping = dma_map_single(kdev, skb->data,
544 RX_BUF_LENGTH, DMA_FROM_DEVICE);
545 if (dma_mapping_error(kdev, mapping)) {
546 priv->mib.rx_dma_failed++;
547 dev_kfree_skb_any(skb);
548 netif_err(priv, rx_err, ndev, "DMA mapping failure\n");
552 /* Grab the current SKB on the ring */
555 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
556 RX_BUF_LENGTH, DMA_FROM_DEVICE);
558 /* Put the new SKB on the ring */
560 dma_unmap_addr_set(cb, dma_addr, mapping);
561 dma_desc_set_addr(priv, cb->bd_addr, mapping);
563 netif_dbg(priv, rx_status, ndev, "RX refill\n");
565 /* Return the current SKB to the caller */
569 static int bcm_sysport_alloc_rx_bufs(struct bcm_sysport_priv *priv)
571 struct bcm_sysport_cb *cb;
575 for (i = 0; i < priv->num_rx_bds; i++) {
576 cb = &priv->rx_cbs[i];
577 skb = bcm_sysport_rx_refill(priv, cb);
587 /* Poll the hardware for up to budget packets to process */
588 static unsigned int bcm_sysport_desc_rx(struct bcm_sysport_priv *priv,
591 struct net_device *ndev = priv->netdev;
592 unsigned int processed = 0, to_process;
593 struct bcm_sysport_cb *cb;
595 unsigned int p_index;
599 /* Determine how much we should process since last call */
600 p_index = rdma_readl(priv, RDMA_PROD_INDEX);
601 p_index &= RDMA_PROD_INDEX_MASK;
603 if (p_index < priv->rx_c_index)
604 to_process = (RDMA_CONS_INDEX_MASK + 1) -
605 priv->rx_c_index + p_index;
607 to_process = p_index - priv->rx_c_index;
609 netif_dbg(priv, rx_status, ndev,
610 "p_index=%d rx_c_index=%d to_process=%d\n",
611 p_index, priv->rx_c_index, to_process);
613 while ((processed < to_process) && (processed < budget)) {
614 cb = &priv->rx_cbs[priv->rx_read_ptr];
615 skb = bcm_sysport_rx_refill(priv, cb);
618 /* We do not have a backing SKB, so we do not a corresponding
619 * DMA mapping for this incoming packet since
620 * bcm_sysport_rx_refill always either has both skb and mapping
623 if (unlikely(!skb)) {
624 netif_err(priv, rx_err, ndev, "out of memory!\n");
625 ndev->stats.rx_dropped++;
626 ndev->stats.rx_errors++;
630 /* Extract the Receive Status Block prepended */
631 rsb = (struct bcm_rsb *)skb->data;
632 len = (rsb->rx_status_len >> DESC_LEN_SHIFT) & DESC_LEN_MASK;
633 status = (rsb->rx_status_len >> DESC_STATUS_SHIFT) &
636 netif_dbg(priv, rx_status, ndev,
637 "p=%d, c=%d, rd_ptr=%d, len=%d, flag=0x%04x\n",
638 p_index, priv->rx_c_index, priv->rx_read_ptr,
641 if (unlikely(!(status & DESC_EOP) || !(status & DESC_SOP))) {
642 netif_err(priv, rx_status, ndev, "fragmented packet!\n");
643 ndev->stats.rx_dropped++;
644 ndev->stats.rx_errors++;
645 dev_kfree_skb_any(skb);
649 if (unlikely(status & (RX_STATUS_ERR | RX_STATUS_OVFLOW))) {
650 netif_err(priv, rx_err, ndev, "error packet\n");
651 if (status & RX_STATUS_OVFLOW)
652 ndev->stats.rx_over_errors++;
653 ndev->stats.rx_dropped++;
654 ndev->stats.rx_errors++;
655 dev_kfree_skb_any(skb);
661 /* Hardware validated our checksum */
662 if (likely(status & DESC_L4_CSUM))
663 skb->ip_summed = CHECKSUM_UNNECESSARY;
665 /* Hardware pre-pends packets with 2bytes before Ethernet
666 * header plus we have the Receive Status Block, strip off all
667 * of this from the SKB.
669 skb_pull(skb, sizeof(*rsb) + 2);
670 len -= (sizeof(*rsb) + 2);
672 /* UniMAC may forward CRC */
674 skb_trim(skb, len - ETH_FCS_LEN);
678 skb->protocol = eth_type_trans(skb, ndev);
679 ndev->stats.rx_packets++;
680 ndev->stats.rx_bytes += len;
682 napi_gro_receive(&priv->napi, skb);
687 if (priv->rx_read_ptr == priv->num_rx_bds)
688 priv->rx_read_ptr = 0;
694 static void bcm_sysport_tx_reclaim_one(struct bcm_sysport_priv *priv,
695 struct bcm_sysport_cb *cb,
696 unsigned int *bytes_compl,
697 unsigned int *pkts_compl)
699 struct device *kdev = &priv->pdev->dev;
700 struct net_device *ndev = priv->netdev;
703 ndev->stats.tx_bytes += cb->skb->len;
704 *bytes_compl += cb->skb->len;
705 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
706 dma_unmap_len(cb, dma_len),
708 ndev->stats.tx_packets++;
710 bcm_sysport_free_cb(cb);
712 } else if (dma_unmap_addr(cb, dma_addr)) {
713 ndev->stats.tx_bytes += dma_unmap_len(cb, dma_len);
714 dma_unmap_page(kdev, dma_unmap_addr(cb, dma_addr),
715 dma_unmap_len(cb, dma_len), DMA_TO_DEVICE);
716 dma_unmap_addr_set(cb, dma_addr, 0);
720 /* Reclaim queued SKBs for transmission completion, lockless version */
721 static unsigned int __bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv,
722 struct bcm_sysport_tx_ring *ring)
724 struct net_device *ndev = priv->netdev;
725 unsigned int c_index, last_c_index, last_tx_cn, num_tx_cbs;
726 unsigned int pkts_compl = 0, bytes_compl = 0;
727 struct bcm_sysport_cb *cb;
728 struct netdev_queue *txq;
731 txq = netdev_get_tx_queue(ndev, ring->index);
733 /* Compute how many descriptors have been processed since last call */
734 hw_ind = tdma_readl(priv, TDMA_DESC_RING_PROD_CONS_INDEX(ring->index));
735 c_index = (hw_ind >> RING_CONS_INDEX_SHIFT) & RING_CONS_INDEX_MASK;
736 ring->p_index = (hw_ind & RING_PROD_INDEX_MASK);
738 last_c_index = ring->c_index;
739 num_tx_cbs = ring->size;
741 c_index &= (num_tx_cbs - 1);
743 if (c_index >= last_c_index)
744 last_tx_cn = c_index - last_c_index;
746 last_tx_cn = num_tx_cbs - last_c_index + c_index;
748 netif_dbg(priv, tx_done, ndev,
749 "ring=%d c_index=%d last_tx_cn=%d last_c_index=%d\n",
750 ring->index, c_index, last_tx_cn, last_c_index);
752 while (last_tx_cn-- > 0) {
753 cb = ring->cbs + last_c_index;
754 bcm_sysport_tx_reclaim_one(priv, cb, &bytes_compl, &pkts_compl);
758 last_c_index &= (num_tx_cbs - 1);
761 ring->c_index = c_index;
763 if (netif_tx_queue_stopped(txq) && pkts_compl)
764 netif_tx_wake_queue(txq);
766 netif_dbg(priv, tx_done, ndev,
767 "ring=%d c_index=%d pkts_compl=%d, bytes_compl=%d\n",
768 ring->index, ring->c_index, pkts_compl, bytes_compl);
773 /* Locked version of the per-ring TX reclaim routine */
774 static unsigned int bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv,
775 struct bcm_sysport_tx_ring *ring)
777 unsigned int released;
780 spin_lock_irqsave(&ring->lock, flags);
781 released = __bcm_sysport_tx_reclaim(priv, ring);
782 spin_unlock_irqrestore(&ring->lock, flags);
787 static int bcm_sysport_tx_poll(struct napi_struct *napi, int budget)
789 struct bcm_sysport_tx_ring *ring =
790 container_of(napi, struct bcm_sysport_tx_ring, napi);
791 unsigned int work_done = 0;
793 work_done = bcm_sysport_tx_reclaim(ring->priv, ring);
795 if (work_done == 0) {
797 /* re-enable TX interrupt */
798 intrl2_1_mask_clear(ring->priv, BIT(ring->index));
806 static void bcm_sysport_tx_reclaim_all(struct bcm_sysport_priv *priv)
810 for (q = 0; q < priv->netdev->num_tx_queues; q++)
811 bcm_sysport_tx_reclaim(priv, &priv->tx_rings[q]);
814 static int bcm_sysport_poll(struct napi_struct *napi, int budget)
816 struct bcm_sysport_priv *priv =
817 container_of(napi, struct bcm_sysport_priv, napi);
818 unsigned int work_done = 0;
820 work_done = bcm_sysport_desc_rx(priv, budget);
822 priv->rx_c_index += work_done;
823 priv->rx_c_index &= RDMA_CONS_INDEX_MASK;
824 rdma_writel(priv, priv->rx_c_index, RDMA_CONS_INDEX);
826 if (work_done < budget) {
828 /* re-enable RX interrupts */
829 intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE);
835 static void bcm_sysport_resume_from_wol(struct bcm_sysport_priv *priv)
839 /* Stop monitoring MPD interrupt */
840 intrl2_0_mask_set(priv, INTRL2_0_MPD);
842 /* Clear the MagicPacket detection logic */
843 reg = umac_readl(priv, UMAC_MPD_CTRL);
845 umac_writel(priv, reg, UMAC_MPD_CTRL);
847 netif_dbg(priv, wol, priv->netdev, "resumed from WOL\n");
850 /* RX and misc interrupt routine */
851 static irqreturn_t bcm_sysport_rx_isr(int irq, void *dev_id)
853 struct net_device *dev = dev_id;
854 struct bcm_sysport_priv *priv = netdev_priv(dev);
856 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
857 ~intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
858 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
860 if (unlikely(priv->irq0_stat == 0)) {
861 netdev_warn(priv->netdev, "spurious RX interrupt\n");
865 if (priv->irq0_stat & INTRL2_0_RDMA_MBDONE) {
866 if (likely(napi_schedule_prep(&priv->napi))) {
867 /* disable RX interrupts */
868 intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE);
869 __napi_schedule(&priv->napi);
873 /* TX ring is full, perform a full reclaim since we do not know
874 * which one would trigger this interrupt
876 if (priv->irq0_stat & INTRL2_0_TX_RING_FULL)
877 bcm_sysport_tx_reclaim_all(priv);
879 if (priv->irq0_stat & INTRL2_0_MPD) {
880 netdev_info(priv->netdev, "Wake-on-LAN interrupt!\n");
881 bcm_sysport_resume_from_wol(priv);
887 /* TX interrupt service routine */
888 static irqreturn_t bcm_sysport_tx_isr(int irq, void *dev_id)
890 struct net_device *dev = dev_id;
891 struct bcm_sysport_priv *priv = netdev_priv(dev);
892 struct bcm_sysport_tx_ring *txr;
895 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
896 ~intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
897 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
899 if (unlikely(priv->irq1_stat == 0)) {
900 netdev_warn(priv->netdev, "spurious TX interrupt\n");
904 for (ring = 0; ring < dev->num_tx_queues; ring++) {
905 if (!(priv->irq1_stat & BIT(ring)))
908 txr = &priv->tx_rings[ring];
910 if (likely(napi_schedule_prep(&txr->napi))) {
911 intrl2_1_mask_set(priv, BIT(ring));
912 __napi_schedule(&txr->napi);
919 static irqreturn_t bcm_sysport_wol_isr(int irq, void *dev_id)
921 struct bcm_sysport_priv *priv = dev_id;
923 pm_wakeup_event(&priv->pdev->dev, 0);
928 static struct sk_buff *bcm_sysport_insert_tsb(struct sk_buff *skb,
929 struct net_device *dev)
931 struct sk_buff *nskb;
938 /* Re-allocate SKB if needed */
939 if (unlikely(skb_headroom(skb) < sizeof(*tsb))) {
940 nskb = skb_realloc_headroom(skb, sizeof(*tsb));
943 dev->stats.tx_errors++;
944 dev->stats.tx_dropped++;
950 tsb = (struct bcm_tsb *)skb_push(skb, sizeof(*tsb));
951 /* Zero-out TSB by default */
952 memset(tsb, 0, sizeof(*tsb));
954 if (skb->ip_summed == CHECKSUM_PARTIAL) {
955 ip_ver = htons(skb->protocol);
958 ip_proto = ip_hdr(skb)->protocol;
961 ip_proto = ipv6_hdr(skb)->nexthdr;
967 /* Get the checksum offset and the L4 (transport) offset */
968 csum_start = skb_checksum_start_offset(skb) - sizeof(*tsb);
969 csum_info = (csum_start + skb->csum_offset) & L4_CSUM_PTR_MASK;
970 csum_info |= (csum_start << L4_PTR_SHIFT);
972 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
973 csum_info |= L4_LENGTH_VALID;
974 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
980 tsb->l4_ptr_dest_map = csum_info;
986 static netdev_tx_t bcm_sysport_xmit(struct sk_buff *skb,
987 struct net_device *dev)
989 struct bcm_sysport_priv *priv = netdev_priv(dev);
990 struct device *kdev = &priv->pdev->dev;
991 struct bcm_sysport_tx_ring *ring;
992 struct bcm_sysport_cb *cb;
993 struct netdev_queue *txq;
994 struct dma_desc *desc;
995 unsigned int skb_len;
1002 queue = skb_get_queue_mapping(skb);
1003 txq = netdev_get_tx_queue(dev, queue);
1004 ring = &priv->tx_rings[queue];
1006 /* lock against tx reclaim in BH context and TX ring full interrupt */
1007 spin_lock_irqsave(&ring->lock, flags);
1008 if (unlikely(ring->desc_count == 0)) {
1009 netif_tx_stop_queue(txq);
1010 netdev_err(dev, "queue %d awake and ring full!\n", queue);
1011 ret = NETDEV_TX_BUSY;
1015 /* Insert TSB and checksum infos */
1017 skb = bcm_sysport_insert_tsb(skb, dev);
1024 /* The Ethernet switch we are interfaced with needs packets to be at
1025 * least 64 bytes (including FCS) otherwise they will be discarded when
1026 * they enter the switch port logic. When Broadcom tags are enabled, we
1027 * need to make sure that packets are at least 68 bytes
1028 * (including FCS and tag) because the length verification is done after
1029 * the Broadcom tag is stripped off the ingress packet.
1031 if (skb_padto(skb, ETH_ZLEN + ENET_BRCM_TAG_LEN)) {
1036 skb_len = skb->len < ETH_ZLEN + ENET_BRCM_TAG_LEN ?
1037 ETH_ZLEN + ENET_BRCM_TAG_LEN : skb->len;
1039 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1040 if (dma_mapping_error(kdev, mapping)) {
1041 priv->mib.tx_dma_failed++;
1042 netif_err(priv, tx_err, dev, "DMA map failed at %p (len=%d)\n",
1043 skb->data, skb_len);
1048 /* Remember the SKB for future freeing */
1049 cb = &ring->cbs[ring->curr_desc];
1051 dma_unmap_addr_set(cb, dma_addr, mapping);
1052 dma_unmap_len_set(cb, dma_len, skb_len);
1054 /* Fetch a descriptor entry from our pool */
1055 desc = ring->desc_cpu;
1057 desc->addr_lo = lower_32_bits(mapping);
1058 len_status = upper_32_bits(mapping) & DESC_ADDR_HI_MASK;
1059 len_status |= (skb_len << DESC_LEN_SHIFT);
1060 len_status |= (DESC_SOP | DESC_EOP | TX_STATUS_APP_CRC) <<
1062 if (skb->ip_summed == CHECKSUM_PARTIAL)
1063 len_status |= (DESC_L4_CSUM << DESC_STATUS_SHIFT);
1066 if (ring->curr_desc == ring->size)
1067 ring->curr_desc = 0;
1070 /* Ensure write completion of the descriptor status/length
1071 * in DRAM before the System Port WRITE_PORT register latches
1075 desc->addr_status_len = len_status;
1078 /* Write this descriptor address to the RING write port */
1079 tdma_port_write_desc_addr(priv, desc, ring->index);
1081 /* Check ring space and update SW control flow */
1082 if (ring->desc_count == 0)
1083 netif_tx_stop_queue(txq);
1085 netif_dbg(priv, tx_queued, dev, "ring=%d desc_count=%d, curr_desc=%d\n",
1086 ring->index, ring->desc_count, ring->curr_desc);
1090 spin_unlock_irqrestore(&ring->lock, flags);
1094 static void bcm_sysport_tx_timeout(struct net_device *dev)
1096 netdev_warn(dev, "transmit timeout!\n");
1098 dev->trans_start = jiffies;
1099 dev->stats.tx_errors++;
1101 netif_tx_wake_all_queues(dev);
1104 /* phylib adjust link callback */
1105 static void bcm_sysport_adj_link(struct net_device *dev)
1107 struct bcm_sysport_priv *priv = netdev_priv(dev);
1108 struct phy_device *phydev = priv->phydev;
1109 unsigned int changed = 0;
1110 u32 cmd_bits = 0, reg;
1112 if (priv->old_link != phydev->link) {
1114 priv->old_link = phydev->link;
1117 if (priv->old_duplex != phydev->duplex) {
1119 priv->old_duplex = phydev->duplex;
1122 switch (phydev->speed) {
1124 cmd_bits = CMD_SPEED_2500;
1127 cmd_bits = CMD_SPEED_1000;
1130 cmd_bits = CMD_SPEED_100;
1133 cmd_bits = CMD_SPEED_10;
1138 cmd_bits <<= CMD_SPEED_SHIFT;
1140 if (phydev->duplex == DUPLEX_HALF)
1141 cmd_bits |= CMD_HD_EN;
1143 if (priv->old_pause != phydev->pause) {
1145 priv->old_pause = phydev->pause;
1149 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
1155 reg = umac_readl(priv, UMAC_CMD);
1156 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
1157 CMD_HD_EN | CMD_RX_PAUSE_IGNORE |
1158 CMD_TX_PAUSE_IGNORE);
1160 umac_writel(priv, reg, UMAC_CMD);
1163 phy_print_status(priv->phydev);
1166 static int bcm_sysport_init_tx_ring(struct bcm_sysport_priv *priv,
1169 struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index];
1170 struct device *kdev = &priv->pdev->dev;
1175 /* Simple descriptors partitioning for now */
1178 /* We just need one DMA descriptor which is DMA-able, since writing to
1179 * the port will allocate a new descriptor in its internal linked-list
1181 p = dma_zalloc_coherent(kdev, sizeof(struct dma_desc), &ring->desc_dma,
1184 netif_err(priv, hw, priv->netdev, "DMA alloc failed\n");
1188 ring->cbs = kcalloc(size, sizeof(struct bcm_sysport_cb), GFP_KERNEL);
1190 netif_err(priv, hw, priv->netdev, "CB allocation failed\n");
1194 /* Initialize SW view of the ring */
1195 spin_lock_init(&ring->lock);
1197 netif_napi_add(priv->netdev, &ring->napi, bcm_sysport_tx_poll, 64);
1198 ring->index = index;
1200 ring->alloc_size = ring->size;
1202 ring->desc_count = ring->size;
1203 ring->curr_desc = 0;
1205 /* Initialize HW ring */
1206 tdma_writel(priv, RING_EN, TDMA_DESC_RING_HEAD_TAIL_PTR(index));
1207 tdma_writel(priv, 0, TDMA_DESC_RING_COUNT(index));
1208 tdma_writel(priv, 1, TDMA_DESC_RING_INTR_CONTROL(index));
1209 tdma_writel(priv, 0, TDMA_DESC_RING_PROD_CONS_INDEX(index));
1210 tdma_writel(priv, RING_IGNORE_STATUS, TDMA_DESC_RING_MAPPING(index));
1211 tdma_writel(priv, 0, TDMA_DESC_RING_PCP_DEI_VID(index));
1213 /* Program the number of descriptors as MAX_THRESHOLD and half of
1214 * its size for the hysteresis trigger
1216 tdma_writel(priv, ring->size |
1217 1 << RING_HYST_THRESH_SHIFT,
1218 TDMA_DESC_RING_MAX_HYST(index));
1220 /* Enable the ring queue in the arbiter */
1221 reg = tdma_readl(priv, TDMA_TIER1_ARB_0_QUEUE_EN);
1222 reg |= (1 << index);
1223 tdma_writel(priv, reg, TDMA_TIER1_ARB_0_QUEUE_EN);
1225 napi_enable(&ring->napi);
1227 netif_dbg(priv, hw, priv->netdev,
1228 "TDMA cfg, size=%d, desc_cpu=%p\n",
1229 ring->size, ring->desc_cpu);
1234 static void bcm_sysport_fini_tx_ring(struct bcm_sysport_priv *priv,
1237 struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index];
1238 struct device *kdev = &priv->pdev->dev;
1241 /* Caller should stop the TDMA engine */
1242 reg = tdma_readl(priv, TDMA_STATUS);
1243 if (!(reg & TDMA_DISABLED))
1244 netdev_warn(priv->netdev, "TDMA not stopped!\n");
1246 /* ring->cbs is the last part in bcm_sysport_init_tx_ring which could
1247 * fail, so by checking this pointer we know whether the TX ring was
1248 * fully initialized or not.
1253 napi_disable(&ring->napi);
1254 netif_napi_del(&ring->napi);
1256 bcm_sysport_tx_reclaim(priv, ring);
1261 if (ring->desc_dma) {
1262 dma_free_coherent(kdev, sizeof(struct dma_desc),
1263 ring->desc_cpu, ring->desc_dma);
1267 ring->alloc_size = 0;
1269 netif_dbg(priv, hw, priv->netdev, "TDMA fini done\n");
1273 static inline int rdma_enable_set(struct bcm_sysport_priv *priv,
1274 unsigned int enable)
1276 unsigned int timeout = 1000;
1279 reg = rdma_readl(priv, RDMA_CONTROL);
1284 rdma_writel(priv, reg, RDMA_CONTROL);
1286 /* Poll for RMDA disabling completion */
1288 reg = rdma_readl(priv, RDMA_STATUS);
1289 if (!!(reg & RDMA_DISABLED) == !enable)
1291 usleep_range(1000, 2000);
1292 } while (timeout-- > 0);
1294 netdev_err(priv->netdev, "timeout waiting for RDMA to finish\n");
1300 static inline int tdma_enable_set(struct bcm_sysport_priv *priv,
1301 unsigned int enable)
1303 unsigned int timeout = 1000;
1306 reg = tdma_readl(priv, TDMA_CONTROL);
1311 tdma_writel(priv, reg, TDMA_CONTROL);
1313 /* Poll for TMDA disabling completion */
1315 reg = tdma_readl(priv, TDMA_STATUS);
1316 if (!!(reg & TDMA_DISABLED) == !enable)
1319 usleep_range(1000, 2000);
1320 } while (timeout-- > 0);
1322 netdev_err(priv->netdev, "timeout waiting for TDMA to finish\n");
1327 static int bcm_sysport_init_rx_ring(struct bcm_sysport_priv *priv)
1329 struct bcm_sysport_cb *cb;
1334 /* Initialize SW view of the RX ring */
1335 priv->num_rx_bds = NUM_RX_DESC;
1336 priv->rx_bds = priv->base + SYS_PORT_RDMA_OFFSET;
1337 priv->rx_c_index = 0;
1338 priv->rx_read_ptr = 0;
1339 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct bcm_sysport_cb),
1341 if (!priv->rx_cbs) {
1342 netif_err(priv, hw, priv->netdev, "CB allocation failed\n");
1346 for (i = 0; i < priv->num_rx_bds; i++) {
1347 cb = priv->rx_cbs + i;
1348 cb->bd_addr = priv->rx_bds + i * DESC_SIZE;
1351 ret = bcm_sysport_alloc_rx_bufs(priv);
1353 netif_err(priv, hw, priv->netdev, "SKB allocation failed\n");
1357 /* Initialize HW, ensure RDMA is disabled */
1358 reg = rdma_readl(priv, RDMA_STATUS);
1359 if (!(reg & RDMA_DISABLED))
1360 rdma_enable_set(priv, 0);
1362 rdma_writel(priv, 0, RDMA_WRITE_PTR_LO);
1363 rdma_writel(priv, 0, RDMA_WRITE_PTR_HI);
1364 rdma_writel(priv, 0, RDMA_PROD_INDEX);
1365 rdma_writel(priv, 0, RDMA_CONS_INDEX);
1366 rdma_writel(priv, priv->num_rx_bds << RDMA_RING_SIZE_SHIFT |
1367 RX_BUF_LENGTH, RDMA_RING_BUF_SIZE);
1368 /* Operate the queue in ring mode */
1369 rdma_writel(priv, 0, RDMA_START_ADDR_HI);
1370 rdma_writel(priv, 0, RDMA_START_ADDR_LO);
1371 rdma_writel(priv, 0, RDMA_END_ADDR_HI);
1372 rdma_writel(priv, NUM_HW_RX_DESC_WORDS - 1, RDMA_END_ADDR_LO);
1374 rdma_writel(priv, 1, RDMA_MBDONE_INTR);
1376 netif_dbg(priv, hw, priv->netdev,
1377 "RDMA cfg, num_rx_bds=%d, rx_bds=%p\n",
1378 priv->num_rx_bds, priv->rx_bds);
1383 static void bcm_sysport_fini_rx_ring(struct bcm_sysport_priv *priv)
1385 struct bcm_sysport_cb *cb;
1389 /* Caller should ensure RDMA is disabled */
1390 reg = rdma_readl(priv, RDMA_STATUS);
1391 if (!(reg & RDMA_DISABLED))
1392 netdev_warn(priv->netdev, "RDMA not stopped!\n");
1394 for (i = 0; i < priv->num_rx_bds; i++) {
1395 cb = &priv->rx_cbs[i];
1396 if (dma_unmap_addr(cb, dma_addr))
1397 dma_unmap_single(&priv->pdev->dev,
1398 dma_unmap_addr(cb, dma_addr),
1399 RX_BUF_LENGTH, DMA_FROM_DEVICE);
1400 bcm_sysport_free_cb(cb);
1403 kfree(priv->rx_cbs);
1404 priv->rx_cbs = NULL;
1406 netif_dbg(priv, hw, priv->netdev, "RDMA fini done\n");
1409 static void bcm_sysport_set_rx_mode(struct net_device *dev)
1411 struct bcm_sysport_priv *priv = netdev_priv(dev);
1414 reg = umac_readl(priv, UMAC_CMD);
1415 if (dev->flags & IFF_PROMISC)
1418 reg &= ~CMD_PROMISC;
1419 umac_writel(priv, reg, UMAC_CMD);
1421 /* No support for ALLMULTI */
1422 if (dev->flags & IFF_ALLMULTI)
1426 static inline void umac_enable_set(struct bcm_sysport_priv *priv,
1427 u32 mask, unsigned int enable)
1431 reg = umac_readl(priv, UMAC_CMD);
1436 umac_writel(priv, reg, UMAC_CMD);
1438 /* UniMAC stops on a packet boundary, wait for a full-sized packet
1439 * to be processed (1 msec).
1442 usleep_range(1000, 2000);
1445 static inline void umac_reset(struct bcm_sysport_priv *priv)
1449 reg = umac_readl(priv, UMAC_CMD);
1450 reg |= CMD_SW_RESET;
1451 umac_writel(priv, reg, UMAC_CMD);
1453 reg = umac_readl(priv, UMAC_CMD);
1454 reg &= ~CMD_SW_RESET;
1455 umac_writel(priv, reg, UMAC_CMD);
1458 static void umac_set_hw_addr(struct bcm_sysport_priv *priv,
1459 unsigned char *addr)
1461 umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
1462 (addr[2] << 8) | addr[3], UMAC_MAC0);
1463 umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
1466 static void topctrl_flush(struct bcm_sysport_priv *priv)
1468 topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL);
1469 topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL);
1471 topctrl_writel(priv, 0, RX_FLUSH_CNTL);
1472 topctrl_writel(priv, 0, TX_FLUSH_CNTL);
1475 static int bcm_sysport_change_mac(struct net_device *dev, void *p)
1477 struct bcm_sysport_priv *priv = netdev_priv(dev);
1478 struct sockaddr *addr = p;
1480 if (!is_valid_ether_addr(addr->sa_data))
1483 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1485 /* interface is disabled, changes to MAC will be reflected on next
1488 if (!netif_running(dev))
1491 umac_set_hw_addr(priv, dev->dev_addr);
1496 static void bcm_sysport_netif_start(struct net_device *dev)
1498 struct bcm_sysport_priv *priv = netdev_priv(dev);
1501 napi_enable(&priv->napi);
1503 /* Enable RX interrupt and TX ring full interrupt */
1504 intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL);
1506 phy_start(priv->phydev);
1508 /* Enable TX interrupts for the 32 TXQs */
1509 intrl2_1_mask_clear(priv, 0xffffffff);
1511 /* Last call before we start the real business */
1512 netif_tx_start_all_queues(dev);
1515 static void rbuf_init(struct bcm_sysport_priv *priv)
1519 reg = rbuf_readl(priv, RBUF_CONTROL);
1520 reg |= RBUF_4B_ALGN | RBUF_RSB_EN;
1521 rbuf_writel(priv, reg, RBUF_CONTROL);
1524 static int bcm_sysport_open(struct net_device *dev)
1526 struct bcm_sysport_priv *priv = netdev_priv(dev);
1533 /* Flush TX and RX FIFOs at TOPCTRL level */
1534 topctrl_flush(priv);
1536 /* Disable the UniMAC RX/TX */
1537 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 0);
1539 /* Enable RBUF 2bytes alignment and Receive Status Block */
1542 /* Set maximum frame length */
1543 umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1545 /* Set MAC address */
1546 umac_set_hw_addr(priv, dev->dev_addr);
1548 /* Read CRC forward */
1549 priv->crc_fwd = !!(umac_readl(priv, UMAC_CMD) & CMD_CRC_FWD);
1551 priv->phydev = of_phy_connect(dev, priv->phy_dn, bcm_sysport_adj_link,
1552 0, priv->phy_interface);
1553 if (!priv->phydev) {
1554 netdev_err(dev, "could not attach to PHY\n");
1558 /* Reset house keeping link status */
1559 priv->old_duplex = -1;
1560 priv->old_link = -1;
1561 priv->old_pause = -1;
1563 /* mask all interrupts and request them */
1564 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
1565 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
1566 intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1567 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
1568 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
1569 intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1571 ret = request_irq(priv->irq0, bcm_sysport_rx_isr, 0, dev->name, dev);
1573 netdev_err(dev, "failed to request RX interrupt\n");
1574 goto out_phy_disconnect;
1577 ret = request_irq(priv->irq1, bcm_sysport_tx_isr, 0, dev->name, dev);
1579 netdev_err(dev, "failed to request TX interrupt\n");
1583 /* Initialize both hardware and software ring */
1584 for (i = 0; i < dev->num_tx_queues; i++) {
1585 ret = bcm_sysport_init_tx_ring(priv, i);
1587 netdev_err(dev, "failed to initialize TX ring %d\n",
1589 goto out_free_tx_ring;
1593 /* Initialize linked-list */
1594 tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS);
1596 /* Initialize RX ring */
1597 ret = bcm_sysport_init_rx_ring(priv);
1599 netdev_err(dev, "failed to initialize RX ring\n");
1600 goto out_free_rx_ring;
1604 ret = rdma_enable_set(priv, 1);
1606 goto out_free_rx_ring;
1609 ret = tdma_enable_set(priv, 1);
1611 goto out_clear_rx_int;
1613 /* Turn on UniMAC TX/RX */
1614 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 1);
1616 bcm_sysport_netif_start(dev);
1621 intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL);
1623 bcm_sysport_fini_rx_ring(priv);
1625 for (i = 0; i < dev->num_tx_queues; i++)
1626 bcm_sysport_fini_tx_ring(priv, i);
1627 free_irq(priv->irq1, dev);
1629 free_irq(priv->irq0, dev);
1631 phy_disconnect(priv->phydev);
1635 static void bcm_sysport_netif_stop(struct net_device *dev)
1637 struct bcm_sysport_priv *priv = netdev_priv(dev);
1639 /* stop all software from updating hardware */
1640 netif_tx_stop_all_queues(dev);
1641 napi_disable(&priv->napi);
1642 phy_stop(priv->phydev);
1644 /* mask all interrupts */
1645 intrl2_0_mask_set(priv, 0xffffffff);
1646 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
1647 intrl2_1_mask_set(priv, 0xffffffff);
1648 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
1651 static int bcm_sysport_stop(struct net_device *dev)
1653 struct bcm_sysport_priv *priv = netdev_priv(dev);
1657 bcm_sysport_netif_stop(dev);
1659 /* Disable UniMAC RX */
1660 umac_enable_set(priv, CMD_RX_EN, 0);
1662 ret = tdma_enable_set(priv, 0);
1664 netdev_err(dev, "timeout disabling RDMA\n");
1668 /* Wait for a maximum packet size to be drained */
1669 usleep_range(2000, 3000);
1671 ret = rdma_enable_set(priv, 0);
1673 netdev_err(dev, "timeout disabling TDMA\n");
1677 /* Disable UniMAC TX */
1678 umac_enable_set(priv, CMD_TX_EN, 0);
1680 /* Free RX/TX rings SW structures */
1681 for (i = 0; i < dev->num_tx_queues; i++)
1682 bcm_sysport_fini_tx_ring(priv, i);
1683 bcm_sysport_fini_rx_ring(priv);
1685 free_irq(priv->irq0, dev);
1686 free_irq(priv->irq1, dev);
1688 /* Disconnect from PHY */
1689 phy_disconnect(priv->phydev);
1694 static struct ethtool_ops bcm_sysport_ethtool_ops = {
1695 .get_settings = bcm_sysport_get_settings,
1696 .set_settings = bcm_sysport_set_settings,
1697 .get_drvinfo = bcm_sysport_get_drvinfo,
1698 .get_msglevel = bcm_sysport_get_msglvl,
1699 .set_msglevel = bcm_sysport_set_msglvl,
1700 .get_link = ethtool_op_get_link,
1701 .get_strings = bcm_sysport_get_strings,
1702 .get_ethtool_stats = bcm_sysport_get_stats,
1703 .get_sset_count = bcm_sysport_get_sset_count,
1704 .get_wol = bcm_sysport_get_wol,
1705 .set_wol = bcm_sysport_set_wol,
1706 .get_coalesce = bcm_sysport_get_coalesce,
1707 .set_coalesce = bcm_sysport_set_coalesce,
1710 static const struct net_device_ops bcm_sysport_netdev_ops = {
1711 .ndo_start_xmit = bcm_sysport_xmit,
1712 .ndo_tx_timeout = bcm_sysport_tx_timeout,
1713 .ndo_open = bcm_sysport_open,
1714 .ndo_stop = bcm_sysport_stop,
1715 .ndo_set_features = bcm_sysport_set_features,
1716 .ndo_set_rx_mode = bcm_sysport_set_rx_mode,
1717 .ndo_set_mac_address = bcm_sysport_change_mac,
1720 #define REV_FMT "v%2x.%02x"
1722 static int bcm_sysport_probe(struct platform_device *pdev)
1724 struct bcm_sysport_priv *priv;
1725 struct device_node *dn;
1726 struct net_device *dev;
1727 const void *macaddr;
1732 dn = pdev->dev.of_node;
1733 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1735 /* Read the Transmit/Receive Queue properties */
1736 if (of_property_read_u32(dn, "systemport,num-txq", &txq))
1737 txq = TDMA_NUM_RINGS;
1738 if (of_property_read_u32(dn, "systemport,num-rxq", &rxq))
1741 dev = alloc_etherdev_mqs(sizeof(*priv), txq, rxq);
1745 /* Initialize private members */
1746 priv = netdev_priv(dev);
1748 priv->irq0 = platform_get_irq(pdev, 0);
1749 priv->irq1 = platform_get_irq(pdev, 1);
1750 priv->wol_irq = platform_get_irq(pdev, 2);
1751 if (priv->irq0 <= 0 || priv->irq1 <= 0) {
1752 dev_err(&pdev->dev, "invalid interrupts\n");
1757 priv->base = devm_ioremap_resource(&pdev->dev, r);
1758 if (IS_ERR(priv->base)) {
1759 ret = PTR_ERR(priv->base);
1766 priv->phy_interface = of_get_phy_mode(dn);
1767 /* Default to GMII interface mode */
1768 if (priv->phy_interface < 0)
1769 priv->phy_interface = PHY_INTERFACE_MODE_GMII;
1771 /* In the case of a fixed PHY, the DT node associated
1772 * to the PHY is the Ethernet MAC DT node.
1774 if (of_phy_is_fixed_link(dn)) {
1775 ret = of_phy_register_fixed_link(dn);
1777 dev_err(&pdev->dev, "failed to register fixed PHY\n");
1784 /* Initialize netdevice members */
1785 macaddr = of_get_mac_address(dn);
1786 if (!macaddr || !is_valid_ether_addr(macaddr)) {
1787 dev_warn(&pdev->dev, "using random Ethernet MAC\n");
1788 random_ether_addr(dev->dev_addr);
1790 ether_addr_copy(dev->dev_addr, macaddr);
1793 SET_NETDEV_DEV(dev, &pdev->dev);
1794 dev_set_drvdata(&pdev->dev, dev);
1795 dev->ethtool_ops = &bcm_sysport_ethtool_ops;
1796 dev->netdev_ops = &bcm_sysport_netdev_ops;
1797 netif_napi_add(dev, &priv->napi, bcm_sysport_poll, 64);
1799 /* HW supported features, none enabled by default */
1800 dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_HIGHDMA |
1801 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1803 /* Request the WOL interrupt and advertise suspend if available */
1804 priv->wol_irq_disabled = 1;
1805 ret = devm_request_irq(&pdev->dev, priv->wol_irq,
1806 bcm_sysport_wol_isr, 0, dev->name, priv);
1808 device_set_wakeup_capable(&pdev->dev, 1);
1810 /* Set the needed headroom once and for all */
1811 BUILD_BUG_ON(sizeof(struct bcm_tsb) != 8);
1812 dev->needed_headroom += sizeof(struct bcm_tsb);
1814 /* libphy will adjust the link state accordingly */
1815 netif_carrier_off(dev);
1817 ret = register_netdev(dev);
1819 dev_err(&pdev->dev, "failed to register net_device\n");
1823 priv->rev = topctrl_readl(priv, REV_CNTL) & REV_MASK;
1824 dev_info(&pdev->dev,
1825 "Broadcom SYSTEMPORT" REV_FMT
1826 " at 0x%p (irqs: %d, %d, TXQs: %d, RXQs: %d)\n",
1827 (priv->rev >> 8) & 0xff, priv->rev & 0xff,
1828 priv->base, priv->irq0, priv->irq1, txq, rxq);
1836 static int bcm_sysport_remove(struct platform_device *pdev)
1838 struct net_device *dev = dev_get_drvdata(&pdev->dev);
1840 /* Not much to do, ndo_close has been called
1841 * and we use managed allocations
1843 unregister_netdev(dev);
1845 dev_set_drvdata(&pdev->dev, NULL);
1850 #ifdef CONFIG_PM_SLEEP
1851 static int bcm_sysport_suspend_to_wol(struct bcm_sysport_priv *priv)
1853 struct net_device *ndev = priv->netdev;
1854 unsigned int timeout = 1000;
1857 /* Password has already been programmed */
1858 reg = umac_readl(priv, UMAC_MPD_CTRL);
1861 if (priv->wolopts & WAKE_MAGICSECURE)
1863 umac_writel(priv, reg, UMAC_MPD_CTRL);
1865 /* Make sure RBUF entered WoL mode as result */
1867 reg = rbuf_readl(priv, RBUF_STATUS);
1868 if (reg & RBUF_WOL_MODE)
1872 } while (timeout-- > 0);
1874 /* Do not leave the UniMAC RBUF matching only MPD packets */
1876 reg = umac_readl(priv, UMAC_MPD_CTRL);
1878 umac_writel(priv, reg, UMAC_MPD_CTRL);
1879 netif_err(priv, wol, ndev, "failed to enter WOL mode\n");
1883 /* UniMAC receive needs to be turned on */
1884 umac_enable_set(priv, CMD_RX_EN, 1);
1886 /* Enable the interrupt wake-up source */
1887 intrl2_0_mask_clear(priv, INTRL2_0_MPD);
1889 netif_dbg(priv, wol, ndev, "entered WOL mode\n");
1894 static int bcm_sysport_suspend(struct device *d)
1896 struct net_device *dev = dev_get_drvdata(d);
1897 struct bcm_sysport_priv *priv = netdev_priv(dev);
1902 if (!netif_running(dev))
1905 bcm_sysport_netif_stop(dev);
1907 phy_suspend(priv->phydev);
1909 netif_device_detach(dev);
1911 /* Disable UniMAC RX */
1912 umac_enable_set(priv, CMD_RX_EN, 0);
1914 ret = rdma_enable_set(priv, 0);
1916 netdev_err(dev, "RDMA timeout!\n");
1920 /* Disable RXCHK if enabled */
1921 if (priv->rx_chk_en) {
1922 reg = rxchk_readl(priv, RXCHK_CONTROL);
1924 rxchk_writel(priv, reg, RXCHK_CONTROL);
1929 topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL);
1931 ret = tdma_enable_set(priv, 0);
1933 netdev_err(dev, "TDMA timeout!\n");
1937 /* Wait for a packet boundary */
1938 usleep_range(2000, 3000);
1940 umac_enable_set(priv, CMD_TX_EN, 0);
1942 topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL);
1944 /* Free RX/TX rings SW structures */
1945 for (i = 0; i < dev->num_tx_queues; i++)
1946 bcm_sysport_fini_tx_ring(priv, i);
1947 bcm_sysport_fini_rx_ring(priv);
1949 /* Get prepared for Wake-on-LAN */
1950 if (device_may_wakeup(d) && priv->wolopts)
1951 ret = bcm_sysport_suspend_to_wol(priv);
1956 static int bcm_sysport_resume(struct device *d)
1958 struct net_device *dev = dev_get_drvdata(d);
1959 struct bcm_sysport_priv *priv = netdev_priv(dev);
1964 if (!netif_running(dev))
1969 /* We may have been suspended and never received a WOL event that
1970 * would turn off MPD detection, take care of that now
1972 bcm_sysport_resume_from_wol(priv);
1974 /* Initialize both hardware and software ring */
1975 for (i = 0; i < dev->num_tx_queues; i++) {
1976 ret = bcm_sysport_init_tx_ring(priv, i);
1978 netdev_err(dev, "failed to initialize TX ring %d\n",
1980 goto out_free_tx_rings;
1984 /* Initialize linked-list */
1985 tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS);
1987 /* Initialize RX ring */
1988 ret = bcm_sysport_init_rx_ring(priv);
1990 netdev_err(dev, "failed to initialize RX ring\n");
1991 goto out_free_rx_ring;
1994 netif_device_attach(dev);
1996 /* RX pipe enable */
1997 topctrl_writel(priv, 0, RX_FLUSH_CNTL);
1999 ret = rdma_enable_set(priv, 1);
2001 netdev_err(dev, "failed to enable RDMA\n");
2002 goto out_free_rx_ring;
2006 if (priv->rx_chk_en) {
2007 reg = rxchk_readl(priv, RXCHK_CONTROL);
2009 rxchk_writel(priv, reg, RXCHK_CONTROL);
2014 /* Set maximum frame length */
2015 umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
2017 /* Set MAC address */
2018 umac_set_hw_addr(priv, dev->dev_addr);
2020 umac_enable_set(priv, CMD_RX_EN, 1);
2022 /* TX pipe enable */
2023 topctrl_writel(priv, 0, TX_FLUSH_CNTL);
2025 umac_enable_set(priv, CMD_TX_EN, 1);
2027 ret = tdma_enable_set(priv, 1);
2029 netdev_err(dev, "TDMA timeout!\n");
2030 goto out_free_rx_ring;
2033 phy_resume(priv->phydev);
2035 bcm_sysport_netif_start(dev);
2040 bcm_sysport_fini_rx_ring(priv);
2042 for (i = 0; i < dev->num_tx_queues; i++)
2043 bcm_sysport_fini_tx_ring(priv, i);
2048 static SIMPLE_DEV_PM_OPS(bcm_sysport_pm_ops,
2049 bcm_sysport_suspend, bcm_sysport_resume);
2051 static const struct of_device_id bcm_sysport_of_match[] = {
2052 { .compatible = "brcm,systemport-v1.00" },
2053 { .compatible = "brcm,systemport" },
2057 static struct platform_driver bcm_sysport_driver = {
2058 .probe = bcm_sysport_probe,
2059 .remove = bcm_sysport_remove,
2061 .name = "brcm-systemport",
2062 .of_match_table = bcm_sysport_of_match,
2063 .pm = &bcm_sysport_pm_ops,
2066 module_platform_driver(bcm_sysport_driver);
2068 MODULE_AUTHOR("Broadcom Corporation");
2069 MODULE_DESCRIPTION("Broadcom System Port Ethernet MAC driver");
2070 MODULE_ALIAS("platform:brcm-systemport");
2071 MODULE_LICENSE("GPL");