2 * Broadcom BCM7xxx System Port Ethernet MAC driver
4 * Copyright (C) 2014 Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #ifndef __BCM_SYSPORT_H
12 #define __BCM_SYSPORT_H
14 #include <linux/if_vlan.h>
15 #include <linux/net_dim.h>
17 /* Receive/transmit descriptor format */
18 #define DESC_ADDR_HI_STATUS_LEN 0x00
19 #define DESC_ADDR_HI_SHIFT 0
20 #define DESC_ADDR_HI_MASK 0xff
21 #define DESC_STATUS_SHIFT 8
22 #define DESC_STATUS_MASK 0x3ff
23 #define DESC_LEN_SHIFT 18
24 #define DESC_LEN_MASK 0x7fff
25 #define DESC_ADDR_LO 0x04
27 /* HW supports 40-bit addressing hence the */
28 #define DESC_SIZE (WORDS_PER_DESC * sizeof(u32))
30 /* Default RX buffer allocation size */
31 #define RX_BUF_LENGTH 2048
33 /* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(4) + FCS(4) = 1526.
34 * 1536 is multiple of 256 bytes
36 #define ENET_BRCM_TAG_LEN 4
38 #define UMAC_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \
39 ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD)
41 /* Transmit status block */
44 #define PCP_DEI_MASK 0xf
46 #define VID_MASK 0xfff
48 #define L4_CSUM_PTR_MASK 0x1ff
49 #define L4_PTR_SHIFT 9
50 #define L4_PTR_MASK 0x1ff
51 #define L4_UDP (1 << 18)
52 #define L4_LENGTH_VALID (1 << 19)
53 #define DEST_MAP_SHIFT 20
54 #define DEST_MAP_MASK 0x1ff
57 /* Receive status block uses the same
58 * definitions as the DMA descriptor
65 /* Common Receive/Transmit status bits */
66 #define DESC_L4_CSUM (1 << 7)
67 #define DESC_SOP (1 << 8)
68 #define DESC_EOP (1 << 9)
70 /* Receive Status bits */
71 #define RX_STATUS_UCAST 0
72 #define RX_STATUS_BCAST 0x04
73 #define RX_STATUS_MCAST 0x08
74 #define RX_STATUS_L2_MCAST 0x0c
75 #define RX_STATUS_ERR (1 << 4)
76 #define RX_STATUS_OVFLOW (1 << 5)
77 #define RX_STATUS_PARSE_FAIL (1 << 6)
79 /* Transmit Status bits */
80 #define TX_STATUS_VLAN_NO_ACT 0x00
81 #define TX_STATUS_VLAN_PCP_TSB 0x01
82 #define TX_STATUS_VLAN_QUEUE 0x02
83 #define TX_STATUS_VLAN_VID_TSB 0x03
84 #define TX_STATUS_OWR_CRC (1 << 2)
85 #define TX_STATUS_APP_CRC (1 << 3)
86 #define TX_STATUS_BRCM_TAG_NO_ACT 0
87 #define TX_STATUS_BRCM_TAG_ZERO 0x10
88 #define TX_STATUS_BRCM_TAG_ONE_QUEUE 0x20
89 #define TX_STATUS_BRCM_TAG_ONE_TSB 0x30
90 #define TX_STATUS_SKIP_BYTES (1 << 6)
92 /* Specific register definitions */
93 #define SYS_PORT_TOPCTRL_OFFSET 0
95 #define REV_MASK 0xffff
97 #define RX_FLUSH_CNTL 0x04
98 #define RX_FLUSH (1 << 0)
100 #define TX_FLUSH_CNTL 0x08
101 #define TX_FLUSH (1 << 0)
103 #define MISC_CNTL 0x0c
104 #define SYS_CLK_SEL (1 << 0)
105 #define TDMA_EOP_SEL (1 << 1)
107 /* Level-2 Interrupt controller offsets and defines */
108 #define SYS_PORT_INTRL2_0_OFFSET 0x200
109 #define SYS_PORT_INTRL2_1_OFFSET 0x240
110 #define INTRL2_CPU_STATUS 0x00
111 #define INTRL2_CPU_SET 0x04
112 #define INTRL2_CPU_CLEAR 0x08
113 #define INTRL2_CPU_MASK_STATUS 0x0c
114 #define INTRL2_CPU_MASK_SET 0x10
115 #define INTRL2_CPU_MASK_CLEAR 0x14
117 /* Level-2 instance 0 interrupt bits */
118 #define INTRL2_0_GISB_ERR (1 << 0)
119 #define INTRL2_0_RBUF_OVFLOW (1 << 1)
120 #define INTRL2_0_TBUF_UNDFLOW (1 << 2)
121 #define INTRL2_0_MPD (1 << 3)
122 #define INTRL2_0_BRCM_MATCH_TAG (1 << 4)
123 #define INTRL2_0_RDMA_MBDONE (1 << 5)
124 #define INTRL2_0_OVER_MAX_THRESH (1 << 6)
125 #define INTRL2_0_BELOW_HYST_THRESH (1 << 7)
126 #define INTRL2_0_FREE_LIST_EMPTY (1 << 8)
127 #define INTRL2_0_TX_RING_FULL (1 << 9)
128 #define INTRL2_0_DESC_ALLOC_ERR (1 << 10)
129 #define INTRL2_0_UNEXP_PKTSIZE_ACK (1 << 11)
131 /* SYSTEMPORT Lite groups the TX queues interrupts on instance 0 */
132 #define INTRL2_0_TDMA_MBDONE_SHIFT 12
133 #define INTRL2_0_TDMA_MBDONE_MASK (0xffff << INTRL2_0_TDMA_MBDONE_SHIFT)
135 /* RXCHK offset and defines */
136 #define SYS_PORT_RXCHK_OFFSET 0x300
138 #define RXCHK_CONTROL 0x00
139 #define RXCHK_EN (1 << 0)
140 #define RXCHK_SKIP_FCS (1 << 1)
141 #define RXCHK_BAD_CSUM_DIS (1 << 2)
142 #define RXCHK_BRCM_TAG_EN (1 << 3)
143 #define RXCHK_BRCM_TAG_MATCH_SHIFT 4
144 #define RXCHK_BRCM_TAG_MATCH_MASK 0xff
145 #define RXCHK_PARSE_TNL (1 << 12)
146 #define RXCHK_VIOL_EN (1 << 13)
147 #define RXCHK_VIOL_DIS (1 << 14)
148 #define RXCHK_INCOM_PKT (1 << 15)
149 #define RXCHK_V6_DUPEXT_EN (1 << 16)
150 #define RXCHK_V6_DUPEXT_DIS (1 << 17)
151 #define RXCHK_ETHERTYPE_DIS (1 << 18)
152 #define RXCHK_L2_HDR_DIS (1 << 19)
153 #define RXCHK_L3_HDR_DIS (1 << 20)
154 #define RXCHK_MAC_RX_ERR_DIS (1 << 21)
155 #define RXCHK_PARSE_AUTH (1 << 22)
157 #define RXCHK_BRCM_TAG0 0x04
158 #define RXCHK_BRCM_TAG(i) ((i) * RXCHK_BRCM_TAG0)
159 #define RXCHK_BRCM_TAG0_MASK 0x24
160 #define RXCHK_BRCM_TAG_MASK(i) ((i) * RXCHK_BRCM_TAG0_MASK)
161 #define RXCHK_BRCM_TAG_MATCH_STATUS 0x44
162 #define RXCHK_ETHERTYPE 0x48
163 #define RXCHK_BAD_CSUM_CNTR 0x4C
164 #define RXCHK_OTHER_DISC_CNTR 0x50
166 /* TXCHCK offsets and defines */
167 #define SYS_PORT_TXCHK_OFFSET 0x380
168 #define TXCHK_PKT_RDY_THRESH 0x00
170 /* Receive buffer offset and defines */
171 #define SYS_PORT_RBUF_OFFSET 0x400
173 #define RBUF_CONTROL 0x00
174 #define RBUF_RSB_EN (1 << 0)
175 #define RBUF_4B_ALGN (1 << 1)
176 #define RBUF_BRCM_TAG_STRIP (1 << 2)
177 #define RBUF_BAD_PKT_DISC (1 << 3)
178 #define RBUF_RESUME_THRESH_SHIFT 4
179 #define RBUF_RESUME_THRESH_MASK 0xff
180 #define RBUF_OK_TO_SEND_SHIFT 12
181 #define RBUF_OK_TO_SEND_MASK 0xff
182 #define RBUF_CRC_REPLACE (1 << 20)
183 #define RBUF_OK_TO_SEND_MODE (1 << 21)
184 /* SYSTEMPORT Lite uses two bits here */
185 #define RBUF_RSB_SWAP0 (1 << 22)
186 #define RBUF_RSB_SWAP1 (1 << 23)
187 #define RBUF_ACPI_EN (1 << 23)
189 #define RBUF_PKT_RDY_THRESH 0x04
191 #define RBUF_STATUS 0x08
192 #define RBUF_WOL_MODE (1 << 0)
193 #define RBUF_MPD (1 << 1)
194 #define RBUF_ACPI (1 << 2)
196 #define RBUF_OVFL_DISC_CNTR 0x0c
197 #define RBUF_ERR_PKT_CNTR 0x10
199 /* Transmit buffer offset and defines */
200 #define SYS_PORT_TBUF_OFFSET 0x600
202 #define TBUF_CONTROL 0x00
203 #define TBUF_BP_EN (1 << 0)
204 #define TBUF_MAX_PKT_THRESH_SHIFT 1
205 #define TBUF_MAX_PKT_THRESH_MASK 0x1f
206 #define TBUF_FULL_THRESH_SHIFT 8
207 #define TBUF_FULL_THRESH_MASK 0x1f
209 /* UniMAC offset and defines */
210 #define SYS_PORT_UMAC_OFFSET 0x800
212 #define UMAC_CMD 0x008
213 #define CMD_TX_EN (1 << 0)
214 #define CMD_RX_EN (1 << 1)
215 #define CMD_SPEED_SHIFT 2
216 #define CMD_SPEED_10 0
217 #define CMD_SPEED_100 1
218 #define CMD_SPEED_1000 2
219 #define CMD_SPEED_2500 3
220 #define CMD_SPEED_MASK 3
221 #define CMD_PROMISC (1 << 4)
222 #define CMD_PAD_EN (1 << 5)
223 #define CMD_CRC_FWD (1 << 6)
224 #define CMD_PAUSE_FWD (1 << 7)
225 #define CMD_RX_PAUSE_IGNORE (1 << 8)
226 #define CMD_TX_ADDR_INS (1 << 9)
227 #define CMD_HD_EN (1 << 10)
228 #define CMD_SW_RESET (1 << 13)
229 #define CMD_LCL_LOOP_EN (1 << 15)
230 #define CMD_AUTO_CONFIG (1 << 22)
231 #define CMD_CNTL_FRM_EN (1 << 23)
232 #define CMD_NO_LEN_CHK (1 << 24)
233 #define CMD_RMT_LOOP_EN (1 << 25)
234 #define CMD_PRBL_EN (1 << 27)
235 #define CMD_TX_PAUSE_IGNORE (1 << 28)
236 #define CMD_TX_RX_EN (1 << 29)
237 #define CMD_RUNT_FILTER_DIS (1 << 30)
239 #define UMAC_MAC0 0x00c
240 #define UMAC_MAC1 0x010
241 #define UMAC_MAX_FRAME_LEN 0x014
243 #define UMAC_TX_FLUSH 0x334
245 #define UMAC_MIB_START 0x400
247 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
248 * between the end of TX stats and the beginning of the RX RUNT
250 #define UMAC_MIB_STAT_OFFSET 0xc
252 #define UMAC_MIB_CTRL 0x580
253 #define MIB_RX_CNT_RST (1 << 0)
254 #define MIB_RUNT_CNT_RST (1 << 1)
255 #define MIB_TX_CNT_RST (1 << 2)
257 /* These offsets are valid for SYSTEMPORT and SYSTEMPORT Lite */
258 #define UMAC_MPD_CTRL 0x620
259 #define MPD_EN (1 << 0)
260 #define MSEQ_LEN_SHIFT 16
261 #define MSEQ_LEN_MASK 0xff
262 #define PSW_EN (1 << 27)
264 #define UMAC_PSW_MS 0x624
265 #define UMAC_PSW_LS 0x628
266 #define UMAC_MDF_CTRL 0x650
267 #define UMAC_MDF_ADDR 0x654
269 /* Only valid on SYSTEMPORT Lite */
270 #define SYS_PORT_GIB_OFFSET 0x1000
272 #define GIB_CONTROL 0x00
273 #define GIB_TX_EN (1 << 0)
274 #define GIB_RX_EN (1 << 1)
275 #define GIB_TX_FLUSH (1 << 2)
276 #define GIB_RX_FLUSH (1 << 3)
277 #define GIB_GTX_CLK_SEL_SHIFT 4
278 #define GIB_GTX_CLK_EXT_CLK (0 << GIB_GTX_CLK_SEL_SHIFT)
279 #define GIB_GTX_CLK_125MHZ (1 << GIB_GTX_CLK_SEL_SHIFT)
280 #define GIB_GTX_CLK_250MHZ (2 << GIB_GTX_CLK_SEL_SHIFT)
281 #define GIB_FCS_STRIP (1 << 6)
282 #define GIB_LCL_LOOP_EN (1 << 7)
283 #define GIB_LCL_LOOP_TXEN (1 << 8)
284 #define GIB_RMT_LOOP_EN (1 << 9)
285 #define GIB_RMT_LOOP_RXEN (1 << 10)
286 #define GIB_RX_PAUSE_EN (1 << 11)
287 #define GIB_PREAMBLE_LEN_SHIFT 12
288 #define GIB_PREAMBLE_LEN_MASK 0xf
289 #define GIB_IPG_LEN_SHIFT 16
290 #define GIB_IPG_LEN_MASK 0x3f
291 #define GIB_PAD_EXTENSION_SHIFT 22
292 #define GIB_PAD_EXTENSION_MASK 0x3f
294 #define GIB_MAC1 0x08
295 #define GIB_MAC0 0x0c
297 /* Receive DMA offset and defines */
298 #define SYS_PORT_RDMA_OFFSET 0x2000
300 #define RDMA_CONTROL 0x1000
301 #define RDMA_EN (1 << 0)
302 #define RDMA_RING_CFG (1 << 1)
303 #define RDMA_DISC_EN (1 << 2)
304 #define RDMA_BUF_DATA_OFFSET_SHIFT 4
305 #define RDMA_BUF_DATA_OFFSET_MASK 0x3ff
307 #define RDMA_STATUS 0x1004
308 #define RDMA_DISABLED (1 << 0)
309 #define RDMA_DESC_RAM_INIT_BUSY (1 << 1)
310 #define RDMA_BP_STATUS (1 << 2)
312 #define RDMA_SCB_BURST_SIZE 0x1008
314 #define RDMA_RING_BUF_SIZE 0x100c
315 #define RDMA_RING_SIZE_SHIFT 16
317 #define RDMA_WRITE_PTR_HI 0x1010
318 #define RDMA_WRITE_PTR_LO 0x1014
319 #define RDMA_PROD_INDEX 0x1018
320 #define RDMA_PROD_INDEX_MASK 0xffff
322 #define RDMA_CONS_INDEX 0x101c
323 #define RDMA_CONS_INDEX_MASK 0xffff
325 #define RDMA_START_ADDR_HI 0x1020
326 #define RDMA_START_ADDR_LO 0x1024
327 #define RDMA_END_ADDR_HI 0x1028
328 #define RDMA_END_ADDR_LO 0x102c
330 #define RDMA_MBDONE_INTR 0x1030
331 #define RDMA_INTR_THRESH_MASK 0x1ff
332 #define RDMA_TIMEOUT_SHIFT 16
333 #define RDMA_TIMEOUT_MASK 0xffff
335 #define RDMA_XON_XOFF_THRESH 0x1034
336 #define RDMA_XON_XOFF_THRESH_MASK 0xffff
337 #define RDMA_XOFF_THRESH_SHIFT 16
339 #define RDMA_READ_PTR_HI 0x1038
340 #define RDMA_READ_PTR_LO 0x103c
342 #define RDMA_OVERRIDE 0x1040
343 #define RDMA_LE_MODE (1 << 0)
344 #define RDMA_REG_MODE (1 << 1)
346 #define RDMA_TEST 0x1044
347 #define RDMA_TP_OUT_SEL (1 << 0)
348 #define RDMA_MEM_SEL (1 << 1)
350 #define RDMA_DEBUG 0x1048
352 /* Transmit DMA offset and defines */
353 #define TDMA_NUM_RINGS 32 /* rings = queues */
354 #define TDMA_PORT_SIZE DESC_SIZE /* two 32-bits words */
356 #define SYS_PORT_TDMA_OFFSET 0x4000
357 #define TDMA_WRITE_PORT_OFFSET 0x0000
358 #define TDMA_WRITE_PORT_HI(i) (TDMA_WRITE_PORT_OFFSET + \
359 (i) * TDMA_PORT_SIZE)
360 #define TDMA_WRITE_PORT_LO(i) (TDMA_WRITE_PORT_OFFSET + \
361 sizeof(u32) + (i) * TDMA_PORT_SIZE)
363 #define TDMA_READ_PORT_OFFSET (TDMA_WRITE_PORT_OFFSET + \
364 (TDMA_NUM_RINGS * TDMA_PORT_SIZE))
365 #define TDMA_READ_PORT_HI(i) (TDMA_READ_PORT_OFFSET + \
366 (i) * TDMA_PORT_SIZE)
367 #define TDMA_READ_PORT_LO(i) (TDMA_READ_PORT_OFFSET + \
368 sizeof(u32) + (i) * TDMA_PORT_SIZE)
370 #define TDMA_READ_PORT_CMD_OFFSET (TDMA_READ_PORT_OFFSET + \
371 (TDMA_NUM_RINGS * TDMA_PORT_SIZE))
372 #define TDMA_READ_PORT_CMD(i) (TDMA_READ_PORT_CMD_OFFSET + \
375 #define TDMA_DESC_RING_00_BASE (TDMA_READ_PORT_CMD_OFFSET + \
376 (TDMA_NUM_RINGS * sizeof(u32)))
378 /* Register offsets and defines relatives to a specific ring number */
379 #define RING_HEAD_TAIL_PTR 0x00
380 #define RING_HEAD_MASK 0x7ff
381 #define RING_TAIL_SHIFT 11
382 #define RING_TAIL_MASK 0x7ff
383 #define RING_FLUSH (1 << 24)
384 #define RING_EN (1 << 25)
386 #define RING_COUNT 0x04
387 #define RING_COUNT_MASK 0x7ff
388 #define RING_BUFF_DONE_SHIFT 11
389 #define RING_BUFF_DONE_MASK 0x7ff
391 #define RING_MAX_HYST 0x08
392 #define RING_MAX_THRESH_MASK 0x7ff
393 #define RING_HYST_THRESH_SHIFT 11
394 #define RING_HYST_THRESH_MASK 0x7ff
396 #define RING_INTR_CONTROL 0x0c
397 #define RING_INTR_THRESH_MASK 0x7ff
398 #define RING_EMPTY_INTR_EN (1 << 15)
399 #define RING_TIMEOUT_SHIFT 16
400 #define RING_TIMEOUT_MASK 0xffff
402 #define RING_PROD_CONS_INDEX 0x10
403 #define RING_PROD_INDEX_MASK 0xffff
404 #define RING_CONS_INDEX_SHIFT 16
405 #define RING_CONS_INDEX_MASK 0xffff
407 #define RING_MAPPING 0x14
408 #define RING_QID_MASK 0x7
409 #define RING_PORT_ID_SHIFT 3
410 #define RING_PORT_ID_MASK 0x7
411 #define RING_IGNORE_STATUS (1 << 6)
412 #define RING_FAILOVER_EN (1 << 7)
413 #define RING_CREDIT_SHIFT 8
414 #define RING_CREDIT_MASK 0xffff
416 #define RING_PCP_DEI_VID 0x18
417 #define RING_VID_MASK 0x7ff
418 #define RING_DEI (1 << 12)
419 #define RING_PCP_SHIFT 13
420 #define RING_PCP_MASK 0x7
421 #define RING_PKT_SIZE_ADJ_SHIFT 16
422 #define RING_PKT_SIZE_ADJ_MASK 0xf
424 #define TDMA_DESC_RING_SIZE 28
426 /* Defininition for a given TX ring base address */
427 #define TDMA_DESC_RING_BASE(i) (TDMA_DESC_RING_00_BASE + \
428 ((i) * TDMA_DESC_RING_SIZE))
430 /* Ring indexed register addreses */
431 #define TDMA_DESC_RING_HEAD_TAIL_PTR(i) (TDMA_DESC_RING_BASE(i) + \
433 #define TDMA_DESC_RING_COUNT(i) (TDMA_DESC_RING_BASE(i) + \
435 #define TDMA_DESC_RING_MAX_HYST(i) (TDMA_DESC_RING_BASE(i) + \
437 #define TDMA_DESC_RING_INTR_CONTROL(i) (TDMA_DESC_RING_BASE(i) + \
439 #define TDMA_DESC_RING_PROD_CONS_INDEX(i) \
440 (TDMA_DESC_RING_BASE(i) + \
441 RING_PROD_CONS_INDEX)
442 #define TDMA_DESC_RING_MAPPING(i) (TDMA_DESC_RING_BASE(i) + \
444 #define TDMA_DESC_RING_PCP_DEI_VID(i) (TDMA_DESC_RING_BASE(i) + \
447 #define TDMA_CONTROL 0x600
450 /* Uses 2 bits on SYSTEMPORT Lite and shifts everything by 1 bit, we
451 * keep the SYSTEMPORT layout here and adjust with tdma_control_bit()
456 #define BUF_DATA_OFFSET_SHIFT 4
457 #define BUF_DATA_OFFSET_MASK 0x3ff
459 #define SW_BRCM_TAG 15
460 #define WNC_KPT_SIZE_UPDATE 16
461 #define SYNC_PKT_SIZE 17
462 #define ACH_TXDONE_DELAY_SHIFT 18
463 #define ACH_TXDONE_DELAY_MASK 0xff
465 #define TDMA_STATUS 0x604
466 #define TDMA_DISABLED (1 << 0)
467 #define TDMA_LL_RAM_INIT_BUSY (1 << 1)
469 #define TDMA_SCB_BURST_SIZE 0x608
470 #define TDMA_OVER_MAX_THRESH_STATUS 0x60c
471 #define TDMA_OVER_HYST_THRESH_STATUS 0x610
472 #define TDMA_TPID 0x614
474 #define TDMA_FREE_LIST_HEAD_TAIL_PTR 0x618
475 #define TDMA_FREE_HEAD_MASK 0x7ff
476 #define TDMA_FREE_TAIL_SHIFT 11
477 #define TDMA_FREE_TAIL_MASK 0x7ff
479 #define TDMA_FREE_LIST_COUNT 0x61c
480 #define TDMA_FREE_LIST_COUNT_MASK 0x7ff
482 #define TDMA_TIER2_ARB_CTRL 0x620
483 #define TDMA_ARB_MODE_RR 0
484 #define TDMA_ARB_MODE_WEIGHT_RR 0x1
485 #define TDMA_ARB_MODE_STRICT 0x2
486 #define TDMA_ARB_MODE_DEFICIT_RR 0x3
487 #define TDMA_CREDIT_SHIFT 4
488 #define TDMA_CREDIT_MASK 0xffff
490 #define TDMA_TIER1_ARB_0_CTRL 0x624
491 #define TDMA_ARB_EN (1 << 0)
493 #define TDMA_TIER1_ARB_0_QUEUE_EN 0x628
494 #define TDMA_TIER1_ARB_1_CTRL 0x62c
495 #define TDMA_TIER1_ARB_1_QUEUE_EN 0x630
496 #define TDMA_TIER1_ARB_2_CTRL 0x634
497 #define TDMA_TIER1_ARB_2_QUEUE_EN 0x638
498 #define TDMA_TIER1_ARB_3_CTRL 0x63c
499 #define TDMA_TIER1_ARB_3_QUEUE_EN 0x640
501 #define TDMA_SCB_ENDIAN_OVERRIDE 0x644
502 #define TDMA_LE_MODE (1 << 0)
503 #define TDMA_REG_MODE (1 << 1)
505 #define TDMA_TEST 0x648
506 #define TDMA_TP_OUT_SEL (1 << 0)
507 #define TDMA_MEM_TM (1 << 1)
509 #define TDMA_DEBUG 0x64c
511 /* Transmit/Receive descriptor */
517 /* Number of Receive hardware descriptor words */
518 #define SP_NUM_HW_RX_DESC_WORDS 1024
519 #define SP_LT_NUM_HW_RX_DESC_WORDS 256
521 /* Internal linked-list RAM size */
522 #define SP_NUM_TX_DESC 1536
523 #define SP_LT_NUM_TX_DESC 256
525 #define WORDS_PER_DESC (sizeof(struct dma_desc) / sizeof(u32))
527 /* Rx/Tx common counter group.*/
528 struct bcm_sysport_pkt_counters {
529 u32 cnt_64; /* RO Received/Transmited 64 bytes packet */
530 u32 cnt_127; /* RO Rx/Tx 127 bytes packet */
531 u32 cnt_255; /* RO Rx/Tx 65-255 bytes packet */
532 u32 cnt_511; /* RO Rx/Tx 256-511 bytes packet */
533 u32 cnt_1023; /* RO Rx/Tx 512-1023 bytes packet */
534 u32 cnt_1518; /* RO Rx/Tx 1024-1518 bytes packet */
535 u32 cnt_mgv; /* RO Rx/Tx 1519-1522 good VLAN packet */
536 u32 cnt_2047; /* RO Rx/Tx 1522-2047 bytes packet*/
537 u32 cnt_4095; /* RO Rx/Tx 2048-4095 bytes packet*/
538 u32 cnt_9216; /* RO Rx/Tx 4096-9216 bytes packet*/
541 /* RSV, Receive Status Vector */
542 struct bcm_sysport_rx_counters {
543 struct bcm_sysport_pkt_counters pkt_cnt;
544 u32 pkt; /* RO (0x428) Received pkt count*/
545 u32 bytes; /* RO Received byte count */
546 u32 mca; /* RO # of Received multicast pkt */
547 u32 bca; /* RO # of Receive broadcast pkt */
548 u32 fcs; /* RO # of Received FCS error */
549 u32 cf; /* RO # of Received control frame pkt*/
550 u32 pf; /* RO # of Received pause frame pkt */
551 u32 uo; /* RO # of unknown op code pkt */
552 u32 aln; /* RO # of alignment error count */
553 u32 flr; /* RO # of frame length out of range count */
554 u32 cde; /* RO # of code error pkt */
555 u32 fcr; /* RO # of carrier sense error pkt */
556 u32 ovr; /* RO # of oversize pkt*/
557 u32 jbr; /* RO # of jabber count */
558 u32 mtue; /* RO # of MTU error pkt*/
559 u32 pok; /* RO # of Received good pkt */
560 u32 uc; /* RO # of unicast pkt */
561 u32 ppp; /* RO # of PPP pkt */
562 u32 rcrc; /* RO (0x470),# of CRC match pkt */
565 /* TSV, Transmit Status Vector */
566 struct bcm_sysport_tx_counters {
567 struct bcm_sysport_pkt_counters pkt_cnt;
568 u32 pkts; /* RO (0x4a8) Transmited pkt */
569 u32 mca; /* RO # of xmited multicast pkt */
570 u32 bca; /* RO # of xmited broadcast pkt */
571 u32 pf; /* RO # of xmited pause frame count */
572 u32 cf; /* RO # of xmited control frame count */
573 u32 fcs; /* RO # of xmited FCS error count */
574 u32 ovr; /* RO # of xmited oversize pkt */
575 u32 drf; /* RO # of xmited deferral pkt */
576 u32 edf; /* RO # of xmited Excessive deferral pkt*/
577 u32 scl; /* RO # of xmited single collision pkt */
578 u32 mcl; /* RO # of xmited multiple collision pkt*/
579 u32 lcl; /* RO # of xmited late collision pkt */
580 u32 ecl; /* RO # of xmited excessive collision pkt*/
581 u32 frg; /* RO # of xmited fragments pkt*/
582 u32 ncl; /* RO # of xmited total collision count */
583 u32 jbr; /* RO # of xmited jabber count*/
584 u32 bytes; /* RO # of xmited byte count */
585 u32 pok; /* RO # of xmited good pkt */
586 u32 uc; /* RO (0x4f0) # of xmited unicast pkt */
589 struct bcm_sysport_mib {
590 struct bcm_sysport_rx_counters rx;
591 struct bcm_sysport_tx_counters tx;
594 u32 rx_runt_fcs_align;
597 u32 rxchk_other_pkt_disc;
600 u32 alloc_rx_buff_failed;
605 /* HW maintains a large list of counters */
606 enum bcm_sysport_stat_type {
607 BCM_SYSPORT_STAT_NETDEV = -1,
608 BCM_SYSPORT_STAT_NETDEV64,
609 BCM_SYSPORT_STAT_MIB_RX,
610 BCM_SYSPORT_STAT_MIB_TX,
611 BCM_SYSPORT_STAT_RUNT,
612 BCM_SYSPORT_STAT_RXCHK,
613 BCM_SYSPORT_STAT_RBUF,
614 BCM_SYSPORT_STAT_SOFT,
617 /* Macros to help define ethtool statistics */
618 #define STAT_NETDEV(m) { \
619 .stat_string = __stringify(m), \
620 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
621 .stat_offset = offsetof(struct net_device_stats, m), \
622 .type = BCM_SYSPORT_STAT_NETDEV, \
625 #define STAT_NETDEV64(m) { \
626 .stat_string = __stringify(m), \
627 .stat_sizeof = sizeof(((struct bcm_sysport_stats64 *)0)->m), \
628 .stat_offset = offsetof(struct bcm_sysport_stats64, m), \
629 .type = BCM_SYSPORT_STAT_NETDEV64, \
632 #define STAT_MIB(str, m, _type) { \
633 .stat_string = str, \
634 .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \
635 .stat_offset = offsetof(struct bcm_sysport_priv, m), \
639 #define STAT_MIB_RX(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_MIB_RX)
640 #define STAT_MIB_TX(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_MIB_TX)
641 #define STAT_RUNT(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_RUNT)
642 #define STAT_MIB_SOFT(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_SOFT)
644 #define STAT_RXCHK(str, m, ofs) { \
645 .stat_string = str, \
646 .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \
647 .stat_offset = offsetof(struct bcm_sysport_priv, m), \
648 .type = BCM_SYSPORT_STAT_RXCHK, \
652 #define STAT_RBUF(str, m, ofs) { \
653 .stat_string = str, \
654 .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \
655 .stat_offset = offsetof(struct bcm_sysport_priv, m), \
656 .type = BCM_SYSPORT_STAT_RBUF, \
660 /* TX bytes and packets */
661 #define NUM_SYSPORT_TXQ_STAT 2
663 struct bcm_sysport_stats {
664 char stat_string[ETH_GSTRING_LEN];
667 enum bcm_sysport_stat_type type;
668 /* reg offset from UMAC base for misc counters */
672 struct bcm_sysport_stats64 {
673 /* 64bit stats on 32bit/64bit Machine */
680 /* Software house keeping helper structure */
681 struct bcm_sysport_cb {
682 struct sk_buff *skb; /* SKB for RX packets */
683 void __iomem *bd_addr; /* Buffer descriptor PHYS addr */
685 DEFINE_DMA_UNMAP_ADDR(dma_addr);
686 DEFINE_DMA_UNMAP_LEN(dma_len);
689 enum bcm_sysport_type {
694 struct bcm_sysport_hw_params {
696 unsigned int num_rx_desc_words;
699 struct bcm_sysport_net_dim {
702 unsigned long packets;
709 /* Software view of the TX ring */
710 struct bcm_sysport_tx_ring {
711 spinlock_t lock; /* Ring lock for tx reclaim/xmit */
712 struct napi_struct napi; /* NAPI per tx queue */
713 dma_addr_t desc_dma; /* DMA cookie */
714 unsigned int index; /* Ring index */
715 unsigned int size; /* Ring current size */
716 unsigned int alloc_size; /* Ring one-time allocated size */
717 unsigned int desc_count; /* Number of descriptors */
718 unsigned int curr_desc; /* Current descriptor */
719 unsigned int c_index; /* Last consumer index */
720 unsigned int clean_index; /* Current clean index */
721 struct bcm_sysport_cb *cbs; /* Transmit control blocks */
722 struct dma_desc *desc_cpu; /* CPU view of the descriptor */
723 struct bcm_sysport_priv *priv; /* private context backpointer */
724 unsigned long packets; /* packets statistics */
725 unsigned long bytes; /* bytes statistics */
726 unsigned int switch_queue; /* switch port queue number */
727 unsigned int switch_port; /* switch port queue number */
728 bool inspect; /* inspect switch port and queue */
731 /* Driver private structure */
732 struct bcm_sysport_priv {
739 unsigned int num_rx_desc_words;
740 struct napi_struct napi ____cacheline_aligned;
741 struct net_device *netdev;
742 struct platform_device *pdev;
748 struct bcm_sysport_tx_ring *tx_rings;
751 void __iomem *rx_bds;
752 struct bcm_sysport_cb *rx_cbs;
753 unsigned int num_rx_bds;
754 unsigned int rx_read_ptr;
755 unsigned int rx_c_index;
757 struct bcm_sysport_net_dim dim;
760 struct device_node *phy_dn;
761 phy_interface_t phy_interface;
767 unsigned int rx_chk_en:1;
768 unsigned int tsb_en:1;
769 unsigned int crc_fwd:1;
772 unsigned int wol_irq_disabled:1;
774 /* MIB related fields */
775 struct bcm_sysport_mib mib;
780 struct bcm_sysport_stats64 stats64;
782 /* For atomic update generic 64bit value on 32bit Machine */
783 struct u64_stats_sync syncp;
785 /* map information between switch port queues and local queues */
786 struct notifier_block dsa_notifier;
787 unsigned int per_port_num_tx_queues;
788 unsigned long queue_bitmap;
789 struct bcm_sysport_tx_ring *ring_map[DSA_MAX_PORTS * 8];
792 #endif /* __BCM_SYSPORT_H */