drivers/net/ethernet/broadcom/genet/bcmgenet.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Broadcom GENET (Gigabit Ethernet) controller driver
   4  *
   5  * Copyright (c) 2014-2019 Broadcom
   6  */
   7
   8 #define pr_fmt(fmt)                             "bcmgenet: " fmt
   9
  10 #include <linux/acpi.h>
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/sched.h>
  14 #include <linux/types.h>
  15 #include <linux/fcntl.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/string.h>
  18 #include <linux/if_ether.h>
  19 #include <linux/init.h>
  20 #include <linux/errno.h>
  21 #include <linux/delay.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/pm.h>
  25 #include <linux/clk.h>
  26 #include <linux/of.h>
  27 #include <linux/of_address.h>
  28 #include <linux/of_irq.h>
  29 #include <linux/of_net.h>
  30 #include <linux/of_platform.h>
  31 #include <net/arp.h>
  32
  33 #include <linux/mii.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/inetdevice.h>
  37 #include <linux/etherdevice.h>
  38 #include <linux/skbuff.h>
  39 #include <linux/in.h>
  40 #include <linux/ip.h>
  41 #include <linux/ipv6.h>
  42 #include <linux/phy.h>
  43 #include <linux/platform_data/bcmgenet.h>
  44
  45 #include <asm/unaligned.h>
  46
  47 #include "bcmgenet.h"
  48
  49 /* Maximum number of hardware queues, downsized if needed */
  50 #define GENET_MAX_MQ_CNT        4
  51
  52 /* Default highest priority queue for multi queue support */
  53 #define GENET_Q0_PRIORITY       0
  54
  55 #define GENET_Q16_RX_BD_CNT     \
  56         (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
  57 #define GENET_Q16_TX_BD_CNT     \
  58         (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
  59
  60 #define RX_BUF_LENGTH           2048
  61 #define SKB_ALIGNMENT           32
  62
  63 /* Tx/Rx DMA register offset, skip 256 descriptors */
  64 #define WORDS_PER_BD(p)         (p->hw_params->words_per_bd)
  65 #define DMA_DESC_SIZE           (WORDS_PER_BD(priv) * sizeof(u32))
  66
  67 #define GENET_TDMA_REG_OFF      (priv->hw_params->tdma_offset + \
  68                                 TOTAL_DESC * DMA_DESC_SIZE)
  69
  70 #define GENET_RDMA_REG_OFF      (priv->hw_params->rdma_offset + \
  71                                 TOTAL_DESC * DMA_DESC_SIZE)
  72
  73 static inline void bcmgenet_writel(u32 value, void __iomem *offset)
  74 {
  75         /* MIPS chips strapped for BE will automagically configure the
  76          * peripheral registers for CPU-native byte order.
  77          */
  78         if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
  79                 __raw_writel(value, offset);
  80         else
  81                 writel_relaxed(value, offset);
  82 }
  83
  84 static inline u32 bcmgenet_readl(void __iomem *offset)
  85 {
  86         if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
  87                 return __raw_readl(offset);
  88         else
  89                 return readl_relaxed(offset);
  90 }
  91
  92 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
  93                                              void __iomem *d, u32 value)
  94 {
  95         bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS);
  96 }
  97
  98 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
  99                                     void __iomem *d,
 100                                     dma_addr_t addr)
 101 {
 102         bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
 103
 104         /* Register writes to GISB bus can take couple hundred nanoseconds
 105          * and are done for each packet, save these expensive writes unless
 106          * the platform is explicitly configured for 64-bits/LPAE.
 107          */
 108 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 109         if (priv->hw_params->flags & GENET_HAS_40BITS)
 110                 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
 111 #endif
 112 }
 113
 114 /* Combined address + length/status setter */
 115 static inline void dmadesc_set(struct bcmgenet_priv *priv,
 116                                void __iomem *d, dma_addr_t addr, u32 val)
 117 {
 118         dmadesc_set_addr(priv, d, addr);
 119         dmadesc_set_length_status(priv, d, val);
 120 }
 121
 122 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
 123                                           void __iomem *d)
 124 {
 125         dma_addr_t addr;
 126
 127         addr = bcmgenet_readl(d + DMA_DESC_ADDRESS_LO);
 128
 129         /* Register writes to GISB bus can take couple hundred nanoseconds
 130          * and are done for each packet, save these expensive writes unless
 131          * the platform is explicitly configured for 64-bits/LPAE.
 132          */
 133 #ifdef CONFIG_PHYS_ADDR_T_64BIT
 134         if (priv->hw_params->flags & GENET_HAS_40BITS)
 135                 addr |= (u64)bcmgenet_readl(d + DMA_DESC_ADDRESS_HI) << 32;
 136 #endif
 137         return addr;
 138 }
 139
 140 #define GENET_VER_FMT   "%1d.%1d EPHY: 0x%04x"
 141
 142 #define GENET_MSG_DEFAULT       (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
 143                                 NETIF_MSG_LINK)
 144
 145 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
 146 {
 147         if (GENET_IS_V1(priv))
 148                 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
 149         else
 150                 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
 151 }
 152
 153 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 154 {
 155         if (GENET_IS_V1(priv))
 156                 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
 157         else
 158                 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
 159 }
 160
 161 /* These macros are defined to deal with register map change
 162  * between GENET1.1 and GENET2. Only those currently being used
 163  * by driver are defined.
 164  */
 165 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
 166 {
 167         if (GENET_IS_V1(priv))
 168                 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
 169         else
 170                 return bcmgenet_readl(priv->base +
 171                                       priv->hw_params->tbuf_offset + TBUF_CTRL);
 172 }
 173
 174 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 175 {
 176         if (GENET_IS_V1(priv))
 177                 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
 178         else
 179                 bcmgenet_writel(val, priv->base +
 180                                 priv->hw_params->tbuf_offset + TBUF_CTRL);
 181 }
 182
 183 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
 184 {
 185         if (GENET_IS_V1(priv))
 186                 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
 187         else
 188                 return bcmgenet_readl(priv->base +
 189                                       priv->hw_params->tbuf_offset + TBUF_BP_MC);
 190 }
 191
 192 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
 193 {
 194         if (GENET_IS_V1(priv))
 195                 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
 196         else
 197                 bcmgenet_writel(val, priv->base +
 198                                 priv->hw_params->tbuf_offset + TBUF_BP_MC);
 199 }
 200
 201 /* RX/TX DMA register accessors */
 202 enum dma_reg {
 203         DMA_RING_CFG = 0,
 204         DMA_CTRL,
 205         DMA_STATUS,
 206         DMA_SCB_BURST_SIZE,
 207         DMA_ARB_CTRL,
 208         DMA_PRIORITY_0,
 209         DMA_PRIORITY_1,
 210         DMA_PRIORITY_2,
 211         DMA_INDEX2RING_0,
 212         DMA_INDEX2RING_1,
 213         DMA_INDEX2RING_2,
 214         DMA_INDEX2RING_3,
 215         DMA_INDEX2RING_4,
 216         DMA_INDEX2RING_5,
 217         DMA_INDEX2RING_6,
 218         DMA_INDEX2RING_7,
 219         DMA_RING0_TIMEOUT,
 220         DMA_RING1_TIMEOUT,
 221         DMA_RING2_TIMEOUT,
 222         DMA_RING3_TIMEOUT,
 223         DMA_RING4_TIMEOUT,
 224         DMA_RING5_TIMEOUT,
 225         DMA_RING6_TIMEOUT,
 226         DMA_RING7_TIMEOUT,
 227         DMA_RING8_TIMEOUT,
 228         DMA_RING9_TIMEOUT,
 229         DMA_RING10_TIMEOUT,
 230         DMA_RING11_TIMEOUT,
 231         DMA_RING12_TIMEOUT,
 232         DMA_RING13_TIMEOUT,
 233         DMA_RING14_TIMEOUT,
 234         DMA_RING15_TIMEOUT,
 235         DMA_RING16_TIMEOUT,
 236 };
 237
 238 static const u8 bcmgenet_dma_regs_v3plus[] = {
 239         [DMA_RING_CFG]          = 0x00,
 240         [DMA_CTRL]              = 0x04,
 241         [DMA_STATUS]            = 0x08,
 242         [DMA_SCB_BURST_SIZE]    = 0x0C,
 243         [DMA_ARB_CTRL]          = 0x2C,
 244         [DMA_PRIORITY_0]        = 0x30,
 245         [DMA_PRIORITY_1]        = 0x34,
 246         [DMA_PRIORITY_2]        = 0x38,
 247         [DMA_RING0_TIMEOUT]     = 0x2C,
 248         [DMA_RING1_TIMEOUT]     = 0x30,
 249         [DMA_RING2_TIMEOUT]     = 0x34,
 250         [DMA_RING3_TIMEOUT]     = 0x38,
 251         [DMA_RING4_TIMEOUT]     = 0x3c,
 252         [DMA_RING5_TIMEOUT]     = 0x40,
 253         [DMA_RING6_TIMEOUT]     = 0x44,
 254         [DMA_RING7_TIMEOUT]     = 0x48,
 255         [DMA_RING8_TIMEOUT]     = 0x4c,
 256         [DMA_RING9_TIMEOUT]     = 0x50,
 257         [DMA_RING10_TIMEOUT]    = 0x54,
 258         [DMA_RING11_TIMEOUT]    = 0x58,
 259         [DMA_RING12_TIMEOUT]    = 0x5c,
 260         [DMA_RING13_TIMEOUT]    = 0x60,
 261         [DMA_RING14_TIMEOUT]    = 0x64,
 262         [DMA_RING15_TIMEOUT]    = 0x68,
 263         [DMA_RING16_TIMEOUT]    = 0x6C,
 264         [DMA_INDEX2RING_0]      = 0x70,
 265         [DMA_INDEX2RING_1]      = 0x74,
 266         [DMA_INDEX2RING_2]      = 0x78,
 267         [DMA_INDEX2RING_3]      = 0x7C,
 268         [DMA_INDEX2RING_4]      = 0x80,
 269         [DMA_INDEX2RING_5]      = 0x84,
 270         [DMA_INDEX2RING_6]      = 0x88,
 271         [DMA_INDEX2RING_7]      = 0x8C,
 272 };
 273
 274 static const u8 bcmgenet_dma_regs_v2[] = {
 275         [DMA_RING_CFG]          = 0x00,
 276         [DMA_CTRL]              = 0x04,
 277         [DMA_STATUS]            = 0x08,
 278         [DMA_SCB_BURST_SIZE]    = 0x0C,
 279         [DMA_ARB_CTRL]          = 0x30,
 280         [DMA_PRIORITY_0]        = 0x34,
 281         [DMA_PRIORITY_1]        = 0x38,
 282         [DMA_PRIORITY_2]        = 0x3C,
 283         [DMA_RING0_TIMEOUT]     = 0x2C,
 284         [DMA_RING1_TIMEOUT]     = 0x30,
 285         [DMA_RING2_TIMEOUT]     = 0x34,
 286         [DMA_RING3_TIMEOUT]     = 0x38,
 287         [DMA_RING4_TIMEOUT]     = 0x3c,
 288         [DMA_RING5_TIMEOUT]     = 0x40,
 289         [DMA_RING6_TIMEOUT]     = 0x44,
 290         [DMA_RING7_TIMEOUT]     = 0x48,
 291         [DMA_RING8_TIMEOUT]     = 0x4c,
 292         [DMA_RING9_TIMEOUT]     = 0x50,
 293         [DMA_RING10_TIMEOUT]    = 0x54,
 294         [DMA_RING11_TIMEOUT]    = 0x58,
 295         [DMA_RING12_TIMEOUT]    = 0x5c,
 296         [DMA_RING13_TIMEOUT]    = 0x60,
 297         [DMA_RING14_TIMEOUT]    = 0x64,
 298         [DMA_RING15_TIMEOUT]    = 0x68,
 299         [DMA_RING16_TIMEOUT]    = 0x6C,
 300 };
 301
 302 static const u8 bcmgenet_dma_regs_v1[] = {
 303         [DMA_CTRL]              = 0x00,
 304         [DMA_STATUS]            = 0x04,
 305         [DMA_SCB_BURST_SIZE]    = 0x0C,
 306         [DMA_ARB_CTRL]          = 0x30,
 307         [DMA_PRIORITY_0]        = 0x34,
 308         [DMA_PRIORITY_1]        = 0x38,
 309         [DMA_PRIORITY_2]        = 0x3C,
 310         [DMA_RING0_TIMEOUT]     = 0x2C,
 311         [DMA_RING1_TIMEOUT]     = 0x30,
 312         [DMA_RING2_TIMEOUT]     = 0x34,
 313         [DMA_RING3_TIMEOUT]     = 0x38,
 314         [DMA_RING4_TIMEOUT]     = 0x3c,
 315         [DMA_RING5_TIMEOUT]     = 0x40,
 316         [DMA_RING6_TIMEOUT]     = 0x44,
 317         [DMA_RING7_TIMEOUT]     = 0x48,
 318         [DMA_RING8_TIMEOUT]     = 0x4c,
 319         [DMA_RING9_TIMEOUT]     = 0x50,
 320         [DMA_RING10_TIMEOUT]    = 0x54,
 321         [DMA_RING11_TIMEOUT]    = 0x58,
 322         [DMA_RING12_TIMEOUT]    = 0x5c,
 323         [DMA_RING13_TIMEOUT]    = 0x60,
 324         [DMA_RING14_TIMEOUT]    = 0x64,
 325         [DMA_RING15_TIMEOUT]    = 0x68,
 326         [DMA_RING16_TIMEOUT]    = 0x6C,
 327 };
 328
 329 /* Set at runtime once bcmgenet version is known */
 330 static const u8 *bcmgenet_dma_regs;
 331
 332 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
 333 {
 334         return netdev_priv(dev_get_drvdata(dev));
 335 }
 336
 337 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
 338                                       enum dma_reg r)
 339 {
 340         return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
 341                               DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 342 }
 343
 344 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
 345                                         u32 val, enum dma_reg r)
 346 {
 347         bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
 348                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 349 }
 350
 351 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
 352                                       enum dma_reg r)
 353 {
 354         return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
 355                               DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 356 }
 357
 358 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
 359                                         u32 val, enum dma_reg r)
 360 {
 361         bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
 362                         DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 363 }
 364
 365 /* RDMA/TDMA ring registers and accessors
 366  * we merge the common fields and just prefix with T/D the registers
 367  * having different meaning depending on the direction
 368  */
 369 enum dma_ring_reg {
 370         TDMA_READ_PTR = 0,
 371         RDMA_WRITE_PTR = TDMA_READ_PTR,
 372         TDMA_READ_PTR_HI,
 373         RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
 374         TDMA_CONS_INDEX,
 375         RDMA_PROD_INDEX = TDMA_CONS_INDEX,
 376         TDMA_PROD_INDEX,
 377         RDMA_CONS_INDEX = TDMA_PROD_INDEX,
 378         DMA_RING_BUF_SIZE,
 379         DMA_START_ADDR,
 380         DMA_START_ADDR_HI,
 381         DMA_END_ADDR,
 382         DMA_END_ADDR_HI,
 383         DMA_MBUF_DONE_THRESH,
 384         TDMA_FLOW_PERIOD,
 385         RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
 386         TDMA_WRITE_PTR,
 387         RDMA_READ_PTR = TDMA_WRITE_PTR,
 388         TDMA_WRITE_PTR_HI,
 389         RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
 390 };
 391
 392 /* GENET v4 supports 40-bits pointer addressing
 393  * for obvious reasons the LO and HI word parts
 394  * are contiguous, but this offsets the other
 395  * registers.
 396  */
 397 static const u8 genet_dma_ring_regs_v4[] = {
 398         [TDMA_READ_PTR]                 = 0x00,
 399         [TDMA_READ_PTR_HI]              = 0x04,
 400         [TDMA_CONS_INDEX]               = 0x08,
 401         [TDMA_PROD_INDEX]               = 0x0C,
 402         [DMA_RING_BUF_SIZE]             = 0x10,
 403         [DMA_START_ADDR]                = 0x14,
 404         [DMA_START_ADDR_HI]             = 0x18,
 405         [DMA_END_ADDR]                  = 0x1C,
 406         [DMA_END_ADDR_HI]               = 0x20,
 407         [DMA_MBUF_DONE_THRESH]          = 0x24,
 408         [TDMA_FLOW_PERIOD]              = 0x28,
 409         [TDMA_WRITE_PTR]                = 0x2C,
 410         [TDMA_WRITE_PTR_HI]             = 0x30,
 411 };
 412
 413 static const u8 genet_dma_ring_regs_v123[] = {
 414         [TDMA_READ_PTR]                 = 0x00,
 415         [TDMA_CONS_INDEX]               = 0x04,
 416         [TDMA_PROD_INDEX]               = 0x08,
 417         [DMA_RING_BUF_SIZE]             = 0x0C,
 418         [DMA_START_ADDR]                = 0x10,
 419         [DMA_END_ADDR]                  = 0x14,
 420         [DMA_MBUF_DONE_THRESH]          = 0x18,
 421         [TDMA_FLOW_PERIOD]              = 0x1C,
 422         [TDMA_WRITE_PTR]                = 0x20,
 423 };
 424
 425 /* Set at runtime once GENET version is known */
 426 static const u8 *genet_dma_ring_regs;
 427
 428 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
 429                                            unsigned int ring,
 430                                            enum dma_ring_reg r)
 431 {
 432         return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
 433                               (DMA_RING_SIZE * ring) +
 434                               genet_dma_ring_regs[r]);
 435 }
 436
 437 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
 438                                              unsigned int ring, u32 val,
 439                                              enum dma_ring_reg r)
 440 {
 441         bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
 442                         (DMA_RING_SIZE * ring) +
 443                         genet_dma_ring_regs[r]);
 444 }
 445
 446 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
 447                                            unsigned int ring,
 448                                            enum dma_ring_reg r)
 449 {
 450         return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
 451                               (DMA_RING_SIZE * ring) +
 452                               genet_dma_ring_regs[r]);
 453 }
 454
 455 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
 456                                              unsigned int ring, u32 val,
 457                                              enum dma_ring_reg r)
 458 {
 459         bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
 460                         (DMA_RING_SIZE * ring) +
 461                         genet_dma_ring_regs[r]);
 462 }
 463
 464 static int bcmgenet_begin(struct net_device *dev)
 465 {
 466         struct bcmgenet_priv *priv = netdev_priv(dev);
 467
 468         /* Turn on the clock */
 469         return clk_prepare_enable(priv->clk);
 470 }
 471
 472 static void bcmgenet_complete(struct net_device *dev)
 473 {
 474         struct bcmgenet_priv *priv = netdev_priv(dev);
 475
 476         /* Turn off the clock */
 477         clk_disable_unprepare(priv->clk);
 478 }
 479
 480 static int bcmgenet_get_link_ksettings(struct net_device *dev,
 481                                        struct ethtool_link_ksettings *cmd)
 482 {
 483         if (!netif_running(dev))
 484                 return -EINVAL;
 485
 486         if (!dev->phydev)
 487                 return -ENODEV;
 488
 489         phy_ethtool_ksettings_get(dev->phydev, cmd);
 490
 491         return 0;
 492 }
 493
 494 static int bcmgenet_set_link_ksettings(struct net_device *dev,
 495                                        const struct ethtool_link_ksettings *cmd)
 496 {
 497         if (!netif_running(dev))
 498                 return -EINVAL;
 499
 500         if (!dev->phydev)
 501                 return -ENODEV;
 502
 503         return phy_ethtool_ksettings_set(dev->phydev, cmd);
 504 }
 505
 506 static int bcmgenet_set_features(struct net_device *dev,
 507                                  netdev_features_t features)
 508 {
 509         struct bcmgenet_priv *priv = netdev_priv(dev);
 510         u32 reg;
 511         int ret;
 512
 513         ret = clk_prepare_enable(priv->clk);
 514         if (ret)
 515                 return ret;
 516
 517         /* Make sure we reflect the value of CRC_CMD_FWD */
 518         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
 519         priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
 520
 521         clk_disable_unprepare(priv->clk);
 522
 523         return ret;
 524 }
 525
 526 static u32 bcmgenet_get_msglevel(struct net_device *dev)
 527 {
 528         struct bcmgenet_priv *priv = netdev_priv(dev);
 529
 530         return priv->msg_enable;
 531 }
 532
 533 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
 534 {
 535         struct bcmgenet_priv *priv = netdev_priv(dev);
 536
 537         priv->msg_enable = level;
 538 }
 539
 540 static int bcmgenet_get_coalesce(struct net_device *dev,
 541                                  struct ethtool_coalesce *ec)
 542 {
 543         struct bcmgenet_priv *priv = netdev_priv(dev);
 544         struct bcmgenet_rx_ring *ring;
 545         unsigned int i;
 546
 547         ec->tx_max_coalesced_frames =
 548                 bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
 549                                          DMA_MBUF_DONE_THRESH);
 550         ec->rx_max_coalesced_frames =
 551                 bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
 552                                          DMA_MBUF_DONE_THRESH);
 553         ec->rx_coalesce_usecs =
 554                 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
 555
 556         for (i = 0; i < priv->hw_params->rx_queues; i++) {
 557                 ring = &priv->rx_rings[i];
 558                 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
 559         }
 560         ring = &priv->rx_rings[DESC_INDEX];
 561         ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
 562
 563         return 0;
 564 }
 565
 566 static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring,
 567                                      u32 usecs, u32 pkts)
 568 {
 569         struct bcmgenet_priv *priv = ring->priv;
 570         unsigned int i = ring->index;
 571         u32 reg;
 572
 573         bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH);
 574
 575         reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
 576         reg &= ~DMA_TIMEOUT_MASK;
 577         reg |= DIV_ROUND_UP(usecs * 1000, 8192);
 578         bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
 579 }
 580
 581 static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring,
 582                                           struct ethtool_coalesce *ec)
 583 {
 584         struct dim_cq_moder moder;
 585         u32 usecs, pkts;
 586
 587         ring->rx_coalesce_usecs = ec->rx_coalesce_usecs;
 588         ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
 589         usecs = ring->rx_coalesce_usecs;
 590         pkts = ring->rx_max_coalesced_frames;
 591
 592         if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) {
 593                 moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode);
 594                 usecs = moder.usec;
 595                 pkts = moder.pkts;
 596         }
 597
 598         ring->dim.use_dim = ec->use_adaptive_rx_coalesce;
 599         bcmgenet_set_rx_coalesce(ring, usecs, pkts);
 600 }
 601
 602 static int bcmgenet_set_coalesce(struct net_device *dev,
 603                                  struct ethtool_coalesce *ec)
 604 {
 605         struct bcmgenet_priv *priv = netdev_priv(dev);
 606         unsigned int i;
 607
 608         /* Base system clock is 125Mhz, DMA timeout is this reference clock
 609          * divided by 1024, which yields roughly 8.192us, our maximum value
 610          * has to fit in the DMA_TIMEOUT_MASK (16 bits)
 611          */
 612         if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
 613             ec->tx_max_coalesced_frames == 0 ||
 614             ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
 615             ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
 616                 return -EINVAL;
 617
 618         if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
 619                 return -EINVAL;
 620
 621         /* GENET TDMA hardware does not support a configurable timeout, but will
 622          * always generate an interrupt either after MBDONE packets have been
 623          * transmitted, or when the ring is empty.
 624          */
 625
 626         /* Program all TX queues with the same values, as there is no
 627          * ethtool knob to do coalescing on a per-queue basis
 628          */
 629         for (i = 0; i < priv->hw_params->tx_queues; i++)
 630                 bcmgenet_tdma_ring_writel(priv, i,
 631                                           ec->tx_max_coalesced_frames,
 632                                           DMA_MBUF_DONE_THRESH);
 633         bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
 634                                   ec->tx_max_coalesced_frames,
 635                                   DMA_MBUF_DONE_THRESH);
 636
 637         for (i = 0; i < priv->hw_params->rx_queues; i++)
 638                 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec);
 639         bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[DESC_INDEX], ec);
 640
 641         return 0;
 642 }
 643
 644 /* standard ethtool support functions. */
 645 enum bcmgenet_stat_type {
 646         BCMGENET_STAT_NETDEV = -1,
 647         BCMGENET_STAT_MIB_RX,
 648         BCMGENET_STAT_MIB_TX,
 649         BCMGENET_STAT_RUNT,
 650         BCMGENET_STAT_MISC,
 651         BCMGENET_STAT_SOFT,
 652 };
 653
 654 struct bcmgenet_stats {
 655         char stat_string[ETH_GSTRING_LEN];
 656         int stat_sizeof;
 657         int stat_offset;
 658         enum bcmgenet_stat_type type;
 659         /* reg offset from UMAC base for misc counters */
 660         u16 reg_offset;
 661 };
 662
 663 #define STAT_NETDEV(m) { \
 664         .stat_string = __stringify(m), \
 665         .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
 666         .stat_offset = offsetof(struct net_device_stats, m), \
 667         .type = BCMGENET_STAT_NETDEV, \
 668 }
 669
 670 #define STAT_GENET_MIB(str, m, _type) { \
 671         .stat_string = str, \
 672         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 673         .stat_offset = offsetof(struct bcmgenet_priv, m), \
 674         .type = _type, \
 675 }
 676
 677 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
 678 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
 679 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
 680 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
 681
 682 #define STAT_GENET_MISC(str, m, offset) { \
 683         .stat_string = str, \
 684         .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 685         .stat_offset = offsetof(struct bcmgenet_priv, m), \
 686         .type = BCMGENET_STAT_MISC, \
 687         .reg_offset = offset, \
 688 }
 689
 690 #define STAT_GENET_Q(num) \
 691         STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \
 692                         tx_rings[num].packets), \
 693         STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \
 694                         tx_rings[num].bytes), \
 695         STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \
 696                         rx_rings[num].bytes),    \
 697         STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \
 698                         rx_rings[num].packets), \
 699         STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \
 700                         rx_rings[num].errors), \
 701         STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \
 702                         rx_rings[num].dropped)
 703
 704 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
 705  * between the end of TX stats and the beginning of the RX RUNT
 706  */
 707 #define BCMGENET_STAT_OFFSET    0xc
 708
 709 /* Hardware counters must be kept in sync because the order/offset
 710  * is important here (order in structure declaration = order in hardware)
 711  */
 712 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
 713         /* general stats */
 714         STAT_NETDEV(rx_packets),
 715         STAT_NETDEV(tx_packets),
 716         STAT_NETDEV(rx_bytes),
 717         STAT_NETDEV(tx_bytes),
 718         STAT_NETDEV(rx_errors),
 719         STAT_NETDEV(tx_errors),
 720         STAT_NETDEV(rx_dropped),
 721         STAT_NETDEV(tx_dropped),
 722         STAT_NETDEV(multicast),
 723         /* UniMAC RSV counters */
 724         STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
 725         STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
 726         STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
 727         STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
 728         STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
 729         STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
 730         STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
 731         STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
 732         STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
 733         STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
 734         STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
 735         STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
 736         STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
 737         STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
 738         STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
 739         STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
 740         STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
 741         STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
 742         STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
 743         STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
 744         STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
 745         STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
 746         STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
 747         STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
 748         STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
 749         STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
 750         STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
 751         STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
 752         STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
 753         /* UniMAC TSV counters */
 754         STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
 755         STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
 756         STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
 757         STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
 758         STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
 759         STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
 760         STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
 761         STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
 762         STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
 763         STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
 764         STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
 765         STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
 766         STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
 767         STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
 768         STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
 769         STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
 770         STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
 771         STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
 772         STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
 773         STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
 774         STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
 775         STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
 776         STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
 777         STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
 778         STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
 779         STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
 780         STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
 781         STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
 782         STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
 783         /* UniMAC RUNT counters */
 784         STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
 785         STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
 786         STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
 787         STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
 788         /* Misc UniMAC counters */
 789         STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
 790                         UMAC_RBUF_OVFL_CNT_V1),
 791         STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt,
 792                         UMAC_RBUF_ERR_CNT_V1),
 793         STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
 794         STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
 795         STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
 796         STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
 797         STAT_GENET_SOFT_MIB("tx_realloc_tsb", mib.tx_realloc_tsb),
 798         STAT_GENET_SOFT_MIB("tx_realloc_tsb_failed",
 799                             mib.tx_realloc_tsb_failed),
 800         /* Per TX queues */
 801         STAT_GENET_Q(0),
 802         STAT_GENET_Q(1),
 803         STAT_GENET_Q(2),
 804         STAT_GENET_Q(3),
 805         STAT_GENET_Q(16),
 806 };
 807
 808 #define BCMGENET_STATS_LEN      ARRAY_SIZE(bcmgenet_gstrings_stats)
 809
 810 static void bcmgenet_get_drvinfo(struct net_device *dev,
 811                                  struct ethtool_drvinfo *info)
 812 {
 813         strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
 814 }
 815
 816 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
 817 {
 818         switch (string_set) {
 819         case ETH_SS_STATS:
 820                 return BCMGENET_STATS_LEN;
 821         default:
 822                 return -EOPNOTSUPP;
 823         }
 824 }
 825
 826 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
 827                                  u8 *data)
 828 {
 829         int i;
 830
 831         switch (stringset) {
 832         case ETH_SS_STATS:
 833                 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 834                         memcpy(data + i * ETH_GSTRING_LEN,
 835                                bcmgenet_gstrings_stats[i].stat_string,
 836                                ETH_GSTRING_LEN);
 837                 }
 838                 break;
 839         }
 840 }
 841
 842 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset)
 843 {
 844         u16 new_offset;
 845         u32 val;
 846
 847         switch (offset) {
 848         case UMAC_RBUF_OVFL_CNT_V1:
 849                 if (GENET_IS_V2(priv))
 850                         new_offset = RBUF_OVFL_CNT_V2;
 851                 else
 852                         new_offset = RBUF_OVFL_CNT_V3PLUS;
 853
 854                 val = bcmgenet_rbuf_readl(priv, new_offset);
 855                 /* clear if overflowed */
 856                 if (val == ~0)
 857                         bcmgenet_rbuf_writel(priv, 0, new_offset);
 858                 break;
 859         case UMAC_RBUF_ERR_CNT_V1:
 860                 if (GENET_IS_V2(priv))
 861                         new_offset = RBUF_ERR_CNT_V2;
 862                 else
 863                         new_offset = RBUF_ERR_CNT_V3PLUS;
 864
 865                 val = bcmgenet_rbuf_readl(priv, new_offset);
 866                 /* clear if overflowed */
 867                 if (val == ~0)
 868                         bcmgenet_rbuf_writel(priv, 0, new_offset);
 869                 break;
 870         default:
 871                 val = bcmgenet_umac_readl(priv, offset);
 872                 /* clear if overflowed */
 873                 if (val == ~0)
 874                         bcmgenet_umac_writel(priv, 0, offset);
 875                 break;
 876         }
 877
 878         return val;
 879 }
 880
 881 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
 882 {
 883         int i, j = 0;
 884
 885         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 886                 const struct bcmgenet_stats *s;
 887                 u8 offset = 0;
 888                 u32 val = 0;
 889                 char *p;
 890
 891                 s = &bcmgenet_gstrings_stats[i];
 892                 switch (s->type) {
 893                 case BCMGENET_STAT_NETDEV:
 894                 case BCMGENET_STAT_SOFT:
 895                         continue;
 896                 case BCMGENET_STAT_RUNT:
 897                         offset += BCMGENET_STAT_OFFSET;
 898                         /* fall through */
 899                 case BCMGENET_STAT_MIB_TX:
 900                         offset += BCMGENET_STAT_OFFSET;
 901                         /* fall through */
 902                 case BCMGENET_STAT_MIB_RX:
 903                         val = bcmgenet_umac_readl(priv,
 904                                                   UMAC_MIB_START + j + offset);
 905                         offset = 0;     /* Reset Offset */
 906                         break;
 907                 case BCMGENET_STAT_MISC:
 908                         if (GENET_IS_V1(priv)) {
 909                                 val = bcmgenet_umac_readl(priv, s->reg_offset);
 910                                 /* clear if overflowed */
 911                                 if (val == ~0)
 912                                         bcmgenet_umac_writel(priv, 0,
 913                                                              s->reg_offset);
 914                         } else {
 915                                 val = bcmgenet_update_stat_misc(priv,
 916                                                                 s->reg_offset);
 917                         }
 918                         break;
 919                 }
 920
 921                 j += s->stat_sizeof;
 922                 p = (char *)priv + s->stat_offset;
 923                 *(u32 *)p = val;
 924         }
 925 }
 926
 927 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
 928                                        struct ethtool_stats *stats,
 929                                        u64 *data)
 930 {
 931         struct bcmgenet_priv *priv = netdev_priv(dev);
 932         int i;
 933
 934         if (netif_running(dev))
 935                 bcmgenet_update_mib_counters(priv);
 936
 937         for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 938                 const struct bcmgenet_stats *s;
 939                 char *p;
 940
 941                 s = &bcmgenet_gstrings_stats[i];
 942                 if (s->type == BCMGENET_STAT_NETDEV)
 943                         p = (char *)&dev->stats;
 944                 else
 945                         p = (char *)priv;
 946                 p += s->stat_offset;
 947                 if (sizeof(unsigned long) != sizeof(u32) &&
 948                     s->stat_sizeof == sizeof(unsigned long))
 949                         data[i] = *(unsigned long *)p;
 950                 else
 951                         data[i] = *(u32 *)p;
 952         }
 953 }
 954
 955 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
 956 {
 957         struct bcmgenet_priv *priv = netdev_priv(dev);
 958         u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
 959         u32 reg;
 960
 961         if (enable && !priv->clk_eee_enabled) {
 962                 clk_prepare_enable(priv->clk_eee);
 963                 priv->clk_eee_enabled = true;
 964         }
 965
 966         reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
 967         if (enable)
 968                 reg |= EEE_EN;
 969         else
 970                 reg &= ~EEE_EN;
 971         bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
 972
 973         /* Enable EEE and switch to a 27Mhz clock automatically */
 974         reg = bcmgenet_readl(priv->base + off);
 975         if (enable)
 976                 reg |= TBUF_EEE_EN | TBUF_PM_EN;
 977         else
 978                 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
 979         bcmgenet_writel(reg, priv->base + off);
 980
 981         /* Do the same for thing for RBUF */
 982         reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
 983         if (enable)
 984                 reg |= RBUF_EEE_EN | RBUF_PM_EN;
 985         else
 986                 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
 987         bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
 988
 989         if (!enable && priv->clk_eee_enabled) {
 990                 clk_disable_unprepare(priv->clk_eee);
 991                 priv->clk_eee_enabled = false;
 992         }
 993
 994         priv->eee.eee_enabled = enable;
 995         priv->eee.eee_active = enable;
 996 }
 997
 998 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
 999 {
1000         struct bcmgenet_priv *priv = netdev_priv(dev);
1001         struct ethtool_eee *p = &priv->eee;
1002
1003         if (GENET_IS_V1(priv))
1004                 return -EOPNOTSUPP;
1005
1006         if (!dev->phydev)
1007                 return -ENODEV;
1008
1009         e->eee_enabled = p->eee_enabled;
1010         e->eee_active = p->eee_active;
1011         e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
1012
1013         return phy_ethtool_get_eee(dev->phydev, e);
1014 }
1015
1016 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
1017 {
1018         struct bcmgenet_priv *priv = netdev_priv(dev);
1019         struct ethtool_eee *p = &priv->eee;
1020         int ret = 0;
1021
1022         if (GENET_IS_V1(priv))
1023                 return -EOPNOTSUPP;
1024
1025         if (!dev->phydev)
1026                 return -ENODEV;
1027
1028         p->eee_enabled = e->eee_enabled;
1029
1030         if (!p->eee_enabled) {
1031                 bcmgenet_eee_enable_set(dev, false);
1032         } else {
1033                 ret = phy_init_eee(dev->phydev, 0);
1034                 if (ret) {
1035                         netif_err(priv, hw, dev, "EEE initialization failed\n");
1036                         return ret;
1037                 }
1038
1039                 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
1040                 bcmgenet_eee_enable_set(dev, true);
1041         }
1042
1043         return phy_ethtool_set_eee(dev->phydev, e);
1044 }
1045
1046 /* standard ethtool support functions. */
1047 static const struct ethtool_ops bcmgenet_ethtool_ops = {
1048         .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS |
1049                                      ETHTOOL_COALESCE_MAX_FRAMES |
1050                                      ETHTOOL_COALESCE_USE_ADAPTIVE_RX,
1051         .begin                  = bcmgenet_begin,
1052         .complete               = bcmgenet_complete,
1053         .get_strings            = bcmgenet_get_strings,
1054         .get_sset_count         = bcmgenet_get_sset_count,
1055         .get_ethtool_stats      = bcmgenet_get_ethtool_stats,
1056         .get_drvinfo            = bcmgenet_get_drvinfo,
1057         .get_link               = ethtool_op_get_link,
1058         .get_msglevel           = bcmgenet_get_msglevel,
1059         .set_msglevel           = bcmgenet_set_msglevel,
1060         .get_wol                = bcmgenet_get_wol,
1061         .set_wol                = bcmgenet_set_wol,
1062         .get_eee                = bcmgenet_get_eee,
1063         .set_eee                = bcmgenet_set_eee,
1064         .nway_reset             = phy_ethtool_nway_reset,
1065         .get_coalesce           = bcmgenet_get_coalesce,
1066         .set_coalesce           = bcmgenet_set_coalesce,
1067         .get_link_ksettings     = bcmgenet_get_link_ksettings,
1068         .set_link_ksettings     = bcmgenet_set_link_ksettings,
1069         .get_ts_info            = ethtool_op_get_ts_info,
1070 };
1071
1072 /* Power down the unimac, based on mode. */
1073 static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1074                                 enum bcmgenet_power_mode mode)
1075 {
1076         int ret = 0;
1077         u32 reg;
1078
1079         switch (mode) {
1080         case GENET_POWER_CABLE_SENSE:
1081                 phy_detach(priv->dev->phydev);
1082                 break;
1083
1084         case GENET_POWER_WOL_MAGIC:
1085                 ret = bcmgenet_wol_power_down_cfg(priv, mode);
1086                 break;
1087
1088         case GENET_POWER_PASSIVE:
1089                 /* Power down LED */
1090                 if (priv->hw_params->flags & GENET_HAS_EXT) {
1091                         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1092                         if (GENET_IS_V5(priv))
1093                                 reg |= EXT_PWR_DOWN_PHY_EN |
1094                                        EXT_PWR_DOWN_PHY_RD |
1095                                        EXT_PWR_DOWN_PHY_SD |
1096                                        EXT_PWR_DOWN_PHY_RX |
1097                                        EXT_PWR_DOWN_PHY_TX |
1098                                        EXT_IDDQ_GLBL_PWR;
1099                         else
1100                                 reg |= EXT_PWR_DOWN_PHY;
1101
1102                         reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1103                         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1104
1105                         bcmgenet_phy_power_set(priv->dev, false);
1106                 }
1107                 break;
1108         default:
1109                 break;
1110         }
1111
1112         return ret;
1113 }
1114
1115 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
1116                               enum bcmgenet_power_mode mode)
1117 {
1118         u32 reg;
1119
1120         if (!(priv->hw_params->flags & GENET_HAS_EXT))
1121                 return;
1122
1123         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1124
1125         switch (mode) {
1126         case GENET_POWER_PASSIVE:
1127                 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1128                 if (GENET_IS_V5(priv)) {
1129                         reg &= ~(EXT_PWR_DOWN_PHY_EN |
1130                                  EXT_PWR_DOWN_PHY_RD |
1131                                  EXT_PWR_DOWN_PHY_SD |
1132                                  EXT_PWR_DOWN_PHY_RX |
1133                                  EXT_PWR_DOWN_PHY_TX |
1134                                  EXT_IDDQ_GLBL_PWR);
1135                         reg |=   EXT_PHY_RESET;
1136                         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1137                         mdelay(1);
1138
1139                         reg &=  ~EXT_PHY_RESET;
1140                 } else {
1141                         reg &= ~EXT_PWR_DOWN_PHY;
1142                         reg |= EXT_PWR_DN_EN_LD;
1143                 }
1144                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1145                 bcmgenet_phy_power_set(priv->dev, true);
1146                 break;
1147
1148         case GENET_POWER_CABLE_SENSE:
1149                 /* enable APD */
1150                 if (!GENET_IS_V5(priv)) {
1151                         reg |= EXT_PWR_DN_EN_LD;
1152                         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1153                 }
1154                 break;
1155         case GENET_POWER_WOL_MAGIC:
1156                 bcmgenet_wol_power_up_cfg(priv, mode);
1157                 return;
1158         default:
1159                 break;
1160         }
1161 }
1162
1163 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1164                                          struct bcmgenet_tx_ring *ring)
1165 {
1166         struct enet_cb *tx_cb_ptr;
1167
1168         tx_cb_ptr = ring->cbs;
1169         tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1170
1171         /* Advancing local write pointer */
1172         if (ring->write_ptr == ring->end_ptr)
1173                 ring->write_ptr = ring->cb_ptr;
1174         else
1175                 ring->write_ptr++;
1176
1177         return tx_cb_ptr;
1178 }
1179
1180 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv,
1181                                          struct bcmgenet_tx_ring *ring)
1182 {
1183         struct enet_cb *tx_cb_ptr;
1184
1185         tx_cb_ptr = ring->cbs;
1186         tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1187
1188         /* Rewinding local write pointer */
1189         if (ring->write_ptr == ring->cb_ptr)
1190                 ring->write_ptr = ring->end_ptr;
1191         else
1192                 ring->write_ptr--;
1193
1194         return tx_cb_ptr;
1195 }
1196
1197 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1198 {
1199         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1200                                  INTRL2_CPU_MASK_SET);
1201 }
1202
1203 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1204 {
1205         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1206                                  INTRL2_CPU_MASK_CLEAR);
1207 }
1208
1209 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1210 {
1211         bcmgenet_intrl2_1_writel(ring->priv,
1212                                  1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1213                                  INTRL2_CPU_MASK_SET);
1214 }
1215
1216 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1217 {
1218         bcmgenet_intrl2_1_writel(ring->priv,
1219                                  1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1220                                  INTRL2_CPU_MASK_CLEAR);
1221 }
1222
1223 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1224 {
1225         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1226                                  INTRL2_CPU_MASK_SET);
1227 }
1228
1229 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1230 {
1231         bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1232                                  INTRL2_CPU_MASK_CLEAR);
1233 }
1234
1235 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1236 {
1237         bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1238                                  INTRL2_CPU_MASK_CLEAR);
1239 }
1240
1241 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1242 {
1243         bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1244                                  INTRL2_CPU_MASK_SET);
1245 }
1246
1247 /* Simple helper to free a transmit control block's resources
1248  * Returns an skb when the last transmit control block associated with the
1249  * skb is freed.  The skb should be freed by the caller if necessary.
1250  */
1251 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev,
1252                                            struct enet_cb *cb)
1253 {
1254         struct sk_buff *skb;
1255
1256         skb = cb->skb;
1257
1258         if (skb) {
1259                 cb->skb = NULL;
1260                 if (cb == GENET_CB(skb)->first_cb)
1261                         dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1262                                          dma_unmap_len(cb, dma_len),
1263                                          DMA_TO_DEVICE);
1264                 else
1265                         dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr),
1266                                        dma_unmap_len(cb, dma_len),
1267                                        DMA_TO_DEVICE);
1268                 dma_unmap_addr_set(cb, dma_addr, 0);
1269
1270                 if (cb == GENET_CB(skb)->last_cb)
1271                         return skb;
1272
1273         } else if (dma_unmap_addr(cb, dma_addr)) {
1274                 dma_unmap_page(dev,
1275                                dma_unmap_addr(cb, dma_addr),
1276                                dma_unmap_len(cb, dma_len),
1277                                DMA_TO_DEVICE);
1278                 dma_unmap_addr_set(cb, dma_addr, 0);
1279         }
1280
1281         return NULL;
1282 }
1283
1284 /* Simple helper to free a receive control block's resources */
1285 static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev,
1286                                            struct enet_cb *cb)
1287 {
1288         struct sk_buff *skb;
1289
1290         skb = cb->skb;
1291         cb->skb = NULL;
1292
1293         if (dma_unmap_addr(cb, dma_addr)) {
1294                 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1295                                  dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE);
1296                 dma_unmap_addr_set(cb, dma_addr, 0);
1297         }
1298
1299         return skb;
1300 }
1301
1302 /* Unlocked version of the reclaim routine */
1303 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1304                                           struct bcmgenet_tx_ring *ring)
1305 {
1306         struct bcmgenet_priv *priv = netdev_priv(dev);
1307         unsigned int txbds_processed = 0;
1308         unsigned int bytes_compl = 0;
1309         unsigned int pkts_compl = 0;
1310         unsigned int txbds_ready;
1311         unsigned int c_index;
1312         struct sk_buff *skb;
1313
1314         /* Clear status before servicing to reduce spurious interrupts */
1315         if (ring->index == DESC_INDEX)
1316                 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE,
1317                                          INTRL2_CPU_CLEAR);
1318         else
1319                 bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
1320                                          INTRL2_CPU_CLEAR);
1321
1322         /* Compute how many buffers are transmitted since last xmit call */
1323         c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX)
1324                 & DMA_C_INDEX_MASK;
1325         txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK;
1326
1327         netif_dbg(priv, tx_done, dev,
1328                   "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1329                   __func__, ring->index, ring->c_index, c_index, txbds_ready);
1330
1331         /* Reclaim transmitted buffers */
1332         while (txbds_processed < txbds_ready) {
1333                 skb = bcmgenet_free_tx_cb(&priv->pdev->dev,
1334                                           &priv->tx_cbs[ring->clean_ptr]);
1335                 if (skb) {
1336                         pkts_compl++;
1337                         bytes_compl += GENET_CB(skb)->bytes_sent;
1338                         dev_consume_skb_any(skb);
1339                 }
1340
1341                 txbds_processed++;
1342                 if (likely(ring->clean_ptr < ring->end_ptr))
1343                         ring->clean_ptr++;
1344                 else
1345                         ring->clean_ptr = ring->cb_ptr;
1346         }
1347
1348         ring->free_bds += txbds_processed;
1349         ring->c_index = c_index;
1350
1351         ring->packets += pkts_compl;
1352         ring->bytes += bytes_compl;
1353
1354         netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue),
1355                                   pkts_compl, bytes_compl);
1356
1357         return txbds_processed;
1358 }
1359
1360 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
1361                                 struct bcmgenet_tx_ring *ring)
1362 {
1363         unsigned int released;
1364
1365         spin_lock_bh(&ring->lock);
1366         released = __bcmgenet_tx_reclaim(dev, ring);
1367         spin_unlock_bh(&ring->lock);
1368
1369         return released;
1370 }
1371
1372 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1373 {
1374         struct bcmgenet_tx_ring *ring =
1375                 container_of(napi, struct bcmgenet_tx_ring, napi);
1376         unsigned int work_done = 0;
1377         struct netdev_queue *txq;
1378
1379         spin_lock(&ring->lock);
1380         work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring);
1381         if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1382                 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue);
1383                 netif_tx_wake_queue(txq);
1384         }
1385         spin_unlock(&ring->lock);
1386
1387         if (work_done == 0) {
1388                 napi_complete(napi);
1389                 ring->int_enable(ring);
1390
1391                 return 0;
1392         }
1393
1394         return budget;
1395 }
1396
1397 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1398 {
1399         struct bcmgenet_priv *priv = netdev_priv(dev);
1400         int i;
1401
1402         if (netif_is_multiqueue(dev)) {
1403                 for (i = 0; i < priv->hw_params->tx_queues; i++)
1404                         bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1405         }
1406
1407         bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1408 }
1409
1410 /* Reallocate the SKB to put enough headroom in front of it and insert
1411  * the transmit checksum offsets in the descriptors
1412  */
1413 static struct sk_buff *bcmgenet_add_tsb(struct net_device *dev,
1414                                         struct sk_buff *skb)
1415 {
1416         struct bcmgenet_priv *priv = netdev_priv(dev);
1417         struct status_64 *status = NULL;
1418         struct sk_buff *new_skb;
1419         u16 offset;
1420         u8 ip_proto;
1421         __be16 ip_ver;
1422         u32 tx_csum_info;
1423
1424         if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1425                 /* If 64 byte status block enabled, must make sure skb has
1426                  * enough headroom for us to insert 64B status block.
1427                  */
1428                 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1429                 if (!new_skb) {
1430                         dev_kfree_skb_any(skb);
1431                         priv->mib.tx_realloc_tsb_failed++;
1432                         dev->stats.tx_dropped++;
1433                         return NULL;
1434                 }
1435                 dev_consume_skb_any(skb);
1436                 skb = new_skb;
1437                 priv->mib.tx_realloc_tsb++;
1438         }
1439
1440         skb_push(skb, sizeof(*status));
1441         status = (struct status_64 *)skb->data;
1442
1443         if (skb->ip_summed  == CHECKSUM_PARTIAL) {
1444                 ip_ver = skb->protocol;
1445                 switch (ip_ver) {
1446                 case htons(ETH_P_IP):
1447                         ip_proto = ip_hdr(skb)->protocol;
1448                         break;
1449                 case htons(ETH_P_IPV6):
1450                         ip_proto = ipv6_hdr(skb)->nexthdr;
1451                         break;
1452                 default:
1453                         /* don't use UDP flag */
1454                         ip_proto = 0;
1455                         break;
1456                 }
1457
1458                 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1459                 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1460                                 (offset + skb->csum_offset) |
1461                                 STATUS_TX_CSUM_LV;
1462
1463                 /* Set the special UDP flag for UDP */
1464                 if (ip_proto == IPPROTO_UDP)
1465                         tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1466
1467                 status->tx_csum_info = tx_csum_info;
1468         }
1469
1470         return skb;
1471 }
1472
1473 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1474 {
1475         struct bcmgenet_priv *priv = netdev_priv(dev);
1476         struct device *kdev = &priv->pdev->dev;
1477         struct bcmgenet_tx_ring *ring = NULL;
1478         struct enet_cb *tx_cb_ptr;
1479         struct netdev_queue *txq;
1480         int nr_frags, index;
1481         dma_addr_t mapping;
1482         unsigned int size;
1483         skb_frag_t *frag;
1484         u32 len_stat;
1485         int ret;
1486         int i;
1487
1488         index = skb_get_queue_mapping(skb);
1489         /* Mapping strategy:
1490          * queue_mapping = 0, unclassified, packet xmited through ring16
1491          * queue_mapping = 1, goes to ring 0. (highest priority queue
1492          * queue_mapping = 2, goes to ring 1.
1493          * queue_mapping = 3, goes to ring 2.
1494          * queue_mapping = 4, goes to ring 3.
1495          */
1496         if (index == 0)
1497                 index = DESC_INDEX;
1498         else
1499                 index -= 1;
1500
1501         ring = &priv->tx_rings[index];
1502         txq = netdev_get_tx_queue(dev, ring->queue);
1503
1504         nr_frags = skb_shinfo(skb)->nr_frags;
1505
1506         spin_lock(&ring->lock);
1507         if (ring->free_bds <= (nr_frags + 1)) {
1508                 if (!netif_tx_queue_stopped(txq)) {
1509                         netif_tx_stop_queue(txq);
1510                         netdev_err(dev,
1511                                    "%s: tx ring %d full when queue %d awake\n",
1512                                    __func__, index, ring->queue);
1513                 }
1514                 ret = NETDEV_TX_BUSY;
1515                 goto out;
1516         }
1517
1518         if (skb_padto(skb, ETH_ZLEN)) {
1519                 ret = NETDEV_TX_OK;
1520                 goto out;
1521         }
1522
1523         /* Retain how many bytes will be sent on the wire, without TSB inserted
1524          * by transmit checksum offload
1525          */
1526         GENET_CB(skb)->bytes_sent = skb->len;
1527
1528         /* add the Transmit Status Block */
1529         skb = bcmgenet_add_tsb(dev, skb);
1530         if (!skb) {
1531                 ret = NETDEV_TX_OK;
1532                 goto out;
1533         }
1534
1535         for (i = 0; i <= nr_frags; i++) {
1536                 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1537
1538                 BUG_ON(!tx_cb_ptr);
1539
1540                 if (!i) {
1541                         /* Transmit single SKB or head of fragment list */
1542                         GENET_CB(skb)->first_cb = tx_cb_ptr;
1543                         size = skb_headlen(skb);
1544                         mapping = dma_map_single(kdev, skb->data, size,
1545                                                  DMA_TO_DEVICE);
1546                 } else {
1547                         /* xmit fragment */
1548                         frag = &skb_shinfo(skb)->frags[i - 1];
1549                         size = skb_frag_size(frag);
1550                         mapping = skb_frag_dma_map(kdev, frag, 0, size,
1551                                                    DMA_TO_DEVICE);
1552                 }
1553
1554                 ret = dma_mapping_error(kdev, mapping);
1555                 if (ret) {
1556                         priv->mib.tx_dma_failed++;
1557                         netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1558                         ret = NETDEV_TX_OK;
1559                         goto out_unmap_frags;
1560                 }
1561                 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1562                 dma_unmap_len_set(tx_cb_ptr, dma_len, size);
1563
1564                 tx_cb_ptr->skb = skb;
1565
1566                 len_stat = (size << DMA_BUFLENGTH_SHIFT) |
1567                            (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT);
1568
1569                 if (!i) {
1570                         len_stat |= DMA_TX_APPEND_CRC | DMA_SOP;
1571                         if (skb->ip_summed == CHECKSUM_PARTIAL)
1572                                 len_stat |= DMA_TX_DO_CSUM;
1573                 }
1574                 if (i == nr_frags)
1575                         len_stat |= DMA_EOP;
1576
1577                 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat);
1578         }
1579
1580         GENET_CB(skb)->last_cb = tx_cb_ptr;
1581         skb_tx_timestamp(skb);
1582
1583         /* Decrement total BD count and advance our write pointer */
1584         ring->free_bds -= nr_frags + 1;
1585         ring->prod_index += nr_frags + 1;
1586         ring->prod_index &= DMA_P_INDEX_MASK;
1587
1588         netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent);
1589
1590         if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
1591                 netif_tx_stop_queue(txq);
1592
1593         if (!netdev_xmit_more() || netif_xmit_stopped(txq))
1594                 /* Packets are ready, update producer index */
1595                 bcmgenet_tdma_ring_writel(priv, ring->index,
1596                                           ring->prod_index, TDMA_PROD_INDEX);
1597 out:
1598         spin_unlock(&ring->lock);
1599
1600         return ret;
1601
1602 out_unmap_frags:
1603         /* Back up for failed control block mapping */
1604         bcmgenet_put_txcb(priv, ring);
1605
1606         /* Unmap successfully mapped control blocks */
1607         while (i-- > 0) {
1608                 tx_cb_ptr = bcmgenet_put_txcb(priv, ring);
1609                 bcmgenet_free_tx_cb(kdev, tx_cb_ptr);
1610         }
1611
1612         dev_kfree_skb(skb);
1613         goto out;
1614 }
1615
1616 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1617                                           struct enet_cb *cb)
1618 {
1619         struct device *kdev = &priv->pdev->dev;
1620         struct sk_buff *skb;
1621         struct sk_buff *rx_skb;
1622         dma_addr_t mapping;
1623
1624         /* Allocate a new Rx skb */
1625         skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
1626         if (!skb) {
1627                 priv->mib.alloc_rx_buff_failed++;
1628                 netif_err(priv, rx_err, priv->dev,
1629                           "%s: Rx skb allocation failed\n", __func__);
1630                 return NULL;
1631         }
1632
1633         /* DMA-map the new Rx skb */
1634         mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1635                                  DMA_FROM_DEVICE);
1636         if (dma_mapping_error(kdev, mapping)) {
1637                 priv->mib.rx_dma_failed++;
1638                 dev_kfree_skb_any(skb);
1639                 netif_err(priv, rx_err, priv->dev,
1640                           "%s: Rx skb DMA mapping failed\n", __func__);
1641                 return NULL;
1642         }
1643
1644         /* Grab the current Rx skb from the ring and DMA-unmap it */
1645         rx_skb = bcmgenet_free_rx_cb(kdev, cb);
1646
1647         /* Put the new Rx skb on the ring */
1648         cb->skb = skb;
1649         dma_unmap_addr_set(cb, dma_addr, mapping);
1650         dma_unmap_len_set(cb, dma_len, priv->rx_buf_len);
1651         dmadesc_set_addr(priv, cb->bd_addr, mapping);
1652
1653         /* Return the current Rx skb to caller */
1654         return rx_skb;
1655 }
1656
1657 /* bcmgenet_desc_rx - descriptor based rx process.
1658  * this could be called from bottom half, or from NAPI polling method.
1659  */
1660 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1661                                      unsigned int budget)
1662 {
1663         struct bcmgenet_priv *priv = ring->priv;
1664         struct net_device *dev = priv->dev;
1665         struct enet_cb *cb;
1666         struct sk_buff *skb;
1667         u32 dma_length_status;
1668         unsigned long dma_flag;
1669         int len;
1670         unsigned int rxpktprocessed = 0, rxpkttoprocess;
1671         unsigned int bytes_processed = 0;
1672         unsigned int p_index, mask;
1673         unsigned int discards;
1674
1675         /* Clear status before servicing to reduce spurious interrupts */
1676         if (ring->index == DESC_INDEX) {
1677                 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE,
1678                                          INTRL2_CPU_CLEAR);
1679         } else {
1680                 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index);
1681                 bcmgenet_intrl2_1_writel(priv,
1682                                          mask,
1683                                          INTRL2_CPU_CLEAR);
1684         }
1685
1686         p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
1687
1688         discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1689                    DMA_P_INDEX_DISCARD_CNT_MASK;
1690         if (discards > ring->old_discards) {
1691                 discards = discards - ring->old_discards;
1692                 ring->errors += discards;
1693                 ring->old_discards += discards;
1694
1695                 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1696                 if (ring->old_discards >= 0xC000) {
1697                         ring->old_discards = 0;
1698                         bcmgenet_rdma_ring_writel(priv, ring->index, 0,
1699                                                   RDMA_PROD_INDEX);
1700                 }
1701         }
1702
1703         p_index &= DMA_P_INDEX_MASK;
1704         rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK;
1705
1706         netif_dbg(priv, rx_status, dev,
1707                   "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1708
1709         while ((rxpktprocessed < rxpkttoprocess) &&
1710                (rxpktprocessed < budget)) {
1711                 struct status_64 *status;
1712                 __be16 rx_csum;
1713
1714                 cb = &priv->rx_cbs[ring->read_ptr];
1715                 skb = bcmgenet_rx_refill(priv, cb);
1716
1717                 if (unlikely(!skb)) {
1718                         ring->dropped++;
1719                         goto next;
1720                 }
1721
1722                 status = (struct status_64 *)skb->data;
1723                 dma_length_status = status->length_status;
1724                 if (dev->features & NETIF_F_RXCSUM) {
1725                         rx_csum = (__force __be16)(status->rx_csum & 0xffff);
1726                         skb->csum = (__force __wsum)ntohs(rx_csum);
1727                         skb->ip_summed = CHECKSUM_COMPLETE;
1728                 }
1729
1730                 /* DMA flags and length are still valid no matter how
1731                  * we got the Receive Status Vector (64B RSB or register)
1732                  */
1733                 dma_flag = dma_length_status & 0xffff;
1734                 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1735
1736                 netif_dbg(priv, rx_status, dev,
1737                           "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1738                           __func__, p_index, ring->c_index,
1739                           ring->read_ptr, dma_length_status);
1740
1741                 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1742                         netif_err(priv, rx_status, dev,
1743                                   "dropping fragmented packet!\n");
1744                         ring->errors++;
1745                         dev_kfree_skb_any(skb);
1746                         goto next;
1747                 }
1748
1749                 /* report errors */
1750                 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1751                                                 DMA_RX_OV |
1752                                                 DMA_RX_NO |
1753                                                 DMA_RX_LG |
1754                                                 DMA_RX_RXER))) {
1755                         netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1756                                   (unsigned int)dma_flag);
1757                         if (dma_flag & DMA_RX_CRC_ERROR)
1758                                 dev->stats.rx_crc_errors++;
1759                         if (dma_flag & DMA_RX_OV)
1760                                 dev->stats.rx_over_errors++;
1761                         if (dma_flag & DMA_RX_NO)
1762                                 dev->stats.rx_frame_errors++;
1763                         if (dma_flag & DMA_RX_LG)
1764                                 dev->stats.rx_length_errors++;
1765                         dev->stats.rx_errors++;
1766                         dev_kfree_skb_any(skb);
1767                         goto next;
1768                 } /* error packet */
1769
1770                 skb_put(skb, len);
1771
1772                 /* remove RSB and hardware 2bytes added for IP alignment */
1773                 skb_pull(skb, 66);
1774                 len -= 66;
1775
1776                 if (priv->crc_fwd_en) {
1777                         skb_trim(skb, len - ETH_FCS_LEN);
1778                         len -= ETH_FCS_LEN;
1779                 }
1780
1781                 bytes_processed += len;
1782
1783                 /*Finish setting up the received SKB and send it to the kernel*/
1784                 skb->protocol = eth_type_trans(skb, priv->dev);
1785                 ring->packets++;
1786                 ring->bytes += len;
1787                 if (dma_flag & DMA_RX_MULT)
1788                         dev->stats.multicast++;
1789
1790                 /* Notify kernel */
1791                 napi_gro_receive(&ring->napi, skb);
1792                 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1793
1794 next:
1795                 rxpktprocessed++;
1796                 if (likely(ring->read_ptr < ring->end_ptr))
1797                         ring->read_ptr++;
1798                 else
1799                         ring->read_ptr = ring->cb_ptr;
1800
1801                 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
1802                 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1803         }
1804
1805         ring->dim.bytes = bytes_processed;
1806         ring->dim.packets = rxpktprocessed;
1807
1808         return rxpktprocessed;
1809 }
1810
1811 /* Rx NAPI polling method */
1812 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1813 {
1814         struct bcmgenet_rx_ring *ring = container_of(napi,
1815                         struct bcmgenet_rx_ring, napi);
1816         struct dim_sample dim_sample = {};
1817         unsigned int work_done;
1818
1819         work_done = bcmgenet_desc_rx(ring, budget);
1820
1821         if (work_done < budget) {
1822                 napi_complete_done(napi, work_done);
1823                 ring->int_enable(ring);
1824         }
1825
1826         if (ring->dim.use_dim) {
1827                 dim_update_sample(ring->dim.event_ctr, ring->dim.packets,
1828                                   ring->dim.bytes, &dim_sample);
1829                 net_dim(&ring->dim.dim, dim_sample);
1830         }
1831
1832         return work_done;
1833 }
1834
1835 static void bcmgenet_dim_work(struct work_struct *work)
1836 {
1837         struct dim *dim = container_of(work, struct dim, work);
1838         struct bcmgenet_net_dim *ndim =
1839                         container_of(dim, struct bcmgenet_net_dim, dim);
1840         struct bcmgenet_rx_ring *ring =
1841                         container_of(ndim, struct bcmgenet_rx_ring, dim);
1842         struct dim_cq_moder cur_profile =
1843                         net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
1844
1845         bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts);
1846         dim->state = DIM_START_MEASURE;
1847 }
1848
1849 /* Assign skb to RX DMA descriptor. */
1850 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1851                                      struct bcmgenet_rx_ring *ring)
1852 {
1853         struct enet_cb *cb;
1854         struct sk_buff *skb;
1855         int i;
1856
1857         netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1858
1859         /* loop here for each buffer needing assign */
1860         for (i = 0; i < ring->size; i++) {
1861                 cb = ring->cbs + i;
1862                 skb = bcmgenet_rx_refill(priv, cb);
1863                 if (skb)
1864                         dev_consume_skb_any(skb);
1865                 if (!cb->skb)
1866                         return -ENOMEM;
1867         }
1868
1869         return 0;
1870 }
1871
1872 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1873 {
1874         struct sk_buff *skb;
1875         struct enet_cb *cb;
1876         int i;
1877
1878         for (i = 0; i < priv->num_rx_bds; i++) {
1879                 cb = &priv->rx_cbs[i];
1880
1881                 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb);
1882                 if (skb)
1883                         dev_consume_skb_any(skb);
1884         }
1885 }
1886
1887 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
1888 {
1889         u32 reg;
1890
1891         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1892         if (reg & CMD_SW_RESET)
1893                 return;
1894         if (enable)
1895                 reg |= mask;
1896         else
1897                 reg &= ~mask;
1898         bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1899
1900         /* UniMAC stops on a packet boundary, wait for a full-size packet
1901          * to be processed
1902          */
1903         if (enable == 0)
1904                 usleep_range(1000, 2000);
1905 }
1906
1907 static void reset_umac(struct bcmgenet_priv *priv)
1908 {
1909         /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1910         bcmgenet_rbuf_ctrl_set(priv, 0);
1911         udelay(10);
1912
1913         /* issue soft reset and disable MAC while updating its registers */
1914         bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1915         udelay(2);
1916 }
1917
1918 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1919 {
1920         /* Mask all interrupts.*/
1921         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1922         bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1923         bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1924         bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1925 }
1926
1927 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
1928 {
1929         u32 int0_enable = 0;
1930
1931         /* Monitor cable plug/unplugged event for internal PHY, external PHY
1932          * and MoCA PHY
1933          */
1934         if (priv->internal_phy) {
1935                 int0_enable |= UMAC_IRQ_LINK_EVENT;
1936                 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
1937                         int0_enable |= UMAC_IRQ_PHY_DET_R;
1938         } else if (priv->ext_phy) {
1939                 int0_enable |= UMAC_IRQ_LINK_EVENT;
1940         } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1941                 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
1942                         int0_enable |= UMAC_IRQ_LINK_EVENT;
1943         }
1944         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1945 }
1946
1947 static void init_umac(struct bcmgenet_priv *priv)
1948 {
1949         struct device *kdev = &priv->pdev->dev;
1950         u32 reg;
1951         u32 int0_enable = 0;
1952
1953         dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1954
1955         reset_umac(priv);
1956
1957         /* clear tx/rx counter */
1958         bcmgenet_umac_writel(priv,
1959                              MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1960                              UMAC_MIB_CTRL);
1961         bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1962
1963         bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1964
1965         /* init tx registers, enable TSB */
1966         reg = bcmgenet_tbuf_ctrl_get(priv);
1967         reg |= TBUF_64B_EN;
1968         bcmgenet_tbuf_ctrl_set(priv, reg);
1969
1970         /* init rx registers, enable ip header optimization and RSB */
1971         reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1972         reg |= RBUF_ALIGN_2B | RBUF_64B_EN;
1973         bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1974
1975         /* enable rx checksumming */
1976         reg = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
1977         reg |= RBUF_RXCHK_EN | RBUF_L3_PARSE_DIS;
1978         /* If UniMAC forwards CRC, we need to skip over it to get
1979          * a valid CHK bit to be set in the per-packet status word
1980          */
1981         if (priv->crc_fwd_en)
1982                 reg |= RBUF_SKIP_FCS;
1983         else
1984                 reg &= ~RBUF_SKIP_FCS;
1985         bcmgenet_rbuf_writel(priv, reg, RBUF_CHK_CTRL);
1986
1987         if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1988                 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1989
1990         bcmgenet_intr_disable(priv);
1991
1992         /* Configure backpressure vectors for MoCA */
1993         if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1994                 reg = bcmgenet_bp_mc_get(priv);
1995                 reg |= BIT(priv->hw_params->bp_in_en_shift);
1996
1997                 /* bp_mask: back pressure mask */
1998                 if (netif_is_multiqueue(priv->dev))
1999                         reg |= priv->hw_params->bp_in_mask;
2000                 else
2001                         reg &= ~priv->hw_params->bp_in_mask;
2002                 bcmgenet_bp_mc_set(priv, reg);
2003         }
2004
2005         /* Enable MDIO interrupts on GENET v3+ */
2006         if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
2007                 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2008
2009         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2010
2011         dev_dbg(kdev, "done init umac\n");
2012 }
2013
2014 static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring,
2015                               void (*cb)(struct work_struct *work))
2016 {
2017         struct bcmgenet_net_dim *dim = &ring->dim;
2018
2019         INIT_WORK(&dim->dim.work, cb);
2020         dim->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2021         dim->event_ctr = 0;
2022         dim->packets = 0;
2023         dim->bytes = 0;
2024 }
2025
2026 static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring)
2027 {
2028         struct bcmgenet_net_dim *dim = &ring->dim;
2029         struct dim_cq_moder moder;
2030         u32 usecs, pkts;
2031
2032         usecs = ring->rx_coalesce_usecs;
2033         pkts = ring->rx_max_coalesced_frames;
2034
2035         /* If DIM was enabled, re-apply default parameters */
2036         if (dim->use_dim) {
2037                 moder = net_dim_get_def_rx_moderation(dim->dim.mode);
2038                 usecs = moder.usec;
2039                 pkts = moder.pkts;
2040         }
2041
2042         bcmgenet_set_rx_coalesce(ring, usecs, pkts);
2043 }
2044
2045 /* Initialize a Tx ring along with corresponding hardware registers */
2046 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
2047                                   unsigned int index, unsigned int size,
2048                                   unsigned int start_ptr, unsigned int end_ptr)
2049 {
2050         struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
2051         u32 words_per_bd = WORDS_PER_BD(priv);
2052         u32 flow_period_val = 0;
2053
2054         spin_lock_init(&ring->lock);
2055         ring->priv = priv;
2056         ring->index = index;
2057         if (index == DESC_INDEX) {
2058                 ring->queue = 0;
2059                 ring->int_enable = bcmgenet_tx_ring16_int_enable;
2060                 ring->int_disable = bcmgenet_tx_ring16_int_disable;
2061         } else {
2062                 ring->queue = index + 1;
2063                 ring->int_enable = bcmgenet_tx_ring_int_enable;
2064                 ring->int_disable = bcmgenet_tx_ring_int_disable;
2065         }
2066         ring->cbs = priv->tx_cbs + start_ptr;
2067         ring->size = size;
2068         ring->clean_ptr = start_ptr;
2069         ring->c_index = 0;
2070         ring->free_bds = size;
2071         ring->write_ptr = start_ptr;
2072         ring->cb_ptr = start_ptr;
2073         ring->end_ptr = end_ptr - 1;
2074         ring->prod_index = 0;
2075
2076         /* Set flow period for ring != 16 */
2077         if (index != DESC_INDEX)
2078                 flow_period_val = ENET_MAX_MTU_SIZE << 16;
2079
2080         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
2081         bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
2082         bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2083         /* Disable rate control for now */
2084         bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
2085                                   TDMA_FLOW_PERIOD);
2086         bcmgenet_tdma_ring_writel(priv, index,
2087                                   ((size << DMA_RING_SIZE_SHIFT) |
2088                                    RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2089
2090         /* Set start and end address, read and write pointers */
2091         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2092                                   DMA_START_ADDR);
2093         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2094                                   TDMA_READ_PTR);
2095         bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2096                                   TDMA_WRITE_PTR);
2097         bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2098                                   DMA_END_ADDR);
2099
2100         /* Initialize Tx NAPI */
2101         netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll,
2102                           NAPI_POLL_WEIGHT);
2103 }
2104
2105 /* Initialize a RDMA ring */
2106 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
2107                                  unsigned int index, unsigned int size,
2108                                  unsigned int start_ptr, unsigned int end_ptr)
2109 {
2110         struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
2111         u32 words_per_bd = WORDS_PER_BD(priv);
2112         int ret;
2113
2114         ring->priv = priv;
2115         ring->index = index;
2116         if (index == DESC_INDEX) {
2117                 ring->int_enable = bcmgenet_rx_ring16_int_enable;
2118                 ring->int_disable = bcmgenet_rx_ring16_int_disable;
2119         } else {
2120                 ring->int_enable = bcmgenet_rx_ring_int_enable;
2121                 ring->int_disable = bcmgenet_rx_ring_int_disable;
2122         }
2123         ring->cbs = priv->rx_cbs + start_ptr;
2124         ring->size = size;
2125         ring->c_index = 0;
2126         ring->read_ptr = start_ptr;
2127         ring->cb_ptr = start_ptr;
2128         ring->end_ptr = end_ptr - 1;
2129
2130         ret = bcmgenet_alloc_rx_buffers(priv, ring);
2131         if (ret)
2132                 return ret;
2133
2134         bcmgenet_init_dim(ring, bcmgenet_dim_work);
2135         bcmgenet_init_rx_coalesce(ring);
2136
2137         /* Initialize Rx NAPI */
2138         netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll,
2139                        NAPI_POLL_WEIGHT);
2140
2141         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2142         bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2143         bcmgenet_rdma_ring_writel(priv, index,
2144                                   ((size << DMA_RING_SIZE_SHIFT) |
2145                                    RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2146         bcmgenet_rdma_ring_writel(priv, index,
2147                                   (DMA_FC_THRESH_LO <<
2148                                    DMA_XOFF_THRESHOLD_SHIFT) |
2149                                    DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
2150
2151         /* Set start and end address, read and write pointers */
2152         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2153                                   DMA_START_ADDR);
2154         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2155                                   RDMA_READ_PTR);
2156         bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2157                                   RDMA_WRITE_PTR);
2158         bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2159                                   DMA_END_ADDR);
2160
2161         return ret;
2162 }
2163
2164 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2165 {
2166         unsigned int i;
2167         struct bcmgenet_tx_ring *ring;
2168
2169         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2170                 ring = &priv->tx_rings[i];
2171                 napi_enable(&ring->napi);
2172                 ring->int_enable(ring);
2173         }
2174
2175         ring = &priv->tx_rings[DESC_INDEX];
2176         napi_enable(&ring->napi);
2177         ring->int_enable(ring);
2178 }
2179
2180 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2181 {
2182         unsigned int i;
2183         struct bcmgenet_tx_ring *ring;
2184
2185         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2186                 ring = &priv->tx_rings[i];
2187                 napi_disable(&ring->napi);
2188         }
2189
2190         ring = &priv->tx_rings[DESC_INDEX];
2191         napi_disable(&ring->napi);
2192 }
2193
2194 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2195 {
2196         unsigned int i;
2197         struct bcmgenet_tx_ring *ring;
2198
2199         for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2200                 ring = &priv->tx_rings[i];
2201                 netif_napi_del(&ring->napi);
2202         }
2203
2204         ring = &priv->tx_rings[DESC_INDEX];
2205         netif_napi_del(&ring->napi);
2206 }
2207
2208 /* Initialize Tx queues
2209  *
2210  * Queues 0-3 are priority-based, each one has 32 descriptors,
2211  * with queue 0 being the highest priority queue.
2212  *
2213  * Queue 16 is the default Tx queue with
2214  * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
2215  *
2216  * The transmit control block pool is then partitioned as follows:
2217  * - Tx queue 0 uses tx_cbs[0..31]
2218  * - Tx queue 1 uses tx_cbs[32..63]
2219  * - Tx queue 2 uses tx_cbs[64..95]
2220  * - Tx queue 3 uses tx_cbs[96..127]
2221  * - Tx queue 16 uses tx_cbs[128..255]
2222  */
2223 static void bcmgenet_init_tx_queues(struct net_device *dev)
2224 {
2225         struct bcmgenet_priv *priv = netdev_priv(dev);
2226         u32 i, dma_enable;
2227         u32 dma_ctrl, ring_cfg;
2228         u32 dma_priority[3] = {0, 0, 0};
2229
2230         dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2231         dma_enable = dma_ctrl & DMA_EN;
2232         dma_ctrl &= ~DMA_EN;
2233         bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2234
2235         dma_ctrl = 0;
2236         ring_cfg = 0;
2237
2238         /* Enable strict priority arbiter mode */
2239         bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2240
2241         /* Initialize Tx priority queues */
2242         for (i = 0; i < priv->hw_params->tx_queues; i++) {
2243                 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2244                                       i * priv->hw_params->tx_bds_per_q,
2245                                       (i + 1) * priv->hw_params->tx_bds_per_q);
2246                 ring_cfg |= (1 << i);
2247                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2248                 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2249                         ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
2250         }
2251
2252         /* Initialize Tx default queue 16 */
2253         bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
2254                               priv->hw_params->tx_queues *
2255                               priv->hw_params->tx_bds_per_q,
2256                               TOTAL_DESC);
2257         ring_cfg |= (1 << DESC_INDEX);
2258         dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2259         dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2260                 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2261                  DMA_PRIO_REG_SHIFT(DESC_INDEX));
2262
2263         /* Set Tx queue priorities */
2264         bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2265         bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2266         bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2267
2268         /* Enable Tx queues */
2269         bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
2270
2271         /* Enable Tx DMA */
2272         if (dma_enable)
2273                 dma_ctrl |= DMA_EN;
2274         bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2275 }
2276
2277 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2278 {
2279         unsigned int i;
2280         struct bcmgenet_rx_ring *ring;
2281
2282         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2283                 ring = &priv->rx_rings[i];
2284                 napi_enable(&ring->napi);
2285                 ring->int_enable(ring);
2286         }
2287
2288         ring = &priv->rx_rings[DESC_INDEX];
2289         napi_enable(&ring->napi);
2290         ring->int_enable(ring);
2291 }
2292
2293 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2294 {
2295         unsigned int i;
2296         struct bcmgenet_rx_ring *ring;
2297
2298         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2299                 ring = &priv->rx_rings[i];
2300                 napi_disable(&ring->napi);
2301                 cancel_work_sync(&ring->dim.dim.work);
2302         }
2303
2304         ring = &priv->rx_rings[DESC_INDEX];
2305         napi_disable(&ring->napi);
2306         cancel_work_sync(&ring->dim.dim.work);
2307 }
2308
2309 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2310 {
2311         unsigned int i;
2312         struct bcmgenet_rx_ring *ring;
2313
2314         for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2315                 ring = &priv->rx_rings[i];
2316                 netif_napi_del(&ring->napi);
2317         }
2318
2319         ring = &priv->rx_rings[DESC_INDEX];
2320         netif_napi_del(&ring->napi);
2321 }
2322
2323 /* Initialize Rx queues
2324  *
2325  * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2326  * used to direct traffic to these queues.
2327  *
2328  * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2329  */
2330 static int bcmgenet_init_rx_queues(struct net_device *dev)
2331 {
2332         struct bcmgenet_priv *priv = netdev_priv(dev);
2333         u32 i;
2334         u32 dma_enable;
2335         u32 dma_ctrl;
2336         u32 ring_cfg;
2337         int ret;
2338
2339         dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2340         dma_enable = dma_ctrl & DMA_EN;
2341         dma_ctrl &= ~DMA_EN;
2342         bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2343
2344         dma_ctrl = 0;
2345         ring_cfg = 0;
2346
2347         /* Initialize Rx priority queues */
2348         for (i = 0; i < priv->hw_params->rx_queues; i++) {
2349                 ret = bcmgenet_init_rx_ring(priv, i,
2350                                             priv->hw_params->rx_bds_per_q,
2351                                             i * priv->hw_params->rx_bds_per_q,
2352                                             (i + 1) *
2353                                             priv->hw_params->rx_bds_per_q);
2354                 if (ret)
2355                         return ret;
2356
2357                 ring_cfg |= (1 << i);
2358                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2359         }
2360
2361         /* Initialize Rx default queue 16 */
2362         ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2363                                     priv->hw_params->rx_queues *
2364                                     priv->hw_params->rx_bds_per_q,
2365                                     TOTAL_DESC);
2366         if (ret)
2367                 return ret;
2368
2369         ring_cfg |= (1 << DESC_INDEX);
2370         dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2371
2372         /* Enable rings */
2373         bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2374
2375         /* Configure ring as descriptor ring and re-enable DMA if enabled */
2376         if (dma_enable)
2377                 dma_ctrl |= DMA_EN;
2378         bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2379
2380         return 0;
2381 }
2382
2383 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2384 {
2385         int ret = 0;
2386         int timeout = 0;
2387         u32 reg;
2388         u32 dma_ctrl;
2389         int i;
2390
2391         /* Disable TDMA to stop add more frames in TX DMA */
2392         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2393         reg &= ~DMA_EN;
2394         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2395
2396         /* Check TDMA status register to confirm TDMA is disabled */
2397         while (timeout++ < DMA_TIMEOUT_VAL) {
2398                 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2399                 if (reg & DMA_DISABLED)
2400                         break;
2401
2402                 udelay(1);
2403         }
2404
2405         if (timeout == DMA_TIMEOUT_VAL) {
2406                 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2407                 ret = -ETIMEDOUT;
2408         }
2409
2410         /* Wait 10ms for packet drain in both tx and rx dma */
2411         usleep_range(10000, 20000);
2412
2413         /* Disable RDMA */
2414         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2415         reg &= ~DMA_EN;
2416         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2417
2418         timeout = 0;
2419         /* Check RDMA status register to confirm RDMA is disabled */
2420         while (timeout++ < DMA_TIMEOUT_VAL) {
2421                 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2422                 if (reg & DMA_DISABLED)
2423                         break;
2424
2425                 udelay(1);
2426         }
2427
2428         if (timeout == DMA_TIMEOUT_VAL) {
2429                 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2430                 ret = -ETIMEDOUT;
2431         }
2432
2433         dma_ctrl = 0;
2434         for (i = 0; i < priv->hw_params->rx_queues; i++)
2435                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2436         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2437         reg &= ~dma_ctrl;
2438         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2439
2440         dma_ctrl = 0;
2441         for (i = 0; i < priv->hw_params->tx_queues; i++)
2442                 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2443         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2444         reg &= ~dma_ctrl;
2445         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2446
2447         return ret;
2448 }
2449
2450 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
2451 {
2452         struct netdev_queue *txq;
2453         int i;
2454
2455         bcmgenet_fini_rx_napi(priv);
2456         bcmgenet_fini_tx_napi(priv);
2457
2458         for (i = 0; i < priv->num_tx_bds; i++)
2459                 dev_kfree_skb(bcmgenet_free_tx_cb(&priv->pdev->dev,
2460                                                   priv->tx_cbs + i));
2461
2462         for (i = 0; i < priv->hw_params->tx_queues; i++) {
2463                 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue);
2464                 netdev_tx_reset_queue(txq);
2465         }
2466
2467         txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue);
2468         netdev_tx_reset_queue(txq);
2469
2470         bcmgenet_free_rx_buffers(priv);
2471         kfree(priv->rx_cbs);
2472         kfree(priv->tx_cbs);
2473 }
2474
2475 /* init_edma: Initialize DMA control register */
2476 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2477 {
2478         int ret;
2479         unsigned int i;
2480         struct enet_cb *cb;
2481
2482         netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
2483
2484         /* Initialize common Rx ring structures */
2485         priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2486         priv->num_rx_bds = TOTAL_DESC;
2487         priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2488                                GFP_KERNEL);
2489         if (!priv->rx_cbs)
2490                 return -ENOMEM;
2491
2492         for (i = 0; i < priv->num_rx_bds; i++) {
2493                 cb = priv->rx_cbs + i;
2494                 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2495         }
2496
2497         /* Initialize common TX ring structures */
2498         priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2499         priv->num_tx_bds = TOTAL_DESC;
2500         priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
2501                                GFP_KERNEL);
2502         if (!priv->tx_cbs) {
2503                 kfree(priv->rx_cbs);
2504                 return -ENOMEM;
2505         }
2506
2507         for (i = 0; i < priv->num_tx_bds; i++) {
2508                 cb = priv->tx_cbs + i;
2509                 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2510         }
2511
2512         /* Init rDma */
2513         bcmgenet_rdma_writel(priv, priv->dma_max_burst_length,
2514                              DMA_SCB_BURST_SIZE);
2515
2516         /* Initialize Rx queues */
2517         ret = bcmgenet_init_rx_queues(priv->dev);
2518         if (ret) {
2519                 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2520                 bcmgenet_free_rx_buffers(priv);
2521                 kfree(priv->rx_cbs);
2522                 kfree(priv->tx_cbs);
2523                 return ret;
2524         }
2525
2526         /* Init tDma */
2527         bcmgenet_tdma_writel(priv, priv->dma_max_burst_length,
2528                              DMA_SCB_BURST_SIZE);
2529
2530         /* Initialize Tx queues */
2531         bcmgenet_init_tx_queues(priv->dev);
2532
2533         return 0;
2534 }
2535
2536 /* Interrupt bottom half */
2537 static void bcmgenet_irq_task(struct work_struct *work)
2538 {
2539         unsigned int status;
2540         struct bcmgenet_priv *priv = container_of(
2541                         work, struct bcmgenet_priv, bcmgenet_irq_work);
2542
2543         netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2544
2545         spin_lock_irq(&priv->lock);
2546         status = priv->irq0_stat;
2547         priv->irq0_stat = 0;
2548         spin_unlock_irq(&priv->lock);
2549
2550         if (status & UMAC_IRQ_PHY_DET_R &&
2551             priv->dev->phydev->autoneg != AUTONEG_ENABLE) {
2552                 phy_init_hw(priv->dev->phydev);
2553                 genphy_config_aneg(priv->dev->phydev);
2554         }
2555
2556         /* Link UP/DOWN event */
2557         if (status & UMAC_IRQ_LINK_EVENT)
2558                 phy_mac_interrupt(priv->dev->phydev);
2559
2560 }
2561
2562 /* bcmgenet_isr1: handle Rx and Tx priority queues */
2563 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2564 {
2565         struct bcmgenet_priv *priv = dev_id;
2566         struct bcmgenet_rx_ring *rx_ring;
2567         struct bcmgenet_tx_ring *tx_ring;
2568         unsigned int index, status;
2569
2570         /* Read irq status */
2571         status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
2572                 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2573
2574         /* clear interrupts */
2575         bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR);
2576
2577         netif_dbg(priv, intr, priv->dev,
2578                   "%s: IRQ=0x%x\n", __func__, status);
2579
2580         /* Check Rx priority queue interrupts */
2581         for (index = 0; index < priv->hw_params->rx_queues; index++) {
2582                 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
2583                         continue;
2584
2585                 rx_ring = &priv->rx_rings[index];
2586                 rx_ring->dim.event_ctr++;
2587
2588                 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2589                         rx_ring->int_disable(rx_ring);
2590                         __napi_schedule_irqoff(&rx_ring->napi);
2591                 }
2592         }
2593
2594         /* Check Tx priority queue interrupts */
2595         for (index = 0; index < priv->hw_params->tx_queues; index++) {
2596                 if (!(status & BIT(index)))
2597                         continue;
2598
2599                 tx_ring = &priv->tx_rings[index];
2600
2601                 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2602                         tx_ring->int_disable(tx_ring);
2603                         __napi_schedule_irqoff(&tx_ring->napi);
2604                 }
2605         }
2606
2607         return IRQ_HANDLED;
2608 }
2609
2610 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
2611 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2612 {
2613         struct bcmgenet_priv *priv = dev_id;
2614         struct bcmgenet_rx_ring *rx_ring;
2615         struct bcmgenet_tx_ring *tx_ring;
2616         unsigned int status;
2617         unsigned long flags;
2618
2619         /* Read irq status */
2620         status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2621                 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2622
2623         /* clear interrupts */
2624         bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR);
2625
2626         netif_dbg(priv, intr, priv->dev,
2627                   "IRQ=0x%x\n", status);
2628
2629         if (status & UMAC_IRQ_RXDMA_DONE) {
2630                 rx_ring = &priv->rx_rings[DESC_INDEX];
2631                 rx_ring->dim.event_ctr++;
2632
2633                 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2634                         rx_ring->int_disable(rx_ring);
2635                         __napi_schedule_irqoff(&rx_ring->napi);
2636                 }
2637         }
2638
2639         if (status & UMAC_IRQ_TXDMA_DONE) {
2640                 tx_ring = &priv->tx_rings[DESC_INDEX];
2641
2642                 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2643                         tx_ring->int_disable(tx_ring);
2644                         __napi_schedule_irqoff(&tx_ring->napi);
2645                 }
2646         }
2647
2648         if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2649                 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
2650                 wake_up(&priv->wq);
2651         }
2652
2653         /* all other interested interrupts handled in bottom half */
2654         status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_PHY_DET_R);
2655         if (status) {
2656                 /* Save irq status for bottom-half processing. */
2657                 spin_lock_irqsave(&priv->lock, flags);
2658                 priv->irq0_stat |= status;
2659                 spin_unlock_irqrestore(&priv->lock, flags);
2660
2661                 schedule_work(&priv->bcmgenet_irq_work);
2662         }
2663
2664         return IRQ_HANDLED;
2665 }
2666
2667 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2668 {
2669         struct bcmgenet_priv *priv = dev_id;
2670
2671         pm_wakeup_event(&priv->pdev->dev, 0);
2672
2673         return IRQ_HANDLED;
2674 }
2675
2676 #ifdef CONFIG_NET_POLL_CONTROLLER
2677 static void bcmgenet_poll_controller(struct net_device *dev)
2678 {
2679         struct bcmgenet_priv *priv = netdev_priv(dev);
2680
2681         /* Invoke the main RX/TX interrupt handler */
2682         disable_irq(priv->irq0);
2683         bcmgenet_isr0(priv->irq0, priv);
2684         enable_irq(priv->irq0);
2685
2686         /* And the interrupt handler for RX/TX priority queues */
2687         disable_irq(priv->irq1);
2688         bcmgenet_isr1(priv->irq1, priv);
2689         enable_irq(priv->irq1);
2690 }
2691 #endif
2692
2693 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2694 {
2695         u32 reg;
2696
2697         reg = bcmgenet_rbuf_ctrl_get(priv);
2698         reg |= BIT(1);
2699         bcmgenet_rbuf_ctrl_set(priv, reg);
2700         udelay(10);
2701
2702         reg &= ~BIT(1);
2703         bcmgenet_rbuf_ctrl_set(priv, reg);
2704         udelay(10);
2705 }
2706
2707 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
2708                                  unsigned char *addr)
2709 {
2710         bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2711                         (addr[2] << 8) | addr[3], UMAC_MAC0);
2712         bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2713 }
2714
2715 static void bcmgenet_get_hw_addr(struct bcmgenet_priv *priv,
2716                                  unsigned char *addr)
2717 {
2718         u32 addr_tmp;
2719
2720         addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC0);
2721         addr[0] = addr_tmp >> 24;
2722         addr[1] = (addr_tmp >> 16) & 0xff;
2723         addr[2] = (addr_tmp >>  8) & 0xff;
2724         addr[3] = addr_tmp & 0xff;
2725         addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC1);
2726         addr[4] = (addr_tmp >> 8) & 0xff;
2727         addr[5] = addr_tmp & 0xff;
2728 }
2729
2730 /* Returns a reusable dma control register value */
2731 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2732 {
2733         u32 reg;
2734         u32 dma_ctrl;
2735
2736         /* disable DMA */
2737         dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2738         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2739         reg &= ~dma_ctrl;
2740         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2741
2742         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2743         reg &= ~dma_ctrl;
2744         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2745
2746         bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2747         udelay(10);
2748         bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2749
2750         return dma_ctrl;
2751 }
2752
2753 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2754 {
2755         u32 reg;
2756
2757         reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2758         reg |= dma_ctrl;
2759         bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2760
2761         reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2762         reg |= dma_ctrl;
2763         bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2764 }
2765
2766 /* bcmgenet_hfb_clear
2767  *
2768  * Clear Hardware Filter Block and disable all filtering.
2769  */
2770 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2771 {
2772         u32 i;
2773
2774         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2775         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2776         bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2777
2778         for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2779                 bcmgenet_rdma_writel(priv, 0x0, i);
2780
2781         for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2782                 bcmgenet_hfb_reg_writel(priv, 0x0,
2783                                         HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2784
2785         for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2786                         priv->hw_params->hfb_filter_size; i++)
2787                 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2788 }
2789
2790 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2791 {
2792         if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2793                 return;
2794
2795         bcmgenet_hfb_clear(priv);
2796 }
2797
2798 static void bcmgenet_netif_start(struct net_device *dev)
2799 {
2800         struct bcmgenet_priv *priv = netdev_priv(dev);
2801
2802         /* Start the network engine */
2803         bcmgenet_enable_rx_napi(priv);
2804
2805         umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2806
2807         bcmgenet_enable_tx_napi(priv);
2808
2809         /* Monitor link interrupts now */
2810         bcmgenet_link_intr_enable(priv);
2811
2812         phy_start(dev->phydev);
2813 }
2814
2815 static int bcmgenet_open(struct net_device *dev)
2816 {
2817         struct bcmgenet_priv *priv = netdev_priv(dev);
2818         unsigned long dma_ctrl;
2819         u32 reg;
2820         int ret;
2821
2822         netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2823
2824         /* Turn on the clock */
2825         clk_prepare_enable(priv->clk);
2826
2827         /* If this is an internal GPHY, power it back on now, before UniMAC is
2828          * brought out of reset as absolutely no UniMAC activity is allowed
2829          */
2830         if (priv->internal_phy)
2831                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2832
2833         /* take MAC out of reset */
2834         bcmgenet_umac_reset(priv);
2835
2836         init_umac(priv);
2837
2838         /* Apply features again in case we changed them while interface was
2839          * down
2840          */
2841         bcmgenet_set_features(dev, dev->features);
2842
2843         bcmgenet_set_hw_addr(priv, dev->dev_addr);
2844
2845         if (priv->internal_phy) {
2846                 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2847                 reg |= EXT_ENERGY_DET_MASK;
2848                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2849         }
2850
2851         /* Disable RX/TX DMA and flush TX queues */
2852         dma_ctrl = bcmgenet_dma_disable(priv);
2853
2854         /* Reinitialize TDMA and RDMA and SW housekeeping */
2855         ret = bcmgenet_init_dma(priv);
2856         if (ret) {
2857                 netdev_err(dev, "failed to initialize DMA\n");
2858                 goto err_clk_disable;
2859         }
2860
2861         /* Always enable ring 16 - descriptor ring */
2862         bcmgenet_enable_dma(priv, dma_ctrl);
2863
2864         /* HFB init */
2865         bcmgenet_hfb_init(priv);
2866
2867         ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2868                           dev->name, priv);
2869         if (ret < 0) {
2870                 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2871                 goto err_fini_dma;
2872         }
2873
2874         ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2875                           dev->name, priv);
2876         if (ret < 0) {
2877                 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2878                 goto err_irq0;
2879         }
2880
2881         ret = bcmgenet_mii_probe(dev);
2882         if (ret) {
2883                 netdev_err(dev, "failed to connect to PHY\n");
2884                 goto err_irq1;
2885         }
2886
2887         bcmgenet_netif_start(dev);
2888
2889         netif_tx_start_all_queues(dev);
2890
2891         return 0;
2892
2893 err_irq1:
2894         free_irq(priv->irq1, priv);
2895 err_irq0:
2896         free_irq(priv->irq0, priv);
2897 err_fini_dma:
2898         bcmgenet_dma_teardown(priv);
2899         bcmgenet_fini_dma(priv);
2900 err_clk_disable:
2901         if (priv->internal_phy)
2902                 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2903         clk_disable_unprepare(priv->clk);
2904         return ret;
2905 }
2906
2907 static void bcmgenet_netif_stop(struct net_device *dev)
2908 {
2909         struct bcmgenet_priv *priv = netdev_priv(dev);
2910
2911         bcmgenet_disable_tx_napi(priv);
2912         netif_tx_disable(dev);
2913
2914         /* Disable MAC receive */
2915         umac_enable_set(priv, CMD_RX_EN, false);
2916
2917         bcmgenet_dma_teardown(priv);
2918
2919         /* Disable MAC transmit. TX DMA disabled must be done before this */
2920         umac_enable_set(priv, CMD_TX_EN, false);
2921
2922         phy_stop(dev->phydev);
2923         bcmgenet_disable_rx_napi(priv);
2924         bcmgenet_intr_disable(priv);
2925
2926         /* Wait for pending work items to complete. Since interrupts are
2927          * disabled no new work will be scheduled.
2928          */
2929         cancel_work_sync(&priv->bcmgenet_irq_work);
2930
2931         priv->old_link = -1;
2932         priv->old_speed = -1;
2933         priv->old_duplex = -1;
2934         priv->old_pause = -1;
2935
2936         /* tx reclaim */
2937         bcmgenet_tx_reclaim_all(dev);
2938         bcmgenet_fini_dma(priv);
2939 }
2940
2941 static int bcmgenet_close(struct net_device *dev)
2942 {
2943         struct bcmgenet_priv *priv = netdev_priv(dev);
2944         int ret = 0;
2945
2946         netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2947
2948         bcmgenet_netif_stop(dev);
2949
2950         /* Really kill the PHY state machine and disconnect from it */
2951         phy_disconnect(dev->phydev);
2952
2953         free_irq(priv->irq0, priv);
2954         free_irq(priv->irq1, priv);
2955
2956         if (priv->internal_phy)
2957                 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2958
2959         clk_disable_unprepare(priv->clk);
2960
2961         return ret;
2962 }
2963
2964 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
2965 {
2966         struct bcmgenet_priv *priv = ring->priv;
2967         u32 p_index, c_index, intsts, intmsk;
2968         struct netdev_queue *txq;
2969         unsigned int free_bds;
2970         bool txq_stopped;
2971
2972         if (!netif_msg_tx_err(priv))
2973                 return;
2974
2975         txq = netdev_get_tx_queue(priv->dev, ring->queue);
2976
2977         spin_lock(&ring->lock);
2978         if (ring->index == DESC_INDEX) {
2979                 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2980                 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
2981         } else {
2982                 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2983                 intmsk = 1 << ring->index;
2984         }
2985         c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
2986         p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
2987         txq_stopped = netif_tx_queue_stopped(txq);
2988         free_bds = ring->free_bds;
2989         spin_unlock(&ring->lock);
2990
2991         netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
2992                   "TX queue status: %s, interrupts: %s\n"
2993                   "(sw)free_bds: %d (sw)size: %d\n"
2994                   "(sw)p_index: %d (hw)p_index: %d\n"
2995                   "(sw)c_index: %d (hw)c_index: %d\n"
2996                   "(sw)clean_p: %d (sw)write_p: %d\n"
2997                   "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
2998                   ring->index, ring->queue,
2999                   txq_stopped ? "stopped" : "active",
3000                   intsts & intmsk ? "enabled" : "disabled",
3001                   free_bds, ring->size,
3002                   ring->prod_index, p_index & DMA_P_INDEX_MASK,
3003                   ring->c_index, c_index & DMA_C_INDEX_MASK,
3004                   ring->clean_ptr, ring->write_ptr,
3005                   ring->cb_ptr, ring->end_ptr);
3006 }
3007
3008 static void bcmgenet_timeout(struct net_device *dev, unsigned int txqueue)
3009 {
3010         struct bcmgenet_priv *priv = netdev_priv(dev);
3011         u32 int0_enable = 0;
3012         u32 int1_enable = 0;
3013         unsigned int q;
3014
3015         netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
3016
3017         for (q = 0; q < priv->hw_params->tx_queues; q++)
3018                 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
3019         bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
3020
3021         bcmgenet_tx_reclaim_all(dev);
3022
3023         for (q = 0; q < priv->hw_params->tx_queues; q++)
3024                 int1_enable |= (1 << q);
3025
3026         int0_enable = UMAC_IRQ_TXDMA_DONE;
3027
3028         /* Re-enable TX interrupts if disabled */
3029         bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
3030         bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
3031
3032         netif_trans_update(dev);
3033
3034         dev->stats.tx_errors++;
3035
3036         netif_tx_wake_all_queues(dev);
3037 }
3038
3039 #define MAX_MDF_FILTER  17
3040
3041 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
3042                                          unsigned char *addr,
3043                                          int *i)
3044 {
3045         bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3046                              UMAC_MDF_ADDR + (*i * 4));
3047         bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3048                              addr[4] << 8 | addr[5],
3049                              UMAC_MDF_ADDR + ((*i + 1) * 4));
3050         *i += 2;
3051 }
3052
3053 static void bcmgenet_set_rx_mode(struct net_device *dev)
3054 {
3055         struct bcmgenet_priv *priv = netdev_priv(dev);
3056         struct netdev_hw_addr *ha;
3057         int i, nfilter;
3058         u32 reg;
3059
3060         netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3061
3062         /* Number of filters needed */
3063         nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2;
3064
3065         /*
3066          * Turn on promicuous mode for three scenarios
3067          * 1. IFF_PROMISC flag is set
3068          * 2. IFF_ALLMULTI flag is set
3069          * 3. The number of filters needed exceeds the number filters
3070          *    supported by the hardware.
3071         */
3072         reg = bcmgenet_umac_readl(priv, UMAC_CMD);
3073         if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) ||
3074             (nfilter > MAX_MDF_FILTER)) {
3075                 reg |= CMD_PROMISC;
3076                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3077                 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3078                 return;
3079         } else {
3080                 reg &= ~CMD_PROMISC;
3081                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3082         }
3083
3084         /* update MDF filter */
3085         i = 0;
3086         /* Broadcast */
3087         bcmgenet_set_mdf_addr(priv, dev->broadcast, &i);
3088         /* my own address.*/
3089         bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i);
3090
3091         /* Unicast */
3092         netdev_for_each_uc_addr(ha, dev)
3093                 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3094
3095         /* Multicast */
3096         netdev_for_each_mc_addr(ha, dev)
3097                 bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3098
3099         /* Enable filters */
3100         reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter);
3101         bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
3102 }
3103
3104 /* Set the hardware MAC address. */
3105 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3106 {
3107         struct sockaddr *addr = p;
3108
3109         /* Setting the MAC address at the hardware level is not possible
3110          * without disabling the UniMAC RX/TX enable bits.
3111          */
3112         if (netif_running(dev))
3113                 return -EBUSY;
3114
3115         ether_addr_copy(dev->dev_addr, addr->sa_data);
3116
3117         return 0;
3118 }
3119
3120 static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev)
3121 {
3122         struct bcmgenet_priv *priv = netdev_priv(dev);
3123         unsigned long tx_bytes = 0, tx_packets = 0;
3124         unsigned long rx_bytes = 0, rx_packets = 0;
3125         unsigned long rx_errors = 0, rx_dropped = 0;
3126         struct bcmgenet_tx_ring *tx_ring;
3127         struct bcmgenet_rx_ring *rx_ring;
3128         unsigned int q;
3129
3130         for (q = 0; q < priv->hw_params->tx_queues; q++) {
3131                 tx_ring = &priv->tx_rings[q];
3132                 tx_bytes += tx_ring->bytes;
3133                 tx_packets += tx_ring->packets;
3134         }
3135         tx_ring = &priv->tx_rings[DESC_INDEX];
3136         tx_bytes += tx_ring->bytes;
3137         tx_packets += tx_ring->packets;
3138
3139         for (q = 0; q < priv->hw_params->rx_queues; q++) {
3140                 rx_ring = &priv->rx_rings[q];
3141
3142                 rx_bytes += rx_ring->bytes;
3143                 rx_packets += rx_ring->packets;
3144                 rx_errors += rx_ring->errors;
3145                 rx_dropped += rx_ring->dropped;
3146         }
3147         rx_ring = &priv->rx_rings[DESC_INDEX];
3148         rx_bytes += rx_ring->bytes;
3149         rx_packets += rx_ring->packets;
3150         rx_errors += rx_ring->errors;
3151         rx_dropped += rx_ring->dropped;
3152
3153         dev->stats.tx_bytes = tx_bytes;
3154         dev->stats.tx_packets = tx_packets;
3155         dev->stats.rx_bytes = rx_bytes;
3156         dev->stats.rx_packets = rx_packets;
3157         dev->stats.rx_errors = rx_errors;
3158         dev->stats.rx_missed_errors = rx_errors;
3159         return &dev->stats;
3160 }
3161
3162 static const struct net_device_ops bcmgenet_netdev_ops = {
3163         .ndo_open               = bcmgenet_open,
3164         .ndo_stop               = bcmgenet_close,
3165         .ndo_start_xmit         = bcmgenet_xmit,
3166         .ndo_tx_timeout         = bcmgenet_timeout,
3167         .ndo_set_rx_mode        = bcmgenet_set_rx_mode,
3168         .ndo_set_mac_address    = bcmgenet_set_mac_addr,
3169         .ndo_do_ioctl           = phy_do_ioctl_running,
3170         .ndo_set_features       = bcmgenet_set_features,
3171 #ifdef CONFIG_NET_POLL_CONTROLLER
3172         .ndo_poll_controller    = bcmgenet_poll_controller,
3173 #endif
3174         .ndo_get_stats          = bcmgenet_get_stats,
3175 };
3176
3177 /* Array of GENET hardware parameters/characteristics */
3178 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3179         [GENET_V1] = {
3180                 .tx_queues = 0,
3181                 .tx_bds_per_q = 0,
3182                 .rx_queues = 0,
3183                 .rx_bds_per_q = 0,
3184                 .bp_in_en_shift = 16,
3185                 .bp_in_mask = 0xffff,
3186                 .hfb_filter_cnt = 16,
3187                 .qtag_mask = 0x1F,
3188                 .hfb_offset = 0x1000,
3189                 .rdma_offset = 0x2000,
3190                 .tdma_offset = 0x3000,
3191                 .words_per_bd = 2,
3192         },
3193         [GENET_V2] = {
3194                 .tx_queues = 4,
3195                 .tx_bds_per_q = 32,
3196                 .rx_queues = 0,
3197                 .rx_bds_per_q = 0,
3198                 .bp_in_en_shift = 16,
3199                 .bp_in_mask = 0xffff,
3200                 .hfb_filter_cnt = 16,
3201                 .qtag_mask = 0x1F,
3202                 .tbuf_offset = 0x0600,
3203                 .hfb_offset = 0x1000,
3204                 .hfb_reg_offset = 0x2000,
3205                 .rdma_offset = 0x3000,
3206                 .tdma_offset = 0x4000,
3207                 .words_per_bd = 2,
3208                 .flags = GENET_HAS_EXT,
3209         },
3210         [GENET_V3] = {
3211                 .tx_queues = 4,
3212                 .tx_bds_per_q = 32,
3213                 .rx_queues = 0,
3214                 .rx_bds_per_q = 0,
3215                 .bp_in_en_shift = 17,
3216                 .bp_in_mask = 0x1ffff,
3217                 .hfb_filter_cnt = 48,
3218                 .hfb_filter_size = 128,
3219                 .qtag_mask = 0x3F,
3220                 .tbuf_offset = 0x0600,
3221                 .hfb_offset = 0x8000,
3222                 .hfb_reg_offset = 0xfc00,
3223                 .rdma_offset = 0x10000,
3224                 .tdma_offset = 0x11000,
3225                 .words_per_bd = 2,
3226                 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3227                          GENET_HAS_MOCA_LINK_DET,
3228         },
3229         [GENET_V4] = {
3230                 .tx_queues = 4,
3231                 .tx_bds_per_q = 32,
3232                 .rx_queues = 0,
3233                 .rx_bds_per_q = 0,
3234                 .bp_in_en_shift = 17,
3235                 .bp_in_mask = 0x1ffff,
3236                 .hfb_filter_cnt = 48,
3237                 .hfb_filter_size = 128,
3238                 .qtag_mask = 0x3F,
3239                 .tbuf_offset = 0x0600,
3240                 .hfb_offset = 0x8000,
3241                 .hfb_reg_offset = 0xfc00,
3242                 .rdma_offset = 0x2000,
3243                 .tdma_offset = 0x4000,
3244                 .words_per_bd = 3,
3245                 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3246                          GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3247         },
3248         [GENET_V5] = {
3249                 .tx_queues = 4,
3250                 .tx_bds_per_q = 32,
3251                 .rx_queues = 0,
3252                 .rx_bds_per_q = 0,
3253                 .bp_in_en_shift = 17,
3254                 .bp_in_mask = 0x1ffff,
3255                 .hfb_filter_cnt = 48,
3256                 .hfb_filter_size = 128,
3257                 .qtag_mask = 0x3F,
3258                 .tbuf_offset = 0x0600,
3259                 .hfb_offset = 0x8000,
3260                 .hfb_reg_offset = 0xfc00,
3261                 .rdma_offset = 0x2000,
3262                 .tdma_offset = 0x4000,
3263                 .words_per_bd = 3,
3264                 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3265                          GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3266         },
3267 };
3268
3269 /* Infer hardware parameters from the detected GENET version */
3270 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3271 {
3272         struct bcmgenet_hw_params *params;
3273         u32 reg;
3274         u8 major;
3275         u16 gphy_rev;
3276
3277         if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) {
3278                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3279                 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3280         } else if (GENET_IS_V3(priv)) {
3281                 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3282                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3283         } else if (GENET_IS_V2(priv)) {
3284                 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3285                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3286         } else if (GENET_IS_V1(priv)) {
3287                 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3288                 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3289         }
3290
3291         /* enum genet_version starts at 1 */
3292         priv->hw_params = &bcmgenet_hw_params[priv->version];
3293         params = priv->hw_params;
3294
3295         /* Read GENET HW version */
3296         reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3297         major = (reg >> 24 & 0x0f);
3298         if (major == 6)
3299                 major = 5;
3300         else if (major == 5)
3301                 major = 4;
3302         else if (major == 0)
3303                 major = 1;
3304         if (major != priv->version) {
3305                 dev_err(&priv->pdev->dev,
3306                         "GENET version mismatch, got: %d, configured for: %d\n",
3307                         major, priv->version);
3308         }
3309
3310         /* Print the GENET core version */
3311         dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
3312                  major, (reg >> 16) & 0x0f, reg & 0xffff);
3313
3314         /* Store the integrated PHY revision for the MDIO probing function
3315          * to pass this information to the PHY driver. The PHY driver expects
3316          * to find the PHY major revision in bits 15:8 while the GENET register
3317          * stores that information in bits 7:0, account for that.
3318          *
3319          * On newer chips, starting with PHY revision G0, a new scheme is
3320          * deployed similar to the Starfighter 2 switch with GPHY major
3321          * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3322          * is reserved as well as special value 0x01ff, we have a small
3323          * heuristic to check for the new GPHY revision and re-arrange things
3324          * so the GPHY driver is happy.
3325          */
3326         gphy_rev = reg & 0xffff;
3327
3328         if (GENET_IS_V5(priv)) {
3329                 /* The EPHY revision should come from the MDIO registers of
3330                  * the PHY not from GENET.
3331                  */
3332                 if (gphy_rev != 0) {
3333                         pr_warn("GENET is reporting EPHY revision: 0x%04x\n",
3334                                 gphy_rev);
3335                 }
3336         /* This is reserved so should require special treatment */
3337         } else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3338                 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3339                 return;
3340         /* This is the good old scheme, just GPHY major, no minor nor patch */
3341         } else if ((gphy_rev & 0xf0) != 0) {
3342                 priv->gphy_rev = gphy_rev << 8;
3343         /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3344         } else if ((gphy_rev & 0xff00) != 0) {
3345                 priv->gphy_rev = gphy_rev;
3346         }
3347
3348 #ifdef CONFIG_PHYS_ADDR_T_64BIT
3349         if (!(params->flags & GENET_HAS_40BITS))
3350                 pr_warn("GENET does not support 40-bits PA\n");
3351 #endif
3352
3353         pr_debug("Configuration for version: %d\n"
3354                 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
3355                 "BP << en: %2d, BP msk: 0x%05x\n"
3356                 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3357                 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3358                 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3359                 "Words/BD: %d\n",
3360                 priv->version,
3361                 params->tx_queues, params->tx_bds_per_q,
3362                 params->rx_queues, params->rx_bds_per_q,
3363                 params->bp_in_en_shift, params->bp_in_mask,
3364                 params->hfb_filter_cnt, params->qtag_mask,
3365                 params->tbuf_offset, params->hfb_offset,
3366                 params->hfb_reg_offset,
3367                 params->rdma_offset, params->tdma_offset,
3368                 params->words_per_bd);
3369 }
3370
3371 struct bcmgenet_plat_data {
3372         enum bcmgenet_version version;
3373         u32 dma_max_burst_length;
3374 };
3375
3376 static const struct bcmgenet_plat_data v1_plat_data = {
3377         .version = GENET_V1,
3378         .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3379 };
3380
3381 static const struct bcmgenet_plat_data v2_plat_data = {
3382         .version = GENET_V2,
3383         .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3384 };
3385
3386 static const struct bcmgenet_plat_data v3_plat_data = {
3387         .version = GENET_V3,
3388         .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3389 };
3390
3391 static const struct bcmgenet_plat_data v4_plat_data = {
3392         .version = GENET_V4,
3393         .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3394 };
3395
3396 static const struct bcmgenet_plat_data v5_plat_data = {
3397         .version = GENET_V5,
3398         .dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3399 };
3400
3401 static const struct bcmgenet_plat_data bcm2711_plat_data = {
3402         .version = GENET_V5,
3403         .dma_max_burst_length = 0x08,
3404 };
3405
3406 static const struct of_device_id bcmgenet_match[] = {
3407         { .compatible = "brcm,genet-v1", .data = &v1_plat_data },
3408         { .compatible = "brcm,genet-v2", .data = &v2_plat_data },
3409         { .compatible = "brcm,genet-v3", .data = &v3_plat_data },
3410         { .compatible = "brcm,genet-v4", .data = &v4_plat_data },
3411         { .compatible = "brcm,genet-v5", .data = &v5_plat_data },
3412         { .compatible = "brcm,bcm2711-genet-v5", .data = &bcm2711_plat_data },
3413         { },
3414 };
3415 MODULE_DEVICE_TABLE(of, bcmgenet_match);
3416
3417 static int bcmgenet_probe(struct platform_device *pdev)
3418 {
3419         struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
3420         struct device_node *dn = pdev->dev.of_node;
3421         const struct of_device_id *of_id = NULL;
3422         const struct bcmgenet_plat_data *pdata;
3423         struct bcmgenet_priv *priv;
3424         struct net_device *dev;
3425         unsigned int i;
3426         int err = -EIO;
3427
3428         /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3429         dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3430                                  GENET_MAX_MQ_CNT + 1);
3431         if (!dev) {
3432                 dev_err(&pdev->dev, "can't allocate net device\n");
3433                 return -ENOMEM;
3434         }
3435
3436         if (dn) {
3437                 of_id = of_match_node(bcmgenet_match, dn);
3438                 if (!of_id)
3439                         return -EINVAL;
3440         }
3441
3442         priv = netdev_priv(dev);
3443         priv->irq0 = platform_get_irq(pdev, 0);
3444         if (priv->irq0 < 0) {
3445                 err = priv->irq0;
3446                 goto err;
3447         }
3448         priv->irq1 = platform_get_irq(pdev, 1);
3449         if (priv->irq1 < 0) {
3450                 err = priv->irq1;
3451                 goto err;
3452         }
3453         priv->wol_irq = platform_get_irq_optional(pdev, 2);
3454
3455         priv->base = devm_platform_ioremap_resource(pdev, 0);
3456         if (IS_ERR(priv->base)) {
3457                 err = PTR_ERR(priv->base);
3458                 goto err;
3459         }
3460
3461         spin_lock_init(&priv->lock);
3462
3463         SET_NETDEV_DEV(dev, &pdev->dev);
3464         dev_set_drvdata(&pdev->dev, dev);
3465         dev->watchdog_timeo = 2 * HZ;
3466         dev->ethtool_ops = &bcmgenet_ethtool_ops;
3467         dev->netdev_ops = &bcmgenet_netdev_ops;
3468
3469         priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3470
3471         /* Set default features */
3472         dev->features |= NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_HW_CSUM |
3473                          NETIF_F_RXCSUM;
3474         dev->hw_features |= dev->features;
3475         dev->vlan_features |= dev->features;
3476
3477         /* Request the WOL interrupt and advertise suspend if available */
3478         priv->wol_irq_disabled = true;
3479         err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
3480                                dev->name, priv);
3481         if (!err)
3482                 device_set_wakeup_capable(&pdev->dev, 1);
3483
3484         /* Set the needed headroom to account for any possible
3485          * features enabling/disabling at runtime
3486          */
3487         dev->needed_headroom += 64;
3488
3489         netdev_boot_setup_check(dev);
3490
3491         priv->dev = dev;
3492         priv->pdev = pdev;
3493
3494         pdata = device_get_match_data(&pdev->dev);
3495         if (pdata) {
3496                 priv->version = pdata->version;
3497                 priv->dma_max_burst_length = pdata->dma_max_burst_length;
3498         } else {
3499                 priv->version = pd->genet_version;
3500                 priv->dma_max_burst_length = DMA_MAX_BURST_LENGTH;
3501         }
3502
3503         priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
3504         if (IS_ERR(priv->clk)) {
3505                 dev_dbg(&priv->pdev->dev, "failed to get enet clock\n");
3506                 priv->clk = NULL;
3507         }
3508
3509         clk_prepare_enable(priv->clk);
3510
3511         bcmgenet_set_hw_params(priv);
3512
3513         err = -EIO;
3514         if (priv->hw_params->flags & GENET_HAS_40BITS)
3515                 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
3516         if (err)
3517                 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3518         if (err)
3519                 goto err;
3520
3521         /* Mii wait queue */
3522         init_waitqueue_head(&priv->wq);
3523         /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3524         priv->rx_buf_len = RX_BUF_LENGTH;
3525         INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3526
3527         priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
3528         if (IS_ERR(priv->clk_wol)) {
3529                 dev_dbg(&priv->pdev->dev, "failed to get enet-wol clock\n");
3530                 priv->clk_wol = NULL;
3531         }
3532
3533         priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3534         if (IS_ERR(priv->clk_eee)) {
3535                 dev_dbg(&priv->pdev->dev, "failed to get enet-eee clock\n");
3536                 priv->clk_eee = NULL;
3537         }
3538
3539         /* If this is an internal GPHY, power it on now, before UniMAC is
3540          * brought out of reset as absolutely no UniMAC activity is allowed
3541          */
3542         if (device_get_phy_mode(&pdev->dev) == PHY_INTERFACE_MODE_INTERNAL)
3543                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3544
3545         if ((pd) && (!IS_ERR_OR_NULL(pd->mac_address)))
3546                 ether_addr_copy(dev->dev_addr, pd->mac_address);
3547         else
3548                 if (!device_get_mac_address(&pdev->dev, dev->dev_addr, ETH_ALEN))
3549                         if (has_acpi_companion(&pdev->dev))
3550                                 bcmgenet_get_hw_addr(priv, dev->dev_addr);
3551
3552         if (!is_valid_ether_addr(dev->dev_addr)) {
3553                 dev_warn(&pdev->dev, "using random Ethernet MAC\n");
3554                 eth_hw_addr_random(dev);
3555         }
3556
3557         reset_umac(priv);
3558
3559         err = bcmgenet_mii_init(dev);
3560         if (err)
3561                 goto err_clk_disable;
3562
3563         /* setup number of real queues  + 1 (GENET_V1 has 0 hardware queues
3564          * just the ring 16 descriptor based TX
3565          */
3566         netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3567         netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3568
3569         /* Set default coalescing parameters */
3570         for (i = 0; i < priv->hw_params->rx_queues; i++)
3571                 priv->rx_rings[i].rx_max_coalesced_frames = 1;
3572         priv->rx_rings[DESC_INDEX].rx_max_coalesced_frames = 1;
3573
3574         /* libphy will determine the link state */
3575         netif_carrier_off(dev);
3576
3577         /* Turn off the main clock, WOL clock is handled separately */
3578         clk_disable_unprepare(priv->clk);
3579
3580         err = register_netdev(dev);
3581         if (err)
3582                 goto err;
3583
3584         return err;
3585
3586 err_clk_disable:
3587         clk_disable_unprepare(priv->clk);
3588 err:
3589         free_netdev(dev);
3590         return err;
3591 }
3592
3593 static int bcmgenet_remove(struct platform_device *pdev)
3594 {
3595         struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3596
3597         dev_set_drvdata(&pdev->dev, NULL);
3598         unregister_netdev(priv->dev);
3599         bcmgenet_mii_exit(priv->dev);
3600         free_netdev(priv->dev);
3601
3602         return 0;
3603 }
3604
3605 static void bcmgenet_shutdown(struct platform_device *pdev)
3606 {
3607         bcmgenet_remove(pdev);
3608 }
3609
3610 #ifdef CONFIG_PM_SLEEP
3611 static int bcmgenet_resume(struct device *d)
3612 {
3613         struct net_device *dev = dev_get_drvdata(d);
3614         struct bcmgenet_priv *priv = netdev_priv(dev);
3615         unsigned long dma_ctrl;
3616         int ret;
3617         u32 reg;
3618
3619         if (!netif_running(dev))
3620                 return 0;
3621
3622         /* Turn on the clock */
3623         ret = clk_prepare_enable(priv->clk);
3624         if (ret)
3625                 return ret;
3626
3627         /* If this is an internal GPHY, power it back on now, before UniMAC is
3628          * brought out of reset as absolutely no UniMAC activity is allowed
3629          */
3630         if (priv->internal_phy)
3631                 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3632
3633         bcmgenet_umac_reset(priv);
3634
3635         init_umac(priv);
3636
3637         /* From WOL-enabled suspend, switch to regular clock */
3638         if (priv->wolopts)
3639                 clk_disable_unprepare(priv->clk_wol);
3640
3641         phy_init_hw(dev->phydev);
3642
3643         /* Speed settings must be restored */
3644         genphy_config_aneg(dev->phydev);
3645         bcmgenet_mii_config(priv->dev, false);
3646
3647         /* Restore enabled features */
3648         bcmgenet_set_features(dev, dev->features);
3649
3650         bcmgenet_set_hw_addr(priv, dev->dev_addr);
3651
3652         if (priv->internal_phy) {
3653                 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3654                 reg |= EXT_ENERGY_DET_MASK;
3655                 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
3656         }
3657
3658         if (priv->wolopts)
3659                 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3660
3661         /* Disable RX/TX DMA and flush TX queues */
3662         dma_ctrl = bcmgenet_dma_disable(priv);
3663
3664         /* Reinitialize TDMA and RDMA and SW housekeeping */
3665         ret = bcmgenet_init_dma(priv);
3666         if (ret) {
3667                 netdev_err(dev, "failed to initialize DMA\n");
3668                 goto out_clk_disable;
3669         }
3670
3671         /* Always enable ring 16 - descriptor ring */
3672         bcmgenet_enable_dma(priv, dma_ctrl);
3673
3674         if (!device_may_wakeup(d))
3675                 phy_resume(dev->phydev);
3676
3677         if (priv->eee.eee_enabled)
3678                 bcmgenet_eee_enable_set(dev, true);
3679
3680         bcmgenet_netif_start(dev);
3681
3682         netif_device_attach(dev);
3683
3684         return 0;
3685
3686 out_clk_disable:
3687         if (priv->internal_phy)
3688                 bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3689         clk_disable_unprepare(priv->clk);
3690         return ret;
3691 }
3692
3693 static int bcmgenet_suspend(struct device *d)
3694 {
3695         struct net_device *dev = dev_get_drvdata(d);
3696         struct bcmgenet_priv *priv = netdev_priv(dev);
3697         int ret = 0;
3698
3699         if (!netif_running(dev))
3700                 return 0;
3701
3702         netif_device_detach(dev);
3703
3704         bcmgenet_netif_stop(dev);
3705
3706         if (!device_may_wakeup(d))
3707                 phy_suspend(dev->phydev);
3708
3709         /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3710         if (device_may_wakeup(d) && priv->wolopts) {
3711                 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
3712                 clk_prepare_enable(priv->clk_wol);
3713         } else if (priv->internal_phy) {
3714                 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3715         }
3716
3717         /* Turn off the clocks */
3718         clk_disable_unprepare(priv->clk);
3719
3720         if (ret)
3721                 bcmgenet_resume(d);
3722
3723         return ret;
3724 }
3725 #endif /* CONFIG_PM_SLEEP */
3726
3727 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3728
3729 static const struct acpi_device_id genet_acpi_match[] = {
3730         { "BCM6E4E", (kernel_ulong_t)&bcm2711_plat_data },
3731         { },
3732 };
3733 MODULE_DEVICE_TABLE(acpi, genet_acpi_match);
3734
3735 static struct platform_driver bcmgenet_driver = {
3736         .probe  = bcmgenet_probe,
3737         .remove = bcmgenet_remove,
3738         .shutdown = bcmgenet_shutdown,
3739         .driver = {
3740                 .name   = "bcmgenet",
3741                 .of_match_table = bcmgenet_match,
3742                 .pm     = &bcmgenet_pm_ops,
3743                 .acpi_match_table = ACPI_PTR(genet_acpi_match),
3744         },
3745 };
3746 module_platform_driver(bcmgenet_driver);
3747
3748 MODULE_AUTHOR("Broadcom Corporation");
3749 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3750 MODULE_ALIAS("platform:bcmgenet");
3751 MODULE_LICENSE("GPL");