drivers/net/ethernet/broadcom/genet/bcmmii.c

   1 /*
   2  * Broadcom GENET MDIO routines
   3  *
   4  * Copyright (c) 2014 Broadcom Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11
  12 #include <linux/types.h>
  13 #include <linux/delay.h>
  14 #include <linux/wait.h>
  15 #include <linux/mii.h>
  16 #include <linux/ethtool.h>
  17 #include <linux/bitops.h>
  18 #include <linux/netdevice.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/phy.h>
  21 #include <linux/phy_fixed.h>
  22 #include <linux/brcmphy.h>
  23 #include <linux/of.h>
  24 #include <linux/of_net.h>
  25 #include <linux/of_mdio.h>
  26 #include <linux/platform_data/bcmgenet.h>
  27
  28 #include "bcmgenet.h"
  29
  30 /* read a value from the MII */
  31 static int bcmgenet_mii_read(struct mii_bus *bus, int phy_id, int location)
  32 {
  33         int ret;
  34         struct net_device *dev = bus->priv;
  35         struct bcmgenet_priv *priv = netdev_priv(dev);
  36         u32 reg;
  37
  38         bcmgenet_umac_writel(priv, (MDIO_RD | (phy_id << MDIO_PMD_SHIFT) |
  39                              (location << MDIO_REG_SHIFT)), UMAC_MDIO_CMD);
  40         /* Start MDIO transaction*/
  41         reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
  42         reg |= MDIO_START_BUSY;
  43         bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
  44         wait_event_timeout(priv->wq,
  45                            !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
  46                            & MDIO_START_BUSY),
  47                            HZ / 100);
  48         ret = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
  49
  50         if (ret & MDIO_READ_FAIL)
  51                 return -EIO;
  52
  53         return ret & 0xffff;
  54 }
  55
  56 /* write a value to the MII */
  57 static int bcmgenet_mii_write(struct mii_bus *bus, int phy_id,
  58                               int location, u16 val)
  59 {
  60         struct net_device *dev = bus->priv;
  61         struct bcmgenet_priv *priv = netdev_priv(dev);
  62         u32 reg;
  63
  64         bcmgenet_umac_writel(priv, (MDIO_WR | (phy_id << MDIO_PMD_SHIFT) |
  65                              (location << MDIO_REG_SHIFT) | (0xffff & val)),
  66                              UMAC_MDIO_CMD);
  67         reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
  68         reg |= MDIO_START_BUSY;
  69         bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
  70         wait_event_timeout(priv->wq,
  71                            !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) &
  72                            MDIO_START_BUSY),
  73                            HZ / 100);
  74
  75         return 0;
  76 }
  77
  78 /* setup netdev link state when PHY link status change and
  79  * update UMAC and RGMII block when link up
  80  */
  81 void bcmgenet_mii_setup(struct net_device *dev)
  82 {
  83         struct bcmgenet_priv *priv = netdev_priv(dev);
  84         struct phy_device *phydev = priv->phydev;
  85         u32 reg, cmd_bits = 0;
  86         bool status_changed = false;
  87
  88         if (priv->old_link != phydev->link) {
  89                 status_changed = true;
  90                 priv->old_link = phydev->link;
  91         }
  92
  93         if (phydev->link) {
  94                 /* check speed/duplex/pause changes */
  95                 if (priv->old_speed != phydev->speed) {
  96                         status_changed = true;
  97                         priv->old_speed = phydev->speed;
  98                 }
  99
 100                 if (priv->old_duplex != phydev->duplex) {
 101                         status_changed = true;
 102                         priv->old_duplex = phydev->duplex;
 103                 }
 104
 105                 if (priv->old_pause != phydev->pause) {
 106                         status_changed = true;
 107                         priv->old_pause = phydev->pause;
 108                 }
 109
 110                 /* done if nothing has changed */
 111                 if (!status_changed)
 112                         return;
 113
 114                 /* speed */
 115                 if (phydev->speed == SPEED_1000)
 116                         cmd_bits = UMAC_SPEED_1000;
 117                 else if (phydev->speed == SPEED_100)
 118                         cmd_bits = UMAC_SPEED_100;
 119                 else
 120                         cmd_bits = UMAC_SPEED_10;
 121                 cmd_bits <<= CMD_SPEED_SHIFT;
 122
 123                 /* duplex */
 124                 if (phydev->duplex != DUPLEX_FULL)
 125                         cmd_bits |= CMD_HD_EN;
 126
 127                 /* pause capability */
 128                 if (!phydev->pause)
 129                         cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
 130
 131                 /*
 132                  * Program UMAC and RGMII block based on established
 133                  * link speed, duplex, and pause. The speed set in
 134                  * umac->cmd tell RGMII block which clock to use for
 135                  * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
 136                  * Receive clock is provided by the PHY.
 137                  */
 138                 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
 139                 reg &= ~OOB_DISABLE;
 140                 reg |= RGMII_LINK;
 141                 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
 142
 143                 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
 144                 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
 145                                CMD_HD_EN |
 146                                CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE);
 147                 reg |= cmd_bits;
 148                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
 149         } else {
 150                 /* done if nothing has changed */
 151                 if (!status_changed)
 152                         return;
 153
 154                 /* needed for MoCA fixed PHY to reflect correct link status */
 155                 netif_carrier_off(dev);
 156         }
 157
 158         phy_print_status(phydev);
 159 }
 160
 161 void bcmgenet_mii_reset(struct net_device *dev)
 162 {
 163         struct bcmgenet_priv *priv = netdev_priv(dev);
 164
 165         if (priv->phydev) {
 166                 phy_init_hw(priv->phydev);
 167                 phy_start_aneg(priv->phydev);
 168         }
 169 }
 170
 171 static void bcmgenet_phy_power_set(struct net_device *dev, bool enable)
 172 {
 173         struct bcmgenet_priv *priv = netdev_priv(dev);
 174         u32 reg = 0;
 175
 176         /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
 177         if (!GENET_IS_V4(priv))
 178                 return;
 179
 180         if (enable) {
 181                 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
 182                 reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | EXT_CK25_DIS);
 183                 reg |= EXT_GPHY_RESET;
 184                 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 185                 mdelay(2);
 186
 187                 reg &= ~EXT_GPHY_RESET;
 188                 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 189                 udelay(20);
 190         }
 191 }
 192
 193 static void bcmgenet_internal_phy_setup(struct net_device *dev)
 194 {
 195         struct bcmgenet_priv *priv = netdev_priv(dev);
 196         u32 reg;
 197
 198         /* Power up PHY */
 199         bcmgenet_phy_power_set(dev, true);
 200         /* enable APD */
 201         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
 202         reg |= EXT_PWR_DN_EN_LD;
 203         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
 204         bcmgenet_mii_reset(dev);
 205 }
 206
 207 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
 208 {
 209         u32 reg;
 210
 211         /* Speed settings are set in bcmgenet_mii_setup() */
 212         reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL);
 213         reg |= LED_ACT_SOURCE_MAC;
 214         bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL);
 215 }
 216
 217 int bcmgenet_mii_config(struct net_device *dev, bool init)
 218 {
 219         struct bcmgenet_priv *priv = netdev_priv(dev);
 220         struct phy_device *phydev = priv->phydev;
 221         struct device *kdev = &priv->pdev->dev;
 222         const char *phy_name = NULL;
 223         u32 id_mode_dis = 0;
 224         u32 port_ctrl;
 225         u32 reg;
 226
 227         priv->ext_phy = !phy_is_internal(priv->phydev) &&
 228                         (priv->phy_interface != PHY_INTERFACE_MODE_MOCA);
 229
 230         if (phy_is_internal(priv->phydev))
 231                 priv->phy_interface = PHY_INTERFACE_MODE_NA;
 232
 233         switch (priv->phy_interface) {
 234         case PHY_INTERFACE_MODE_NA:
 235         case PHY_INTERFACE_MODE_MOCA:
 236                 /* Irrespective of the actually configured PHY speed (100 or
 237                  * 1000) GENETv4 only has an internal GPHY so we will just end
 238                  * up masking the Gigabit features from what we support, not
 239                  * switching to the EPHY
 240                  */
 241                 if (GENET_IS_V4(priv))
 242                         port_ctrl = PORT_MODE_INT_GPHY;
 243                 else
 244                         port_ctrl = PORT_MODE_INT_EPHY;
 245
 246                 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
 247
 248                 if (phy_is_internal(priv->phydev)) {
 249                         phy_name = "internal PHY";
 250                         bcmgenet_internal_phy_setup(dev);
 251                 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
 252                         phy_name = "MoCA";
 253                         bcmgenet_moca_phy_setup(priv);
 254                 }
 255                 break;
 256
 257         case PHY_INTERFACE_MODE_MII:
 258                 phy_name = "external MII";
 259                 phydev->supported &= PHY_BASIC_FEATURES;
 260                 bcmgenet_sys_writel(priv,
 261                                     PORT_MODE_EXT_EPHY, SYS_PORT_CTRL);
 262                 break;
 263
 264         case PHY_INTERFACE_MODE_REVMII:
 265                 phy_name = "external RvMII";
 266                 /* of_mdiobus_register took care of reading the 'max-speed'
 267                  * PHY property for us, effectively limiting the PHY supported
 268                  * capabilities, use that knowledge to also configure the
 269                  * Reverse MII interface correctly.
 270                  */
 271                 if ((priv->phydev->supported & PHY_BASIC_FEATURES) ==
 272                                 PHY_BASIC_FEATURES)
 273                         port_ctrl = PORT_MODE_EXT_RVMII_25;
 274                 else
 275                         port_ctrl = PORT_MODE_EXT_RVMII_50;
 276                 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
 277                 break;
 278
 279         case PHY_INTERFACE_MODE_RGMII:
 280                 /* RGMII_NO_ID: TXC transitions at the same time as TXD
 281                  *              (requires PCB or receiver-side delay)
 282                  * RGMII:       Add 2ns delay on TXC (90 degree shift)
 283                  *
 284                  * ID is implicitly disabled for 100Mbps (RG)MII operation.
 285                  */
 286                 id_mode_dis = BIT(16);
 287                 /* fall through */
 288         case PHY_INTERFACE_MODE_RGMII_TXID:
 289                 if (id_mode_dis)
 290                         phy_name = "external RGMII (no delay)";
 291                 else
 292                         phy_name = "external RGMII (TX delay)";
 293                 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
 294                 reg |= RGMII_MODE_EN | id_mode_dis;
 295                 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
 296                 bcmgenet_sys_writel(priv,
 297                                     PORT_MODE_EXT_GPHY, SYS_PORT_CTRL);
 298                 break;
 299         default:
 300                 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
 301                 return -EINVAL;
 302         }
 303
 304         if (init)
 305                 dev_info(kdev, "configuring instance for %s\n", phy_name);
 306
 307         return 0;
 308 }
 309
 310 static int bcmgenet_mii_probe(struct net_device *dev)
 311 {
 312         struct bcmgenet_priv *priv = netdev_priv(dev);
 313         struct device_node *dn = priv->pdev->dev.of_node;
 314         struct phy_device *phydev;
 315         u32 phy_flags;
 316         int ret;
 317
 318         /* Communicate the integrated PHY revision */
 319         phy_flags = priv->gphy_rev;
 320
 321         /* Initialize link state variables that bcmgenet_mii_setup() uses */
 322         priv->old_link = -1;
 323         priv->old_speed = -1;
 324         priv->old_duplex = -1;
 325         priv->old_pause = -1;
 326
 327         if (dn) {
 328                 if (priv->phydev) {
 329                         pr_info("PHY already attached\n");
 330                         return 0;
 331                 }
 332
 333                 /* In the case of a fixed PHY, the DT node associated
 334                  * to the PHY is the Ethernet MAC DT node.
 335                  */
 336                 if (!priv->phy_dn && of_phy_is_fixed_link(dn)) {
 337                         ret = of_phy_register_fixed_link(dn);
 338                         if (ret)
 339                                 return ret;
 340
 341                         priv->phy_dn = of_node_get(dn);
 342                 }
 343
 344                 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup,
 345                                         phy_flags, priv->phy_interface);
 346                 if (!phydev) {
 347                         pr_err("could not attach to PHY\n");
 348                         return -ENODEV;
 349                 }
 350         } else {
 351                 phydev = priv->phydev;
 352                 phydev->dev_flags = phy_flags;
 353
 354                 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup,
 355                                          priv->phy_interface);
 356                 if (ret) {
 357                         pr_err("could not attach to PHY\n");
 358                         return -ENODEV;
 359                 }
 360         }
 361
 362         priv->phydev = phydev;
 363
 364         /* Configure port multiplexer based on what the probed PHY device since
 365          * reading the 'max-speed' property determines the maximum supported
 366          * PHY speed which is needed for bcmgenet_mii_config() to configure
 367          * things appropriately.
 368          */
 369         ret = bcmgenet_mii_config(dev, true);
 370         if (ret) {
 371                 phy_disconnect(priv->phydev);
 372                 return ret;
 373         }
 374
 375         phydev->advertising = phydev->supported;
 376
 377         /* The internal PHY has its link interrupts routed to the
 378          * Ethernet MAC ISRs
 379          */
 380         if (phy_is_internal(priv->phydev))
 381                 priv->mii_bus->irq[phydev->addr] = PHY_IGNORE_INTERRUPT;
 382         else
 383                 priv->mii_bus->irq[phydev->addr] = PHY_POLL;
 384
 385         pr_info("attached PHY at address %d [%s]\n",
 386                 phydev->addr, phydev->drv->name);
 387
 388         return 0;
 389 }
 390
 391 static int bcmgenet_mii_alloc(struct bcmgenet_priv *priv)
 392 {
 393         struct mii_bus *bus;
 394
 395         if (priv->mii_bus)
 396                 return 0;
 397
 398         priv->mii_bus = mdiobus_alloc();
 399         if (!priv->mii_bus) {
 400                 pr_err("failed to allocate\n");
 401                 return -ENOMEM;
 402         }
 403
 404         bus = priv->mii_bus;
 405         bus->priv = priv->dev;
 406         bus->name = "bcmgenet MII bus";
 407         bus->parent = &priv->pdev->dev;
 408         bus->read = bcmgenet_mii_read;
 409         bus->write = bcmgenet_mii_write;
 410         snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d",
 411                  priv->pdev->name, priv->pdev->id);
 412
 413         bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
 414         if (!bus->irq) {
 415                 mdiobus_free(priv->mii_bus);
 416                 return -ENOMEM;
 417         }
 418
 419         return 0;
 420 }
 421
 422 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
 423 {
 424         struct device_node *dn = priv->pdev->dev.of_node;
 425         struct device *kdev = &priv->pdev->dev;
 426         struct device_node *mdio_dn;
 427         char *compat;
 428         int ret;
 429
 430         compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
 431         if (!compat)
 432                 return -ENOMEM;
 433
 434         mdio_dn = of_find_compatible_node(dn, NULL, compat);
 435         kfree(compat);
 436         if (!mdio_dn) {
 437                 dev_err(kdev, "unable to find MDIO bus node\n");
 438                 return -ENODEV;
 439         }
 440
 441         ret = of_mdiobus_register(priv->mii_bus, mdio_dn);
 442         if (ret) {
 443                 dev_err(kdev, "failed to register MDIO bus\n");
 444                 return ret;
 445         }
 446
 447         /* Fetch the PHY phandle */
 448         priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);
 449
 450         /* Get the link mode */
 451         priv->phy_interface = of_get_phy_mode(dn);
 452
 453         return 0;
 454 }
 455
 456 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv)
 457 {
 458         struct device *kdev = &priv->pdev->dev;
 459         struct bcmgenet_platform_data *pd = kdev->platform_data;
 460         struct mii_bus *mdio = priv->mii_bus;
 461         struct phy_device *phydev;
 462         int ret;
 463
 464         if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
 465                 /*
 466                  * Internal or external PHY with MDIO access
 467                  */
 468                 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
 469                         mdio->phy_mask = ~(1 << pd->phy_address);
 470                 else
 471                         mdio->phy_mask = 0;
 472
 473                 ret = mdiobus_register(mdio);
 474                 if (ret) {
 475                         dev_err(kdev, "failed to register MDIO bus\n");
 476                         return ret;
 477                 }
 478
 479                 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
 480                         phydev = mdio->phy_map[pd->phy_address];
 481                 else
 482                         phydev = phy_find_first(mdio);
 483
 484                 if (!phydev) {
 485                         dev_err(kdev, "failed to register PHY device\n");
 486                         mdiobus_unregister(mdio);
 487                         return -ENODEV;
 488                 }
 489         } else {
 490                 /*
 491                  * MoCA port or no MDIO access.
 492                  * Use fixed PHY to represent the link layer.
 493                  */
 494                 struct fixed_phy_status fphy_status = {
 495                         .link = 1,
 496                         .speed = pd->phy_speed,
 497                         .duplex = pd->phy_duplex,
 498                         .pause = 0,
 499                         .asym_pause = 0,
 500                 };
 501
 502                 phydev = fixed_phy_register(PHY_POLL, &fphy_status, NULL);
 503                 if (!phydev || IS_ERR(phydev)) {
 504                         dev_err(kdev, "failed to register fixed PHY device\n");
 505                         return -ENODEV;
 506                 }
 507         }
 508
 509         priv->phydev = phydev;
 510         priv->phy_interface = pd->phy_interface;
 511
 512         return 0;
 513 }
 514
 515 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv)
 516 {
 517         struct device_node *dn = priv->pdev->dev.of_node;
 518
 519         if (dn)
 520                 return bcmgenet_mii_of_init(priv);
 521         else
 522                 return bcmgenet_mii_pd_init(priv);
 523 }
 524
 525 int bcmgenet_mii_init(struct net_device *dev)
 526 {
 527         struct bcmgenet_priv *priv = netdev_priv(dev);
 528         int ret;
 529
 530         ret = bcmgenet_mii_alloc(priv);
 531         if (ret)
 532                 return ret;
 533
 534         ret = bcmgenet_mii_bus_init(priv);
 535         if (ret)
 536                 goto out_free;
 537
 538         ret = bcmgenet_mii_probe(dev);
 539         if (ret)
 540                 goto out;
 541
 542         return 0;
 543
 544 out:
 545         of_node_put(priv->phy_dn);
 546         mdiobus_unregister(priv->mii_bus);
 547 out_free:
 548         kfree(priv->mii_bus->irq);
 549         mdiobus_free(priv->mii_bus);
 550         return ret;
 551 }
 552
 553 void bcmgenet_mii_exit(struct net_device *dev)
 554 {
 555         struct bcmgenet_priv *priv = netdev_priv(dev);
 556
 557         of_node_put(priv->phy_dn);
 558         mdiobus_unregister(priv->mii_bus);
 559         kfree(priv->mii_bus->irq);
 560         mdiobus_free(priv->mii_bus);
 561 }