drivers/net/ethernet/broadcom/genet/bcmmii.c

   1 /*
   2  * Broadcom GENET MDIO routines
   3  *
   4  * Copyright (c) 2014 Broadcom Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11
  12 #include <linux/types.h>
  13 #include <linux/delay.h>
  14 #include <linux/wait.h>
  15 #include <linux/mii.h>
  16 #include <linux/ethtool.h>
  17 #include <linux/bitops.h>
  18 #include <linux/netdevice.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/phy.h>
  21 #include <linux/phy_fixed.h>
  22 #include <linux/brcmphy.h>
  23 #include <linux/of.h>
  24 #include <linux/of_net.h>
  25 #include <linux/of_mdio.h>
  26 #include <linux/platform_data/bcmgenet.h>
  27
  28 #include "bcmgenet.h"
  29
  30 /* read a value from the MII */
  31 static int bcmgenet_mii_read(struct mii_bus *bus, int phy_id, int location)
  32 {
  33         int ret;
  34         struct net_device *dev = bus->priv;
  35         struct bcmgenet_priv *priv = netdev_priv(dev);
  36         u32 reg;
  37
  38         bcmgenet_umac_writel(priv, (MDIO_RD | (phy_id << MDIO_PMD_SHIFT) |
  39                              (location << MDIO_REG_SHIFT)), UMAC_MDIO_CMD);
  40         /* Start MDIO transaction*/
  41         reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
  42         reg |= MDIO_START_BUSY;
  43         bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
  44         wait_event_timeout(priv->wq,
  45                            !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
  46                            & MDIO_START_BUSY),
  47                            HZ / 100);
  48         ret = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
  49
  50         if (ret & MDIO_READ_FAIL)
  51                 return -EIO;
  52
  53         return ret & 0xffff;
  54 }
  55
  56 /* write a value to the MII */
  57 static int bcmgenet_mii_write(struct mii_bus *bus, int phy_id,
  58                               int location, u16 val)
  59 {
  60         struct net_device *dev = bus->priv;
  61         struct bcmgenet_priv *priv = netdev_priv(dev);
  62         u32 reg;
  63
  64         bcmgenet_umac_writel(priv, (MDIO_WR | (phy_id << MDIO_PMD_SHIFT) |
  65                              (location << MDIO_REG_SHIFT) | (0xffff & val)),
  66                              UMAC_MDIO_CMD);
  67         reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
  68         reg |= MDIO_START_BUSY;
  69         bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
  70         wait_event_timeout(priv->wq,
  71                            !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) &
  72                            MDIO_START_BUSY),
  73                            HZ / 100);
  74
  75         return 0;
  76 }
  77
  78 /* setup netdev link state when PHY link status change and
  79  * update UMAC and RGMII block when link up
  80  */
  81 void bcmgenet_mii_setup(struct net_device *dev)
  82 {
  83         struct bcmgenet_priv *priv = netdev_priv(dev);
  84         struct phy_device *phydev = priv->phydev;
  85         u32 reg, cmd_bits = 0;
  86         bool status_changed = false;
  87
  88         if (priv->old_link != phydev->link) {
  89                 status_changed = true;
  90                 priv->old_link = phydev->link;
  91         }
  92
  93         if (phydev->link) {
  94                 /* check speed/duplex/pause changes */
  95                 if (priv->old_speed != phydev->speed) {
  96                         status_changed = true;
  97                         priv->old_speed = phydev->speed;
  98                 }
  99
 100                 if (priv->old_duplex != phydev->duplex) {
 101                         status_changed = true;
 102                         priv->old_duplex = phydev->duplex;
 103                 }
 104
 105                 if (priv->old_pause != phydev->pause) {
 106                         status_changed = true;
 107                         priv->old_pause = phydev->pause;
 108                 }
 109
 110                 /* done if nothing has changed */
 111                 if (!status_changed)
 112                         return;
 113
 114                 /* speed */
 115                 if (phydev->speed == SPEED_1000)
 116                         cmd_bits = UMAC_SPEED_1000;
 117                 else if (phydev->speed == SPEED_100)
 118                         cmd_bits = UMAC_SPEED_100;
 119                 else
 120                         cmd_bits = UMAC_SPEED_10;
 121                 cmd_bits <<= CMD_SPEED_SHIFT;
 122
 123                 /* duplex */
 124                 if (phydev->duplex != DUPLEX_FULL)
 125                         cmd_bits |= CMD_HD_EN;
 126
 127                 /* pause capability */
 128                 if (!phydev->pause)
 129                         cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
 130
 131                 /*
 132                  * Program UMAC and RGMII block based on established
 133                  * link speed, duplex, and pause. The speed set in
 134                  * umac->cmd tell RGMII block which clock to use for
 135                  * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
 136                  * Receive clock is provided by the PHY.
 137                  */
 138                 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
 139                 reg &= ~OOB_DISABLE;
 140                 reg |= RGMII_LINK;
 141                 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
 142
 143                 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
 144                 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
 145                                CMD_HD_EN |
 146                                CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE);
 147                 reg |= cmd_bits;
 148                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
 149         } else {
 150                 /* done if nothing has changed */
 151                 if (!status_changed)
 152                         return;
 153
 154                 /* needed for MoCA fixed PHY to reflect correct link status */
 155                 netif_carrier_off(dev);
 156         }
 157
 158         phy_print_status(phydev);
 159 }
 160
 161 void bcmgenet_mii_reset(struct net_device *dev)
 162 {
 163         struct bcmgenet_priv *priv = netdev_priv(dev);
 164
 165         if (priv->phydev) {
 166                 phy_init_hw(priv->phydev);
 167                 phy_start_aneg(priv->phydev);
 168         }
 169 }
 170
 171 static void bcmgenet_ephy_power_up(struct net_device *dev)
 172 {
 173         struct bcmgenet_priv *priv = netdev_priv(dev);
 174         u32 reg = 0;
 175
 176         /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
 177         if (!GENET_IS_V4(priv))
 178                 return;
 179
 180         reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
 181         reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN);
 182         reg |= EXT_GPHY_RESET;
 183         bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 184         mdelay(2);
 185
 186         reg &= ~EXT_GPHY_RESET;
 187         bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 188         udelay(20);
 189 }
 190
 191 static void bcmgenet_internal_phy_setup(struct net_device *dev)
 192 {
 193         struct bcmgenet_priv *priv = netdev_priv(dev);
 194         u32 reg;
 195
 196         /* Power up EPHY */
 197         bcmgenet_ephy_power_up(dev);
 198         /* enable APD */
 199         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
 200         reg |= EXT_PWR_DN_EN_LD;
 201         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
 202         bcmgenet_mii_reset(dev);
 203 }
 204
 205 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
 206 {
 207         u32 reg;
 208
 209         /* Speed settings are set in bcmgenet_mii_setup() */
 210         reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL);
 211         reg |= LED_ACT_SOURCE_MAC;
 212         bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL);
 213 }
 214
 215 int bcmgenet_mii_config(struct net_device *dev, bool init)
 216 {
 217         struct bcmgenet_priv *priv = netdev_priv(dev);
 218         struct phy_device *phydev = priv->phydev;
 219         struct device *kdev = &priv->pdev->dev;
 220         const char *phy_name = NULL;
 221         u32 id_mode_dis = 0;
 222         u32 port_ctrl;
 223         u32 reg;
 224
 225         priv->ext_phy = !phy_is_internal(priv->phydev) &&
 226                         (priv->phy_interface != PHY_INTERFACE_MODE_MOCA);
 227
 228         if (phy_is_internal(priv->phydev))
 229                 priv->phy_interface = PHY_INTERFACE_MODE_NA;
 230
 231         switch (priv->phy_interface) {
 232         case PHY_INTERFACE_MODE_NA:
 233         case PHY_INTERFACE_MODE_MOCA:
 234                 /* Irrespective of the actually configured PHY speed (100 or
 235                  * 1000) GENETv4 only has an internal GPHY so we will just end
 236                  * up masking the Gigabit features from what we support, not
 237                  * switching to the EPHY
 238                  */
 239                 if (GENET_IS_V4(priv))
 240                         port_ctrl = PORT_MODE_INT_GPHY;
 241                 else
 242                         port_ctrl = PORT_MODE_INT_EPHY;
 243
 244                 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
 245
 246                 if (phy_is_internal(priv->phydev)) {
 247                         phy_name = "internal PHY";
 248                         bcmgenet_internal_phy_setup(dev);
 249                 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
 250                         phy_name = "MoCA";
 251                         bcmgenet_moca_phy_setup(priv);
 252                 }
 253                 break;
 254
 255         case PHY_INTERFACE_MODE_MII:
 256                 phy_name = "external MII";
 257                 phydev->supported &= PHY_BASIC_FEATURES;
 258                 bcmgenet_sys_writel(priv,
 259                                     PORT_MODE_EXT_EPHY, SYS_PORT_CTRL);
 260                 break;
 261
 262         case PHY_INTERFACE_MODE_REVMII:
 263                 phy_name = "external RvMII";
 264                 /* of_mdiobus_register took care of reading the 'max-speed'
 265                  * PHY property for us, effectively limiting the PHY supported
 266                  * capabilities, use that knowledge to also configure the
 267                  * Reverse MII interface correctly.
 268                  */
 269                 if ((priv->phydev->supported & PHY_BASIC_FEATURES) ==
 270                                 PHY_BASIC_FEATURES)
 271                         port_ctrl = PORT_MODE_EXT_RVMII_25;
 272                 else
 273                         port_ctrl = PORT_MODE_EXT_RVMII_50;
 274                 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
 275                 break;
 276
 277         case PHY_INTERFACE_MODE_RGMII:
 278                 /* RGMII_NO_ID: TXC transitions at the same time as TXD
 279                  *              (requires PCB or receiver-side delay)
 280                  * RGMII:       Add 2ns delay on TXC (90 degree shift)
 281                  *
 282                  * ID is implicitly disabled for 100Mbps (RG)MII operation.
 283                  */
 284                 id_mode_dis = BIT(16);
 285                 /* fall through */
 286         case PHY_INTERFACE_MODE_RGMII_TXID:
 287                 if (id_mode_dis)
 288                         phy_name = "external RGMII (no delay)";
 289                 else
 290                         phy_name = "external RGMII (TX delay)";
 291                 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
 292                 reg |= RGMII_MODE_EN | id_mode_dis;
 293                 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
 294                 bcmgenet_sys_writel(priv,
 295                                     PORT_MODE_EXT_GPHY, SYS_PORT_CTRL);
 296                 break;
 297         default:
 298                 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
 299                 return -EINVAL;
 300         }
 301
 302         if (init)
 303                 dev_info(kdev, "configuring instance for %s\n", phy_name);
 304
 305         return 0;
 306 }
 307
 308 static int bcmgenet_mii_probe(struct net_device *dev)
 309 {
 310         struct bcmgenet_priv *priv = netdev_priv(dev);
 311         struct device_node *dn = priv->pdev->dev.of_node;
 312         struct phy_device *phydev;
 313         u32 phy_flags;
 314         int ret;
 315
 316         /* Communicate the integrated PHY revision */
 317         phy_flags = priv->gphy_rev;
 318
 319         /* Initialize link state variables that bcmgenet_mii_setup() uses */
 320         priv->old_link = -1;
 321         priv->old_speed = -1;
 322         priv->old_duplex = -1;
 323         priv->old_pause = -1;
 324
 325         if (dn) {
 326                 if (priv->phydev) {
 327                         pr_info("PHY already attached\n");
 328                         return 0;
 329                 }
 330
 331                 /* In the case of a fixed PHY, the DT node associated
 332                  * to the PHY is the Ethernet MAC DT node.
 333                  */
 334                 if (!priv->phy_dn && of_phy_is_fixed_link(dn)) {
 335                         ret = of_phy_register_fixed_link(dn);
 336                         if (ret)
 337                                 return ret;
 338
 339                         priv->phy_dn = of_node_get(dn);
 340                 }
 341
 342                 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup,
 343                                         phy_flags, priv->phy_interface);
 344                 if (!phydev) {
 345                         pr_err("could not attach to PHY\n");
 346                         return -ENODEV;
 347                 }
 348         } else {
 349                 phydev = priv->phydev;
 350                 phydev->dev_flags = phy_flags;
 351
 352                 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup,
 353                                          priv->phy_interface);
 354                 if (ret) {
 355                         pr_err("could not attach to PHY\n");
 356                         return -ENODEV;
 357                 }
 358         }
 359
 360         priv->phydev = phydev;
 361
 362         /* Configure port multiplexer based on what the probed PHY device since
 363          * reading the 'max-speed' property determines the maximum supported
 364          * PHY speed which is needed for bcmgenet_mii_config() to configure
 365          * things appropriately.
 366          */
 367         ret = bcmgenet_mii_config(dev, true);
 368         if (ret) {
 369                 phy_disconnect(priv->phydev);
 370                 return ret;
 371         }
 372
 373         phydev->advertising = phydev->supported;
 374
 375         /* The internal PHY has its link interrupts routed to the
 376          * Ethernet MAC ISRs
 377          */
 378         if (phy_is_internal(priv->phydev))
 379                 priv->mii_bus->irq[phydev->addr] = PHY_IGNORE_INTERRUPT;
 380         else
 381                 priv->mii_bus->irq[phydev->addr] = PHY_POLL;
 382
 383         pr_info("attached PHY at address %d [%s]\n",
 384                 phydev->addr, phydev->drv->name);
 385
 386         return 0;
 387 }
 388
 389 static int bcmgenet_mii_alloc(struct bcmgenet_priv *priv)
 390 {
 391         struct mii_bus *bus;
 392
 393         if (priv->mii_bus)
 394                 return 0;
 395
 396         priv->mii_bus = mdiobus_alloc();
 397         if (!priv->mii_bus) {
 398                 pr_err("failed to allocate\n");
 399                 return -ENOMEM;
 400         }
 401
 402         bus = priv->mii_bus;
 403         bus->priv = priv->dev;
 404         bus->name = "bcmgenet MII bus";
 405         bus->parent = &priv->pdev->dev;
 406         bus->read = bcmgenet_mii_read;
 407         bus->write = bcmgenet_mii_write;
 408         snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d",
 409                  priv->pdev->name, priv->pdev->id);
 410
 411         bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
 412         if (!bus->irq) {
 413                 mdiobus_free(priv->mii_bus);
 414                 return -ENOMEM;
 415         }
 416
 417         return 0;
 418 }
 419
 420 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
 421 {
 422         struct device_node *dn = priv->pdev->dev.of_node;
 423         struct device *kdev = &priv->pdev->dev;
 424         struct device_node *mdio_dn;
 425         char *compat;
 426         int ret;
 427
 428         compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
 429         if (!compat)
 430                 return -ENOMEM;
 431
 432         mdio_dn = of_find_compatible_node(dn, NULL, compat);
 433         kfree(compat);
 434         if (!mdio_dn) {
 435                 dev_err(kdev, "unable to find MDIO bus node\n");
 436                 return -ENODEV;
 437         }
 438
 439         ret = of_mdiobus_register(priv->mii_bus, mdio_dn);
 440         if (ret) {
 441                 dev_err(kdev, "failed to register MDIO bus\n");
 442                 return ret;
 443         }
 444
 445         /* Fetch the PHY phandle */
 446         priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);
 447
 448         /* Get the link mode */
 449         priv->phy_interface = of_get_phy_mode(dn);
 450
 451         return 0;
 452 }
 453
 454 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv)
 455 {
 456         struct device *kdev = &priv->pdev->dev;
 457         struct bcmgenet_platform_data *pd = kdev->platform_data;
 458         struct mii_bus *mdio = priv->mii_bus;
 459         struct phy_device *phydev;
 460         int ret;
 461
 462         if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
 463                 /*
 464                  * Internal or external PHY with MDIO access
 465                  */
 466                 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
 467                         mdio->phy_mask = ~(1 << pd->phy_address);
 468                 else
 469                         mdio->phy_mask = 0;
 470
 471                 ret = mdiobus_register(mdio);
 472                 if (ret) {
 473                         dev_err(kdev, "failed to register MDIO bus\n");
 474                         return ret;
 475                 }
 476
 477                 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
 478                         phydev = mdio->phy_map[pd->phy_address];
 479                 else
 480                         phydev = phy_find_first(mdio);
 481
 482                 if (!phydev) {
 483                         dev_err(kdev, "failed to register PHY device\n");
 484                         mdiobus_unregister(mdio);
 485                         return -ENODEV;
 486                 }
 487         } else {
 488                 /*
 489                  * MoCA port or no MDIO access.
 490                  * Use fixed PHY to represent the link layer.
 491                  */
 492                 struct fixed_phy_status fphy_status = {
 493                         .link = 1,
 494                         .speed = pd->phy_speed,
 495                         .duplex = pd->phy_duplex,
 496                         .pause = 0,
 497                         .asym_pause = 0,
 498                 };
 499
 500                 phydev = fixed_phy_register(PHY_POLL, &fphy_status, NULL);
 501                 if (!phydev || IS_ERR(phydev)) {
 502                         dev_err(kdev, "failed to register fixed PHY device\n");
 503                         return -ENODEV;
 504                 }
 505         }
 506
 507         priv->phydev = phydev;
 508         priv->phy_interface = pd->phy_interface;
 509
 510         return 0;
 511 }
 512
 513 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv)
 514 {
 515         struct device_node *dn = priv->pdev->dev.of_node;
 516
 517         if (dn)
 518                 return bcmgenet_mii_of_init(priv);
 519         else
 520                 return bcmgenet_mii_pd_init(priv);
 521 }
 522
 523 int bcmgenet_mii_init(struct net_device *dev)
 524 {
 525         struct bcmgenet_priv *priv = netdev_priv(dev);
 526         int ret;
 527
 528         ret = bcmgenet_mii_alloc(priv);
 529         if (ret)
 530                 return ret;
 531
 532         ret = bcmgenet_mii_bus_init(priv);
 533         if (ret)
 534                 goto out_free;
 535
 536         ret = bcmgenet_mii_probe(dev);
 537         if (ret)
 538                 goto out;
 539
 540         return 0;
 541
 542 out:
 543         of_node_put(priv->phy_dn);
 544         mdiobus_unregister(priv->mii_bus);
 545 out_free:
 546         kfree(priv->mii_bus->irq);
 547         mdiobus_free(priv->mii_bus);
 548         return ret;
 549 }
 550
 551 void bcmgenet_mii_exit(struct net_device *dev)
 552 {
 553         struct bcmgenet_priv *priv = netdev_priv(dev);
 554
 555         of_node_put(priv->phy_dn);
 556         mdiobus_unregister(priv->mii_bus);
 557         kfree(priv->mii_bus->irq);
 558         mdiobus_free(priv->mii_bus);
 559 }