2 * Broadcom GENET MDIO routines
4 * Copyright (c) 2014 Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
12 #include <linux/types.h>
13 #include <linux/delay.h>
14 #include <linux/wait.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/bitops.h>
18 #include <linux/netdevice.h>
19 #include <linux/platform_device.h>
20 #include <linux/phy.h>
21 #include <linux/phy_fixed.h>
22 #include <linux/brcmphy.h>
24 #include <linux/of_net.h>
25 #include <linux/of_mdio.h>
29 /* read a value from the MII */
30 static int bcmgenet_mii_read(struct mii_bus *bus, int phy_id, int location)
33 struct net_device *dev = bus->priv;
34 struct bcmgenet_priv *priv = netdev_priv(dev);
37 bcmgenet_umac_writel(priv, (MDIO_RD | (phy_id << MDIO_PMD_SHIFT) |
38 (location << MDIO_REG_SHIFT)), UMAC_MDIO_CMD);
39 /* Start MDIO transaction*/
40 reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
41 reg |= MDIO_START_BUSY;
42 bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
43 wait_event_timeout(priv->wq,
44 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
47 ret = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
49 if (ret & MDIO_READ_FAIL)
55 /* write a value to the MII */
56 static int bcmgenet_mii_write(struct mii_bus *bus, int phy_id,
57 int location, u16 val)
59 struct net_device *dev = bus->priv;
60 struct bcmgenet_priv *priv = netdev_priv(dev);
63 bcmgenet_umac_writel(priv, (MDIO_WR | (phy_id << MDIO_PMD_SHIFT) |
64 (location << MDIO_REG_SHIFT) | (0xffff & val)),
66 reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
67 reg |= MDIO_START_BUSY;
68 bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
69 wait_event_timeout(priv->wq,
70 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) &
77 /* setup netdev link state when PHY link status change and
78 * update UMAC and RGMII block when link up
80 static void bcmgenet_mii_setup(struct net_device *dev)
82 struct bcmgenet_priv *priv = netdev_priv(dev);
83 struct phy_device *phydev = priv->phydev;
84 u32 reg, cmd_bits = 0;
85 bool status_changed = false;
87 if (priv->old_link != phydev->link) {
88 status_changed = true;
89 priv->old_link = phydev->link;
93 /* check speed/duplex/pause changes */
94 if (priv->old_speed != phydev->speed) {
95 status_changed = true;
96 priv->old_speed = phydev->speed;
99 if (priv->old_duplex != phydev->duplex) {
100 status_changed = true;
101 priv->old_duplex = phydev->duplex;
104 if (priv->old_pause != phydev->pause) {
105 status_changed = true;
106 priv->old_pause = phydev->pause;
109 /* done if nothing has changed */
114 if (phydev->speed == SPEED_1000)
115 cmd_bits = UMAC_SPEED_1000;
116 else if (phydev->speed == SPEED_100)
117 cmd_bits = UMAC_SPEED_100;
119 cmd_bits = UMAC_SPEED_10;
120 cmd_bits <<= CMD_SPEED_SHIFT;
123 if (phydev->duplex != DUPLEX_FULL)
124 cmd_bits |= CMD_HD_EN;
126 /* pause capability */
128 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
131 * Program UMAC and RGMII block based on established
132 * link speed, duplex, and pause. The speed set in
133 * umac->cmd tell RGMII block which clock to use for
134 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
135 * Receive clock is provided by the PHY.
137 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
140 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
142 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
143 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
145 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE);
147 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
149 /* done if nothing has changed */
153 /* needed for MoCA fixed PHY to reflect correct link status */
154 netif_carrier_off(dev);
157 phy_print_status(phydev);
160 void bcmgenet_mii_reset(struct net_device *dev)
162 struct bcmgenet_priv *priv = netdev_priv(dev);
165 phy_init_hw(priv->phydev);
166 phy_start_aneg(priv->phydev);
170 static void bcmgenet_ephy_power_up(struct net_device *dev)
172 struct bcmgenet_priv *priv = netdev_priv(dev);
175 /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
176 if (!GENET_IS_V4(priv))
179 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
180 reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN);
181 reg |= EXT_GPHY_RESET;
182 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
185 reg &= ~EXT_GPHY_RESET;
186 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
190 static void bcmgenet_internal_phy_setup(struct net_device *dev)
192 struct bcmgenet_priv *priv = netdev_priv(dev);
196 bcmgenet_ephy_power_up(dev);
198 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
199 reg |= EXT_PWR_DN_EN_LD;
200 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
201 bcmgenet_mii_reset(dev);
204 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
208 /* Speed settings are set in bcmgenet_mii_setup() */
209 reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL);
210 reg |= LED_ACT_SOURCE_MAC;
211 bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL);
214 int bcmgenet_mii_config(struct net_device *dev)
216 struct bcmgenet_priv *priv = netdev_priv(dev);
217 struct phy_device *phydev = priv->phydev;
218 struct device *kdev = &priv->pdev->dev;
219 const char *phy_name = NULL;
224 priv->ext_phy = !phy_is_internal(priv->phydev) &&
225 (priv->phy_interface != PHY_INTERFACE_MODE_MOCA);
227 if (phy_is_internal(priv->phydev))
228 priv->phy_interface = PHY_INTERFACE_MODE_NA;
230 switch (priv->phy_interface) {
231 case PHY_INTERFACE_MODE_NA:
232 case PHY_INTERFACE_MODE_MOCA:
233 /* Irrespective of the actually configured PHY speed (100 or
234 * 1000) GENETv4 only has an internal GPHY so we will just end
235 * up masking the Gigabit features from what we support, not
236 * switching to the EPHY
238 if (GENET_IS_V4(priv))
239 port_ctrl = PORT_MODE_INT_GPHY;
241 port_ctrl = PORT_MODE_INT_EPHY;
243 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
245 if (phy_is_internal(priv->phydev)) {
246 phy_name = "internal PHY";
247 bcmgenet_internal_phy_setup(dev);
248 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
250 bcmgenet_moca_phy_setup(priv);
254 case PHY_INTERFACE_MODE_MII:
255 phy_name = "external MII";
256 phydev->supported &= PHY_BASIC_FEATURES;
257 bcmgenet_sys_writel(priv,
258 PORT_MODE_EXT_EPHY, SYS_PORT_CTRL);
261 case PHY_INTERFACE_MODE_REVMII:
262 phy_name = "external RvMII";
263 /* of_mdiobus_register took care of reading the 'max-speed'
264 * PHY property for us, effectively limiting the PHY supported
265 * capabilities, use that knowledge to also configure the
266 * Reverse MII interface correctly.
268 if ((priv->phydev->supported & PHY_BASIC_FEATURES) ==
270 port_ctrl = PORT_MODE_EXT_RVMII_25;
272 port_ctrl = PORT_MODE_EXT_RVMII_50;
273 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
276 case PHY_INTERFACE_MODE_RGMII:
277 /* RGMII_NO_ID: TXC transitions at the same time as TXD
278 * (requires PCB or receiver-side delay)
279 * RGMII: Add 2ns delay on TXC (90 degree shift)
281 * ID is implicitly disabled for 100Mbps (RG)MII operation.
283 id_mode_dis = BIT(16);
285 case PHY_INTERFACE_MODE_RGMII_TXID:
287 phy_name = "external RGMII (no delay)";
289 phy_name = "external RGMII (TX delay)";
290 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
291 reg |= RGMII_MODE_EN | id_mode_dis;
292 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
293 bcmgenet_sys_writel(priv,
294 PORT_MODE_EXT_GPHY, SYS_PORT_CTRL);
297 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
301 dev_info(kdev, "configuring instance for %s\n", phy_name);
306 static int bcmgenet_mii_probe(struct net_device *dev)
308 struct bcmgenet_priv *priv = netdev_priv(dev);
309 struct device_node *dn = priv->pdev->dev.of_node;
310 struct phy_device *phydev;
315 pr_info("PHY already attached\n");
319 /* In the case of a fixed PHY, the DT node associated
320 * to the PHY is the Ethernet MAC DT node.
322 if (!priv->phy_dn && of_phy_is_fixed_link(dn)) {
323 ret = of_phy_register_fixed_link(dn);
327 priv->phy_dn = of_node_get(dn);
330 /* Communicate the integrated PHY revision */
331 phy_flags = priv->gphy_rev;
333 /* Initialize link state variables that bcmgenet_mii_setup() uses */
335 priv->old_speed = -1;
336 priv->old_duplex = -1;
337 priv->old_pause = -1;
339 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup,
340 phy_flags, priv->phy_interface);
342 pr_err("could not attach to PHY\n");
346 priv->phydev = phydev;
348 /* Configure port multiplexer based on what the probed PHY device since
349 * reading the 'max-speed' property determines the maximum supported
350 * PHY speed which is needed for bcmgenet_mii_config() to configure
351 * things appropriately.
353 ret = bcmgenet_mii_config(dev);
355 phy_disconnect(priv->phydev);
359 phydev->advertising = phydev->supported;
361 /* The internal PHY has its link interrupts routed to the
364 if (phy_is_internal(priv->phydev))
365 priv->mii_bus->irq[phydev->addr] = PHY_IGNORE_INTERRUPT;
367 priv->mii_bus->irq[phydev->addr] = PHY_POLL;
369 pr_info("attached PHY at address %d [%s]\n",
370 phydev->addr, phydev->drv->name);
375 static int bcmgenet_mii_alloc(struct bcmgenet_priv *priv)
382 priv->mii_bus = mdiobus_alloc();
383 if (!priv->mii_bus) {
384 pr_err("failed to allocate\n");
389 bus->priv = priv->dev;
390 bus->name = "bcmgenet MII bus";
391 bus->parent = &priv->pdev->dev;
392 bus->read = bcmgenet_mii_read;
393 bus->write = bcmgenet_mii_write;
394 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d",
395 priv->pdev->name, priv->pdev->id);
397 bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
399 mdiobus_free(priv->mii_bus);
406 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
408 struct device_node *dn = priv->pdev->dev.of_node;
409 struct device *kdev = &priv->pdev->dev;
410 struct device_node *mdio_dn;
414 compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
418 mdio_dn = of_find_compatible_node(dn, NULL, compat);
421 dev_err(kdev, "unable to find MDIO bus node\n");
425 ret = of_mdiobus_register(priv->mii_bus, mdio_dn);
427 dev_err(kdev, "failed to register MDIO bus\n");
431 /* Fetch the PHY phandle */
432 priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);
434 /* Get the link mode */
435 priv->phy_interface = of_get_phy_mode(dn);
440 int bcmgenet_mii_init(struct net_device *dev)
442 struct bcmgenet_priv *priv = netdev_priv(dev);
445 ret = bcmgenet_mii_alloc(priv);
449 ret = bcmgenet_mii_of_init(priv);
453 ret = bcmgenet_mii_probe(dev);
460 of_node_put(priv->phy_dn);
461 mdiobus_unregister(priv->mii_bus);
463 kfree(priv->mii_bus->irq);
464 mdiobus_free(priv->mii_bus);
468 void bcmgenet_mii_exit(struct net_device *dev)
470 struct bcmgenet_priv *priv = netdev_priv(dev);
472 of_node_put(priv->phy_dn);
473 mdiobus_unregister(priv->mii_bus);
474 kfree(priv->mii_bus->irq);
475 mdiobus_free(priv->mii_bus);