2 * Cadence MACB/GEM Ethernet Controller driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/circ_buf.h>
18 #include <linux/slab.h>
19 #include <linux/init.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_data/macb.h>
27 #include <linux/platform_device.h>
28 #include <linux/phy.h>
30 #include <linux/of_device.h>
31 #include <linux/of_mdio.h>
32 #include <linux/of_net.h>
36 #define MACB_RX_BUFFER_SIZE 128
37 #define RX_BUFFER_MULTIPLE 64 /* bytes */
38 #define RX_RING_SIZE 512 /* must be power of 2 */
39 #define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
41 #define TX_RING_SIZE 128 /* must be power of 2 */
42 #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
44 /* level of occupied TX descriptors under which we wake up TX process */
45 #define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4)
47 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
49 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
52 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
54 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1))
55 #define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1))
57 #define GEM_MTU_MIN_SIZE 68
60 * Graceful stop timeouts in us. We should allow up to
61 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
63 #define MACB_HALT_TIMEOUT 1230
65 /* Ring buffer accessors */
66 static unsigned int macb_tx_ring_wrap(unsigned int index)
68 return index & (TX_RING_SIZE - 1);
71 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
74 return &queue->tx_ring[macb_tx_ring_wrap(index)];
77 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
80 return &queue->tx_skb[macb_tx_ring_wrap(index)];
83 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
87 offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc);
89 return queue->tx_ring_dma + offset;
92 static unsigned int macb_rx_ring_wrap(unsigned int index)
94 return index & (RX_RING_SIZE - 1);
97 static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
99 return &bp->rx_ring[macb_rx_ring_wrap(index)];
102 static void *macb_rx_buffer(struct macb *bp, unsigned int index)
104 return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index);
107 static void macb_set_hwaddr(struct macb *bp)
112 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
113 macb_or_gem_writel(bp, SA1B, bottom);
114 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
115 macb_or_gem_writel(bp, SA1T, top);
117 /* Clear unused address register sets */
118 macb_or_gem_writel(bp, SA2B, 0);
119 macb_or_gem_writel(bp, SA2T, 0);
120 macb_or_gem_writel(bp, SA3B, 0);
121 macb_or_gem_writel(bp, SA3T, 0);
122 macb_or_gem_writel(bp, SA4B, 0);
123 macb_or_gem_writel(bp, SA4T, 0);
126 static void macb_get_hwaddr(struct macb *bp)
128 struct macb_platform_data *pdata;
134 pdata = dev_get_platdata(&bp->pdev->dev);
136 /* Check all 4 address register for vaild address */
137 for (i = 0; i < 4; i++) {
138 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
139 top = macb_or_gem_readl(bp, SA1T + i * 8);
141 if (pdata && pdata->rev_eth_addr) {
142 addr[5] = bottom & 0xff;
143 addr[4] = (bottom >> 8) & 0xff;
144 addr[3] = (bottom >> 16) & 0xff;
145 addr[2] = (bottom >> 24) & 0xff;
146 addr[1] = top & 0xff;
147 addr[0] = (top & 0xff00) >> 8;
149 addr[0] = bottom & 0xff;
150 addr[1] = (bottom >> 8) & 0xff;
151 addr[2] = (bottom >> 16) & 0xff;
152 addr[3] = (bottom >> 24) & 0xff;
153 addr[4] = top & 0xff;
154 addr[5] = (top >> 8) & 0xff;
157 if (is_valid_ether_addr(addr)) {
158 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
163 netdev_info(bp->dev, "invalid hw address, using random\n");
164 eth_hw_addr_random(bp->dev);
167 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
169 struct macb *bp = bus->priv;
172 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
173 | MACB_BF(RW, MACB_MAN_READ)
174 | MACB_BF(PHYA, mii_id)
175 | MACB_BF(REGA, regnum)
176 | MACB_BF(CODE, MACB_MAN_CODE)));
178 /* wait for end of transfer */
179 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
182 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
187 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
190 struct macb *bp = bus->priv;
192 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
193 | MACB_BF(RW, MACB_MAN_WRITE)
194 | MACB_BF(PHYA, mii_id)
195 | MACB_BF(REGA, regnum)
196 | MACB_BF(CODE, MACB_MAN_CODE)
197 | MACB_BF(DATA, value)));
199 /* wait for end of transfer */
200 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
207 * macb_set_tx_clk() - Set a clock to a new frequency
208 * @clk Pointer to the clock to change
209 * @rate New frequency in Hz
210 * @dev Pointer to the struct net_device
212 static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
214 long ferr, rate, rate_rounded;
233 rate_rounded = clk_round_rate(clk, rate);
234 if (rate_rounded < 0)
237 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
240 ferr = abs(rate_rounded - rate);
241 ferr = DIV_ROUND_UP(ferr, rate / 100000);
243 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
246 if (clk_set_rate(clk, rate_rounded))
247 netdev_err(dev, "adjusting tx_clk failed.\n");
250 static void macb_handle_link_change(struct net_device *dev)
252 struct macb *bp = netdev_priv(dev);
253 struct phy_device *phydev = bp->phy_dev;
256 int status_change = 0;
258 spin_lock_irqsave(&bp->lock, flags);
261 if ((bp->speed != phydev->speed) ||
262 (bp->duplex != phydev->duplex)) {
265 reg = macb_readl(bp, NCFGR);
266 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
268 reg &= ~GEM_BIT(GBE);
272 if (phydev->speed == SPEED_100)
273 reg |= MACB_BIT(SPD);
274 if (phydev->speed == SPEED_1000 &&
275 bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
278 macb_or_gem_writel(bp, NCFGR, reg);
280 bp->speed = phydev->speed;
281 bp->duplex = phydev->duplex;
286 if (phydev->link != bp->link) {
291 bp->link = phydev->link;
296 spin_unlock_irqrestore(&bp->lock, flags);
300 /* Update the TX clock rate if and only if the link is
301 * up and there has been a link change.
303 macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
305 netif_carrier_on(dev);
306 netdev_info(dev, "link up (%d/%s)\n",
308 phydev->duplex == DUPLEX_FULL ?
311 netif_carrier_off(dev);
312 netdev_info(dev, "link down\n");
317 /* based on au1000_eth. c*/
318 static int macb_mii_probe(struct net_device *dev)
320 struct macb *bp = netdev_priv(dev);
321 struct macb_platform_data *pdata;
322 struct phy_device *phydev;
326 phydev = phy_find_first(bp->mii_bus);
328 netdev_err(dev, "no PHY found\n");
332 pdata = dev_get_platdata(&bp->pdev->dev);
333 if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
334 ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, "phy int");
336 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
337 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
341 /* attach the mac to the phy */
342 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
345 netdev_err(dev, "Could not attach to PHY\n");
349 /* mask with MAC supported features */
350 if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
351 phydev->supported &= PHY_GBIT_FEATURES;
353 phydev->supported &= PHY_BASIC_FEATURES;
355 phydev->advertising = phydev->supported;
360 bp->phy_dev = phydev;
365 static int macb_mii_init(struct macb *bp)
367 struct macb_platform_data *pdata;
368 struct device_node *np;
371 /* Enable management port */
372 macb_writel(bp, NCR, MACB_BIT(MPE));
374 bp->mii_bus = mdiobus_alloc();
375 if (bp->mii_bus == NULL) {
380 bp->mii_bus->name = "MACB_mii_bus";
381 bp->mii_bus->read = &macb_mdio_read;
382 bp->mii_bus->write = &macb_mdio_write;
383 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
384 bp->pdev->name, bp->pdev->id);
385 bp->mii_bus->priv = bp;
386 bp->mii_bus->parent = &bp->dev->dev;
387 pdata = dev_get_platdata(&bp->pdev->dev);
389 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
390 if (!bp->mii_bus->irq) {
392 goto err_out_free_mdiobus;
395 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
397 np = bp->pdev->dev.of_node;
399 /* try dt phy registration */
400 err = of_mdiobus_register(bp->mii_bus, np);
402 /* fallback to standard phy registration if no phy were
403 found during dt phy registration */
404 if (!err && !phy_find_first(bp->mii_bus)) {
405 for (i = 0; i < PHY_MAX_ADDR; i++) {
406 struct phy_device *phydev;
408 phydev = mdiobus_scan(bp->mii_bus, i);
409 if (IS_ERR(phydev)) {
410 err = PTR_ERR(phydev);
416 goto err_out_unregister_bus;
419 for (i = 0; i < PHY_MAX_ADDR; i++)
420 bp->mii_bus->irq[i] = PHY_POLL;
423 bp->mii_bus->phy_mask = pdata->phy_mask;
425 err = mdiobus_register(bp->mii_bus);
429 goto err_out_free_mdio_irq;
431 err = macb_mii_probe(bp->dev);
433 goto err_out_unregister_bus;
437 err_out_unregister_bus:
438 mdiobus_unregister(bp->mii_bus);
439 err_out_free_mdio_irq:
440 kfree(bp->mii_bus->irq);
441 err_out_free_mdiobus:
442 mdiobus_free(bp->mii_bus);
447 static void macb_update_stats(struct macb *bp)
449 u32 __iomem *reg = bp->regs + MACB_PFR;
450 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
451 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
453 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
455 for(; p < end; p++, reg++)
456 *p += readl_relaxed(reg);
459 static int macb_halt_tx(struct macb *bp)
461 unsigned long halt_time, timeout;
464 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
466 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
469 status = macb_readl(bp, TSR);
470 if (!(status & MACB_BIT(TGO)))
473 usleep_range(10, 250);
474 } while (time_before(halt_time, timeout));
479 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
481 if (tx_skb->mapping) {
482 if (tx_skb->mapped_as_page)
483 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
484 tx_skb->size, DMA_TO_DEVICE);
486 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
487 tx_skb->size, DMA_TO_DEVICE);
492 dev_kfree_skb_any(tx_skb->skb);
497 static void macb_tx_error_task(struct work_struct *work)
499 struct macb_queue *queue = container_of(work, struct macb_queue,
501 struct macb *bp = queue->bp;
502 struct macb_tx_skb *tx_skb;
503 struct macb_dma_desc *desc;
508 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
509 (unsigned int)(queue - bp->queues),
510 queue->tx_tail, queue->tx_head);
512 /* Prevent the queue IRQ handlers from running: each of them may call
513 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
514 * As explained below, we have to halt the transmission before updating
515 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
516 * network engine about the macb/gem being halted.
518 spin_lock_irqsave(&bp->lock, flags);
520 /* Make sure nobody is trying to queue up new packets */
521 netif_tx_stop_all_queues(bp->dev);
524 * Stop transmission now
525 * (in case we have just queued new packets)
526 * macb/gem must be halted to write TBQP register
528 if (macb_halt_tx(bp))
529 /* Just complain for now, reinitializing TX path can be good */
530 netdev_err(bp->dev, "BUG: halt tx timed out\n");
533 * Treat frames in TX queue including the ones that caused the error.
534 * Free transmit buffers in upper layer.
536 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
539 desc = macb_tx_desc(queue, tail);
541 tx_skb = macb_tx_skb(queue, tail);
544 if (ctrl & MACB_BIT(TX_USED)) {
545 /* skb is set for the last buffer of the frame */
547 macb_tx_unmap(bp, tx_skb);
549 tx_skb = macb_tx_skb(queue, tail);
553 /* ctrl still refers to the first buffer descriptor
554 * since it's the only one written back by the hardware
556 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
557 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
558 macb_tx_ring_wrap(tail), skb->data);
559 bp->stats.tx_packets++;
560 bp->stats.tx_bytes += skb->len;
564 * "Buffers exhausted mid-frame" errors may only happen
565 * if the driver is buggy, so complain loudly about those.
566 * Statistics are updated by hardware.
568 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
570 "BUG: TX buffers exhausted mid-frame\n");
572 desc->ctrl = ctrl | MACB_BIT(TX_USED);
575 macb_tx_unmap(bp, tx_skb);
578 /* Set end of TX queue */
579 desc = macb_tx_desc(queue, 0);
581 desc->ctrl = MACB_BIT(TX_USED);
583 /* Make descriptor updates visible to hardware */
586 /* Reinitialize the TX desc queue */
587 queue_writel(queue, TBQP, queue->tx_ring_dma);
588 /* Make TX ring reflect state of hardware */
592 /* Housework before enabling TX IRQ */
593 macb_writel(bp, TSR, macb_readl(bp, TSR));
594 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
596 /* Now we are ready to start transmission again */
597 netif_tx_start_all_queues(bp->dev);
598 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
600 spin_unlock_irqrestore(&bp->lock, flags);
603 static void macb_tx_interrupt(struct macb_queue *queue)
608 struct macb *bp = queue->bp;
609 u16 queue_index = queue - bp->queues;
611 status = macb_readl(bp, TSR);
612 macb_writel(bp, TSR, status);
614 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
615 queue_writel(queue, ISR, MACB_BIT(TCOMP));
617 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
618 (unsigned long)status);
620 head = queue->tx_head;
621 for (tail = queue->tx_tail; tail != head; tail++) {
622 struct macb_tx_skb *tx_skb;
624 struct macb_dma_desc *desc;
627 desc = macb_tx_desc(queue, tail);
629 /* Make hw descriptor updates visible to CPU */
634 /* TX_USED bit is only set by hardware on the very first buffer
635 * descriptor of the transmitted frame.
637 if (!(ctrl & MACB_BIT(TX_USED)))
640 /* Process all buffers of the current transmitted frame */
642 tx_skb = macb_tx_skb(queue, tail);
645 /* First, update TX stats if needed */
647 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
648 macb_tx_ring_wrap(tail), skb->data);
649 bp->stats.tx_packets++;
650 bp->stats.tx_bytes += skb->len;
653 /* Now we can safely release resources */
654 macb_tx_unmap(bp, tx_skb);
656 /* skb is set only for the last buffer of the frame.
657 * WARNING: at this point skb has been freed by
665 queue->tx_tail = tail;
666 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
667 CIRC_CNT(queue->tx_head, queue->tx_tail,
668 TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH)
669 netif_wake_subqueue(bp->dev, queue_index);
672 static void gem_rx_refill(struct macb *bp)
678 while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail, RX_RING_SIZE) > 0) {
679 entry = macb_rx_ring_wrap(bp->rx_prepared_head);
681 /* Make hw descriptor updates visible to CPU */
684 bp->rx_prepared_head++;
686 if (bp->rx_skbuff[entry] == NULL) {
687 /* allocate sk_buff for this free entry in ring */
688 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
689 if (unlikely(skb == NULL)) {
691 "Unable to allocate sk_buff\n");
695 /* now fill corresponding descriptor entry */
696 paddr = dma_map_single(&bp->pdev->dev, skb->data,
697 bp->rx_buffer_size, DMA_FROM_DEVICE);
698 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
703 bp->rx_skbuff[entry] = skb;
705 if (entry == RX_RING_SIZE - 1)
706 paddr |= MACB_BIT(RX_WRAP);
707 bp->rx_ring[entry].addr = paddr;
708 bp->rx_ring[entry].ctrl = 0;
710 /* properly align Ethernet header */
711 skb_reserve(skb, NET_IP_ALIGN);
713 bp->rx_ring[entry].addr &= ~MACB_BIT(RX_USED);
714 bp->rx_ring[entry].ctrl = 0;
718 /* Make descriptor updates visible to hardware */
721 netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
722 bp->rx_prepared_head, bp->rx_tail);
725 /* Mark DMA descriptors from begin up to and not including end as unused */
726 static void discard_partial_frame(struct macb *bp, unsigned int begin,
731 for (frag = begin; frag != end; frag++) {
732 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
733 desc->addr &= ~MACB_BIT(RX_USED);
736 /* Make descriptor updates visible to hardware */
740 * When this happens, the hardware stats registers for
741 * whatever caused this is updated, so we don't have to record
746 static int gem_rx(struct macb *bp, int budget)
751 struct macb_dma_desc *desc;
754 while (count < budget) {
757 entry = macb_rx_ring_wrap(bp->rx_tail);
758 desc = &bp->rx_ring[entry];
760 /* Make hw descriptor updates visible to CPU */
766 if (!(addr & MACB_BIT(RX_USED)))
772 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
774 "not whole frame pointed by descriptor\n");
775 bp->stats.rx_dropped++;
778 skb = bp->rx_skbuff[entry];
779 if (unlikely(!skb)) {
781 "inconsistent Rx descriptor chain\n");
782 bp->stats.rx_dropped++;
785 /* now everything is ready for receiving packet */
786 bp->rx_skbuff[entry] = NULL;
787 len = ctrl & bp->rx_frm_len_mask;
789 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
792 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, addr));
793 dma_unmap_single(&bp->pdev->dev, addr,
794 bp->rx_buffer_size, DMA_FROM_DEVICE);
796 skb->protocol = eth_type_trans(skb, bp->dev);
797 skb_checksum_none_assert(skb);
798 if (bp->dev->features & NETIF_F_RXCSUM &&
799 !(bp->dev->flags & IFF_PROMISC) &&
800 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
801 skb->ip_summed = CHECKSUM_UNNECESSARY;
803 bp->stats.rx_packets++;
804 bp->stats.rx_bytes += skb->len;
806 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
807 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
808 skb->len, skb->csum);
809 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
810 skb_mac_header(skb), 16, true);
811 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
812 skb->data, 32, true);
815 netif_receive_skb(skb);
823 static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
824 unsigned int last_frag)
830 struct macb_dma_desc *desc;
832 desc = macb_rx_desc(bp, last_frag);
833 len = desc->ctrl & bp->rx_frm_len_mask;
835 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
836 macb_rx_ring_wrap(first_frag),
837 macb_rx_ring_wrap(last_frag), len);
840 * The ethernet header starts NET_IP_ALIGN bytes into the
841 * first buffer. Since the header is 14 bytes, this makes the
842 * payload word-aligned.
844 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
845 * the two padding bytes into the skb so that we avoid hitting
846 * the slowpath in memcpy(), and pull them off afterwards.
848 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
850 bp->stats.rx_dropped++;
851 for (frag = first_frag; ; frag++) {
852 desc = macb_rx_desc(bp, frag);
853 desc->addr &= ~MACB_BIT(RX_USED);
854 if (frag == last_frag)
858 /* Make descriptor updates visible to hardware */
866 skb_checksum_none_assert(skb);
869 for (frag = first_frag; ; frag++) {
870 unsigned int frag_len = bp->rx_buffer_size;
872 if (offset + frag_len > len) {
873 BUG_ON(frag != last_frag);
874 frag_len = len - offset;
876 skb_copy_to_linear_data_offset(skb, offset,
877 macb_rx_buffer(bp, frag), frag_len);
878 offset += bp->rx_buffer_size;
879 desc = macb_rx_desc(bp, frag);
880 desc->addr &= ~MACB_BIT(RX_USED);
882 if (frag == last_frag)
886 /* Make descriptor updates visible to hardware */
889 __skb_pull(skb, NET_IP_ALIGN);
890 skb->protocol = eth_type_trans(skb, bp->dev);
892 bp->stats.rx_packets++;
893 bp->stats.rx_bytes += skb->len;
894 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
895 skb->len, skb->csum);
896 netif_receive_skb(skb);
901 static int macb_rx(struct macb *bp, int budget)
907 for (tail = bp->rx_tail; budget > 0; tail++) {
908 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
911 /* Make hw descriptor updates visible to CPU */
917 if (!(addr & MACB_BIT(RX_USED)))
920 if (ctrl & MACB_BIT(RX_SOF)) {
921 if (first_frag != -1)
922 discard_partial_frame(bp, first_frag, tail);
926 if (ctrl & MACB_BIT(RX_EOF)) {
928 BUG_ON(first_frag == -1);
930 dropped = macb_rx_frame(bp, first_frag, tail);
939 if (first_frag != -1)
940 bp->rx_tail = first_frag;
947 static int macb_poll(struct napi_struct *napi, int budget)
949 struct macb *bp = container_of(napi, struct macb, napi);
953 status = macb_readl(bp, RSR);
954 macb_writel(bp, RSR, status);
958 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
959 (unsigned long)status, budget);
961 work_done = bp->macbgem_ops.mog_rx(bp, budget);
962 if (work_done < budget) {
965 /* Packets received while interrupts were disabled */
966 status = macb_readl(bp, RSR);
968 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
969 macb_writel(bp, ISR, MACB_BIT(RCOMP));
970 napi_reschedule(napi);
972 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
976 /* TODO: Handle errors */
981 static irqreturn_t macb_interrupt(int irq, void *dev_id)
983 struct macb_queue *queue = dev_id;
984 struct macb *bp = queue->bp;
985 struct net_device *dev = bp->dev;
988 status = queue_readl(queue, ISR);
990 if (unlikely(!status))
993 spin_lock(&bp->lock);
996 /* close possible race with dev_close */
997 if (unlikely(!netif_running(dev))) {
998 queue_writel(queue, IDR, -1);
1002 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1003 (unsigned int)(queue - bp->queues),
1004 (unsigned long)status);
1006 if (status & MACB_RX_INT_FLAGS) {
1008 * There's no point taking any more interrupts
1009 * until we have processed the buffers. The
1010 * scheduling call may fail if the poll routine
1011 * is already scheduled, so disable interrupts
1014 queue_writel(queue, IDR, MACB_RX_INT_FLAGS);
1015 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1016 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1018 if (napi_schedule_prep(&bp->napi)) {
1019 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1020 __napi_schedule(&bp->napi);
1024 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1025 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1026 schedule_work(&queue->tx_error_task);
1028 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1029 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1034 if (status & MACB_BIT(TCOMP))
1035 macb_tx_interrupt(queue);
1038 * Link change detection isn't possible with RMII, so we'll
1039 * add that if/when we get our hands on a full-blown MII PHY.
1042 if (status & MACB_BIT(RXUBR)) {
1043 ctrl = macb_readl(bp, NCR);
1044 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1045 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1047 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1048 macb_writel(bp, ISR, MACB_BIT(RXUBR));
1051 if (status & MACB_BIT(ISR_ROVR)) {
1052 /* We missed at least one packet */
1053 if (macb_is_gem(bp))
1054 bp->hw_stats.gem.rx_overruns++;
1056 bp->hw_stats.macb.rx_overruns++;
1058 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1059 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1062 if (status & MACB_BIT(HRESP)) {
1064 * TODO: Reset the hardware, and maybe move the
1065 * netdev_err to a lower-priority context as well
1068 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1070 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1071 queue_writel(queue, ISR, MACB_BIT(HRESP));
1074 status = queue_readl(queue, ISR);
1077 spin_unlock(&bp->lock);
1082 #ifdef CONFIG_NET_POLL_CONTROLLER
1084 * Polling receive - used by netconsole and other diagnostic tools
1085 * to allow network i/o with interrupts disabled.
1087 static void macb_poll_controller(struct net_device *dev)
1089 struct macb *bp = netdev_priv(dev);
1090 struct macb_queue *queue;
1091 unsigned long flags;
1094 local_irq_save(flags);
1095 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1096 macb_interrupt(dev->irq, queue);
1097 local_irq_restore(flags);
1101 static inline unsigned int macb_count_tx_descriptors(struct macb *bp,
1104 return (len + bp->max_tx_length - 1) / bp->max_tx_length;
1107 static unsigned int macb_tx_map(struct macb *bp,
1108 struct macb_queue *queue,
1109 struct sk_buff *skb)
1112 unsigned int len, entry, i, tx_head = queue->tx_head;
1113 struct macb_tx_skb *tx_skb = NULL;
1114 struct macb_dma_desc *desc;
1115 unsigned int offset, size, count = 0;
1116 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1117 unsigned int eof = 1;
1120 /* First, map non-paged data */
1121 len = skb_headlen(skb);
1124 size = min(len, bp->max_tx_length);
1125 entry = macb_tx_ring_wrap(tx_head);
1126 tx_skb = &queue->tx_skb[entry];
1128 mapping = dma_map_single(&bp->pdev->dev,
1130 size, DMA_TO_DEVICE);
1131 if (dma_mapping_error(&bp->pdev->dev, mapping))
1134 /* Save info to properly release resources */
1136 tx_skb->mapping = mapping;
1137 tx_skb->size = size;
1138 tx_skb->mapped_as_page = false;
1146 /* Then, map paged data from fragments */
1147 for (f = 0; f < nr_frags; f++) {
1148 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1150 len = skb_frag_size(frag);
1153 size = min(len, bp->max_tx_length);
1154 entry = macb_tx_ring_wrap(tx_head);
1155 tx_skb = &queue->tx_skb[entry];
1157 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1158 offset, size, DMA_TO_DEVICE);
1159 if (dma_mapping_error(&bp->pdev->dev, mapping))
1162 /* Save info to properly release resources */
1164 tx_skb->mapping = mapping;
1165 tx_skb->size = size;
1166 tx_skb->mapped_as_page = true;
1175 /* Should never happen */
1176 if (unlikely(tx_skb == NULL)) {
1177 netdev_err(bp->dev, "BUG! empty skb!\n");
1181 /* This is the last buffer of the frame: save socket buffer */
1184 /* Update TX ring: update buffer descriptors in reverse order
1185 * to avoid race condition
1188 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1189 * to set the end of TX queue
1192 entry = macb_tx_ring_wrap(i);
1193 ctrl = MACB_BIT(TX_USED);
1194 desc = &queue->tx_ring[entry];
1199 entry = macb_tx_ring_wrap(i);
1200 tx_skb = &queue->tx_skb[entry];
1201 desc = &queue->tx_ring[entry];
1203 ctrl = (u32)tx_skb->size;
1205 ctrl |= MACB_BIT(TX_LAST);
1208 if (unlikely(entry == (TX_RING_SIZE - 1)))
1209 ctrl |= MACB_BIT(TX_WRAP);
1211 /* Set TX buffer descriptor */
1212 desc->addr = tx_skb->mapping;
1213 /* desc->addr must be visible to hardware before clearing
1214 * 'TX_USED' bit in desc->ctrl.
1218 } while (i != queue->tx_head);
1220 queue->tx_head = tx_head;
1225 netdev_err(bp->dev, "TX DMA map failed\n");
1227 for (i = queue->tx_head; i != tx_head; i++) {
1228 tx_skb = macb_tx_skb(queue, i);
1230 macb_tx_unmap(bp, tx_skb);
1236 static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1238 u16 queue_index = skb_get_queue_mapping(skb);
1239 struct macb *bp = netdev_priv(dev);
1240 struct macb_queue *queue = &bp->queues[queue_index];
1241 unsigned long flags;
1242 unsigned int count, nr_frags, frag_size, f;
1244 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1245 netdev_vdbg(bp->dev,
1246 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
1247 queue_index, skb->len, skb->head, skb->data,
1248 skb_tail_pointer(skb), skb_end_pointer(skb));
1249 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1250 skb->data, 16, true);
1253 /* Count how many TX buffer descriptors are needed to send this
1254 * socket buffer: skb fragments of jumbo frames may need to be
1255 * splitted into many buffer descriptors.
1257 count = macb_count_tx_descriptors(bp, skb_headlen(skb));
1258 nr_frags = skb_shinfo(skb)->nr_frags;
1259 for (f = 0; f < nr_frags; f++) {
1260 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
1261 count += macb_count_tx_descriptors(bp, frag_size);
1264 spin_lock_irqsave(&bp->lock, flags);
1266 /* This is a hard error, log it. */
1267 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, TX_RING_SIZE) < count) {
1268 netif_stop_subqueue(dev, queue_index);
1269 spin_unlock_irqrestore(&bp->lock, flags);
1270 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1271 queue->tx_head, queue->tx_tail);
1272 return NETDEV_TX_BUSY;
1275 /* Map socket buffer for DMA transfer */
1276 if (!macb_tx_map(bp, queue, skb)) {
1277 dev_kfree_skb_any(skb);
1281 /* Make newly initialized descriptor visible to hardware */
1284 skb_tx_timestamp(skb);
1286 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1288 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, TX_RING_SIZE) < 1)
1289 netif_stop_subqueue(dev, queue_index);
1292 spin_unlock_irqrestore(&bp->lock, flags);
1294 return NETDEV_TX_OK;
1297 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1299 if (!macb_is_gem(bp)) {
1300 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1302 bp->rx_buffer_size = size;
1304 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
1306 "RX buffer must be multiple of %d bytes, expanding\n",
1307 RX_BUFFER_MULTIPLE);
1308 bp->rx_buffer_size =
1309 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1313 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%Zu]\n",
1314 bp->dev->mtu, bp->rx_buffer_size);
1317 static void gem_free_rx_buffers(struct macb *bp)
1319 struct sk_buff *skb;
1320 struct macb_dma_desc *desc;
1327 for (i = 0; i < RX_RING_SIZE; i++) {
1328 skb = bp->rx_skbuff[i];
1333 desc = &bp->rx_ring[i];
1334 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
1335 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
1337 dev_kfree_skb_any(skb);
1341 kfree(bp->rx_skbuff);
1342 bp->rx_skbuff = NULL;
1345 static void macb_free_rx_buffers(struct macb *bp)
1347 if (bp->rx_buffers) {
1348 dma_free_coherent(&bp->pdev->dev,
1349 RX_RING_SIZE * bp->rx_buffer_size,
1350 bp->rx_buffers, bp->rx_buffers_dma);
1351 bp->rx_buffers = NULL;
1355 static void macb_free_consistent(struct macb *bp)
1357 struct macb_queue *queue;
1360 bp->macbgem_ops.mog_free_rx_buffers(bp);
1362 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
1363 bp->rx_ring, bp->rx_ring_dma);
1367 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1368 kfree(queue->tx_skb);
1369 queue->tx_skb = NULL;
1370 if (queue->tx_ring) {
1371 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
1372 queue->tx_ring, queue->tx_ring_dma);
1373 queue->tx_ring = NULL;
1378 static int gem_alloc_rx_buffers(struct macb *bp)
1382 size = RX_RING_SIZE * sizeof(struct sk_buff *);
1383 bp->rx_skbuff = kzalloc(size, GFP_KERNEL);
1388 "Allocated %d RX struct sk_buff entries at %p\n",
1389 RX_RING_SIZE, bp->rx_skbuff);
1393 static int macb_alloc_rx_buffers(struct macb *bp)
1397 size = RX_RING_SIZE * bp->rx_buffer_size;
1398 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1399 &bp->rx_buffers_dma, GFP_KERNEL);
1400 if (!bp->rx_buffers)
1404 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1405 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
1409 static int macb_alloc_consistent(struct macb *bp)
1411 struct macb_queue *queue;
1415 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1416 size = TX_RING_BYTES;
1417 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1418 &queue->tx_ring_dma,
1420 if (!queue->tx_ring)
1423 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
1424 q, size, (unsigned long)queue->tx_ring_dma,
1427 size = TX_RING_SIZE * sizeof(struct macb_tx_skb);
1428 queue->tx_skb = kmalloc(size, GFP_KERNEL);
1433 size = RX_RING_BYTES;
1434 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1435 &bp->rx_ring_dma, GFP_KERNEL);
1439 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1440 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
1442 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
1448 macb_free_consistent(bp);
1452 static void gem_init_rings(struct macb *bp)
1454 struct macb_queue *queue;
1458 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1459 for (i = 0; i < TX_RING_SIZE; i++) {
1460 queue->tx_ring[i].addr = 0;
1461 queue->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1463 queue->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1469 bp->rx_prepared_head = 0;
1474 static void macb_init_rings(struct macb *bp)
1479 addr = bp->rx_buffers_dma;
1480 for (i = 0; i < RX_RING_SIZE; i++) {
1481 bp->rx_ring[i].addr = addr;
1482 bp->rx_ring[i].ctrl = 0;
1483 addr += bp->rx_buffer_size;
1485 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
1487 for (i = 0; i < TX_RING_SIZE; i++) {
1488 bp->queues[0].tx_ring[i].addr = 0;
1489 bp->queues[0].tx_ring[i].ctrl = MACB_BIT(TX_USED);
1491 bp->queues[0].tx_head = 0;
1492 bp->queues[0].tx_tail = 0;
1493 bp->queues[0].tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1498 static void macb_reset_hw(struct macb *bp)
1500 struct macb_queue *queue;
1504 * Disable RX and TX (XXX: Should we halt the transmission
1507 macb_writel(bp, NCR, 0);
1509 /* Clear the stats registers (XXX: Update stats first?) */
1510 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
1512 /* Clear all status flags */
1513 macb_writel(bp, TSR, -1);
1514 macb_writel(bp, RSR, -1);
1516 /* Disable all interrupts */
1517 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1518 queue_writel(queue, IDR, -1);
1519 queue_readl(queue, ISR);
1523 static u32 gem_mdc_clk_div(struct macb *bp)
1526 unsigned long pclk_hz = clk_get_rate(bp->pclk);
1528 if (pclk_hz <= 20000000)
1529 config = GEM_BF(CLK, GEM_CLK_DIV8);
1530 else if (pclk_hz <= 40000000)
1531 config = GEM_BF(CLK, GEM_CLK_DIV16);
1532 else if (pclk_hz <= 80000000)
1533 config = GEM_BF(CLK, GEM_CLK_DIV32);
1534 else if (pclk_hz <= 120000000)
1535 config = GEM_BF(CLK, GEM_CLK_DIV48);
1536 else if (pclk_hz <= 160000000)
1537 config = GEM_BF(CLK, GEM_CLK_DIV64);
1539 config = GEM_BF(CLK, GEM_CLK_DIV96);
1544 static u32 macb_mdc_clk_div(struct macb *bp)
1547 unsigned long pclk_hz;
1549 if (macb_is_gem(bp))
1550 return gem_mdc_clk_div(bp);
1552 pclk_hz = clk_get_rate(bp->pclk);
1553 if (pclk_hz <= 20000000)
1554 config = MACB_BF(CLK, MACB_CLK_DIV8);
1555 else if (pclk_hz <= 40000000)
1556 config = MACB_BF(CLK, MACB_CLK_DIV16);
1557 else if (pclk_hz <= 80000000)
1558 config = MACB_BF(CLK, MACB_CLK_DIV32);
1560 config = MACB_BF(CLK, MACB_CLK_DIV64);
1566 * Get the DMA bus width field of the network configuration register that we
1567 * should program. We find the width from decoding the design configuration
1568 * register to find the maximum supported data bus width.
1570 static u32 macb_dbw(struct macb *bp)
1572 if (!macb_is_gem(bp))
1575 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
1577 return GEM_BF(DBW, GEM_DBW128);
1579 return GEM_BF(DBW, GEM_DBW64);
1582 return GEM_BF(DBW, GEM_DBW32);
1587 * Configure the receive DMA engine
1588 * - use the correct receive buffer size
1589 * - set best burst length for DMA operations
1590 * (if not supported by FIFO, it will fallback to default)
1591 * - set both rx/tx packet buffers to full memory size
1592 * These are configurable parameters for GEM.
1594 static void macb_configure_dma(struct macb *bp)
1599 if (macb_is_gem(bp)) {
1600 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
1601 dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
1602 if (bp->dma_burst_length)
1603 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
1604 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
1605 dmacfg &= ~GEM_BIT(ENDIA_PKT);
1607 /* Find the CPU endianness by using the loopback bit of net_ctrl
1608 * register. save it first. When the CPU is in big endian we
1609 * need to program swaped mode for management descriptor access.
1611 ncr = macb_readl(bp, NCR);
1612 __raw_writel(MACB_BIT(LLB), bp->regs + MACB_NCR);
1613 tmp = __raw_readl(bp->regs + MACB_NCR);
1615 if (tmp == MACB_BIT(LLB))
1616 dmacfg &= ~GEM_BIT(ENDIA_DESC);
1618 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
1620 /* Restore net_ctrl */
1621 macb_writel(bp, NCR, ncr);
1623 if (bp->dev->features & NETIF_F_HW_CSUM)
1624 dmacfg |= GEM_BIT(TXCOEN);
1626 dmacfg &= ~GEM_BIT(TXCOEN);
1627 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
1629 gem_writel(bp, DMACFG, dmacfg);
1633 static void macb_init_hw(struct macb *bp)
1635 struct macb_queue *queue;
1641 macb_set_hwaddr(bp);
1643 config = macb_mdc_clk_div(bp);
1644 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
1645 config |= MACB_BIT(PAE); /* PAuse Enable */
1646 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
1647 if (bp->caps | MACB_CAPS_JUMBO)
1648 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
1650 config |= MACB_BIT(BIG); /* Receive oversized frames */
1651 if (bp->dev->flags & IFF_PROMISC)
1652 config |= MACB_BIT(CAF); /* Copy All Frames */
1653 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
1654 config |= GEM_BIT(RXCOEN);
1655 if (!(bp->dev->flags & IFF_BROADCAST))
1656 config |= MACB_BIT(NBC); /* No BroadCast */
1657 config |= macb_dbw(bp);
1658 macb_writel(bp, NCFGR, config);
1659 if ((bp->caps | MACB_CAPS_JUMBO) && bp->jumbo_max_len)
1660 gem_writel(bp, JML, bp->jumbo_max_len);
1661 bp->speed = SPEED_10;
1662 bp->duplex = DUPLEX_HALF;
1663 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
1664 if (bp->caps | MACB_CAPS_JUMBO)
1665 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
1667 macb_configure_dma(bp);
1669 /* Initialize TX and RX buffers */
1670 macb_writel(bp, RBQP, bp->rx_ring_dma);
1671 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1672 queue_writel(queue, TBQP, queue->tx_ring_dma);
1674 /* Enable interrupts */
1675 queue_writel(queue, IER,
1681 /* Enable TX and RX */
1682 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
1686 * The hash address register is 64 bits long and takes up two
1687 * locations in the memory map. The least significant bits are stored
1688 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1690 * The unicast hash enable and the multicast hash enable bits in the
1691 * network configuration register enable the reception of hash matched
1692 * frames. The destination address is reduced to a 6 bit index into
1693 * the 64 bit hash register using the following hash function. The
1694 * hash function is an exclusive or of every sixth bit of the
1695 * destination address.
1697 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1698 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
1699 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
1700 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1701 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1702 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1704 * da[0] represents the least significant bit of the first byte
1705 * received, that is, the multicast/unicast indicator, and da[47]
1706 * represents the most significant bit of the last byte received. If
1707 * the hash index, hi[n], points to a bit that is set in the hash
1708 * register then the frame will be matched according to whether the
1709 * frame is multicast or unicast. A multicast match will be signalled
1710 * if the multicast hash enable bit is set, da[0] is 1 and the hash
1711 * index points to a bit set in the hash register. A unicast match
1712 * will be signalled if the unicast hash enable bit is set, da[0] is 0
1713 * and the hash index points to a bit set in the hash register. To
1714 * receive all multicast frames, the hash register should be set with
1715 * all ones and the multicast hash enable bit should be set in the
1716 * network configuration register.
1719 static inline int hash_bit_value(int bitnr, __u8 *addr)
1721 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
1727 * Return the hash index value for the specified address.
1729 static int hash_get_index(__u8 *addr)
1734 for (j = 0; j < 6; j++) {
1735 for (i = 0, bitval = 0; i < 8; i++)
1736 bitval ^= hash_bit_value(i * 6 + j, addr);
1738 hash_index |= (bitval << j);
1745 * Add multicast addresses to the internal multicast-hash table.
1747 static void macb_sethashtable(struct net_device *dev)
1749 struct netdev_hw_addr *ha;
1750 unsigned long mc_filter[2];
1752 struct macb *bp = netdev_priv(dev);
1754 mc_filter[0] = mc_filter[1] = 0;
1756 netdev_for_each_mc_addr(ha, dev) {
1757 bitnr = hash_get_index(ha->addr);
1758 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1761 macb_or_gem_writel(bp, HRB, mc_filter[0]);
1762 macb_or_gem_writel(bp, HRT, mc_filter[1]);
1766 * Enable/Disable promiscuous and multicast modes.
1768 static void macb_set_rx_mode(struct net_device *dev)
1771 struct macb *bp = netdev_priv(dev);
1773 cfg = macb_readl(bp, NCFGR);
1775 if (dev->flags & IFF_PROMISC) {
1776 /* Enable promiscuous mode */
1777 cfg |= MACB_BIT(CAF);
1779 /* Disable RX checksum offload */
1780 if (macb_is_gem(bp))
1781 cfg &= ~GEM_BIT(RXCOEN);
1783 /* Disable promiscuous mode */
1784 cfg &= ~MACB_BIT(CAF);
1786 /* Enable RX checksum offload only if requested */
1787 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
1788 cfg |= GEM_BIT(RXCOEN);
1791 if (dev->flags & IFF_ALLMULTI) {
1792 /* Enable all multicast mode */
1793 macb_or_gem_writel(bp, HRB, -1);
1794 macb_or_gem_writel(bp, HRT, -1);
1795 cfg |= MACB_BIT(NCFGR_MTI);
1796 } else if (!netdev_mc_empty(dev)) {
1797 /* Enable specific multicasts */
1798 macb_sethashtable(dev);
1799 cfg |= MACB_BIT(NCFGR_MTI);
1800 } else if (dev->flags & (~IFF_ALLMULTI)) {
1801 /* Disable all multicast mode */
1802 macb_or_gem_writel(bp, HRB, 0);
1803 macb_or_gem_writel(bp, HRT, 0);
1804 cfg &= ~MACB_BIT(NCFGR_MTI);
1807 macb_writel(bp, NCFGR, cfg);
1810 static int macb_open(struct net_device *dev)
1812 struct macb *bp = netdev_priv(dev);
1813 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
1816 netdev_dbg(bp->dev, "open\n");
1818 /* carrier starts down */
1819 netif_carrier_off(dev);
1821 /* if the phy is not yet register, retry later*/
1825 /* RX buffers initialization */
1826 macb_init_rx_buffer_size(bp, bufsz);
1828 err = macb_alloc_consistent(bp);
1830 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1835 napi_enable(&bp->napi);
1837 bp->macbgem_ops.mog_init_rings(bp);
1840 /* schedule a link state check */
1841 phy_start(bp->phy_dev);
1843 netif_tx_start_all_queues(dev);
1848 static int macb_close(struct net_device *dev)
1850 struct macb *bp = netdev_priv(dev);
1851 unsigned long flags;
1853 netif_tx_stop_all_queues(dev);
1854 napi_disable(&bp->napi);
1857 phy_stop(bp->phy_dev);
1859 spin_lock_irqsave(&bp->lock, flags);
1861 netif_carrier_off(dev);
1862 spin_unlock_irqrestore(&bp->lock, flags);
1864 macb_free_consistent(bp);
1869 static int macb_change_mtu(struct net_device *dev, int new_mtu)
1871 struct macb *bp = netdev_priv(dev);
1874 if (netif_running(dev))
1877 max_mtu = ETH_DATA_LEN;
1878 if (bp->caps | MACB_CAPS_JUMBO)
1879 max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
1881 if ((new_mtu > max_mtu) || (new_mtu < GEM_MTU_MIN_SIZE))
1889 static void gem_update_stats(struct macb *bp)
1892 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
1894 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
1895 u32 offset = gem_statistics[i].offset;
1896 u64 val = readl_relaxed(bp->regs + offset);
1898 bp->ethtool_stats[i] += val;
1901 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
1902 /* Add GEM_OCTTXH, GEM_OCTRXH */
1903 val = readl_relaxed(bp->regs + offset + 4);
1904 bp->ethtool_stats[i] += ((u64)val) << 32;
1910 static struct net_device_stats *gem_get_stats(struct macb *bp)
1912 struct gem_stats *hwstat = &bp->hw_stats.gem;
1913 struct net_device_stats *nstat = &bp->stats;
1915 gem_update_stats(bp);
1917 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
1918 hwstat->rx_alignment_errors +
1919 hwstat->rx_resource_errors +
1920 hwstat->rx_overruns +
1921 hwstat->rx_oversize_frames +
1922 hwstat->rx_jabbers +
1923 hwstat->rx_undersized_frames +
1924 hwstat->rx_length_field_frame_errors);
1925 nstat->tx_errors = (hwstat->tx_late_collisions +
1926 hwstat->tx_excessive_collisions +
1927 hwstat->tx_underrun +
1928 hwstat->tx_carrier_sense_errors);
1929 nstat->multicast = hwstat->rx_multicast_frames;
1930 nstat->collisions = (hwstat->tx_single_collision_frames +
1931 hwstat->tx_multiple_collision_frames +
1932 hwstat->tx_excessive_collisions);
1933 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
1934 hwstat->rx_jabbers +
1935 hwstat->rx_undersized_frames +
1936 hwstat->rx_length_field_frame_errors);
1937 nstat->rx_over_errors = hwstat->rx_resource_errors;
1938 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
1939 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
1940 nstat->rx_fifo_errors = hwstat->rx_overruns;
1941 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
1942 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
1943 nstat->tx_fifo_errors = hwstat->tx_underrun;
1948 static void gem_get_ethtool_stats(struct net_device *dev,
1949 struct ethtool_stats *stats, u64 *data)
1953 bp = netdev_priv(dev);
1954 gem_update_stats(bp);
1955 memcpy(data, &bp->ethtool_stats, sizeof(u64) * GEM_STATS_LEN);
1958 static int gem_get_sset_count(struct net_device *dev, int sset)
1962 return GEM_STATS_LEN;
1968 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
1974 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
1975 memcpy(p, gem_statistics[i].stat_string,
1981 static struct net_device_stats *macb_get_stats(struct net_device *dev)
1983 struct macb *bp = netdev_priv(dev);
1984 struct net_device_stats *nstat = &bp->stats;
1985 struct macb_stats *hwstat = &bp->hw_stats.macb;
1987 if (macb_is_gem(bp))
1988 return gem_get_stats(bp);
1990 /* read stats from hardware */
1991 macb_update_stats(bp);
1993 /* Convert HW stats into netdevice stats */
1994 nstat->rx_errors = (hwstat->rx_fcs_errors +
1995 hwstat->rx_align_errors +
1996 hwstat->rx_resource_errors +
1997 hwstat->rx_overruns +
1998 hwstat->rx_oversize_pkts +
1999 hwstat->rx_jabbers +
2000 hwstat->rx_undersize_pkts +
2001 hwstat->rx_length_mismatch);
2002 nstat->tx_errors = (hwstat->tx_late_cols +
2003 hwstat->tx_excessive_cols +
2004 hwstat->tx_underruns +
2005 hwstat->tx_carrier_errors +
2006 hwstat->sqe_test_errors);
2007 nstat->collisions = (hwstat->tx_single_cols +
2008 hwstat->tx_multiple_cols +
2009 hwstat->tx_excessive_cols);
2010 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2011 hwstat->rx_jabbers +
2012 hwstat->rx_undersize_pkts +
2013 hwstat->rx_length_mismatch);
2014 nstat->rx_over_errors = hwstat->rx_resource_errors +
2015 hwstat->rx_overruns;
2016 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2017 nstat->rx_frame_errors = hwstat->rx_align_errors;
2018 nstat->rx_fifo_errors = hwstat->rx_overruns;
2019 /* XXX: What does "missed" mean? */
2020 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
2021 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
2022 nstat->tx_fifo_errors = hwstat->tx_underruns;
2023 /* Don't know about heartbeat or window errors... */
2028 static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2030 struct macb *bp = netdev_priv(dev);
2031 struct phy_device *phydev = bp->phy_dev;
2036 return phy_ethtool_gset(phydev, cmd);
2039 static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2041 struct macb *bp = netdev_priv(dev);
2042 struct phy_device *phydev = bp->phy_dev;
2047 return phy_ethtool_sset(phydev, cmd);
2050 static int macb_get_regs_len(struct net_device *netdev)
2052 return MACB_GREGS_NBR * sizeof(u32);
2055 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2058 struct macb *bp = netdev_priv(dev);
2059 unsigned int tail, head;
2062 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2063 | MACB_GREGS_VERSION;
2065 tail = macb_tx_ring_wrap(bp->queues[0].tx_tail);
2066 head = macb_tx_ring_wrap(bp->queues[0].tx_head);
2068 regs_buff[0] = macb_readl(bp, NCR);
2069 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
2070 regs_buff[2] = macb_readl(bp, NSR);
2071 regs_buff[3] = macb_readl(bp, TSR);
2072 regs_buff[4] = macb_readl(bp, RBQP);
2073 regs_buff[5] = macb_readl(bp, TBQP);
2074 regs_buff[6] = macb_readl(bp, RSR);
2075 regs_buff[7] = macb_readl(bp, IMR);
2077 regs_buff[8] = tail;
2078 regs_buff[9] = head;
2079 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2080 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
2082 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
2083 if (macb_is_gem(bp)) {
2084 regs_buff[13] = gem_readl(bp, DMACFG);
2088 static const struct ethtool_ops macb_ethtool_ops = {
2089 .get_settings = macb_get_settings,
2090 .set_settings = macb_set_settings,
2091 .get_regs_len = macb_get_regs_len,
2092 .get_regs = macb_get_regs,
2093 .get_link = ethtool_op_get_link,
2094 .get_ts_info = ethtool_op_get_ts_info,
2097 static const struct ethtool_ops gem_ethtool_ops = {
2098 .get_settings = macb_get_settings,
2099 .set_settings = macb_set_settings,
2100 .get_regs_len = macb_get_regs_len,
2101 .get_regs = macb_get_regs,
2102 .get_link = ethtool_op_get_link,
2103 .get_ts_info = ethtool_op_get_ts_info,
2104 .get_ethtool_stats = gem_get_ethtool_stats,
2105 .get_strings = gem_get_ethtool_strings,
2106 .get_sset_count = gem_get_sset_count,
2109 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2111 struct macb *bp = netdev_priv(dev);
2112 struct phy_device *phydev = bp->phy_dev;
2114 if (!netif_running(dev))
2120 return phy_mii_ioctl(phydev, rq, cmd);
2123 static int macb_set_features(struct net_device *netdev,
2124 netdev_features_t features)
2126 struct macb *bp = netdev_priv(netdev);
2127 netdev_features_t changed = features ^ netdev->features;
2129 /* TX checksum offload */
2130 if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) {
2133 dmacfg = gem_readl(bp, DMACFG);
2134 if (features & NETIF_F_HW_CSUM)
2135 dmacfg |= GEM_BIT(TXCOEN);
2137 dmacfg &= ~GEM_BIT(TXCOEN);
2138 gem_writel(bp, DMACFG, dmacfg);
2141 /* RX checksum offload */
2142 if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) {
2145 netcfg = gem_readl(bp, NCFGR);
2146 if (features & NETIF_F_RXCSUM &&
2147 !(netdev->flags & IFF_PROMISC))
2148 netcfg |= GEM_BIT(RXCOEN);
2150 netcfg &= ~GEM_BIT(RXCOEN);
2151 gem_writel(bp, NCFGR, netcfg);
2157 static const struct net_device_ops macb_netdev_ops = {
2158 .ndo_open = macb_open,
2159 .ndo_stop = macb_close,
2160 .ndo_start_xmit = macb_start_xmit,
2161 .ndo_set_rx_mode = macb_set_rx_mode,
2162 .ndo_get_stats = macb_get_stats,
2163 .ndo_do_ioctl = macb_ioctl,
2164 .ndo_validate_addr = eth_validate_addr,
2165 .ndo_change_mtu = macb_change_mtu,
2166 .ndo_set_mac_address = eth_mac_addr,
2167 #ifdef CONFIG_NET_POLL_CONTROLLER
2168 .ndo_poll_controller = macb_poll_controller,
2170 .ndo_set_features = macb_set_features,
2174 * Configure peripheral capabilities according to device tree
2175 * and integration options used
2177 static void macb_configure_caps(struct macb *bp, const struct macb_config *dt_conf)
2182 bp->caps = dt_conf->caps;
2184 if (macb_is_gem_hw(bp->regs)) {
2185 bp->caps |= MACB_CAPS_MACB_IS_GEM;
2187 dcfg = gem_readl(bp, DCFG1);
2188 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
2189 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
2190 dcfg = gem_readl(bp, DCFG2);
2191 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
2192 bp->caps |= MACB_CAPS_FIFO_MODE;
2195 netdev_dbg(bp->dev, "Cadence caps 0x%08x\n", bp->caps);
2198 static void macb_probe_queues(void __iomem *mem,
2199 unsigned int *queue_mask,
2200 unsigned int *num_queues)
2207 /* is it macb or gem ?
2209 * We need to read directly from the hardware here because
2210 * we are early in the probe process and don't have the
2211 * MACB_CAPS_MACB_IS_GEM flag positioned
2213 if (!macb_is_gem_hw(mem))
2216 /* bit 0 is never set but queue 0 always exists */
2217 *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff;
2221 for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q)
2222 if (*queue_mask & (1 << hw_q))
2226 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
2227 struct clk **hclk, struct clk **tx_clk)
2231 *pclk = devm_clk_get(&pdev->dev, "pclk");
2232 if (IS_ERR(*pclk)) {
2233 err = PTR_ERR(*pclk);
2234 dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err);
2238 *hclk = devm_clk_get(&pdev->dev, "hclk");
2239 if (IS_ERR(*hclk)) {
2240 err = PTR_ERR(*hclk);
2241 dev_err(&pdev->dev, "failed to get hclk (%u)\n", err);
2245 *tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
2246 if (IS_ERR(*tx_clk))
2249 err = clk_prepare_enable(*pclk);
2251 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
2255 err = clk_prepare_enable(*hclk);
2257 dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err);
2258 goto err_disable_pclk;
2261 err = clk_prepare_enable(*tx_clk);
2263 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
2264 goto err_disable_hclk;
2270 clk_disable_unprepare(*hclk);
2273 clk_disable_unprepare(*pclk);
2278 static int macb_init(struct platform_device *pdev)
2280 struct net_device *dev = platform_get_drvdata(pdev);
2281 unsigned int hw_q, q;
2282 struct macb *bp = netdev_priv(dev);
2283 struct macb_queue *queue;
2287 /* set the queue register mapping once for all: queue0 has a special
2288 * register mapping but we don't want to test the queue index then
2289 * compute the corresponding register offset at run time.
2291 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
2292 if (!(bp->queue_mask & (1 << hw_q)))
2295 queue = &bp->queues[q];
2298 queue->ISR = GEM_ISR(hw_q - 1);
2299 queue->IER = GEM_IER(hw_q - 1);
2300 queue->IDR = GEM_IDR(hw_q - 1);
2301 queue->IMR = GEM_IMR(hw_q - 1);
2302 queue->TBQP = GEM_TBQP(hw_q - 1);
2304 /* queue0 uses legacy registers */
2305 queue->ISR = MACB_ISR;
2306 queue->IER = MACB_IER;
2307 queue->IDR = MACB_IDR;
2308 queue->IMR = MACB_IMR;
2309 queue->TBQP = MACB_TBQP;
2312 /* get irq: here we use the linux queue index, not the hardware
2313 * queue index. the queue irq definitions in the device tree
2314 * must remove the optional gaps that could exist in the
2315 * hardware queue mask.
2317 queue->irq = platform_get_irq(pdev, q);
2318 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
2319 IRQF_SHARED, dev->name, queue);
2322 "Unable to request IRQ %d (error %d)\n",
2327 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
2331 dev->netdev_ops = &macb_netdev_ops;
2332 netif_napi_add(dev, &bp->napi, macb_poll, 64);
2334 /* setup appropriated routines according to adapter type */
2335 if (macb_is_gem(bp)) {
2336 bp->max_tx_length = GEM_MAX_TX_LEN;
2337 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
2338 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
2339 bp->macbgem_ops.mog_init_rings = gem_init_rings;
2340 bp->macbgem_ops.mog_rx = gem_rx;
2341 dev->ethtool_ops = &gem_ethtool_ops;
2343 bp->max_tx_length = MACB_MAX_TX_LEN;
2344 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
2345 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
2346 bp->macbgem_ops.mog_init_rings = macb_init_rings;
2347 bp->macbgem_ops.mog_rx = macb_rx;
2348 dev->ethtool_ops = &macb_ethtool_ops;
2352 dev->hw_features = NETIF_F_SG;
2353 /* Checksum offload is only available on gem with packet buffer */
2354 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
2355 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
2356 if (bp->caps & MACB_CAPS_SG_DISABLED)
2357 dev->hw_features &= ~NETIF_F_SG;
2358 dev->features = dev->hw_features;
2361 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
2362 val = GEM_BIT(RGMII);
2363 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
2364 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
2365 val = MACB_BIT(RMII);
2366 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
2367 val = MACB_BIT(MII);
2369 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
2370 val |= MACB_BIT(CLKEN);
2372 macb_or_gem_writel(bp, USRIO, val);
2374 /* Set MII management clock divider */
2375 val = macb_mdc_clk_div(bp);
2376 val |= macb_dbw(bp);
2377 macb_writel(bp, NCFGR, val);
2382 #if defined(CONFIG_OF)
2383 /* 1518 rounded up */
2384 #define AT91ETHER_MAX_RBUFF_SZ 0x600
2385 /* max number of receive buffers */
2386 #define AT91ETHER_MAX_RX_DESCR 9
2388 /* Initialize and start the Receiver and Transmit subsystems */
2389 static int at91ether_start(struct net_device *dev)
2391 struct macb *lp = netdev_priv(dev);
2396 lp->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
2397 (AT91ETHER_MAX_RX_DESCR *
2398 sizeof(struct macb_dma_desc)),
2399 &lp->rx_ring_dma, GFP_KERNEL);
2403 lp->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
2404 AT91ETHER_MAX_RX_DESCR *
2405 AT91ETHER_MAX_RBUFF_SZ,
2406 &lp->rx_buffers_dma, GFP_KERNEL);
2407 if (!lp->rx_buffers) {
2408 dma_free_coherent(&lp->pdev->dev,
2409 AT91ETHER_MAX_RX_DESCR *
2410 sizeof(struct macb_dma_desc),
2411 lp->rx_ring, lp->rx_ring_dma);
2416 addr = lp->rx_buffers_dma;
2417 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
2418 lp->rx_ring[i].addr = addr;
2419 lp->rx_ring[i].ctrl = 0;
2420 addr += AT91ETHER_MAX_RBUFF_SZ;
2423 /* Set the Wrap bit on the last descriptor */
2424 lp->rx_ring[AT91ETHER_MAX_RX_DESCR - 1].addr |= MACB_BIT(RX_WRAP);
2426 /* Reset buffer index */
2429 /* Program address of descriptor list in Rx Buffer Queue register */
2430 macb_writel(lp, RBQP, lp->rx_ring_dma);
2432 /* Enable Receive and Transmit */
2433 ctl = macb_readl(lp, NCR);
2434 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
2439 /* Open the ethernet interface */
2440 static int at91ether_open(struct net_device *dev)
2442 struct macb *lp = netdev_priv(dev);
2446 /* Clear internal statistics */
2447 ctl = macb_readl(lp, NCR);
2448 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
2450 macb_set_hwaddr(lp);
2452 ret = at91ether_start(dev);
2456 /* Enable MAC interrupts */
2457 macb_writel(lp, IER, MACB_BIT(RCOMP) |
2459 MACB_BIT(ISR_TUND) |
2462 MACB_BIT(ISR_ROVR) |
2465 /* schedule a link state check */
2466 phy_start(lp->phy_dev);
2468 netif_start_queue(dev);
2473 /* Close the interface */
2474 static int at91ether_close(struct net_device *dev)
2476 struct macb *lp = netdev_priv(dev);
2479 /* Disable Receiver and Transmitter */
2480 ctl = macb_readl(lp, NCR);
2481 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
2483 /* Disable MAC interrupts */
2484 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
2486 MACB_BIT(ISR_TUND) |
2489 MACB_BIT(ISR_ROVR) |
2492 netif_stop_queue(dev);
2494 dma_free_coherent(&lp->pdev->dev,
2495 AT91ETHER_MAX_RX_DESCR *
2496 sizeof(struct macb_dma_desc),
2497 lp->rx_ring, lp->rx_ring_dma);
2500 dma_free_coherent(&lp->pdev->dev,
2501 AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ,
2502 lp->rx_buffers, lp->rx_buffers_dma);
2503 lp->rx_buffers = NULL;
2508 /* Transmit packet */
2509 static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
2511 struct macb *lp = netdev_priv(dev);
2513 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
2514 netif_stop_queue(dev);
2516 /* Store packet information (to free when Tx completed) */
2518 lp->skb_length = skb->len;
2519 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len,
2522 /* Set address of the data in the Transmit Address register */
2523 macb_writel(lp, TAR, lp->skb_physaddr);
2524 /* Set length of the packet in the Transmit Control register */
2525 macb_writel(lp, TCR, skb->len);
2528 netdev_err(dev, "%s called, but device is busy!\n", __func__);
2529 return NETDEV_TX_BUSY;
2532 return NETDEV_TX_OK;
2535 /* Extract received frame from buffer descriptors and sent to upper layers.
2536 * (Called from interrupt context)
2538 static void at91ether_rx(struct net_device *dev)
2540 struct macb *lp = netdev_priv(dev);
2541 unsigned char *p_recv;
2542 struct sk_buff *skb;
2543 unsigned int pktlen;
2545 while (lp->rx_ring[lp->rx_tail].addr & MACB_BIT(RX_USED)) {
2546 p_recv = lp->rx_buffers + lp->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
2547 pktlen = MACB_BF(RX_FRMLEN, lp->rx_ring[lp->rx_tail].ctrl);
2548 skb = netdev_alloc_skb(dev, pktlen + 2);
2550 skb_reserve(skb, 2);
2551 memcpy(skb_put(skb, pktlen), p_recv, pktlen);
2553 skb->protocol = eth_type_trans(skb, dev);
2554 lp->stats.rx_packets++;
2555 lp->stats.rx_bytes += pktlen;
2558 lp->stats.rx_dropped++;
2561 if (lp->rx_ring[lp->rx_tail].ctrl & MACB_BIT(RX_MHASH_MATCH))
2562 lp->stats.multicast++;
2564 /* reset ownership bit */
2565 lp->rx_ring[lp->rx_tail].addr &= ~MACB_BIT(RX_USED);
2567 /* wrap after last buffer */
2568 if (lp->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
2575 /* MAC interrupt handler */
2576 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
2578 struct net_device *dev = dev_id;
2579 struct macb *lp = netdev_priv(dev);
2582 /* MAC Interrupt Status register indicates what interrupts are pending.
2583 * It is automatically cleared once read.
2585 intstatus = macb_readl(lp, ISR);
2587 /* Receive complete */
2588 if (intstatus & MACB_BIT(RCOMP))
2591 /* Transmit complete */
2592 if (intstatus & MACB_BIT(TCOMP)) {
2593 /* The TCOM bit is set even if the transmission failed */
2594 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
2595 lp->stats.tx_errors++;
2598 dev_kfree_skb_irq(lp->skb);
2600 dma_unmap_single(NULL, lp->skb_physaddr,
2601 lp->skb_length, DMA_TO_DEVICE);
2602 lp->stats.tx_packets++;
2603 lp->stats.tx_bytes += lp->skb_length;
2605 netif_wake_queue(dev);
2608 /* Work-around for EMAC Errata section 41.3.1 */
2609 if (intstatus & MACB_BIT(RXUBR)) {
2610 ctl = macb_readl(lp, NCR);
2611 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
2612 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
2615 if (intstatus & MACB_BIT(ISR_ROVR))
2616 netdev_err(dev, "ROVR error\n");
2621 #ifdef CONFIG_NET_POLL_CONTROLLER
2622 static void at91ether_poll_controller(struct net_device *dev)
2624 unsigned long flags;
2626 local_irq_save(flags);
2627 at91ether_interrupt(dev->irq, dev);
2628 local_irq_restore(flags);
2632 static const struct net_device_ops at91ether_netdev_ops = {
2633 .ndo_open = at91ether_open,
2634 .ndo_stop = at91ether_close,
2635 .ndo_start_xmit = at91ether_start_xmit,
2636 .ndo_get_stats = macb_get_stats,
2637 .ndo_set_rx_mode = macb_set_rx_mode,
2638 .ndo_set_mac_address = eth_mac_addr,
2639 .ndo_do_ioctl = macb_ioctl,
2640 .ndo_validate_addr = eth_validate_addr,
2641 .ndo_change_mtu = eth_change_mtu,
2642 #ifdef CONFIG_NET_POLL_CONTROLLER
2643 .ndo_poll_controller = at91ether_poll_controller,
2647 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
2648 struct clk **hclk, struct clk **tx_clk)
2655 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
2657 return PTR_ERR(*pclk);
2659 err = clk_prepare_enable(*pclk);
2661 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
2668 static int at91ether_init(struct platform_device *pdev)
2670 struct net_device *dev = platform_get_drvdata(pdev);
2671 struct macb *bp = netdev_priv(dev);
2675 dev->netdev_ops = &at91ether_netdev_ops;
2676 dev->ethtool_ops = &macb_ethtool_ops;
2678 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
2683 macb_writel(bp, NCR, 0);
2685 reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG);
2686 if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
2687 reg |= MACB_BIT(RM9200_RMII);
2689 macb_writel(bp, NCFGR, reg);
2694 static const struct macb_config at91sam9260_config = {
2695 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII,
2696 .clk_init = macb_clk_init,
2700 static const struct macb_config pc302gem_config = {
2701 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
2702 .dma_burst_length = 16,
2703 .clk_init = macb_clk_init,
2707 static const struct macb_config sama5d3_config = {
2708 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
2709 .dma_burst_length = 16,
2710 .clk_init = macb_clk_init,
2714 static const struct macb_config sama5d4_config = {
2716 .dma_burst_length = 4,
2717 .clk_init = macb_clk_init,
2721 static const struct macb_config emac_config = {
2722 .clk_init = at91ether_clk_init,
2723 .init = at91ether_init,
2726 static const struct macb_config zynqmp_config = {
2727 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE |
2729 .dma_burst_length = 16,
2730 .clk_init = macb_clk_init,
2732 .jumbo_max_len = 10240,
2735 static const struct of_device_id macb_dt_ids[] = {
2736 { .compatible = "cdns,at32ap7000-macb" },
2737 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
2738 { .compatible = "cdns,macb" },
2739 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
2740 { .compatible = "cdns,gem", .data = &pc302gem_config },
2741 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
2742 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
2743 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
2744 { .compatible = "cdns,emac", .data = &emac_config },
2745 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
2748 MODULE_DEVICE_TABLE(of, macb_dt_ids);
2749 #endif /* CONFIG_OF */
2751 static int macb_probe(struct platform_device *pdev)
2753 int (*clk_init)(struct platform_device *, struct clk **,
2754 struct clk **, struct clk **)
2756 int (*init)(struct platform_device *) = macb_init;
2757 struct device_node *np = pdev->dev.of_node;
2758 const struct macb_config *macb_config = NULL;
2759 struct clk *pclk, *hclk, *tx_clk;
2760 unsigned int queue_mask, num_queues;
2761 struct macb_platform_data *pdata;
2762 struct phy_device *phydev;
2763 struct net_device *dev;
2764 struct resource *regs;
2771 const struct of_device_id *match;
2773 match = of_match_node(macb_dt_ids, np);
2774 if (match && match->data) {
2775 macb_config = match->data;
2776 clk_init = macb_config->clk_init;
2777 init = macb_config->init;
2781 err = clk_init(pdev, &pclk, &hclk, &tx_clk);
2785 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2786 mem = devm_ioremap_resource(&pdev->dev, regs);
2789 goto err_disable_clocks;
2792 macb_probe_queues(mem, &queue_mask, &num_queues);
2793 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
2796 goto err_disable_clocks;
2799 dev->base_addr = regs->start;
2801 SET_NETDEV_DEV(dev, &pdev->dev);
2803 bp = netdev_priv(dev);
2807 bp->num_queues = num_queues;
2808 bp->queue_mask = queue_mask;
2810 bp->dma_burst_length = macb_config->dma_burst_length;
2813 bp->tx_clk = tx_clk;
2814 if (macb_config->jumbo_max_len) {
2815 bp->jumbo_max_len = macb_config->jumbo_max_len;
2818 spin_lock_init(&bp->lock);
2820 /* setup capabilities */
2821 macb_configure_caps(bp, macb_config);
2823 platform_set_drvdata(pdev, dev);
2825 dev->irq = platform_get_irq(pdev, 0);
2828 goto err_disable_clocks;
2831 mac = of_get_mac_address(np);
2833 memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
2835 macb_get_hwaddr(bp);
2837 err = of_get_phy_mode(np);
2839 pdata = dev_get_platdata(&pdev->dev);
2840 if (pdata && pdata->is_rmii)
2841 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
2843 bp->phy_interface = PHY_INTERFACE_MODE_MII;
2845 bp->phy_interface = err;
2848 /* IP specific init */
2851 goto err_out_free_netdev;
2853 err = register_netdev(dev);
2855 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
2856 goto err_out_unregister_netdev;
2859 err = macb_mii_init(bp);
2861 goto err_out_unregister_netdev;
2863 netif_carrier_off(dev);
2865 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
2866 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
2867 dev->base_addr, dev->irq, dev->dev_addr);
2869 phydev = bp->phy_dev;
2870 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
2871 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
2875 err_out_unregister_netdev:
2876 unregister_netdev(dev);
2878 err_out_free_netdev:
2882 clk_disable_unprepare(tx_clk);
2883 clk_disable_unprepare(hclk);
2884 clk_disable_unprepare(pclk);
2889 static int macb_remove(struct platform_device *pdev)
2891 struct net_device *dev;
2894 dev = platform_get_drvdata(pdev);
2897 bp = netdev_priv(dev);
2899 phy_disconnect(bp->phy_dev);
2900 mdiobus_unregister(bp->mii_bus);
2901 kfree(bp->mii_bus->irq);
2902 mdiobus_free(bp->mii_bus);
2903 unregister_netdev(dev);
2904 clk_disable_unprepare(bp->tx_clk);
2905 clk_disable_unprepare(bp->hclk);
2906 clk_disable_unprepare(bp->pclk);
2913 static int __maybe_unused macb_suspend(struct device *dev)
2915 struct platform_device *pdev = to_platform_device(dev);
2916 struct net_device *netdev = platform_get_drvdata(pdev);
2917 struct macb *bp = netdev_priv(netdev);
2919 netif_carrier_off(netdev);
2920 netif_device_detach(netdev);
2922 clk_disable_unprepare(bp->tx_clk);
2923 clk_disable_unprepare(bp->hclk);
2924 clk_disable_unprepare(bp->pclk);
2929 static int __maybe_unused macb_resume(struct device *dev)
2931 struct platform_device *pdev = to_platform_device(dev);
2932 struct net_device *netdev = platform_get_drvdata(pdev);
2933 struct macb *bp = netdev_priv(netdev);
2935 clk_prepare_enable(bp->pclk);
2936 clk_prepare_enable(bp->hclk);
2937 clk_prepare_enable(bp->tx_clk);
2939 netif_device_attach(netdev);
2944 static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
2946 static struct platform_driver macb_driver = {
2947 .probe = macb_probe,
2948 .remove = macb_remove,
2951 .of_match_table = of_match_ptr(macb_dt_ids),
2956 module_platform_driver(macb_driver);
2958 MODULE_LICENSE("GPL");
2959 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
2960 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2961 MODULE_ALIAS("platform:macb");