2 * Atmel MACB Ethernet Controller driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
13 #define MACB_GREGS_NBR 16
14 #define MACB_GREGS_VERSION 2
15 #define MACB_MAX_QUEUES 8
17 /* MACB register offsets */
18 #define MACB_NCR 0x0000 /* Network Control */
19 #define MACB_NCFGR 0x0004 /* Network Config */
20 #define MACB_NSR 0x0008 /* Network Status */
21 #define MACB_TAR 0x000c /* AT91RM9200 only */
22 #define MACB_TCR 0x0010 /* AT91RM9200 only */
23 #define MACB_TSR 0x0014 /* Transmit Status */
24 #define MACB_RBQP 0x0018 /* RX Q Base Address */
25 #define MACB_TBQP 0x001c /* TX Q Base Address */
26 #define MACB_RSR 0x0020 /* Receive Status */
27 #define MACB_ISR 0x0024 /* Interrupt Status */
28 #define MACB_IER 0x0028 /* Interrupt Enable */
29 #define MACB_IDR 0x002c /* Interrupt Disable */
30 #define MACB_IMR 0x0030 /* Interrupt Mask */
31 #define MACB_MAN 0x0034 /* PHY Maintenance */
32 #define MACB_PTR 0x0038
33 #define MACB_PFR 0x003c
34 #define MACB_FTO 0x0040
35 #define MACB_SCF 0x0044
36 #define MACB_MCF 0x0048
37 #define MACB_FRO 0x004c
38 #define MACB_FCSE 0x0050
39 #define MACB_ALE 0x0054
40 #define MACB_DTF 0x0058
41 #define MACB_LCOL 0x005c
42 #define MACB_EXCOL 0x0060
43 #define MACB_TUND 0x0064
44 #define MACB_CSE 0x0068
45 #define MACB_RRE 0x006c
46 #define MACB_ROVR 0x0070
47 #define MACB_RSE 0x0074
48 #define MACB_ELE 0x0078
49 #define MACB_RJA 0x007c
50 #define MACB_USF 0x0080
51 #define MACB_STE 0x0084
52 #define MACB_RLE 0x0088
53 #define MACB_TPF 0x008c
54 #define MACB_HRB 0x0090
55 #define MACB_HRT 0x0094
56 #define MACB_SA1B 0x0098
57 #define MACB_SA1T 0x009c
58 #define MACB_SA2B 0x00a0
59 #define MACB_SA2T 0x00a4
60 #define MACB_SA3B 0x00a8
61 #define MACB_SA3T 0x00ac
62 #define MACB_SA4B 0x00b0
63 #define MACB_SA4T 0x00b4
64 #define MACB_TID 0x00b8
65 #define MACB_TPQ 0x00bc
66 #define MACB_USRIO 0x00c0
67 #define MACB_WOL 0x00c4
68 #define MACB_MID 0x00fc
70 /* GEM register offsets. */
71 #define GEM_NCFGR 0x0004 /* Network Config */
72 #define GEM_USRIO 0x000c /* User IO */
73 #define GEM_DMACFG 0x0010 /* DMA Configuration */
74 #define GEM_JML 0x0048 /* Jumbo Max Length */
75 #define GEM_HRB 0x0080 /* Hash Bottom */
76 #define GEM_HRT 0x0084 /* Hash Top */
77 #define GEM_SA1B 0x0088 /* Specific1 Bottom */
78 #define GEM_SA1T 0x008C /* Specific1 Top */
79 #define GEM_SA2B 0x0090 /* Specific2 Bottom */
80 #define GEM_SA2T 0x0094 /* Specific2 Top */
81 #define GEM_SA3B 0x0098 /* Specific3 Bottom */
82 #define GEM_SA3T 0x009C /* Specific3 Top */
83 #define GEM_SA4B 0x00A0 /* Specific4 Bottom */
84 #define GEM_SA4T 0x00A4 /* Specific4 Top */
85 #define GEM_OTX 0x0100 /* Octets transmitted */
86 #define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */
87 #define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */
88 #define GEM_TXCNT 0x0108 /* Frames Transmitted counter */
89 #define GEM_TXBCCNT 0x010c /* Broadcast Frames counter */
90 #define GEM_TXMCCNT 0x0110 /* Multicast Frames counter */
91 #define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */
92 #define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */
93 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
94 #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
95 #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
96 #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
97 #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
98 #define GEM_TX1519CNT 0x0130 /* 1519+ byte Frames TX counter */
99 #define GEM_TXURUNCNT 0x0134 /* TX under run error counter */
100 #define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */
101 #define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */
102 #define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */
103 #define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */
104 #define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */
105 #define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */
106 #define GEM_ORX 0x0150 /* Octets received */
107 #define GEM_OCTRXL 0x0150 /* Octets received [31:0] */
108 #define GEM_OCTRXH 0x0154 /* Octets received [47:32] */
109 #define GEM_RXCNT 0x0158 /* Frames Received Counter */
110 #define GEM_RXBROADCNT 0x015c /* Broadcast Frames Received Counter */
111 #define GEM_RXMULTICNT 0x0160 /* Multicast Frames Received Counter */
112 #define GEM_RXPAUSECNT 0x0164 /* Pause Frames Received Counter */
113 #define GEM_RX64CNT 0x0168 /* 64 byte Frames RX Counter */
114 #define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */
115 #define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */
116 #define GEM_RX256CNT 0x0174 /* 256-511 byte Frames RX Counter */
117 #define GEM_RX512CNT 0x0178 /* 512-1023 byte Frames RX Counter */
118 #define GEM_RX1024CNT 0x017c /* 1024-1518 byte Frames RX Counter */
119 #define GEM_RX1519CNT 0x0180 /* 1519+ byte Frames RX Counter */
120 #define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */
121 #define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */
122 #define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */
123 #define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */
124 #define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */
125 #define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */
126 #define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */
127 #define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */
128 #define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */
129 #define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */
130 #define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */
131 #define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */
132 #define GEM_DCFG1 0x0280 /* Design Config 1 */
133 #define GEM_DCFG2 0x0284 /* Design Config 2 */
134 #define GEM_DCFG3 0x0288 /* Design Config 3 */
135 #define GEM_DCFG4 0x028c /* Design Config 4 */
136 #define GEM_DCFG5 0x0290 /* Design Config 5 */
137 #define GEM_DCFG6 0x0294 /* Design Config 6 */
138 #define GEM_DCFG7 0x0298 /* Design Config 7 */
140 #define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2))
141 #define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
142 #define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2))
143 #define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2))
144 #define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2))
145 #define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2))
147 /* Bitfields in NCR */
148 #define MACB_LB_OFFSET 0 /* reserved */
149 #define MACB_LB_SIZE 1
150 #define MACB_LLB_OFFSET 1 /* Loop back local */
151 #define MACB_LLB_SIZE 1
152 #define MACB_RE_OFFSET 2 /* Receive enable */
153 #define MACB_RE_SIZE 1
154 #define MACB_TE_OFFSET 3 /* Transmit enable */
155 #define MACB_TE_SIZE 1
156 #define MACB_MPE_OFFSET 4 /* Management port enable */
157 #define MACB_MPE_SIZE 1
158 #define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */
159 #define MACB_CLRSTAT_SIZE 1
160 #define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */
161 #define MACB_INCSTAT_SIZE 1
162 #define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */
163 #define MACB_WESTAT_SIZE 1
164 #define MACB_BP_OFFSET 8 /* Back pressure */
165 #define MACB_BP_SIZE 1
166 #define MACB_TSTART_OFFSET 9 /* Start transmission */
167 #define MACB_TSTART_SIZE 1
168 #define MACB_THALT_OFFSET 10 /* Transmit halt */
169 #define MACB_THALT_SIZE 1
170 #define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */
171 #define MACB_NCR_TPF_SIZE 1
172 #define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */
173 #define MACB_TZQ_SIZE 1
175 /* Bitfields in NCFGR */
176 #define MACB_SPD_OFFSET 0 /* Speed */
177 #define MACB_SPD_SIZE 1
178 #define MACB_FD_OFFSET 1 /* Full duplex */
179 #define MACB_FD_SIZE 1
180 #define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */
181 #define MACB_BIT_RATE_SIZE 1
182 #define MACB_JFRAME_OFFSET 3 /* reserved */
183 #define MACB_JFRAME_SIZE 1
184 #define MACB_CAF_OFFSET 4 /* Copy all frames */
185 #define MACB_CAF_SIZE 1
186 #define MACB_NBC_OFFSET 5 /* No broadcast */
187 #define MACB_NBC_SIZE 1
188 #define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */
189 #define MACB_NCFGR_MTI_SIZE 1
190 #define MACB_UNI_OFFSET 7 /* Unicast hash enable */
191 #define MACB_UNI_SIZE 1
192 #define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */
193 #define MACB_BIG_SIZE 1
194 #define MACB_EAE_OFFSET 9 /* External address match enable */
195 #define MACB_EAE_SIZE 1
196 #define MACB_CLK_OFFSET 10
197 #define MACB_CLK_SIZE 2
198 #define MACB_RTY_OFFSET 12 /* Retry test */
199 #define MACB_RTY_SIZE 1
200 #define MACB_PAE_OFFSET 13 /* Pause enable */
201 #define MACB_PAE_SIZE 1
202 #define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */
203 #define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
204 #define MACB_RBOF_OFFSET 14 /* Receive buffer offset */
205 #define MACB_RBOF_SIZE 2
206 #define MACB_RLCE_OFFSET 16 /* Length field error frame discard */
207 #define MACB_RLCE_SIZE 1
208 #define MACB_DRFCS_OFFSET 17 /* FCS remove */
209 #define MACB_DRFCS_SIZE 1
210 #define MACB_EFRHD_OFFSET 18
211 #define MACB_EFRHD_SIZE 1
212 #define MACB_IRXFCS_OFFSET 19
213 #define MACB_IRXFCS_SIZE 1
215 /* GEM specific NCFGR bitfields. */
216 #define GEM_GBE_OFFSET 10 /* Gigabit mode enable */
217 #define GEM_GBE_SIZE 1
218 #define GEM_CLK_OFFSET 18 /* MDC clock division */
219 #define GEM_CLK_SIZE 3
220 #define GEM_DBW_OFFSET 21 /* Data bus width */
221 #define GEM_DBW_SIZE 2
222 #define GEM_RXCOEN_OFFSET 24
223 #define GEM_RXCOEN_SIZE 1
225 /* Constants for data bus width. */
226 #define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */
227 #define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */
228 #define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */
230 /* Bitfields in DMACFG. */
231 #define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */
232 #define GEM_FBLDO_SIZE 5
233 #define GEM_ENDIA_DESC_OFFSET 6 /* endian swap mode for management descriptor access */
234 #define GEM_ENDIA_DESC_SIZE 1
235 #define GEM_ENDIA_PKT_OFFSET 7 /* endian swap mode for packet data access */
236 #define GEM_ENDIA_PKT_SIZE 1
237 #define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */
238 #define GEM_RXBMS_SIZE 2
239 #define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */
240 #define GEM_TXPBMS_SIZE 1
241 #define GEM_TXCOEN_OFFSET 11 /* TX IP/TCP/UDP checksum gen offload */
242 #define GEM_TXCOEN_SIZE 1
243 #define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */
244 #define GEM_RXBS_SIZE 8
245 #define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */
246 #define GEM_DDRP_SIZE 1
249 /* Bitfields in NSR */
250 #define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
251 #define MACB_NSR_LINK_SIZE 1
252 #define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */
253 #define MACB_MDIO_SIZE 1
254 #define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */
255 #define MACB_IDLE_SIZE 1
257 /* Bitfields in TSR */
258 #define MACB_UBR_OFFSET 0 /* Used bit read */
259 #define MACB_UBR_SIZE 1
260 #define MACB_COL_OFFSET 1 /* Collision occurred */
261 #define MACB_COL_SIZE 1
262 #define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */
263 #define MACB_TSR_RLE_SIZE 1
264 #define MACB_TGO_OFFSET 3 /* Transmit go */
265 #define MACB_TGO_SIZE 1
266 #define MACB_BEX_OFFSET 4 /* TX frame corruption due to AHB error */
267 #define MACB_BEX_SIZE 1
268 #define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
269 #define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
270 #define MACB_COMP_OFFSET 5 /* Trnasmit complete */
271 #define MACB_COMP_SIZE 1
272 #define MACB_UND_OFFSET 6 /* Trnasmit under run */
273 #define MACB_UND_SIZE 1
275 /* Bitfields in RSR */
276 #define MACB_BNA_OFFSET 0 /* Buffer not available */
277 #define MACB_BNA_SIZE 1
278 #define MACB_REC_OFFSET 1 /* Frame received */
279 #define MACB_REC_SIZE 1
280 #define MACB_OVR_OFFSET 2 /* Receive overrun */
281 #define MACB_OVR_SIZE 1
283 /* Bitfields in ISR/IER/IDR/IMR */
284 #define MACB_MFD_OFFSET 0 /* Management frame sent */
285 #define MACB_MFD_SIZE 1
286 #define MACB_RCOMP_OFFSET 1 /* Receive complete */
287 #define MACB_RCOMP_SIZE 1
288 #define MACB_RXUBR_OFFSET 2 /* RX used bit read */
289 #define MACB_RXUBR_SIZE 1
290 #define MACB_TXUBR_OFFSET 3 /* TX used bit read */
291 #define MACB_TXUBR_SIZE 1
292 #define MACB_ISR_TUND_OFFSET 4 /* Enable TX buffer under run interrupt */
293 #define MACB_ISR_TUND_SIZE 1
294 #define MACB_ISR_RLE_OFFSET 5 /* EN retry exceeded/late coll interrupt */
295 #define MACB_ISR_RLE_SIZE 1
296 #define MACB_TXERR_OFFSET 6 /* EN TX frame corrupt from error interrupt */
297 #define MACB_TXERR_SIZE 1
298 #define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */
299 #define MACB_TCOMP_SIZE 1
300 #define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */
301 #define MACB_ISR_LINK_SIZE 1
302 #define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */
303 #define MACB_ISR_ROVR_SIZE 1
304 #define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */
305 #define MACB_HRESP_SIZE 1
306 #define MACB_PFR_OFFSET 12 /* Enable pause frame w/ quantum interrupt */
307 #define MACB_PFR_SIZE 1
308 #define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */
309 #define MACB_PTZ_SIZE 1
311 /* Bitfields in MAN */
312 #define MACB_DATA_OFFSET 0 /* data */
313 #define MACB_DATA_SIZE 16
314 #define MACB_CODE_OFFSET 16 /* Must be written to 10 */
315 #define MACB_CODE_SIZE 2
316 #define MACB_REGA_OFFSET 18 /* Register address */
317 #define MACB_REGA_SIZE 5
318 #define MACB_PHYA_OFFSET 23 /* PHY address */
319 #define MACB_PHYA_SIZE 5
320 #define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */
321 #define MACB_RW_SIZE 2
322 #define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 */
323 #define MACB_SOF_SIZE 2
325 /* Bitfields in USRIO (AVR32) */
326 #define MACB_MII_OFFSET 0
327 #define MACB_MII_SIZE 1
328 #define MACB_EAM_OFFSET 1
329 #define MACB_EAM_SIZE 1
330 #define MACB_TX_PAUSE_OFFSET 2
331 #define MACB_TX_PAUSE_SIZE 1
332 #define MACB_TX_PAUSE_ZERO_OFFSET 3
333 #define MACB_TX_PAUSE_ZERO_SIZE 1
335 /* Bitfields in USRIO (AT91) */
336 #define MACB_RMII_OFFSET 0
337 #define MACB_RMII_SIZE 1
338 #define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */
339 #define GEM_RGMII_SIZE 1
340 #define MACB_CLKEN_OFFSET 1
341 #define MACB_CLKEN_SIZE 1
343 /* Bitfields in WOL */
344 #define MACB_IP_OFFSET 0
345 #define MACB_IP_SIZE 16
346 #define MACB_MAG_OFFSET 16
347 #define MACB_MAG_SIZE 1
348 #define MACB_ARP_OFFSET 17
349 #define MACB_ARP_SIZE 1
350 #define MACB_SA1_OFFSET 18
351 #define MACB_SA1_SIZE 1
352 #define MACB_WOL_MTI_OFFSET 19
353 #define MACB_WOL_MTI_SIZE 1
355 /* Bitfields in MID */
356 #define MACB_IDNUM_OFFSET 16
357 #define MACB_IDNUM_SIZE 12
358 #define MACB_REV_OFFSET 0
359 #define MACB_REV_SIZE 16
361 /* Bitfields in DCFG1. */
362 #define GEM_IRQCOR_OFFSET 23
363 #define GEM_IRQCOR_SIZE 1
364 #define GEM_DBWDEF_OFFSET 25
365 #define GEM_DBWDEF_SIZE 3
367 /* Bitfields in DCFG2. */
368 #define GEM_RX_PKT_BUFF_OFFSET 20
369 #define GEM_RX_PKT_BUFF_SIZE 1
370 #define GEM_TX_PKT_BUFF_OFFSET 21
371 #define GEM_TX_PKT_BUFF_SIZE 1
373 /* Constants for CLK */
374 #define MACB_CLK_DIV8 0
375 #define MACB_CLK_DIV16 1
376 #define MACB_CLK_DIV32 2
377 #define MACB_CLK_DIV64 3
379 /* GEM specific constants for CLK. */
380 #define GEM_CLK_DIV8 0
381 #define GEM_CLK_DIV16 1
382 #define GEM_CLK_DIV32 2
383 #define GEM_CLK_DIV48 3
384 #define GEM_CLK_DIV64 4
385 #define GEM_CLK_DIV96 5
387 /* Constants for MAN register */
388 #define MACB_MAN_SOF 1
389 #define MACB_MAN_WRITE 1
390 #define MACB_MAN_READ 2
391 #define MACB_MAN_CODE 2
393 /* Capability mask bits */
394 #define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001
395 #define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002
396 #define MACB_CAPS_USRIO_DEFAULT_IS_MII 0x00000004
397 #define MACB_CAPS_NO_GIGABIT_HALF 0x00000008
398 #define MACB_CAPS_FIFO_MODE 0x10000000
399 #define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000
400 #define MACB_CAPS_SG_DISABLED 0x40000000
401 #define MACB_CAPS_MACB_IS_GEM 0x80000000
402 #define MACB_CAPS_JUMBO 0x00000008
404 /* Bit manipulation macros */
405 #define MACB_BIT(name) \
406 (1 << MACB_##name##_OFFSET)
407 #define MACB_BF(name,value) \
408 (((value) & ((1 << MACB_##name##_SIZE) - 1)) \
409 << MACB_##name##_OFFSET)
410 #define MACB_BFEXT(name,value)\
411 (((value) >> MACB_##name##_OFFSET) \
412 & ((1 << MACB_##name##_SIZE) - 1))
413 #define MACB_BFINS(name,value,old) \
414 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
415 << MACB_##name##_OFFSET)) \
416 | MACB_BF(name,value))
418 #define GEM_BIT(name) \
419 (1 << GEM_##name##_OFFSET)
420 #define GEM_BF(name, value) \
421 (((value) & ((1 << GEM_##name##_SIZE) - 1)) \
422 << GEM_##name##_OFFSET)
423 #define GEM_BFEXT(name, value)\
424 (((value) >> GEM_##name##_OFFSET) \
425 & ((1 << GEM_##name##_SIZE) - 1))
426 #define GEM_BFINS(name, value, old) \
427 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \
428 << GEM_##name##_OFFSET)) \
429 | GEM_BF(name, value))
431 /* Register access macros */
432 #define macb_readl(port,reg) \
433 readl_relaxed((port)->regs + MACB_##reg)
434 #define macb_writel(port,reg,value) \
435 writel_relaxed((value), (port)->regs + MACB_##reg)
436 #define gem_readl(port, reg) \
437 readl_relaxed((port)->regs + GEM_##reg)
438 #define gem_writel(port, reg, value) \
439 writel_relaxed((value), (port)->regs + GEM_##reg)
440 #define queue_readl(queue, reg) \
441 readl_relaxed((queue)->bp->regs + (queue)->reg)
442 #define queue_writel(queue, reg, value) \
443 writel_relaxed((value), (queue)->bp->regs + (queue)->reg)
445 /* Conditional GEM/MACB macros. These perform the operation to the correct
446 * register dependent on whether the device is a GEM or a MACB. For registers
447 * and bitfields that are common across both devices, use macb_{read,write}l
448 * to avoid the cost of the conditional.
450 #define macb_or_gem_writel(__bp, __reg, __value) \
452 if (macb_is_gem((__bp))) \
453 gem_writel((__bp), __reg, __value); \
455 macb_writel((__bp), __reg, __value); \
458 #define macb_or_gem_readl(__bp, __reg) \
461 if (macb_is_gem((__bp))) \
462 __v = gem_readl((__bp), __reg); \
464 __v = macb_readl((__bp), __reg); \
468 /* struct macb_dma_desc - Hardware DMA descriptor
469 * @addr: DMA address of data buffer
470 * @ctrl: Control and status bits
472 struct macb_dma_desc {
477 /* DMA descriptor bitfields */
478 #define MACB_RX_USED_OFFSET 0
479 #define MACB_RX_USED_SIZE 1
480 #define MACB_RX_WRAP_OFFSET 1
481 #define MACB_RX_WRAP_SIZE 1
482 #define MACB_RX_WADDR_OFFSET 2
483 #define MACB_RX_WADDR_SIZE 30
485 #define MACB_RX_FRMLEN_OFFSET 0
486 #define MACB_RX_FRMLEN_SIZE 12
487 #define MACB_RX_OFFSET_OFFSET 12
488 #define MACB_RX_OFFSET_SIZE 2
489 #define MACB_RX_SOF_OFFSET 14
490 #define MACB_RX_SOF_SIZE 1
491 #define MACB_RX_EOF_OFFSET 15
492 #define MACB_RX_EOF_SIZE 1
493 #define MACB_RX_CFI_OFFSET 16
494 #define MACB_RX_CFI_SIZE 1
495 #define MACB_RX_VLAN_PRI_OFFSET 17
496 #define MACB_RX_VLAN_PRI_SIZE 3
497 #define MACB_RX_PRI_TAG_OFFSET 20
498 #define MACB_RX_PRI_TAG_SIZE 1
499 #define MACB_RX_VLAN_TAG_OFFSET 21
500 #define MACB_RX_VLAN_TAG_SIZE 1
501 #define MACB_RX_TYPEID_MATCH_OFFSET 22
502 #define MACB_RX_TYPEID_MATCH_SIZE 1
503 #define MACB_RX_SA4_MATCH_OFFSET 23
504 #define MACB_RX_SA4_MATCH_SIZE 1
505 #define MACB_RX_SA3_MATCH_OFFSET 24
506 #define MACB_RX_SA3_MATCH_SIZE 1
507 #define MACB_RX_SA2_MATCH_OFFSET 25
508 #define MACB_RX_SA2_MATCH_SIZE 1
509 #define MACB_RX_SA1_MATCH_OFFSET 26
510 #define MACB_RX_SA1_MATCH_SIZE 1
511 #define MACB_RX_EXT_MATCH_OFFSET 28
512 #define MACB_RX_EXT_MATCH_SIZE 1
513 #define MACB_RX_UHASH_MATCH_OFFSET 29
514 #define MACB_RX_UHASH_MATCH_SIZE 1
515 #define MACB_RX_MHASH_MATCH_OFFSET 30
516 #define MACB_RX_MHASH_MATCH_SIZE 1
517 #define MACB_RX_BROADCAST_OFFSET 31
518 #define MACB_RX_BROADCAST_SIZE 1
520 #define MACB_RX_FRMLEN_MASK 0xFFF
521 #define MACB_RX_JFRMLEN_MASK 0x3FFF
523 /* RX checksum offload disabled: bit 24 clear in NCFGR */
524 #define GEM_RX_TYPEID_MATCH_OFFSET 22
525 #define GEM_RX_TYPEID_MATCH_SIZE 2
527 /* RX checksum offload enabled: bit 24 set in NCFGR */
528 #define GEM_RX_CSUM_OFFSET 22
529 #define GEM_RX_CSUM_SIZE 2
531 #define MACB_TX_FRMLEN_OFFSET 0
532 #define MACB_TX_FRMLEN_SIZE 11
533 #define MACB_TX_LAST_OFFSET 15
534 #define MACB_TX_LAST_SIZE 1
535 #define MACB_TX_NOCRC_OFFSET 16
536 #define MACB_TX_NOCRC_SIZE 1
537 #define MACB_TX_BUF_EXHAUSTED_OFFSET 27
538 #define MACB_TX_BUF_EXHAUSTED_SIZE 1
539 #define MACB_TX_UNDERRUN_OFFSET 28
540 #define MACB_TX_UNDERRUN_SIZE 1
541 #define MACB_TX_ERROR_OFFSET 29
542 #define MACB_TX_ERROR_SIZE 1
543 #define MACB_TX_WRAP_OFFSET 30
544 #define MACB_TX_WRAP_SIZE 1
545 #define MACB_TX_USED_OFFSET 31
546 #define MACB_TX_USED_SIZE 1
548 #define GEM_TX_FRMLEN_OFFSET 0
549 #define GEM_TX_FRMLEN_SIZE 14
551 /* Buffer descriptor constants */
552 #define GEM_RX_CSUM_NONE 0
553 #define GEM_RX_CSUM_IP_ONLY 1
554 #define GEM_RX_CSUM_IP_TCP 2
555 #define GEM_RX_CSUM_IP_UDP 3
557 /* limit RX checksum offload to TCP and UDP packets */
558 #define GEM_RX_CSUM_CHECKED_MASK 2
560 /* struct macb_tx_skb - data about an skb which is being transmitted
561 * @skb: skb currently being transmitted, only set for the last buffer
563 * @mapping: DMA address of the skb's fragment buffer
564 * @size: size of the DMA mapped buffer
565 * @mapped_as_page: true when buffer was mapped with skb_frag_dma_map(),
566 * false when buffer was mapped with dma_map_single()
575 /* Hardware-collected statistics. Used when updating the network
576 * device stats by a periodic timer.
582 u32 tx_multiple_cols;
588 u32 tx_excessive_cols;
590 u32 tx_carrier_errors;
591 u32 rx_resource_errors;
593 u32 rx_symbol_errors;
594 u32 rx_oversize_pkts;
596 u32 rx_undersize_pkts;
598 u32 rx_length_mismatch;
606 u32 tx_broadcast_frames;
607 u32 tx_multicast_frames;
609 u32 tx_64_byte_frames;
610 u32 tx_65_127_byte_frames;
611 u32 tx_128_255_byte_frames;
612 u32 tx_256_511_byte_frames;
613 u32 tx_512_1023_byte_frames;
614 u32 tx_1024_1518_byte_frames;
615 u32 tx_greater_than_1518_byte_frames;
617 u32 tx_single_collision_frames;
618 u32 tx_multiple_collision_frames;
619 u32 tx_excessive_collisions;
620 u32 tx_late_collisions;
621 u32 tx_deferred_frames;
622 u32 tx_carrier_sense_errors;
626 u32 rx_broadcast_frames;
627 u32 rx_multicast_frames;
629 u32 rx_64_byte_frames;
630 u32 rx_65_127_byte_frames;
631 u32 rx_128_255_byte_frames;
632 u32 rx_256_511_byte_frames;
633 u32 rx_512_1023_byte_frames;
634 u32 rx_1024_1518_byte_frames;
635 u32 rx_greater_than_1518_byte_frames;
636 u32 rx_undersized_frames;
637 u32 rx_oversize_frames;
639 u32 rx_frame_check_sequence_errors;
640 u32 rx_length_field_frame_errors;
641 u32 rx_symbol_errors;
642 u32 rx_alignment_errors;
643 u32 rx_resource_errors;
645 u32 rx_ip_header_checksum_errors;
646 u32 rx_tcp_checksum_errors;
647 u32 rx_udp_checksum_errors;
650 /* Describes the name and offset of an individual statistic register, as
651 * returned by `ethtool -S`. Also describes which net_device_stats statistics
652 * this register should contribute to.
654 struct gem_statistic {
655 char stat_string[ETH_GSTRING_LEN];
660 /* Bitfield defs for net_device_stat statistics */
661 #define GEM_NDS_RXERR_OFFSET 0
662 #define GEM_NDS_RXLENERR_OFFSET 1
663 #define GEM_NDS_RXOVERERR_OFFSET 2
664 #define GEM_NDS_RXCRCERR_OFFSET 3
665 #define GEM_NDS_RXFRAMEERR_OFFSET 4
666 #define GEM_NDS_RXFIFOERR_OFFSET 5
667 #define GEM_NDS_TXERR_OFFSET 6
668 #define GEM_NDS_TXABORTEDERR_OFFSET 7
669 #define GEM_NDS_TXCARRIERERR_OFFSET 8
670 #define GEM_NDS_TXFIFOERR_OFFSET 9
671 #define GEM_NDS_COLLISIONS_OFFSET 10
673 #define GEM_STAT_TITLE(name, title) GEM_STAT_TITLE_BITS(name, title, 0)
674 #define GEM_STAT_TITLE_BITS(name, title, bits) { \
675 .stat_string = title, \
676 .offset = GEM_##name, \
680 /* list of gem statistic registers. The names MUST match the
681 * corresponding GEM_* definitions.
683 static const struct gem_statistic gem_statistics[] = {
684 GEM_STAT_TITLE(OCTTXL, "tx_octets"), /* OCTTXH combined with OCTTXL */
685 GEM_STAT_TITLE(TXCNT, "tx_frames"),
686 GEM_STAT_TITLE(TXBCCNT, "tx_broadcast_frames"),
687 GEM_STAT_TITLE(TXMCCNT, "tx_multicast_frames"),
688 GEM_STAT_TITLE(TXPAUSECNT, "tx_pause_frames"),
689 GEM_STAT_TITLE(TX64CNT, "tx_64_byte_frames"),
690 GEM_STAT_TITLE(TX65CNT, "tx_65_127_byte_frames"),
691 GEM_STAT_TITLE(TX128CNT, "tx_128_255_byte_frames"),
692 GEM_STAT_TITLE(TX256CNT, "tx_256_511_byte_frames"),
693 GEM_STAT_TITLE(TX512CNT, "tx_512_1023_byte_frames"),
694 GEM_STAT_TITLE(TX1024CNT, "tx_1024_1518_byte_frames"),
695 GEM_STAT_TITLE(TX1519CNT, "tx_greater_than_1518_byte_frames"),
696 GEM_STAT_TITLE_BITS(TXURUNCNT, "tx_underrun",
697 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_TXFIFOERR)),
698 GEM_STAT_TITLE_BITS(SNGLCOLLCNT, "tx_single_collision_frames",
699 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
700 GEM_STAT_TITLE_BITS(MULTICOLLCNT, "tx_multiple_collision_frames",
701 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
702 GEM_STAT_TITLE_BITS(EXCESSCOLLCNT, "tx_excessive_collisions",
704 GEM_BIT(NDS_TXABORTEDERR)|
705 GEM_BIT(NDS_COLLISIONS)),
706 GEM_STAT_TITLE_BITS(LATECOLLCNT, "tx_late_collisions",
707 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
708 GEM_STAT_TITLE(TXDEFERCNT, "tx_deferred_frames"),
709 GEM_STAT_TITLE_BITS(TXCSENSECNT, "tx_carrier_sense_errors",
710 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
711 GEM_STAT_TITLE(OCTRXL, "rx_octets"), /* OCTRXH combined with OCTRXL */
712 GEM_STAT_TITLE(RXCNT, "rx_frames"),
713 GEM_STAT_TITLE(RXBROADCNT, "rx_broadcast_frames"),
714 GEM_STAT_TITLE(RXMULTICNT, "rx_multicast_frames"),
715 GEM_STAT_TITLE(RXPAUSECNT, "rx_pause_frames"),
716 GEM_STAT_TITLE(RX64CNT, "rx_64_byte_frames"),
717 GEM_STAT_TITLE(RX65CNT, "rx_65_127_byte_frames"),
718 GEM_STAT_TITLE(RX128CNT, "rx_128_255_byte_frames"),
719 GEM_STAT_TITLE(RX256CNT, "rx_256_511_byte_frames"),
720 GEM_STAT_TITLE(RX512CNT, "rx_512_1023_byte_frames"),
721 GEM_STAT_TITLE(RX1024CNT, "rx_1024_1518_byte_frames"),
722 GEM_STAT_TITLE(RX1519CNT, "rx_greater_than_1518_byte_frames"),
723 GEM_STAT_TITLE_BITS(RXUNDRCNT, "rx_undersized_frames",
724 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
725 GEM_STAT_TITLE_BITS(RXOVRCNT, "rx_oversize_frames",
726 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
727 GEM_STAT_TITLE_BITS(RXJABCNT, "rx_jabbers",
728 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
729 GEM_STAT_TITLE_BITS(RXFCSCNT, "rx_frame_check_sequence_errors",
730 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXCRCERR)),
731 GEM_STAT_TITLE_BITS(RXLENGTHCNT, "rx_length_field_frame_errors",
733 GEM_STAT_TITLE_BITS(RXSYMBCNT, "rx_symbol_errors",
734 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFRAMEERR)),
735 GEM_STAT_TITLE_BITS(RXALIGNCNT, "rx_alignment_errors",
736 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
737 GEM_STAT_TITLE_BITS(RXRESERRCNT, "rx_resource_errors",
738 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
739 GEM_STAT_TITLE_BITS(RXORCNT, "rx_overruns",
740 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFIFOERR)),
741 GEM_STAT_TITLE_BITS(RXIPCCNT, "rx_ip_header_checksum_errors",
743 GEM_STAT_TITLE_BITS(RXTCPCCNT, "rx_tcp_checksum_errors",
745 GEM_STAT_TITLE_BITS(RXUDPCCNT, "rx_udp_checksum_errors",
749 #define GEM_STATS_LEN ARRAY_SIZE(gem_statistics)
753 struct macb_or_gem_ops {
754 int (*mog_alloc_rx_buffers)(struct macb *bp);
755 void (*mog_free_rx_buffers)(struct macb *bp);
756 void (*mog_init_rings)(struct macb *bp);
757 int (*mog_rx)(struct macb *bp, int budget);
762 unsigned int dma_burst_length;
763 int (*clk_init)(struct platform_device *pdev, struct clk **pclk,
764 struct clk **hclk, struct clk **tx_clk);
765 int (*init)(struct platform_device *pdev);
779 unsigned int tx_head, tx_tail;
780 struct macb_dma_desc *tx_ring;
781 struct macb_tx_skb *tx_skb;
782 dma_addr_t tx_ring_dma;
783 struct work_struct tx_error_task;
789 unsigned int rx_tail;
790 unsigned int rx_prepared_head;
791 struct macb_dma_desc *rx_ring;
792 struct sk_buff **rx_skbuff;
794 size_t rx_buffer_size;
796 unsigned int num_queues;
797 unsigned int queue_mask;
798 struct macb_queue queues[MACB_MAX_QUEUES];
801 struct platform_device *pdev;
805 struct net_device *dev;
806 struct napi_struct napi;
807 struct net_device_stats stats;
809 struct macb_stats macb;
810 struct gem_stats gem;
813 dma_addr_t rx_ring_dma;
814 dma_addr_t rx_buffers_dma;
816 struct macb_or_gem_ops macbgem_ops;
818 struct mii_bus *mii_bus;
819 struct phy_device *phy_dev;
825 unsigned int dma_burst_length;
827 phy_interface_t phy_interface;
829 /* AT91RM9200 transmit */
830 struct sk_buff *skb; /* holds skb until xmit interrupt completes */
831 dma_addr_t skb_physaddr; /* phys addr from pci_map_single */
832 int skb_length; /* saved skb length for pci_unmap_single */
833 unsigned int max_tx_length;
835 u64 ethtool_stats[GEM_STATS_LEN];
837 unsigned int rx_frm_len_mask;
838 unsigned int jumbo_max_len;
841 static inline bool macb_is_gem(struct macb *bp)
843 return !!(bp->caps & MACB_CAPS_MACB_IS_GEM);
846 static inline bool macb_is_gem_hw(void __iomem *addr)
848 return !!(MACB_BFEXT(IDNUM, readl_relaxed(addr + MACB_MID)) >= 0x2);
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