drivers/net/ethernet/cavium/liquidio/octeon_device.c

   1 /**********************************************************************
   2  * Author: Cavium, Inc.
   3  *
   4  * Contact: support@cavium.com
   5  *          Please include "LiquidIO" in the subject.
   6  *
   7  * Copyright (c) 2003-2016 Cavium, Inc.
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more details.
  17  ***********************************************************************/
  18 #include <linux/pci.h>
  19 #include <linux/netdevice.h>
  20 #include <linux/vmalloc.h>
  21 #include "liquidio_common.h"
  22 #include "octeon_droq.h"
  23 #include "octeon_iq.h"
  24 #include "response_manager.h"
  25 #include "octeon_device.h"
  26 #include "octeon_main.h"
  27 #include "octeon_network.h"
  28 #include "cn66xx_regs.h"
  29 #include "cn66xx_device.h"
  30 #include "cn23xx_pf_device.h"
  31 #include "cn23xx_vf_device.h"
  32
  33 /** Default configuration
  34  *  for CN66XX OCTEON Models.
  35  */
  36 static struct octeon_config default_cn66xx_conf = {
  37         .card_type                              = LIO_210SV,
  38         .card_name                              = LIO_210SV_NAME,
  39
  40         /** IQ attributes */
  41         .iq                                     = {
  42                 .max_iqs                        = CN6XXX_CFG_IO_QUEUES,
  43                 .pending_list_size              =
  44                         (CN6XXX_MAX_IQ_DESCRIPTORS * CN6XXX_CFG_IO_QUEUES),
  45                 .instr_type                     = OCTEON_64BYTE_INSTR,
  46                 .db_min                         = CN6XXX_DB_MIN,
  47                 .db_timeout                     = CN6XXX_DB_TIMEOUT,
  48         }
  49         ,
  50
  51         /** OQ attributes */
  52         .oq                                     = {
  53                 .max_oqs                        = CN6XXX_CFG_IO_QUEUES,
  54                 .info_ptr                       = OCTEON_OQ_INFOPTR_MODE,
  55                 .refill_threshold               = CN6XXX_OQ_REFIL_THRESHOLD,
  56                 .oq_intr_pkt                    = CN6XXX_OQ_INTR_PKT,
  57                 .oq_intr_time                   = CN6XXX_OQ_INTR_TIME,
  58                 .pkts_per_intr                  = CN6XXX_OQ_PKTSPER_INTR,
  59         }
  60         ,
  61
  62         .num_nic_ports                          = DEFAULT_NUM_NIC_PORTS_66XX,
  63         .num_def_rx_descs                       = CN6XXX_MAX_OQ_DESCRIPTORS,
  64         .num_def_tx_descs                       = CN6XXX_MAX_IQ_DESCRIPTORS,
  65         .def_rx_buf_size                        = CN6XXX_OQ_BUF_SIZE,
  66
  67         /* For ethernet interface 0:  Port cfg Attributes */
  68         .nic_if_cfg[0] = {
  69                 /* Max Txqs: Half for each of the two ports :max_iq/2 */
  70                 .max_txqs                       = MAX_TXQS_PER_INTF,
  71
  72                 /* Actual configured value. Range could be: 1...max_txqs */
  73                 .num_txqs                       = DEF_TXQS_PER_INTF,
  74
  75                 /* Max Rxqs: Half for each of the two ports :max_oq/2  */
  76                 .max_rxqs                       = MAX_RXQS_PER_INTF,
  77
  78                 /* Actual configured value. Range could be: 1...max_rxqs */
  79                 .num_rxqs                       = DEF_RXQS_PER_INTF,
  80
  81                 /* Num of desc for rx rings */
  82                 .num_rx_descs                   = CN6XXX_MAX_OQ_DESCRIPTORS,
  83
  84                 /* Num of desc for tx rings */
  85                 .num_tx_descs                   = CN6XXX_MAX_IQ_DESCRIPTORS,
  86
  87                 /* SKB size, We need not change buf size even for Jumbo frames.
  88                  * Octeon can send jumbo frames in 4 consecutive descriptors,
  89                  */
  90                 .rx_buf_size                    = CN6XXX_OQ_BUF_SIZE,
  91
  92                 .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
  93
  94                 .gmx_port_id                    = 0,
  95         },
  96
  97         .nic_if_cfg[1] = {
  98                 /* Max Txqs: Half for each of the two ports :max_iq/2 */
  99                 .max_txqs                       = MAX_TXQS_PER_INTF,
 100
 101                 /* Actual configured value. Range could be: 1...max_txqs */
 102                 .num_txqs                       = DEF_TXQS_PER_INTF,
 103
 104                 /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 105                 .max_rxqs                       = MAX_RXQS_PER_INTF,
 106
 107                 /* Actual configured value. Range could be: 1...max_rxqs */
 108                 .num_rxqs                       = DEF_RXQS_PER_INTF,
 109
 110                 /* Num of desc for rx rings */
 111                 .num_rx_descs                   = CN6XXX_MAX_OQ_DESCRIPTORS,
 112
 113                 /* Num of desc for tx rings */
 114                 .num_tx_descs                   = CN6XXX_MAX_IQ_DESCRIPTORS,
 115
 116                 /* SKB size, We need not change buf size even for Jumbo frames.
 117                  * Octeon can send jumbo frames in 4 consecutive descriptors,
 118                  */
 119                 .rx_buf_size                    = CN6XXX_OQ_BUF_SIZE,
 120
 121                 .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
 122
 123                 .gmx_port_id                    = 1,
 124         },
 125
 126         /** Miscellaneous attributes */
 127         .misc                                   = {
 128                 /* Host driver link query interval */
 129                 .oct_link_query_interval        = 100,
 130
 131                 /* Octeon link query interval */
 132                 .host_link_query_interval       = 500,
 133
 134                 .enable_sli_oq_bp               = 0,
 135
 136                 /* Control queue group */
 137                 .ctrlq_grp                      = 1,
 138         }
 139         ,
 140 };
 141
 142 /** Default configuration
 143  *  for CN68XX OCTEON Model.
 144  */
 145
 146 static struct octeon_config default_cn68xx_conf = {
 147         .card_type                              = LIO_410NV,
 148         .card_name                              = LIO_410NV_NAME,
 149
 150         /** IQ attributes */
 151         .iq                                     = {
 152                 .max_iqs                        = CN6XXX_CFG_IO_QUEUES,
 153                 .pending_list_size              =
 154                         (CN6XXX_MAX_IQ_DESCRIPTORS * CN6XXX_CFG_IO_QUEUES),
 155                 .instr_type                     = OCTEON_64BYTE_INSTR,
 156                 .db_min                         = CN6XXX_DB_MIN,
 157                 .db_timeout                     = CN6XXX_DB_TIMEOUT,
 158         }
 159         ,
 160
 161         /** OQ attributes */
 162         .oq                                     = {
 163                 .max_oqs                        = CN6XXX_CFG_IO_QUEUES,
 164                 .info_ptr                       = OCTEON_OQ_INFOPTR_MODE,
 165                 .refill_threshold               = CN6XXX_OQ_REFIL_THRESHOLD,
 166                 .oq_intr_pkt                    = CN6XXX_OQ_INTR_PKT,
 167                 .oq_intr_time                   = CN6XXX_OQ_INTR_TIME,
 168                 .pkts_per_intr                  = CN6XXX_OQ_PKTSPER_INTR,
 169         }
 170         ,
 171
 172         .num_nic_ports                          = DEFAULT_NUM_NIC_PORTS_68XX,
 173         .num_def_rx_descs                       = CN6XXX_MAX_OQ_DESCRIPTORS,
 174         .num_def_tx_descs                       = CN6XXX_MAX_IQ_DESCRIPTORS,
 175         .def_rx_buf_size                        = CN6XXX_OQ_BUF_SIZE,
 176
 177         .nic_if_cfg[0] = {
 178                 /* Max Txqs: Half for each of the two ports :max_iq/2 */
 179                 .max_txqs                       = MAX_TXQS_PER_INTF,
 180
 181                 /* Actual configured value. Range could be: 1...max_txqs */
 182                 .num_txqs                       = DEF_TXQS_PER_INTF,
 183
 184                 /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 185                 .max_rxqs                       = MAX_RXQS_PER_INTF,
 186
 187                 /* Actual configured value. Range could be: 1...max_rxqs */
 188                 .num_rxqs                       = DEF_RXQS_PER_INTF,
 189
 190                 /* Num of desc for rx rings */
 191                 .num_rx_descs                   = CN6XXX_MAX_OQ_DESCRIPTORS,
 192
 193                 /* Num of desc for tx rings */
 194                 .num_tx_descs                   = CN6XXX_MAX_IQ_DESCRIPTORS,
 195
 196                 /* SKB size, We need not change buf size even for Jumbo frames.
 197                  * Octeon can send jumbo frames in 4 consecutive descriptors,
 198                  */
 199                 .rx_buf_size                    = CN6XXX_OQ_BUF_SIZE,
 200
 201                 .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
 202
 203                 .gmx_port_id                    = 0,
 204         },
 205
 206         .nic_if_cfg[1] = {
 207                 /* Max Txqs: Half for each of the two ports :max_iq/2 */
 208                 .max_txqs                       = MAX_TXQS_PER_INTF,
 209
 210                 /* Actual configured value. Range could be: 1...max_txqs */
 211                 .num_txqs                       = DEF_TXQS_PER_INTF,
 212
 213                 /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 214                 .max_rxqs                       = MAX_RXQS_PER_INTF,
 215
 216                 /* Actual configured value. Range could be: 1...max_rxqs */
 217                 .num_rxqs                       = DEF_RXQS_PER_INTF,
 218
 219                 /* Num of desc for rx rings */
 220                 .num_rx_descs                   = CN6XXX_MAX_OQ_DESCRIPTORS,
 221
 222                 /* Num of desc for tx rings */
 223                 .num_tx_descs                   = CN6XXX_MAX_IQ_DESCRIPTORS,
 224
 225                 /* SKB size, We need not change buf size even for Jumbo frames.
 226                  * Octeon can send jumbo frames in 4 consecutive descriptors,
 227                  */
 228                 .rx_buf_size                    = CN6XXX_OQ_BUF_SIZE,
 229
 230                 .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
 231
 232                 .gmx_port_id                    = 1,
 233         },
 234
 235         .nic_if_cfg[2] = {
 236                 /* Max Txqs: Half for each of the two ports :max_iq/2 */
 237                 .max_txqs                       = MAX_TXQS_PER_INTF,
 238
 239                 /* Actual configured value. Range could be: 1...max_txqs */
 240                 .num_txqs                       = DEF_TXQS_PER_INTF,
 241
 242                 /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 243                 .max_rxqs                       = MAX_RXQS_PER_INTF,
 244
 245                 /* Actual configured value. Range could be: 1...max_rxqs */
 246                 .num_rxqs                       = DEF_RXQS_PER_INTF,
 247
 248                 /* Num of desc for rx rings */
 249                 .num_rx_descs                   = CN6XXX_MAX_OQ_DESCRIPTORS,
 250
 251                 /* Num of desc for tx rings */
 252                 .num_tx_descs                   = CN6XXX_MAX_IQ_DESCRIPTORS,
 253
 254                 /* SKB size, We need not change buf size even for Jumbo frames.
 255                  * Octeon can send jumbo frames in 4 consecutive descriptors,
 256                  */
 257                 .rx_buf_size                    = CN6XXX_OQ_BUF_SIZE,
 258
 259                 .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
 260
 261                 .gmx_port_id                    = 2,
 262         },
 263
 264         .nic_if_cfg[3] = {
 265                 /* Max Txqs: Half for each of the two ports :max_iq/2 */
 266                 .max_txqs                       = MAX_TXQS_PER_INTF,
 267
 268                 /* Actual configured value. Range could be: 1...max_txqs */
 269                 .num_txqs                       = DEF_TXQS_PER_INTF,
 270
 271                 /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 272                 .max_rxqs                       = MAX_RXQS_PER_INTF,
 273
 274                 /* Actual configured value. Range could be: 1...max_rxqs */
 275                 .num_rxqs                       = DEF_RXQS_PER_INTF,
 276
 277                 /* Num of desc for rx rings */
 278                 .num_rx_descs                   = CN6XXX_MAX_OQ_DESCRIPTORS,
 279
 280                 /* Num of desc for tx rings */
 281                 .num_tx_descs                   = CN6XXX_MAX_IQ_DESCRIPTORS,
 282
 283                 /* SKB size, We need not change buf size even for Jumbo frames.
 284                  * Octeon can send jumbo frames in 4 consecutive descriptors,
 285                  */
 286                 .rx_buf_size                    = CN6XXX_OQ_BUF_SIZE,
 287
 288                 .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
 289
 290                 .gmx_port_id                    = 3,
 291         },
 292
 293         /** Miscellaneous attributes */
 294         .misc                                   = {
 295                 /* Host driver link query interval */
 296                 .oct_link_query_interval        = 100,
 297
 298                 /* Octeon link query interval */
 299                 .host_link_query_interval       = 500,
 300
 301                 .enable_sli_oq_bp               = 0,
 302
 303                 /* Control queue group */
 304                 .ctrlq_grp                      = 1,
 305         }
 306         ,
 307 };
 308
 309 /** Default configuration
 310  *  for CN68XX OCTEON Model.
 311  */
 312 static struct octeon_config default_cn68xx_210nv_conf = {
 313         .card_type                              = LIO_210NV,
 314         .card_name                              = LIO_210NV_NAME,
 315
 316         /** IQ attributes */
 317
 318         .iq                                     = {
 319                 .max_iqs                        = CN6XXX_CFG_IO_QUEUES,
 320                 .pending_list_size              =
 321                         (CN6XXX_MAX_IQ_DESCRIPTORS * CN6XXX_CFG_IO_QUEUES),
 322                 .instr_type                     = OCTEON_64BYTE_INSTR,
 323                 .db_min                         = CN6XXX_DB_MIN,
 324                 .db_timeout                     = CN6XXX_DB_TIMEOUT,
 325         }
 326         ,
 327
 328         /** OQ attributes */
 329         .oq                                     = {
 330                 .max_oqs                        = CN6XXX_CFG_IO_QUEUES,
 331                 .info_ptr                       = OCTEON_OQ_INFOPTR_MODE,
 332                 .refill_threshold               = CN6XXX_OQ_REFIL_THRESHOLD,
 333                 .oq_intr_pkt                    = CN6XXX_OQ_INTR_PKT,
 334                 .oq_intr_time                   = CN6XXX_OQ_INTR_TIME,
 335                 .pkts_per_intr                  = CN6XXX_OQ_PKTSPER_INTR,
 336         }
 337         ,
 338
 339         .num_nic_ports                  = DEFAULT_NUM_NIC_PORTS_68XX_210NV,
 340         .num_def_rx_descs               = CN6XXX_MAX_OQ_DESCRIPTORS,
 341         .num_def_tx_descs               = CN6XXX_MAX_IQ_DESCRIPTORS,
 342         .def_rx_buf_size                = CN6XXX_OQ_BUF_SIZE,
 343
 344         .nic_if_cfg[0] = {
 345                 /* Max Txqs: Half for each of the two ports :max_iq/2 */
 346                 .max_txqs                       = MAX_TXQS_PER_INTF,
 347
 348                 /* Actual configured value. Range could be: 1...max_txqs */
 349                 .num_txqs                       = DEF_TXQS_PER_INTF,
 350
 351                 /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 352                 .max_rxqs                       = MAX_RXQS_PER_INTF,
 353
 354                 /* Actual configured value. Range could be: 1...max_rxqs */
 355                 .num_rxqs                       = DEF_RXQS_PER_INTF,
 356
 357                 /* Num of desc for rx rings */
 358                 .num_rx_descs                   = CN6XXX_MAX_OQ_DESCRIPTORS,
 359
 360                 /* Num of desc for tx rings */
 361                 .num_tx_descs                   = CN6XXX_MAX_IQ_DESCRIPTORS,
 362
 363                 /* SKB size, We need not change buf size even for Jumbo frames.
 364                  * Octeon can send jumbo frames in 4 consecutive descriptors,
 365                  */
 366                 .rx_buf_size                    = CN6XXX_OQ_BUF_SIZE,
 367
 368                 .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
 369
 370                 .gmx_port_id                    = 0,
 371         },
 372
 373         .nic_if_cfg[1] = {
 374                 /* Max Txqs: Half for each of the two ports :max_iq/2 */
 375                 .max_txqs                       = MAX_TXQS_PER_INTF,
 376
 377                 /* Actual configured value. Range could be: 1...max_txqs */
 378                 .num_txqs                       = DEF_TXQS_PER_INTF,
 379
 380                 /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 381                 .max_rxqs                       = MAX_RXQS_PER_INTF,
 382
 383                 /* Actual configured value. Range could be: 1...max_rxqs */
 384                 .num_rxqs                       = DEF_RXQS_PER_INTF,
 385
 386                 /* Num of desc for rx rings */
 387                 .num_rx_descs                   = CN6XXX_MAX_OQ_DESCRIPTORS,
 388
 389                 /* Num of desc for tx rings */
 390                 .num_tx_descs                   = CN6XXX_MAX_IQ_DESCRIPTORS,
 391
 392                 /* SKB size, We need not change buf size even for Jumbo frames.
 393                  * Octeon can send jumbo frames in 4 consecutive descriptors,
 394                  */
 395                 .rx_buf_size                    = CN6XXX_OQ_BUF_SIZE,
 396
 397                 .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
 398
 399                 .gmx_port_id                    = 1,
 400         },
 401
 402         /** Miscellaneous attributes */
 403         .misc                                   = {
 404                 /* Host driver link query interval */
 405                 .oct_link_query_interval        = 100,
 406
 407                 /* Octeon link query interval */
 408                 .host_link_query_interval       = 500,
 409
 410                 .enable_sli_oq_bp               = 0,
 411
 412                 /* Control queue group */
 413                 .ctrlq_grp                      = 1,
 414         }
 415         ,
 416 };
 417
 418 static struct octeon_config default_cn23xx_conf = {
 419         .card_type                              = LIO_23XX,
 420         .card_name                              = LIO_23XX_NAME,
 421         /** IQ attributes */
 422         .iq = {
 423                 .max_iqs                = CN23XX_CFG_IO_QUEUES,
 424                 .pending_list_size      = (CN23XX_MAX_IQ_DESCRIPTORS *
 425                                            CN23XX_CFG_IO_QUEUES),
 426                 .instr_type             = OCTEON_64BYTE_INSTR,
 427                 .db_min                 = CN23XX_DB_MIN,
 428                 .db_timeout             = CN23XX_DB_TIMEOUT,
 429                 .iq_intr_pkt            = CN23XX_DEF_IQ_INTR_THRESHOLD,
 430         },
 431
 432         /** OQ attributes */
 433         .oq = {
 434                 .max_oqs                = CN23XX_CFG_IO_QUEUES,
 435                 .info_ptr               = OCTEON_OQ_INFOPTR_MODE,
 436                 .pkts_per_intr  = CN23XX_OQ_PKTSPER_INTR,
 437                 .refill_threshold       = CN23XX_OQ_REFIL_THRESHOLD,
 438                 .oq_intr_pkt    = CN23XX_OQ_INTR_PKT,
 439                 .oq_intr_time   = CN23XX_OQ_INTR_TIME,
 440         },
 441
 442         .num_nic_ports                          = DEFAULT_NUM_NIC_PORTS_23XX,
 443         .num_def_rx_descs                       = CN23XX_MAX_OQ_DESCRIPTORS,
 444         .num_def_tx_descs                       = CN23XX_MAX_IQ_DESCRIPTORS,
 445         .def_rx_buf_size                        = CN23XX_OQ_BUF_SIZE,
 446
 447         /* For ethernet interface 0:  Port cfg Attributes */
 448         .nic_if_cfg[0] = {
 449                 /* Max Txqs: Half for each of the two ports :max_iq/2 */
 450                 .max_txqs                       = MAX_TXQS_PER_INTF,
 451
 452                 /* Actual configured value. Range could be: 1...max_txqs */
 453                 .num_txqs                       = DEF_TXQS_PER_INTF,
 454
 455                 /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 456                 .max_rxqs                       = MAX_RXQS_PER_INTF,
 457
 458                 /* Actual configured value. Range could be: 1...max_rxqs */
 459                 .num_rxqs                       = DEF_RXQS_PER_INTF,
 460
 461                 /* Num of desc for rx rings */
 462                 .num_rx_descs                   = CN23XX_MAX_OQ_DESCRIPTORS,
 463
 464                 /* Num of desc for tx rings */
 465                 .num_tx_descs                   = CN23XX_MAX_IQ_DESCRIPTORS,
 466
 467                 /* SKB size, We need not change buf size even for Jumbo frames.
 468                  * Octeon can send jumbo frames in 4 consecutive descriptors,
 469                  */
 470                 .rx_buf_size                    = CN23XX_OQ_BUF_SIZE,
 471
 472                 .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
 473
 474                 .gmx_port_id                    = 0,
 475         },
 476
 477         .nic_if_cfg[1] = {
 478                 /* Max Txqs: Half for each of the two ports :max_iq/2 */
 479                 .max_txqs                       = MAX_TXQS_PER_INTF,
 480
 481                 /* Actual configured value. Range could be: 1...max_txqs */
 482                 .num_txqs                       = DEF_TXQS_PER_INTF,
 483
 484                 /* Max Rxqs: Half for each of the two ports :max_oq/2  */
 485                 .max_rxqs                       = MAX_RXQS_PER_INTF,
 486
 487                 /* Actual configured value. Range could be: 1...max_rxqs */
 488                 .num_rxqs                       = DEF_RXQS_PER_INTF,
 489
 490                 /* Num of desc for rx rings */
 491                 .num_rx_descs                   = CN23XX_MAX_OQ_DESCRIPTORS,
 492
 493                 /* Num of desc for tx rings */
 494                 .num_tx_descs                   = CN23XX_MAX_IQ_DESCRIPTORS,
 495
 496                 /* SKB size, We need not change buf size even for Jumbo frames.
 497                  * Octeon can send jumbo frames in 4 consecutive descriptors,
 498                  */
 499                 .rx_buf_size                    = CN23XX_OQ_BUF_SIZE,
 500
 501                 .base_queue                     = BASE_QUEUE_NOT_REQUESTED,
 502
 503                 .gmx_port_id                    = 1,
 504         },
 505
 506         .misc                                   = {
 507                 /* Host driver link query interval */
 508                 .oct_link_query_interval        = 100,
 509
 510                 /* Octeon link query interval */
 511                 .host_link_query_interval       = 500,
 512
 513                 .enable_sli_oq_bp               = 0,
 514
 515                 /* Control queue group */
 516                 .ctrlq_grp                      = 1,
 517         }
 518 };
 519
 520 static struct octeon_config_ptr {
 521         u32 conf_type;
 522 } oct_conf_info[MAX_OCTEON_DEVICES] = {
 523         {
 524                 OCTEON_CONFIG_TYPE_DEFAULT,
 525         }, {
 526                 OCTEON_CONFIG_TYPE_DEFAULT,
 527         }, {
 528                 OCTEON_CONFIG_TYPE_DEFAULT,
 529         }, {
 530                 OCTEON_CONFIG_TYPE_DEFAULT,
 531         },
 532 };
 533
 534 static char oct_dev_state_str[OCT_DEV_STATES + 1][32] = {
 535         "BEGIN", "PCI-MAP-DONE", "DISPATCH-INIT-DONE",
 536         "IQ-INIT-DONE", "SCBUFF-POOL-INIT-DONE", "RESPLIST-INIT-DONE",
 537         "DROQ-INIT-DONE", "IO-QUEUES-INIT-DONE", "CONSOLE-INIT-DONE",
 538         "HOST-READY", "CORE-READY", "RUNNING", "IN-RESET",
 539         "INVALID"
 540 };
 541
 542 static char oct_dev_app_str[CVM_DRV_APP_COUNT + 1][32] = {
 543         "BASE", "NIC", "UNKNOWN"};
 544
 545 static struct octeon_device *octeon_device[MAX_OCTEON_DEVICES];
 546 static u32 octeon_device_count;
 547
 548 static struct octeon_core_setup core_setup[MAX_OCTEON_DEVICES];
 549
 550 static void oct_set_config_info(int oct_id, int conf_type)
 551 {
 552         if (conf_type < 0 || conf_type > (NUM_OCTEON_CONFS - 1))
 553                 conf_type = OCTEON_CONFIG_TYPE_DEFAULT;
 554         oct_conf_info[oct_id].conf_type = conf_type;
 555 }
 556
 557 void octeon_init_device_list(int conf_type)
 558 {
 559         int i;
 560
 561         memset(octeon_device, 0, (sizeof(void *) * MAX_OCTEON_DEVICES));
 562         for (i = 0; i <  MAX_OCTEON_DEVICES; i++)
 563                 oct_set_config_info(i, conf_type);
 564 }
 565
 566 static void *__retrieve_octeon_config_info(struct octeon_device *oct,
 567                                            u16 card_type)
 568 {
 569         u32 oct_id = oct->octeon_id;
 570         void *ret = NULL;
 571
 572         switch (oct_conf_info[oct_id].conf_type) {
 573         case OCTEON_CONFIG_TYPE_DEFAULT:
 574                 if (oct->chip_id == OCTEON_CN66XX) {
 575                         ret = (void *)&default_cn66xx_conf;
 576                 } else if ((oct->chip_id == OCTEON_CN68XX) &&
 577                            (card_type == LIO_210NV)) {
 578                         ret =  (void *)&default_cn68xx_210nv_conf;
 579                 } else if ((oct->chip_id == OCTEON_CN68XX) &&
 580                            (card_type == LIO_410NV)) {
 581                         ret =  (void *)&default_cn68xx_conf;
 582                 } else if (oct->chip_id == OCTEON_CN23XX_PF_VID) {
 583                         ret =  (void *)&default_cn23xx_conf;
 584                 }
 585                 break;
 586         default:
 587                 break;
 588         }
 589         return ret;
 590 }
 591
 592 static int __verify_octeon_config_info(struct octeon_device *oct, void *conf)
 593 {
 594         switch (oct->chip_id) {
 595         case OCTEON_CN66XX:
 596         case OCTEON_CN68XX:
 597                 return lio_validate_cn6xxx_config_info(oct, conf);
 598         case OCTEON_CN23XX_PF_VID:
 599                 return 0;
 600         default:
 601                 break;
 602         }
 603
 604         return 1;
 605 }
 606
 607 void *oct_get_config_info(struct octeon_device *oct, u16 card_type)
 608 {
 609         void *conf = NULL;
 610
 611         conf = __retrieve_octeon_config_info(oct, card_type);
 612         if (!conf)
 613                 return NULL;
 614
 615         if (__verify_octeon_config_info(oct, conf)) {
 616                 dev_err(&oct->pci_dev->dev, "Configuration verification failed\n");
 617                 return NULL;
 618         }
 619
 620         return conf;
 621 }
 622
 623 char *lio_get_state_string(atomic_t *state_ptr)
 624 {
 625         s32 istate = (s32)atomic_read(state_ptr);
 626
 627         if (istate > OCT_DEV_STATES || istate < 0)
 628                 return oct_dev_state_str[OCT_DEV_STATE_INVALID];
 629         return oct_dev_state_str[istate];
 630 }
 631
 632 static char *get_oct_app_string(u32 app_mode)
 633 {
 634         if (app_mode <= CVM_DRV_APP_END)
 635                 return oct_dev_app_str[app_mode - CVM_DRV_APP_START];
 636         return oct_dev_app_str[CVM_DRV_INVALID_APP - CVM_DRV_APP_START];
 637 }
 638
 639 void octeon_free_device_mem(struct octeon_device *oct)
 640 {
 641         int i;
 642
 643         for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) {
 644                 if (oct->io_qmask.oq & BIT_ULL(i))
 645                         vfree(oct->droq[i]);
 646         }
 647
 648         for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) {
 649                 if (oct->io_qmask.iq & BIT_ULL(i))
 650                         vfree(oct->instr_queue[i]);
 651         }
 652
 653         i = oct->octeon_id;
 654         vfree(oct);
 655
 656         octeon_device[i] = NULL;
 657         octeon_device_count--;
 658 }
 659
 660 static struct octeon_device *octeon_allocate_device_mem(u32 pci_id,
 661                                                         u32 priv_size)
 662 {
 663         struct octeon_device *oct;
 664         u8 *buf = NULL;
 665         u32 octdevsize = 0, configsize = 0, size;
 666
 667         switch (pci_id) {
 668         case OCTEON_CN68XX:
 669         case OCTEON_CN66XX:
 670                 configsize = sizeof(struct octeon_cn6xxx);
 671                 break;
 672
 673         case OCTEON_CN23XX_PF_VID:
 674                 configsize = sizeof(struct octeon_cn23xx_pf);
 675                 break;
 676         case OCTEON_CN23XX_VF_VID:
 677                 configsize = sizeof(struct octeon_cn23xx_vf);
 678                 break;
 679         default:
 680                 pr_err("%s: Unknown PCI Device: 0x%x\n",
 681                        __func__,
 682                        pci_id);
 683                 return NULL;
 684         }
 685
 686         if (configsize & 0x7)
 687                 configsize += (8 - (configsize & 0x7));
 688
 689         octdevsize = sizeof(struct octeon_device);
 690         if (octdevsize & 0x7)
 691                 octdevsize += (8 - (octdevsize & 0x7));
 692
 693         if (priv_size & 0x7)
 694                 priv_size += (8 - (priv_size & 0x7));
 695
 696         size = octdevsize + priv_size + configsize +
 697                 (sizeof(struct octeon_dispatch) * DISPATCH_LIST_SIZE);
 698
 699         buf = vmalloc(size);
 700         if (!buf)
 701                 return NULL;
 702
 703         memset(buf, 0, size);
 704
 705         oct = (struct octeon_device *)buf;
 706         oct->priv = (void *)(buf + octdevsize);
 707         oct->chip = (void *)(buf + octdevsize + priv_size);
 708         oct->dispatch.dlist = (struct octeon_dispatch *)
 709                 (buf + octdevsize + priv_size + configsize);
 710
 711         return oct;
 712 }
 713
 714 struct octeon_device *octeon_allocate_device(u32 pci_id,
 715                                              u32 priv_size)
 716 {
 717         u32 oct_idx = 0;
 718         struct octeon_device *oct = NULL;
 719
 720         for (oct_idx = 0; oct_idx < MAX_OCTEON_DEVICES; oct_idx++)
 721                 if (!octeon_device[oct_idx])
 722                         break;
 723
 724         if (oct_idx == MAX_OCTEON_DEVICES)
 725                 return NULL;
 726
 727         oct = octeon_allocate_device_mem(pci_id, priv_size);
 728         if (!oct)
 729                 return NULL;
 730
 731         spin_lock_init(&oct->pci_win_lock);
 732         spin_lock_init(&oct->mem_access_lock);
 733
 734         octeon_device_count++;
 735         octeon_device[oct_idx] = oct;
 736
 737         oct->octeon_id = oct_idx;
 738         snprintf(oct->device_name, sizeof(oct->device_name),
 739                  "LiquidIO%d", (oct->octeon_id));
 740
 741         return oct;
 742 }
 743
 744 int
 745 octeon_allocate_ioq_vector(struct octeon_device  *oct)
 746 {
 747         int i, num_ioqs = 0;
 748         struct octeon_ioq_vector *ioq_vector;
 749         int cpu_num;
 750         int size;
 751
 752         if (OCTEON_CN23XX_PF(oct))
 753                 num_ioqs = oct->sriov_info.num_pf_rings;
 754         size = sizeof(struct octeon_ioq_vector) * num_ioqs;
 755
 756         oct->ioq_vector = vmalloc(size);
 757         if (!oct->ioq_vector)
 758                 return 1;
 759         memset(oct->ioq_vector, 0, size);
 760         for (i = 0; i < num_ioqs; i++) {
 761                 ioq_vector              = &oct->ioq_vector[i];
 762                 ioq_vector->oct_dev     = oct;
 763                 ioq_vector->iq_index    = i;
 764                 ioq_vector->droq_index  = i;
 765                 ioq_vector->mbox        = oct->mbox[i];
 766
 767                 cpu_num = i % num_online_cpus();
 768                 cpumask_set_cpu(cpu_num, &ioq_vector->affinity_mask);
 769
 770                 if (oct->chip_id == OCTEON_CN23XX_PF_VID)
 771                         ioq_vector->ioq_num     = i + oct->sriov_info.pf_srn;
 772                 else
 773                         ioq_vector->ioq_num     = i;
 774         }
 775         return 0;
 776 }
 777
 778 void
 779 octeon_free_ioq_vector(struct octeon_device *oct)
 780 {
 781         vfree(oct->ioq_vector);
 782 }
 783
 784 /* this function is only for setting up the first queue */
 785 int octeon_setup_instr_queues(struct octeon_device *oct)
 786 {
 787         u32 num_descs = 0;
 788         u32 iq_no = 0;
 789         union oct_txpciq txpciq;
 790         int numa_node = cpu_to_node(iq_no % num_online_cpus());
 791
 792         if (OCTEON_CN6XXX(oct))
 793                 num_descs =
 794                         CFG_GET_NUM_DEF_TX_DESCS(CHIP_CONF(oct, cn6xxx));
 795         else if (OCTEON_CN23XX_PF(oct))
 796                 num_descs = CFG_GET_NUM_DEF_TX_DESCS(CHIP_CONF(oct, cn23xx_pf));
 797
 798         oct->num_iqs = 0;
 799
 800         oct->instr_queue[0] = vmalloc_node(sizeof(*oct->instr_queue[0]),
 801                                 numa_node);
 802         if (!oct->instr_queue[0])
 803                 oct->instr_queue[0] =
 804                         vmalloc(sizeof(struct octeon_instr_queue));
 805         if (!oct->instr_queue[0])
 806                 return 1;
 807         memset(oct->instr_queue[0], 0, sizeof(struct octeon_instr_queue));
 808         oct->instr_queue[0]->q_index = 0;
 809         oct->instr_queue[0]->app_ctx = (void *)(size_t)0;
 810         oct->instr_queue[0]->ifidx = 0;
 811         txpciq.u64 = 0;
 812         txpciq.s.q_no = iq_no;
 813         txpciq.s.pkind = oct->pfvf_hsword.pkind;
 814         txpciq.s.use_qpg = 0;
 815         txpciq.s.qpg = 0;
 816         if (octeon_init_instr_queue(oct, txpciq, num_descs)) {
 817                 /* prevent memory leak */
 818                 vfree(oct->instr_queue[0]);
 819                 oct->instr_queue[0] = NULL;
 820                 return 1;
 821         }
 822
 823         oct->num_iqs++;
 824         return 0;
 825 }
 826
 827 int octeon_setup_output_queues(struct octeon_device *oct)
 828 {
 829         u32 num_descs = 0;
 830         u32 desc_size = 0;
 831         u32 oq_no = 0;
 832         int numa_node = cpu_to_node(oq_no % num_online_cpus());
 833
 834         if (OCTEON_CN6XXX(oct)) {
 835                 num_descs =
 836                         CFG_GET_NUM_DEF_RX_DESCS(CHIP_CONF(oct, cn6xxx));
 837                 desc_size =
 838                         CFG_GET_DEF_RX_BUF_SIZE(CHIP_CONF(oct, cn6xxx));
 839         } else if (OCTEON_CN23XX_PF(oct)) {
 840                 num_descs = CFG_GET_NUM_DEF_RX_DESCS(CHIP_CONF(oct, cn23xx_pf));
 841                 desc_size = CFG_GET_DEF_RX_BUF_SIZE(CHIP_CONF(oct, cn23xx_pf));
 842         }
 843         oct->num_oqs = 0;
 844         oct->droq[0] = vmalloc_node(sizeof(*oct->droq[0]), numa_node);
 845         if (!oct->droq[0])
 846                 oct->droq[0] = vmalloc(sizeof(*oct->droq[0]));
 847         if (!oct->droq[0])
 848                 return 1;
 849
 850         if (octeon_init_droq(oct, oq_no, num_descs, desc_size, NULL)) {
 851                 vfree(oct->droq[oq_no]);
 852                 oct->droq[oq_no] = NULL;
 853                 return 1;
 854         }
 855         oct->num_oqs++;
 856
 857         return 0;
 858 }
 859
 860 void octeon_set_io_queues_off(struct octeon_device *oct)
 861 {
 862         if (OCTEON_CN6XXX(oct)) {
 863                 octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB, 0);
 864                 octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, 0);
 865         }
 866 }
 867
 868 void octeon_set_droq_pkt_op(struct octeon_device *oct,
 869                             u32 q_no,
 870                             u32 enable)
 871 {
 872         u32 reg_val = 0;
 873
 874         /* Disable the i/p and o/p queues for this Octeon. */
 875         if (OCTEON_CN6XXX(oct)) {
 876                 reg_val = octeon_read_csr(oct, CN6XXX_SLI_PKT_OUT_ENB);
 877
 878                 if (enable)
 879                         reg_val = reg_val | (1 << q_no);
 880                 else
 881                         reg_val = reg_val & (~(1 << q_no));
 882
 883                 octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, reg_val);
 884         }
 885 }
 886
 887 int octeon_init_dispatch_list(struct octeon_device *oct)
 888 {
 889         u32 i;
 890
 891         oct->dispatch.count = 0;
 892
 893         for (i = 0; i < DISPATCH_LIST_SIZE; i++) {
 894                 oct->dispatch.dlist[i].opcode = 0;
 895                 INIT_LIST_HEAD(&oct->dispatch.dlist[i].list);
 896         }
 897
 898         for (i = 0; i <= REQTYPE_LAST; i++)
 899                 octeon_register_reqtype_free_fn(oct, i, NULL);
 900
 901         spin_lock_init(&oct->dispatch.lock);
 902
 903         return 0;
 904 }
 905
 906 void octeon_delete_dispatch_list(struct octeon_device *oct)
 907 {
 908         u32 i;
 909         struct list_head freelist, *temp, *tmp2;
 910
 911         INIT_LIST_HEAD(&freelist);
 912
 913         spin_lock_bh(&oct->dispatch.lock);
 914
 915         for (i = 0; i < DISPATCH_LIST_SIZE; i++) {
 916                 struct list_head *dispatch;
 917
 918                 dispatch = &oct->dispatch.dlist[i].list;
 919                 while (dispatch->next != dispatch) {
 920                         temp = dispatch->next;
 921                         list_del(temp);
 922                         list_add_tail(temp, &freelist);
 923                 }
 924
 925                 oct->dispatch.dlist[i].opcode = 0;
 926         }
 927
 928         oct->dispatch.count = 0;
 929
 930         spin_unlock_bh(&oct->dispatch.lock);
 931
 932         list_for_each_safe(temp, tmp2, &freelist) {
 933                 list_del(temp);
 934                 vfree(temp);
 935         }
 936 }
 937
 938 octeon_dispatch_fn_t
 939 octeon_get_dispatch(struct octeon_device *octeon_dev, u16 opcode,
 940                     u16 subcode)
 941 {
 942         u32 idx;
 943         struct list_head *dispatch;
 944         octeon_dispatch_fn_t fn = NULL;
 945         u16 combined_opcode = OPCODE_SUBCODE(opcode, subcode);
 946
 947         idx = combined_opcode & OCTEON_OPCODE_MASK;
 948
 949         spin_lock_bh(&octeon_dev->dispatch.lock);
 950
 951         if (octeon_dev->dispatch.count == 0) {
 952                 spin_unlock_bh(&octeon_dev->dispatch.lock);
 953                 return NULL;
 954         }
 955
 956         if (!(octeon_dev->dispatch.dlist[idx].opcode)) {
 957                 spin_unlock_bh(&octeon_dev->dispatch.lock);
 958                 return NULL;
 959         }
 960
 961         if (octeon_dev->dispatch.dlist[idx].opcode == combined_opcode) {
 962                 fn = octeon_dev->dispatch.dlist[idx].dispatch_fn;
 963         } else {
 964                 list_for_each(dispatch,
 965                               &octeon_dev->dispatch.dlist[idx].list) {
 966                         if (((struct octeon_dispatch *)dispatch)->opcode ==
 967                             combined_opcode) {
 968                                 fn = ((struct octeon_dispatch *)
 969                                       dispatch)->dispatch_fn;
 970                                 break;
 971                         }
 972                 }
 973         }
 974
 975         spin_unlock_bh(&octeon_dev->dispatch.lock);
 976         return fn;
 977 }
 978
 979 /* octeon_register_dispatch_fn
 980  * Parameters:
 981  *   octeon_id - id of the octeon device.
 982  *   opcode    - opcode for which driver should call the registered function
 983  *   subcode   - subcode for which driver should call the registered function
 984  *   fn        - The function to call when a packet with "opcode" arrives in
 985  *                octeon output queues.
 986  *   fn_arg    - The argument to be passed when calling function "fn".
 987  * Description:
 988  *   Registers a function and its argument to be called when a packet
 989  *   arrives in Octeon output queues with "opcode".
 990  * Returns:
 991  *   Success: 0
 992  *   Failure: 1
 993  * Locks:
 994  *   No locks are held.
 995  */
 996 int
 997 octeon_register_dispatch_fn(struct octeon_device *oct,
 998                             u16 opcode,
 999                             u16 subcode,
1000                             octeon_dispatch_fn_t fn, void *fn_arg)
1001 {
1002         u32 idx;
1003         octeon_dispatch_fn_t pfn;
1004         u16 combined_opcode = OPCODE_SUBCODE(opcode, subcode);
1005
1006         idx = combined_opcode & OCTEON_OPCODE_MASK;
1007
1008         spin_lock_bh(&oct->dispatch.lock);
1009         /* Add dispatch function to first level of lookup table */
1010         if (oct->dispatch.dlist[idx].opcode == 0) {
1011                 oct->dispatch.dlist[idx].opcode = combined_opcode;
1012                 oct->dispatch.dlist[idx].dispatch_fn = fn;
1013                 oct->dispatch.dlist[idx].arg = fn_arg;
1014                 oct->dispatch.count++;
1015                 spin_unlock_bh(&oct->dispatch.lock);
1016                 return 0;
1017         }
1018
1019         spin_unlock_bh(&oct->dispatch.lock);
1020
1021         /* Check if there was a function already registered for this
1022          * opcode/subcode.
1023          */
1024         pfn = octeon_get_dispatch(oct, opcode, subcode);
1025         if (!pfn) {
1026                 struct octeon_dispatch *dispatch;
1027
1028                 dev_dbg(&oct->pci_dev->dev,
1029                         "Adding opcode to dispatch list linked list\n");
1030                 dispatch = (struct octeon_dispatch *)
1031                            vmalloc(sizeof(struct octeon_dispatch));
1032                 if (!dispatch) {
1033                         dev_err(&oct->pci_dev->dev,
1034                                 "No memory to add dispatch function\n");
1035                         return 1;
1036                 }
1037                 dispatch->opcode = combined_opcode;
1038                 dispatch->dispatch_fn = fn;
1039                 dispatch->arg = fn_arg;
1040
1041                 /* Add dispatch function to linked list of fn ptrs
1042                  * at the hashed index.
1043                  */
1044                 spin_lock_bh(&oct->dispatch.lock);
1045                 list_add(&dispatch->list, &oct->dispatch.dlist[idx].list);
1046                 oct->dispatch.count++;
1047                 spin_unlock_bh(&oct->dispatch.lock);
1048
1049         } else {
1050                 dev_err(&oct->pci_dev->dev,
1051                         "Found previously registered dispatch fn for opcode/subcode: %x/%x\n",
1052                         opcode, subcode);
1053                 return 1;
1054         }
1055
1056         return 0;
1057 }
1058
1059 int octeon_core_drv_init(struct octeon_recv_info *recv_info, void *buf)
1060 {
1061         u32 i;
1062         char app_name[16];
1063         struct octeon_device *oct = (struct octeon_device *)buf;
1064         struct octeon_recv_pkt *recv_pkt = recv_info->recv_pkt;
1065         struct octeon_core_setup *cs = NULL;
1066         u32 num_nic_ports = 0;
1067
1068         if (OCTEON_CN6XXX(oct))
1069                 num_nic_ports =
1070                         CFG_GET_NUM_NIC_PORTS(CHIP_CONF(oct, cn6xxx));
1071         else if (OCTEON_CN23XX_PF(oct))
1072                 num_nic_ports =
1073                         CFG_GET_NUM_NIC_PORTS(CHIP_CONF(oct, cn23xx_pf));
1074
1075         if (atomic_read(&oct->status) >= OCT_DEV_RUNNING) {
1076                 dev_err(&oct->pci_dev->dev, "Received CORE OK when device state is 0x%x\n",
1077                         atomic_read(&oct->status));
1078                 goto core_drv_init_err;
1079         }
1080
1081         strncpy(app_name,
1082                 get_oct_app_string(
1083                 (u32)recv_pkt->rh.r_core_drv_init.app_mode),
1084                 sizeof(app_name) - 1);
1085         oct->app_mode = (u32)recv_pkt->rh.r_core_drv_init.app_mode;
1086         if (recv_pkt->rh.r_core_drv_init.app_mode == CVM_DRV_NIC_APP) {
1087                 oct->fw_info.max_nic_ports =
1088                         (u32)recv_pkt->rh.r_core_drv_init.max_nic_ports;
1089                 oct->fw_info.num_gmx_ports =
1090                         (u32)recv_pkt->rh.r_core_drv_init.num_gmx_ports;
1091         }
1092
1093         if (oct->fw_info.max_nic_ports < num_nic_ports) {
1094                 dev_err(&oct->pci_dev->dev,
1095                         "Config has more ports than firmware allows (%d > %d).\n",
1096                         num_nic_ports, oct->fw_info.max_nic_ports);
1097                 goto core_drv_init_err;
1098         }
1099         oct->fw_info.app_cap_flags = recv_pkt->rh.r_core_drv_init.app_cap_flags;
1100         oct->fw_info.app_mode = (u32)recv_pkt->rh.r_core_drv_init.app_mode;
1101         oct->pfvf_hsword.app_mode = (u32)recv_pkt->rh.r_core_drv_init.app_mode;
1102
1103         oct->pfvf_hsword.pkind = recv_pkt->rh.r_core_drv_init.pkind;
1104
1105         for (i = 0; i < oct->num_iqs; i++)
1106                 oct->instr_queue[i]->txpciq.s.pkind = oct->pfvf_hsword.pkind;
1107
1108         atomic_set(&oct->status, OCT_DEV_CORE_OK);
1109
1110         cs = &core_setup[oct->octeon_id];
1111
1112         if (recv_pkt->buffer_size[0] != sizeof(*cs)) {
1113                 dev_dbg(&oct->pci_dev->dev, "Core setup bytes expected %u found %d\n",
1114                         (u32)sizeof(*cs),
1115                         recv_pkt->buffer_size[0]);
1116         }
1117
1118         memcpy(cs, get_rbd(recv_pkt->buffer_ptr[0]), sizeof(*cs));
1119         strncpy(oct->boardinfo.name, cs->boardname, OCT_BOARD_NAME);
1120         strncpy(oct->boardinfo.serial_number, cs->board_serial_number,
1121                 OCT_SERIAL_LEN);
1122
1123         octeon_swap_8B_data((u64 *)cs, (sizeof(*cs) >> 3));
1124
1125         oct->boardinfo.major = cs->board_rev_major;
1126         oct->boardinfo.minor = cs->board_rev_minor;
1127
1128         dev_info(&oct->pci_dev->dev,
1129                  "Running %s (%llu Hz)\n",
1130                  app_name, CVM_CAST64(cs->corefreq));
1131
1132 core_drv_init_err:
1133         for (i = 0; i < recv_pkt->buffer_count; i++)
1134                 recv_buffer_free(recv_pkt->buffer_ptr[i]);
1135         octeon_free_recv_info(recv_info);
1136         return 0;
1137 }
1138
1139 int octeon_get_tx_qsize(struct octeon_device *oct, u32 q_no)
1140
1141 {
1142         if (oct && (q_no < MAX_OCTEON_INSTR_QUEUES(oct)) &&
1143             (oct->io_qmask.iq & BIT_ULL(q_no)))
1144                 return oct->instr_queue[q_no]->max_count;
1145
1146         return -1;
1147 }
1148
1149 int octeon_get_rx_qsize(struct octeon_device *oct, u32 q_no)
1150 {
1151         if (oct && (q_no < MAX_OCTEON_OUTPUT_QUEUES(oct)) &&
1152             (oct->io_qmask.oq & BIT_ULL(q_no)))
1153                 return oct->droq[q_no]->max_count;
1154         return -1;
1155 }
1156
1157 /* Retruns the host firmware handshake OCTEON specific configuration */
1158 struct octeon_config *octeon_get_conf(struct octeon_device *oct)
1159 {
1160         struct octeon_config *default_oct_conf = NULL;
1161
1162         /* check the OCTEON Device model & return the corresponding octeon
1163          * configuration
1164          */
1165
1166         if (OCTEON_CN6XXX(oct)) {
1167                 default_oct_conf =
1168                         (struct octeon_config *)(CHIP_CONF(oct, cn6xxx));
1169         } else if (OCTEON_CN23XX_PF(oct)) {
1170                 default_oct_conf = (struct octeon_config *)
1171                         (CHIP_CONF(oct, cn23xx_pf));
1172         }
1173         return default_oct_conf;
1174 }
1175
1176 /* scratch register address is same in all the OCT-II and CN70XX models */
1177 #define CNXX_SLI_SCRATCH1   0x3C0
1178
1179 /** Get the octeon device pointer.
1180  *  @param octeon_id  - The id for which the octeon device pointer is required.
1181  *  @return Success: Octeon device pointer.
1182  *  @return Failure: NULL.
1183  */
1184 struct octeon_device *lio_get_device(u32 octeon_id)
1185 {
1186         if (octeon_id >= MAX_OCTEON_DEVICES)
1187                 return NULL;
1188         else
1189                 return octeon_device[octeon_id];
1190 }
1191
1192 u64 lio_pci_readq(struct octeon_device *oct, u64 addr)
1193 {
1194         u64 val64;
1195         unsigned long flags;
1196         u32 val32, addrhi;
1197
1198         spin_lock_irqsave(&oct->pci_win_lock, flags);
1199
1200         /* The windowed read happens when the LSB of the addr is written.
1201          * So write MSB first
1202          */
1203         addrhi = (addr >> 32);
1204         if ((oct->chip_id == OCTEON_CN66XX) ||
1205             (oct->chip_id == OCTEON_CN68XX) ||
1206             (oct->chip_id == OCTEON_CN23XX_PF_VID))
1207                 addrhi |= 0x00060000;
1208         writel(addrhi, oct->reg_list.pci_win_rd_addr_hi);
1209
1210         /* Read back to preserve ordering of writes */
1211         val32 = readl(oct->reg_list.pci_win_rd_addr_hi);
1212
1213         writel(addr & 0xffffffff, oct->reg_list.pci_win_rd_addr_lo);
1214         val32 = readl(oct->reg_list.pci_win_rd_addr_lo);
1215
1216         val64 = readq(oct->reg_list.pci_win_rd_data);
1217
1218         spin_unlock_irqrestore(&oct->pci_win_lock, flags);
1219
1220         return val64;
1221 }
1222
1223 void lio_pci_writeq(struct octeon_device *oct,
1224                     u64 val,
1225                     u64 addr)
1226 {
1227         u32 val32;
1228         unsigned long flags;
1229
1230         spin_lock_irqsave(&oct->pci_win_lock, flags);
1231
1232         writeq(addr, oct->reg_list.pci_win_wr_addr);
1233
1234         /* The write happens when the LSB is written. So write MSB first. */
1235         writel(val >> 32, oct->reg_list.pci_win_wr_data_hi);
1236         /* Read the MSB to ensure ordering of writes. */
1237         val32 = readl(oct->reg_list.pci_win_wr_data_hi);
1238
1239         writel(val & 0xffffffff, oct->reg_list.pci_win_wr_data_lo);
1240
1241         spin_unlock_irqrestore(&oct->pci_win_lock, flags);
1242 }
1243
1244 int octeon_mem_access_ok(struct octeon_device *oct)
1245 {
1246         u64 access_okay = 0;
1247         u64 lmc0_reset_ctl;
1248
1249         /* Check to make sure a DDR interface is enabled */
1250         if (OCTEON_CN23XX_PF(oct)) {
1251                 lmc0_reset_ctl = lio_pci_readq(oct, CN23XX_LMC0_RESET_CTL);
1252                 access_okay =
1253                         (lmc0_reset_ctl & CN23XX_LMC0_RESET_CTL_DDR3RST_MASK);
1254         } else {
1255                 lmc0_reset_ctl = lio_pci_readq(oct, CN6XXX_LMC0_RESET_CTL);
1256                 access_okay =
1257                         (lmc0_reset_ctl & CN6XXX_LMC0_RESET_CTL_DDR3RST_MASK);
1258         }
1259
1260         return access_okay ? 0 : 1;
1261 }
1262
1263 int octeon_wait_for_ddr_init(struct octeon_device *oct, u32 *timeout)
1264 {
1265         int ret = 1;
1266         u32 ms;
1267
1268         if (!timeout)
1269                 return ret;
1270
1271         for (ms = 0; (ret != 0) && ((*timeout == 0) || (ms <= *timeout));
1272              ms += HZ / 10) {
1273                 ret = octeon_mem_access_ok(oct);
1274
1275                 /* wait 100 ms */
1276                 if (ret)
1277                         schedule_timeout_uninterruptible(HZ / 10);
1278         }
1279
1280         return ret;
1281 }
1282
1283 /** Get the octeon id assigned to the octeon device passed as argument.
1284  *  This function is exported to other modules.
1285  *  @param dev - octeon device pointer passed as a void *.
1286  *  @return octeon device id
1287  */
1288 int lio_get_device_id(void *dev)
1289 {
1290         struct octeon_device *octeon_dev = (struct octeon_device *)dev;
1291         u32 i;
1292
1293         for (i = 0; i < MAX_OCTEON_DEVICES; i++)
1294                 if (octeon_device[i] == octeon_dev)
1295                         return octeon_dev->octeon_id;
1296         return -1;
1297 }
1298
1299 void lio_enable_irq(struct octeon_droq *droq, struct octeon_instr_queue *iq)
1300 {
1301         u64 instr_cnt;
1302         struct octeon_device *oct = NULL;
1303
1304         /* the whole thing needs to be atomic, ideally */
1305         if (droq) {
1306                 spin_lock_bh(&droq->lock);
1307                 writel(droq->pkt_count, droq->pkts_sent_reg);
1308                 droq->pkt_count = 0;
1309                 spin_unlock_bh(&droq->lock);
1310                 oct = droq->oct_dev;
1311         }
1312         if (iq) {
1313                 spin_lock_bh(&iq->lock);
1314                 writel(iq->pkt_in_done, iq->inst_cnt_reg);
1315                 iq->pkt_in_done = 0;
1316                 spin_unlock_bh(&iq->lock);
1317                 oct = iq->oct_dev;
1318         }
1319         /*write resend. Writing RESEND in SLI_PKTX_CNTS should be enough
1320          *to trigger tx interrupts as well, if they are pending.
1321          */
1322         if (oct && OCTEON_CN23XX_PF(oct)) {
1323                 if (droq)
1324                         writeq(CN23XX_INTR_RESEND, droq->pkts_sent_reg);
1325                 /*we race with firmrware here. read and write the IN_DONE_CNTS*/
1326                 else if (iq) {
1327                         instr_cnt =  readq(iq->inst_cnt_reg);
1328                         writeq(((instr_cnt & 0xFFFFFFFF00000000ULL) |
1329                                 CN23XX_INTR_RESEND),
1330                                iq->inst_cnt_reg);
1331                 }
1332         }
1333 }