2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
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17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/delay.h>
38 #include "t4_values.h"
40 #include "t4fw_version.h"
43 * t4_wait_op_done_val - wait until an operation is completed
44 * @adapter: the adapter performing the operation
45 * @reg: the register to check for completion
46 * @mask: a single-bit field within @reg that indicates completion
47 * @polarity: the value of the field when the operation is completed
48 * @attempts: number of check iterations
49 * @delay: delay in usecs between iterations
50 * @valp: where to store the value of the register at completion time
52 * Wait until an operation is completed by checking a bit in a register
53 * up to @attempts times. If @valp is not NULL the value of the register
54 * at the time it indicated completion is stored there. Returns 0 if the
55 * operation completes and -EAGAIN otherwise.
57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
58 int polarity, int attempts, int delay, u32 *valp)
61 u32 val = t4_read_reg(adapter, reg);
63 if (!!(val & mask) == polarity) {
75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
76 int polarity, int attempts, int delay)
78 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
83 * t4_set_reg_field - set a register field to a value
84 * @adapter: the adapter to program
85 * @addr: the register address
86 * @mask: specifies the portion of the register to modify
87 * @val: the new value for the register field
89 * Sets a register field specified by the supplied mask to the
92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
95 u32 v = t4_read_reg(adapter, addr) & ~mask;
97 t4_write_reg(adapter, addr, v | val);
98 (void) t4_read_reg(adapter, addr); /* flush */
102 * t4_read_indirect - read indirectly addressed registers
104 * @addr_reg: register holding the indirect address
105 * @data_reg: register holding the value of the indirect register
106 * @vals: where the read register values are stored
107 * @nregs: how many indirect registers to read
108 * @start_idx: index of first indirect register to read
110 * Reads registers that are accessed indirectly through an address/data
113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
114 unsigned int data_reg, u32 *vals,
115 unsigned int nregs, unsigned int start_idx)
118 t4_write_reg(adap, addr_reg, start_idx);
119 *vals++ = t4_read_reg(adap, data_reg);
125 * t4_write_indirect - write indirectly addressed registers
127 * @addr_reg: register holding the indirect addresses
128 * @data_reg: register holding the value for the indirect registers
129 * @vals: values to write
130 * @nregs: how many indirect registers to write
131 * @start_idx: address of first indirect register to write
133 * Writes a sequential block of registers that are accessed indirectly
134 * through an address/data register pair.
136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
137 unsigned int data_reg, const u32 *vals,
138 unsigned int nregs, unsigned int start_idx)
141 t4_write_reg(adap, addr_reg, start_idx++);
142 t4_write_reg(adap, data_reg, *vals++);
147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
148 * mechanism. This guarantees that we get the real value even if we're
149 * operating within a Virtual Machine and the Hypervisor is trapping our
150 * Configuration Space accesses.
152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
154 u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
156 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
161 if (is_t4(adap->params.chip))
164 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
165 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
168 * Configuration Space read. (None of the other fields matter when
169 * ENABLE is 0 so a simple register write is easier than a
170 * read-modify-write via t4_set_reg_field().)
172 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
176 * t4_report_fw_error - report firmware error
179 * The adapter firmware can indicate error conditions to the host.
180 * If the firmware has indicated an error, print out the reason for
181 * the firmware error.
183 static void t4_report_fw_error(struct adapter *adap)
185 static const char *const reason[] = {
186 "Crash", /* PCIE_FW_EVAL_CRASH */
187 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
188 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
189 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
190 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
191 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
192 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
193 "Reserved", /* reserved */
197 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
198 if (pcie_fw & PCIE_FW_ERR_F)
199 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
200 reason[PCIE_FW_EVAL_G(pcie_fw)]);
204 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
206 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
209 for ( ; nflit; nflit--, mbox_addr += 8)
210 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
214 * Handle a FW assertion reported in a mailbox.
216 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
218 struct fw_debug_cmd asrt;
220 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
221 dev_alert(adap->pdev_dev,
222 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
223 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
224 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
228 * t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
229 * @adapter: the adapter
230 * @cmd: the Firmware Mailbox Command or Reply
231 * @size: command length in bytes
232 * @access: the time (ms) needed to access the Firmware Mailbox
233 * @execute: the time (ms) the command spent being executed
235 static void t4_record_mbox(struct adapter *adapter,
236 const __be64 *cmd, unsigned int size,
237 int access, int execute)
239 struct mbox_cmd_log *log = adapter->mbox_log;
240 struct mbox_cmd *entry;
243 entry = mbox_cmd_log_entry(log, log->cursor++);
244 if (log->cursor == log->size)
247 for (i = 0; i < size / 8; i++)
248 entry->cmd[i] = be64_to_cpu(cmd[i]);
249 while (i < MBOX_LEN / 8)
251 entry->timestamp = jiffies;
252 entry->seqno = log->seqno++;
253 entry->access = access;
254 entry->execute = execute;
258 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
260 * @mbox: index of the mailbox to use
261 * @cmd: the command to write
262 * @size: command length in bytes
263 * @rpl: where to optionally store the reply
264 * @sleep_ok: if true we may sleep while awaiting command completion
265 * @timeout: time to wait for command to finish before timing out
267 * Sends the given command to FW through the selected mailbox and waits
268 * for the FW to execute the command. If @rpl is not %NULL it is used to
269 * store the FW's reply to the command. The command and its optional
270 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
271 * to respond. @sleep_ok determines whether we may sleep while awaiting
272 * the response. If sleeping is allowed we use progressive backoff
275 * The return value is 0 on success or a negative errno on failure. A
276 * failure can happen either because we are not able to execute the
277 * command or FW executes it but signals an error. In the latter case
278 * the return value is the error code indicated by FW (negated).
280 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
281 int size, void *rpl, bool sleep_ok, int timeout)
283 static const int delay[] = {
284 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
287 struct mbox_list entry;
292 int i, ms, delay_idx, ret;
293 const __be64 *p = cmd;
294 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
295 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
296 __be64 cmd_rpl[MBOX_LEN / 8];
299 if ((size & 15) || size > MBOX_LEN)
303 * If the device is off-line, as in EEH, commands will time out.
304 * Fail them early so we don't waste time waiting.
306 if (adap->pdev->error_state != pci_channel_io_normal)
309 /* If we have a negative timeout, that implies that we can't sleep. */
315 /* Queue ourselves onto the mailbox access list. When our entry is at
316 * the front of the list, we have rights to access the mailbox. So we
317 * wait [for a while] till we're at the front [or bail out with an
320 spin_lock(&adap->mbox_lock);
321 list_add_tail(&entry.list, &adap->mlist.list);
322 spin_unlock(&adap->mbox_lock);
327 for (i = 0; ; i += ms) {
328 /* If we've waited too long, return a busy indication. This
329 * really ought to be based on our initial position in the
330 * mailbox access list but this is a start. We very rearely
331 * contend on access to the mailbox ...
333 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
334 if (i > FW_CMD_MAX_TIMEOUT || (pcie_fw & PCIE_FW_ERR_F)) {
335 spin_lock(&adap->mbox_lock);
336 list_del(&entry.list);
337 spin_unlock(&adap->mbox_lock);
338 ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -EBUSY;
339 t4_record_mbox(adap, cmd, size, access, ret);
343 /* If we're at the head, break out and start the mailbox
346 if (list_first_entry(&adap->mlist.list, struct mbox_list,
350 /* Delay for a bit before checking again ... */
352 ms = delay[delay_idx]; /* last element may repeat */
353 if (delay_idx < ARRAY_SIZE(delay) - 1)
361 /* Loop trying to get ownership of the mailbox. Return an error
362 * if we can't gain ownership.
364 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
365 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
366 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
367 if (v != MBOX_OWNER_DRV) {
368 spin_lock(&adap->mbox_lock);
369 list_del(&entry.list);
370 spin_unlock(&adap->mbox_lock);
371 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
372 t4_record_mbox(adap, cmd, size, access, ret);
376 /* Copy in the new mailbox command and send it on its way ... */
377 t4_record_mbox(adap, cmd, size, access, 0);
378 for (i = 0; i < size; i += 8)
379 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
381 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
382 t4_read_reg(adap, ctl_reg); /* flush write */
388 !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) &&
392 ms = delay[delay_idx]; /* last element may repeat */
393 if (delay_idx < ARRAY_SIZE(delay) - 1)
399 v = t4_read_reg(adap, ctl_reg);
400 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
401 if (!(v & MBMSGVALID_F)) {
402 t4_write_reg(adap, ctl_reg, 0);
406 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN / 8, data_reg);
407 res = be64_to_cpu(cmd_rpl[0]);
409 if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
410 fw_asrt(adap, data_reg);
411 res = FW_CMD_RETVAL_V(EIO);
413 memcpy(rpl, cmd_rpl, size);
416 t4_write_reg(adap, ctl_reg, 0);
419 t4_record_mbox(adap, cmd_rpl,
420 MBOX_LEN, access, execute);
421 spin_lock(&adap->mbox_lock);
422 list_del(&entry.list);
423 spin_unlock(&adap->mbox_lock);
424 return -FW_CMD_RETVAL_G((int)res);
428 ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -ETIMEDOUT;
429 t4_record_mbox(adap, cmd, size, access, ret);
430 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
431 *(const u8 *)cmd, mbox);
432 t4_report_fw_error(adap);
433 spin_lock(&adap->mbox_lock);
434 list_del(&entry.list);
435 spin_unlock(&adap->mbox_lock);
440 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
441 void *rpl, bool sleep_ok)
443 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
447 static int t4_edc_err_read(struct adapter *adap, int idx)
449 u32 edc_ecc_err_addr_reg;
452 if (is_t4(adap->params.chip)) {
453 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
456 if (idx != 0 && idx != 1) {
457 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
461 edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
462 rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
465 "edc%d err addr 0x%x: 0x%x.\n",
466 idx, edc_ecc_err_addr_reg,
467 t4_read_reg(adap, edc_ecc_err_addr_reg));
469 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
471 (unsigned long long)t4_read_reg64(adap, rdata_reg),
472 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
473 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
474 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
475 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
476 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
477 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
478 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
479 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
485 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
487 * @win: PCI-E Memory Window to use
488 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
489 * @addr: address within indicated memory type
490 * @len: amount of memory to transfer
491 * @hbuf: host memory buffer
492 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
494 * Reads/writes an [almost] arbitrary memory region in the firmware: the
495 * firmware memory address and host buffer must be aligned on 32-bit
496 * boudaries; the length may be arbitrary. The memory is transferred as
497 * a raw byte sequence from/to the firmware's memory. If this memory
498 * contains data structures which contain multi-byte integers, it's the
499 * caller's responsibility to perform appropriate byte order conversions.
501 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
502 u32 len, void *hbuf, int dir)
504 u32 pos, offset, resid, memoffset;
505 u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
508 /* Argument sanity checks ...
510 if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
514 /* It's convenient to be able to handle lengths which aren't a
515 * multiple of 32-bits because we often end up transferring files to
516 * the firmware. So we'll handle that by normalizing the length here
517 * and then handling any residual transfer at the end.
522 /* Offset into the region of memory which is being accessed
525 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
526 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
528 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
529 if (mtype != MEM_MC1)
530 memoffset = (mtype * (edc_size * 1024 * 1024));
532 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
533 MA_EXT_MEMORY0_BAR_A));
534 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
537 /* Determine the PCIE_MEM_ACCESS_OFFSET */
538 addr = addr + memoffset;
540 /* Each PCI-E Memory Window is programmed with a window size -- or
541 * "aperture" -- which controls the granularity of its mapping onto
542 * adapter memory. We need to grab that aperture in order to know
543 * how to use the specified window. The window is also programmed
544 * with the base address of the Memory Window in BAR0's address
545 * space. For T4 this is an absolute PCI-E Bus Address. For T5
546 * the address is relative to BAR0.
548 mem_reg = t4_read_reg(adap,
549 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
551 mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
552 mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
553 if (is_t4(adap->params.chip))
554 mem_base -= adap->t4_bar0;
555 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
557 /* Calculate our initial PCI-E Memory Window Position and Offset into
560 pos = addr & ~(mem_aperture-1);
563 /* Set up initial PCI-E Memory Window to cover the start of our
564 * transfer. (Read it back to ensure that changes propagate before we
565 * attempt to use the new value.)
568 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
571 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
573 /* Transfer data to/from the adapter as long as there's an integral
574 * number of 32-bit transfers to complete.
576 * A note on Endianness issues:
578 * The "register" reads and writes below from/to the PCI-E Memory
579 * Window invoke the standard adapter Big-Endian to PCI-E Link
580 * Little-Endian "swizzel." As a result, if we have the following
581 * data in adapter memory:
583 * Memory: ... | b0 | b1 | b2 | b3 | ...
584 * Address: i+0 i+1 i+2 i+3
586 * Then a read of the adapter memory via the PCI-E Memory Window
591 * [ b3 | b2 | b1 | b0 ]
593 * If this value is stored into local memory on a Little-Endian system
594 * it will show up correctly in local memory as:
596 * ( ..., b0, b1, b2, b3, ... )
598 * But on a Big-Endian system, the store will show up in memory
599 * incorrectly swizzled as:
601 * ( ..., b3, b2, b1, b0, ... )
603 * So we need to account for this in the reads and writes to the
604 * PCI-E Memory Window below by undoing the register read/write
608 if (dir == T4_MEMORY_READ)
609 *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
612 t4_write_reg(adap, mem_base + offset,
613 (__force u32)cpu_to_le32(*buf++));
614 offset += sizeof(__be32);
615 len -= sizeof(__be32);
617 /* If we've reached the end of our current window aperture,
618 * move the PCI-E Memory Window on to the next. Note that
619 * doing this here after "len" may be 0 allows us to set up
620 * the PCI-E Memory Window for a possible final residual
623 if (offset == mem_aperture) {
627 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
630 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
635 /* If the original transfer had a length which wasn't a multiple of
636 * 32-bits, now's where we need to finish off the transfer of the
637 * residual amount. The PCI-E Memory Window has already been moved
638 * above (if necessary) to cover this final transfer.
648 if (dir == T4_MEMORY_READ) {
649 last.word = le32_to_cpu(
650 (__force __le32)t4_read_reg(adap,
652 for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
653 bp[i] = last.byte[i];
656 for (i = resid; i < 4; i++)
658 t4_write_reg(adap, mem_base + offset,
659 (__force u32)cpu_to_le32(last.word));
666 /* Return the specified PCI-E Configuration Space register from our Physical
667 * Function. We try first via a Firmware LDST Command since we prefer to let
668 * the firmware own all of these registers, but if that fails we go for it
669 * directly ourselves.
671 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
673 u32 val, ldst_addrspace;
675 /* If fw_attach != 0, construct and send the Firmware LDST Command to
676 * retrieve the specified PCI-E Configuration Space register.
678 struct fw_ldst_cmd ldst_cmd;
681 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
682 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
683 ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
687 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
688 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
689 ldst_cmd.u.pcie.ctrl_to_fn =
690 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
691 ldst_cmd.u.pcie.r = reg;
693 /* If the LDST Command succeeds, return the result, otherwise
694 * fall through to reading it directly ourselves ...
696 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
699 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
701 /* Read the desired Configuration Space register via the PCI-E
702 * Backdoor mechanism.
704 t4_hw_pci_read_cfg4(adap, reg, &val);
708 /* Get the window based on base passed to it.
709 * Window aperture is currently unhandled, but there is no use case for it
712 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
717 if (is_t4(adap->params.chip)) {
720 /* Truncation intentional: we only read the bottom 32-bits of
721 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
722 * mechanism to read BAR0 instead of using
723 * pci_resource_start() because we could be operating from
724 * within a Virtual Machine which is trapping our accesses to
725 * our Configuration Space and we need to set up the PCI-E
726 * Memory Window decoders with the actual addresses which will
727 * be coming across the PCI-E link.
729 bar0 = t4_read_pcie_cfg4(adap, pci_base);
731 adap->t4_bar0 = bar0;
733 ret = bar0 + memwin_base;
735 /* For T5, only relative offset inside the PCIe BAR is passed */
741 /* Get the default utility window (win0) used by everyone */
742 u32 t4_get_util_window(struct adapter *adap)
744 return t4_get_window(adap, PCI_BASE_ADDRESS_0,
745 PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
748 /* Set up memory window for accessing adapter memory ranges. (Read
749 * back MA register to ensure that changes propagate before we attempt
750 * to use the new values.)
752 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
755 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
756 memwin_base | BIR_V(0) |
757 WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
759 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
763 * t4_get_regs_len - return the size of the chips register set
764 * @adapter: the adapter
766 * Returns the size of the chip's BAR0 register space.
768 unsigned int t4_get_regs_len(struct adapter *adapter)
770 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
772 switch (chip_version) {
774 return T4_REGMAP_SIZE;
778 return T5_REGMAP_SIZE;
781 dev_err(adapter->pdev_dev,
782 "Unsupported chip version %d\n", chip_version);
787 * t4_get_regs - read chip registers into provided buffer
789 * @buf: register buffer
790 * @buf_size: size (in bytes) of register buffer
792 * If the provided register buffer isn't large enough for the chip's
793 * full register range, the register dump will be truncated to the
794 * register buffer's size.
796 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
798 static const unsigned int t4_reg_ranges[] = {
1256 static const unsigned int t5_reg_ranges[] = {
2031 static const unsigned int t6_reg_ranges[] = {
2608 u32 *buf_end = (u32 *)((char *)buf + buf_size);
2609 const unsigned int *reg_ranges;
2610 int reg_ranges_size, range;
2611 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2613 /* Select the right set of register ranges to dump depending on the
2614 * adapter chip type.
2616 switch (chip_version) {
2618 reg_ranges = t4_reg_ranges;
2619 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2623 reg_ranges = t5_reg_ranges;
2624 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2628 reg_ranges = t6_reg_ranges;
2629 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2633 dev_err(adap->pdev_dev,
2634 "Unsupported chip version %d\n", chip_version);
2638 /* Clear the register buffer and insert the appropriate register
2639 * values selected by the above register ranges.
2641 memset(buf, 0, buf_size);
2642 for (range = 0; range < reg_ranges_size; range += 2) {
2643 unsigned int reg = reg_ranges[range];
2644 unsigned int last_reg = reg_ranges[range + 1];
2645 u32 *bufp = (u32 *)((char *)buf + reg);
2647 /* Iterate across the register range filling in the register
2648 * buffer but don't write past the end of the register buffer.
2650 while (reg <= last_reg && bufp < buf_end) {
2651 *bufp++ = t4_read_reg(adap, reg);
2657 #define EEPROM_STAT_ADDR 0x7bfc
2658 #define VPD_SIZE 0x800
2659 #define VPD_BASE 0x400
2660 #define VPD_BASE_OLD 0
2661 #define VPD_LEN 1024
2662 #define CHELSIO_VPD_UNIQUE_ID 0x82
2665 * t4_seeprom_wp - enable/disable EEPROM write protection
2666 * @adapter: the adapter
2667 * @enable: whether to enable or disable write protection
2669 * Enables or disables write protection on the serial EEPROM.
2671 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2673 unsigned int v = enable ? 0xc : 0;
2674 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2675 return ret < 0 ? ret : 0;
2679 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2680 * @adapter: adapter to read
2681 * @p: where to store the parameters
2683 * Reads card parameters stored in VPD EEPROM.
2685 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2687 int i, ret = 0, addr;
2690 unsigned int vpdr_len, kw_offset, id_len;
2692 vpd = vmalloc(VPD_LEN);
2696 /* We have two VPD data structures stored in the adapter VPD area.
2697 * By default, Linux calculates the size of the VPD area by traversing
2698 * the first VPD area at offset 0x0, so we need to tell the OS what
2699 * our real VPD size is.
2701 ret = pci_set_vpd_size(adapter->pdev, VPD_SIZE);
2705 /* Card information normally starts at VPD_BASE but early cards had
2708 ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2712 /* The VPD shall have a unique identifier specified by the PCI SIG.
2713 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2714 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2715 * is expected to automatically put this entry at the
2716 * beginning of the VPD.
2718 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2720 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2724 if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2725 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2730 id_len = pci_vpd_lrdt_size(vpd);
2731 if (id_len > ID_LEN)
2734 i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2736 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2741 vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2742 kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2743 if (vpdr_len + kw_offset > VPD_LEN) {
2744 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2749 #define FIND_VPD_KW(var, name) do { \
2750 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2752 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2756 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2759 FIND_VPD_KW(i, "RV");
2760 for (csum = 0; i >= 0; i--)
2764 dev_err(adapter->pdev_dev,
2765 "corrupted VPD EEPROM, actual csum %u\n", csum);
2770 FIND_VPD_KW(ec, "EC");
2771 FIND_VPD_KW(sn, "SN");
2772 FIND_VPD_KW(pn, "PN");
2773 FIND_VPD_KW(na, "NA");
2776 memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2778 memcpy(p->ec, vpd + ec, EC_LEN);
2780 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2781 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2783 i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2784 memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2786 memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2787 strim((char *)p->na);
2791 return ret < 0 ? ret : 0;
2795 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2796 * @adapter: adapter to read
2797 * @p: where to store the parameters
2799 * Reads card parameters stored in VPD EEPROM and retrieves the Core
2800 * Clock. This can only be called after a connection to the firmware
2803 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2805 u32 cclk_param, cclk_val;
2808 /* Grab the raw VPD parameters.
2810 ret = t4_get_raw_vpd_params(adapter, p);
2814 /* Ask firmware for the Core Clock since it knows how to translate the
2815 * Reference Clock ('V2') VPD field into a Core Clock value ...
2817 cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2818 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2819 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2820 1, &cclk_param, &cclk_val);
2829 /* serial flash and firmware constants */
2831 SF_ATTEMPTS = 10, /* max retries for SF operations */
2833 /* flash command opcodes */
2834 SF_PROG_PAGE = 2, /* program page */
2835 SF_WR_DISABLE = 4, /* disable writes */
2836 SF_RD_STATUS = 5, /* read status register */
2837 SF_WR_ENABLE = 6, /* enable writes */
2838 SF_RD_DATA_FAST = 0xb, /* read flash */
2839 SF_RD_ID = 0x9f, /* read ID */
2840 SF_ERASE_SECTOR = 0xd8, /* erase sector */
2842 FW_MAX_SIZE = 16 * SF_SEC_SIZE,
2846 * sf1_read - read data from the serial flash
2847 * @adapter: the adapter
2848 * @byte_cnt: number of bytes to read
2849 * @cont: whether another operation will be chained
2850 * @lock: whether to lock SF for PL access only
2851 * @valp: where to store the read data
2853 * Reads up to 4 bytes of data from the serial flash. The location of
2854 * the read needs to be specified prior to calling this by issuing the
2855 * appropriate commands to the serial flash.
2857 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2858 int lock, u32 *valp)
2862 if (!byte_cnt || byte_cnt > 4)
2864 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2866 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2867 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2868 ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2870 *valp = t4_read_reg(adapter, SF_DATA_A);
2875 * sf1_write - write data to the serial flash
2876 * @adapter: the adapter
2877 * @byte_cnt: number of bytes to write
2878 * @cont: whether another operation will be chained
2879 * @lock: whether to lock SF for PL access only
2880 * @val: value to write
2882 * Writes up to 4 bytes of data to the serial flash. The location of
2883 * the write needs to be specified prior to calling this by issuing the
2884 * appropriate commands to the serial flash.
2886 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2889 if (!byte_cnt || byte_cnt > 4)
2891 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2893 t4_write_reg(adapter, SF_DATA_A, val);
2894 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2895 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2896 return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2900 * flash_wait_op - wait for a flash operation to complete
2901 * @adapter: the adapter
2902 * @attempts: max number of polls of the status register
2903 * @delay: delay between polls in ms
2905 * Wait for a flash operation to complete by polling the status register.
2907 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
2913 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
2914 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
2918 if (--attempts == 0)
2926 * t4_read_flash - read words from serial flash
2927 * @adapter: the adapter
2928 * @addr: the start address for the read
2929 * @nwords: how many 32-bit words to read
2930 * @data: where to store the read data
2931 * @byte_oriented: whether to store data as bytes or as words
2933 * Read the specified number of 32-bit words from the serial flash.
2934 * If @byte_oriented is set the read data is stored as a byte array
2935 * (i.e., big-endian), otherwise as 32-bit words in the platform's
2936 * natural endianness.
2938 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2939 unsigned int nwords, u32 *data, int byte_oriented)
2943 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
2946 addr = swab32(addr) | SF_RD_DATA_FAST;
2948 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
2949 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
2952 for ( ; nwords; nwords--, data++) {
2953 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2955 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2959 *data = (__force __u32)(cpu_to_be32(*data));
2965 * t4_write_flash - write up to a page of data to the serial flash
2966 * @adapter: the adapter
2967 * @addr: the start address to write
2968 * @n: length of data to write in bytes
2969 * @data: the data to write
2971 * Writes up to a page of data (256 bytes) to the serial flash starting
2972 * at the given address. All the data must be written to the same page.
2974 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
2975 unsigned int n, const u8 *data)
2979 unsigned int i, c, left, val, offset = addr & 0xff;
2981 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
2984 val = swab32(addr) | SF_PROG_PAGE;
2986 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
2987 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
2990 for (left = n; left; left -= c) {
2992 for (val = 0, i = 0; i < c; ++i)
2993 val = (val << 8) + *data++;
2995 ret = sf1_write(adapter, c, c != left, 1, val);
2999 ret = flash_wait_op(adapter, 8, 1);
3003 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3005 /* Read the page to verify the write succeeded */
3006 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
3010 if (memcmp(data - n, (u8 *)buf + offset, n)) {
3011 dev_err(adapter->pdev_dev,
3012 "failed to correctly write the flash page at %#x\n",
3019 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3024 * t4_get_fw_version - read the firmware version
3025 * @adapter: the adapter
3026 * @vers: where to place the version
3028 * Reads the FW version from flash.
3030 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3032 return t4_read_flash(adapter, FLASH_FW_START +
3033 offsetof(struct fw_hdr, fw_ver), 1,
3038 * t4_get_bs_version - read the firmware bootstrap version
3039 * @adapter: the adapter
3040 * @vers: where to place the version
3042 * Reads the FW Bootstrap version from flash.
3044 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3046 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3047 offsetof(struct fw_hdr, fw_ver), 1,
3052 * t4_get_tp_version - read the TP microcode version
3053 * @adapter: the adapter
3054 * @vers: where to place the version
3056 * Reads the TP microcode version from flash.
3058 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3060 return t4_read_flash(adapter, FLASH_FW_START +
3061 offsetof(struct fw_hdr, tp_microcode_ver),
3066 * t4_get_exprom_version - return the Expansion ROM version (if any)
3067 * @adapter: the adapter
3068 * @vers: where to place the version
3070 * Reads the Expansion ROM header from FLASH and returns the version
3071 * number (if present) through the @vers return value pointer. We return
3072 * this in the Firmware Version Format since it's convenient. Return
3073 * 0 on success, -ENOENT if no Expansion ROM is present.
3075 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3077 struct exprom_header {
3078 unsigned char hdr_arr[16]; /* must start with 0x55aa */
3079 unsigned char hdr_ver[4]; /* Expansion ROM version */
3081 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3085 ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3086 ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3091 hdr = (struct exprom_header *)exprom_header_buf;
3092 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3095 *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
3096 FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
3097 FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
3098 FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
3103 * t4_check_fw_version - check if the FW is supported with this driver
3104 * @adap: the adapter
3106 * Checks if an adapter's FW is compatible with the driver. Returns 0
3107 * if there's exact match, a negative error if the version could not be
3108 * read or there's a major version mismatch
3110 int t4_check_fw_version(struct adapter *adap)
3112 int i, ret, major, minor, micro;
3113 int exp_major, exp_minor, exp_micro;
3114 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3116 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3117 /* Try multiple times before returning error */
3118 for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3119 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3124 major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3125 minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3126 micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3128 switch (chip_version) {
3130 exp_major = T4FW_MIN_VERSION_MAJOR;
3131 exp_minor = T4FW_MIN_VERSION_MINOR;
3132 exp_micro = T4FW_MIN_VERSION_MICRO;
3135 exp_major = T5FW_MIN_VERSION_MAJOR;
3136 exp_minor = T5FW_MIN_VERSION_MINOR;
3137 exp_micro = T5FW_MIN_VERSION_MICRO;
3140 exp_major = T6FW_MIN_VERSION_MAJOR;
3141 exp_minor = T6FW_MIN_VERSION_MINOR;
3142 exp_micro = T6FW_MIN_VERSION_MICRO;
3145 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3150 if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3151 (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3152 dev_err(adap->pdev_dev,
3153 "Card has firmware version %u.%u.%u, minimum "
3154 "supported firmware is %u.%u.%u.\n", major, minor,
3155 micro, exp_major, exp_minor, exp_micro);
3161 /* Is the given firmware API compatible with the one the driver was compiled
3164 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3167 /* short circuit if it's the exact same firmware version */
3168 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3171 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3172 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3173 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3180 /* The firmware in the filesystem is usable, but should it be installed?
3181 * This routine explains itself in detail if it indicates the filesystem
3182 * firmware should be installed.
3184 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3189 if (!card_fw_usable) {
3190 reason = "incompatible or unusable";
3195 reason = "older than the version supported with this driver";
3202 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3203 "installing firmware %u.%u.%u.%u on card.\n",
3204 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3205 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3206 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3207 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3212 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3213 const u8 *fw_data, unsigned int fw_size,
3214 struct fw_hdr *card_fw, enum dev_state state,
3217 int ret, card_fw_usable, fs_fw_usable;
3218 const struct fw_hdr *fs_fw;
3219 const struct fw_hdr *drv_fw;
3221 drv_fw = &fw_info->fw_hdr;
3223 /* Read the header of the firmware on the card */
3224 ret = -t4_read_flash(adap, FLASH_FW_START,
3225 sizeof(*card_fw) / sizeof(uint32_t),
3226 (uint32_t *)card_fw, 1);
3228 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3230 dev_err(adap->pdev_dev,
3231 "Unable to read card's firmware header: %d\n", ret);
3235 if (fw_data != NULL) {
3236 fs_fw = (const void *)fw_data;
3237 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3243 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3244 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3245 /* Common case: the firmware on the card is an exact match and
3246 * the filesystem one is an exact match too, or the filesystem
3247 * one is absent/incompatible.
3249 } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3250 should_install_fs_fw(adap, card_fw_usable,
3251 be32_to_cpu(fs_fw->fw_ver),
3252 be32_to_cpu(card_fw->fw_ver))) {
3253 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
3256 dev_err(adap->pdev_dev,
3257 "failed to install firmware: %d\n", ret);
3261 /* Installed successfully, update the cached header too. */
3264 *reset = 0; /* already reset as part of load_fw */
3267 if (!card_fw_usable) {
3270 d = be32_to_cpu(drv_fw->fw_ver);
3271 c = be32_to_cpu(card_fw->fw_ver);
3272 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3274 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3276 "driver compiled with %d.%d.%d.%d, "
3277 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3279 FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3280 FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3281 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3282 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3283 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3284 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3289 /* We're using whatever's on the card and it's known to be good. */
3290 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3291 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3298 * t4_flash_erase_sectors - erase a range of flash sectors
3299 * @adapter: the adapter
3300 * @start: the first sector to erase
3301 * @end: the last sector to erase
3303 * Erases the sectors in the given inclusive range.
3305 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3309 if (end >= adapter->params.sf_nsec)
3312 while (start <= end) {
3313 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3314 (ret = sf1_write(adapter, 4, 0, 1,
3315 SF_ERASE_SECTOR | (start << 8))) != 0 ||
3316 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3317 dev_err(adapter->pdev_dev,
3318 "erase of flash sector %d failed, error %d\n",
3324 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3329 * t4_flash_cfg_addr - return the address of the flash configuration file
3330 * @adapter: the adapter
3332 * Return the address within the flash where the Firmware Configuration
3335 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3337 if (adapter->params.sf_size == 0x100000)
3338 return FLASH_FPGA_CFG_START;
3340 return FLASH_CFG_START;
3343 /* Return TRUE if the specified firmware matches the adapter. I.e. T4
3344 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
3345 * and emit an error message for mismatched firmware to save our caller the
3348 static bool t4_fw_matches_chip(const struct adapter *adap,
3349 const struct fw_hdr *hdr)
3351 /* The expression below will return FALSE for any unsupported adapter
3352 * which will keep us "honest" in the future ...
3354 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3355 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3356 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3359 dev_err(adap->pdev_dev,
3360 "FW image (%d) is not suitable for this adapter (%d)\n",
3361 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3366 * t4_load_fw - download firmware
3367 * @adap: the adapter
3368 * @fw_data: the firmware image to write
3371 * Write the supplied firmware image to the card's serial flash.
3373 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3378 u8 first_page[SF_PAGE_SIZE];
3379 const __be32 *p = (const __be32 *)fw_data;
3380 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3381 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3382 unsigned int fw_img_start = adap->params.sf_fw_start;
3383 unsigned int fw_start_sec = fw_img_start / sf_sec_size;
3386 dev_err(adap->pdev_dev, "FW image has no data\n");
3390 dev_err(adap->pdev_dev,
3391 "FW image size not multiple of 512 bytes\n");
3394 if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3395 dev_err(adap->pdev_dev,
3396 "FW image size differs from size in FW header\n");
3399 if (size > FW_MAX_SIZE) {
3400 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3404 if (!t4_fw_matches_chip(adap, hdr))
3407 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3408 csum += be32_to_cpu(p[i]);
3410 if (csum != 0xffffffff) {
3411 dev_err(adap->pdev_dev,
3412 "corrupted firmware image, checksum %#x\n", csum);
3416 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
3417 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3422 * We write the correct version at the end so the driver can see a bad
3423 * version if the FW write fails. Start by writing a copy of the
3424 * first page with a bad version.
3426 memcpy(first_page, fw_data, SF_PAGE_SIZE);
3427 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3428 ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page);
3432 addr = fw_img_start;
3433 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3434 addr += SF_PAGE_SIZE;
3435 fw_data += SF_PAGE_SIZE;
3436 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
3441 ret = t4_write_flash(adap,
3442 fw_img_start + offsetof(struct fw_hdr, fw_ver),
3443 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
3446 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3449 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3454 * t4_phy_fw_ver - return current PHY firmware version
3455 * @adap: the adapter
3456 * @phy_fw_ver: return value buffer for PHY firmware version
3458 * Returns the current version of external PHY firmware on the
3461 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3466 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3467 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3468 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3469 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3470 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3479 * t4_load_phy_fw - download port PHY firmware
3480 * @adap: the adapter
3481 * @win: the PCI-E Memory Window index to use for t4_memory_rw()
3482 * @win_lock: the lock to use to guard the memory copy
3483 * @phy_fw_version: function to check PHY firmware versions
3484 * @phy_fw_data: the PHY firmware image to write
3485 * @phy_fw_size: image size
3487 * Transfer the specified PHY firmware to the adapter. If a non-NULL
3488 * @phy_fw_version is supplied, then it will be used to determine if
3489 * it's necessary to perform the transfer by comparing the version
3490 * of any existing adapter PHY firmware with that of the passed in
3491 * PHY firmware image. If @win_lock is non-NULL then it will be used
3492 * around the call to t4_memory_rw() which transfers the PHY firmware
3495 * A negative error number will be returned if an error occurs. If
3496 * version number support is available and there's no need to upgrade
3497 * the firmware, 0 will be returned. If firmware is successfully
3498 * transferred to the adapter, 1 will be retured.
3500 * NOTE: some adapters only have local RAM to store the PHY firmware. As
3501 * a result, a RESET of the adapter would cause that RAM to lose its
3502 * contents. Thus, loading PHY firmware on such adapters must happen
3503 * after any FW_RESET_CMDs ...
3505 int t4_load_phy_fw(struct adapter *adap,
3506 int win, spinlock_t *win_lock,
3507 int (*phy_fw_version)(const u8 *, size_t),
3508 const u8 *phy_fw_data, size_t phy_fw_size)
3510 unsigned long mtype = 0, maddr = 0;
3512 int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3515 /* If we have version number support, then check to see if the adapter
3516 * already has up-to-date PHY firmware loaded.
3518 if (phy_fw_version) {
3519 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3520 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3524 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3525 CH_WARN(adap, "PHY Firmware already up-to-date, "
3526 "version %#x\n", cur_phy_fw_ver);
3531 /* Ask the firmware where it wants us to copy the PHY firmware image.
3532 * The size of the file requires a special version of the READ coommand
3533 * which will pass the file size via the values field in PARAMS_CMD and
3534 * retrieve the return value from firmware and place it in the same
3537 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3538 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3539 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3540 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3542 ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3543 ¶m, &val, 1, true);
3547 maddr = (val & 0xff) << 16;
3549 /* Copy the supplied PHY Firmware image to the adapter memory location
3550 * allocated by the adapter firmware.
3553 spin_lock_bh(win_lock);
3554 ret = t4_memory_rw(adap, win, mtype, maddr,
3555 phy_fw_size, (__be32 *)phy_fw_data,
3558 spin_unlock_bh(win_lock);
3562 /* Tell the firmware that the PHY firmware image has been written to
3563 * RAM and it can now start copying it over to the PHYs. The chip
3564 * firmware will RESET the affected PHYs as part of this operation
3565 * leaving them running the new PHY firmware image.
3567 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3568 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3569 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3570 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3571 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3572 ¶m, &val, 30000);
3574 /* If we have version number support, then check to see that the new
3575 * firmware got loaded properly.
3577 if (phy_fw_version) {
3578 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3582 if (cur_phy_fw_ver != new_phy_fw_vers) {
3583 CH_WARN(adap, "PHY Firmware did not update: "
3584 "version on adapter %#x, "
3585 "version flashed %#x\n",
3586 cur_phy_fw_ver, new_phy_fw_vers);
3595 * t4_fwcache - firmware cache operation
3596 * @adap: the adapter
3597 * @op : the operation (flush or flush and invalidate)
3599 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3601 struct fw_params_cmd c;
3603 memset(&c, 0, sizeof(c));
3605 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3606 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3607 FW_PARAMS_CMD_PFN_V(adap->pf) |
3608 FW_PARAMS_CMD_VFN_V(0));
3609 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3611 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3612 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3613 c.param[0].val = (__force __be32)op;
3615 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3618 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3619 unsigned int *pif_req_wrptr,
3620 unsigned int *pif_rsp_wrptr)
3623 u32 cfg, val, req, rsp;
3625 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3626 if (cfg & LADBGEN_F)
3627 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3629 val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3630 req = POLADBGWRPTR_G(val);
3631 rsp = PILADBGWRPTR_G(val);
3633 *pif_req_wrptr = req;
3635 *pif_rsp_wrptr = rsp;
3637 for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3638 for (j = 0; j < 6; j++) {
3639 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3640 PILADBGRDPTR_V(rsp));
3641 *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3642 *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3646 req = (req + 2) & POLADBGRDPTR_M;
3647 rsp = (rsp + 2) & PILADBGRDPTR_M;
3649 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3652 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3657 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3658 if (cfg & LADBGEN_F)
3659 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3661 for (i = 0; i < CIM_MALA_SIZE; i++) {
3662 for (j = 0; j < 5; j++) {
3664 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3665 PILADBGRDPTR_V(idx));
3666 *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3667 *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3670 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3673 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3677 for (i = 0; i < 8; i++) {
3678 u32 *p = la_buf + i;
3680 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3681 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3682 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3683 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3684 *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3688 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
3689 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_25G | \
3690 FW_PORT_CAP_SPEED_40G | FW_PORT_CAP_SPEED_100G | \
3694 * t4_link_l1cfg - apply link configuration to MAC/PHY
3695 * @phy: the PHY to setup
3696 * @mac: the MAC to setup
3697 * @lc: the requested link configuration
3699 * Set up a port's MAC and PHY according to a desired link configuration.
3700 * - If the PHY can auto-negotiate first decide what to advertise, then
3701 * enable/disable auto-negotiation as desired, and reset.
3702 * - If the PHY does not auto-negotiate just reset it.
3703 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3704 * otherwise do it later based on the outcome of auto-negotiation.
3706 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
3707 struct link_config *lc)
3709 struct fw_port_cmd c;
3710 unsigned int mdi = FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO);
3711 unsigned int fc = 0, fec = 0, fw_fec = 0;
3714 if (lc->requested_fc & PAUSE_RX)
3715 fc |= FW_PORT_CAP_FC_RX;
3716 if (lc->requested_fc & PAUSE_TX)
3717 fc |= FW_PORT_CAP_FC_TX;
3719 fec = lc->requested_fec & FEC_AUTO ? lc->auto_fec : lc->requested_fec;
3722 fw_fec |= FW_PORT_CAP_FEC_RS;
3723 if (fec & FEC_BASER_RS)
3724 fw_fec |= FW_PORT_CAP_FEC_BASER_RS;
3726 memset(&c, 0, sizeof(c));
3727 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3728 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3729 FW_PORT_CMD_PORTID_V(port));
3731 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3734 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
3735 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
3737 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3738 } else if (lc->autoneg == AUTONEG_DISABLE) {
3739 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc |
3741 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3743 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc |
3746 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3750 * t4_restart_aneg - restart autonegotiation
3751 * @adap: the adapter
3752 * @mbox: mbox to use for the FW command
3753 * @port: the port id
3755 * Restarts autonegotiation for the selected port.
3757 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
3759 struct fw_port_cmd c;
3761 memset(&c, 0, sizeof(c));
3762 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3763 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3764 FW_PORT_CMD_PORTID_V(port));
3766 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3768 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
3769 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3772 typedef void (*int_handler_t)(struct adapter *adap);
3775 unsigned int mask; /* bits to check in interrupt status */
3776 const char *msg; /* message to print or NULL */
3777 short stat_idx; /* stat counter to increment or -1 */
3778 unsigned short fatal; /* whether the condition reported is fatal */
3779 int_handler_t int_handler; /* platform-specific int handler */
3783 * t4_handle_intr_status - table driven interrupt handler
3784 * @adapter: the adapter that generated the interrupt
3785 * @reg: the interrupt status register to process
3786 * @acts: table of interrupt actions
3788 * A table driven interrupt handler that applies a set of masks to an
3789 * interrupt status word and performs the corresponding actions if the
3790 * interrupts described by the mask have occurred. The actions include
3791 * optionally emitting a warning or alert message. The table is terminated
3792 * by an entry specifying mask 0. Returns the number of fatal interrupt
3795 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
3796 const struct intr_info *acts)
3799 unsigned int mask = 0;
3800 unsigned int status = t4_read_reg(adapter, reg);
3802 for ( ; acts->mask; ++acts) {
3803 if (!(status & acts->mask))
3807 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3808 status & acts->mask);
3809 } else if (acts->msg && printk_ratelimit())
3810 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3811 status & acts->mask);
3812 if (acts->int_handler)
3813 acts->int_handler(adapter);
3817 if (status) /* clear processed interrupts */
3818 t4_write_reg(adapter, reg, status);
3823 * Interrupt handler for the PCIE module.
3825 static void pcie_intr_handler(struct adapter *adapter)
3827 static const struct intr_info sysbus_intr_info[] = {
3828 { RNPP_F, "RXNP array parity error", -1, 1 },
3829 { RPCP_F, "RXPC array parity error", -1, 1 },
3830 { RCIP_F, "RXCIF array parity error", -1, 1 },
3831 { RCCP_F, "Rx completions control array parity error", -1, 1 },
3832 { RFTP_F, "RXFT array parity error", -1, 1 },
3835 static const struct intr_info pcie_port_intr_info[] = {
3836 { TPCP_F, "TXPC array parity error", -1, 1 },
3837 { TNPP_F, "TXNP array parity error", -1, 1 },
3838 { TFTP_F, "TXFT array parity error", -1, 1 },
3839 { TCAP_F, "TXCA array parity error", -1, 1 },
3840 { TCIP_F, "TXCIF array parity error", -1, 1 },
3841 { RCAP_F, "RXCA array parity error", -1, 1 },
3842 { OTDD_F, "outbound request TLP discarded", -1, 1 },
3843 { RDPE_F, "Rx data parity error", -1, 1 },
3844 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
3847 static const struct intr_info pcie_intr_info[] = {
3848 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
3849 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
3850 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
3851 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3852 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3853 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3854 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3855 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
3856 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
3857 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3858 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
3859 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3860 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3861 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
3862 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3863 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3864 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
3865 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3866 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3867 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3868 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3869 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
3870 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
3871 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3872 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
3873 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
3874 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
3875 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
3876 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
3877 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
3882 static struct intr_info t5_pcie_intr_info[] = {
3883 { MSTGRPPERR_F, "Master Response Read Queue parity error",
3885 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
3886 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
3887 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3888 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3889 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3890 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3891 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
3893 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
3895 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3896 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
3897 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3898 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3899 { DREQWRPERR_F, "PCI DMA channel write request parity error",
3901 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3902 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3903 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
3904 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3905 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3906 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3907 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3908 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
3909 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
3910 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3911 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
3913 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
3915 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
3916 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
3917 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
3918 { READRSPERR_F, "Outbound read error", -1, 0 },
3924 if (is_t4(adapter->params.chip))
3925 fat = t4_handle_intr_status(adapter,
3926 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
3928 t4_handle_intr_status(adapter,
3929 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
3930 pcie_port_intr_info) +
3931 t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3934 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3938 t4_fatal_err(adapter);
3942 * TP interrupt handler.
3944 static void tp_intr_handler(struct adapter *adapter)
3946 static const struct intr_info tp_intr_info[] = {
3947 { 0x3fffffff, "TP parity error", -1, 1 },
3948 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
3952 if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
3953 t4_fatal_err(adapter);
3957 * SGE interrupt handler.
3959 static void sge_intr_handler(struct adapter *adapter)
3964 static const struct intr_info sge_intr_info[] = {
3965 { ERR_CPL_EXCEED_IQE_SIZE_F,
3966 "SGE received CPL exceeding IQE size", -1, 1 },
3967 { ERR_INVALID_CIDX_INC_F,
3968 "SGE GTS CIDX increment too large", -1, 0 },
3969 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
3970 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
3971 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
3972 "SGE IQID > 1023 received CPL for FL", -1, 0 },
3973 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
3975 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
3977 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
3979 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
3981 { ERR_ING_CTXT_PRIO_F,
3982 "SGE too many priority ingress contexts", -1, 0 },
3983 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
3984 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
3988 static struct intr_info t4t5_sge_intr_info[] = {
3989 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
3990 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
3991 { ERR_EGR_CTXT_PRIO_F,
3992 "SGE too many priority egress contexts", -1, 0 },
3996 v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
3997 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
3999 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
4000 (unsigned long long)v);
4001 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);
4002 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
4005 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
4006 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4007 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
4008 t4t5_sge_intr_info);
4010 err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
4011 if (err & ERROR_QID_VALID_F) {
4012 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
4014 if (err & UNCAPTURED_ERROR_F)
4015 dev_err(adapter->pdev_dev,
4016 "SGE UNCAPTURED_ERROR set (clearing)\n");
4017 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
4018 UNCAPTURED_ERROR_F);
4022 t4_fatal_err(adapter);
4025 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
4026 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
4027 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
4028 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
4031 * CIM interrupt handler.
4033 static void cim_intr_handler(struct adapter *adapter)
4035 static const struct intr_info cim_intr_info[] = {
4036 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
4037 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
4038 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
4039 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
4040 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
4041 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
4042 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
4043 { TIMER0INT_F, "CIM TIMER0 interrupt", -1, 1 },
4046 static const struct intr_info cim_upintr_info[] = {
4047 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
4048 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
4049 { ILLWRINT_F, "CIM illegal write", -1, 1 },
4050 { ILLRDINT_F, "CIM illegal read", -1, 1 },
4051 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
4052 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
4053 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
4054 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
4055 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
4056 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
4057 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
4058 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
4059 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
4060 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
4061 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
4062 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
4063 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
4064 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
4065 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
4066 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
4067 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
4068 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
4069 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
4070 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
4071 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
4072 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
4073 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
4074 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
4081 fw_err = t4_read_reg(adapter, PCIE_FW_A);
4082 if (fw_err & PCIE_FW_ERR_F)
4083 t4_report_fw_error(adapter);
4085 /* When the Firmware detects an internal error which normally
4086 * wouldn't raise a Host Interrupt, it forces a CIM Timer0 interrupt
4087 * in order to make sure the Host sees the Firmware Crash. So
4088 * if we have a Timer0 interrupt and don't see a Firmware Crash,
4089 * ignore the Timer0 interrupt.
4092 val = t4_read_reg(adapter, CIM_HOST_INT_CAUSE_A);
4093 if (val & TIMER0INT_F)
4094 if (!(fw_err & PCIE_FW_ERR_F) ||
4095 (PCIE_FW_EVAL_G(fw_err) != PCIE_FW_EVAL_CRASH))
4096 t4_write_reg(adapter, CIM_HOST_INT_CAUSE_A,
4099 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
4101 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
4104 t4_fatal_err(adapter);
4108 * ULP RX interrupt handler.
4110 static void ulprx_intr_handler(struct adapter *adapter)
4112 static const struct intr_info ulprx_intr_info[] = {
4113 { 0x1800000, "ULPRX context error", -1, 1 },
4114 { 0x7fffff, "ULPRX parity error", -1, 1 },
4118 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
4119 t4_fatal_err(adapter);
4123 * ULP TX interrupt handler.
4125 static void ulptx_intr_handler(struct adapter *adapter)
4127 static const struct intr_info ulptx_intr_info[] = {
4128 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
4130 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
4132 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
4134 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
4136 { 0xfffffff, "ULPTX parity error", -1, 1 },
4140 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4141 t4_fatal_err(adapter);
4145 * PM TX interrupt handler.
4147 static void pmtx_intr_handler(struct adapter *adapter)
4149 static const struct intr_info pmtx_intr_info[] = {
4150 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4151 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4152 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4153 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4154 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4155 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4156 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4158 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4159 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4163 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4164 t4_fatal_err(adapter);
4168 * PM RX interrupt handler.
4170 static void pmrx_intr_handler(struct adapter *adapter)
4172 static const struct intr_info pmrx_intr_info[] = {
4173 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4174 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4175 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4176 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4178 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4179 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4183 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4184 t4_fatal_err(adapter);
4188 * CPL switch interrupt handler.
4190 static void cplsw_intr_handler(struct adapter *adapter)
4192 static const struct intr_info cplsw_intr_info[] = {
4193 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4194 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4195 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4196 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4197 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4198 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4202 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4203 t4_fatal_err(adapter);
4207 * LE interrupt handler.
4209 static void le_intr_handler(struct adapter *adap)
4211 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4212 static const struct intr_info le_intr_info[] = {
4213 { LIPMISS_F, "LE LIP miss", -1, 0 },
4214 { LIP0_F, "LE 0 LIP error", -1, 0 },
4215 { PARITYERR_F, "LE parity error", -1, 1 },
4216 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4217 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4221 static struct intr_info t6_le_intr_info[] = {
4222 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4223 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4224 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4225 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4226 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4230 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4231 (chip <= CHELSIO_T5) ?
4232 le_intr_info : t6_le_intr_info))
4237 * MPS interrupt handler.
4239 static void mps_intr_handler(struct adapter *adapter)
4241 static const struct intr_info mps_rx_intr_info[] = {
4242 { 0xffffff, "MPS Rx parity error", -1, 1 },
4245 static const struct intr_info mps_tx_intr_info[] = {
4246 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4247 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4248 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4250 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4252 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4253 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4254 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4257 static const struct intr_info mps_trc_intr_info[] = {
4258 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4259 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4261 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4264 static const struct intr_info mps_stat_sram_intr_info[] = {
4265 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4268 static const struct intr_info mps_stat_tx_intr_info[] = {
4269 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4272 static const struct intr_info mps_stat_rx_intr_info[] = {
4273 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4276 static const struct intr_info mps_cls_intr_info[] = {
4277 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4278 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4279 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4285 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4287 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4289 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4290 mps_trc_intr_info) +
4291 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4292 mps_stat_sram_intr_info) +
4293 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4294 mps_stat_tx_intr_info) +
4295 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4296 mps_stat_rx_intr_info) +
4297 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4300 t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4301 t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */
4303 t4_fatal_err(adapter);
4306 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4310 * EDC/MC interrupt handler.
4312 static void mem_intr_handler(struct adapter *adapter, int idx)
4314 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4316 unsigned int addr, cnt_addr, v;
4318 if (idx <= MEM_EDC1) {
4319 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4320 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4321 } else if (idx == MEM_MC) {
4322 if (is_t4(adapter->params.chip)) {
4323 addr = MC_INT_CAUSE_A;
4324 cnt_addr = MC_ECC_STATUS_A;
4326 addr = MC_P_INT_CAUSE_A;
4327 cnt_addr = MC_P_ECC_STATUS_A;
4330 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4331 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4334 v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4335 if (v & PERR_INT_CAUSE_F)
4336 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4338 if (v & ECC_CE_INT_CAUSE_F) {
4339 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4341 t4_edc_err_read(adapter, idx);
4343 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4344 if (printk_ratelimit())
4345 dev_warn(adapter->pdev_dev,
4346 "%u %s correctable ECC data error%s\n",
4347 cnt, name[idx], cnt > 1 ? "s" : "");
4349 if (v & ECC_UE_INT_CAUSE_F)
4350 dev_alert(adapter->pdev_dev,
4351 "%s uncorrectable ECC data error\n", name[idx]);
4353 t4_write_reg(adapter, addr, v);
4354 if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4355 t4_fatal_err(adapter);
4359 * MA interrupt handler.
4361 static void ma_intr_handler(struct adapter *adap)
4363 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4365 if (status & MEM_PERR_INT_CAUSE_F) {
4366 dev_alert(adap->pdev_dev,
4367 "MA parity error, parity status %#x\n",
4368 t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4369 if (is_t5(adap->params.chip))
4370 dev_alert(adap->pdev_dev,
4371 "MA parity error, parity status %#x\n",
4373 MA_PARITY_ERROR_STATUS2_A));
4375 if (status & MEM_WRAP_INT_CAUSE_F) {
4376 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4377 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4378 "client %u to address %#x\n",
4379 MEM_WRAP_CLIENT_NUM_G(v),
4380 MEM_WRAP_ADDRESS_G(v) << 4);
4382 t4_write_reg(adap, MA_INT_CAUSE_A, status);
4387 * SMB interrupt handler.
4389 static void smb_intr_handler(struct adapter *adap)
4391 static const struct intr_info smb_intr_info[] = {
4392 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4393 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4394 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4398 if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4403 * NC-SI interrupt handler.
4405 static void ncsi_intr_handler(struct adapter *adap)
4407 static const struct intr_info ncsi_intr_info[] = {
4408 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4409 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4410 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4411 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4415 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4420 * XGMAC interrupt handler.
4422 static void xgmac_intr_handler(struct adapter *adap, int port)
4424 u32 v, int_cause_reg;
4426 if (is_t4(adap->params.chip))
4427 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4429 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4431 v = t4_read_reg(adap, int_cause_reg);
4433 v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4437 if (v & TXFIFO_PRTY_ERR_F)
4438 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4440 if (v & RXFIFO_PRTY_ERR_F)
4441 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4443 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4448 * PL interrupt handler.
4450 static void pl_intr_handler(struct adapter *adap)
4452 static const struct intr_info pl_intr_info[] = {
4453 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4454 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4458 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
4462 #define PF_INTR_MASK (PFSW_F)
4463 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
4464 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
4465 CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
4468 * t4_slow_intr_handler - control path interrupt handler
4469 * @adapter: the adapter
4471 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
4472 * The designation 'slow' is because it involves register reads, while
4473 * data interrupts typically don't involve any MMIOs.
4475 int t4_slow_intr_handler(struct adapter *adapter)
4477 u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
4479 if (!(cause & GLBL_INTR_MASK))
4482 cim_intr_handler(adapter);
4484 mps_intr_handler(adapter);
4486 ncsi_intr_handler(adapter);
4488 pl_intr_handler(adapter);
4490 smb_intr_handler(adapter);
4491 if (cause & XGMAC0_F)
4492 xgmac_intr_handler(adapter, 0);
4493 if (cause & XGMAC1_F)
4494 xgmac_intr_handler(adapter, 1);
4495 if (cause & XGMAC_KR0_F)
4496 xgmac_intr_handler(adapter, 2);
4497 if (cause & XGMAC_KR1_F)
4498 xgmac_intr_handler(adapter, 3);
4500 pcie_intr_handler(adapter);
4502 mem_intr_handler(adapter, MEM_MC);
4503 if (is_t5(adapter->params.chip) && (cause & MC1_F))
4504 mem_intr_handler(adapter, MEM_MC1);
4506 mem_intr_handler(adapter, MEM_EDC0);
4508 mem_intr_handler(adapter, MEM_EDC1);
4510 le_intr_handler(adapter);
4512 tp_intr_handler(adapter);
4514 ma_intr_handler(adapter);
4515 if (cause & PM_TX_F)
4516 pmtx_intr_handler(adapter);
4517 if (cause & PM_RX_F)
4518 pmrx_intr_handler(adapter);
4519 if (cause & ULP_RX_F)
4520 ulprx_intr_handler(adapter);
4521 if (cause & CPL_SWITCH_F)
4522 cplsw_intr_handler(adapter);
4524 sge_intr_handler(adapter);
4525 if (cause & ULP_TX_F)
4526 ulptx_intr_handler(adapter);
4528 /* Clear the interrupts just processed for which we are the master. */
4529 t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK);
4530 (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
4535 * t4_intr_enable - enable interrupts
4536 * @adapter: the adapter whose interrupts should be enabled
4538 * Enable PF-specific interrupts for the calling function and the top-level
4539 * interrupt concentrator for global interrupts. Interrupts are already
4540 * enabled at each module, here we just enable the roots of the interrupt
4543 * Note: this function should be called only when the driver manages
4544 * non PF-specific interrupts from the various HW modules. Only one PCI
4545 * function at a time should be doing this.
4547 void t4_intr_enable(struct adapter *adapter)
4550 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4551 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4552 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4554 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4555 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
4556 t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
4557 ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
4558 ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
4559 ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
4560 ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
4561 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
4562 DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
4563 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
4564 t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
4568 * t4_intr_disable - disable interrupts
4569 * @adapter: the adapter whose interrupts should be disabled
4571 * Disable interrupts. We only disable the top-level interrupt
4572 * concentrators. The caller must be a PCI function managing global
4575 void t4_intr_disable(struct adapter *adapter)
4579 if (pci_channel_offline(adapter->pdev))
4582 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4583 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4584 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4586 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
4587 t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
4591 * t4_config_rss_range - configure a portion of the RSS mapping table
4592 * @adapter: the adapter
4593 * @mbox: mbox to use for the FW command
4594 * @viid: virtual interface whose RSS subtable is to be written
4595 * @start: start entry in the table to write
4596 * @n: how many table entries to write
4597 * @rspq: values for the response queue lookup table
4598 * @nrspq: number of values in @rspq
4600 * Programs the selected part of the VI's RSS mapping table with the
4601 * provided values. If @nrspq < @n the supplied values are used repeatedly
4602 * until the full table range is populated.
4604 * The caller must ensure the values in @rspq are in the range allowed for
4607 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
4608 int start, int n, const u16 *rspq, unsigned int nrspq)
4611 const u16 *rsp = rspq;
4612 const u16 *rsp_end = rspq + nrspq;
4613 struct fw_rss_ind_tbl_cmd cmd;
4615 memset(&cmd, 0, sizeof(cmd));
4616 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
4617 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4618 FW_RSS_IND_TBL_CMD_VIID_V(viid));
4619 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
4621 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
4623 int nq = min(n, 32);
4624 __be32 *qp = &cmd.iq0_to_iq2;
4626 cmd.niqid = cpu_to_be16(nq);
4627 cmd.startidx = cpu_to_be16(start);
4635 v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
4636 if (++rsp >= rsp_end)
4638 v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
4639 if (++rsp >= rsp_end)
4641 v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
4642 if (++rsp >= rsp_end)
4645 *qp++ = cpu_to_be32(v);
4649 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4657 * t4_config_glbl_rss - configure the global RSS mode
4658 * @adapter: the adapter
4659 * @mbox: mbox to use for the FW command
4660 * @mode: global RSS mode
4661 * @flags: mode-specific flags
4663 * Sets the global RSS mode.
4665 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
4668 struct fw_rss_glb_config_cmd c;
4670 memset(&c, 0, sizeof(c));
4671 c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
4672 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
4673 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4674 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
4675 c.u.manual.mode_pkd =
4676 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4677 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
4678 c.u.basicvirtual.mode_pkd =
4679 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4680 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
4683 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4687 * t4_config_vi_rss - configure per VI RSS settings
4688 * @adapter: the adapter
4689 * @mbox: mbox to use for the FW command
4692 * @defq: id of the default RSS queue for the VI.
4694 * Configures VI-specific RSS properties.
4696 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
4697 unsigned int flags, unsigned int defq)
4699 struct fw_rss_vi_config_cmd c;
4701 memset(&c, 0, sizeof(c));
4702 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
4703 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4704 FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
4705 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4706 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
4707 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
4708 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4711 /* Read an RSS table row */
4712 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
4714 t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
4715 return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
4720 * t4_read_rss - read the contents of the RSS mapping table
4721 * @adapter: the adapter
4722 * @map: holds the contents of the RSS mapping table
4724 * Reads the contents of the RSS hash->queue mapping table.
4726 int t4_read_rss(struct adapter *adapter, u16 *map)
4731 for (i = 0; i < RSS_NENTRIES / 2; ++i) {
4732 ret = rd_rss_row(adapter, i, &val);
4735 *map++ = LKPTBLQUEUE0_G(val);
4736 *map++ = LKPTBLQUEUE1_G(val);
4741 static unsigned int t4_use_ldst(struct adapter *adap)
4743 return (adap->flags & FW_OK) || !adap->use_bd;
4747 * t4_fw_tp_pio_rw - Access TP PIO through LDST
4748 * @adap: the adapter
4749 * @vals: where the indirect register values are stored/written
4750 * @nregs: how many indirect registers to read/write
4751 * @start_idx: index of first indirect register to read/write
4752 * @rw: Read (1) or Write (0)
4754 * Access TP PIO registers through LDST
4756 static void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
4757 unsigned int start_index, unsigned int rw)
4760 int cmd = FW_LDST_ADDRSPC_TP_PIO;
4761 struct fw_ldst_cmd c;
4763 for (i = 0 ; i < nregs; i++) {
4764 memset(&c, 0, sizeof(c));
4765 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
4767 (rw ? FW_CMD_READ_F :
4769 FW_LDST_CMD_ADDRSPACE_V(cmd));
4770 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
4772 c.u.addrval.addr = cpu_to_be32(start_index + i);
4773 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);
4774 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
4776 vals[i] = be32_to_cpu(c.u.addrval.val);
4781 * t4_read_rss_key - read the global RSS key
4782 * @adap: the adapter
4783 * @key: 10-entry array holding the 320-bit RSS key
4785 * Reads the global 320-bit RSS key.
4787 void t4_read_rss_key(struct adapter *adap, u32 *key)
4789 if (t4_use_ldst(adap))
4790 t4_fw_tp_pio_rw(adap, key, 10, TP_RSS_SECRET_KEY0_A, 1);
4792 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4793 TP_RSS_SECRET_KEY0_A);
4797 * t4_write_rss_key - program one of the RSS keys
4798 * @adap: the adapter
4799 * @key: 10-entry array holding the 320-bit RSS key
4800 * @idx: which RSS key to write
4802 * Writes one of the RSS keys with the given 320-bit value. If @idx is
4803 * 0..15 the corresponding entry in the RSS key table is written,
4804 * otherwise the global RSS key is written.
4806 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx)
4808 u8 rss_key_addr_cnt = 16;
4809 u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
4811 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
4812 * allows access to key addresses 16-63 by using KeyWrAddrX
4813 * as index[5:4](upper 2) into key table
4815 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
4816 (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
4817 rss_key_addr_cnt = 32;
4819 if (t4_use_ldst(adap))
4820 t4_fw_tp_pio_rw(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, 0);
4822 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4823 TP_RSS_SECRET_KEY0_A);
4825 if (idx >= 0 && idx < rss_key_addr_cnt) {
4826 if (rss_key_addr_cnt > 16)
4827 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4828 KEYWRADDRX_V(idx >> 4) |
4829 T6_VFWRADDR_V(idx) | KEYWREN_F);
4831 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4832 KEYWRADDR_V(idx) | KEYWREN_F);
4837 * t4_read_rss_pf_config - read PF RSS Configuration Table
4838 * @adapter: the adapter
4839 * @index: the entry in the PF RSS table to read
4840 * @valp: where to store the returned value
4842 * Reads the PF RSS Configuration Table at the specified index and returns
4843 * the value found there.
4845 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
4848 if (t4_use_ldst(adapter))
4849 t4_fw_tp_pio_rw(adapter, valp, 1,
4850 TP_RSS_PF0_CONFIG_A + index, 1);
4852 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4853 valp, 1, TP_RSS_PF0_CONFIG_A + index);
4857 * t4_read_rss_vf_config - read VF RSS Configuration Table
4858 * @adapter: the adapter
4859 * @index: the entry in the VF RSS table to read
4860 * @vfl: where to store the returned VFL
4861 * @vfh: where to store the returned VFH
4863 * Reads the VF RSS Configuration Table at the specified index and returns
4864 * the (VFL, VFH) values found there.
4866 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
4869 u32 vrt, mask, data;
4871 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
4872 mask = VFWRADDR_V(VFWRADDR_M);
4873 data = VFWRADDR_V(index);
4875 mask = T6_VFWRADDR_V(T6_VFWRADDR_M);
4876 data = T6_VFWRADDR_V(index);
4879 /* Request that the index'th VF Table values be read into VFL/VFH.
4881 vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
4882 vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
4883 vrt |= data | VFRDEN_F;
4884 t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
4886 /* Grab the VFL/VFH values ...
4888 if (t4_use_ldst(adapter)) {
4889 t4_fw_tp_pio_rw(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, 1);
4890 t4_fw_tp_pio_rw(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, 1);
4892 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4893 vfl, 1, TP_RSS_VFL_CONFIG_A);
4894 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4895 vfh, 1, TP_RSS_VFH_CONFIG_A);
4900 * t4_read_rss_pf_map - read PF RSS Map
4901 * @adapter: the adapter
4903 * Reads the PF RSS Map register and returns its value.
4905 u32 t4_read_rss_pf_map(struct adapter *adapter)
4909 if (t4_use_ldst(adapter))
4910 t4_fw_tp_pio_rw(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, 1);
4912 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4913 &pfmap, 1, TP_RSS_PF_MAP_A);
4918 * t4_read_rss_pf_mask - read PF RSS Mask
4919 * @adapter: the adapter
4921 * Reads the PF RSS Mask register and returns its value.
4923 u32 t4_read_rss_pf_mask(struct adapter *adapter)
4927 if (t4_use_ldst(adapter))
4928 t4_fw_tp_pio_rw(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, 1);
4930 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4931 &pfmask, 1, TP_RSS_PF_MSK_A);
4936 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
4937 * @adap: the adapter
4938 * @v4: holds the TCP/IP counter values
4939 * @v6: holds the TCP/IPv6 counter values
4941 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
4942 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
4944 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
4945 struct tp_tcp_stats *v6)
4947 u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
4949 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
4950 #define STAT(x) val[STAT_IDX(x)]
4951 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
4954 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4955 ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST_A);
4956 v4->tcp_out_rsts = STAT(OUT_RST);
4957 v4->tcp_in_segs = STAT64(IN_SEG);
4958 v4->tcp_out_segs = STAT64(OUT_SEG);
4959 v4->tcp_retrans_segs = STAT64(RXT_SEG);
4962 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4963 ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST_A);
4964 v6->tcp_out_rsts = STAT(OUT_RST);
4965 v6->tcp_in_segs = STAT64(IN_SEG);
4966 v6->tcp_out_segs = STAT64(OUT_SEG);
4967 v6->tcp_retrans_segs = STAT64(RXT_SEG);
4975 * t4_tp_get_err_stats - read TP's error MIB counters
4976 * @adap: the adapter
4977 * @st: holds the counter values
4979 * Returns the values of TP's error counters.
4981 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st)
4983 int nchan = adap->params.arch.nchan;
4985 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4986 st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A);
4987 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4988 st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A);
4989 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4990 st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A);
4991 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4992 st->tnl_cong_drops, nchan, TP_MIB_TNL_CNG_DROP_0_A);
4993 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4994 st->ofld_chan_drops, nchan, TP_MIB_OFD_CHN_DROP_0_A);
4995 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4996 st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A);
4997 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4998 st->ofld_vlan_drops, nchan, TP_MIB_OFD_VLN_DROP_0_A);
4999 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
5000 st->tcp6_in_errs, nchan, TP_MIB_TCP_V6IN_ERR_0_A);
5002 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
5003 &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A);
5007 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
5008 * @adap: the adapter
5009 * @st: holds the counter values
5011 * Returns the values of TP's CPL counters.
5013 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st)
5015 int nchan = adap->params.arch.nchan;
5017 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->req,
5018 nchan, TP_MIB_CPL_IN_REQ_0_A);
5019 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->rsp,
5020 nchan, TP_MIB_CPL_OUT_RSP_0_A);
5025 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5026 * @adap: the adapter
5027 * @st: holds the counter values
5029 * Returns the values of TP's RDMA counters.
5031 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st)
5033 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->rqe_dfr_pkt,
5034 2, TP_MIB_RQE_DFR_PKT_A);
5038 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5039 * @adap: the adapter
5040 * @idx: the port index
5041 * @st: holds the counter values
5043 * Returns the values of TP's FCoE counters for the selected port.
5045 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
5046 struct tp_fcoe_stats *st)
5050 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_ddp,
5051 1, TP_MIB_FCOE_DDP_0_A + idx);
5052 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_drop,
5053 1, TP_MIB_FCOE_DROP_0_A + idx);
5054 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
5055 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx);
5056 st->octets_ddp = ((u64)val[0] << 32) | val[1];
5060 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5061 * @adap: the adapter
5062 * @st: holds the counter values
5064 * Returns the values of TP's counters for non-TCP directly-placed packets.
5066 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st)
5070 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 4,
5072 st->frames = val[0];
5074 st->octets = ((u64)val[2] << 32) | val[3];
5078 * t4_read_mtu_tbl - returns the values in the HW path MTU table
5079 * @adap: the adapter
5080 * @mtus: where to store the MTU values
5081 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
5083 * Reads the HW path MTU table.
5085 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
5090 for (i = 0; i < NMTUS; ++i) {
5091 t4_write_reg(adap, TP_MTU_TABLE_A,
5092 MTUINDEX_V(0xff) | MTUVALUE_V(i));
5093 v = t4_read_reg(adap, TP_MTU_TABLE_A);
5094 mtus[i] = MTUVALUE_G(v);
5096 mtu_log[i] = MTUWIDTH_G(v);
5101 * t4_read_cong_tbl - reads the congestion control table
5102 * @adap: the adapter
5103 * @incr: where to store the alpha values
5105 * Reads the additive increments programmed into the HW congestion
5108 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5110 unsigned int mtu, w;
5112 for (mtu = 0; mtu < NMTUS; ++mtu)
5113 for (w = 0; w < NCCTRL_WIN; ++w) {
5114 t4_write_reg(adap, TP_CCTRL_TABLE_A,
5115 ROWINDEX_V(0xffff) | (mtu << 5) | w);
5116 incr[mtu][w] = (u16)t4_read_reg(adap,
5117 TP_CCTRL_TABLE_A) & 0x1fff;
5122 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5123 * @adap: the adapter
5124 * @addr: the indirect TP register address
5125 * @mask: specifies the field within the register to modify
5126 * @val: new value for the field
5128 * Sets a field of an indirect TP register to the given value.
5130 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5131 unsigned int mask, unsigned int val)
5133 t4_write_reg(adap, TP_PIO_ADDR_A, addr);
5134 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5135 t4_write_reg(adap, TP_PIO_DATA_A, val);
5139 * init_cong_ctrl - initialize congestion control parameters
5140 * @a: the alpha values for congestion control
5141 * @b: the beta values for congestion control
5143 * Initialize the congestion control parameters.
5145 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5147 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5172 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5175 b[13] = b[14] = b[15] = b[16] = 3;
5176 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5177 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5182 /* The minimum additive increment value for the congestion control table */
5183 #define CC_MIN_INCR 2U
5186 * t4_load_mtus - write the MTU and congestion control HW tables
5187 * @adap: the adapter
5188 * @mtus: the values for the MTU table
5189 * @alpha: the values for the congestion control alpha parameter
5190 * @beta: the values for the congestion control beta parameter
5192 * Write the HW MTU table with the supplied MTUs and the high-speed
5193 * congestion control table with the supplied alpha, beta, and MTUs.
5194 * We write the two tables together because the additive increments
5195 * depend on the MTUs.
5197 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5198 const unsigned short *alpha, const unsigned short *beta)
5200 static const unsigned int avg_pkts[NCCTRL_WIN] = {
5201 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5202 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5203 28672, 40960, 57344, 81920, 114688, 163840, 229376
5208 for (i = 0; i < NMTUS; ++i) {
5209 unsigned int mtu = mtus[i];
5210 unsigned int log2 = fls(mtu);
5212 if (!(mtu & ((1 << log2) >> 2))) /* round */
5214 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5215 MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5217 for (w = 0; w < NCCTRL_WIN; ++w) {
5220 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5223 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5224 (w << 16) | (beta[w] << 13) | inc);
5229 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5230 * clocks. The formula is
5232 * bytes/s = bytes256 * 256 * ClkFreq / 4096
5234 * which is equivalent to
5236 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5238 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5240 u64 v = bytes256 * adap->params.vpd.cclk;
5242 return v * 62 + v / 2;
5246 * t4_get_chan_txrate - get the current per channel Tx rates
5247 * @adap: the adapter
5248 * @nic_rate: rates for NIC traffic
5249 * @ofld_rate: rates for offloaded traffic
5251 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
5254 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5258 v = t4_read_reg(adap, TP_TX_TRATE_A);
5259 nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5260 nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5261 if (adap->params.arch.nchan == NCHAN) {
5262 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5263 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5266 v = t4_read_reg(adap, TP_TX_ORATE_A);
5267 ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5268 ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5269 if (adap->params.arch.nchan == NCHAN) {
5270 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5271 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5276 * t4_set_trace_filter - configure one of the tracing filters
5277 * @adap: the adapter
5278 * @tp: the desired trace filter parameters
5279 * @idx: which filter to configure
5280 * @enable: whether to enable or disable the filter
5282 * Configures one of the tracing filters available in HW. If @enable is
5283 * %0 @tp is not examined and may be %NULL. The user is responsible to
5284 * set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5286 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5287 int idx, int enable)
5289 int i, ofst = idx * 4;
5290 u32 data_reg, mask_reg, cfg;
5291 u32 multitrc = TRCMULTIFILTER_F;
5294 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5298 cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5299 if (cfg & TRCMULTIFILTER_F) {
5300 /* If multiple tracers are enabled, then maximum
5301 * capture size is 2.5KB (FIFO size of a single channel)
5302 * minus 2 flits for CPL_TRACE_PKT header.
5304 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5307 /* If multiple tracers are disabled, to avoid deadlocks
5308 * maximum packet capture size of 9600 bytes is recommended.
5309 * Also in this mode, only trace0 can be enabled and running.
5312 if (tp->snap_len > 9600 || idx)
5316 if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5317 tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5318 tp->min_len > TFMINPKTSIZE_M)
5321 /* stop the tracer we'll be changing */
5322 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5324 idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5325 data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5326 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5328 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5329 t4_write_reg(adap, data_reg, tp->data[i]);
5330 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5332 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
5333 TFCAPTUREMAX_V(tp->snap_len) |
5334 TFMINPKTSIZE_V(tp->min_len));
5335 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
5336 TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
5337 (is_t4(adap->params.chip) ?
5338 TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
5339 T5_TFPORT_V(tp->port) | T5_TFEN_F |
5340 T5_TFINVERTMATCH_V(tp->invert)));
5346 * t4_get_trace_filter - query one of the tracing filters
5347 * @adap: the adapter
5348 * @tp: the current trace filter parameters
5349 * @idx: which trace filter to query
5350 * @enabled: non-zero if the filter is enabled
5352 * Returns the current settings of one of the HW tracing filters.
5354 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5358 int i, ofst = idx * 4;
5359 u32 data_reg, mask_reg;
5361 ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
5362 ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
5364 if (is_t4(adap->params.chip)) {
5365 *enabled = !!(ctla & TFEN_F);
5366 tp->port = TFPORT_G(ctla);
5367 tp->invert = !!(ctla & TFINVERTMATCH_F);
5369 *enabled = !!(ctla & T5_TFEN_F);
5370 tp->port = T5_TFPORT_G(ctla);
5371 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
5373 tp->snap_len = TFCAPTUREMAX_G(ctlb);
5374 tp->min_len = TFMINPKTSIZE_G(ctlb);
5375 tp->skip_ofst = TFOFFSET_G(ctla);
5376 tp->skip_len = TFLENGTH_G(ctla);
5378 ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
5379 data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
5380 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
5382 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5383 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5384 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5389 * t4_pmtx_get_stats - returns the HW stats from PMTX
5390 * @adap: the adapter
5391 * @cnt: where to store the count statistics
5392 * @cycles: where to store the cycle statistics
5394 * Returns performance statistics from PMTX.
5396 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5401 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5402 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
5403 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
5404 if (is_t4(adap->params.chip)) {
5405 cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
5407 t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
5408 PM_TX_DBG_DATA_A, data, 2,
5409 PM_TX_DBG_STAT_MSB_A);
5410 cycles[i] = (((u64)data[0] << 32) | data[1]);
5416 * t4_pmrx_get_stats - returns the HW stats from PMRX
5417 * @adap: the adapter
5418 * @cnt: where to store the count statistics
5419 * @cycles: where to store the cycle statistics
5421 * Returns performance statistics from PMRX.
5423 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5428 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5429 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
5430 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
5431 if (is_t4(adap->params.chip)) {
5432 cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
5434 t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
5435 PM_RX_DBG_DATA_A, data, 2,
5436 PM_RX_DBG_STAT_MSB_A);
5437 cycles[i] = (((u64)data[0] << 32) | data[1]);
5443 * compute_mps_bg_map - compute the MPS Buffer Group Map for a Port
5444 * @adap: the adapter
5445 * @pidx: the port index
5447 * Computes and returns a bitmap indicating which MPS buffer groups are
5448 * associated with the given Port. Bit i is set if buffer group i is
5451 static inline unsigned int compute_mps_bg_map(struct adapter *adapter,
5454 unsigned int chip_version, nports;
5456 chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
5457 nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
5459 switch (chip_version) {
5464 case 2: return 3 << (2 * pidx);
5465 case 4: return 1 << pidx;
5471 case 2: return 1 << (2 * pidx);
5476 dev_err(adapter->pdev_dev, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
5477 chip_version, nports);
5483 * t4_get_mps_bg_map - return the buffer groups associated with a port
5484 * @adapter: the adapter
5485 * @pidx: the port index
5487 * Returns a bitmap indicating which MPS buffer groups are associated
5488 * with the given Port. Bit i is set if buffer group i is used by the
5491 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx)
5494 unsigned int nports;
5496 nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
5497 if (pidx >= nports) {
5498 CH_WARN(adapter, "MPS Port Index %d >= Nports %d\n",
5503 /* If we've already retrieved/computed this, just return the result.
5505 mps_bg_map = adapter->params.mps_bg_map;
5506 if (mps_bg_map[pidx])
5507 return mps_bg_map[pidx];
5509 /* Newer Firmware can tell us what the MPS Buffer Group Map is.
5510 * If we're talking to such Firmware, let it tell us. If the new
5511 * API isn't supported, revert back to old hardcoded way. The value
5512 * obtained from Firmware is encoded in below format:
5514 * val = (( MPSBGMAP[Port 3] << 24 ) |
5515 * ( MPSBGMAP[Port 2] << 16 ) |
5516 * ( MPSBGMAP[Port 1] << 8 ) |
5517 * ( MPSBGMAP[Port 0] << 0 ))
5519 if (adapter->flags & FW_OK) {
5523 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
5524 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_MPSBGMAP));
5525 ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf,
5526 0, 1, ¶m, &val);
5530 /* Store the BG Map for all of the Ports in order to
5531 * avoid more calls to the Firmware in the future.
5533 for (p = 0; p < MAX_NPORTS; p++, val >>= 8)
5534 mps_bg_map[p] = val & 0xff;
5536 return mps_bg_map[pidx];
5540 /* Either we're not talking to the Firmware or we're dealing with
5541 * older Firmware which doesn't support the new API to get the MPS
5542 * Buffer Group Map. Fall back to computing it ourselves.
5544 mps_bg_map[pidx] = compute_mps_bg_map(adapter, pidx);
5545 return mps_bg_map[pidx];
5549 * t4_get_tp_ch_map - return TP ingress channels associated with a port
5550 * @adapter: the adapter
5551 * @pidx: the port index
5553 * Returns a bitmap indicating which TP Ingress Channels are associated
5554 * with a given Port. Bit i is set if TP Ingress Channel i is used by
5557 unsigned int t4_get_tp_ch_map(struct adapter *adap, int pidx)
5559 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
5560 unsigned int nports = 1 << NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
5562 if (pidx >= nports) {
5563 dev_warn(adap->pdev_dev, "TP Port Index %d >= Nports %d\n",
5568 switch (chip_version) {
5571 /* Note that this happens to be the same values as the MPS
5572 * Buffer Group Map for these Chips. But we replicate the code
5573 * here because they're really separate concepts.
5577 case 2: return 3 << (2 * pidx);
5578 case 4: return 1 << pidx;
5584 case 2: return 1 << pidx;
5589 dev_err(adap->pdev_dev, "Need TP Channel Map for Chip %0x, Nports %d\n",
5590 chip_version, nports);
5595 * t4_get_port_type_description - return Port Type string description
5596 * @port_type: firmware Port Type enumeration
5598 const char *t4_get_port_type_description(enum fw_port_type port_type)
5600 static const char *const port_type_description[] = {
5625 if (port_type < ARRAY_SIZE(port_type_description))
5626 return port_type_description[port_type];
5631 * t4_get_port_stats_offset - collect port stats relative to a previous
5633 * @adap: The adapter
5635 * @stats: Current stats to fill
5636 * @offset: Previous stats snapshot
5638 void t4_get_port_stats_offset(struct adapter *adap, int idx,
5639 struct port_stats *stats,
5640 struct port_stats *offset)
5645 t4_get_port_stats(adap, idx, stats);
5646 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
5647 i < (sizeof(struct port_stats) / sizeof(u64));
5653 * t4_get_port_stats - collect port statistics
5654 * @adap: the adapter
5655 * @idx: the port index
5656 * @p: the stats structure to fill
5658 * Collect statistics related to the given port from HW.
5660 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
5662 u32 bgmap = t4_get_mps_bg_map(adap, idx);
5663 u32 stat_ctl = t4_read_reg(adap, MPS_STAT_CTL_A);
5665 #define GET_STAT(name) \
5666 t4_read_reg64(adap, \
5667 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
5668 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
5669 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5671 p->tx_octets = GET_STAT(TX_PORT_BYTES);
5672 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
5673 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
5674 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
5675 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
5676 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
5677 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
5678 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
5679 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
5680 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
5681 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
5682 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
5683 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
5684 p->tx_drop = GET_STAT(TX_PORT_DROP);
5685 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
5686 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
5687 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
5688 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
5689 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
5690 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
5691 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
5692 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
5693 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
5695 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
5696 if (stat_ctl & COUNTPAUSESTATTX_F) {
5697 p->tx_frames -= p->tx_pause;
5698 p->tx_octets -= p->tx_pause * 64;
5700 if (stat_ctl & COUNTPAUSEMCTX_F)
5701 p->tx_mcast_frames -= p->tx_pause;
5703 p->rx_octets = GET_STAT(RX_PORT_BYTES);
5704 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
5705 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
5706 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
5707 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
5708 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
5709 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
5710 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
5711 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
5712 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
5713 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
5714 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
5715 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
5716 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
5717 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
5718 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
5719 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
5720 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
5721 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
5722 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
5723 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
5724 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
5725 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
5726 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
5727 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
5728 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
5729 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
5731 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
5732 if (stat_ctl & COUNTPAUSESTATRX_F) {
5733 p->rx_frames -= p->rx_pause;
5734 p->rx_octets -= p->rx_pause * 64;
5736 if (stat_ctl & COUNTPAUSEMCRX_F)
5737 p->rx_mcast_frames -= p->rx_pause;
5740 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
5741 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
5742 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
5743 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
5744 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
5745 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
5746 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
5747 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
5754 * t4_get_lb_stats - collect loopback port statistics
5755 * @adap: the adapter
5756 * @idx: the loopback port index
5757 * @p: the stats structure to fill
5759 * Return HW statistics for the given loopback port.
5761 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
5763 u32 bgmap = t4_get_mps_bg_map(adap, idx);
5765 #define GET_STAT(name) \
5766 t4_read_reg64(adap, \
5767 (is_t4(adap->params.chip) ? \
5768 PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
5769 T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
5770 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5772 p->octets = GET_STAT(BYTES);
5773 p->frames = GET_STAT(FRAMES);
5774 p->bcast_frames = GET_STAT(BCAST);
5775 p->mcast_frames = GET_STAT(MCAST);
5776 p->ucast_frames = GET_STAT(UCAST);
5777 p->error_frames = GET_STAT(ERROR);
5779 p->frames_64 = GET_STAT(64B);
5780 p->frames_65_127 = GET_STAT(65B_127B);
5781 p->frames_128_255 = GET_STAT(128B_255B);
5782 p->frames_256_511 = GET_STAT(256B_511B);
5783 p->frames_512_1023 = GET_STAT(512B_1023B);
5784 p->frames_1024_1518 = GET_STAT(1024B_1518B);
5785 p->frames_1519_max = GET_STAT(1519B_MAX);
5786 p->drop = GET_STAT(DROP_FRAMES);
5788 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
5789 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
5790 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
5791 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
5792 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
5793 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
5794 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
5795 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
5801 /* t4_mk_filtdelwr - create a delete filter WR
5802 * @ftid: the filter ID
5803 * @wr: the filter work request to populate
5804 * @qid: ingress queue to receive the delete notification
5806 * Creates a filter work request to delete the supplied filter. If @qid is
5807 * negative the delete notification is suppressed.
5809 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
5811 memset(wr, 0, sizeof(*wr));
5812 wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
5813 wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
5814 wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
5815 FW_FILTER_WR_NOREPLY_V(qid < 0));
5816 wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
5818 wr->rx_chan_rx_rpl_iq =
5819 cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
5822 #define INIT_CMD(var, cmd, rd_wr) do { \
5823 (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
5824 FW_CMD_REQUEST_F | \
5825 FW_CMD_##rd_wr##_F); \
5826 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
5829 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
5833 struct fw_ldst_cmd c;
5835 memset(&c, 0, sizeof(c));
5836 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
5837 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5841 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5842 c.u.addrval.addr = cpu_to_be32(addr);
5843 c.u.addrval.val = cpu_to_be32(val);
5845 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5849 * t4_mdio_rd - read a PHY register through MDIO
5850 * @adap: the adapter
5851 * @mbox: mailbox to use for the FW command
5852 * @phy_addr: the PHY address
5853 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5854 * @reg: the register to read
5855 * @valp: where to store the value
5857 * Issues a FW command through the given mailbox to read a PHY register.
5859 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5860 unsigned int mmd, unsigned int reg, u16 *valp)
5864 struct fw_ldst_cmd c;
5866 memset(&c, 0, sizeof(c));
5867 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5868 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5869 FW_CMD_REQUEST_F | FW_CMD_READ_F |
5871 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5872 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5873 FW_LDST_CMD_MMD_V(mmd));
5874 c.u.mdio.raddr = cpu_to_be16(reg);
5876 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5878 *valp = be16_to_cpu(c.u.mdio.rval);
5883 * t4_mdio_wr - write a PHY register through MDIO
5884 * @adap: the adapter
5885 * @mbox: mailbox to use for the FW command
5886 * @phy_addr: the PHY address
5887 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5888 * @reg: the register to write
5889 * @valp: value to write
5891 * Issues a FW command through the given mailbox to write a PHY register.
5893 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5894 unsigned int mmd, unsigned int reg, u16 val)
5897 struct fw_ldst_cmd c;
5899 memset(&c, 0, sizeof(c));
5900 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5901 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5902 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5904 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5905 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5906 FW_LDST_CMD_MMD_V(mmd));
5907 c.u.mdio.raddr = cpu_to_be16(reg);
5908 c.u.mdio.rval = cpu_to_be16(val);
5910 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5914 * t4_sge_decode_idma_state - decode the idma state
5915 * @adap: the adapter
5916 * @state: the state idma is stuck in
5918 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
5920 static const char * const t4_decode[] = {
5922 "IDMA_PUSH_MORE_CPL_FIFO",
5923 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5925 "IDMA_PHYSADDR_SEND_PCIEHDR",
5926 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5927 "IDMA_PHYSADDR_SEND_PAYLOAD",
5928 "IDMA_SEND_FIFO_TO_IMSG",
5929 "IDMA_FL_REQ_DATA_FL_PREP",
5930 "IDMA_FL_REQ_DATA_FL",
5932 "IDMA_FL_H_REQ_HEADER_FL",
5933 "IDMA_FL_H_SEND_PCIEHDR",
5934 "IDMA_FL_H_PUSH_CPL_FIFO",
5935 "IDMA_FL_H_SEND_CPL",
5936 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5937 "IDMA_FL_H_SEND_IP_HDR",
5938 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5939 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5940 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5941 "IDMA_FL_D_SEND_PCIEHDR",
5942 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5943 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5944 "IDMA_FL_SEND_PCIEHDR",
5945 "IDMA_FL_PUSH_CPL_FIFO",
5947 "IDMA_FL_SEND_PAYLOAD_FIRST",
5948 "IDMA_FL_SEND_PAYLOAD",
5949 "IDMA_FL_REQ_NEXT_DATA_FL",
5950 "IDMA_FL_SEND_NEXT_PCIEHDR",
5951 "IDMA_FL_SEND_PADDING",
5952 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5953 "IDMA_FL_SEND_FIFO_TO_IMSG",
5954 "IDMA_FL_REQ_DATAFL_DONE",
5955 "IDMA_FL_REQ_HEADERFL_DONE",
5957 static const char * const t5_decode[] = {
5960 "IDMA_PUSH_MORE_CPL_FIFO",
5961 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5962 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5963 "IDMA_PHYSADDR_SEND_PCIEHDR",
5964 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5965 "IDMA_PHYSADDR_SEND_PAYLOAD",
5966 "IDMA_SEND_FIFO_TO_IMSG",
5967 "IDMA_FL_REQ_DATA_FL",
5969 "IDMA_FL_DROP_SEND_INC",
5970 "IDMA_FL_H_REQ_HEADER_FL",
5971 "IDMA_FL_H_SEND_PCIEHDR",
5972 "IDMA_FL_H_PUSH_CPL_FIFO",
5973 "IDMA_FL_H_SEND_CPL",
5974 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5975 "IDMA_FL_H_SEND_IP_HDR",
5976 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5977 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5978 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5979 "IDMA_FL_D_SEND_PCIEHDR",
5980 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5981 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5982 "IDMA_FL_SEND_PCIEHDR",
5983 "IDMA_FL_PUSH_CPL_FIFO",
5985 "IDMA_FL_SEND_PAYLOAD_FIRST",
5986 "IDMA_FL_SEND_PAYLOAD",
5987 "IDMA_FL_REQ_NEXT_DATA_FL",
5988 "IDMA_FL_SEND_NEXT_PCIEHDR",
5989 "IDMA_FL_SEND_PADDING",
5990 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5992 static const char * const t6_decode[] = {
5994 "IDMA_PUSH_MORE_CPL_FIFO",
5995 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5996 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5997 "IDMA_PHYSADDR_SEND_PCIEHDR",
5998 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5999 "IDMA_PHYSADDR_SEND_PAYLOAD",
6000 "IDMA_FL_REQ_DATA_FL",
6002 "IDMA_FL_DROP_SEND_INC",
6003 "IDMA_FL_H_REQ_HEADER_FL",
6004 "IDMA_FL_H_SEND_PCIEHDR",
6005 "IDMA_FL_H_PUSH_CPL_FIFO",
6006 "IDMA_FL_H_SEND_CPL",
6007 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6008 "IDMA_FL_H_SEND_IP_HDR",
6009 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6010 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6011 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6012 "IDMA_FL_D_SEND_PCIEHDR",
6013 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6014 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6015 "IDMA_FL_SEND_PCIEHDR",
6016 "IDMA_FL_PUSH_CPL_FIFO",
6018 "IDMA_FL_SEND_PAYLOAD_FIRST",
6019 "IDMA_FL_SEND_PAYLOAD",
6020 "IDMA_FL_REQ_NEXT_DATA_FL",
6021 "IDMA_FL_SEND_NEXT_PCIEHDR",
6022 "IDMA_FL_SEND_PADDING",
6023 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6025 static const u32 sge_regs[] = {
6026 SGE_DEBUG_DATA_LOW_INDEX_2_A,
6027 SGE_DEBUG_DATA_LOW_INDEX_3_A,
6028 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
6030 const char **sge_idma_decode;
6031 int sge_idma_decode_nstates;
6033 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
6035 /* Select the right set of decode strings to dump depending on the
6036 * adapter chip type.
6038 switch (chip_version) {
6040 sge_idma_decode = (const char **)t4_decode;
6041 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6045 sge_idma_decode = (const char **)t5_decode;
6046 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6050 sge_idma_decode = (const char **)t6_decode;
6051 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
6055 dev_err(adapter->pdev_dev,
6056 "Unsupported chip version %d\n", chip_version);
6060 if (is_t4(adapter->params.chip)) {
6061 sge_idma_decode = (const char **)t4_decode;
6062 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6064 sge_idma_decode = (const char **)t5_decode;
6065 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6068 if (state < sge_idma_decode_nstates)
6069 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
6071 CH_WARN(adapter, "idma state %d unknown\n", state);
6073 for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
6074 CH_WARN(adapter, "SGE register %#x value %#x\n",
6075 sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
6079 * t4_sge_ctxt_flush - flush the SGE context cache
6080 * @adap: the adapter
6081 * @mbox: mailbox to use for the FW command
6083 * Issues a FW command through the given mailbox to flush the
6084 * SGE context cache.
6086 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
6090 struct fw_ldst_cmd c;
6092 memset(&c, 0, sizeof(c));
6093 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_SGE_EGRC);
6094 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6095 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6097 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6098 c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
6100 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6105 * t4_fw_hello - establish communication with FW
6106 * @adap: the adapter
6107 * @mbox: mailbox to use for the FW command
6108 * @evt_mbox: mailbox to receive async FW events
6109 * @master: specifies the caller's willingness to be the device master
6110 * @state: returns the current device state (if non-NULL)
6112 * Issues a command to establish communication with FW. Returns either
6113 * an error (negative integer) or the mailbox of the Master PF.
6115 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
6116 enum dev_master master, enum dev_state *state)
6119 struct fw_hello_cmd c;
6121 unsigned int master_mbox;
6122 int retries = FW_CMD_HELLO_RETRIES;
6125 memset(&c, 0, sizeof(c));
6126 INIT_CMD(c, HELLO, WRITE);
6127 c.err_to_clearinit = cpu_to_be32(
6128 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
6129 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
6130 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
6131 mbox : FW_HELLO_CMD_MBMASTER_M) |
6132 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
6133 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
6134 FW_HELLO_CMD_CLEARINIT_F);
6137 * Issue the HELLO command to the firmware. If it's not successful
6138 * but indicates that we got a "busy" or "timeout" condition, retry
6139 * the HELLO until we exhaust our retry limit. If we do exceed our
6140 * retry limit, check to see if the firmware left us any error
6141 * information and report that if so.
6143 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6145 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
6147 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
6148 t4_report_fw_error(adap);
6152 v = be32_to_cpu(c.err_to_clearinit);
6153 master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
6155 if (v & FW_HELLO_CMD_ERR_F)
6156 *state = DEV_STATE_ERR;
6157 else if (v & FW_HELLO_CMD_INIT_F)
6158 *state = DEV_STATE_INIT;
6160 *state = DEV_STATE_UNINIT;
6164 * If we're not the Master PF then we need to wait around for the
6165 * Master PF Driver to finish setting up the adapter.
6167 * Note that we also do this wait if we're a non-Master-capable PF and
6168 * there is no current Master PF; a Master PF may show up momentarily
6169 * and we wouldn't want to fail pointlessly. (This can happen when an
6170 * OS loads lots of different drivers rapidly at the same time). In
6171 * this case, the Master PF returned by the firmware will be
6172 * PCIE_FW_MASTER_M so the test below will work ...
6174 if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
6175 master_mbox != mbox) {
6176 int waiting = FW_CMD_HELLO_TIMEOUT;
6179 * Wait for the firmware to either indicate an error or
6180 * initialized state. If we see either of these we bail out
6181 * and report the issue to the caller. If we exhaust the
6182 * "hello timeout" and we haven't exhausted our retries, try
6183 * again. Otherwise bail with a timeout error.
6192 * If neither Error nor Initialialized are indicated
6193 * by the firmware keep waiting till we exaust our
6194 * timeout ... and then retry if we haven't exhausted
6197 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
6198 if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
6209 * We either have an Error or Initialized condition
6210 * report errors preferentially.
6213 if (pcie_fw & PCIE_FW_ERR_F)
6214 *state = DEV_STATE_ERR;
6215 else if (pcie_fw & PCIE_FW_INIT_F)
6216 *state = DEV_STATE_INIT;
6220 * If we arrived before a Master PF was selected and
6221 * there's not a valid Master PF, grab its identity
6224 if (master_mbox == PCIE_FW_MASTER_M &&
6225 (pcie_fw & PCIE_FW_MASTER_VLD_F))
6226 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
6235 * t4_fw_bye - end communication with FW
6236 * @adap: the adapter
6237 * @mbox: mailbox to use for the FW command
6239 * Issues a command to terminate communication with FW.
6241 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6243 struct fw_bye_cmd c;
6245 memset(&c, 0, sizeof(c));
6246 INIT_CMD(c, BYE, WRITE);
6247 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6251 * t4_init_cmd - ask FW to initialize the device
6252 * @adap: the adapter
6253 * @mbox: mailbox to use for the FW command
6255 * Issues a command to FW to partially initialize the device. This
6256 * performs initialization that generally doesn't depend on user input.
6258 int t4_early_init(struct adapter *adap, unsigned int mbox)
6260 struct fw_initialize_cmd c;
6262 memset(&c, 0, sizeof(c));
6263 INIT_CMD(c, INITIALIZE, WRITE);
6264 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6268 * t4_fw_reset - issue a reset to FW
6269 * @adap: the adapter
6270 * @mbox: mailbox to use for the FW command
6271 * @reset: specifies the type of reset to perform
6273 * Issues a reset command of the specified type to FW.
6275 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
6277 struct fw_reset_cmd c;
6279 memset(&c, 0, sizeof(c));
6280 INIT_CMD(c, RESET, WRITE);
6281 c.val = cpu_to_be32(reset);
6282 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6286 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
6287 * @adap: the adapter
6288 * @mbox: mailbox to use for the FW RESET command (if desired)
6289 * @force: force uP into RESET even if FW RESET command fails
6291 * Issues a RESET command to firmware (if desired) with a HALT indication
6292 * and then puts the microprocessor into RESET state. The RESET command
6293 * will only be issued if a legitimate mailbox is provided (mbox <=
6294 * PCIE_FW_MASTER_M).
6296 * This is generally used in order for the host to safely manipulate the
6297 * adapter without fear of conflicting with whatever the firmware might
6298 * be doing. The only way out of this state is to RESTART the firmware
6301 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
6306 * If a legitimate mailbox is provided, issue a RESET command
6307 * with a HALT indication.
6309 if (mbox <= PCIE_FW_MASTER_M) {
6310 struct fw_reset_cmd c;
6312 memset(&c, 0, sizeof(c));
6313 INIT_CMD(c, RESET, WRITE);
6314 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
6315 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
6316 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6320 * Normally we won't complete the operation if the firmware RESET
6321 * command fails but if our caller insists we'll go ahead and put the
6322 * uP into RESET. This can be useful if the firmware is hung or even
6323 * missing ... We'll have to take the risk of putting the uP into
6324 * RESET without the cooperation of firmware in that case.
6326 * We also force the firmware's HALT flag to be on in case we bypassed
6327 * the firmware RESET command above or we're dealing with old firmware
6328 * which doesn't have the HALT capability. This will serve as a flag
6329 * for the incoming firmware to know that it's coming out of a HALT
6330 * rather than a RESET ... if it's new enough to understand that ...
6332 if (ret == 0 || force) {
6333 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
6334 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
6339 * And we always return the result of the firmware RESET command
6340 * even when we force the uP into RESET ...
6346 * t4_fw_restart - restart the firmware by taking the uP out of RESET
6347 * @adap: the adapter
6348 * @reset: if we want to do a RESET to restart things
6350 * Restart firmware previously halted by t4_fw_halt(). On successful
6351 * return the previous PF Master remains as the new PF Master and there
6352 * is no need to issue a new HELLO command, etc.
6354 * We do this in two ways:
6356 * 1. If we're dealing with newer firmware we'll simply want to take
6357 * the chip's microprocessor out of RESET. This will cause the
6358 * firmware to start up from its start vector. And then we'll loop
6359 * until the firmware indicates it's started again (PCIE_FW.HALT
6360 * reset to 0) or we timeout.
6362 * 2. If we're dealing with older firmware then we'll need to RESET
6363 * the chip since older firmware won't recognize the PCIE_FW.HALT
6364 * flag and automatically RESET itself on startup.
6366 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6370 * Since we're directing the RESET instead of the firmware
6371 * doing it automatically, we need to clear the PCIE_FW.HALT
6374 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
6377 * If we've been given a valid mailbox, first try to get the
6378 * firmware to do the RESET. If that works, great and we can
6379 * return success. Otherwise, if we haven't been given a
6380 * valid mailbox or the RESET command failed, fall back to
6381 * hitting the chip with a hammer.
6383 if (mbox <= PCIE_FW_MASTER_M) {
6384 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6386 if (t4_fw_reset(adap, mbox,
6387 PIORST_F | PIORSTMODE_F) == 0)
6391 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
6396 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6397 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6398 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
6409 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6410 * @adap: the adapter
6411 * @mbox: mailbox to use for the FW RESET command (if desired)
6412 * @fw_data: the firmware image to write
6414 * @force: force upgrade even if firmware doesn't cooperate
6416 * Perform all of the steps necessary for upgrading an adapter's
6417 * firmware image. Normally this requires the cooperation of the
6418 * existing firmware in order to halt all existing activities
6419 * but if an invalid mailbox token is passed in we skip that step
6420 * (though we'll still put the adapter microprocessor into RESET in
6423 * On successful return the new firmware will have been loaded and
6424 * the adapter will have been fully RESET losing all previous setup
6425 * state. On unsuccessful return the adapter may be completely hosed ...
6426 * positive errno indicates that the adapter is ~probably~ intact, a
6427 * negative errno indicates that things are looking bad ...
6429 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
6430 const u8 *fw_data, unsigned int size, int force)
6432 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6435 if (!t4_fw_matches_chip(adap, fw_hdr))
6438 /* Disable FW_OK flag so that mbox commands with FW_OK flag set
6439 * wont be sent when we are flashing FW.
6441 adap->flags &= ~FW_OK;
6443 ret = t4_fw_halt(adap, mbox, force);
6444 if (ret < 0 && !force)
6447 ret = t4_load_fw(adap, fw_data, size);
6452 * Older versions of the firmware don't understand the new
6453 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
6454 * restart. So for newly loaded older firmware we'll have to do the
6455 * RESET for it so it starts up on a clean slate. We can tell if
6456 * the newly loaded firmware will handle this right by checking
6457 * its header flags to see if it advertises the capability.
6459 reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
6460 ret = t4_fw_restart(adap, mbox, reset);
6462 /* Grab potentially new Firmware Device Log parameters so we can see
6463 * how healthy the new Firmware is. It's okay to contact the new
6464 * Firmware for these parameters even though, as far as it's
6465 * concerned, we've never said "HELLO" to it ...
6467 (void)t4_init_devlog_params(adap);
6469 adap->flags |= FW_OK;
6474 * t4_fl_pkt_align - return the fl packet alignment
6475 * @adap: the adapter
6477 * T4 has a single field to specify the packing and padding boundary.
6478 * T5 onwards has separate fields for this and hence the alignment for
6479 * next packet offset is maximum of these two.
6482 int t4_fl_pkt_align(struct adapter *adap)
6484 u32 sge_control, sge_control2;
6485 unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
6487 sge_control = t4_read_reg(adap, SGE_CONTROL_A);
6489 /* T4 uses a single control field to specify both the PCIe Padding and
6490 * Packing Boundary. T5 introduced the ability to specify these
6491 * separately. The actual Ingress Packet Data alignment boundary
6492 * within Packed Buffer Mode is the maximum of these two
6493 * specifications. (Note that it makes no real practical sense to
6494 * have the Pading Boudary be larger than the Packing Boundary but you
6495 * could set the chip up that way and, in fact, legacy T4 code would
6496 * end doing this because it would initialize the Padding Boundary and
6497 * leave the Packing Boundary initialized to 0 (16 bytes).)
6498 * Padding Boundary values in T6 starts from 8B,
6499 * where as it is 32B for T4 and T5.
6501 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
6502 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
6504 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
6506 ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
6508 fl_align = ingpadboundary;
6509 if (!is_t4(adap->params.chip)) {
6510 /* T5 has a weird interpretation of one of the PCIe Packing
6511 * Boundary values. No idea why ...
6513 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
6514 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
6515 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
6516 ingpackboundary = 16;
6518 ingpackboundary = 1 << (ingpackboundary +
6519 INGPACKBOUNDARY_SHIFT_X);
6521 fl_align = max(ingpadboundary, ingpackboundary);
6527 * t4_fixup_host_params - fix up host-dependent parameters
6528 * @adap: the adapter
6529 * @page_size: the host's Base Page Size
6530 * @cache_line_size: the host's Cache Line Size
6532 * Various registers in T4 contain values which are dependent on the
6533 * host's Base Page and Cache Line Sizes. This function will fix all of
6534 * those registers with the appropriate values as passed in ...
6536 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
6537 unsigned int cache_line_size)
6539 unsigned int page_shift = fls(page_size) - 1;
6540 unsigned int sge_hps = page_shift - 10;
6541 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
6542 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
6543 unsigned int fl_align_log = fls(fl_align) - 1;
6545 t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
6546 HOSTPAGESIZEPF0_V(sge_hps) |
6547 HOSTPAGESIZEPF1_V(sge_hps) |
6548 HOSTPAGESIZEPF2_V(sge_hps) |
6549 HOSTPAGESIZEPF3_V(sge_hps) |
6550 HOSTPAGESIZEPF4_V(sge_hps) |
6551 HOSTPAGESIZEPF5_V(sge_hps) |
6552 HOSTPAGESIZEPF6_V(sge_hps) |
6553 HOSTPAGESIZEPF7_V(sge_hps));
6555 if (is_t4(adap->params.chip)) {
6556 t4_set_reg_field(adap, SGE_CONTROL_A,
6557 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6558 EGRSTATUSPAGESIZE_F,
6559 INGPADBOUNDARY_V(fl_align_log -
6560 INGPADBOUNDARY_SHIFT_X) |
6561 EGRSTATUSPAGESIZE_V(stat_len != 64));
6563 unsigned int pack_align;
6564 unsigned int ingpad, ingpack;
6565 unsigned int pcie_cap;
6567 /* T5 introduced the separation of the Free List Padding and
6568 * Packing Boundaries. Thus, we can select a smaller Padding
6569 * Boundary to avoid uselessly chewing up PCIe Link and Memory
6570 * Bandwidth, and use a Packing Boundary which is large enough
6571 * to avoid false sharing between CPUs, etc.
6573 * For the PCI Link, the smaller the Padding Boundary the
6574 * better. For the Memory Controller, a smaller Padding
6575 * Boundary is better until we cross under the Memory Line
6576 * Size (the minimum unit of transfer to/from Memory). If we
6577 * have a Padding Boundary which is smaller than the Memory
6578 * Line Size, that'll involve a Read-Modify-Write cycle on the
6579 * Memory Controller which is never good.
6582 /* We want the Packing Boundary to be based on the Cache Line
6583 * Size in order to help avoid False Sharing performance
6584 * issues between CPUs, etc. We also want the Packing
6585 * Boundary to incorporate the PCI-E Maximum Payload Size. We
6586 * get best performance when the Packing Boundary is a
6587 * multiple of the Maximum Payload Size.
6589 pack_align = fl_align;
6590 pcie_cap = pci_find_capability(adap->pdev, PCI_CAP_ID_EXP);
6592 unsigned int mps, mps_log;
6595 /* The PCIe Device Control Maximum Payload Size field
6596 * [bits 7:5] encodes sizes as powers of 2 starting at
6599 pci_read_config_word(adap->pdev,
6600 pcie_cap + PCI_EXP_DEVCTL,
6602 mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
6604 if (mps > pack_align)
6608 /* N.B. T5/T6 have a crazy special interpretation of the "0"
6609 * value for the Packing Boundary. This corresponds to 16
6610 * bytes instead of the expected 32 bytes. So if we want 32
6611 * bytes, the best we can really do is 64 bytes ...
6613 if (pack_align <= 16) {
6614 ingpack = INGPACKBOUNDARY_16B_X;
6616 } else if (pack_align == 32) {
6617 ingpack = INGPACKBOUNDARY_64B_X;
6620 unsigned int pack_align_log = fls(pack_align) - 1;
6622 ingpack = pack_align_log - INGPACKBOUNDARY_SHIFT_X;
6623 fl_align = pack_align;
6626 /* Use the smallest Ingress Padding which isn't smaller than
6627 * the Memory Controller Read/Write Size. We'll take that as
6628 * being 8 bytes since we don't know of any system with a
6629 * wider Memory Controller Bus Width.
6631 if (is_t5(adap->params.chip))
6632 ingpad = INGPADBOUNDARY_32B_X;
6634 ingpad = T6_INGPADBOUNDARY_8B_X;
6636 t4_set_reg_field(adap, SGE_CONTROL_A,
6637 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6638 EGRSTATUSPAGESIZE_F,
6639 INGPADBOUNDARY_V(ingpad) |
6640 EGRSTATUSPAGESIZE_V(stat_len != 64));
6641 t4_set_reg_field(adap, SGE_CONTROL2_A,
6642 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
6643 INGPACKBOUNDARY_V(ingpack));
6646 * Adjust various SGE Free List Host Buffer Sizes.
6648 * This is something of a crock since we're using fixed indices into
6649 * the array which are also known by the sge.c code and the T4
6650 * Firmware Configuration File. We need to come up with a much better
6651 * approach to managing this array. For now, the first four entries
6656 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
6657 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
6659 * For the single-MTU buffers in unpacked mode we need to include
6660 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
6661 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
6662 * Padding boundary. All of these are accommodated in the Factory
6663 * Default Firmware Configuration File but we need to adjust it for
6664 * this host's cache line size.
6666 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
6667 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
6668 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
6670 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
6671 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
6674 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
6680 * t4_fw_initialize - ask FW to initialize the device
6681 * @adap: the adapter
6682 * @mbox: mailbox to use for the FW command
6684 * Issues a command to FW to partially initialize the device. This
6685 * performs initialization that generally doesn't depend on user input.
6687 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
6689 struct fw_initialize_cmd c;
6691 memset(&c, 0, sizeof(c));
6692 INIT_CMD(c, INITIALIZE, WRITE);
6693 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6697 * t4_query_params_rw - query FW or device parameters
6698 * @adap: the adapter
6699 * @mbox: mailbox to use for the FW command
6702 * @nparams: the number of parameters
6703 * @params: the parameter names
6704 * @val: the parameter values
6705 * @rw: Write and read flag
6706 * @sleep_ok: if true, we may sleep awaiting mbox cmd completion
6708 * Reads the value of FW or device parameters. Up to 7 parameters can be
6711 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
6712 unsigned int vf, unsigned int nparams, const u32 *params,
6713 u32 *val, int rw, bool sleep_ok)
6716 struct fw_params_cmd c;
6717 __be32 *p = &c.param[0].mnem;
6722 memset(&c, 0, sizeof(c));
6723 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6724 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6725 FW_PARAMS_CMD_PFN_V(pf) |
6726 FW_PARAMS_CMD_VFN_V(vf));
6727 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6729 for (i = 0; i < nparams; i++) {
6730 *p++ = cpu_to_be32(*params++);
6732 *p = cpu_to_be32(*(val + i));
6736 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6738 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
6739 *val++ = be32_to_cpu(*p);
6743 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6744 unsigned int vf, unsigned int nparams, const u32 *params,
6747 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
6751 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
6752 unsigned int vf, unsigned int nparams, const u32 *params,
6755 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
6760 * t4_set_params_timeout - sets FW or device parameters
6761 * @adap: the adapter
6762 * @mbox: mailbox to use for the FW command
6765 * @nparams: the number of parameters
6766 * @params: the parameter names
6767 * @val: the parameter values
6768 * @timeout: the timeout time
6770 * Sets the value of FW or device parameters. Up to 7 parameters can be
6771 * specified at once.
6773 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
6774 unsigned int pf, unsigned int vf,
6775 unsigned int nparams, const u32 *params,
6776 const u32 *val, int timeout)
6778 struct fw_params_cmd c;
6779 __be32 *p = &c.param[0].mnem;
6784 memset(&c, 0, sizeof(c));
6785 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6786 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6787 FW_PARAMS_CMD_PFN_V(pf) |
6788 FW_PARAMS_CMD_VFN_V(vf));
6789 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6792 *p++ = cpu_to_be32(*params++);
6793 *p++ = cpu_to_be32(*val++);
6796 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
6800 * t4_set_params - sets FW or device parameters
6801 * @adap: the adapter
6802 * @mbox: mailbox to use for the FW command
6805 * @nparams: the number of parameters
6806 * @params: the parameter names
6807 * @val: the parameter values
6809 * Sets the value of FW or device parameters. Up to 7 parameters can be
6810 * specified at once.
6812 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6813 unsigned int vf, unsigned int nparams, const u32 *params,
6816 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
6817 FW_CMD_MAX_TIMEOUT);
6821 * t4_cfg_pfvf - configure PF/VF resource limits
6822 * @adap: the adapter
6823 * @mbox: mailbox to use for the FW command
6824 * @pf: the PF being configured
6825 * @vf: the VF being configured
6826 * @txq: the max number of egress queues
6827 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
6828 * @rxqi: the max number of interrupt-capable ingress queues
6829 * @rxq: the max number of interruptless ingress queues
6830 * @tc: the PCI traffic class
6831 * @vi: the max number of virtual interfaces
6832 * @cmask: the channel access rights mask for the PF/VF
6833 * @pmask: the port access rights mask for the PF/VF
6834 * @nexact: the maximum number of exact MPS filters
6835 * @rcaps: read capabilities
6836 * @wxcaps: write/execute capabilities
6838 * Configures resource limits and capabilities for a physical or virtual
6841 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
6842 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
6843 unsigned int rxqi, unsigned int rxq, unsigned int tc,
6844 unsigned int vi, unsigned int cmask, unsigned int pmask,
6845 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
6847 struct fw_pfvf_cmd c;
6849 memset(&c, 0, sizeof(c));
6850 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
6851 FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
6852 FW_PFVF_CMD_VFN_V(vf));
6853 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6854 c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
6855 FW_PFVF_CMD_NIQ_V(rxq));
6856 c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
6857 FW_PFVF_CMD_PMASK_V(pmask) |
6858 FW_PFVF_CMD_NEQ_V(txq));
6859 c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
6860 FW_PFVF_CMD_NVI_V(vi) |
6861 FW_PFVF_CMD_NEXACTF_V(nexact));
6862 c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
6863 FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
6864 FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
6865 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6869 * t4_alloc_vi - allocate a virtual interface
6870 * @adap: the adapter
6871 * @mbox: mailbox to use for the FW command
6872 * @port: physical port associated with the VI
6873 * @pf: the PF owning the VI
6874 * @vf: the VF owning the VI
6875 * @nmac: number of MAC addresses needed (1 to 5)
6876 * @mac: the MAC addresses of the VI
6877 * @rss_size: size of RSS table slice associated with this VI
6879 * Allocates a virtual interface for the given physical port. If @mac is
6880 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
6881 * @mac should be large enough to hold @nmac Ethernet addresses, they are
6882 * stored consecutively so the space needed is @nmac * 6 bytes.
6883 * Returns a negative error number or the non-negative VI id.
6885 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
6886 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
6887 unsigned int *rss_size)
6892 memset(&c, 0, sizeof(c));
6893 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
6894 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
6895 FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
6896 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
6897 c.portid_pkd = FW_VI_CMD_PORTID_V(port);
6900 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6905 memcpy(mac, c.mac, sizeof(c.mac));
6908 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
6910 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
6912 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
6914 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
6918 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
6919 return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
6923 * t4_free_vi - free a virtual interface
6924 * @adap: the adapter
6925 * @mbox: mailbox to use for the FW command
6926 * @pf: the PF owning the VI
6927 * @vf: the VF owning the VI
6928 * @viid: virtual interface identifiler
6930 * Free a previously allocated virtual interface.
6932 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
6933 unsigned int vf, unsigned int viid)
6937 memset(&c, 0, sizeof(c));
6938 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
6941 FW_VI_CMD_PFN_V(pf) |
6942 FW_VI_CMD_VFN_V(vf));
6943 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
6944 c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
6946 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6950 * t4_set_rxmode - set Rx properties of a virtual interface
6951 * @adap: the adapter
6952 * @mbox: mailbox to use for the FW command
6954 * @mtu: the new MTU or -1
6955 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
6956 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
6957 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
6958 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
6959 * @sleep_ok: if true we may sleep while awaiting command completion
6961 * Sets Rx properties of a virtual interface.
6963 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
6964 int mtu, int promisc, int all_multi, int bcast, int vlanex,
6967 struct fw_vi_rxmode_cmd c;
6969 /* convert to FW values */
6971 mtu = FW_RXMODE_MTU_NO_CHG;
6973 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
6975 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
6977 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
6979 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
6981 memset(&c, 0, sizeof(c));
6982 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
6983 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6984 FW_VI_RXMODE_CMD_VIID_V(viid));
6985 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6987 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
6988 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
6989 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
6990 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
6991 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
6992 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6996 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
6997 * @adap: the adapter
6998 * @mbox: mailbox to use for the FW command
7000 * @free: if true any existing filters for this VI id are first removed
7001 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
7002 * @addr: the MAC address(es)
7003 * @idx: where to store the index of each allocated filter
7004 * @hash: pointer to hash address filter bitmap
7005 * @sleep_ok: call is allowed to sleep
7007 * Allocates an exact-match filter for each of the supplied addresses and
7008 * sets it to the corresponding address. If @idx is not %NULL it should
7009 * have at least @naddr entries, each of which will be set to the index of
7010 * the filter allocated for the corresponding MAC address. If a filter
7011 * could not be allocated for an address its index is set to 0xffff.
7012 * If @hash is not %NULL addresses that fail to allocate an exact filter
7013 * are hashed and update the hash filter bitmap pointed at by @hash.
7015 * Returns a negative error number or the number of filters allocated.
7017 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
7018 unsigned int viid, bool free, unsigned int naddr,
7019 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
7021 int offset, ret = 0;
7022 struct fw_vi_mac_cmd c;
7023 unsigned int nfilters = 0;
7024 unsigned int max_naddr = adap->params.arch.mps_tcam_size;
7025 unsigned int rem = naddr;
7027 if (naddr > max_naddr)
7030 for (offset = 0; offset < naddr ; /**/) {
7031 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
7032 rem : ARRAY_SIZE(c.u.exact));
7033 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
7034 u.exact[fw_naddr]), 16);
7035 struct fw_vi_mac_exact *p;
7038 memset(&c, 0, sizeof(c));
7039 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7042 FW_CMD_EXEC_V(free) |
7043 FW_VI_MAC_CMD_VIID_V(viid));
7044 c.freemacs_to_len16 =
7045 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
7046 FW_CMD_LEN16_V(len16));
7048 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7050 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7051 FW_VI_MAC_CMD_IDX_V(
7052 FW_VI_MAC_ADD_MAC));
7053 memcpy(p->macaddr, addr[offset + i],
7054 sizeof(p->macaddr));
7057 /* It's okay if we run out of space in our MAC address arena.
7058 * Some of the addresses we submit may get stored so we need
7059 * to run through the reply to see what the results were ...
7061 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7062 if (ret && ret != -FW_ENOMEM)
7065 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7066 u16 index = FW_VI_MAC_CMD_IDX_G(
7067 be16_to_cpu(p->valid_to_idx));
7070 idx[offset + i] = (index >= max_naddr ?
7072 if (index < max_naddr)
7076 hash_mac_addr(addr[offset + i]));
7084 if (ret == 0 || ret == -FW_ENOMEM)
7090 * t4_free_mac_filt - frees exact-match filters of given MAC addresses
7091 * @adap: the adapter
7092 * @mbox: mailbox to use for the FW command
7094 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
7095 * @addr: the MAC address(es)
7096 * @sleep_ok: call is allowed to sleep
7098 * Frees the exact-match filter for each of the supplied addresses
7100 * Returns a negative error number or the number of filters freed.
7102 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
7103 unsigned int viid, unsigned int naddr,
7104 const u8 **addr, bool sleep_ok)
7106 int offset, ret = 0;
7107 struct fw_vi_mac_cmd c;
7108 unsigned int nfilters = 0;
7109 unsigned int max_naddr = is_t4(adap->params.chip) ?
7110 NUM_MPS_CLS_SRAM_L_INSTANCES :
7111 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7112 unsigned int rem = naddr;
7114 if (naddr > max_naddr)
7117 for (offset = 0; offset < (int)naddr ; /**/) {
7118 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
7120 : ARRAY_SIZE(c.u.exact));
7121 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
7122 u.exact[fw_naddr]), 16);
7123 struct fw_vi_mac_exact *p;
7126 memset(&c, 0, sizeof(c));
7127 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7131 FW_VI_MAC_CMD_VIID_V(viid));
7132 c.freemacs_to_len16 =
7133 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7134 FW_CMD_LEN16_V(len16));
7136 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
7137 p->valid_to_idx = cpu_to_be16(
7138 FW_VI_MAC_CMD_VALID_F |
7139 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
7140 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
7143 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7147 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7148 u16 index = FW_VI_MAC_CMD_IDX_G(
7149 be16_to_cpu(p->valid_to_idx));
7151 if (index < max_naddr)
7165 * t4_change_mac - modifies the exact-match filter for a MAC address
7166 * @adap: the adapter
7167 * @mbox: mailbox to use for the FW command
7169 * @idx: index of existing filter for old value of MAC address, or -1
7170 * @addr: the new MAC address value
7171 * @persist: whether a new MAC allocation should be persistent
7172 * @add_smt: if true also add the address to the HW SMT
7174 * Modifies an exact-match filter and sets it to the new MAC address.
7175 * Note that in general it is not possible to modify the value of a given
7176 * filter so the generic way to modify an address filter is to free the one
7177 * being used by the old address value and allocate a new filter for the
7178 * new address value. @idx can be -1 if the address is a new addition.
7180 * Returns a negative error number or the index of the filter with the new
7183 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
7184 int idx, const u8 *addr, bool persist, bool add_smt)
7187 struct fw_vi_mac_cmd c;
7188 struct fw_vi_mac_exact *p = c.u.exact;
7189 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
7191 if (idx < 0) /* new allocation */
7192 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
7193 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
7195 memset(&c, 0, sizeof(c));
7196 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7197 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7198 FW_VI_MAC_CMD_VIID_V(viid));
7199 c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
7200 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7201 FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
7202 FW_VI_MAC_CMD_IDX_V(idx));
7203 memcpy(p->macaddr, addr, sizeof(p->macaddr));
7205 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7207 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
7208 if (ret >= max_mac_addr)
7215 * t4_set_addr_hash - program the MAC inexact-match hash filter
7216 * @adap: the adapter
7217 * @mbox: mailbox to use for the FW command
7219 * @ucast: whether the hash filter should also match unicast addresses
7220 * @vec: the value to be written to the hash filter
7221 * @sleep_ok: call is allowed to sleep
7223 * Sets the 64-bit inexact-match hash filter for a virtual interface.
7225 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
7226 bool ucast, u64 vec, bool sleep_ok)
7228 struct fw_vi_mac_cmd c;
7230 memset(&c, 0, sizeof(c));
7231 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7232 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7233 FW_VI_ENABLE_CMD_VIID_V(viid));
7234 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
7235 FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
7237 c.u.hash.hashvec = cpu_to_be64(vec);
7238 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7242 * t4_enable_vi_params - enable/disable a virtual interface
7243 * @adap: the adapter
7244 * @mbox: mailbox to use for the FW command
7246 * @rx_en: 1=enable Rx, 0=disable Rx
7247 * @tx_en: 1=enable Tx, 0=disable Tx
7248 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
7250 * Enables/disables a virtual interface. Note that setting DCB Enable
7251 * only makes sense when enabling a Virtual Interface ...
7253 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
7254 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
7256 struct fw_vi_enable_cmd c;
7258 memset(&c, 0, sizeof(c));
7259 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
7260 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7261 FW_VI_ENABLE_CMD_VIID_V(viid));
7262 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
7263 FW_VI_ENABLE_CMD_EEN_V(tx_en) |
7264 FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
7266 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
7270 * t4_enable_vi - enable/disable a virtual interface
7271 * @adap: the adapter
7272 * @mbox: mailbox to use for the FW command
7274 * @rx_en: 1=enable Rx, 0=disable Rx
7275 * @tx_en: 1=enable Tx, 0=disable Tx
7277 * Enables/disables a virtual interface.
7279 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
7280 bool rx_en, bool tx_en)
7282 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
7286 * t4_identify_port - identify a VI's port by blinking its LED
7287 * @adap: the adapter
7288 * @mbox: mailbox to use for the FW command
7290 * @nblinks: how many times to blink LED at 2.5 Hz
7292 * Identifies a VI's port by blinking its LED.
7294 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
7295 unsigned int nblinks)
7297 struct fw_vi_enable_cmd c;
7299 memset(&c, 0, sizeof(c));
7300 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
7301 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7302 FW_VI_ENABLE_CMD_VIID_V(viid));
7303 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
7304 c.blinkdur = cpu_to_be16(nblinks);
7305 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7309 * t4_iq_stop - stop an ingress queue and its FLs
7310 * @adap: the adapter
7311 * @mbox: mailbox to use for the FW command
7312 * @pf: the PF owning the queues
7313 * @vf: the VF owning the queues
7314 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
7315 * @iqid: ingress queue id
7316 * @fl0id: FL0 queue id or 0xffff if no attached FL0
7317 * @fl1id: FL1 queue id or 0xffff if no attached FL1
7319 * Stops an ingress queue and its associated FLs, if any. This causes
7320 * any current or future data/messages destined for these queues to be
7323 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
7324 unsigned int vf, unsigned int iqtype, unsigned int iqid,
7325 unsigned int fl0id, unsigned int fl1id)
7329 memset(&c, 0, sizeof(c));
7330 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7331 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7332 FW_IQ_CMD_VFN_V(vf));
7333 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
7334 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7335 c.iqid = cpu_to_be16(iqid);
7336 c.fl0id = cpu_to_be16(fl0id);
7337 c.fl1id = cpu_to_be16(fl1id);
7338 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7342 * t4_iq_free - free an ingress queue and its FLs
7343 * @adap: the adapter
7344 * @mbox: mailbox to use for the FW command
7345 * @pf: the PF owning the queues
7346 * @vf: the VF owning the queues
7347 * @iqtype: the ingress queue type
7348 * @iqid: ingress queue id
7349 * @fl0id: FL0 queue id or 0xffff if no attached FL0
7350 * @fl1id: FL1 queue id or 0xffff if no attached FL1
7352 * Frees an ingress queue and its associated FLs, if any.
7354 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7355 unsigned int vf, unsigned int iqtype, unsigned int iqid,
7356 unsigned int fl0id, unsigned int fl1id)
7360 memset(&c, 0, sizeof(c));
7361 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7362 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7363 FW_IQ_CMD_VFN_V(vf));
7364 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
7365 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7366 c.iqid = cpu_to_be16(iqid);
7367 c.fl0id = cpu_to_be16(fl0id);
7368 c.fl1id = cpu_to_be16(fl1id);
7369 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7373 * t4_eth_eq_free - free an Ethernet egress queue
7374 * @adap: the adapter
7375 * @mbox: mailbox to use for the FW command
7376 * @pf: the PF owning the queue
7377 * @vf: the VF owning the queue
7378 * @eqid: egress queue id
7380 * Frees an Ethernet egress queue.
7382 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7383 unsigned int vf, unsigned int eqid)
7385 struct fw_eq_eth_cmd c;
7387 memset(&c, 0, sizeof(c));
7388 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
7389 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7390 FW_EQ_ETH_CMD_PFN_V(pf) |
7391 FW_EQ_ETH_CMD_VFN_V(vf));
7392 c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
7393 c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
7394 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7398 * t4_ctrl_eq_free - free a control egress queue
7399 * @adap: the adapter
7400 * @mbox: mailbox to use for the FW command
7401 * @pf: the PF owning the queue
7402 * @vf: the VF owning the queue
7403 * @eqid: egress queue id
7405 * Frees a control egress queue.
7407 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7408 unsigned int vf, unsigned int eqid)
7410 struct fw_eq_ctrl_cmd c;
7412 memset(&c, 0, sizeof(c));
7413 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
7414 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7415 FW_EQ_CTRL_CMD_PFN_V(pf) |
7416 FW_EQ_CTRL_CMD_VFN_V(vf));
7417 c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
7418 c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
7419 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7423 * t4_ofld_eq_free - free an offload egress queue
7424 * @adap: the adapter
7425 * @mbox: mailbox to use for the FW command
7426 * @pf: the PF owning the queue
7427 * @vf: the VF owning the queue
7428 * @eqid: egress queue id
7430 * Frees a control egress queue.
7432 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7433 unsigned int vf, unsigned int eqid)
7435 struct fw_eq_ofld_cmd c;
7437 memset(&c, 0, sizeof(c));
7438 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
7439 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7440 FW_EQ_OFLD_CMD_PFN_V(pf) |
7441 FW_EQ_OFLD_CMD_VFN_V(vf));
7442 c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
7443 c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
7444 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7448 * t4_link_down_rc_str - return a string for a Link Down Reason Code
7449 * @adap: the adapter
7450 * @link_down_rc: Link Down Reason Code
7452 * Returns a string representation of the Link Down Reason Code.
7454 static const char *t4_link_down_rc_str(unsigned char link_down_rc)
7456 static const char * const reason[] = {
7459 "Auto-negotiation Failure",
7461 "Insufficient Airflow",
7462 "Unable To Determine Reason",
7463 "No RX Signal Detected",
7467 if (link_down_rc >= ARRAY_SIZE(reason))
7468 return "Bad Reason Code";
7470 return reason[link_down_rc];
7474 * t4_handle_get_port_info - process a FW reply message
7475 * @pi: the port info
7476 * @rpl: start of the FW message
7478 * Processes a GET_PORT_INFO FW reply message.
7480 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
7482 const struct fw_port_cmd *p = (const void *)rpl;
7483 struct adapter *adap = pi->adapter;
7485 /* link/module state change message */
7486 int speed = 0, fc = 0;
7487 struct link_config *lc;
7488 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
7489 int link_ok = (stat & FW_PORT_CMD_LSTATUS_F) != 0;
7490 u32 mod = FW_PORT_CMD_MODTYPE_G(stat);
7492 if (stat & FW_PORT_CMD_RXPAUSE_F)
7494 if (stat & FW_PORT_CMD_TXPAUSE_F)
7496 if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
7498 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
7500 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
7502 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
7504 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
7506 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
7511 if (mod != pi->mod_type) {
7513 t4_os_portmod_changed(adap, pi->port_id);
7515 if (link_ok != lc->link_ok || speed != lc->speed ||
7516 fc != lc->fc) { /* something changed */
7517 if (!link_ok && lc->link_ok) {
7518 unsigned char rc = FW_PORT_CMD_LINKDNRC_G(stat);
7520 lc->link_down_rc = rc;
7521 dev_warn(adap->pdev_dev,
7522 "Port %d link down, reason: %s\n",
7523 pi->port_id, t4_link_down_rc_str(rc));
7525 lc->link_ok = link_ok;
7528 lc->supported = be16_to_cpu(p->u.info.pcap);
7529 lc->lp_advertising = be16_to_cpu(p->u.info.lpacap);
7531 t4_os_link_changed(adap, pi->port_id, link_ok);
7536 * t4_update_port_info - retrieve and update port information if changed
7537 * @pi: the port_info
7539 * We issue a Get Port Information Command to the Firmware and, if
7540 * successful, we check to see if anything is different from what we
7541 * last recorded and update things accordingly.
7543 int t4_update_port_info(struct port_info *pi)
7545 struct fw_port_cmd port_cmd;
7548 memset(&port_cmd, 0, sizeof(port_cmd));
7549 port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
7550 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7551 FW_PORT_CMD_PORTID_V(pi->port_id));
7552 port_cmd.action_to_len16 = cpu_to_be32(
7553 FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) |
7554 FW_LEN16(port_cmd));
7555 ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
7556 &port_cmd, sizeof(port_cmd), &port_cmd);
7560 t4_handle_get_port_info(pi, (__be64 *)&port_cmd);
7565 * t4_handle_fw_rpl - process a FW reply message
7566 * @adap: the adapter
7567 * @rpl: start of the FW message
7569 * Processes a FW message, such as link state change messages.
7571 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
7573 u8 opcode = *(const u8 *)rpl;
7575 /* This might be a port command ... this simplifies the following
7576 * conditionals ... We can get away with pre-dereferencing
7577 * action_to_len16 because it's in the first 16 bytes and all messages
7578 * will be at least that long.
7580 const struct fw_port_cmd *p = (const void *)rpl;
7581 unsigned int action =
7582 FW_PORT_CMD_ACTION_G(be32_to_cpu(p->action_to_len16));
7584 if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
7586 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
7587 struct port_info *pi = NULL;
7589 for_each_port(adap, i) {
7590 pi = adap2pinfo(adap, i);
7591 if (pi->tx_chan == chan)
7595 t4_handle_get_port_info(pi, rpl);
7597 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n", opcode);
7603 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
7607 if (pci_is_pcie(adapter->pdev)) {
7608 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
7609 p->speed = val & PCI_EXP_LNKSTA_CLS;
7610 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
7615 * init_link_config - initialize a link's SW state
7616 * @lc: structure holding the link state
7617 * @caps: link capabilities
7619 * Initializes the SW state maintained for each link, including the link's
7620 * capabilities and default speed/flow-control/autonegotiation settings.
7622 static void init_link_config(struct link_config *lc, unsigned int pcaps,
7625 lc->supported = pcaps;
7626 lc->lp_advertising = 0;
7627 lc->requested_speed = 0;
7629 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
7632 /* For Forward Error Control, we default to whatever the Firmware
7633 * tells us the Link is currently advertising.
7635 if (acaps & FW_PORT_CAP_FEC_RS)
7636 lc->auto_fec |= FEC_RS;
7637 if (acaps & FW_PORT_CAP_FEC_BASER_RS)
7638 lc->auto_fec |= FEC_BASER_RS;
7639 lc->requested_fec = FEC_AUTO;
7640 lc->fec = lc->auto_fec;
7642 if (lc->supported & FW_PORT_CAP_ANEG) {
7643 lc->advertising = lc->supported & ADVERT_MASK;
7644 lc->autoneg = AUTONEG_ENABLE;
7645 lc->requested_fc |= PAUSE_AUTONEG;
7647 lc->advertising = 0;
7648 lc->autoneg = AUTONEG_DISABLE;
7652 #define CIM_PF_NOACCESS 0xeeeeeeee
7654 int t4_wait_dev_ready(void __iomem *regs)
7658 whoami = readl(regs + PL_WHOAMI_A);
7659 if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
7663 whoami = readl(regs + PL_WHOAMI_A);
7664 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
7668 u32 vendor_and_model_id;
7672 static int get_flash_params(struct adapter *adap)
7674 /* Table for non-Numonix supported flash parts. Numonix parts are left
7675 * to the preexisting code. All flash parts have 64KB sectors.
7677 static struct flash_desc supported_flash[] = {
7678 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
7684 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
7686 ret = sf1_read(adap, 3, 0, 1, &info);
7687 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */
7691 for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret)
7692 if (supported_flash[ret].vendor_and_model_id == info) {
7693 adap->params.sf_size = supported_flash[ret].size_mb;
7694 adap->params.sf_nsec =
7695 adap->params.sf_size / SF_SEC_SIZE;
7699 if ((info & 0xff) != 0x20) /* not a Numonix flash */
7701 info >>= 16; /* log2 of size */
7702 if (info >= 0x14 && info < 0x18)
7703 adap->params.sf_nsec = 1 << (info - 16);
7704 else if (info == 0x18)
7705 adap->params.sf_nsec = 64;
7708 adap->params.sf_size = 1 << info;
7709 adap->params.sf_fw_start =
7710 t4_read_reg(adap, CIM_BOOT_CFG_A) & BOOTADDR_M;
7712 if (adap->params.sf_size < FLASH_MIN_SIZE)
7713 dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n",
7714 adap->params.sf_size, FLASH_MIN_SIZE);
7718 static void set_pcie_completion_timeout(struct adapter *adapter, u8 range)
7723 pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
7725 pci_read_config_word(adapter->pdev,
7726 pcie_cap + PCI_EXP_DEVCTL2, &val);
7727 val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
7729 pci_write_config_word(adapter->pdev,
7730 pcie_cap + PCI_EXP_DEVCTL2, val);
7735 * t4_prep_adapter - prepare SW and HW for operation
7736 * @adapter: the adapter
7737 * @reset: if true perform a HW reset
7739 * Initialize adapter SW state for the various HW modules, set initial
7740 * values for some adapter tunables, take PHYs out of reset, and
7741 * initialize the MDIO interface.
7743 int t4_prep_adapter(struct adapter *adapter)
7749 get_pci_mode(adapter, &adapter->params.pci);
7750 pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
7752 ret = get_flash_params(adapter);
7754 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
7758 /* Retrieve adapter's device ID
7760 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
7761 ver = device_id >> 12;
7762 adapter->params.chip = 0;
7765 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
7766 adapter->params.arch.sge_fl_db = DBPRIO_F;
7767 adapter->params.arch.mps_tcam_size =
7768 NUM_MPS_CLS_SRAM_L_INSTANCES;
7769 adapter->params.arch.mps_rplc_size = 128;
7770 adapter->params.arch.nchan = NCHAN;
7771 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7772 adapter->params.arch.vfcount = 128;
7773 /* Congestion map is for 4 channels so that
7774 * MPS can have 4 priority per port.
7776 adapter->params.arch.cng_ch_bits_log = 2;
7779 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
7780 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
7781 adapter->params.arch.mps_tcam_size =
7782 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7783 adapter->params.arch.mps_rplc_size = 128;
7784 adapter->params.arch.nchan = NCHAN;
7785 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7786 adapter->params.arch.vfcount = 128;
7787 adapter->params.arch.cng_ch_bits_log = 2;
7790 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
7791 adapter->params.arch.sge_fl_db = 0;
7792 adapter->params.arch.mps_tcam_size =
7793 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7794 adapter->params.arch.mps_rplc_size = 256;
7795 adapter->params.arch.nchan = 2;
7796 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
7797 adapter->params.arch.vfcount = 256;
7798 /* Congestion map will be for 2 channels so that
7799 * MPS can have 8 priority per port.
7801 adapter->params.arch.cng_ch_bits_log = 3;
7804 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
7809 adapter->params.cim_la_size = CIMLA_SIZE;
7810 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
7813 * Default port for debugging in case we can't reach FW.
7815 adapter->params.nports = 1;
7816 adapter->params.portvec = 1;
7817 adapter->params.vpd.cclk = 50000;
7819 /* Set pci completion timeout value to 4 seconds. */
7820 set_pcie_completion_timeout(adapter, 0xd);
7825 * t4_shutdown_adapter - shut down adapter, host & wire
7826 * @adapter: the adapter
7828 * Perform an emergency shutdown of the adapter and stop it from
7829 * continuing any further communication on the ports or DMA to the
7830 * host. This is typically used when the adapter and/or firmware
7831 * have crashed and we want to prevent any further accidental
7832 * communication with the rest of the world. This will also force
7833 * the port Link Status to go down -- if register writes work --
7834 * which should help our peers figure out that we're down.
7836 int t4_shutdown_adapter(struct adapter *adapter)
7840 t4_intr_disable(adapter);
7841 t4_write_reg(adapter, DBG_GPIO_EN_A, 0);
7842 for_each_port(adapter, port) {
7843 u32 a_port_cfg = is_t4(adapter->params.chip) ?
7844 PORT_REG(port, XGMAC_PORT_CFG_A) :
7845 T5_PORT_REG(port, MAC_PORT_CFG_A);
7847 t4_write_reg(adapter, a_port_cfg,
7848 t4_read_reg(adapter, a_port_cfg)
7849 & ~SIGNAL_DET_V(1));
7851 t4_set_reg_field(adapter, SGE_CONTROL_A, GLOBALENABLE_F, 0);
7857 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
7858 * @adapter: the adapter
7859 * @qid: the Queue ID
7860 * @qtype: the Ingress or Egress type for @qid
7861 * @user: true if this request is for a user mode queue
7862 * @pbar2_qoffset: BAR2 Queue Offset
7863 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
7865 * Returns the BAR2 SGE Queue Registers information associated with the
7866 * indicated Absolute Queue ID. These are passed back in return value
7867 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
7868 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
7870 * This may return an error which indicates that BAR2 SGE Queue
7871 * registers aren't available. If an error is not returned, then the
7872 * following values are returned:
7874 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
7875 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
7877 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
7878 * require the "Inferred Queue ID" ability may be used. E.g. the
7879 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
7880 * then these "Inferred Queue ID" register may not be used.
7882 int t4_bar2_sge_qregs(struct adapter *adapter,
7884 enum t4_bar2_qtype qtype,
7887 unsigned int *pbar2_qid)
7889 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
7890 u64 bar2_page_offset, bar2_qoffset;
7891 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
7893 /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
7894 if (!user && is_t4(adapter->params.chip))
7897 /* Get our SGE Page Size parameters.
7899 page_shift = adapter->params.sge.hps + 10;
7900 page_size = 1 << page_shift;
7902 /* Get the right Queues per Page parameters for our Queue.
7904 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
7905 ? adapter->params.sge.eq_qpp
7906 : adapter->params.sge.iq_qpp);
7907 qpp_mask = (1 << qpp_shift) - 1;
7909 /* Calculate the basics of the BAR2 SGE Queue register area:
7910 * o The BAR2 page the Queue registers will be in.
7911 * o The BAR2 Queue ID.
7912 * o The BAR2 Queue ID Offset into the BAR2 page.
7914 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
7915 bar2_qid = qid & qpp_mask;
7916 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
7918 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
7919 * hardware will infer the Absolute Queue ID simply from the writes to
7920 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
7921 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
7922 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
7923 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
7924 * from the BAR2 Page and BAR2 Queue ID.
7926 * One important censequence of this is that some BAR2 SGE registers
7927 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
7928 * there. But other registers synthesize the SGE Queue ID purely
7929 * from the writes to the registers -- the Write Combined Doorbell
7930 * Buffer is a good example. These BAR2 SGE Registers are only
7931 * available for those BAR2 SGE Register areas where the SGE Absolute
7932 * Queue ID can be inferred from simple writes.
7934 bar2_qoffset = bar2_page_offset;
7935 bar2_qinferred = (bar2_qid_offset < page_size);
7936 if (bar2_qinferred) {
7937 bar2_qoffset += bar2_qid_offset;
7941 *pbar2_qoffset = bar2_qoffset;
7942 *pbar2_qid = bar2_qid;
7947 * t4_init_devlog_params - initialize adapter->params.devlog
7948 * @adap: the adapter
7950 * Initialize various fields of the adapter's Firmware Device Log
7951 * Parameters structure.
7953 int t4_init_devlog_params(struct adapter *adap)
7955 struct devlog_params *dparams = &adap->params.devlog;
7957 unsigned int devlog_meminfo;
7958 struct fw_devlog_cmd devlog_cmd;
7961 /* If we're dealing with newer firmware, the Device Log Paramerters
7962 * are stored in a designated register which allows us to access the
7963 * Device Log even if we can't talk to the firmware.
7966 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
7968 unsigned int nentries, nentries128;
7970 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
7971 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
7973 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
7974 nentries = (nentries128 + 1) * 128;
7975 dparams->size = nentries * sizeof(struct fw_devlog_e);
7980 /* Otherwise, ask the firmware for it's Device Log Parameters.
7982 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
7983 devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
7984 FW_CMD_REQUEST_F | FW_CMD_READ_F);
7985 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
7986 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
7992 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
7993 dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
7994 dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
7995 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
8001 * t4_init_sge_params - initialize adap->params.sge
8002 * @adapter: the adapter
8004 * Initialize various fields of the adapter's SGE Parameters structure.
8006 int t4_init_sge_params(struct adapter *adapter)
8008 struct sge_params *sge_params = &adapter->params.sge;
8010 unsigned int s_hps, s_qpp;
8012 /* Extract the SGE Page Size for our PF.
8014 hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
8015 s_hps = (HOSTPAGESIZEPF0_S +
8016 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
8017 sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
8019 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
8021 s_qpp = (QUEUESPERPAGEPF0_S +
8022 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
8023 qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
8024 sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
8025 qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
8026 sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
8032 * t4_init_tp_params - initialize adap->params.tp
8033 * @adap: the adapter
8035 * Initialize various fields of the adapter's TP Parameters structure.
8037 int t4_init_tp_params(struct adapter *adap)
8042 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
8043 adap->params.tp.tre = TIMERRESOLUTION_G(v);
8044 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
8046 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
8047 for (chan = 0; chan < NCHAN; chan++)
8048 adap->params.tp.tx_modq[chan] = chan;
8050 /* Cache the adapter's Compressed Filter Mode and global Incress
8053 if (t4_use_ldst(adap)) {
8054 t4_fw_tp_pio_rw(adap, &adap->params.tp.vlan_pri_map, 1,
8055 TP_VLAN_PRI_MAP_A, 1);
8056 t4_fw_tp_pio_rw(adap, &adap->params.tp.ingress_config, 1,
8057 TP_INGRESS_CONFIG_A, 1);
8059 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
8060 &adap->params.tp.vlan_pri_map, 1,
8062 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
8063 &adap->params.tp.ingress_config, 1,
8064 TP_INGRESS_CONFIG_A);
8066 /* For T6, cache the adapter's compressed error vector
8067 * and passing outer header info for encapsulated packets.
8069 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
8070 v = t4_read_reg(adap, TP_OUT_CONFIG_A);
8071 adap->params.tp.rx_pkt_encap = (v & CRXPKTENC_F) ? 1 : 0;
8074 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
8075 * shift positions of several elements of the Compressed Filter Tuple
8076 * for this adapter which we need frequently ...
8078 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
8079 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
8080 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
8081 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
8084 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
8085 * represents the presence of an Outer VLAN instead of a VNIC ID.
8087 if ((adap->params.tp.ingress_config & VNIC_F) == 0)
8088 adap->params.tp.vnic_shift = -1;
8094 * t4_filter_field_shift - calculate filter field shift
8095 * @adap: the adapter
8096 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
8098 * Return the shift position of a filter field within the Compressed
8099 * Filter Tuple. The filter field is specified via its selection bit
8100 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
8102 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
8104 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
8108 if ((filter_mode & filter_sel) == 0)
8111 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
8112 switch (filter_mode & sel) {
8114 field_shift += FT_FCOE_W;
8117 field_shift += FT_PORT_W;
8120 field_shift += FT_VNIC_ID_W;
8123 field_shift += FT_VLAN_W;
8126 field_shift += FT_TOS_W;
8129 field_shift += FT_PROTOCOL_W;
8132 field_shift += FT_ETHERTYPE_W;
8135 field_shift += FT_MACMATCH_W;
8138 field_shift += FT_MPSHITTYPE_W;
8140 case FRAGMENTATION_F:
8141 field_shift += FT_FRAGMENTATION_W;
8148 int t4_init_rss_mode(struct adapter *adap, int mbox)
8151 struct fw_rss_vi_config_cmd rvc;
8153 memset(&rvc, 0, sizeof(rvc));
8155 for_each_port(adap, i) {
8156 struct port_info *p = adap2pinfo(adap, i);
8159 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
8160 FW_CMD_REQUEST_F | FW_CMD_READ_F |
8161 FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
8162 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
8163 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
8166 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
8172 * t4_init_portinfo - allocate a virtual interface amd initialize port_info
8173 * @pi: the port_info
8174 * @mbox: mailbox to use for the FW command
8175 * @port: physical port associated with the VI
8176 * @pf: the PF owning the VI
8177 * @vf: the VF owning the VI
8178 * @mac: the MAC address of the VI
8180 * Allocates a virtual interface for the given physical port. If @mac is
8181 * not %NULL it contains the MAC address of the VI as assigned by FW.
8182 * @mac should be large enough to hold an Ethernet address.
8183 * Returns < 0 on error.
8185 int t4_init_portinfo(struct port_info *pi, int mbox,
8186 int port, int pf, int vf, u8 mac[])
8189 struct fw_port_cmd c;
8190 unsigned int rss_size;
8192 memset(&c, 0, sizeof(c));
8193 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8194 FW_CMD_REQUEST_F | FW_CMD_READ_F |
8195 FW_PORT_CMD_PORTID_V(port));
8196 c.action_to_len16 = cpu_to_be32(
8197 FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) |
8199 ret = t4_wr_mbox(pi->adapter, mbox, &c, sizeof(c), &c);
8203 ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size);
8210 pi->rss_size = rss_size;
8212 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
8213 pi->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP_F) ?
8214 FW_PORT_CMD_MDIOADDR_G(ret) : -1;
8215 pi->port_type = FW_PORT_CMD_PTYPE_G(ret);
8216 pi->mod_type = FW_PORT_MOD_TYPE_NA;
8218 init_link_config(&pi->link_cfg, be16_to_cpu(c.u.info.pcap),
8219 be16_to_cpu(c.u.info.acap));
8223 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
8228 for_each_port(adap, i) {
8229 struct port_info *pi = adap2pinfo(adap, i);
8231 while ((adap->params.portvec & (1 << j)) == 0)
8234 ret = t4_init_portinfo(pi, mbox, j, pf, vf, addr);
8238 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
8245 * t4_read_cimq_cfg - read CIM queue configuration
8246 * @adap: the adapter
8247 * @base: holds the queue base addresses in bytes
8248 * @size: holds the queue sizes in bytes
8249 * @thres: holds the queue full thresholds in bytes
8251 * Returns the current configuration of the CIM queues, starting with
8252 * the IBQs, then the OBQs.
8254 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
8257 int cim_num_obq = is_t4(adap->params.chip) ?
8258 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
8260 for (i = 0; i < CIM_NUM_IBQ; i++) {
8261 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
8263 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
8264 /* value is in 256-byte units */
8265 *base++ = CIMQBASE_G(v) * 256;
8266 *size++ = CIMQSIZE_G(v) * 256;
8267 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
8269 for (i = 0; i < cim_num_obq; i++) {
8270 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
8272 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
8273 /* value is in 256-byte units */
8274 *base++ = CIMQBASE_G(v) * 256;
8275 *size++ = CIMQSIZE_G(v) * 256;
8280 * t4_read_cim_ibq - read the contents of a CIM inbound queue
8281 * @adap: the adapter
8282 * @qid: the queue index
8283 * @data: where to store the queue contents
8284 * @n: capacity of @data in 32-bit words
8286 * Reads the contents of the selected CIM queue starting at address 0 up
8287 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
8288 * error and the number of 32-bit words actually read on success.
8290 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
8292 int i, err, attempts;
8294 const unsigned int nwords = CIM_IBQ_SIZE * 4;
8296 if (qid > 5 || (n & 3))
8299 addr = qid * nwords;
8303 /* It might take 3-10ms before the IBQ debug read access is allowed.
8304 * Wait for 1 Sec with a delay of 1 usec.
8308 for (i = 0; i < n; i++, addr++) {
8309 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
8311 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
8315 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
8317 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
8322 * t4_read_cim_obq - read the contents of a CIM outbound queue
8323 * @adap: the adapter
8324 * @qid: the queue index
8325 * @data: where to store the queue contents
8326 * @n: capacity of @data in 32-bit words
8328 * Reads the contents of the selected CIM queue starting at address 0 up
8329 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
8330 * error and the number of 32-bit words actually read on success.
8332 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
8335 unsigned int addr, v, nwords;
8336 int cim_num_obq = is_t4(adap->params.chip) ?
8337 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
8339 if ((qid > (cim_num_obq - 1)) || (n & 3))
8342 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
8343 QUENUMSELECT_V(qid));
8344 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
8346 addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */
8347 nwords = CIMQSIZE_G(v) * 64; /* same */
8351 for (i = 0; i < n; i++, addr++) {
8352 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
8354 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
8358 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
8360 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
8365 * t4_cim_read - read a block from CIM internal address space
8366 * @adap: the adapter
8367 * @addr: the start address within the CIM address space
8368 * @n: number of words to read
8369 * @valp: where to store the result
8371 * Reads a block of 4-byte words from the CIM intenal address space.
8373 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
8378 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
8381 for ( ; !ret && n--; addr += 4) {
8382 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
8383 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
8386 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
8392 * t4_cim_write - write a block into CIM internal address space
8393 * @adap: the adapter
8394 * @addr: the start address within the CIM address space
8395 * @n: number of words to write
8396 * @valp: set of values to write
8398 * Writes a block of 4-byte words into the CIM intenal address space.
8400 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
8401 const unsigned int *valp)
8405 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
8408 for ( ; !ret && n--; addr += 4) {
8409 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
8410 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
8411 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
8417 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
8420 return t4_cim_write(adap, addr, 1, &val);
8424 * t4_cim_read_la - read CIM LA capture buffer
8425 * @adap: the adapter
8426 * @la_buf: where to store the LA data
8427 * @wrptr: the HW write pointer within the capture buffer
8429 * Reads the contents of the CIM LA buffer with the most recent entry at
8430 * the end of the returned data and with the entry at @wrptr first.
8431 * We try to leave the LA in the running state we find it in.
8433 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
8436 unsigned int cfg, val, idx;
8438 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
8442 if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */
8443 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
8448 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
8452 idx = UPDBGLAWRPTR_G(val);
8456 for (i = 0; i < adap->params.cim_la_size; i++) {
8457 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
8458 UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
8461 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
8464 if (val & UPDBGLARDEN_F) {
8468 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
8472 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
8473 * identify the 32-bit portion of the full 312-bit data
8475 if (is_t6(adap->params.chip) && (idx & 0xf) >= 9)
8476 idx = (idx & 0xff0) + 0x10;
8479 /* address can't exceed 0xfff */
8480 idx &= UPDBGLARDPTR_M;
8483 if (cfg & UPDBGLAEN_F) {
8484 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
8485 cfg & ~UPDBGLARDEN_F);
8493 * t4_tp_read_la - read TP LA capture buffer
8494 * @adap: the adapter
8495 * @la_buf: where to store the LA data
8496 * @wrptr: the HW write pointer within the capture buffer
8498 * Reads the contents of the TP LA buffer with the most recent entry at
8499 * the end of the returned data and with the entry at @wrptr first.
8500 * We leave the LA in the running state we find it in.
8502 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
8504 bool last_incomplete;
8505 unsigned int i, cfg, val, idx;
8507 cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
8508 if (cfg & DBGLAENABLE_F) /* freeze LA */
8509 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
8510 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
8512 val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
8513 idx = DBGLAWPTR_G(val);
8514 last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
8515 if (last_incomplete)
8516 idx = (idx + 1) & DBGLARPTR_M;
8521 val &= ~DBGLARPTR_V(DBGLARPTR_M);
8522 val |= adap->params.tp.la_mask;
8524 for (i = 0; i < TPLA_SIZE; i++) {
8525 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
8526 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
8527 idx = (idx + 1) & DBGLARPTR_M;
8530 /* Wipe out last entry if it isn't valid */
8531 if (last_incomplete)
8532 la_buf[TPLA_SIZE - 1] = ~0ULL;
8534 if (cfg & DBGLAENABLE_F) /* restore running state */
8535 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
8536 cfg | adap->params.tp.la_mask);
8539 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
8540 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
8541 * state for more than the Warning Threshold then we'll issue a warning about
8542 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
8543 * appears to be hung every Warning Repeat second till the situation clears.
8544 * If the situation clears, we'll note that as well.
8546 #define SGE_IDMA_WARN_THRESH 1
8547 #define SGE_IDMA_WARN_REPEAT 300
8550 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
8551 * @adapter: the adapter
8552 * @idma: the adapter IDMA Monitor state
8554 * Initialize the state of an SGE Ingress DMA Monitor.
8556 void t4_idma_monitor_init(struct adapter *adapter,
8557 struct sge_idma_monitor_state *idma)
8559 /* Initialize the state variables for detecting an SGE Ingress DMA
8560 * hang. The SGE has internal counters which count up on each clock
8561 * tick whenever the SGE finds its Ingress DMA State Engines in the
8562 * same state they were on the previous clock tick. The clock used is
8563 * the Core Clock so we have a limit on the maximum "time" they can
8564 * record; typically a very small number of seconds. For instance,
8565 * with a 600MHz Core Clock, we can only count up to a bit more than
8566 * 7s. So we'll synthesize a larger counter in order to not run the
8567 * risk of having the "timers" overflow and give us the flexibility to
8568 * maintain a Hung SGE State Machine of our own which operates across
8569 * a longer time frame.
8571 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
8572 idma->idma_stalled[0] = 0;
8573 idma->idma_stalled[1] = 0;
8577 * t4_idma_monitor - monitor SGE Ingress DMA state
8578 * @adapter: the adapter
8579 * @idma: the adapter IDMA Monitor state
8580 * @hz: number of ticks/second
8581 * @ticks: number of ticks since the last IDMA Monitor call
8583 void t4_idma_monitor(struct adapter *adapter,
8584 struct sge_idma_monitor_state *idma,
8587 int i, idma_same_state_cnt[2];
8589 /* Read the SGE Debug Ingress DMA Same State Count registers. These
8590 * are counters inside the SGE which count up on each clock when the
8591 * SGE finds its Ingress DMA State Engines in the same states they
8592 * were in the previous clock. The counters will peg out at
8593 * 0xffffffff without wrapping around so once they pass the 1s
8594 * threshold they'll stay above that till the IDMA state changes.
8596 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
8597 idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
8598 idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8600 for (i = 0; i < 2; i++) {
8601 u32 debug0, debug11;
8603 /* If the Ingress DMA Same State Counter ("timer") is less
8604 * than 1s, then we can reset our synthesized Stall Timer and
8605 * continue. If we have previously emitted warnings about a
8606 * potential stalled Ingress Queue, issue a note indicating
8607 * that the Ingress Queue has resumed forward progress.
8609 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
8610 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
8611 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
8612 "resumed after %d seconds\n",
8613 i, idma->idma_qid[i],
8614 idma->idma_stalled[i] / hz);
8615 idma->idma_stalled[i] = 0;
8619 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
8620 * domain. The first time we get here it'll be because we
8621 * passed the 1s Threshold; each additional time it'll be
8622 * because the RX Timer Callback is being fired on its regular
8625 * If the stall is below our Potential Hung Ingress Queue
8626 * Warning Threshold, continue.
8628 if (idma->idma_stalled[i] == 0) {
8629 idma->idma_stalled[i] = hz;
8630 idma->idma_warn[i] = 0;
8632 idma->idma_stalled[i] += ticks;
8633 idma->idma_warn[i] -= ticks;
8636 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
8639 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
8641 if (idma->idma_warn[i] > 0)
8643 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
8645 /* Read and save the SGE IDMA State and Queue ID information.
8646 * We do this every time in case it changes across time ...
8647 * can't be too careful ...
8649 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
8650 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8651 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
8653 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
8654 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8655 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
8657 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
8658 "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
8659 i, idma->idma_qid[i], idma->idma_state[i],
8660 idma->idma_stalled[i] / hz,
8662 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
8667 * t4_set_vf_mac - Set MAC address for the specified VF
8668 * @adapter: The adapter
8669 * @vf: one of the VFs instantiated by the specified PF
8670 * @naddr: the number of MAC addresses
8671 * @addr: the MAC address(es) to be set to the specified VF
8673 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
8674 unsigned int naddr, u8 *addr)
8676 struct fw_acl_mac_cmd cmd;
8678 memset(&cmd, 0, sizeof(cmd));
8679 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD) |
8682 FW_ACL_MAC_CMD_PFN_V(adapter->pf) |
8683 FW_ACL_MAC_CMD_VFN_V(vf));
8685 /* Note: Do not enable the ACL */
8686 cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
8689 switch (adapter->pf) {
8691 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3));
8694 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2));
8697 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1));
8700 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0));
8704 return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
8707 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
8708 int rateunit, int ratemode, int channel, int class,
8709 int minrate, int maxrate, int weight, int pktsize)
8711 struct fw_sched_cmd cmd;
8713 memset(&cmd, 0, sizeof(cmd));
8714 cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_SCHED_CMD) |
8717 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
8719 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
8720 cmd.u.params.type = type;
8721 cmd.u.params.level = level;
8722 cmd.u.params.mode = mode;
8723 cmd.u.params.ch = channel;
8724 cmd.u.params.cl = class;
8725 cmd.u.params.unit = rateunit;
8726 cmd.u.params.rate = ratemode;
8727 cmd.u.params.min = cpu_to_be32(minrate);
8728 cmd.u.params.max = cpu_to_be32(maxrate);
8729 cmd.u.params.weight = cpu_to_be16(weight);
8730 cmd.u.params.pktsize = cpu_to_be16(pktsize);
8732 return t4_wr_mbox_meat(adapter, adapter->mbox, &cmd, sizeof(cmd),