1 /* drivers/net/ethernet/freescale/gianfar.c
3 * Gianfar Ethernet Driver
4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
6 * Based on 8260_io/fcc_enet.c
9 * Maintainer: Kumar Gala
10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
12 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
13 * Copyright 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
67 #include <linux/kernel.h>
68 #include <linux/string.h>
69 #include <linux/errno.h>
70 #include <linux/unistd.h>
71 #include <linux/slab.h>
72 #include <linux/interrupt.h>
73 #include <linux/delay.h>
74 #include <linux/netdevice.h>
75 #include <linux/etherdevice.h>
76 #include <linux/skbuff.h>
77 #include <linux/if_vlan.h>
78 #include <linux/spinlock.h>
80 #include <linux/of_address.h>
81 #include <linux/of_irq.h>
82 #include <linux/of_mdio.h>
83 #include <linux/of_platform.h>
85 #include <linux/tcp.h>
86 #include <linux/udp.h>
88 #include <linux/net_tstamp.h>
93 #include <asm/mpc85xx.h>
96 #include <asm/uaccess.h>
97 #include <linux/module.h>
98 #include <linux/dma-mapping.h>
99 #include <linux/crc32.h>
100 #include <linux/mii.h>
101 #include <linux/phy.h>
102 #include <linux/phy_fixed.h>
103 #include <linux/of.h>
104 #include <linux/of_net.h>
105 #include <linux/of_address.h>
106 #include <linux/of_irq.h>
110 #define TX_TIMEOUT (1*HZ)
112 const char gfar_driver_version[] = "1.3";
114 static int gfar_enet_open(struct net_device *dev);
115 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
116 static void gfar_reset_task(struct work_struct *work);
117 static void gfar_timeout(struct net_device *dev);
118 static int gfar_close(struct net_device *dev);
119 static struct sk_buff *gfar_new_skb(struct net_device *dev,
120 dma_addr_t *bufaddr);
121 static int gfar_set_mac_address(struct net_device *dev);
122 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
123 static irqreturn_t gfar_error(int irq, void *dev_id);
124 static irqreturn_t gfar_transmit(int irq, void *dev_id);
125 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
126 static void adjust_link(struct net_device *dev);
127 static noinline void gfar_update_link_state(struct gfar_private *priv);
128 static int init_phy(struct net_device *dev);
129 static int gfar_probe(struct platform_device *ofdev);
130 static int gfar_remove(struct platform_device *ofdev);
131 static void free_skb_resources(struct gfar_private *priv);
132 static void gfar_set_multi(struct net_device *dev);
133 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
134 static void gfar_configure_serdes(struct net_device *dev);
135 static int gfar_poll_rx(struct napi_struct *napi, int budget);
136 static int gfar_poll_tx(struct napi_struct *napi, int budget);
137 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget);
138 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget);
139 #ifdef CONFIG_NET_POLL_CONTROLLER
140 static void gfar_netpoll(struct net_device *dev);
142 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
143 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
144 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
145 int amount_pull, struct napi_struct *napi);
146 static void gfar_halt_nodisable(struct gfar_private *priv);
147 static void gfar_clear_exact_match(struct net_device *dev);
148 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
150 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
152 MODULE_AUTHOR("Freescale Semiconductor, Inc");
153 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
154 MODULE_LICENSE("GPL");
156 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
161 bdp->bufPtr = cpu_to_be32(buf);
163 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
164 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
165 lstatus |= BD_LFLAG(RXBD_WRAP);
169 bdp->lstatus = cpu_to_be32(lstatus);
172 static int gfar_init_bds(struct net_device *ndev)
174 struct gfar_private *priv = netdev_priv(ndev);
175 struct gfar __iomem *regs = priv->gfargrp[0].regs;
176 struct gfar_priv_tx_q *tx_queue = NULL;
177 struct gfar_priv_rx_q *rx_queue = NULL;
184 for (i = 0; i < priv->num_tx_queues; i++) {
185 tx_queue = priv->tx_queue[i];
186 /* Initialize some variables in our dev structure */
187 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
188 tx_queue->dirty_tx = tx_queue->tx_bd_base;
189 tx_queue->cur_tx = tx_queue->tx_bd_base;
190 tx_queue->skb_curtx = 0;
191 tx_queue->skb_dirtytx = 0;
193 /* Initialize Transmit Descriptor Ring */
194 txbdp = tx_queue->tx_bd_base;
195 for (j = 0; j < tx_queue->tx_ring_size; j++) {
201 /* Set the last descriptor in the ring to indicate wrap */
203 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) |
207 rfbptr = ®s->rfbptr0;
208 for (i = 0; i < priv->num_rx_queues; i++) {
209 rx_queue = priv->rx_queue[i];
210 rx_queue->cur_rx = rx_queue->rx_bd_base;
211 rx_queue->skb_currx = 0;
212 rxbdp = rx_queue->rx_bd_base;
214 for (j = 0; j < rx_queue->rx_ring_size; j++) {
215 struct sk_buff *skb = rx_queue->rx_skbuff[j];
218 bufaddr = be32_to_cpu(rxbdp->bufPtr);
220 skb = gfar_new_skb(ndev, &bufaddr);
222 netdev_err(ndev, "Can't allocate RX buffers\n");
225 rx_queue->rx_skbuff[j] = skb;
228 gfar_init_rxbdp(rx_queue, rxbdp, bufaddr);
232 rx_queue->rfbptr = rfbptr;
239 static int gfar_alloc_skb_resources(struct net_device *ndev)
244 struct gfar_private *priv = netdev_priv(ndev);
245 struct device *dev = priv->dev;
246 struct gfar_priv_tx_q *tx_queue = NULL;
247 struct gfar_priv_rx_q *rx_queue = NULL;
249 priv->total_tx_ring_size = 0;
250 for (i = 0; i < priv->num_tx_queues; i++)
251 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
253 priv->total_rx_ring_size = 0;
254 for (i = 0; i < priv->num_rx_queues; i++)
255 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
257 /* Allocate memory for the buffer descriptors */
258 vaddr = dma_alloc_coherent(dev,
259 (priv->total_tx_ring_size *
260 sizeof(struct txbd8)) +
261 (priv->total_rx_ring_size *
262 sizeof(struct rxbd8)),
267 for (i = 0; i < priv->num_tx_queues; i++) {
268 tx_queue = priv->tx_queue[i];
269 tx_queue->tx_bd_base = vaddr;
270 tx_queue->tx_bd_dma_base = addr;
271 tx_queue->dev = ndev;
272 /* enet DMA only understands physical addresses */
273 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
274 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
277 /* Start the rx descriptor ring where the tx ring leaves off */
278 for (i = 0; i < priv->num_rx_queues; i++) {
279 rx_queue = priv->rx_queue[i];
280 rx_queue->rx_bd_base = vaddr;
281 rx_queue->rx_bd_dma_base = addr;
282 rx_queue->dev = ndev;
283 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
284 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
287 /* Setup the skbuff rings */
288 for (i = 0; i < priv->num_tx_queues; i++) {
289 tx_queue = priv->tx_queue[i];
290 tx_queue->tx_skbuff =
291 kmalloc_array(tx_queue->tx_ring_size,
292 sizeof(*tx_queue->tx_skbuff),
294 if (!tx_queue->tx_skbuff)
297 for (k = 0; k < tx_queue->tx_ring_size; k++)
298 tx_queue->tx_skbuff[k] = NULL;
301 for (i = 0; i < priv->num_rx_queues; i++) {
302 rx_queue = priv->rx_queue[i];
303 rx_queue->rx_skbuff =
304 kmalloc_array(rx_queue->rx_ring_size,
305 sizeof(*rx_queue->rx_skbuff),
307 if (!rx_queue->rx_skbuff)
310 for (j = 0; j < rx_queue->rx_ring_size; j++)
311 rx_queue->rx_skbuff[j] = NULL;
314 if (gfar_init_bds(ndev))
320 free_skb_resources(priv);
324 static void gfar_init_tx_rx_base(struct gfar_private *priv)
326 struct gfar __iomem *regs = priv->gfargrp[0].regs;
330 baddr = ®s->tbase0;
331 for (i = 0; i < priv->num_tx_queues; i++) {
332 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
336 baddr = ®s->rbase0;
337 for (i = 0; i < priv->num_rx_queues; i++) {
338 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
343 static void gfar_init_rqprm(struct gfar_private *priv)
345 struct gfar __iomem *regs = priv->gfargrp[0].regs;
349 baddr = ®s->rqprm0;
350 for (i = 0; i < priv->num_rx_queues; i++) {
351 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
352 (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
357 static void gfar_rx_buff_size_config(struct gfar_private *priv)
359 int frame_size = priv->ndev->mtu + ETH_HLEN + ETH_FCS_LEN;
361 /* set this when rx hw offload (TOE) functions are being used */
362 priv->uses_rxfcb = 0;
364 if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
365 priv->uses_rxfcb = 1;
367 if (priv->hwts_rx_en)
368 priv->uses_rxfcb = 1;
370 if (priv->uses_rxfcb)
371 frame_size += GMAC_FCB_LEN;
373 frame_size += priv->padding;
375 frame_size = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
376 INCREMENTAL_BUFFER_SIZE;
378 priv->rx_buffer_size = frame_size;
381 static void gfar_mac_rx_config(struct gfar_private *priv)
383 struct gfar __iomem *regs = priv->gfargrp[0].regs;
386 if (priv->rx_filer_enable) {
387 rctrl |= RCTRL_FILREN;
388 /* Program the RIR0 reg with the required distribution */
389 if (priv->poll_mode == GFAR_SQ_POLLING)
390 gfar_write(®s->rir0, DEFAULT_2RXQ_RIR0);
391 else /* GFAR_MQ_POLLING */
392 gfar_write(®s->rir0, DEFAULT_8RXQ_RIR0);
395 /* Restore PROMISC mode */
396 if (priv->ndev->flags & IFF_PROMISC)
399 if (priv->ndev->features & NETIF_F_RXCSUM)
400 rctrl |= RCTRL_CHECKSUMMING;
402 if (priv->extended_hash)
403 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
406 rctrl &= ~RCTRL_PAL_MASK;
407 rctrl |= RCTRL_PADDING(priv->padding);
410 /* Enable HW time stamping if requested from user space */
411 if (priv->hwts_rx_en)
412 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
414 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
415 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
417 /* Clear the LFC bit */
418 gfar_write(®s->rctrl, rctrl);
419 /* Init flow control threshold values */
420 gfar_init_rqprm(priv);
421 gfar_write(®s->ptv, DEFAULT_LFC_PTVVAL);
424 /* Init rctrl based on our settings */
425 gfar_write(®s->rctrl, rctrl);
428 static void gfar_mac_tx_config(struct gfar_private *priv)
430 struct gfar __iomem *regs = priv->gfargrp[0].regs;
433 if (priv->ndev->features & NETIF_F_IP_CSUM)
434 tctrl |= TCTRL_INIT_CSUM;
436 if (priv->prio_sched_en)
437 tctrl |= TCTRL_TXSCHED_PRIO;
439 tctrl |= TCTRL_TXSCHED_WRRS;
440 gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT);
441 gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT);
444 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
445 tctrl |= TCTRL_VLINS;
447 gfar_write(®s->tctrl, tctrl);
450 static void gfar_configure_coalescing(struct gfar_private *priv,
451 unsigned long tx_mask, unsigned long rx_mask)
453 struct gfar __iomem *regs = priv->gfargrp[0].regs;
456 if (priv->mode == MQ_MG_MODE) {
459 baddr = ®s->txic0;
460 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
461 gfar_write(baddr + i, 0);
462 if (likely(priv->tx_queue[i]->txcoalescing))
463 gfar_write(baddr + i, priv->tx_queue[i]->txic);
466 baddr = ®s->rxic0;
467 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
468 gfar_write(baddr + i, 0);
469 if (likely(priv->rx_queue[i]->rxcoalescing))
470 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
473 /* Backward compatible case -- even if we enable
474 * multiple queues, there's only single reg to program
476 gfar_write(®s->txic, 0);
477 if (likely(priv->tx_queue[0]->txcoalescing))
478 gfar_write(®s->txic, priv->tx_queue[0]->txic);
480 gfar_write(®s->rxic, 0);
481 if (unlikely(priv->rx_queue[0]->rxcoalescing))
482 gfar_write(®s->rxic, priv->rx_queue[0]->rxic);
486 void gfar_configure_coalescing_all(struct gfar_private *priv)
488 gfar_configure_coalescing(priv, 0xFF, 0xFF);
491 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
493 struct gfar_private *priv = netdev_priv(dev);
494 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
495 unsigned long tx_packets = 0, tx_bytes = 0;
498 for (i = 0; i < priv->num_rx_queues; i++) {
499 rx_packets += priv->rx_queue[i]->stats.rx_packets;
500 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
501 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
504 dev->stats.rx_packets = rx_packets;
505 dev->stats.rx_bytes = rx_bytes;
506 dev->stats.rx_dropped = rx_dropped;
508 for (i = 0; i < priv->num_tx_queues; i++) {
509 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
510 tx_packets += priv->tx_queue[i]->stats.tx_packets;
513 dev->stats.tx_bytes = tx_bytes;
514 dev->stats.tx_packets = tx_packets;
519 static int gfar_set_mac_addr(struct net_device *dev, void *p)
521 eth_mac_addr(dev, p);
523 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
528 static const struct net_device_ops gfar_netdev_ops = {
529 .ndo_open = gfar_enet_open,
530 .ndo_start_xmit = gfar_start_xmit,
531 .ndo_stop = gfar_close,
532 .ndo_change_mtu = gfar_change_mtu,
533 .ndo_set_features = gfar_set_features,
534 .ndo_set_rx_mode = gfar_set_multi,
535 .ndo_tx_timeout = gfar_timeout,
536 .ndo_do_ioctl = gfar_ioctl,
537 .ndo_get_stats = gfar_get_stats,
538 .ndo_set_mac_address = gfar_set_mac_addr,
539 .ndo_validate_addr = eth_validate_addr,
540 #ifdef CONFIG_NET_POLL_CONTROLLER
541 .ndo_poll_controller = gfar_netpoll,
545 static void gfar_ints_disable(struct gfar_private *priv)
548 for (i = 0; i < priv->num_grps; i++) {
549 struct gfar __iomem *regs = priv->gfargrp[i].regs;
551 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
553 /* Initialize IMASK */
554 gfar_write(®s->imask, IMASK_INIT_CLEAR);
558 static void gfar_ints_enable(struct gfar_private *priv)
561 for (i = 0; i < priv->num_grps; i++) {
562 struct gfar __iomem *regs = priv->gfargrp[i].regs;
563 /* Unmask the interrupts we look for */
564 gfar_write(®s->imask, IMASK_DEFAULT);
568 static void lock_tx_qs(struct gfar_private *priv)
572 for (i = 0; i < priv->num_tx_queues; i++)
573 spin_lock(&priv->tx_queue[i]->txlock);
576 static void unlock_tx_qs(struct gfar_private *priv)
580 for (i = 0; i < priv->num_tx_queues; i++)
581 spin_unlock(&priv->tx_queue[i]->txlock);
584 static int gfar_alloc_tx_queues(struct gfar_private *priv)
588 for (i = 0; i < priv->num_tx_queues; i++) {
589 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
591 if (!priv->tx_queue[i])
594 priv->tx_queue[i]->tx_skbuff = NULL;
595 priv->tx_queue[i]->qindex = i;
596 priv->tx_queue[i]->dev = priv->ndev;
597 spin_lock_init(&(priv->tx_queue[i]->txlock));
602 static int gfar_alloc_rx_queues(struct gfar_private *priv)
606 for (i = 0; i < priv->num_rx_queues; i++) {
607 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
609 if (!priv->rx_queue[i])
612 priv->rx_queue[i]->rx_skbuff = NULL;
613 priv->rx_queue[i]->qindex = i;
614 priv->rx_queue[i]->dev = priv->ndev;
619 static void gfar_free_tx_queues(struct gfar_private *priv)
623 for (i = 0; i < priv->num_tx_queues; i++)
624 kfree(priv->tx_queue[i]);
627 static void gfar_free_rx_queues(struct gfar_private *priv)
631 for (i = 0; i < priv->num_rx_queues; i++)
632 kfree(priv->rx_queue[i]);
635 static void unmap_group_regs(struct gfar_private *priv)
639 for (i = 0; i < MAXGROUPS; i++)
640 if (priv->gfargrp[i].regs)
641 iounmap(priv->gfargrp[i].regs);
644 static void free_gfar_dev(struct gfar_private *priv)
648 for (i = 0; i < priv->num_grps; i++)
649 for (j = 0; j < GFAR_NUM_IRQS; j++) {
650 kfree(priv->gfargrp[i].irqinfo[j]);
651 priv->gfargrp[i].irqinfo[j] = NULL;
654 free_netdev(priv->ndev);
657 static void disable_napi(struct gfar_private *priv)
661 for (i = 0; i < priv->num_grps; i++) {
662 napi_disable(&priv->gfargrp[i].napi_rx);
663 napi_disable(&priv->gfargrp[i].napi_tx);
667 static void enable_napi(struct gfar_private *priv)
671 for (i = 0; i < priv->num_grps; i++) {
672 napi_enable(&priv->gfargrp[i].napi_rx);
673 napi_enable(&priv->gfargrp[i].napi_tx);
677 static int gfar_parse_group(struct device_node *np,
678 struct gfar_private *priv, const char *model)
680 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
683 for (i = 0; i < GFAR_NUM_IRQS; i++) {
684 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
686 if (!grp->irqinfo[i])
690 grp->regs = of_iomap(np, 0);
694 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
696 /* If we aren't the FEC we have multiple interrupts */
697 if (model && strcasecmp(model, "FEC")) {
698 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
699 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
700 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
701 gfar_irq(grp, RX)->irq == NO_IRQ ||
702 gfar_irq(grp, ER)->irq == NO_IRQ)
707 spin_lock_init(&grp->grplock);
708 if (priv->mode == MQ_MG_MODE) {
709 u32 rxq_mask, txq_mask;
712 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
713 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
715 ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask);
717 grp->rx_bit_map = rxq_mask ?
718 rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
721 ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask);
723 grp->tx_bit_map = txq_mask ?
724 txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
727 if (priv->poll_mode == GFAR_SQ_POLLING) {
728 /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
729 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
730 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
733 grp->rx_bit_map = 0xFF;
734 grp->tx_bit_map = 0xFF;
737 /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
738 * right to left, so we need to revert the 8 bits to get the q index
740 grp->rx_bit_map = bitrev8(grp->rx_bit_map);
741 grp->tx_bit_map = bitrev8(grp->tx_bit_map);
743 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
744 * also assign queues to groups
746 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
748 grp->rx_queue = priv->rx_queue[i];
749 grp->num_rx_queues++;
750 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
751 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
752 priv->rx_queue[i]->grp = grp;
755 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
757 grp->tx_queue = priv->tx_queue[i];
758 grp->num_tx_queues++;
759 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
760 priv->tqueue |= (TQUEUE_EN0 >> i);
761 priv->tx_queue[i]->grp = grp;
769 static int gfar_of_group_count(struct device_node *np)
771 struct device_node *child;
774 for_each_available_child_of_node(np, child)
775 if (!of_node_cmp(child->name, "queue-group"))
781 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
785 const void *mac_addr;
787 struct net_device *dev = NULL;
788 struct gfar_private *priv = NULL;
789 struct device_node *np = ofdev->dev.of_node;
790 struct device_node *child = NULL;
791 struct property *stash;
794 unsigned int num_tx_qs, num_rx_qs;
795 unsigned short mode, poll_mode;
800 if (of_device_is_compatible(np, "fsl,etsec2")) {
802 poll_mode = GFAR_SQ_POLLING;
805 poll_mode = GFAR_SQ_POLLING;
808 if (mode == SQ_SG_MODE) {
811 } else { /* MQ_MG_MODE */
812 /* get the actual number of supported groups */
813 unsigned int num_grps = gfar_of_group_count(np);
815 if (num_grps == 0 || num_grps > MAXGROUPS) {
816 dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
818 pr_err("Cannot do alloc_etherdev, aborting\n");
822 if (poll_mode == GFAR_SQ_POLLING) {
823 num_tx_qs = num_grps; /* one txq per int group */
824 num_rx_qs = num_grps; /* one rxq per int group */
825 } else { /* GFAR_MQ_POLLING */
826 u32 tx_queues, rx_queues;
829 /* parse the num of HW tx and rx queues */
830 ret = of_property_read_u32(np, "fsl,num_tx_queues",
832 num_tx_qs = ret ? 1 : tx_queues;
834 ret = of_property_read_u32(np, "fsl,num_rx_queues",
836 num_rx_qs = ret ? 1 : rx_queues;
840 if (num_tx_qs > MAX_TX_QS) {
841 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
842 num_tx_qs, MAX_TX_QS);
843 pr_err("Cannot do alloc_etherdev, aborting\n");
847 if (num_rx_qs > MAX_RX_QS) {
848 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
849 num_rx_qs, MAX_RX_QS);
850 pr_err("Cannot do alloc_etherdev, aborting\n");
854 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
859 priv = netdev_priv(dev);
863 priv->poll_mode = poll_mode;
865 priv->num_tx_queues = num_tx_qs;
866 netif_set_real_num_rx_queues(dev, num_rx_qs);
867 priv->num_rx_queues = num_rx_qs;
869 err = gfar_alloc_tx_queues(priv);
871 goto tx_alloc_failed;
873 err = gfar_alloc_rx_queues(priv);
875 goto rx_alloc_failed;
877 err = of_property_read_string(np, "model", &model);
879 pr_err("Device model property missing, aborting\n");
880 goto rx_alloc_failed;
883 /* Init Rx queue filer rule set linked list */
884 INIT_LIST_HEAD(&priv->rx_list.list);
885 priv->rx_list.count = 0;
886 mutex_init(&priv->rx_queue_access);
888 for (i = 0; i < MAXGROUPS; i++)
889 priv->gfargrp[i].regs = NULL;
891 /* Parse and initialize group specific information */
892 if (priv->mode == MQ_MG_MODE) {
893 for_each_available_child_of_node(np, child) {
894 if (of_node_cmp(child->name, "queue-group"))
897 err = gfar_parse_group(child, priv, model);
901 } else { /* SQ_SG_MODE */
902 err = gfar_parse_group(np, priv, model);
907 stash = of_find_property(np, "bd-stash", NULL);
910 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
911 priv->bd_stash_en = 1;
914 err = of_property_read_u32(np, "rx-stash-len", &stash_len);
917 priv->rx_stash_size = stash_len;
919 err = of_property_read_u32(np, "rx-stash-idx", &stash_idx);
922 priv->rx_stash_index = stash_idx;
924 if (stash_len || stash_idx)
925 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
927 mac_addr = of_get_mac_address(np);
930 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
932 if (model && !strcasecmp(model, "TSEC"))
933 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
934 FSL_GIANFAR_DEV_HAS_COALESCE |
935 FSL_GIANFAR_DEV_HAS_RMON |
936 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
938 if (model && !strcasecmp(model, "eTSEC"))
939 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
940 FSL_GIANFAR_DEV_HAS_COALESCE |
941 FSL_GIANFAR_DEV_HAS_RMON |
942 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
943 FSL_GIANFAR_DEV_HAS_CSUM |
944 FSL_GIANFAR_DEV_HAS_VLAN |
945 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
946 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
947 FSL_GIANFAR_DEV_HAS_TIMER;
949 err = of_property_read_string(np, "phy-connection-type", &ctype);
951 /* We only care about rgmii-id. The rest are autodetected */
952 if (err == 0 && !strcmp(ctype, "rgmii-id"))
953 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
955 priv->interface = PHY_INTERFACE_MODE_MII;
957 if (of_find_property(np, "fsl,magic-packet", NULL))
958 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
960 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
962 /* In the case of a fixed PHY, the DT node associated
963 * to the PHY is the Ethernet MAC DT node.
965 if (!priv->phy_node && of_phy_is_fixed_link(np)) {
966 err = of_phy_register_fixed_link(np);
970 priv->phy_node = of_node_get(np);
973 /* Find the TBI PHY. If it's not there, we don't support SGMII */
974 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
979 unmap_group_regs(priv);
981 gfar_free_rx_queues(priv);
983 gfar_free_tx_queues(priv);
988 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
990 struct hwtstamp_config config;
991 struct gfar_private *priv = netdev_priv(netdev);
993 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
996 /* reserved for future extensions */
1000 switch (config.tx_type) {
1001 case HWTSTAMP_TX_OFF:
1002 priv->hwts_tx_en = 0;
1004 case HWTSTAMP_TX_ON:
1005 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
1007 priv->hwts_tx_en = 1;
1013 switch (config.rx_filter) {
1014 case HWTSTAMP_FILTER_NONE:
1015 if (priv->hwts_rx_en) {
1016 priv->hwts_rx_en = 0;
1021 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
1023 if (!priv->hwts_rx_en) {
1024 priv->hwts_rx_en = 1;
1027 config.rx_filter = HWTSTAMP_FILTER_ALL;
1031 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1035 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
1037 struct hwtstamp_config config;
1038 struct gfar_private *priv = netdev_priv(netdev);
1041 config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1042 config.rx_filter = (priv->hwts_rx_en ?
1043 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
1045 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1049 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1051 struct gfar_private *priv = netdev_priv(dev);
1053 if (!netif_running(dev))
1056 if (cmd == SIOCSHWTSTAMP)
1057 return gfar_hwtstamp_set(dev, rq);
1058 if (cmd == SIOCGHWTSTAMP)
1059 return gfar_hwtstamp_get(dev, rq);
1064 return phy_mii_ioctl(priv->phydev, rq, cmd);
1067 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
1070 u32 rqfpr = FPR_FILER_MASK;
1074 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
1075 priv->ftp_rqfpr[rqfar] = rqfpr;
1076 priv->ftp_rqfcr[rqfar] = rqfcr;
1077 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1080 rqfcr = RQFCR_CMP_NOMATCH;
1081 priv->ftp_rqfpr[rqfar] = rqfpr;
1082 priv->ftp_rqfcr[rqfar] = rqfcr;
1083 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1086 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
1088 priv->ftp_rqfcr[rqfar] = rqfcr;
1089 priv->ftp_rqfpr[rqfar] = rqfpr;
1090 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1093 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
1095 priv->ftp_rqfcr[rqfar] = rqfcr;
1096 priv->ftp_rqfpr[rqfar] = rqfpr;
1097 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1102 static void gfar_init_filer_table(struct gfar_private *priv)
1105 u32 rqfar = MAX_FILER_IDX;
1107 u32 rqfpr = FPR_FILER_MASK;
1110 rqfcr = RQFCR_CMP_MATCH;
1111 priv->ftp_rqfcr[rqfar] = rqfcr;
1112 priv->ftp_rqfpr[rqfar] = rqfpr;
1113 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1115 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
1116 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
1117 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
1118 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
1119 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
1120 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
1122 /* cur_filer_idx indicated the first non-masked rule */
1123 priv->cur_filer_idx = rqfar;
1125 /* Rest are masked rules */
1126 rqfcr = RQFCR_CMP_NOMATCH;
1127 for (i = 0; i < rqfar; i++) {
1128 priv->ftp_rqfcr[i] = rqfcr;
1129 priv->ftp_rqfpr[i] = rqfpr;
1130 gfar_write_filer(priv, i, rqfcr, rqfpr);
1135 static void __gfar_detect_errata_83xx(struct gfar_private *priv)
1137 unsigned int pvr = mfspr(SPRN_PVR);
1138 unsigned int svr = mfspr(SPRN_SVR);
1139 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
1140 unsigned int rev = svr & 0xffff;
1142 /* MPC8313 Rev 2.0 and higher; All MPC837x */
1143 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
1144 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1145 priv->errata |= GFAR_ERRATA_74;
1147 /* MPC8313 and MPC837x all rev */
1148 if ((pvr == 0x80850010 && mod == 0x80b0) ||
1149 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1150 priv->errata |= GFAR_ERRATA_76;
1152 /* MPC8313 Rev < 2.0 */
1153 if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
1154 priv->errata |= GFAR_ERRATA_12;
1157 static void __gfar_detect_errata_85xx(struct gfar_private *priv)
1159 unsigned int svr = mfspr(SPRN_SVR);
1161 if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
1162 priv->errata |= GFAR_ERRATA_12;
1163 if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
1164 ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)))
1165 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
1169 static void gfar_detect_errata(struct gfar_private *priv)
1171 struct device *dev = &priv->ofdev->dev;
1173 /* no plans to fix */
1174 priv->errata |= GFAR_ERRATA_A002;
1177 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
1178 __gfar_detect_errata_85xx(priv);
1179 else /* non-mpc85xx parts, i.e. e300 core based */
1180 __gfar_detect_errata_83xx(priv);
1184 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
1188 void gfar_mac_reset(struct gfar_private *priv)
1190 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1193 /* Reset MAC layer */
1194 gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET);
1196 /* We need to delay at least 3 TX clocks */
1199 /* the soft reset bit is not self-resetting, so we need to
1200 * clear it before resuming normal operation
1202 gfar_write(®s->maccfg1, 0);
1206 /* Compute rx_buff_size based on config flags */
1207 gfar_rx_buff_size_config(priv);
1209 /* Initialize the max receive frame/buffer lengths */
1210 gfar_write(®s->maxfrm, priv->rx_buffer_size);
1211 gfar_write(®s->mrblr, priv->rx_buffer_size);
1213 /* Initialize the Minimum Frame Length Register */
1214 gfar_write(®s->minflr, MINFLR_INIT_SETTINGS);
1216 /* Initialize MACCFG2. */
1217 tempval = MACCFG2_INIT_SETTINGS;
1219 /* If the mtu is larger than the max size for standard
1220 * ethernet frames (ie, a jumbo frame), then set maccfg2
1221 * to allow huge frames, and to check the length
1223 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
1224 gfar_has_errata(priv, GFAR_ERRATA_74))
1225 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1227 gfar_write(®s->maccfg2, tempval);
1229 /* Clear mac addr hash registers */
1230 gfar_write(®s->igaddr0, 0);
1231 gfar_write(®s->igaddr1, 0);
1232 gfar_write(®s->igaddr2, 0);
1233 gfar_write(®s->igaddr3, 0);
1234 gfar_write(®s->igaddr4, 0);
1235 gfar_write(®s->igaddr5, 0);
1236 gfar_write(®s->igaddr6, 0);
1237 gfar_write(®s->igaddr7, 0);
1239 gfar_write(®s->gaddr0, 0);
1240 gfar_write(®s->gaddr1, 0);
1241 gfar_write(®s->gaddr2, 0);
1242 gfar_write(®s->gaddr3, 0);
1243 gfar_write(®s->gaddr4, 0);
1244 gfar_write(®s->gaddr5, 0);
1245 gfar_write(®s->gaddr6, 0);
1246 gfar_write(®s->gaddr7, 0);
1248 if (priv->extended_hash)
1249 gfar_clear_exact_match(priv->ndev);
1251 gfar_mac_rx_config(priv);
1253 gfar_mac_tx_config(priv);
1255 gfar_set_mac_address(priv->ndev);
1257 gfar_set_multi(priv->ndev);
1259 /* clear ievent and imask before configuring coalescing */
1260 gfar_ints_disable(priv);
1262 /* Configure the coalescing support */
1263 gfar_configure_coalescing_all(priv);
1266 static void gfar_hw_init(struct gfar_private *priv)
1268 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1271 /* Stop the DMA engine now, in case it was running before
1272 * (The firmware could have used it, and left it running).
1276 gfar_mac_reset(priv);
1278 /* Zero out the rmon mib registers if it has them */
1279 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1280 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
1282 /* Mask off the CAM interrupts */
1283 gfar_write(®s->rmon.cam1, 0xffffffff);
1284 gfar_write(®s->rmon.cam2, 0xffffffff);
1287 /* Initialize ECNTRL */
1288 gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS);
1290 /* Set the extraction length and index */
1291 attrs = ATTRELI_EL(priv->rx_stash_size) |
1292 ATTRELI_EI(priv->rx_stash_index);
1294 gfar_write(®s->attreli, attrs);
1296 /* Start with defaults, and add stashing
1297 * depending on driver parameters
1299 attrs = ATTR_INIT_SETTINGS;
1301 if (priv->bd_stash_en)
1302 attrs |= ATTR_BDSTASH;
1304 if (priv->rx_stash_size != 0)
1305 attrs |= ATTR_BUFSTASH;
1307 gfar_write(®s->attr, attrs);
1310 gfar_write(®s->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
1311 gfar_write(®s->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
1312 gfar_write(®s->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
1314 /* Program the interrupt steering regs, only for MG devices */
1315 if (priv->num_grps > 1)
1316 gfar_write_isrg(priv);
1319 static void gfar_init_addr_hash_table(struct gfar_private *priv)
1321 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1323 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1324 priv->extended_hash = 1;
1325 priv->hash_width = 9;
1327 priv->hash_regs[0] = ®s->igaddr0;
1328 priv->hash_regs[1] = ®s->igaddr1;
1329 priv->hash_regs[2] = ®s->igaddr2;
1330 priv->hash_regs[3] = ®s->igaddr3;
1331 priv->hash_regs[4] = ®s->igaddr4;
1332 priv->hash_regs[5] = ®s->igaddr5;
1333 priv->hash_regs[6] = ®s->igaddr6;
1334 priv->hash_regs[7] = ®s->igaddr7;
1335 priv->hash_regs[8] = ®s->gaddr0;
1336 priv->hash_regs[9] = ®s->gaddr1;
1337 priv->hash_regs[10] = ®s->gaddr2;
1338 priv->hash_regs[11] = ®s->gaddr3;
1339 priv->hash_regs[12] = ®s->gaddr4;
1340 priv->hash_regs[13] = ®s->gaddr5;
1341 priv->hash_regs[14] = ®s->gaddr6;
1342 priv->hash_regs[15] = ®s->gaddr7;
1345 priv->extended_hash = 0;
1346 priv->hash_width = 8;
1348 priv->hash_regs[0] = ®s->gaddr0;
1349 priv->hash_regs[1] = ®s->gaddr1;
1350 priv->hash_regs[2] = ®s->gaddr2;
1351 priv->hash_regs[3] = ®s->gaddr3;
1352 priv->hash_regs[4] = ®s->gaddr4;
1353 priv->hash_regs[5] = ®s->gaddr5;
1354 priv->hash_regs[6] = ®s->gaddr6;
1355 priv->hash_regs[7] = ®s->gaddr7;
1359 /* Set up the ethernet device structure, private data,
1360 * and anything else we need before we start
1362 static int gfar_probe(struct platform_device *ofdev)
1364 struct net_device *dev = NULL;
1365 struct gfar_private *priv = NULL;
1368 err = gfar_of_init(ofdev, &dev);
1373 priv = netdev_priv(dev);
1375 priv->ofdev = ofdev;
1376 priv->dev = &ofdev->dev;
1377 SET_NETDEV_DEV(dev, &ofdev->dev);
1379 spin_lock_init(&priv->bflock);
1380 INIT_WORK(&priv->reset_task, gfar_reset_task);
1382 platform_set_drvdata(ofdev, priv);
1384 gfar_detect_errata(priv);
1386 /* Set the dev->base_addr to the gfar reg region */
1387 dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
1389 /* Fill in the dev structure */
1390 dev->watchdog_timeo = TX_TIMEOUT;
1392 dev->netdev_ops = &gfar_netdev_ops;
1393 dev->ethtool_ops = &gfar_ethtool_ops;
1395 /* Register for napi ...We are registering NAPI for each grp */
1396 for (i = 0; i < priv->num_grps; i++) {
1397 if (priv->poll_mode == GFAR_SQ_POLLING) {
1398 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1399 gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
1400 netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1401 gfar_poll_tx_sq, 2);
1403 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1404 gfar_poll_rx, GFAR_DEV_WEIGHT);
1405 netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1410 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1411 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1413 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1414 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1417 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1418 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1419 NETIF_F_HW_VLAN_CTAG_RX;
1420 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1423 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
1425 gfar_init_addr_hash_table(priv);
1427 /* Insert receive time stamps into padding alignment bytes */
1428 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1431 if (dev->features & NETIF_F_IP_CSUM ||
1432 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1433 dev->needed_headroom = GMAC_FCB_LEN;
1435 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1437 /* Initializing some of the rx/tx queue level parameters */
1438 for (i = 0; i < priv->num_tx_queues; i++) {
1439 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1440 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1441 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1442 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1445 for (i = 0; i < priv->num_rx_queues; i++) {
1446 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1447 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1448 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1451 /* always enable rx filer */
1452 priv->rx_filer_enable = 1;
1453 /* Enable most messages by default */
1454 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1455 /* use pritority h/w tx queue scheduling for single queue devices */
1456 if (priv->num_tx_queues == 1)
1457 priv->prio_sched_en = 1;
1459 set_bit(GFAR_DOWN, &priv->state);
1463 /* Carrier starts down, phylib will bring it up */
1464 netif_carrier_off(dev);
1466 err = register_netdev(dev);
1469 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1473 device_init_wakeup(&dev->dev,
1474 priv->device_flags &
1475 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1477 /* fill out IRQ number and name fields */
1478 for (i = 0; i < priv->num_grps; i++) {
1479 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1480 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1481 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1482 dev->name, "_g", '0' + i, "_tx");
1483 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1484 dev->name, "_g", '0' + i, "_rx");
1485 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1486 dev->name, "_g", '0' + i, "_er");
1488 strcpy(gfar_irq(grp, TX)->name, dev->name);
1491 /* Initialize the filer table */
1492 gfar_init_filer_table(priv);
1494 /* Print out the device info */
1495 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1497 /* Even more device info helps when determining which kernel
1498 * provided which set of benchmarks.
1500 netdev_info(dev, "Running with NAPI enabled\n");
1501 for (i = 0; i < priv->num_rx_queues; i++)
1502 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1503 i, priv->rx_queue[i]->rx_ring_size);
1504 for (i = 0; i < priv->num_tx_queues; i++)
1505 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1506 i, priv->tx_queue[i]->tx_ring_size);
1511 unmap_group_regs(priv);
1512 gfar_free_rx_queues(priv);
1513 gfar_free_tx_queues(priv);
1514 of_node_put(priv->phy_node);
1515 of_node_put(priv->tbi_node);
1516 free_gfar_dev(priv);
1520 static int gfar_remove(struct platform_device *ofdev)
1522 struct gfar_private *priv = platform_get_drvdata(ofdev);
1524 of_node_put(priv->phy_node);
1525 of_node_put(priv->tbi_node);
1527 unregister_netdev(priv->ndev);
1528 unmap_group_regs(priv);
1529 gfar_free_rx_queues(priv);
1530 gfar_free_tx_queues(priv);
1531 free_gfar_dev(priv);
1538 static int gfar_suspend(struct device *dev)
1540 struct gfar_private *priv = dev_get_drvdata(dev);
1541 struct net_device *ndev = priv->ndev;
1542 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1543 unsigned long flags;
1546 int magic_packet = priv->wol_en &&
1547 (priv->device_flags &
1548 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1550 netif_device_detach(ndev);
1552 if (netif_running(ndev)) {
1554 local_irq_save(flags);
1557 gfar_halt_nodisable(priv);
1559 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1560 tempval = gfar_read(®s->maccfg1);
1562 tempval &= ~MACCFG1_TX_EN;
1565 tempval &= ~MACCFG1_RX_EN;
1567 gfar_write(®s->maccfg1, tempval);
1570 local_irq_restore(flags);
1575 /* Enable interrupt on Magic Packet */
1576 gfar_write(®s->imask, IMASK_MAG);
1578 /* Enable Magic Packet mode */
1579 tempval = gfar_read(®s->maccfg2);
1580 tempval |= MACCFG2_MPEN;
1581 gfar_write(®s->maccfg2, tempval);
1583 phy_stop(priv->phydev);
1590 static int gfar_resume(struct device *dev)
1592 struct gfar_private *priv = dev_get_drvdata(dev);
1593 struct net_device *ndev = priv->ndev;
1594 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1595 unsigned long flags;
1597 int magic_packet = priv->wol_en &&
1598 (priv->device_flags &
1599 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1601 if (!netif_running(ndev)) {
1602 netif_device_attach(ndev);
1606 if (!magic_packet && priv->phydev)
1607 phy_start(priv->phydev);
1609 /* Disable Magic Packet mode, in case something
1612 local_irq_save(flags);
1615 tempval = gfar_read(®s->maccfg2);
1616 tempval &= ~MACCFG2_MPEN;
1617 gfar_write(®s->maccfg2, tempval);
1622 local_irq_restore(flags);
1624 netif_device_attach(ndev);
1631 static int gfar_restore(struct device *dev)
1633 struct gfar_private *priv = dev_get_drvdata(dev);
1634 struct net_device *ndev = priv->ndev;
1636 if (!netif_running(ndev)) {
1637 netif_device_attach(ndev);
1642 if (gfar_init_bds(ndev)) {
1643 free_skb_resources(priv);
1647 gfar_mac_reset(priv);
1649 gfar_init_tx_rx_base(priv);
1655 priv->oldduplex = -1;
1658 phy_start(priv->phydev);
1660 netif_device_attach(ndev);
1666 static struct dev_pm_ops gfar_pm_ops = {
1667 .suspend = gfar_suspend,
1668 .resume = gfar_resume,
1669 .freeze = gfar_suspend,
1670 .thaw = gfar_resume,
1671 .restore = gfar_restore,
1674 #define GFAR_PM_OPS (&gfar_pm_ops)
1678 #define GFAR_PM_OPS NULL
1682 /* Reads the controller's registers to determine what interface
1683 * connects it to the PHY.
1685 static phy_interface_t gfar_get_interface(struct net_device *dev)
1687 struct gfar_private *priv = netdev_priv(dev);
1688 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1691 ecntrl = gfar_read(®s->ecntrl);
1693 if (ecntrl & ECNTRL_SGMII_MODE)
1694 return PHY_INTERFACE_MODE_SGMII;
1696 if (ecntrl & ECNTRL_TBI_MODE) {
1697 if (ecntrl & ECNTRL_REDUCED_MODE)
1698 return PHY_INTERFACE_MODE_RTBI;
1700 return PHY_INTERFACE_MODE_TBI;
1703 if (ecntrl & ECNTRL_REDUCED_MODE) {
1704 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1705 return PHY_INTERFACE_MODE_RMII;
1708 phy_interface_t interface = priv->interface;
1710 /* This isn't autodetected right now, so it must
1711 * be set by the device tree or platform code.
1713 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1714 return PHY_INTERFACE_MODE_RGMII_ID;
1716 return PHY_INTERFACE_MODE_RGMII;
1720 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1721 return PHY_INTERFACE_MODE_GMII;
1723 return PHY_INTERFACE_MODE_MII;
1727 /* Initializes driver's PHY state, and attaches to the PHY.
1728 * Returns 0 on success.
1730 static int init_phy(struct net_device *dev)
1732 struct gfar_private *priv = netdev_priv(dev);
1733 uint gigabit_support =
1734 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1735 GFAR_SUPPORTED_GBIT : 0;
1736 phy_interface_t interface;
1740 priv->oldduplex = -1;
1742 interface = gfar_get_interface(dev);
1744 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1746 if (!priv->phydev) {
1747 dev_err(&dev->dev, "could not attach to PHY\n");
1751 if (interface == PHY_INTERFACE_MODE_SGMII)
1752 gfar_configure_serdes(dev);
1754 /* Remove any features not supported by the controller */
1755 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1756 priv->phydev->advertising = priv->phydev->supported;
1758 /* Add support for flow control, but don't advertise it by default */
1759 priv->phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause);
1764 /* Initialize TBI PHY interface for communicating with the
1765 * SERDES lynx PHY on the chip. We communicate with this PHY
1766 * through the MDIO bus on each controller, treating it as a
1767 * "normal" PHY at the address found in the TBIPA register. We assume
1768 * that the TBIPA register is valid. Either the MDIO bus code will set
1769 * it to a value that doesn't conflict with other PHYs on the bus, or the
1770 * value doesn't matter, as there are no other PHYs on the bus.
1772 static void gfar_configure_serdes(struct net_device *dev)
1774 struct gfar_private *priv = netdev_priv(dev);
1775 struct phy_device *tbiphy;
1777 if (!priv->tbi_node) {
1778 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1779 "device tree specify a tbi-handle\n");
1783 tbiphy = of_phy_find_device(priv->tbi_node);
1785 dev_err(&dev->dev, "error: Could not get TBI device\n");
1789 /* If the link is already up, we must already be ok, and don't need to
1790 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1791 * everything for us? Resetting it takes the link down and requires
1792 * several seconds for it to come back.
1794 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1797 /* Single clk mode, mii mode off(for serdes communication) */
1798 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1800 phy_write(tbiphy, MII_ADVERTISE,
1801 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1802 ADVERTISE_1000XPSE_ASYM);
1804 phy_write(tbiphy, MII_BMCR,
1805 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1809 static int __gfar_is_rx_idle(struct gfar_private *priv)
1813 /* Normaly TSEC should not hang on GRS commands, so we should
1814 * actually wait for IEVENT_GRSC flag.
1816 if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1819 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1820 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1821 * and the Rx can be safely reset.
1823 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1825 if ((res & 0xffff) == (res >> 16))
1831 /* Halt the receive and transmit queues */
1832 static void gfar_halt_nodisable(struct gfar_private *priv)
1834 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1836 unsigned int timeout;
1839 gfar_ints_disable(priv);
1841 if (gfar_is_dma_stopped(priv))
1844 /* Stop the DMA, and wait for it to stop */
1845 tempval = gfar_read(®s->dmactrl);
1846 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1847 gfar_write(®s->dmactrl, tempval);
1851 while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1857 stopped = gfar_is_dma_stopped(priv);
1859 if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1860 !__gfar_is_rx_idle(priv))
1864 /* Halt the receive and transmit queues */
1865 void gfar_halt(struct gfar_private *priv)
1867 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1870 /* Dissable the Rx/Tx hw queues */
1871 gfar_write(®s->rqueue, 0);
1872 gfar_write(®s->tqueue, 0);
1876 gfar_halt_nodisable(priv);
1878 /* Disable Rx/Tx DMA */
1879 tempval = gfar_read(®s->maccfg1);
1880 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1881 gfar_write(®s->maccfg1, tempval);
1884 void stop_gfar(struct net_device *dev)
1886 struct gfar_private *priv = netdev_priv(dev);
1888 netif_tx_stop_all_queues(dev);
1890 smp_mb__before_atomic();
1891 set_bit(GFAR_DOWN, &priv->state);
1892 smp_mb__after_atomic();
1896 /* disable ints and gracefully shut down Rx/Tx DMA */
1899 phy_stop(priv->phydev);
1901 free_skb_resources(priv);
1904 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1906 struct txbd8 *txbdp;
1907 struct gfar_private *priv = netdev_priv(tx_queue->dev);
1910 txbdp = tx_queue->tx_bd_base;
1912 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1913 if (!tx_queue->tx_skbuff[i])
1916 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr),
1917 be16_to_cpu(txbdp->length), DMA_TO_DEVICE);
1919 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1922 dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr),
1923 be16_to_cpu(txbdp->length),
1927 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1928 tx_queue->tx_skbuff[i] = NULL;
1930 kfree(tx_queue->tx_skbuff);
1931 tx_queue->tx_skbuff = NULL;
1934 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1936 struct rxbd8 *rxbdp;
1937 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1940 rxbdp = rx_queue->rx_bd_base;
1942 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1943 if (rx_queue->rx_skbuff[i]) {
1944 dma_unmap_single(priv->dev, be32_to_cpu(rxbdp->bufPtr),
1945 priv->rx_buffer_size,
1947 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1948 rx_queue->rx_skbuff[i] = NULL;
1954 kfree(rx_queue->rx_skbuff);
1955 rx_queue->rx_skbuff = NULL;
1958 /* If there are any tx skbs or rx skbs still around, free them.
1959 * Then free tx_skbuff and rx_skbuff
1961 static void free_skb_resources(struct gfar_private *priv)
1963 struct gfar_priv_tx_q *tx_queue = NULL;
1964 struct gfar_priv_rx_q *rx_queue = NULL;
1967 /* Go through all the buffer descriptors and free their data buffers */
1968 for (i = 0; i < priv->num_tx_queues; i++) {
1969 struct netdev_queue *txq;
1971 tx_queue = priv->tx_queue[i];
1972 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1973 if (tx_queue->tx_skbuff)
1974 free_skb_tx_queue(tx_queue);
1975 netdev_tx_reset_queue(txq);
1978 for (i = 0; i < priv->num_rx_queues; i++) {
1979 rx_queue = priv->rx_queue[i];
1980 if (rx_queue->rx_skbuff)
1981 free_skb_rx_queue(rx_queue);
1984 dma_free_coherent(priv->dev,
1985 sizeof(struct txbd8) * priv->total_tx_ring_size +
1986 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1987 priv->tx_queue[0]->tx_bd_base,
1988 priv->tx_queue[0]->tx_bd_dma_base);
1991 void gfar_start(struct gfar_private *priv)
1993 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1997 /* Enable Rx/Tx hw queues */
1998 gfar_write(®s->rqueue, priv->rqueue);
1999 gfar_write(®s->tqueue, priv->tqueue);
2001 /* Initialize DMACTRL to have WWR and WOP */
2002 tempval = gfar_read(®s->dmactrl);
2003 tempval |= DMACTRL_INIT_SETTINGS;
2004 gfar_write(®s->dmactrl, tempval);
2006 /* Make sure we aren't stopped */
2007 tempval = gfar_read(®s->dmactrl);
2008 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
2009 gfar_write(®s->dmactrl, tempval);
2011 for (i = 0; i < priv->num_grps; i++) {
2012 regs = priv->gfargrp[i].regs;
2013 /* Clear THLT/RHLT, so that the DMA starts polling now */
2014 gfar_write(®s->tstat, priv->gfargrp[i].tstat);
2015 gfar_write(®s->rstat, priv->gfargrp[i].rstat);
2018 /* Enable Rx/Tx DMA */
2019 tempval = gfar_read(®s->maccfg1);
2020 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
2021 gfar_write(®s->maccfg1, tempval);
2023 gfar_ints_enable(priv);
2025 priv->ndev->trans_start = jiffies; /* prevent tx timeout */
2028 static void free_grp_irqs(struct gfar_priv_grp *grp)
2030 free_irq(gfar_irq(grp, TX)->irq, grp);
2031 free_irq(gfar_irq(grp, RX)->irq, grp);
2032 free_irq(gfar_irq(grp, ER)->irq, grp);
2035 static int register_grp_irqs(struct gfar_priv_grp *grp)
2037 struct gfar_private *priv = grp->priv;
2038 struct net_device *dev = priv->ndev;
2041 /* If the device has multiple interrupts, register for
2042 * them. Otherwise, only register for the one
2044 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2045 /* Install our interrupt handlers for Error,
2046 * Transmit, and Receive
2048 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
2049 gfar_irq(grp, ER)->name, grp);
2051 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2052 gfar_irq(grp, ER)->irq);
2056 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
2057 gfar_irq(grp, TX)->name, grp);
2059 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2060 gfar_irq(grp, TX)->irq);
2063 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
2064 gfar_irq(grp, RX)->name, grp);
2066 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2067 gfar_irq(grp, RX)->irq);
2071 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
2072 gfar_irq(grp, TX)->name, grp);
2074 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2075 gfar_irq(grp, TX)->irq);
2083 free_irq(gfar_irq(grp, TX)->irq, grp);
2085 free_irq(gfar_irq(grp, ER)->irq, grp);
2091 static void gfar_free_irq(struct gfar_private *priv)
2096 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2097 for (i = 0; i < priv->num_grps; i++)
2098 free_grp_irqs(&priv->gfargrp[i]);
2100 for (i = 0; i < priv->num_grps; i++)
2101 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2106 static int gfar_request_irq(struct gfar_private *priv)
2110 for (i = 0; i < priv->num_grps; i++) {
2111 err = register_grp_irqs(&priv->gfargrp[i]);
2113 for (j = 0; j < i; j++)
2114 free_grp_irqs(&priv->gfargrp[j]);
2122 /* Bring the controller up and running */
2123 int startup_gfar(struct net_device *ndev)
2125 struct gfar_private *priv = netdev_priv(ndev);
2128 gfar_mac_reset(priv);
2130 err = gfar_alloc_skb_resources(ndev);
2134 gfar_init_tx_rx_base(priv);
2136 smp_mb__before_atomic();
2137 clear_bit(GFAR_DOWN, &priv->state);
2138 smp_mb__after_atomic();
2140 /* Start Rx/Tx DMA and enable the interrupts */
2143 phy_start(priv->phydev);
2147 netif_tx_wake_all_queues(ndev);
2152 /* Called when something needs to use the ethernet device
2153 * Returns 0 for success.
2155 static int gfar_enet_open(struct net_device *dev)
2157 struct gfar_private *priv = netdev_priv(dev);
2160 err = init_phy(dev);
2164 err = gfar_request_irq(priv);
2168 err = startup_gfar(dev);
2172 device_set_wakeup_enable(&dev->dev, priv->wol_en);
2177 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
2179 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
2181 memset(fcb, 0, GMAC_FCB_LEN);
2186 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2189 /* If we're here, it's a IP packet with a TCP or UDP
2190 * payload. We set it to checksum, using a pseudo-header
2193 u8 flags = TXFCB_DEFAULT;
2195 /* Tell the controller what the protocol is
2196 * And provide the already calculated phcs
2198 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2200 fcb->phcs = (__force __be16)(udp_hdr(skb)->check);
2202 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check);
2204 /* l3os is the distance between the start of the
2205 * frame (skb->data) and the start of the IP hdr.
2206 * l4os is the distance between the start of the
2207 * l3 hdr and the l4 hdr
2209 fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length);
2210 fcb->l4os = skb_network_header_len(skb);
2215 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2217 fcb->flags |= TXFCB_VLN;
2218 fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb));
2221 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2222 struct txbd8 *base, int ring_size)
2224 struct txbd8 *new_bd = bdp + stride;
2226 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2229 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2232 return skip_txbd(bdp, 1, base, ring_size);
2235 /* eTSEC12: csum generation not supported for some fcb offsets */
2236 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2237 unsigned long fcb_addr)
2239 return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2240 (fcb_addr % 0x20) > 0x18);
2243 /* eTSEC76: csum generation for frames larger than 2500 may
2244 * cause excess delays before start of transmission
2246 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2249 return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2253 /* This is called by the kernel when a frame is ready for transmission.
2254 * It is pointed to by the dev->hard_start_xmit function pointer
2256 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2258 struct gfar_private *priv = netdev_priv(dev);
2259 struct gfar_priv_tx_q *tx_queue = NULL;
2260 struct netdev_queue *txq;
2261 struct gfar __iomem *regs = NULL;
2262 struct txfcb *fcb = NULL;
2263 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2266 int do_tstamp, do_csum, do_vlan;
2268 unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
2270 rq = skb->queue_mapping;
2271 tx_queue = priv->tx_queue[rq];
2272 txq = netdev_get_tx_queue(dev, rq);
2273 base = tx_queue->tx_bd_base;
2274 regs = tx_queue->grp->regs;
2276 do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
2277 do_vlan = skb_vlan_tag_present(skb);
2278 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2281 if (do_csum || do_vlan)
2282 fcb_len = GMAC_FCB_LEN;
2284 /* check if time stamp should be generated */
2285 if (unlikely(do_tstamp))
2286 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2288 /* make space for additional header when fcb is needed */
2289 if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
2290 struct sk_buff *skb_new;
2292 skb_new = skb_realloc_headroom(skb, fcb_len);
2294 dev->stats.tx_errors++;
2295 dev_kfree_skb_any(skb);
2296 return NETDEV_TX_OK;
2300 skb_set_owner_w(skb_new, skb->sk);
2301 dev_consume_skb_any(skb);
2305 /* total number of fragments in the SKB */
2306 nr_frags = skb_shinfo(skb)->nr_frags;
2308 /* calculate the required number of TxBDs for this skb */
2309 if (unlikely(do_tstamp))
2310 nr_txbds = nr_frags + 2;
2312 nr_txbds = nr_frags + 1;
2314 /* check if there is space to queue this packet */
2315 if (nr_txbds > tx_queue->num_txbdfree) {
2316 /* no space, stop the queue */
2317 netif_tx_stop_queue(txq);
2318 dev->stats.tx_fifo_errors++;
2319 return NETDEV_TX_BUSY;
2322 /* Update transmit stats */
2323 bytes_sent = skb->len;
2324 tx_queue->stats.tx_bytes += bytes_sent;
2325 /* keep Tx bytes on wire for BQL accounting */
2326 GFAR_CB(skb)->bytes_sent = bytes_sent;
2327 tx_queue->stats.tx_packets++;
2329 txbdp = txbdp_start = tx_queue->cur_tx;
2330 lstatus = be32_to_cpu(txbdp->lstatus);
2332 /* Time stamp insertion requires one additional TxBD */
2333 if (unlikely(do_tstamp))
2334 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2335 tx_queue->tx_ring_size);
2337 if (nr_frags == 0) {
2338 if (unlikely(do_tstamp)) {
2339 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2341 lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2342 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2344 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2347 /* Place the fragment addresses and lengths into the TxBDs */
2348 for (i = 0; i < nr_frags; i++) {
2349 unsigned int frag_len;
2350 /* Point at the next BD, wrapping as needed */
2351 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2353 frag_len = skb_shinfo(skb)->frags[i].size;
2355 lstatus = be32_to_cpu(txbdp->lstatus) | frag_len |
2356 BD_LFLAG(TXBD_READY);
2358 /* Handle the last BD specially */
2359 if (i == nr_frags - 1)
2360 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2362 bufaddr = skb_frag_dma_map(priv->dev,
2363 &skb_shinfo(skb)->frags[i],
2367 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2370 /* set the TxBD length and buffer pointer */
2371 txbdp->bufPtr = cpu_to_be32(bufaddr);
2372 txbdp->lstatus = cpu_to_be32(lstatus);
2375 lstatus = be32_to_cpu(txbdp_start->lstatus);
2378 /* Add TxPAL between FCB and frame if required */
2379 if (unlikely(do_tstamp)) {
2380 skb_push(skb, GMAC_TXPAL_LEN);
2381 memset(skb->data, 0, GMAC_TXPAL_LEN);
2384 /* Add TxFCB if required */
2386 fcb = gfar_add_fcb(skb);
2387 lstatus |= BD_LFLAG(TXBD_TOE);
2390 /* Set up checksumming */
2392 gfar_tx_checksum(skb, fcb, fcb_len);
2394 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2395 unlikely(gfar_csum_errata_76(priv, skb->len))) {
2396 __skb_pull(skb, GMAC_FCB_LEN);
2397 skb_checksum_help(skb);
2398 if (do_vlan || do_tstamp) {
2399 /* put back a new fcb for vlan/tstamp TOE */
2400 fcb = gfar_add_fcb(skb);
2402 /* Tx TOE not used */
2403 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2410 gfar_tx_vlan(skb, fcb);
2412 /* Setup tx hardware time stamping if requested */
2413 if (unlikely(do_tstamp)) {
2414 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2418 bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
2420 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2423 txbdp_start->bufPtr = cpu_to_be32(bufaddr);
2425 /* If time stamping is requested one additional TxBD must be set up. The
2426 * first TxBD points to the FCB and must have a data length of
2427 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2428 * the full frame length.
2430 if (unlikely(do_tstamp)) {
2431 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2433 bufaddr = be32_to_cpu(txbdp_start->bufPtr);
2435 lstatus_ts |= BD_LFLAG(TXBD_READY) |
2436 (skb_headlen(skb) - fcb_len);
2438 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr);
2439 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2440 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2442 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2445 netdev_tx_sent_queue(txq, bytes_sent);
2449 txbdp_start->lstatus = cpu_to_be32(lstatus);
2451 gfar_wmb(); /* force lstatus write before tx_skbuff */
2453 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2455 /* Update the current skb pointer to the next entry we will use
2456 * (wrapping if necessary)
2458 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2459 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2461 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2463 /* We can work in parallel with gfar_clean_tx_ring(), except
2464 * when modifying num_txbdfree. Note that we didn't grab the lock
2465 * when we were reading the num_txbdfree and checking for available
2466 * space, that's because outside of this function it can only grow.
2468 spin_lock_bh(&tx_queue->txlock);
2469 /* reduce TxBD free count */
2470 tx_queue->num_txbdfree -= (nr_txbds);
2471 spin_unlock_bh(&tx_queue->txlock);
2473 /* If the next BD still needs to be cleaned up, then the bds
2474 * are full. We need to tell the kernel to stop sending us stuff.
2476 if (!tx_queue->num_txbdfree) {
2477 netif_tx_stop_queue(txq);
2479 dev->stats.tx_fifo_errors++;
2482 /* Tell the DMA to go go go */
2483 gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2485 return NETDEV_TX_OK;
2488 txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2490 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2491 for (i = 0; i < nr_frags; i++) {
2492 lstatus = be32_to_cpu(txbdp->lstatus);
2493 if (!(lstatus & BD_LFLAG(TXBD_READY)))
2496 lstatus &= ~BD_LFLAG(TXBD_READY);
2497 txbdp->lstatus = cpu_to_be32(lstatus);
2498 bufaddr = be32_to_cpu(txbdp->bufPtr);
2499 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length),
2501 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2504 dev_kfree_skb_any(skb);
2505 return NETDEV_TX_OK;
2508 /* Stops the kernel queue, and halts the controller */
2509 static int gfar_close(struct net_device *dev)
2511 struct gfar_private *priv = netdev_priv(dev);
2513 cancel_work_sync(&priv->reset_task);
2516 /* Disconnect from the PHY */
2517 phy_disconnect(priv->phydev);
2518 priv->phydev = NULL;
2520 gfar_free_irq(priv);
2525 /* Changes the mac address if the controller is not running. */
2526 static int gfar_set_mac_address(struct net_device *dev)
2528 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2533 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2535 struct gfar_private *priv = netdev_priv(dev);
2536 int frame_size = new_mtu + ETH_HLEN;
2538 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2539 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2543 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2546 if (dev->flags & IFF_UP)
2551 if (dev->flags & IFF_UP)
2554 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2559 void reset_gfar(struct net_device *ndev)
2561 struct gfar_private *priv = netdev_priv(ndev);
2563 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2569 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2572 /* gfar_reset_task gets scheduled when a packet has not been
2573 * transmitted after a set amount of time.
2574 * For now, assume that clearing out all the structures, and
2575 * starting over will fix the problem.
2577 static void gfar_reset_task(struct work_struct *work)
2579 struct gfar_private *priv = container_of(work, struct gfar_private,
2581 reset_gfar(priv->ndev);
2584 static void gfar_timeout(struct net_device *dev)
2586 struct gfar_private *priv = netdev_priv(dev);
2588 dev->stats.tx_errors++;
2589 schedule_work(&priv->reset_task);
2592 static void gfar_align_skb(struct sk_buff *skb)
2594 /* We need the data buffer to be aligned properly. We will reserve
2595 * as many bytes as needed to align the data properly
2597 skb_reserve(skb, RXBUF_ALIGNMENT -
2598 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2601 /* Interrupt Handler for Transmit complete */
2602 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2604 struct net_device *dev = tx_queue->dev;
2605 struct netdev_queue *txq;
2606 struct gfar_private *priv = netdev_priv(dev);
2607 struct txbd8 *bdp, *next = NULL;
2608 struct txbd8 *lbdp = NULL;
2609 struct txbd8 *base = tx_queue->tx_bd_base;
2610 struct sk_buff *skb;
2612 int tx_ring_size = tx_queue->tx_ring_size;
2613 int frags = 0, nr_txbds = 0;
2616 int tqi = tx_queue->qindex;
2617 unsigned int bytes_sent = 0;
2621 txq = netdev_get_tx_queue(dev, tqi);
2622 bdp = tx_queue->dirty_tx;
2623 skb_dirtytx = tx_queue->skb_dirtytx;
2625 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2627 frags = skb_shinfo(skb)->nr_frags;
2629 /* When time stamping, one additional TxBD must be freed.
2630 * Also, we need to dma_unmap_single() the TxPAL.
2632 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2633 nr_txbds = frags + 2;
2635 nr_txbds = frags + 1;
2637 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2639 lstatus = be32_to_cpu(lbdp->lstatus);
2641 /* Only clean completed frames */
2642 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2643 (lstatus & BD_LENGTH_MASK))
2646 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2647 next = next_txbd(bdp, base, tx_ring_size);
2648 buflen = be16_to_cpu(next->length) +
2649 GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2651 buflen = be16_to_cpu(bdp->length);
2653 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
2654 buflen, DMA_TO_DEVICE);
2656 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2657 struct skb_shared_hwtstamps shhwtstamps;
2658 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2660 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2661 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2662 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2663 skb_tstamp_tx(skb, &shhwtstamps);
2664 gfar_clear_txbd_status(bdp);
2668 gfar_clear_txbd_status(bdp);
2669 bdp = next_txbd(bdp, base, tx_ring_size);
2671 for (i = 0; i < frags; i++) {
2672 dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr),
2673 be16_to_cpu(bdp->length),
2675 gfar_clear_txbd_status(bdp);
2676 bdp = next_txbd(bdp, base, tx_ring_size);
2679 bytes_sent += GFAR_CB(skb)->bytes_sent;
2681 dev_kfree_skb_any(skb);
2683 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2685 skb_dirtytx = (skb_dirtytx + 1) &
2686 TX_RING_MOD_MASK(tx_ring_size);
2689 spin_lock(&tx_queue->txlock);
2690 tx_queue->num_txbdfree += nr_txbds;
2691 spin_unlock(&tx_queue->txlock);
2694 /* If we freed a buffer, we can restart transmission, if necessary */
2695 if (tx_queue->num_txbdfree &&
2696 netif_tx_queue_stopped(txq) &&
2697 !(test_bit(GFAR_DOWN, &priv->state)))
2698 netif_wake_subqueue(priv->ndev, tqi);
2700 /* Update dirty indicators */
2701 tx_queue->skb_dirtytx = skb_dirtytx;
2702 tx_queue->dirty_tx = bdp;
2704 netdev_tx_completed_queue(txq, howmany, bytes_sent);
2707 static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
2709 struct gfar_private *priv = netdev_priv(dev);
2710 struct sk_buff *skb;
2712 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2716 gfar_align_skb(skb);
2721 static struct sk_buff *gfar_new_skb(struct net_device *dev, dma_addr_t *bufaddr)
2723 struct gfar_private *priv = netdev_priv(dev);
2724 struct sk_buff *skb;
2727 skb = gfar_alloc_skb(dev);
2731 addr = dma_map_single(priv->dev, skb->data,
2732 priv->rx_buffer_size, DMA_FROM_DEVICE);
2733 if (unlikely(dma_mapping_error(priv->dev, addr))) {
2734 dev_kfree_skb_any(skb);
2742 static inline void count_errors(unsigned short status, struct net_device *dev)
2744 struct gfar_private *priv = netdev_priv(dev);
2745 struct net_device_stats *stats = &dev->stats;
2746 struct gfar_extra_stats *estats = &priv->extra_stats;
2748 /* If the packet was truncated, none of the other errors matter */
2749 if (status & RXBD_TRUNCATED) {
2750 stats->rx_length_errors++;
2752 atomic64_inc(&estats->rx_trunc);
2756 /* Count the errors, if there were any */
2757 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2758 stats->rx_length_errors++;
2760 if (status & RXBD_LARGE)
2761 atomic64_inc(&estats->rx_large);
2763 atomic64_inc(&estats->rx_short);
2765 if (status & RXBD_NONOCTET) {
2766 stats->rx_frame_errors++;
2767 atomic64_inc(&estats->rx_nonoctet);
2769 if (status & RXBD_CRCERR) {
2770 atomic64_inc(&estats->rx_crcerr);
2771 stats->rx_crc_errors++;
2773 if (status & RXBD_OVERRUN) {
2774 atomic64_inc(&estats->rx_overrun);
2775 stats->rx_crc_errors++;
2779 irqreturn_t gfar_receive(int irq, void *grp_id)
2781 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2782 unsigned long flags;
2785 if (likely(napi_schedule_prep(&grp->napi_rx))) {
2786 spin_lock_irqsave(&grp->grplock, flags);
2787 imask = gfar_read(&grp->regs->imask);
2788 imask &= IMASK_RX_DISABLED;
2789 gfar_write(&grp->regs->imask, imask);
2790 spin_unlock_irqrestore(&grp->grplock, flags);
2791 __napi_schedule(&grp->napi_rx);
2793 /* Clear IEVENT, so interrupts aren't called again
2794 * because of the packets that have already arrived.
2796 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2802 /* Interrupt Handler for Transmit complete */
2803 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2805 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2806 unsigned long flags;
2809 if (likely(napi_schedule_prep(&grp->napi_tx))) {
2810 spin_lock_irqsave(&grp->grplock, flags);
2811 imask = gfar_read(&grp->regs->imask);
2812 imask &= IMASK_TX_DISABLED;
2813 gfar_write(&grp->regs->imask, imask);
2814 spin_unlock_irqrestore(&grp->grplock, flags);
2815 __napi_schedule(&grp->napi_tx);
2817 /* Clear IEVENT, so interrupts aren't called again
2818 * because of the packets that have already arrived.
2820 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2826 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2828 /* If valid headers were found, and valid sums
2829 * were verified, then we tell the kernel that no
2830 * checksumming is necessary. Otherwise, it is [FIXME]
2832 if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) ==
2833 (RXFCB_CIP | RXFCB_CTU))
2834 skb->ip_summed = CHECKSUM_UNNECESSARY;
2836 skb_checksum_none_assert(skb);
2839 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2840 static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2841 int amount_pull, struct napi_struct *napi)
2843 struct gfar_private *priv = netdev_priv(dev);
2844 struct rxfcb *fcb = NULL;
2846 /* fcb is at the beginning if exists */
2847 fcb = (struct rxfcb *)skb->data;
2849 /* Remove the FCB from the skb
2850 * Remove the padded bytes, if there are any
2853 skb_record_rx_queue(skb, fcb->rq);
2854 skb_pull(skb, amount_pull);
2857 /* Get receive timestamp from the skb */
2858 if (priv->hwts_rx_en) {
2859 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2860 u64 *ns = (u64 *) skb->data;
2862 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2863 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2867 skb_pull(skb, priv->padding);
2869 if (dev->features & NETIF_F_RXCSUM)
2870 gfar_rx_checksum(skb, fcb);
2872 /* Tell the skb what kind of packet this is */
2873 skb->protocol = eth_type_trans(skb, dev);
2875 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
2876 * Even if vlan rx accel is disabled, on some chips
2877 * RXFCB_VLN is pseudo randomly set.
2879 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX &&
2880 be16_to_cpu(fcb->flags) & RXFCB_VLN)
2881 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2882 be16_to_cpu(fcb->vlctl));
2884 /* Send the packet up the stack */
2885 napi_gro_receive(napi, skb);
2889 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2890 * until the budget/quota has been reached. Returns the number
2893 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2895 struct net_device *dev = rx_queue->dev;
2896 struct rxbd8 *bdp, *base;
2897 struct sk_buff *skb;
2901 struct gfar_private *priv = netdev_priv(dev);
2903 /* Get the first full descriptor */
2904 bdp = rx_queue->cur_rx;
2905 base = rx_queue->rx_bd_base;
2907 amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0;
2909 while (!(be16_to_cpu(bdp->status) & RXBD_EMPTY) && rx_work_limit--) {
2910 struct sk_buff *newskb;
2915 /* Add another skb for the future */
2916 newskb = gfar_new_skb(dev, &bufaddr);
2918 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2920 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
2921 priv->rx_buffer_size, DMA_FROM_DEVICE);
2923 if (unlikely(!(be16_to_cpu(bdp->status) & RXBD_ERR) &&
2924 be16_to_cpu(bdp->length) > priv->rx_buffer_size))
2925 bdp->status = cpu_to_be16(RXBD_LARGE);
2927 /* We drop the frame if we failed to allocate a new buffer */
2928 if (unlikely(!newskb ||
2929 !(be16_to_cpu(bdp->status) & RXBD_LAST) ||
2930 be16_to_cpu(bdp->status) & RXBD_ERR)) {
2931 count_errors(be16_to_cpu(bdp->status), dev);
2933 if (unlikely(!newskb)) {
2935 bufaddr = be32_to_cpu(bdp->bufPtr);
2939 /* Increment the number of packets */
2940 rx_queue->stats.rx_packets++;
2944 pkt_len = be16_to_cpu(bdp->length) -
2946 /* Remove the FCS from the packet length */
2947 skb_put(skb, pkt_len);
2948 rx_queue->stats.rx_bytes += pkt_len;
2949 skb_record_rx_queue(skb, rx_queue->qindex);
2950 gfar_process_frame(dev, skb, amount_pull,
2951 &rx_queue->grp->napi_rx);
2954 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2955 rx_queue->stats.rx_dropped++;
2956 atomic64_inc(&priv->extra_stats.rx_skbmissing);
2961 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2963 /* Setup the new bdp */
2964 gfar_init_rxbdp(rx_queue, bdp, bufaddr);
2966 /* Update Last Free RxBD pointer for LFC */
2967 if (unlikely(rx_queue->rfbptr && priv->tx_actual_en))
2968 gfar_write(rx_queue->rfbptr, (u32)bdp);
2970 /* Update to the next pointer */
2971 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2973 /* update to point at the next skb */
2974 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2975 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2978 /* Update the current rxbd pointer to be the next one */
2979 rx_queue->cur_rx = bdp;
2984 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
2986 struct gfar_priv_grp *gfargrp =
2987 container_of(napi, struct gfar_priv_grp, napi_rx);
2988 struct gfar __iomem *regs = gfargrp->regs;
2989 struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
2992 /* Clear IEVENT, so interrupts aren't called again
2993 * because of the packets that have already arrived
2995 gfar_write(®s->ievent, IEVENT_RX_MASK);
2997 work_done = gfar_clean_rx_ring(rx_queue, budget);
2999 if (work_done < budget) {
3001 napi_complete(napi);
3002 /* Clear the halt bit in RSTAT */
3003 gfar_write(®s->rstat, gfargrp->rstat);
3005 spin_lock_irq(&gfargrp->grplock);
3006 imask = gfar_read(®s->imask);
3007 imask |= IMASK_RX_DEFAULT;
3008 gfar_write(®s->imask, imask);
3009 spin_unlock_irq(&gfargrp->grplock);
3015 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
3017 struct gfar_priv_grp *gfargrp =
3018 container_of(napi, struct gfar_priv_grp, napi_tx);
3019 struct gfar __iomem *regs = gfargrp->regs;
3020 struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
3023 /* Clear IEVENT, so interrupts aren't called again
3024 * because of the packets that have already arrived
3026 gfar_write(®s->ievent, IEVENT_TX_MASK);
3028 /* run Tx cleanup to completion */
3029 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
3030 gfar_clean_tx_ring(tx_queue);
3032 napi_complete(napi);
3034 spin_lock_irq(&gfargrp->grplock);
3035 imask = gfar_read(®s->imask);
3036 imask |= IMASK_TX_DEFAULT;
3037 gfar_write(®s->imask, imask);
3038 spin_unlock_irq(&gfargrp->grplock);
3043 static int gfar_poll_rx(struct napi_struct *napi, int budget)
3045 struct gfar_priv_grp *gfargrp =
3046 container_of(napi, struct gfar_priv_grp, napi_rx);
3047 struct gfar_private *priv = gfargrp->priv;
3048 struct gfar __iomem *regs = gfargrp->regs;
3049 struct gfar_priv_rx_q *rx_queue = NULL;
3050 int work_done = 0, work_done_per_q = 0;
3051 int i, budget_per_q = 0;
3052 unsigned long rstat_rxf;
3055 /* Clear IEVENT, so interrupts aren't called again
3056 * because of the packets that have already arrived
3058 gfar_write(®s->ievent, IEVENT_RX_MASK);
3060 rstat_rxf = gfar_read(®s->rstat) & RSTAT_RXF_MASK;
3062 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
3064 budget_per_q = budget/num_act_queues;
3066 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
3067 /* skip queue if not active */
3068 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
3071 rx_queue = priv->rx_queue[i];
3073 gfar_clean_rx_ring(rx_queue, budget_per_q);
3074 work_done += work_done_per_q;
3076 /* finished processing this queue */
3077 if (work_done_per_q < budget_per_q) {
3078 /* clear active queue hw indication */
3079 gfar_write(®s->rstat,
3080 RSTAT_CLEAR_RXF0 >> i);
3083 if (!num_act_queues)
3088 if (!num_act_queues) {
3090 napi_complete(napi);
3092 /* Clear the halt bit in RSTAT */
3093 gfar_write(®s->rstat, gfargrp->rstat);
3095 spin_lock_irq(&gfargrp->grplock);
3096 imask = gfar_read(®s->imask);
3097 imask |= IMASK_RX_DEFAULT;
3098 gfar_write(®s->imask, imask);
3099 spin_unlock_irq(&gfargrp->grplock);
3105 static int gfar_poll_tx(struct napi_struct *napi, int budget)
3107 struct gfar_priv_grp *gfargrp =
3108 container_of(napi, struct gfar_priv_grp, napi_tx);
3109 struct gfar_private *priv = gfargrp->priv;
3110 struct gfar __iomem *regs = gfargrp->regs;
3111 struct gfar_priv_tx_q *tx_queue = NULL;
3112 int has_tx_work = 0;
3115 /* Clear IEVENT, so interrupts aren't called again
3116 * because of the packets that have already arrived
3118 gfar_write(®s->ievent, IEVENT_TX_MASK);
3120 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
3121 tx_queue = priv->tx_queue[i];
3122 /* run Tx cleanup to completion */
3123 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
3124 gfar_clean_tx_ring(tx_queue);
3131 napi_complete(napi);
3133 spin_lock_irq(&gfargrp->grplock);
3134 imask = gfar_read(®s->imask);
3135 imask |= IMASK_TX_DEFAULT;
3136 gfar_write(®s->imask, imask);
3137 spin_unlock_irq(&gfargrp->grplock);
3144 #ifdef CONFIG_NET_POLL_CONTROLLER
3145 /* Polling 'interrupt' - used by things like netconsole to send skbs
3146 * without having to re-enable interrupts. It's not called while
3147 * the interrupt routine is executing.
3149 static void gfar_netpoll(struct net_device *dev)
3151 struct gfar_private *priv = netdev_priv(dev);
3154 /* If the device has multiple interrupts, run tx/rx */
3155 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3156 for (i = 0; i < priv->num_grps; i++) {
3157 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3159 disable_irq(gfar_irq(grp, TX)->irq);
3160 disable_irq(gfar_irq(grp, RX)->irq);
3161 disable_irq(gfar_irq(grp, ER)->irq);
3162 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3163 enable_irq(gfar_irq(grp, ER)->irq);
3164 enable_irq(gfar_irq(grp, RX)->irq);
3165 enable_irq(gfar_irq(grp, TX)->irq);
3168 for (i = 0; i < priv->num_grps; i++) {
3169 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3171 disable_irq(gfar_irq(grp, TX)->irq);
3172 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3173 enable_irq(gfar_irq(grp, TX)->irq);
3179 /* The interrupt handler for devices with one interrupt */
3180 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
3182 struct gfar_priv_grp *gfargrp = grp_id;
3184 /* Save ievent for future reference */
3185 u32 events = gfar_read(&gfargrp->regs->ievent);
3187 /* Check for reception */
3188 if (events & IEVENT_RX_MASK)
3189 gfar_receive(irq, grp_id);
3191 /* Check for transmit completion */
3192 if (events & IEVENT_TX_MASK)
3193 gfar_transmit(irq, grp_id);
3195 /* Check for errors */
3196 if (events & IEVENT_ERR_MASK)
3197 gfar_error(irq, grp_id);
3202 /* Called every time the controller might need to be made
3203 * aware of new link state. The PHY code conveys this
3204 * information through variables in the phydev structure, and this
3205 * function converts those variables into the appropriate
3206 * register values, and can bring down the device if needed.
3208 static void adjust_link(struct net_device *dev)
3210 struct gfar_private *priv = netdev_priv(dev);
3211 struct phy_device *phydev = priv->phydev;
3213 if (unlikely(phydev->link != priv->oldlink ||
3214 (phydev->link && (phydev->duplex != priv->oldduplex ||
3215 phydev->speed != priv->oldspeed))))
3216 gfar_update_link_state(priv);
3219 /* Update the hash table based on the current list of multicast
3220 * addresses we subscribe to. Also, change the promiscuity of
3221 * the device based on the flags (this function is called
3222 * whenever dev->flags is changed
3224 static void gfar_set_multi(struct net_device *dev)
3226 struct netdev_hw_addr *ha;
3227 struct gfar_private *priv = netdev_priv(dev);
3228 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3231 if (dev->flags & IFF_PROMISC) {
3232 /* Set RCTRL to PROM */
3233 tempval = gfar_read(®s->rctrl);
3234 tempval |= RCTRL_PROM;
3235 gfar_write(®s->rctrl, tempval);
3237 /* Set RCTRL to not PROM */
3238 tempval = gfar_read(®s->rctrl);
3239 tempval &= ~(RCTRL_PROM);
3240 gfar_write(®s->rctrl, tempval);
3243 if (dev->flags & IFF_ALLMULTI) {
3244 /* Set the hash to rx all multicast frames */
3245 gfar_write(®s->igaddr0, 0xffffffff);
3246 gfar_write(®s->igaddr1, 0xffffffff);
3247 gfar_write(®s->igaddr2, 0xffffffff);
3248 gfar_write(®s->igaddr3, 0xffffffff);
3249 gfar_write(®s->igaddr4, 0xffffffff);
3250 gfar_write(®s->igaddr5, 0xffffffff);
3251 gfar_write(®s->igaddr6, 0xffffffff);
3252 gfar_write(®s->igaddr7, 0xffffffff);
3253 gfar_write(®s->gaddr0, 0xffffffff);
3254 gfar_write(®s->gaddr1, 0xffffffff);
3255 gfar_write(®s->gaddr2, 0xffffffff);
3256 gfar_write(®s->gaddr3, 0xffffffff);
3257 gfar_write(®s->gaddr4, 0xffffffff);
3258 gfar_write(®s->gaddr5, 0xffffffff);
3259 gfar_write(®s->gaddr6, 0xffffffff);
3260 gfar_write(®s->gaddr7, 0xffffffff);
3265 /* zero out the hash */
3266 gfar_write(®s->igaddr0, 0x0);
3267 gfar_write(®s->igaddr1, 0x0);
3268 gfar_write(®s->igaddr2, 0x0);
3269 gfar_write(®s->igaddr3, 0x0);
3270 gfar_write(®s->igaddr4, 0x0);
3271 gfar_write(®s->igaddr5, 0x0);
3272 gfar_write(®s->igaddr6, 0x0);
3273 gfar_write(®s->igaddr7, 0x0);
3274 gfar_write(®s->gaddr0, 0x0);
3275 gfar_write(®s->gaddr1, 0x0);
3276 gfar_write(®s->gaddr2, 0x0);
3277 gfar_write(®s->gaddr3, 0x0);
3278 gfar_write(®s->gaddr4, 0x0);
3279 gfar_write(®s->gaddr5, 0x0);
3280 gfar_write(®s->gaddr6, 0x0);
3281 gfar_write(®s->gaddr7, 0x0);
3283 /* If we have extended hash tables, we need to
3284 * clear the exact match registers to prepare for
3287 if (priv->extended_hash) {
3288 em_num = GFAR_EM_NUM + 1;
3289 gfar_clear_exact_match(dev);
3296 if (netdev_mc_empty(dev))
3299 /* Parse the list, and set the appropriate bits */
3300 netdev_for_each_mc_addr(ha, dev) {
3302 gfar_set_mac_for_addr(dev, idx, ha->addr);
3305 gfar_set_hash_for_addr(dev, ha->addr);
3311 /* Clears each of the exact match registers to zero, so they
3312 * don't interfere with normal reception
3314 static void gfar_clear_exact_match(struct net_device *dev)
3317 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3319 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3320 gfar_set_mac_for_addr(dev, idx, zero_arr);
3323 /* Set the appropriate hash bit for the given addr */
3324 /* The algorithm works like so:
3325 * 1) Take the Destination Address (ie the multicast address), and
3326 * do a CRC on it (little endian), and reverse the bits of the
3328 * 2) Use the 8 most significant bits as a hash into a 256-entry
3329 * table. The table is controlled through 8 32-bit registers:
3330 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3331 * gaddr7. This means that the 3 most significant bits in the
3332 * hash index which gaddr register to use, and the 5 other bits
3333 * indicate which bit (assuming an IBM numbering scheme, which
3334 * for PowerPC (tm) is usually the case) in the register holds
3337 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3340 struct gfar_private *priv = netdev_priv(dev);
3341 u32 result = ether_crc(ETH_ALEN, addr);
3342 int width = priv->hash_width;
3343 u8 whichbit = (result >> (32 - width)) & 0x1f;
3344 u8 whichreg = result >> (32 - width + 5);
3345 u32 value = (1 << (31-whichbit));
3347 tempval = gfar_read(priv->hash_regs[whichreg]);
3349 gfar_write(priv->hash_regs[whichreg], tempval);
3353 /* There are multiple MAC Address register pairs on some controllers
3354 * This function sets the numth pair to a given address
3356 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3359 struct gfar_private *priv = netdev_priv(dev);
3360 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3362 u32 __iomem *macptr = ®s->macstnaddr1;
3366 /* For a station address of 0x12345678ABCD in transmission
3367 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
3368 * MACnADDR2 is set to 0x34120000.
3370 tempval = (addr[5] << 24) | (addr[4] << 16) |
3371 (addr[3] << 8) | addr[2];
3373 gfar_write(macptr, tempval);
3375 tempval = (addr[1] << 24) | (addr[0] << 16);
3377 gfar_write(macptr+1, tempval);
3380 /* GFAR error interrupt handler */
3381 static irqreturn_t gfar_error(int irq, void *grp_id)
3383 struct gfar_priv_grp *gfargrp = grp_id;
3384 struct gfar __iomem *regs = gfargrp->regs;
3385 struct gfar_private *priv= gfargrp->priv;
3386 struct net_device *dev = priv->ndev;
3388 /* Save ievent for future reference */
3389 u32 events = gfar_read(®s->ievent);
3392 gfar_write(®s->ievent, events & IEVENT_ERR_MASK);
3394 /* Magic Packet is not an error. */
3395 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3396 (events & IEVENT_MAG))
3397 events &= ~IEVENT_MAG;
3400 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3402 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3403 events, gfar_read(®s->imask));
3405 /* Update the error counters */
3406 if (events & IEVENT_TXE) {
3407 dev->stats.tx_errors++;
3409 if (events & IEVENT_LC)
3410 dev->stats.tx_window_errors++;
3411 if (events & IEVENT_CRL)
3412 dev->stats.tx_aborted_errors++;
3413 if (events & IEVENT_XFUN) {
3414 netif_dbg(priv, tx_err, dev,
3415 "TX FIFO underrun, packet dropped\n");
3416 dev->stats.tx_dropped++;
3417 atomic64_inc(&priv->extra_stats.tx_underrun);
3419 schedule_work(&priv->reset_task);
3421 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3423 if (events & IEVENT_BSY) {
3424 dev->stats.rx_errors++;
3425 atomic64_inc(&priv->extra_stats.rx_bsy);
3427 gfar_receive(irq, grp_id);
3429 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3430 gfar_read(®s->rstat));
3432 if (events & IEVENT_BABR) {
3433 dev->stats.rx_errors++;
3434 atomic64_inc(&priv->extra_stats.rx_babr);
3436 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3438 if (events & IEVENT_EBERR) {
3439 atomic64_inc(&priv->extra_stats.eberr);
3440 netif_dbg(priv, rx_err, dev, "bus error\n");
3442 if (events & IEVENT_RXC)
3443 netif_dbg(priv, rx_status, dev, "control frame\n");
3445 if (events & IEVENT_BABT) {
3446 atomic64_inc(&priv->extra_stats.tx_babt);
3447 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3452 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3454 struct phy_device *phydev = priv->phydev;
3457 if (!phydev->duplex)
3460 if (!priv->pause_aneg_en) {
3461 if (priv->tx_pause_en)
3462 val |= MACCFG1_TX_FLOW;
3463 if (priv->rx_pause_en)
3464 val |= MACCFG1_RX_FLOW;
3466 u16 lcl_adv, rmt_adv;
3468 /* get link partner capabilities */
3471 rmt_adv = LPA_PAUSE_CAP;
3472 if (phydev->asym_pause)
3473 rmt_adv |= LPA_PAUSE_ASYM;
3476 if (phydev->advertising & ADVERTISED_Pause)
3477 lcl_adv |= ADVERTISE_PAUSE_CAP;
3478 if (phydev->advertising & ADVERTISED_Asym_Pause)
3479 lcl_adv |= ADVERTISE_PAUSE_ASYM;
3481 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3482 if (flowctrl & FLOW_CTRL_TX)
3483 val |= MACCFG1_TX_FLOW;
3484 if (flowctrl & FLOW_CTRL_RX)
3485 val |= MACCFG1_RX_FLOW;
3491 static noinline void gfar_update_link_state(struct gfar_private *priv)
3493 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3494 struct phy_device *phydev = priv->phydev;
3495 struct gfar_priv_rx_q *rx_queue = NULL;
3499 if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
3503 u32 tempval1 = gfar_read(®s->maccfg1);
3504 u32 tempval = gfar_read(®s->maccfg2);
3505 u32 ecntrl = gfar_read(®s->ecntrl);
3506 u32 tx_flow_oldval = (tempval & MACCFG1_TX_FLOW);
3508 if (phydev->duplex != priv->oldduplex) {
3509 if (!(phydev->duplex))
3510 tempval &= ~(MACCFG2_FULL_DUPLEX);
3512 tempval |= MACCFG2_FULL_DUPLEX;
3514 priv->oldduplex = phydev->duplex;
3517 if (phydev->speed != priv->oldspeed) {
3518 switch (phydev->speed) {
3521 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3523 ecntrl &= ~(ECNTRL_R100);
3528 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3530 /* Reduced mode distinguishes
3531 * between 10 and 100
3533 if (phydev->speed == SPEED_100)
3534 ecntrl |= ECNTRL_R100;
3536 ecntrl &= ~(ECNTRL_R100);
3539 netif_warn(priv, link, priv->ndev,
3540 "Ack! Speed (%d) is not 10/100/1000!\n",
3545 priv->oldspeed = phydev->speed;
3548 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3549 tempval1 |= gfar_get_flowctrl_cfg(priv);
3551 /* Turn last free buffer recording on */
3552 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
3553 for (i = 0; i < priv->num_rx_queues; i++) {
3554 rx_queue = priv->rx_queue[i];
3555 bdp = rx_queue->cur_rx;
3556 /* skip to previous bd */
3557 bdp = skip_bd(bdp, rx_queue->rx_ring_size - 1,
3558 rx_queue->rx_bd_base,
3559 rx_queue->rx_ring_size);
3561 if (rx_queue->rfbptr)
3562 gfar_write(rx_queue->rfbptr, (u32)bdp);
3565 priv->tx_actual_en = 1;
3568 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
3569 priv->tx_actual_en = 0;
3571 gfar_write(®s->maccfg1, tempval1);
3572 gfar_write(®s->maccfg2, tempval);
3573 gfar_write(®s->ecntrl, ecntrl);
3578 } else if (priv->oldlink) {
3581 priv->oldduplex = -1;
3584 if (netif_msg_link(priv))
3585 phy_print_status(phydev);
3588 static const struct of_device_id gfar_match[] =
3592 .compatible = "gianfar",
3595 .compatible = "fsl,etsec2",
3599 MODULE_DEVICE_TABLE(of, gfar_match);
3601 /* Structure for a device driver */
3602 static struct platform_driver gfar_driver = {
3604 .name = "fsl-gianfar",
3606 .of_match_table = gfar_match,
3608 .probe = gfar_probe,
3609 .remove = gfar_remove,
3612 module_platform_driver(gfar_driver);