drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* Copyright (c) 2018-2019 Hisilicon Limited. */
   3
   4 #include <linux/debugfs.h>
   5 #include <linux/device.h>
   6
   7 #include "hnae3.h"
   8 #include "hns3_debugfs.h"
   9 #include "hns3_enet.h"
  10
  11 static struct dentry *hns3_dbgfs_root;
  12
  13 static struct hns3_dbg_dentry_info hns3_dbg_dentry[] = {
  14         {
  15                 .name = "tm"
  16         },
  17         {
  18                 .name = "tx_bd_info"
  19         },
  20         {
  21                 .name = "rx_bd_info"
  22         },
  23         {
  24                 .name = "mac_list"
  25         },
  26         {
  27                 .name = "reg"
  28         },
  29         {
  30                 .name = "queue"
  31         },
  32         {
  33                 .name = "fd"
  34         },
  35         /* keep common at the bottom and add new directory above */
  36         {
  37                 .name = "common"
  38         },
  39 };
  40
  41 static int hns3_dbg_bd_file_init(struct hnae3_handle *handle, u32 cmd);
  42 static int hns3_dbg_common_file_init(struct hnae3_handle *handle, u32 cmd);
  43
  44 static struct hns3_dbg_cmd_info hns3_dbg_cmd[] = {
  45         {
  46                 .name = "tm_nodes",
  47                 .cmd = HNAE3_DBG_CMD_TM_NODES,
  48                 .dentry = HNS3_DBG_DENTRY_TM,
  49                 .buf_len = HNS3_DBG_READ_LEN,
  50                 .init = hns3_dbg_common_file_init,
  51         },
  52         {
  53                 .name = "tm_priority",
  54                 .cmd = HNAE3_DBG_CMD_TM_PRI,
  55                 .dentry = HNS3_DBG_DENTRY_TM,
  56                 .buf_len = HNS3_DBG_READ_LEN,
  57                 .init = hns3_dbg_common_file_init,
  58         },
  59         {
  60                 .name = "tm_qset",
  61                 .cmd = HNAE3_DBG_CMD_TM_QSET,
  62                 .dentry = HNS3_DBG_DENTRY_TM,
  63                 .buf_len = HNS3_DBG_READ_LEN,
  64                 .init = hns3_dbg_common_file_init,
  65         },
  66         {
  67                 .name = "tm_map",
  68                 .cmd = HNAE3_DBG_CMD_TM_MAP,
  69                 .dentry = HNS3_DBG_DENTRY_TM,
  70                 .buf_len = HNS3_DBG_READ_LEN_1MB,
  71                 .init = hns3_dbg_common_file_init,
  72         },
  73         {
  74                 .name = "tm_pg",
  75                 .cmd = HNAE3_DBG_CMD_TM_PG,
  76                 .dentry = HNS3_DBG_DENTRY_TM,
  77                 .buf_len = HNS3_DBG_READ_LEN,
  78                 .init = hns3_dbg_common_file_init,
  79         },
  80         {
  81                 .name = "tm_port",
  82                 .cmd = HNAE3_DBG_CMD_TM_PORT,
  83                 .dentry = HNS3_DBG_DENTRY_TM,
  84                 .buf_len = HNS3_DBG_READ_LEN,
  85                 .init = hns3_dbg_common_file_init,
  86         },
  87         {
  88                 .name = "tc_sch_info",
  89                 .cmd = HNAE3_DBG_CMD_TC_SCH_INFO,
  90                 .dentry = HNS3_DBG_DENTRY_TM,
  91                 .buf_len = HNS3_DBG_READ_LEN,
  92                 .init = hns3_dbg_common_file_init,
  93         },
  94         {
  95                 .name = "qos_pause_cfg",
  96                 .cmd = HNAE3_DBG_CMD_QOS_PAUSE_CFG,
  97                 .dentry = HNS3_DBG_DENTRY_TM,
  98                 .buf_len = HNS3_DBG_READ_LEN,
  99                 .init = hns3_dbg_common_file_init,
 100         },
 101         {
 102                 .name = "qos_pri_map",
 103                 .cmd = HNAE3_DBG_CMD_QOS_PRI_MAP,
 104                 .dentry = HNS3_DBG_DENTRY_TM,
 105                 .buf_len = HNS3_DBG_READ_LEN,
 106                 .init = hns3_dbg_common_file_init,
 107         },
 108         {
 109                 .name = "qos_dscp_map",
 110                 .cmd = HNAE3_DBG_CMD_QOS_DSCP_MAP,
 111                 .dentry = HNS3_DBG_DENTRY_TM,
 112                 .buf_len = HNS3_DBG_READ_LEN,
 113                 .init = hns3_dbg_common_file_init,
 114         },
 115         {
 116                 .name = "qos_buf_cfg",
 117                 .cmd = HNAE3_DBG_CMD_QOS_BUF_CFG,
 118                 .dentry = HNS3_DBG_DENTRY_TM,
 119                 .buf_len = HNS3_DBG_READ_LEN,
 120                 .init = hns3_dbg_common_file_init,
 121         },
 122         {
 123                 .name = "dev_info",
 124                 .cmd = HNAE3_DBG_CMD_DEV_INFO,
 125                 .dentry = HNS3_DBG_DENTRY_COMMON,
 126                 .buf_len = HNS3_DBG_READ_LEN,
 127                 .init = hns3_dbg_common_file_init,
 128         },
 129         {
 130                 .name = "tx_bd_queue",
 131                 .cmd = HNAE3_DBG_CMD_TX_BD,
 132                 .dentry = HNS3_DBG_DENTRY_TX_BD,
 133                 .buf_len = HNS3_DBG_READ_LEN_5MB,
 134                 .init = hns3_dbg_bd_file_init,
 135         },
 136         {
 137                 .name = "rx_bd_queue",
 138                 .cmd = HNAE3_DBG_CMD_RX_BD,
 139                 .dentry = HNS3_DBG_DENTRY_RX_BD,
 140                 .buf_len = HNS3_DBG_READ_LEN_4MB,
 141                 .init = hns3_dbg_bd_file_init,
 142         },
 143         {
 144                 .name = "uc",
 145                 .cmd = HNAE3_DBG_CMD_MAC_UC,
 146                 .dentry = HNS3_DBG_DENTRY_MAC,
 147                 .buf_len = HNS3_DBG_READ_LEN_128KB,
 148                 .init = hns3_dbg_common_file_init,
 149         },
 150         {
 151                 .name = "mc",
 152                 .cmd = HNAE3_DBG_CMD_MAC_MC,
 153                 .dentry = HNS3_DBG_DENTRY_MAC,
 154                 .buf_len = HNS3_DBG_READ_LEN,
 155                 .init = hns3_dbg_common_file_init,
 156         },
 157         {
 158                 .name = "mng_tbl",
 159                 .cmd = HNAE3_DBG_CMD_MNG_TBL,
 160                 .dentry = HNS3_DBG_DENTRY_COMMON,
 161                 .buf_len = HNS3_DBG_READ_LEN,
 162                 .init = hns3_dbg_common_file_init,
 163         },
 164         {
 165                 .name = "loopback",
 166                 .cmd = HNAE3_DBG_CMD_LOOPBACK,
 167                 .dentry = HNS3_DBG_DENTRY_COMMON,
 168                 .buf_len = HNS3_DBG_READ_LEN,
 169                 .init = hns3_dbg_common_file_init,
 170         },
 171         {
 172                 .name = "interrupt_info",
 173                 .cmd = HNAE3_DBG_CMD_INTERRUPT_INFO,
 174                 .dentry = HNS3_DBG_DENTRY_COMMON,
 175                 .buf_len = HNS3_DBG_READ_LEN,
 176                 .init = hns3_dbg_common_file_init,
 177         },
 178         {
 179                 .name = "reset_info",
 180                 .cmd = HNAE3_DBG_CMD_RESET_INFO,
 181                 .dentry = HNS3_DBG_DENTRY_COMMON,
 182                 .buf_len = HNS3_DBG_READ_LEN,
 183                 .init = hns3_dbg_common_file_init,
 184         },
 185         {
 186                 .name = "imp_info",
 187                 .cmd = HNAE3_DBG_CMD_IMP_INFO,
 188                 .dentry = HNS3_DBG_DENTRY_COMMON,
 189                 .buf_len = HNS3_DBG_READ_LEN,
 190                 .init = hns3_dbg_common_file_init,
 191         },
 192         {
 193                 .name = "ncl_config",
 194                 .cmd = HNAE3_DBG_CMD_NCL_CONFIG,
 195                 .dentry = HNS3_DBG_DENTRY_COMMON,
 196                 .buf_len = HNS3_DBG_READ_LEN_128KB,
 197                 .init = hns3_dbg_common_file_init,
 198         },
 199         {
 200                 .name = "mac_tnl_status",
 201                 .cmd = HNAE3_DBG_CMD_MAC_TNL_STATUS,
 202                 .dentry = HNS3_DBG_DENTRY_COMMON,
 203                 .buf_len = HNS3_DBG_READ_LEN,
 204                 .init = hns3_dbg_common_file_init,
 205         },
 206         {
 207                 .name = "bios_common",
 208                 .cmd = HNAE3_DBG_CMD_REG_BIOS_COMMON,
 209                 .dentry = HNS3_DBG_DENTRY_REG,
 210                 .buf_len = HNS3_DBG_READ_LEN,
 211                 .init = hns3_dbg_common_file_init,
 212         },
 213         {
 214                 .name = "ssu",
 215                 .cmd = HNAE3_DBG_CMD_REG_SSU,
 216                 .dentry = HNS3_DBG_DENTRY_REG,
 217                 .buf_len = HNS3_DBG_READ_LEN,
 218                 .init = hns3_dbg_common_file_init,
 219         },
 220         {
 221                 .name = "igu_egu",
 222                 .cmd = HNAE3_DBG_CMD_REG_IGU_EGU,
 223                 .dentry = HNS3_DBG_DENTRY_REG,
 224                 .buf_len = HNS3_DBG_READ_LEN,
 225                 .init = hns3_dbg_common_file_init,
 226         },
 227         {
 228                 .name = "rpu",
 229                 .cmd = HNAE3_DBG_CMD_REG_RPU,
 230                 .dentry = HNS3_DBG_DENTRY_REG,
 231                 .buf_len = HNS3_DBG_READ_LEN,
 232                 .init = hns3_dbg_common_file_init,
 233         },
 234         {
 235                 .name = "ncsi",
 236                 .cmd = HNAE3_DBG_CMD_REG_NCSI,
 237                 .dentry = HNS3_DBG_DENTRY_REG,
 238                 .buf_len = HNS3_DBG_READ_LEN,
 239                 .init = hns3_dbg_common_file_init,
 240         },
 241         {
 242                 .name = "rtc",
 243                 .cmd = HNAE3_DBG_CMD_REG_RTC,
 244                 .dentry = HNS3_DBG_DENTRY_REG,
 245                 .buf_len = HNS3_DBG_READ_LEN,
 246                 .init = hns3_dbg_common_file_init,
 247         },
 248         {
 249                 .name = "ppp",
 250                 .cmd = HNAE3_DBG_CMD_REG_PPP,
 251                 .dentry = HNS3_DBG_DENTRY_REG,
 252                 .buf_len = HNS3_DBG_READ_LEN,
 253                 .init = hns3_dbg_common_file_init,
 254         },
 255         {
 256                 .name = "rcb",
 257                 .cmd = HNAE3_DBG_CMD_REG_RCB,
 258                 .dentry = HNS3_DBG_DENTRY_REG,
 259                 .buf_len = HNS3_DBG_READ_LEN,
 260                 .init = hns3_dbg_common_file_init,
 261         },
 262         {
 263                 .name = "tqp",
 264                 .cmd = HNAE3_DBG_CMD_REG_TQP,
 265                 .dentry = HNS3_DBG_DENTRY_REG,
 266                 .buf_len = HNS3_DBG_READ_LEN_128KB,
 267                 .init = hns3_dbg_common_file_init,
 268         },
 269         {
 270                 .name = "mac",
 271                 .cmd = HNAE3_DBG_CMD_REG_MAC,
 272                 .dentry = HNS3_DBG_DENTRY_REG,
 273                 .buf_len = HNS3_DBG_READ_LEN,
 274                 .init = hns3_dbg_common_file_init,
 275         },
 276         {
 277                 .name = "dcb",
 278                 .cmd = HNAE3_DBG_CMD_REG_DCB,
 279                 .dentry = HNS3_DBG_DENTRY_REG,
 280                 .buf_len = HNS3_DBG_READ_LEN,
 281                 .init = hns3_dbg_common_file_init,
 282         },
 283         {
 284                 .name = "queue_map",
 285                 .cmd = HNAE3_DBG_CMD_QUEUE_MAP,
 286                 .dentry = HNS3_DBG_DENTRY_QUEUE,
 287                 .buf_len = HNS3_DBG_READ_LEN,
 288                 .init = hns3_dbg_common_file_init,
 289         },
 290         {
 291                 .name = "rx_queue_info",
 292                 .cmd = HNAE3_DBG_CMD_RX_QUEUE_INFO,
 293                 .dentry = HNS3_DBG_DENTRY_QUEUE,
 294                 .buf_len = HNS3_DBG_READ_LEN_1MB,
 295                 .init = hns3_dbg_common_file_init,
 296         },
 297         {
 298                 .name = "tx_queue_info",
 299                 .cmd = HNAE3_DBG_CMD_TX_QUEUE_INFO,
 300                 .dentry = HNS3_DBG_DENTRY_QUEUE,
 301                 .buf_len = HNS3_DBG_READ_LEN_1MB,
 302                 .init = hns3_dbg_common_file_init,
 303         },
 304         {
 305                 .name = "fd_tcam",
 306                 .cmd = HNAE3_DBG_CMD_FD_TCAM,
 307                 .dentry = HNS3_DBG_DENTRY_FD,
 308                 .buf_len = HNS3_DBG_READ_LEN_1MB,
 309                 .init = hns3_dbg_common_file_init,
 310         },
 311         {
 312                 .name = "service_task_info",
 313                 .cmd = HNAE3_DBG_CMD_SERV_INFO,
 314                 .dentry = HNS3_DBG_DENTRY_COMMON,
 315                 .buf_len = HNS3_DBG_READ_LEN,
 316                 .init = hns3_dbg_common_file_init,
 317         },
 318         {
 319                 .name = "vlan_config",
 320                 .cmd = HNAE3_DBG_CMD_VLAN_CONFIG,
 321                 .dentry = HNS3_DBG_DENTRY_COMMON,
 322                 .buf_len = HNS3_DBG_READ_LEN,
 323                 .init = hns3_dbg_common_file_init,
 324         },
 325         {
 326                 .name = "ptp_info",
 327                 .cmd = HNAE3_DBG_CMD_PTP_INFO,
 328                 .dentry = HNS3_DBG_DENTRY_COMMON,
 329                 .buf_len = HNS3_DBG_READ_LEN,
 330                 .init = hns3_dbg_common_file_init,
 331         },
 332         {
 333                 .name = "fd_counter",
 334                 .cmd = HNAE3_DBG_CMD_FD_COUNTER,
 335                 .dentry = HNS3_DBG_DENTRY_FD,
 336                 .buf_len = HNS3_DBG_READ_LEN,
 337                 .init = hns3_dbg_common_file_init,
 338         },
 339         {
 340                 .name = "umv_info",
 341                 .cmd = HNAE3_DBG_CMD_UMV_INFO,
 342                 .dentry = HNS3_DBG_DENTRY_COMMON,
 343                 .buf_len = HNS3_DBG_READ_LEN,
 344                 .init = hns3_dbg_common_file_init,
 345         },
 346         {
 347                 .name = "page_pool_info",
 348                 .cmd = HNAE3_DBG_CMD_PAGE_POOL_INFO,
 349                 .dentry = HNS3_DBG_DENTRY_COMMON,
 350                 .buf_len = HNS3_DBG_READ_LEN,
 351                 .init = hns3_dbg_common_file_init,
 352         },
 353         {
 354                 .name = "coalesce_info",
 355                 .cmd = HNAE3_DBG_CMD_COAL_INFO,
 356                 .dentry = HNS3_DBG_DENTRY_COMMON,
 357                 .buf_len = HNS3_DBG_READ_LEN_1MB,
 358                 .init = hns3_dbg_common_file_init,
 359         },
 360 };
 361
 362 static struct hns3_dbg_cap_info hns3_dbg_cap[] = {
 363         {
 364                 .name = "support FD",
 365                 .cap_bit = HNAE3_DEV_SUPPORT_FD_B,
 366         }, {
 367                 .name = "support GRO",
 368                 .cap_bit = HNAE3_DEV_SUPPORT_GRO_B,
 369         }, {
 370                 .name = "support FEC",
 371                 .cap_bit = HNAE3_DEV_SUPPORT_FEC_B,
 372         }, {
 373                 .name = "support UDP GSO",
 374                 .cap_bit = HNAE3_DEV_SUPPORT_UDP_GSO_B,
 375         }, {
 376                 .name = "support PTP",
 377                 .cap_bit = HNAE3_DEV_SUPPORT_PTP_B,
 378         }, {
 379                 .name = "support INT QL",
 380                 .cap_bit = HNAE3_DEV_SUPPORT_INT_QL_B,
 381         }, {
 382                 .name = "support HW TX csum",
 383                 .cap_bit = HNAE3_DEV_SUPPORT_HW_TX_CSUM_B,
 384         }, {
 385                 .name = "support UDP tunnel csum",
 386                 .cap_bit = HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B,
 387         }, {
 388                 .name = "support TX push",
 389                 .cap_bit = HNAE3_DEV_SUPPORT_TX_PUSH_B,
 390         }, {
 391                 .name = "support imp-controlled PHY",
 392                 .cap_bit = HNAE3_DEV_SUPPORT_PHY_IMP_B,
 393         }, {
 394                 .name = "support imp-controlled RAS",
 395                 .cap_bit = HNAE3_DEV_SUPPORT_RAS_IMP_B,
 396         }, {
 397                 .name = "support rxd advanced layout",
 398                 .cap_bit = HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B,
 399         }, {
 400                 .name = "support port vlan bypass",
 401                 .cap_bit = HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B,
 402         }, {
 403                 .name = "support modify vlan filter state",
 404                 .cap_bit = HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B,
 405         }, {
 406                 .name = "support FEC statistics",
 407                 .cap_bit = HNAE3_DEV_SUPPORT_FEC_STATS_B,
 408         }, {
 409                 .name = "support lane num",
 410                 .cap_bit = HNAE3_DEV_SUPPORT_LANE_NUM_B,
 411         }, {
 412                 .name = "support wake on lan",
 413                 .cap_bit = HNAE3_DEV_SUPPORT_WOL_B,
 414         }, {
 415                 .name = "support tm flush",
 416                 .cap_bit = HNAE3_DEV_SUPPORT_TM_FLUSH_B,
 417         }
 418 };
 419
 420 static const struct hns3_dbg_item coal_info_items[] = {
 421         { "VEC_ID", 2 },
 422         { "ALGO_STATE", 2 },
 423         { "PROFILE_ID", 2 },
 424         { "CQE_MODE", 2 },
 425         { "TUNE_STATE", 2 },
 426         { "STEPS_LEFT", 2 },
 427         { "STEPS_RIGHT", 2 },
 428         { "TIRED", 2 },
 429         { "SW_GL", 2 },
 430         { "SW_QL", 2 },
 431         { "HW_GL", 2 },
 432         { "HW_QL", 2 },
 433 };
 434
 435 static const char * const dim_cqe_mode_str[] = { "EQE", "CQE" };
 436 static const char * const dim_state_str[] = { "START", "IN_PROG", "APPLY" };
 437 static const char * const
 438 dim_tune_stat_str[] = { "ON_TOP", "TIRED", "RIGHT", "LEFT" };
 439
 440 static void hns3_dbg_fill_content(char *content, u16 len,
 441                                   const struct hns3_dbg_item *items,
 442                                   const char **result, u16 size)
 443 {
 444 #define HNS3_DBG_LINE_END_LEN   2
 445         char *pos = content;
 446         u16 item_len;
 447         u16 i;
 448
 449         if (!len) {
 450                 return;
 451         } else if (len <= HNS3_DBG_LINE_END_LEN) {
 452                 *pos++ = '\0';
 453                 return;
 454         }
 455
 456         memset(content, ' ', len);
 457         len -= HNS3_DBG_LINE_END_LEN;
 458
 459         for (i = 0; i < size; i++) {
 460                 item_len = strlen(items[i].name) + items[i].interval;
 461                 if (len < item_len)
 462                         break;
 463
 464                 if (result) {
 465                         if (item_len < strlen(result[i]))
 466                                 break;
 467                         memcpy(pos, result[i], strlen(result[i]));
 468                 } else {
 469                         memcpy(pos, items[i].name, strlen(items[i].name));
 470                 }
 471                 pos += item_len;
 472                 len -= item_len;
 473         }
 474         *pos++ = '\n';
 475         *pos++ = '\0';
 476 }
 477
 478 static void hns3_get_coal_info(struct hns3_enet_tqp_vector *tqp_vector,
 479                                char **result, int i, bool is_tx)
 480 {
 481         unsigned int gl_offset, ql_offset;
 482         struct hns3_enet_coalesce *coal;
 483         unsigned int reg_val;
 484         unsigned int j = 0;
 485         struct dim *dim;
 486         bool ql_enable;
 487
 488         if (is_tx) {
 489                 coal = &tqp_vector->tx_group.coal;
 490                 dim = &tqp_vector->tx_group.dim;
 491                 gl_offset = HNS3_VECTOR_GL1_OFFSET;
 492                 ql_offset = HNS3_VECTOR_TX_QL_OFFSET;
 493                 ql_enable = tqp_vector->tx_group.coal.ql_enable;
 494         } else {
 495                 coal = &tqp_vector->rx_group.coal;
 496                 dim = &tqp_vector->rx_group.dim;
 497                 gl_offset = HNS3_VECTOR_GL0_OFFSET;
 498                 ql_offset = HNS3_VECTOR_RX_QL_OFFSET;
 499                 ql_enable = tqp_vector->rx_group.coal.ql_enable;
 500         }
 501
 502         sprintf(result[j++], "%d", i);
 503         sprintf(result[j++], "%s", dim_state_str[dim->state]);
 504         sprintf(result[j++], "%u", dim->profile_ix);
 505         sprintf(result[j++], "%s", dim_cqe_mode_str[dim->mode]);
 506         sprintf(result[j++], "%s",
 507                 dim_tune_stat_str[dim->tune_state]);
 508         sprintf(result[j++], "%u", dim->steps_left);
 509         sprintf(result[j++], "%u", dim->steps_right);
 510         sprintf(result[j++], "%u", dim->tired);
 511         sprintf(result[j++], "%u", coal->int_gl);
 512         sprintf(result[j++], "%u", coal->int_ql);
 513         reg_val = readl(tqp_vector->mask_addr + gl_offset) &
 514                   HNS3_VECTOR_GL_MASK;
 515         sprintf(result[j++], "%u", reg_val);
 516         if (ql_enable) {
 517                 reg_val = readl(tqp_vector->mask_addr + ql_offset) &
 518                           HNS3_VECTOR_QL_MASK;
 519                 sprintf(result[j++], "%u", reg_val);
 520         } else {
 521                 sprintf(result[j++], "NA");
 522         }
 523 }
 524
 525 static void hns3_dump_coal_info(struct hnae3_handle *h, char *buf, int len,
 526                                 int *pos, bool is_tx)
 527 {
 528         char data_str[ARRAY_SIZE(coal_info_items)][HNS3_DBG_DATA_STR_LEN];
 529         char *result[ARRAY_SIZE(coal_info_items)];
 530         struct hns3_enet_tqp_vector *tqp_vector;
 531         struct hns3_nic_priv *priv = h->priv;
 532         char content[HNS3_DBG_INFO_LEN];
 533         unsigned int i;
 534
 535         for (i = 0; i < ARRAY_SIZE(coal_info_items); i++)
 536                 result[i] = &data_str[i][0];
 537
 538         *pos += scnprintf(buf + *pos, len - *pos,
 539                           "%s interrupt coalesce info:\n",
 540                           is_tx ? "tx" : "rx");
 541         hns3_dbg_fill_content(content, sizeof(content), coal_info_items,
 542                               NULL, ARRAY_SIZE(coal_info_items));
 543         *pos += scnprintf(buf + *pos, len - *pos, "%s", content);
 544
 545         for (i = 0; i < priv->vector_num; i++) {
 546                 tqp_vector = &priv->tqp_vector[i];
 547                 hns3_get_coal_info(tqp_vector, result, i, is_tx);
 548                 hns3_dbg_fill_content(content, sizeof(content), coal_info_items,
 549                                       (const char **)result,
 550                                       ARRAY_SIZE(coal_info_items));
 551                 *pos += scnprintf(buf + *pos, len - *pos, "%s", content);
 552         }
 553 }
 554
 555 static int hns3_dbg_coal_info(struct hnae3_handle *h, char *buf, int len)
 556 {
 557         int pos = 0;
 558
 559         hns3_dump_coal_info(h, buf, len, &pos, true);
 560         pos += scnprintf(buf + pos, len - pos, "\n");
 561         hns3_dump_coal_info(h, buf, len, &pos, false);
 562
 563         return 0;
 564 }
 565
 566 static const struct hns3_dbg_item tx_spare_info_items[] = {
 567         { "QUEUE_ID", 2 },
 568         { "COPYBREAK", 2 },
 569         { "LEN", 7 },
 570         { "NTU", 4 },
 571         { "NTC", 4 },
 572         { "LTC", 4 },
 573         { "DMA", 17 },
 574 };
 575
 576 static void hns3_dbg_tx_spare_info(struct hns3_enet_ring *ring, char *buf,
 577                                    int len, u32 ring_num, int *pos)
 578 {
 579         char data_str[ARRAY_SIZE(tx_spare_info_items)][HNS3_DBG_DATA_STR_LEN];
 580         struct hns3_tx_spare *tx_spare = ring->tx_spare;
 581         char *result[ARRAY_SIZE(tx_spare_info_items)];
 582         char content[HNS3_DBG_INFO_LEN];
 583         u32 i, j;
 584
 585         if (!tx_spare) {
 586                 *pos += scnprintf(buf + *pos, len - *pos,
 587                                   "tx spare buffer is not enabled\n");
 588                 return;
 589         }
 590
 591         for (i = 0; i < ARRAY_SIZE(tx_spare_info_items); i++)
 592                 result[i] = &data_str[i][0];
 593
 594         *pos += scnprintf(buf + *pos, len - *pos, "tx spare buffer info\n");
 595         hns3_dbg_fill_content(content, sizeof(content), tx_spare_info_items,
 596                               NULL, ARRAY_SIZE(tx_spare_info_items));
 597         *pos += scnprintf(buf + *pos, len - *pos, "%s", content);
 598
 599         for (i = 0; i < ring_num; i++) {
 600                 j = 0;
 601                 sprintf(result[j++], "%u", i);
 602                 sprintf(result[j++], "%u", ring->tx_copybreak);
 603                 sprintf(result[j++], "%u", tx_spare->len);
 604                 sprintf(result[j++], "%u", tx_spare->next_to_use);
 605                 sprintf(result[j++], "%u", tx_spare->next_to_clean);
 606                 sprintf(result[j++], "%u", tx_spare->last_to_clean);
 607                 sprintf(result[j++], "%pad", &tx_spare->dma);
 608                 hns3_dbg_fill_content(content, sizeof(content),
 609                                       tx_spare_info_items,
 610                                       (const char **)result,
 611                                       ARRAY_SIZE(tx_spare_info_items));
 612                 *pos += scnprintf(buf + *pos, len - *pos, "%s", content);
 613         }
 614 }
 615
 616 static const struct hns3_dbg_item rx_queue_info_items[] = {
 617         { "QUEUE_ID", 2 },
 618         { "BD_NUM", 2 },
 619         { "BD_LEN", 2 },
 620         { "TAIL", 2 },
 621         { "HEAD", 2 },
 622         { "FBDNUM", 2 },
 623         { "PKTNUM", 5 },
 624         { "COPYBREAK", 2 },
 625         { "RING_EN", 2 },
 626         { "RX_RING_EN", 2 },
 627         { "BASE_ADDR", 10 },
 628 };
 629
 630 static void hns3_dump_rx_queue_info(struct hns3_enet_ring *ring,
 631                                     struct hnae3_ae_dev *ae_dev, char **result,
 632                                     u32 index)
 633 {
 634         u32 base_add_l, base_add_h;
 635         u32 j = 0;
 636
 637         sprintf(result[j++], "%u", index);
 638
 639         sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
 640                 HNS3_RING_RX_RING_BD_NUM_REG));
 641
 642         sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
 643                 HNS3_RING_RX_RING_BD_LEN_REG));
 644
 645         sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
 646                 HNS3_RING_RX_RING_TAIL_REG));
 647
 648         sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
 649                 HNS3_RING_RX_RING_HEAD_REG));
 650
 651         sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
 652                 HNS3_RING_RX_RING_FBDNUM_REG));
 653
 654         sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
 655                 HNS3_RING_RX_RING_PKTNUM_RECORD_REG));
 656         sprintf(result[j++], "%u", ring->rx_copybreak);
 657
 658         sprintf(result[j++], "%s", readl_relaxed(ring->tqp->io_base +
 659                 HNS3_RING_EN_REG) ? "on" : "off");
 660
 661         if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev))
 662                 sprintf(result[j++], "%s", readl_relaxed(ring->tqp->io_base +
 663                         HNS3_RING_RX_EN_REG) ? "on" : "off");
 664         else
 665                 sprintf(result[j++], "%s", "NA");
 666
 667         base_add_h = readl_relaxed(ring->tqp->io_base +
 668                                         HNS3_RING_RX_RING_BASEADDR_H_REG);
 669         base_add_l = readl_relaxed(ring->tqp->io_base +
 670                                         HNS3_RING_RX_RING_BASEADDR_L_REG);
 671         sprintf(result[j++], "0x%08x%08x", base_add_h, base_add_l);
 672 }
 673
 674 static int hns3_dbg_rx_queue_info(struct hnae3_handle *h,
 675                                   char *buf, int len)
 676 {
 677         char data_str[ARRAY_SIZE(rx_queue_info_items)][HNS3_DBG_DATA_STR_LEN];
 678         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
 679         char *result[ARRAY_SIZE(rx_queue_info_items)];
 680         struct hns3_nic_priv *priv = h->priv;
 681         char content[HNS3_DBG_INFO_LEN];
 682         struct hns3_enet_ring *ring;
 683         int pos = 0;
 684         u32 i;
 685
 686         if (!priv->ring) {
 687                 dev_err(&h->pdev->dev, "priv->ring is NULL\n");
 688                 return -EFAULT;
 689         }
 690
 691         for (i = 0; i < ARRAY_SIZE(rx_queue_info_items); i++)
 692                 result[i] = &data_str[i][0];
 693
 694         hns3_dbg_fill_content(content, sizeof(content), rx_queue_info_items,
 695                               NULL, ARRAY_SIZE(rx_queue_info_items));
 696         pos += scnprintf(buf + pos, len - pos, "%s", content);
 697         for (i = 0; i < h->kinfo.num_tqps; i++) {
 698                 /* Each cycle needs to determine whether the instance is reset,
 699                  * to prevent reference to invalid memory. And need to ensure
 700                  * that the following code is executed within 100ms.
 701                  */
 702                 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) ||
 703                     test_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
 704                         return -EPERM;
 705
 706                 ring = &priv->ring[(u32)(i + h->kinfo.num_tqps)];
 707                 hns3_dump_rx_queue_info(ring, ae_dev, result, i);
 708                 hns3_dbg_fill_content(content, sizeof(content),
 709                                       rx_queue_info_items,
 710                                       (const char **)result,
 711                                       ARRAY_SIZE(rx_queue_info_items));
 712                 pos += scnprintf(buf + pos, len - pos, "%s", content);
 713         }
 714
 715         return 0;
 716 }
 717
 718 static const struct hns3_dbg_item tx_queue_info_items[] = {
 719         { "QUEUE_ID", 2 },
 720         { "BD_NUM", 2 },
 721         { "TC", 2 },
 722         { "TAIL", 2 },
 723         { "HEAD", 2 },
 724         { "FBDNUM", 2 },
 725         { "OFFSET", 2 },
 726         { "PKTNUM", 5 },
 727         { "RING_EN", 2 },
 728         { "TX_RING_EN", 2 },
 729         { "BASE_ADDR", 10 },
 730 };
 731
 732 static void hns3_dump_tx_queue_info(struct hns3_enet_ring *ring,
 733                                     struct hnae3_ae_dev *ae_dev, char **result,
 734                                     u32 index)
 735 {
 736         u32 base_add_l, base_add_h;
 737         u32 j = 0;
 738
 739         sprintf(result[j++], "%u", index);
 740         sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
 741                 HNS3_RING_TX_RING_BD_NUM_REG));
 742
 743         sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
 744                 HNS3_RING_TX_RING_TC_REG));
 745
 746         sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
 747                 HNS3_RING_TX_RING_TAIL_REG));
 748
 749         sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
 750                 HNS3_RING_TX_RING_HEAD_REG));
 751
 752         sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
 753                 HNS3_RING_TX_RING_FBDNUM_REG));
 754
 755         sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
 756                 HNS3_RING_TX_RING_OFFSET_REG));
 757
 758         sprintf(result[j++], "%u", readl_relaxed(ring->tqp->io_base +
 759                 HNS3_RING_TX_RING_PKTNUM_RECORD_REG));
 760
 761         sprintf(result[j++], "%s", readl_relaxed(ring->tqp->io_base +
 762                 HNS3_RING_EN_REG) ? "on" : "off");
 763
 764         if (hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev))
 765                 sprintf(result[j++], "%s", readl_relaxed(ring->tqp->io_base +
 766                         HNS3_RING_TX_EN_REG) ? "on" : "off");
 767         else
 768                 sprintf(result[j++], "%s", "NA");
 769
 770         base_add_h = readl_relaxed(ring->tqp->io_base +
 771                                         HNS3_RING_TX_RING_BASEADDR_H_REG);
 772         base_add_l = readl_relaxed(ring->tqp->io_base +
 773                                         HNS3_RING_TX_RING_BASEADDR_L_REG);
 774         sprintf(result[j++], "0x%08x%08x", base_add_h, base_add_l);
 775 }
 776
 777 static int hns3_dbg_tx_queue_info(struct hnae3_handle *h,
 778                                   char *buf, int len)
 779 {
 780         char data_str[ARRAY_SIZE(tx_queue_info_items)][HNS3_DBG_DATA_STR_LEN];
 781         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
 782         char *result[ARRAY_SIZE(tx_queue_info_items)];
 783         struct hns3_nic_priv *priv = h->priv;
 784         char content[HNS3_DBG_INFO_LEN];
 785         struct hns3_enet_ring *ring;
 786         int pos = 0;
 787         u32 i;
 788
 789         if (!priv->ring) {
 790                 dev_err(&h->pdev->dev, "priv->ring is NULL\n");
 791                 return -EFAULT;
 792         }
 793
 794         for (i = 0; i < ARRAY_SIZE(tx_queue_info_items); i++)
 795                 result[i] = &data_str[i][0];
 796
 797         hns3_dbg_fill_content(content, sizeof(content), tx_queue_info_items,
 798                               NULL, ARRAY_SIZE(tx_queue_info_items));
 799         pos += scnprintf(buf + pos, len - pos, "%s", content);
 800
 801         for (i = 0; i < h->kinfo.num_tqps; i++) {
 802                 /* Each cycle needs to determine whether the instance is reset,
 803                  * to prevent reference to invalid memory. And need to ensure
 804                  * that the following code is executed within 100ms.
 805                  */
 806                 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) ||
 807                     test_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
 808                         return -EPERM;
 809
 810                 ring = &priv->ring[i];
 811                 hns3_dump_tx_queue_info(ring, ae_dev, result, i);
 812                 hns3_dbg_fill_content(content, sizeof(content),
 813                                       tx_queue_info_items,
 814                                       (const char **)result,
 815                                       ARRAY_SIZE(tx_queue_info_items));
 816                 pos += scnprintf(buf + pos, len - pos, "%s", content);
 817         }
 818
 819         hns3_dbg_tx_spare_info(ring, buf, len, h->kinfo.num_tqps, &pos);
 820
 821         return 0;
 822 }
 823
 824 static const struct hns3_dbg_item queue_map_items[] = {
 825         { "local_queue_id", 2 },
 826         { "global_queue_id", 2 },
 827         { "vector_id", 2 },
 828 };
 829
 830 static int hns3_dbg_queue_map(struct hnae3_handle *h, char *buf, int len)
 831 {
 832         char data_str[ARRAY_SIZE(queue_map_items)][HNS3_DBG_DATA_STR_LEN];
 833         char *result[ARRAY_SIZE(queue_map_items)];
 834         struct hns3_nic_priv *priv = h->priv;
 835         char content[HNS3_DBG_INFO_LEN];
 836         int pos = 0;
 837         int j;
 838         u32 i;
 839
 840         if (!h->ae_algo->ops->get_global_queue_id)
 841                 return -EOPNOTSUPP;
 842
 843         for (i = 0; i < ARRAY_SIZE(queue_map_items); i++)
 844                 result[i] = &data_str[i][0];
 845
 846         hns3_dbg_fill_content(content, sizeof(content), queue_map_items,
 847                               NULL, ARRAY_SIZE(queue_map_items));
 848         pos += scnprintf(buf + pos, len - pos, "%s", content);
 849         for (i = 0; i < h->kinfo.num_tqps; i++) {
 850                 if (!priv->ring || !priv->ring[i].tqp_vector)
 851                         continue;
 852                 j = 0;
 853                 sprintf(result[j++], "%u", i);
 854                 sprintf(result[j++], "%u",
 855                         h->ae_algo->ops->get_global_queue_id(h, i));
 856                 sprintf(result[j++], "%d",
 857                         priv->ring[i].tqp_vector->vector_irq);
 858                 hns3_dbg_fill_content(content, sizeof(content), queue_map_items,
 859                                       (const char **)result,
 860                                       ARRAY_SIZE(queue_map_items));
 861                 pos += scnprintf(buf + pos, len - pos, "%s", content);
 862         }
 863
 864         return 0;
 865 }
 866
 867 static const struct hns3_dbg_item rx_bd_info_items[] = {
 868         { "BD_IDX", 3 },
 869         { "L234_INFO", 2 },
 870         { "PKT_LEN", 3 },
 871         { "SIZE", 4 },
 872         { "RSS_HASH", 4 },
 873         { "FD_ID", 2 },
 874         { "VLAN_TAG", 2 },
 875         { "O_DM_VLAN_ID_FB", 2 },
 876         { "OT_VLAN_TAG", 2 },
 877         { "BD_BASE_INFO", 2 },
 878         { "PTYPE", 2 },
 879         { "HW_CSUM", 2 },
 880 };
 881
 882 static void hns3_dump_rx_bd_info(struct hns3_nic_priv *priv,
 883                                  struct hns3_desc *desc, char **result, int idx)
 884 {
 885         unsigned int j = 0;
 886
 887         sprintf(result[j++], "%d", idx);
 888         sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.l234_info));
 889         sprintf(result[j++], "%u", le16_to_cpu(desc->rx.pkt_len));
 890         sprintf(result[j++], "%u", le16_to_cpu(desc->rx.size));
 891         sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.rss_hash));
 892         sprintf(result[j++], "%u", le16_to_cpu(desc->rx.fd_id));
 893         sprintf(result[j++], "%u", le16_to_cpu(desc->rx.vlan_tag));
 894         sprintf(result[j++], "%u", le16_to_cpu(desc->rx.o_dm_vlan_id_fb));
 895         sprintf(result[j++], "%u", le16_to_cpu(desc->rx.ot_vlan_tag));
 896         sprintf(result[j++], "%#x", le32_to_cpu(desc->rx.bd_base_info));
 897         if (test_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state)) {
 898                 u32 ol_info = le32_to_cpu(desc->rx.ol_info);
 899
 900                 sprintf(result[j++], "%5lu", hnae3_get_field(ol_info,
 901                                                              HNS3_RXD_PTYPE_M,
 902                                                              HNS3_RXD_PTYPE_S));
 903                 sprintf(result[j++], "%7u", le16_to_cpu(desc->csum));
 904         } else {
 905                 sprintf(result[j++], "NA");
 906                 sprintf(result[j++], "NA");
 907         }
 908 }
 909
 910 static int hns3_dbg_rx_bd_info(struct hns3_dbg_data *d, char *buf, int len)
 911 {
 912         char data_str[ARRAY_SIZE(rx_bd_info_items)][HNS3_DBG_DATA_STR_LEN];
 913         struct hns3_nic_priv *priv = d->handle->priv;
 914         char *result[ARRAY_SIZE(rx_bd_info_items)];
 915         char content[HNS3_DBG_INFO_LEN];
 916         struct hns3_enet_ring *ring;
 917         struct hns3_desc *desc;
 918         unsigned int i;
 919         int pos = 0;
 920
 921         if (d->qid >= d->handle->kinfo.num_tqps) {
 922                 dev_err(&d->handle->pdev->dev,
 923                         "queue%u is not in use\n", d->qid);
 924                 return -EINVAL;
 925         }
 926
 927         for (i = 0; i < ARRAY_SIZE(rx_bd_info_items); i++)
 928                 result[i] = &data_str[i][0];
 929
 930         pos += scnprintf(buf + pos, len - pos,
 931                           "Queue %u rx bd info:\n", d->qid);
 932         hns3_dbg_fill_content(content, sizeof(content), rx_bd_info_items,
 933                               NULL, ARRAY_SIZE(rx_bd_info_items));
 934         pos += scnprintf(buf + pos, len - pos, "%s", content);
 935
 936         ring = &priv->ring[d->qid + d->handle->kinfo.num_tqps];
 937         for (i = 0; i < ring->desc_num; i++) {
 938                 desc = &ring->desc[i];
 939
 940                 hns3_dump_rx_bd_info(priv, desc, result, i);
 941                 hns3_dbg_fill_content(content, sizeof(content),
 942                                       rx_bd_info_items, (const char **)result,
 943                                       ARRAY_SIZE(rx_bd_info_items));
 944                 pos += scnprintf(buf + pos, len - pos, "%s", content);
 945         }
 946
 947         return 0;
 948 }
 949
 950 static const struct hns3_dbg_item tx_bd_info_items[] = {
 951         { "BD_IDX", 2 },
 952         { "ADDRESS", 13 },
 953         { "VLAN_TAG", 2 },
 954         { "SIZE", 2 },
 955         { "T_CS_VLAN_TSO", 2 },
 956         { "OT_VLAN_TAG", 3 },
 957         { "TV", 5 },
 958         { "OLT_VLAN_LEN", 2 },
 959         { "PAYLEN_OL4CS", 2 },
 960         { "BD_FE_SC_VLD", 2 },
 961         { "MSS_HW_CSUM", 0 },
 962 };
 963
 964 static void hns3_dump_tx_bd_info(struct hns3_desc *desc, char **result, int idx)
 965 {
 966         unsigned int j = 0;
 967
 968         sprintf(result[j++], "%d", idx);
 969         sprintf(result[j++], "%#llx", le64_to_cpu(desc->addr));
 970         sprintf(result[j++], "%u", le16_to_cpu(desc->tx.vlan_tag));
 971         sprintf(result[j++], "%u", le16_to_cpu(desc->tx.send_size));
 972         sprintf(result[j++], "%#x",
 973                 le32_to_cpu(desc->tx.type_cs_vlan_tso_len));
 974         sprintf(result[j++], "%u", le16_to_cpu(desc->tx.outer_vlan_tag));
 975         sprintf(result[j++], "%u", le16_to_cpu(desc->tx.tv));
 976         sprintf(result[j++], "%u",
 977                 le32_to_cpu(desc->tx.ol_type_vlan_len_msec));
 978         sprintf(result[j++], "%#x", le32_to_cpu(desc->tx.paylen_ol4cs));
 979         sprintf(result[j++], "%#x", le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri));
 980         sprintf(result[j++], "%u", le16_to_cpu(desc->tx.mss_hw_csum));
 981 }
 982
 983 static int hns3_dbg_tx_bd_info(struct hns3_dbg_data *d, char *buf, int len)
 984 {
 985         char data_str[ARRAY_SIZE(tx_bd_info_items)][HNS3_DBG_DATA_STR_LEN];
 986         struct hns3_nic_priv *priv = d->handle->priv;
 987         char *result[ARRAY_SIZE(tx_bd_info_items)];
 988         char content[HNS3_DBG_INFO_LEN];
 989         struct hns3_enet_ring *ring;
 990         struct hns3_desc *desc;
 991         unsigned int i;
 992         int pos = 0;
 993
 994         if (d->qid >= d->handle->kinfo.num_tqps) {
 995                 dev_err(&d->handle->pdev->dev,
 996                         "queue%u is not in use\n", d->qid);
 997                 return -EINVAL;
 998         }
 999
1000         for (i = 0; i < ARRAY_SIZE(tx_bd_info_items); i++)
1001                 result[i] = &data_str[i][0];
1002
1003         pos += scnprintf(buf + pos, len - pos,
1004                           "Queue %u tx bd info:\n", d->qid);
1005         hns3_dbg_fill_content(content, sizeof(content), tx_bd_info_items,
1006                               NULL, ARRAY_SIZE(tx_bd_info_items));
1007         pos += scnprintf(buf + pos, len - pos, "%s", content);
1008
1009         ring = &priv->ring[d->qid];
1010         for (i = 0; i < ring->desc_num; i++) {
1011                 desc = &ring->desc[i];
1012
1013                 hns3_dump_tx_bd_info(desc, result, i);
1014                 hns3_dbg_fill_content(content, sizeof(content),
1015                                       tx_bd_info_items, (const char **)result,
1016                                       ARRAY_SIZE(tx_bd_info_items));
1017                 pos += scnprintf(buf + pos, len - pos, "%s", content);
1018         }
1019
1020         return 0;
1021 }
1022
1023 static void
1024 hns3_dbg_dev_caps(struct hnae3_handle *h, char *buf, int len, int *pos)
1025 {
1026         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
1027         const char * const str[] = {"no", "yes"};
1028         unsigned long *caps = ae_dev->caps;
1029         u32 i, state;
1030
1031         *pos += scnprintf(buf + *pos, len - *pos, "dev capability:\n");
1032
1033         for (i = 0; i < ARRAY_SIZE(hns3_dbg_cap); i++) {
1034                 state = test_bit(hns3_dbg_cap[i].cap_bit, caps);
1035                 *pos += scnprintf(buf + *pos, len - *pos, "%s: %s\n",
1036                                   hns3_dbg_cap[i].name, str[state]);
1037         }
1038
1039         *pos += scnprintf(buf + *pos, len - *pos, "\n");
1040 }
1041
1042 static void
1043 hns3_dbg_dev_specs(struct hnae3_handle *h, char *buf, int len, int *pos)
1044 {
1045         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
1046         struct hnae3_dev_specs *dev_specs = &ae_dev->dev_specs;
1047         struct hnae3_knic_private_info *kinfo = &h->kinfo;
1048
1049         *pos += scnprintf(buf + *pos, len - *pos, "dev_spec:\n");
1050         *pos += scnprintf(buf + *pos, len - *pos, "MAC entry num: %u\n",
1051                           dev_specs->mac_entry_num);
1052         *pos += scnprintf(buf + *pos, len - *pos, "MNG entry num: %u\n",
1053                           dev_specs->mng_entry_num);
1054         *pos += scnprintf(buf + *pos, len - *pos, "MAX non tso bd num: %u\n",
1055                           dev_specs->max_non_tso_bd_num);
1056         *pos += scnprintf(buf + *pos, len - *pos, "RSS ind tbl size: %u\n",
1057                           dev_specs->rss_ind_tbl_size);
1058         *pos += scnprintf(buf + *pos, len - *pos, "RSS key size: %u\n",
1059                           dev_specs->rss_key_size);
1060         *pos += scnprintf(buf + *pos, len - *pos, "RSS size: %u\n",
1061                           kinfo->rss_size);
1062         *pos += scnprintf(buf + *pos, len - *pos, "Allocated RSS size: %u\n",
1063                           kinfo->req_rss_size);
1064         *pos += scnprintf(buf + *pos, len - *pos,
1065                           "Task queue pairs numbers: %u\n",
1066                           kinfo->num_tqps);
1067         *pos += scnprintf(buf + *pos, len - *pos, "RX buffer length: %u\n",
1068                           kinfo->rx_buf_len);
1069         *pos += scnprintf(buf + *pos, len - *pos, "Desc num per TX queue: %u\n",
1070                           kinfo->num_tx_desc);
1071         *pos += scnprintf(buf + *pos, len - *pos, "Desc num per RX queue: %u\n",
1072                           kinfo->num_rx_desc);
1073         *pos += scnprintf(buf + *pos, len - *pos,
1074                           "Total number of enabled TCs: %u\n",
1075                           kinfo->tc_info.num_tc);
1076         *pos += scnprintf(buf + *pos, len - *pos, "MAX INT QL: %u\n",
1077                           dev_specs->int_ql_max);
1078         *pos += scnprintf(buf + *pos, len - *pos, "MAX INT GL: %u\n",
1079                           dev_specs->max_int_gl);
1080         *pos += scnprintf(buf + *pos, len - *pos, "MAX TM RATE: %u\n",
1081                           dev_specs->max_tm_rate);
1082         *pos += scnprintf(buf + *pos, len - *pos, "MAX QSET number: %u\n",
1083                           dev_specs->max_qset_num);
1084         *pos += scnprintf(buf + *pos, len - *pos, "umv size: %u\n",
1085                           dev_specs->umv_size);
1086         *pos += scnprintf(buf + *pos, len - *pos, "mc mac size: %u\n",
1087                           dev_specs->mc_mac_size);
1088         *pos += scnprintf(buf + *pos, len - *pos, "MAC statistics number: %u\n",
1089                           dev_specs->mac_stats_num);
1090 }
1091
1092 static int hns3_dbg_dev_info(struct hnae3_handle *h, char *buf, int len)
1093 {
1094         int pos = 0;
1095
1096         hns3_dbg_dev_caps(h, buf, len, &pos);
1097
1098         hns3_dbg_dev_specs(h, buf, len, &pos);
1099
1100         return 0;
1101 }
1102
1103 static const struct hns3_dbg_item page_pool_info_items[] = {
1104         { "QUEUE_ID", 2 },
1105         { "ALLOCATE_CNT", 2 },
1106         { "FREE_CNT", 6 },
1107         { "POOL_SIZE(PAGE_NUM)", 2 },
1108         { "ORDER", 2 },
1109         { "NUMA_ID", 2 },
1110         { "MAX_LEN", 2 },
1111 };
1112
1113 static void hns3_dump_page_pool_info(struct hns3_enet_ring *ring,
1114                                      char **result, u32 index)
1115 {
1116         u32 j = 0;
1117
1118         sprintf(result[j++], "%u", index);
1119         sprintf(result[j++], "%u",
1120                 READ_ONCE(ring->page_pool->pages_state_hold_cnt));
1121         sprintf(result[j++], "%d",
1122                 atomic_read(&ring->page_pool->pages_state_release_cnt));
1123         sprintf(result[j++], "%u", ring->page_pool->p.pool_size);
1124         sprintf(result[j++], "%u", ring->page_pool->p.order);
1125         sprintf(result[j++], "%d", ring->page_pool->p.nid);
1126         sprintf(result[j++], "%uK", ring->page_pool->p.max_len / 1024);
1127 }
1128
1129 static int
1130 hns3_dbg_page_pool_info(struct hnae3_handle *h, char *buf, int len)
1131 {
1132         char data_str[ARRAY_SIZE(page_pool_info_items)][HNS3_DBG_DATA_STR_LEN];
1133         char *result[ARRAY_SIZE(page_pool_info_items)];
1134         struct hns3_nic_priv *priv = h->priv;
1135         char content[HNS3_DBG_INFO_LEN];
1136         struct hns3_enet_ring *ring;
1137         int pos = 0;
1138         u32 i;
1139
1140         if (!priv->ring) {
1141                 dev_err(&h->pdev->dev, "priv->ring is NULL\n");
1142                 return -EFAULT;
1143         }
1144
1145         if (!priv->ring[h->kinfo.num_tqps].page_pool) {
1146                 dev_err(&h->pdev->dev, "page pool is not initialized\n");
1147                 return -EFAULT;
1148         }
1149
1150         for (i = 0; i < ARRAY_SIZE(page_pool_info_items); i++)
1151                 result[i] = &data_str[i][0];
1152
1153         hns3_dbg_fill_content(content, sizeof(content), page_pool_info_items,
1154                               NULL, ARRAY_SIZE(page_pool_info_items));
1155         pos += scnprintf(buf + pos, len - pos, "%s", content);
1156         for (i = 0; i < h->kinfo.num_tqps; i++) {
1157                 if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) ||
1158                     test_bit(HNS3_NIC_STATE_RESETTING, &priv->state))
1159                         return -EPERM;
1160                 ring = &priv->ring[(u32)(i + h->kinfo.num_tqps)];
1161                 hns3_dump_page_pool_info(ring, result, i);
1162                 hns3_dbg_fill_content(content, sizeof(content),
1163                                       page_pool_info_items,
1164                                       (const char **)result,
1165                                       ARRAY_SIZE(page_pool_info_items));
1166                 pos += scnprintf(buf + pos, len - pos, "%s", content);
1167         }
1168
1169         return 0;
1170 }
1171
1172 static int hns3_dbg_get_cmd_index(struct hns3_dbg_data *dbg_data, u32 *index)
1173 {
1174         u32 i;
1175
1176         for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) {
1177                 if (hns3_dbg_cmd[i].cmd == dbg_data->cmd) {
1178                         *index = i;
1179                         return 0;
1180                 }
1181         }
1182
1183         dev_err(&dbg_data->handle->pdev->dev, "unknown command(%d)\n",
1184                 dbg_data->cmd);
1185         return -EINVAL;
1186 }
1187
1188 static const struct hns3_dbg_func hns3_dbg_cmd_func[] = {
1189         {
1190                 .cmd = HNAE3_DBG_CMD_QUEUE_MAP,
1191                 .dbg_dump = hns3_dbg_queue_map,
1192         },
1193         {
1194                 .cmd = HNAE3_DBG_CMD_DEV_INFO,
1195                 .dbg_dump = hns3_dbg_dev_info,
1196         },
1197         {
1198                 .cmd = HNAE3_DBG_CMD_TX_BD,
1199                 .dbg_dump_bd = hns3_dbg_tx_bd_info,
1200         },
1201         {
1202                 .cmd = HNAE3_DBG_CMD_RX_BD,
1203                 .dbg_dump_bd = hns3_dbg_rx_bd_info,
1204         },
1205         {
1206                 .cmd = HNAE3_DBG_CMD_RX_QUEUE_INFO,
1207                 .dbg_dump = hns3_dbg_rx_queue_info,
1208         },
1209         {
1210                 .cmd = HNAE3_DBG_CMD_TX_QUEUE_INFO,
1211                 .dbg_dump = hns3_dbg_tx_queue_info,
1212         },
1213         {
1214                 .cmd = HNAE3_DBG_CMD_PAGE_POOL_INFO,
1215                 .dbg_dump = hns3_dbg_page_pool_info,
1216         },
1217         {
1218                 .cmd = HNAE3_DBG_CMD_COAL_INFO,
1219                 .dbg_dump = hns3_dbg_coal_info,
1220         },
1221 };
1222
1223 static int hns3_dbg_read_cmd(struct hns3_dbg_data *dbg_data,
1224                              enum hnae3_dbg_cmd cmd, char *buf, int len)
1225 {
1226         const struct hnae3_ae_ops *ops = dbg_data->handle->ae_algo->ops;
1227         const struct hns3_dbg_func *cmd_func;
1228         u32 i;
1229
1230         for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd_func); i++) {
1231                 if (cmd == hns3_dbg_cmd_func[i].cmd) {
1232                         cmd_func = &hns3_dbg_cmd_func[i];
1233                         if (cmd_func->dbg_dump)
1234                                 return cmd_func->dbg_dump(dbg_data->handle, buf,
1235                                                           len);
1236                         else
1237                                 return cmd_func->dbg_dump_bd(dbg_data, buf,
1238                                                              len);
1239                 }
1240         }
1241
1242         if (!ops->dbg_read_cmd)
1243                 return -EOPNOTSUPP;
1244
1245         return ops->dbg_read_cmd(dbg_data->handle, cmd, buf, len);
1246 }
1247
1248 static ssize_t hns3_dbg_read(struct file *filp, char __user *buffer,
1249                              size_t count, loff_t *ppos)
1250 {
1251         struct hns3_dbg_data *dbg_data = filp->private_data;
1252         struct hnae3_handle *handle = dbg_data->handle;
1253         struct hns3_nic_priv *priv = handle->priv;
1254         ssize_t size = 0;
1255         char **save_buf;
1256         char *read_buf;
1257         u32 index;
1258         int ret;
1259
1260         ret = hns3_dbg_get_cmd_index(dbg_data, &index);
1261         if (ret)
1262                 return ret;
1263
1264         mutex_lock(&handle->dbgfs_lock);
1265         save_buf = &handle->dbgfs_buf[index];
1266
1267         if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) ||
1268             test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) {
1269                 ret = -EBUSY;
1270                 goto out;
1271         }
1272
1273         if (*save_buf) {
1274                 read_buf = *save_buf;
1275         } else {
1276                 read_buf = kvzalloc(hns3_dbg_cmd[index].buf_len, GFP_KERNEL);
1277                 if (!read_buf) {
1278                         ret = -ENOMEM;
1279                         goto out;
1280                 }
1281
1282                 /* save the buffer addr until the last read operation */
1283                 *save_buf = read_buf;
1284
1285                 /* get data ready for the first time to read */
1286                 ret = hns3_dbg_read_cmd(dbg_data, hns3_dbg_cmd[index].cmd,
1287                                         read_buf, hns3_dbg_cmd[index].buf_len);
1288                 if (ret)
1289                         goto out;
1290         }
1291
1292         size = simple_read_from_buffer(buffer, count, ppos, read_buf,
1293                                        strlen(read_buf));
1294         if (size > 0) {
1295                 mutex_unlock(&handle->dbgfs_lock);
1296                 return size;
1297         }
1298
1299 out:
1300         /* free the buffer for the last read operation */
1301         if (*save_buf) {
1302                 kvfree(*save_buf);
1303                 *save_buf = NULL;
1304         }
1305
1306         mutex_unlock(&handle->dbgfs_lock);
1307         return ret;
1308 }
1309
1310 static const struct file_operations hns3_dbg_fops = {
1311         .owner = THIS_MODULE,
1312         .open  = simple_open,
1313         .read  = hns3_dbg_read,
1314 };
1315
1316 static int hns3_dbg_bd_file_init(struct hnae3_handle *handle, u32 cmd)
1317 {
1318         struct dentry *entry_dir;
1319         struct hns3_dbg_data *data;
1320         u16 max_queue_num;
1321         unsigned int i;
1322
1323         entry_dir = hns3_dbg_dentry[hns3_dbg_cmd[cmd].dentry].dentry;
1324         max_queue_num = hns3_get_max_available_channels(handle);
1325         data = devm_kzalloc(&handle->pdev->dev, max_queue_num * sizeof(*data),
1326                             GFP_KERNEL);
1327         if (!data)
1328                 return -ENOMEM;
1329
1330         for (i = 0; i < max_queue_num; i++) {
1331                 char name[HNS3_DBG_FILE_NAME_LEN];
1332
1333                 data[i].handle = handle;
1334                 data[i].cmd = hns3_dbg_cmd[cmd].cmd;
1335                 data[i].qid = i;
1336                 sprintf(name, "%s%u", hns3_dbg_cmd[cmd].name, i);
1337                 debugfs_create_file(name, 0400, entry_dir, &data[i],
1338                                     &hns3_dbg_fops);
1339         }
1340
1341         return 0;
1342 }
1343
1344 static int
1345 hns3_dbg_common_file_init(struct hnae3_handle *handle, u32 cmd)
1346 {
1347         struct hns3_dbg_data *data;
1348         struct dentry *entry_dir;
1349
1350         data = devm_kzalloc(&handle->pdev->dev, sizeof(*data), GFP_KERNEL);
1351         if (!data)
1352                 return -ENOMEM;
1353
1354         data->handle = handle;
1355         data->cmd = hns3_dbg_cmd[cmd].cmd;
1356         entry_dir = hns3_dbg_dentry[hns3_dbg_cmd[cmd].dentry].dentry;
1357         debugfs_create_file(hns3_dbg_cmd[cmd].name, 0400, entry_dir,
1358                             data, &hns3_dbg_fops);
1359
1360         return 0;
1361 }
1362
1363 int hns3_dbg_init(struct hnae3_handle *handle)
1364 {
1365         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
1366         const char *name = pci_name(handle->pdev);
1367         int ret;
1368         u32 i;
1369
1370         handle->dbgfs_buf = devm_kcalloc(&handle->pdev->dev,
1371                                          ARRAY_SIZE(hns3_dbg_cmd),
1372                                          sizeof(*handle->dbgfs_buf),
1373                                          GFP_KERNEL);
1374         if (!handle->dbgfs_buf)
1375                 return -ENOMEM;
1376
1377         hns3_dbg_dentry[HNS3_DBG_DENTRY_COMMON].dentry =
1378                                 debugfs_create_dir(name, hns3_dbgfs_root);
1379         handle->hnae3_dbgfs = hns3_dbg_dentry[HNS3_DBG_DENTRY_COMMON].dentry;
1380
1381         for (i = 0; i < HNS3_DBG_DENTRY_COMMON; i++)
1382                 hns3_dbg_dentry[i].dentry =
1383                         debugfs_create_dir(hns3_dbg_dentry[i].name,
1384                                            handle->hnae3_dbgfs);
1385
1386         mutex_init(&handle->dbgfs_lock);
1387
1388         for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++) {
1389                 if ((hns3_dbg_cmd[i].cmd == HNAE3_DBG_CMD_TM_NODES &&
1390                      ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2) ||
1391                     (hns3_dbg_cmd[i].cmd == HNAE3_DBG_CMD_PTP_INFO &&
1392                      !test_bit(HNAE3_DEV_SUPPORT_PTP_B, ae_dev->caps)))
1393                         continue;
1394
1395                 if (!hns3_dbg_cmd[i].init) {
1396                         dev_err(&handle->pdev->dev,
1397                                 "cmd %s lack of init func\n",
1398                                 hns3_dbg_cmd[i].name);
1399                         ret = -EINVAL;
1400                         goto out;
1401                 }
1402
1403                 ret = hns3_dbg_cmd[i].init(handle, i);
1404                 if (ret) {
1405                         dev_err(&handle->pdev->dev, "failed to init cmd %s\n",
1406                                 hns3_dbg_cmd[i].name);
1407                         goto out;
1408                 }
1409         }
1410
1411         return 0;
1412
1413 out:
1414         mutex_destroy(&handle->dbgfs_lock);
1415         debugfs_remove_recursive(handle->hnae3_dbgfs);
1416         handle->hnae3_dbgfs = NULL;
1417         return ret;
1418 }
1419
1420 void hns3_dbg_uninit(struct hnae3_handle *handle)
1421 {
1422         u32 i;
1423
1424         for (i = 0; i < ARRAY_SIZE(hns3_dbg_cmd); i++)
1425                 if (handle->dbgfs_buf[i]) {
1426                         kvfree(handle->dbgfs_buf[i]);
1427                         handle->dbgfs_buf[i] = NULL;
1428                 }
1429
1430         mutex_destroy(&handle->dbgfs_lock);
1431         debugfs_remove_recursive(handle->hnae3_dbgfs);
1432         handle->hnae3_dbgfs = NULL;
1433 }
1434
1435 void hns3_dbg_register_debugfs(const char *debugfs_dir_name)
1436 {
1437         hns3_dbgfs_root = debugfs_create_dir(debugfs_dir_name, NULL);
1438 }
1439
1440 void hns3_dbg_unregister_debugfs(void)
1441 {
1442         debugfs_remove_recursive(hns3_dbgfs_root);
1443         hns3_dbgfs_root = NULL;
1444 }