drivers/net/ethernet/intel/i40e/i40e_nvm.c

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Driver
   4  * Copyright(c) 2013 - 2014 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #include "i40e_prototype.h"
  28
  29 /**
  30  * i40e_init_nvm_ops - Initialize NVM function pointers
  31  * @hw: pointer to the HW structure
  32  *
  33  * Setup the function pointers and the NVM info structure. Should be called
  34  * once per NVM initialization, e.g. inside the i40e_init_shared_code().
  35  * Please notice that the NVM term is used here (& in all methods covered
  36  * in this file) as an equivalent of the FLASH part mapped into the SR.
  37  * We are accessing FLASH always thru the Shadow RAM.
  38  **/
  39 i40e_status i40e_init_nvm(struct i40e_hw *hw)
  40 {
  41         struct i40e_nvm_info *nvm = &hw->nvm;
  42         i40e_status ret_code = 0;
  43         u32 fla, gens;
  44         u8 sr_size;
  45
  46         /* The SR size is stored regardless of the nvm programming mode
  47          * as the blank mode may be used in the factory line.
  48          */
  49         gens = rd32(hw, I40E_GLNVM_GENS);
  50         sr_size = ((gens & I40E_GLNVM_GENS_SR_SIZE_MASK) >>
  51                            I40E_GLNVM_GENS_SR_SIZE_SHIFT);
  52         /* Switching to words (sr_size contains power of 2KB) */
  53         nvm->sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB;
  54
  55         /* Check if we are in the normal or blank NVM programming mode */
  56         fla = rd32(hw, I40E_GLNVM_FLA);
  57         if (fla & I40E_GLNVM_FLA_LOCKED_MASK) { /* Normal programming mode */
  58                 /* Max NVM timeout */
  59                 nvm->timeout = I40E_MAX_NVM_TIMEOUT;
  60                 nvm->blank_nvm_mode = false;
  61         } else { /* Blank programming mode */
  62                 nvm->blank_nvm_mode = true;
  63                 ret_code = I40E_ERR_NVM_BLANK_MODE;
  64                 i40e_debug(hw, I40E_DEBUG_NVM, "NVM init error: unsupported blank mode.\n");
  65         }
  66
  67         return ret_code;
  68 }
  69
  70 /**
  71  * i40e_acquire_nvm - Generic request for acquiring the NVM ownership
  72  * @hw: pointer to the HW structure
  73  * @access: NVM access type (read or write)
  74  *
  75  * This function will request NVM ownership for reading
  76  * via the proper Admin Command.
  77  **/
  78 i40e_status i40e_acquire_nvm(struct i40e_hw *hw,
  79                                        enum i40e_aq_resource_access_type access)
  80 {
  81         i40e_status ret_code = 0;
  82         u64 gtime, timeout;
  83         u64 time_left = 0;
  84
  85         if (hw->nvm.blank_nvm_mode)
  86                 goto i40e_i40e_acquire_nvm_exit;
  87
  88         ret_code = i40e_aq_request_resource(hw, I40E_NVM_RESOURCE_ID, access,
  89                                             0, &time_left, NULL);
  90         /* Reading the Global Device Timer */
  91         gtime = rd32(hw, I40E_GLVFGEN_TIMER);
  92
  93         /* Store the timeout */
  94         hw->nvm.hw_semaphore_timeout = I40E_MS_TO_GTIME(time_left) + gtime;
  95
  96         if (ret_code)
  97                 i40e_debug(hw, I40E_DEBUG_NVM,
  98                            "NVM acquire type %d failed time_left=%llu ret=%d aq_err=%d\n",
  99                            access, time_left, ret_code, hw->aq.asq_last_status);
 100
 101         if (ret_code && time_left) {
 102                 /* Poll until the current NVM owner timeouts */
 103                 timeout = I40E_MS_TO_GTIME(I40E_MAX_NVM_TIMEOUT) + gtime;
 104                 while ((gtime < timeout) && time_left) {
 105                         usleep_range(10000, 20000);
 106                         gtime = rd32(hw, I40E_GLVFGEN_TIMER);
 107                         ret_code = i40e_aq_request_resource(hw,
 108                                                         I40E_NVM_RESOURCE_ID,
 109                                                         access, 0, &time_left,
 110                                                         NULL);
 111                         if (!ret_code) {
 112                                 hw->nvm.hw_semaphore_timeout =
 113                                             I40E_MS_TO_GTIME(time_left) + gtime;
 114                                 break;
 115                         }
 116                 }
 117                 if (ret_code) {
 118                         hw->nvm.hw_semaphore_timeout = 0;
 119                         i40e_debug(hw, I40E_DEBUG_NVM,
 120                                    "NVM acquire timed out, wait %llu ms before trying again. status=%d aq_err=%d\n",
 121                                    time_left, ret_code, hw->aq.asq_last_status);
 122                 }
 123         }
 124
 125 i40e_i40e_acquire_nvm_exit:
 126         return ret_code;
 127 }
 128
 129 /**
 130  * i40e_release_nvm - Generic request for releasing the NVM ownership
 131  * @hw: pointer to the HW structure
 132  *
 133  * This function will release NVM resource via the proper Admin Command.
 134  **/
 135 void i40e_release_nvm(struct i40e_hw *hw)
 136 {
 137         i40e_status ret_code = I40E_SUCCESS;
 138         u32 total_delay = 0;
 139
 140         if (hw->nvm.blank_nvm_mode)
 141                 return;
 142
 143         ret_code = i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);
 144
 145         /* there are some rare cases when trying to release the resource
 146          * results in an admin Q timeout, so handle them correctly
 147          */
 148         while ((ret_code == I40E_ERR_ADMIN_QUEUE_TIMEOUT) &&
 149                (total_delay < hw->aq.asq_cmd_timeout)) {
 150                 usleep_range(1000, 2000);
 151                 ret_code = i40e_aq_release_resource(hw,
 152                                                     I40E_NVM_RESOURCE_ID,
 153                                                     0, NULL);
 154                 total_delay++;
 155         }
 156 }
 157
 158 /**
 159  * i40e_poll_sr_srctl_done_bit - Polls the GLNVM_SRCTL done bit
 160  * @hw: pointer to the HW structure
 161  *
 162  * Polls the SRCTL Shadow RAM register done bit.
 163  **/
 164 static i40e_status i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw)
 165 {
 166         i40e_status ret_code = I40E_ERR_TIMEOUT;
 167         u32 srctl, wait_cnt;
 168
 169         /* Poll the I40E_GLNVM_SRCTL until the done bit is set */
 170         for (wait_cnt = 0; wait_cnt < I40E_SRRD_SRCTL_ATTEMPTS; wait_cnt++) {
 171                 srctl = rd32(hw, I40E_GLNVM_SRCTL);
 172                 if (srctl & I40E_GLNVM_SRCTL_DONE_MASK) {
 173                         ret_code = 0;
 174                         break;
 175                 }
 176                 udelay(5);
 177         }
 178         if (ret_code == I40E_ERR_TIMEOUT)
 179                 i40e_debug(hw, I40E_DEBUG_NVM, "Done bit in GLNVM_SRCTL not set");
 180         return ret_code;
 181 }
 182
 183 /**
 184  * i40e_read_nvm_word_srctl - Reads Shadow RAM via SRCTL register
 185  * @hw: pointer to the HW structure
 186  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
 187  * @data: word read from the Shadow RAM
 188  *
 189  * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
 190  **/
 191 static i40e_status i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,
 192                                             u16 *data)
 193 {
 194         i40e_status ret_code = I40E_ERR_TIMEOUT;
 195         u32 sr_reg;
 196
 197         if (offset >= hw->nvm.sr_size) {
 198                 i40e_debug(hw, I40E_DEBUG_NVM,
 199                            "NVM read error: offset %d beyond Shadow RAM limit %d\n",
 200                            offset, hw->nvm.sr_size);
 201                 ret_code = I40E_ERR_PARAM;
 202                 goto read_nvm_exit;
 203         }
 204
 205         /* Poll the done bit first */
 206         ret_code = i40e_poll_sr_srctl_done_bit(hw);
 207         if (!ret_code) {
 208                 /* Write the address and start reading */
 209                 sr_reg = ((u32)offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) |
 210                          BIT(I40E_GLNVM_SRCTL_START_SHIFT);
 211                 wr32(hw, I40E_GLNVM_SRCTL, sr_reg);
 212
 213                 /* Poll I40E_GLNVM_SRCTL until the done bit is set */
 214                 ret_code = i40e_poll_sr_srctl_done_bit(hw);
 215                 if (!ret_code) {
 216                         sr_reg = rd32(hw, I40E_GLNVM_SRDATA);
 217                         *data = (u16)((sr_reg &
 218                                        I40E_GLNVM_SRDATA_RDDATA_MASK)
 219                                     >> I40E_GLNVM_SRDATA_RDDATA_SHIFT);
 220                 }
 221         }
 222         if (ret_code)
 223                 i40e_debug(hw, I40E_DEBUG_NVM,
 224                            "NVM read error: Couldn't access Shadow RAM address: 0x%x\n",
 225                            offset);
 226
 227 read_nvm_exit:
 228         return ret_code;
 229 }
 230
 231 /**
 232  * i40e_read_nvm_aq - Read Shadow RAM.
 233  * @hw: pointer to the HW structure.
 234  * @module_pointer: module pointer location in words from the NVM beginning
 235  * @offset: offset in words from module start
 236  * @words: number of words to write
 237  * @data: buffer with words to write to the Shadow RAM
 238  * @last_command: tells the AdminQ that this is the last command
 239  *
 240  * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
 241  **/
 242 static i40e_status i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
 243                                     u32 offset, u16 words, void *data,
 244                                     bool last_command)
 245 {
 246         i40e_status ret_code = I40E_ERR_NVM;
 247         struct i40e_asq_cmd_details cmd_details;
 248
 249         memset(&cmd_details, 0, sizeof(cmd_details));
 250         cmd_details.wb_desc = &hw->nvm_wb_desc;
 251
 252         /* Here we are checking the SR limit only for the flat memory model.
 253          * We cannot do it for the module-based model, as we did not acquire
 254          * the NVM resource yet (we cannot get the module pointer value).
 255          * Firmware will check the module-based model.
 256          */
 257         if ((offset + words) > hw->nvm.sr_size)
 258                 i40e_debug(hw, I40E_DEBUG_NVM,
 259                            "NVM write error: offset %d beyond Shadow RAM limit %d\n",
 260                            (offset + words), hw->nvm.sr_size);
 261         else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
 262                 /* We can write only up to 4KB (one sector), in one AQ write */
 263                 i40e_debug(hw, I40E_DEBUG_NVM,
 264                            "NVM write fail error: tried to write %d words, limit is %d.\n",
 265                            words, I40E_SR_SECTOR_SIZE_IN_WORDS);
 266         else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
 267                  != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
 268                 /* A single write cannot spread over two sectors */
 269                 i40e_debug(hw, I40E_DEBUG_NVM,
 270                            "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n",
 271                            offset, words);
 272         else
 273                 ret_code = i40e_aq_read_nvm(hw, module_pointer,
 274                                             2 * offset,  /*bytes*/
 275                                             2 * words,   /*bytes*/
 276                                             data, last_command, &cmd_details);
 277
 278         return ret_code;
 279 }
 280
 281 /**
 282  * i40e_read_nvm_word_aq - Reads Shadow RAM via AQ
 283  * @hw: pointer to the HW structure
 284  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
 285  * @data: word read from the Shadow RAM
 286  *
 287  * Reads one 16 bit word from the Shadow RAM using the AdminQ
 288  **/
 289 static i40e_status i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,
 290                                          u16 *data)
 291 {
 292         i40e_status ret_code = I40E_ERR_TIMEOUT;
 293
 294         ret_code = i40e_read_nvm_aq(hw, 0x0, offset, 1, data, true);
 295         *data = le16_to_cpu(*(__le16 *)data);
 296
 297         return ret_code;
 298 }
 299
 300 /**
 301  * __i40e_read_nvm_word - Reads nvm word, assumes called does the locking
 302  * @hw: pointer to the HW structure
 303  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
 304  * @data: word read from the Shadow RAM
 305  *
 306  * Reads one 16 bit word from the Shadow RAM.
 307  *
 308  * Do not use this function except in cases where the nvm lock is already
 309  * taken via i40e_acquire_nvm().
 310  **/
 311 static i40e_status __i40e_read_nvm_word(struct i40e_hw *hw,
 312                                         u16 offset, u16 *data)
 313 {
 314         if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE)
 315                 return i40e_read_nvm_word_aq(hw, offset, data);
 316
 317         return i40e_read_nvm_word_srctl(hw, offset, data);
 318 }
 319
 320 /**
 321  * i40e_read_nvm_word - Reads nvm word and acquire lock if necessary
 322  * @hw: pointer to the HW structure
 323  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
 324  * @data: word read from the Shadow RAM
 325  *
 326  * Reads one 16 bit word from the Shadow RAM.
 327  **/
 328 i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
 329                                u16 *data)
 330 {
 331         i40e_status ret_code;
 332
 333         ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
 334         if (ret_code)
 335                 return ret_code;
 336
 337         ret_code = __i40e_read_nvm_word(hw, offset, data);
 338
 339         i40e_release_nvm(hw);
 340
 341         return ret_code;
 342 }
 343
 344 /**
 345  * i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register
 346  * @hw: pointer to the HW structure
 347  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
 348  * @words: (in) number of words to read; (out) number of words actually read
 349  * @data: words read from the Shadow RAM
 350  *
 351  * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
 352  * method. The buffer read is preceded by the NVM ownership take
 353  * and followed by the release.
 354  **/
 355 static i40e_status i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,
 356                                               u16 *words, u16 *data)
 357 {
 358         i40e_status ret_code = 0;
 359         u16 index, word;
 360
 361         /* Loop thru the selected region */
 362         for (word = 0; word < *words; word++) {
 363                 index = offset + word;
 364                 ret_code = i40e_read_nvm_word_srctl(hw, index, &data[word]);
 365                 if (ret_code)
 366                         break;
 367         }
 368
 369         /* Update the number of words read from the Shadow RAM */
 370         *words = word;
 371
 372         return ret_code;
 373 }
 374
 375 /**
 376  * i40e_read_nvm_buffer_aq - Reads Shadow RAM buffer via AQ
 377  * @hw: pointer to the HW structure
 378  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
 379  * @words: (in) number of words to read; (out) number of words actually read
 380  * @data: words read from the Shadow RAM
 381  *
 382  * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_aq()
 383  * method. The buffer read is preceded by the NVM ownership take
 384  * and followed by the release.
 385  **/
 386 static i40e_status i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset,
 387                                            u16 *words, u16 *data)
 388 {
 389         i40e_status ret_code;
 390         u16 read_size = *words;
 391         bool last_cmd = false;
 392         u16 words_read = 0;
 393         u16 i = 0;
 394
 395         do {
 396                 /* Calculate number of bytes we should read in this step.
 397                  * FVL AQ do not allow to read more than one page at a time or
 398                  * to cross page boundaries.
 399                  */
 400                 if (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)
 401                         read_size = min(*words,
 402                                         (u16)(I40E_SR_SECTOR_SIZE_IN_WORDS -
 403                                       (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)));
 404                 else
 405                         read_size = min((*words - words_read),
 406                                         I40E_SR_SECTOR_SIZE_IN_WORDS);
 407
 408                 /* Check if this is last command, if so set proper flag */
 409                 if ((words_read + read_size) >= *words)
 410                         last_cmd = true;
 411
 412                 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, read_size,
 413                                             data + words_read, last_cmd);
 414                 if (ret_code)
 415                         goto read_nvm_buffer_aq_exit;
 416
 417                 /* Increment counter for words already read and move offset to
 418                  * new read location
 419                  */
 420                 words_read += read_size;
 421                 offset += read_size;
 422         } while (words_read < *words);
 423
 424         for (i = 0; i < *words; i++)
 425                 data[i] = le16_to_cpu(((__le16 *)data)[i]);
 426
 427 read_nvm_buffer_aq_exit:
 428         *words = words_read;
 429         return ret_code;
 430 }
 431
 432 /**
 433  * __i40e_read_nvm_buffer - Reads nvm buffer, caller must acquire lock
 434  * @hw: pointer to the HW structure
 435  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
 436  * @words: (in) number of words to read; (out) number of words actually read
 437  * @data: words read from the Shadow RAM
 438  *
 439  * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
 440  * method.
 441  **/
 442 static i40e_status __i40e_read_nvm_buffer(struct i40e_hw *hw,
 443                                           u16 offset, u16 *words,
 444                                           u16 *data)
 445 {
 446         if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE)
 447                 return i40e_read_nvm_buffer_aq(hw, offset, words, data);
 448
 449         return i40e_read_nvm_buffer_srctl(hw, offset, words, data);
 450 }
 451
 452 /**
 453  * i40e_write_nvm_aq - Writes Shadow RAM.
 454  * @hw: pointer to the HW structure.
 455  * @module_pointer: module pointer location in words from the NVM beginning
 456  * @offset: offset in words from module start
 457  * @words: number of words to write
 458  * @data: buffer with words to write to the Shadow RAM
 459  * @last_command: tells the AdminQ that this is the last command
 460  *
 461  * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
 462  **/
 463 static i40e_status i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
 464                                      u32 offset, u16 words, void *data,
 465                                      bool last_command)
 466 {
 467         i40e_status ret_code = I40E_ERR_NVM;
 468         struct i40e_asq_cmd_details cmd_details;
 469
 470         memset(&cmd_details, 0, sizeof(cmd_details));
 471         cmd_details.wb_desc = &hw->nvm_wb_desc;
 472
 473         /* Here we are checking the SR limit only for the flat memory model.
 474          * We cannot do it for the module-based model, as we did not acquire
 475          * the NVM resource yet (we cannot get the module pointer value).
 476          * Firmware will check the module-based model.
 477          */
 478         if ((offset + words) > hw->nvm.sr_size)
 479                 i40e_debug(hw, I40E_DEBUG_NVM,
 480                            "NVM write error: offset %d beyond Shadow RAM limit %d\n",
 481                            (offset + words), hw->nvm.sr_size);
 482         else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
 483                 /* We can write only up to 4KB (one sector), in one AQ write */
 484                 i40e_debug(hw, I40E_DEBUG_NVM,
 485                            "NVM write fail error: tried to write %d words, limit is %d.\n",
 486                            words, I40E_SR_SECTOR_SIZE_IN_WORDS);
 487         else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
 488                  != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
 489                 /* A single write cannot spread over two sectors */
 490                 i40e_debug(hw, I40E_DEBUG_NVM,
 491                            "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n",
 492                            offset, words);
 493         else
 494                 ret_code = i40e_aq_update_nvm(hw, module_pointer,
 495                                               2 * offset,  /*bytes*/
 496                                               2 * words,   /*bytes*/
 497                                               data, last_command, &cmd_details);
 498
 499         return ret_code;
 500 }
 501
 502 /**
 503  * i40e_calc_nvm_checksum - Calculates and returns the checksum
 504  * @hw: pointer to hardware structure
 505  * @checksum: pointer to the checksum
 506  *
 507  * This function calculates SW Checksum that covers the whole 64kB shadow RAM
 508  * except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD
 509  * is customer specific and unknown. Therefore, this function skips all maximum
 510  * possible size of VPD (1kB).
 511  **/
 512 static i40e_status i40e_calc_nvm_checksum(struct i40e_hw *hw,
 513                                                     u16 *checksum)
 514 {
 515         i40e_status ret_code;
 516         struct i40e_virt_mem vmem;
 517         u16 pcie_alt_module = 0;
 518         u16 checksum_local = 0;
 519         u16 vpd_module = 0;
 520         u16 *data;
 521         u16 i = 0;
 522
 523         ret_code = i40e_allocate_virt_mem(hw, &vmem,
 524                                     I40E_SR_SECTOR_SIZE_IN_WORDS * sizeof(u16));
 525         if (ret_code)
 526                 goto i40e_calc_nvm_checksum_exit;
 527         data = (u16 *)vmem.va;
 528
 529         /* read pointer to VPD area */
 530         ret_code = __i40e_read_nvm_word(hw, I40E_SR_VPD_PTR, &vpd_module);
 531         if (ret_code) {
 532                 ret_code = I40E_ERR_NVM_CHECKSUM;
 533                 goto i40e_calc_nvm_checksum_exit;
 534         }
 535
 536         /* read pointer to PCIe Alt Auto-load module */
 537         ret_code = __i40e_read_nvm_word(hw, I40E_SR_PCIE_ALT_AUTO_LOAD_PTR,
 538                                         &pcie_alt_module);
 539         if (ret_code) {
 540                 ret_code = I40E_ERR_NVM_CHECKSUM;
 541                 goto i40e_calc_nvm_checksum_exit;
 542         }
 543
 544         /* Calculate SW checksum that covers the whole 64kB shadow RAM
 545          * except the VPD and PCIe ALT Auto-load modules
 546          */
 547         for (i = 0; i < hw->nvm.sr_size; i++) {
 548                 /* Read SR page */
 549                 if ((i % I40E_SR_SECTOR_SIZE_IN_WORDS) == 0) {
 550                         u16 words = I40E_SR_SECTOR_SIZE_IN_WORDS;
 551
 552                         ret_code = __i40e_read_nvm_buffer(hw, i, &words, data);
 553                         if (ret_code) {
 554                                 ret_code = I40E_ERR_NVM_CHECKSUM;
 555                                 goto i40e_calc_nvm_checksum_exit;
 556                         }
 557                 }
 558
 559                 /* Skip Checksum word */
 560                 if (i == I40E_SR_SW_CHECKSUM_WORD)
 561                         continue;
 562                 /* Skip VPD module (convert byte size to word count) */
 563                 if ((i >= (u32)vpd_module) &&
 564                     (i < ((u32)vpd_module +
 565                      (I40E_SR_VPD_MODULE_MAX_SIZE / 2)))) {
 566                         continue;
 567                 }
 568                 /* Skip PCIe ALT module (convert byte size to word count) */
 569                 if ((i >= (u32)pcie_alt_module) &&
 570                     (i < ((u32)pcie_alt_module +
 571                      (I40E_SR_PCIE_ALT_MODULE_MAX_SIZE / 2)))) {
 572                         continue;
 573                 }
 574
 575                 checksum_local += data[i % I40E_SR_SECTOR_SIZE_IN_WORDS];
 576         }
 577
 578         *checksum = (u16)I40E_SR_SW_CHECKSUM_BASE - checksum_local;
 579
 580 i40e_calc_nvm_checksum_exit:
 581         i40e_free_virt_mem(hw, &vmem);
 582         return ret_code;
 583 }
 584
 585 /**
 586  * i40e_update_nvm_checksum - Updates the NVM checksum
 587  * @hw: pointer to hardware structure
 588  *
 589  * NVM ownership must be acquired before calling this function and released
 590  * on ARQ completion event reception by caller.
 591  * This function will commit SR to NVM.
 592  **/
 593 i40e_status i40e_update_nvm_checksum(struct i40e_hw *hw)
 594 {
 595         i40e_status ret_code;
 596         u16 checksum;
 597         __le16 le_sum;
 598
 599         ret_code = i40e_calc_nvm_checksum(hw, &checksum);
 600         if (!ret_code) {
 601                 le_sum = cpu_to_le16(checksum);
 602                 ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD,
 603                                              1, &le_sum, true);
 604         }
 605
 606         return ret_code;
 607 }
 608
 609 /**
 610  * i40e_validate_nvm_checksum - Validate EEPROM checksum
 611  * @hw: pointer to hardware structure
 612  * @checksum: calculated checksum
 613  *
 614  * Performs checksum calculation and validates the NVM SW checksum. If the
 615  * caller does not need checksum, the value can be NULL.
 616  **/
 617 i40e_status i40e_validate_nvm_checksum(struct i40e_hw *hw,
 618                                                  u16 *checksum)
 619 {
 620         i40e_status ret_code = 0;
 621         u16 checksum_sr = 0;
 622         u16 checksum_local = 0;
 623
 624         /* We must acquire the NVM lock in order to correctly synchronize the
 625          * NVM accesses across multiple PFs. Without doing so it is possible
 626          * for one of the PFs to read invalid data potentially indicating that
 627          * the checksum is invalid.
 628          */
 629         ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
 630         if (ret_code)
 631                 return ret_code;
 632         ret_code = i40e_calc_nvm_checksum(hw, &checksum_local);
 633         __i40e_read_nvm_word(hw, I40E_SR_SW_CHECKSUM_WORD, &checksum_sr);
 634         i40e_release_nvm(hw);
 635         if (ret_code)
 636                 return ret_code;
 637
 638         /* Verify read checksum from EEPROM is the same as
 639          * calculated checksum
 640          */
 641         if (checksum_local != checksum_sr)
 642                 ret_code = I40E_ERR_NVM_CHECKSUM;
 643
 644         /* If the user cares, return the calculated checksum */
 645         if (checksum)
 646                 *checksum = checksum_local;
 647
 648         return ret_code;
 649 }
 650
 651 static i40e_status i40e_nvmupd_state_init(struct i40e_hw *hw,
 652                                           struct i40e_nvm_access *cmd,
 653                                           u8 *bytes, int *perrno);
 654 static i40e_status i40e_nvmupd_state_reading(struct i40e_hw *hw,
 655                                              struct i40e_nvm_access *cmd,
 656                                              u8 *bytes, int *perrno);
 657 static i40e_status i40e_nvmupd_state_writing(struct i40e_hw *hw,
 658                                              struct i40e_nvm_access *cmd,
 659                                              u8 *bytes, int *errno);
 660 static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,
 661                                                 struct i40e_nvm_access *cmd,
 662                                                 int *perrno);
 663 static i40e_status i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
 664                                          struct i40e_nvm_access *cmd,
 665                                          int *perrno);
 666 static i40e_status i40e_nvmupd_nvm_write(struct i40e_hw *hw,
 667                                          struct i40e_nvm_access *cmd,
 668                                          u8 *bytes, int *perrno);
 669 static i40e_status i40e_nvmupd_nvm_read(struct i40e_hw *hw,
 670                                         struct i40e_nvm_access *cmd,
 671                                         u8 *bytes, int *perrno);
 672 static i40e_status i40e_nvmupd_exec_aq(struct i40e_hw *hw,
 673                                        struct i40e_nvm_access *cmd,
 674                                        u8 *bytes, int *perrno);
 675 static i40e_status i40e_nvmupd_get_aq_result(struct i40e_hw *hw,
 676                                              struct i40e_nvm_access *cmd,
 677                                              u8 *bytes, int *perrno);
 678 static inline u8 i40e_nvmupd_get_module(u32 val)
 679 {
 680         return (u8)(val & I40E_NVM_MOD_PNT_MASK);
 681 }
 682 static inline u8 i40e_nvmupd_get_transaction(u32 val)
 683 {
 684         return (u8)((val & I40E_NVM_TRANS_MASK) >> I40E_NVM_TRANS_SHIFT);
 685 }
 686
 687 static const char * const i40e_nvm_update_state_str[] = {
 688         "I40E_NVMUPD_INVALID",
 689         "I40E_NVMUPD_READ_CON",
 690         "I40E_NVMUPD_READ_SNT",
 691         "I40E_NVMUPD_READ_LCB",
 692         "I40E_NVMUPD_READ_SA",
 693         "I40E_NVMUPD_WRITE_ERA",
 694         "I40E_NVMUPD_WRITE_CON",
 695         "I40E_NVMUPD_WRITE_SNT",
 696         "I40E_NVMUPD_WRITE_LCB",
 697         "I40E_NVMUPD_WRITE_SA",
 698         "I40E_NVMUPD_CSUM_CON",
 699         "I40E_NVMUPD_CSUM_SA",
 700         "I40E_NVMUPD_CSUM_LCB",
 701         "I40E_NVMUPD_STATUS",
 702         "I40E_NVMUPD_EXEC_AQ",
 703         "I40E_NVMUPD_GET_AQ_RESULT",
 704 };
 705
 706 /**
 707  * i40e_nvmupd_command - Process an NVM update command
 708  * @hw: pointer to hardware structure
 709  * @cmd: pointer to nvm update command
 710  * @bytes: pointer to the data buffer
 711  * @perrno: pointer to return error code
 712  *
 713  * Dispatches command depending on what update state is current
 714  **/
 715 i40e_status i40e_nvmupd_command(struct i40e_hw *hw,
 716                                 struct i40e_nvm_access *cmd,
 717                                 u8 *bytes, int *perrno)
 718 {
 719         i40e_status status;
 720         enum i40e_nvmupd_cmd upd_cmd;
 721
 722         /* assume success */
 723         *perrno = 0;
 724
 725         /* early check for status command and debug msgs */
 726         upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
 727
 728         i40e_debug(hw, I40E_DEBUG_NVM, "%s state %d nvm_release_on_hold %d opc 0x%04x cmd 0x%08x config 0x%08x offset 0x%08x data_size 0x%08x\n",
 729                    i40e_nvm_update_state_str[upd_cmd],
 730                    hw->nvmupd_state,
 731                    hw->nvm_release_on_done, hw->nvm_wait_opcode,
 732                    cmd->command, cmd->config, cmd->offset, cmd->data_size);
 733
 734         if (upd_cmd == I40E_NVMUPD_INVALID) {
 735                 *perrno = -EFAULT;
 736                 i40e_debug(hw, I40E_DEBUG_NVM,
 737                            "i40e_nvmupd_validate_command returns %d errno %d\n",
 738                            upd_cmd, *perrno);
 739         }
 740
 741         /* a status request returns immediately rather than
 742          * going into the state machine
 743          */
 744         if (upd_cmd == I40E_NVMUPD_STATUS) {
 745                 if (!cmd->data_size) {
 746                         *perrno = -EFAULT;
 747                         return I40E_ERR_BUF_TOO_SHORT;
 748                 }
 749
 750                 bytes[0] = hw->nvmupd_state;
 751
 752                 if (cmd->data_size >= 4) {
 753                         bytes[1] = 0;
 754                         *((u16 *)&bytes[2]) = hw->nvm_wait_opcode;
 755                 }
 756
 757                 /* Clear error status on read */
 758                 if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR)
 759                         hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
 760
 761                 return 0;
 762         }
 763
 764         /* Clear status even it is not read and log */
 765         if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR) {
 766                 i40e_debug(hw, I40E_DEBUG_NVM,
 767                            "Clearing I40E_NVMUPD_STATE_ERROR state without reading\n");
 768                 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
 769         }
 770
 771         /* Acquire lock to prevent race condition where adminq_task
 772          * can execute after i40e_nvmupd_nvm_read/write but before state
 773          * variables (nvm_wait_opcode, nvm_release_on_done) are updated.
 774          *
 775          * During NVMUpdate, it is observed that lock could be held for
 776          * ~5ms for most commands. However lock is held for ~60ms for
 777          * NVMUPD_CSUM_LCB command.
 778          */
 779         mutex_lock(&hw->aq.arq_mutex);
 780         switch (hw->nvmupd_state) {
 781         case I40E_NVMUPD_STATE_INIT:
 782                 status = i40e_nvmupd_state_init(hw, cmd, bytes, perrno);
 783                 break;
 784
 785         case I40E_NVMUPD_STATE_READING:
 786                 status = i40e_nvmupd_state_reading(hw, cmd, bytes, perrno);
 787                 break;
 788
 789         case I40E_NVMUPD_STATE_WRITING:
 790                 status = i40e_nvmupd_state_writing(hw, cmd, bytes, perrno);
 791                 break;
 792
 793         case I40E_NVMUPD_STATE_INIT_WAIT:
 794         case I40E_NVMUPD_STATE_WRITE_WAIT:
 795                 /* if we need to stop waiting for an event, clear
 796                  * the wait info and return before doing anything else
 797                  */
 798                 if (cmd->offset == 0xffff) {
 799                         i40e_nvmupd_check_wait_event(hw, hw->nvm_wait_opcode);
 800                         status = 0;
 801                         goto exit;
 802                 }
 803
 804                 status = I40E_ERR_NOT_READY;
 805                 *perrno = -EBUSY;
 806                 break;
 807
 808         default:
 809                 /* invalid state, should never happen */
 810                 i40e_debug(hw, I40E_DEBUG_NVM,
 811                            "NVMUPD: no such state %d\n", hw->nvmupd_state);
 812                 status = I40E_NOT_SUPPORTED;
 813                 *perrno = -ESRCH;
 814                 break;
 815         }
 816 exit:
 817         mutex_unlock(&hw->aq.arq_mutex);
 818         return status;
 819 }
 820
 821 /**
 822  * i40e_nvmupd_state_init - Handle NVM update state Init
 823  * @hw: pointer to hardware structure
 824  * @cmd: pointer to nvm update command buffer
 825  * @bytes: pointer to the data buffer
 826  * @perrno: pointer to return error code
 827  *
 828  * Process legitimate commands of the Init state and conditionally set next
 829  * state. Reject all other commands.
 830  **/
 831 static i40e_status i40e_nvmupd_state_init(struct i40e_hw *hw,
 832                                           struct i40e_nvm_access *cmd,
 833                                           u8 *bytes, int *perrno)
 834 {
 835         i40e_status status = 0;
 836         enum i40e_nvmupd_cmd upd_cmd;
 837
 838         upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
 839
 840         switch (upd_cmd) {
 841         case I40E_NVMUPD_READ_SA:
 842                 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
 843                 if (status) {
 844                         *perrno = i40e_aq_rc_to_posix(status,
 845                                                      hw->aq.asq_last_status);
 846                 } else {
 847                         status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
 848                         i40e_release_nvm(hw);
 849                 }
 850                 break;
 851
 852         case I40E_NVMUPD_READ_SNT:
 853                 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
 854                 if (status) {
 855                         *perrno = i40e_aq_rc_to_posix(status,
 856                                                      hw->aq.asq_last_status);
 857                 } else {
 858                         status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
 859                         if (status)
 860                                 i40e_release_nvm(hw);
 861                         else
 862                                 hw->nvmupd_state = I40E_NVMUPD_STATE_READING;
 863                 }
 864                 break;
 865
 866         case I40E_NVMUPD_WRITE_ERA:
 867                 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
 868                 if (status) {
 869                         *perrno = i40e_aq_rc_to_posix(status,
 870                                                      hw->aq.asq_last_status);
 871                 } else {
 872                         status = i40e_nvmupd_nvm_erase(hw, cmd, perrno);
 873                         if (status) {
 874                                 i40e_release_nvm(hw);
 875                         } else {
 876                                 hw->nvm_release_on_done = true;
 877                                 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_erase;
 878                                 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
 879                         }
 880                 }
 881                 break;
 882
 883         case I40E_NVMUPD_WRITE_SA:
 884                 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
 885                 if (status) {
 886                         *perrno = i40e_aq_rc_to_posix(status,
 887                                                      hw->aq.asq_last_status);
 888                 } else {
 889                         status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
 890                         if (status) {
 891                                 i40e_release_nvm(hw);
 892                         } else {
 893                                 hw->nvm_release_on_done = true;
 894                                 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
 895                                 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
 896                         }
 897                 }
 898                 break;
 899
 900         case I40E_NVMUPD_WRITE_SNT:
 901                 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
 902                 if (status) {
 903                         *perrno = i40e_aq_rc_to_posix(status,
 904                                                      hw->aq.asq_last_status);
 905                 } else {
 906                         status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
 907                         if (status) {
 908                                 i40e_release_nvm(hw);
 909                         } else {
 910                                 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
 911                                 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
 912                         }
 913                 }
 914                 break;
 915
 916         case I40E_NVMUPD_CSUM_SA:
 917                 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
 918                 if (status) {
 919                         *perrno = i40e_aq_rc_to_posix(status,
 920                                                      hw->aq.asq_last_status);
 921                 } else {
 922                         status = i40e_update_nvm_checksum(hw);
 923                         if (status) {
 924                                 *perrno = hw->aq.asq_last_status ?
 925                                    i40e_aq_rc_to_posix(status,
 926                                                        hw->aq.asq_last_status) :
 927                                    -EIO;
 928                                 i40e_release_nvm(hw);
 929                         } else {
 930                                 hw->nvm_release_on_done = true;
 931                                 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
 932                                 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
 933                         }
 934                 }
 935                 break;
 936
 937         case I40E_NVMUPD_EXEC_AQ:
 938                 status = i40e_nvmupd_exec_aq(hw, cmd, bytes, perrno);
 939                 break;
 940
 941         case I40E_NVMUPD_GET_AQ_RESULT:
 942                 status = i40e_nvmupd_get_aq_result(hw, cmd, bytes, perrno);
 943                 break;
 944
 945         default:
 946                 i40e_debug(hw, I40E_DEBUG_NVM,
 947                            "NVMUPD: bad cmd %s in init state\n",
 948                            i40e_nvm_update_state_str[upd_cmd]);
 949                 status = I40E_ERR_NVM;
 950                 *perrno = -ESRCH;
 951                 break;
 952         }
 953         return status;
 954 }
 955
 956 /**
 957  * i40e_nvmupd_state_reading - Handle NVM update state Reading
 958  * @hw: pointer to hardware structure
 959  * @cmd: pointer to nvm update command buffer
 960  * @bytes: pointer to the data buffer
 961  * @perrno: pointer to return error code
 962  *
 963  * NVM ownership is already held.  Process legitimate commands and set any
 964  * change in state; reject all other commands.
 965  **/
 966 static i40e_status i40e_nvmupd_state_reading(struct i40e_hw *hw,
 967                                              struct i40e_nvm_access *cmd,
 968                                              u8 *bytes, int *perrno)
 969 {
 970         i40e_status status = 0;
 971         enum i40e_nvmupd_cmd upd_cmd;
 972
 973         upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
 974
 975         switch (upd_cmd) {
 976         case I40E_NVMUPD_READ_SA:
 977         case I40E_NVMUPD_READ_CON:
 978                 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
 979                 break;
 980
 981         case I40E_NVMUPD_READ_LCB:
 982                 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
 983                 i40e_release_nvm(hw);
 984                 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
 985                 break;
 986
 987         default:
 988                 i40e_debug(hw, I40E_DEBUG_NVM,
 989                            "NVMUPD: bad cmd %s in reading state.\n",
 990                            i40e_nvm_update_state_str[upd_cmd]);
 991                 status = I40E_NOT_SUPPORTED;
 992                 *perrno = -ESRCH;
 993                 break;
 994         }
 995         return status;
 996 }
 997
 998 /**
 999  * i40e_nvmupd_state_writing - Handle NVM update state Writing
1000  * @hw: pointer to hardware structure
1001  * @cmd: pointer to nvm update command buffer
1002  * @bytes: pointer to the data buffer
1003  * @perrno: pointer to return error code
1004  *
1005  * NVM ownership is already held.  Process legitimate commands and set any
1006  * change in state; reject all other commands
1007  **/
1008 static i40e_status i40e_nvmupd_state_writing(struct i40e_hw *hw,
1009                                              struct i40e_nvm_access *cmd,
1010                                              u8 *bytes, int *perrno)
1011 {
1012         i40e_status status = 0;
1013         enum i40e_nvmupd_cmd upd_cmd;
1014         bool retry_attempt = false;
1015
1016         upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
1017
1018 retry:
1019         switch (upd_cmd) {
1020         case I40E_NVMUPD_WRITE_CON:
1021                 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
1022                 if (!status) {
1023                         hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
1024                         hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
1025                 }
1026                 break;
1027
1028         case I40E_NVMUPD_WRITE_LCB:
1029                 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
1030                 if (status) {
1031                         *perrno = hw->aq.asq_last_status ?
1032                                    i40e_aq_rc_to_posix(status,
1033                                                        hw->aq.asq_last_status) :
1034                                    -EIO;
1035                         hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1036                 } else {
1037                         hw->nvm_release_on_done = true;
1038                         hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
1039                         hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1040                 }
1041                 break;
1042
1043         case I40E_NVMUPD_CSUM_CON:
1044                 /* Assumes the caller has acquired the nvm */
1045                 status = i40e_update_nvm_checksum(hw);
1046                 if (status) {
1047                         *perrno = hw->aq.asq_last_status ?
1048                                    i40e_aq_rc_to_posix(status,
1049                                                        hw->aq.asq_last_status) :
1050                                    -EIO;
1051                         hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1052                 } else {
1053                         hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
1054                         hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
1055                 }
1056                 break;
1057
1058         case I40E_NVMUPD_CSUM_LCB:
1059                 /* Assumes the caller has acquired the nvm */
1060                 status = i40e_update_nvm_checksum(hw);
1061                 if (status) {
1062                         *perrno = hw->aq.asq_last_status ?
1063                                    i40e_aq_rc_to_posix(status,
1064                                                        hw->aq.asq_last_status) :
1065                                    -EIO;
1066                         hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1067                 } else {
1068                         hw->nvm_release_on_done = true;
1069                         hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
1070                         hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1071                 }
1072                 break;
1073
1074         default:
1075                 i40e_debug(hw, I40E_DEBUG_NVM,
1076                            "NVMUPD: bad cmd %s in writing state.\n",
1077                            i40e_nvm_update_state_str[upd_cmd]);
1078                 status = I40E_NOT_SUPPORTED;
1079                 *perrno = -ESRCH;
1080                 break;
1081         }
1082
1083         /* In some circumstances, a multi-write transaction takes longer
1084          * than the default 3 minute timeout on the write semaphore.  If
1085          * the write failed with an EBUSY status, this is likely the problem,
1086          * so here we try to reacquire the semaphore then retry the write.
1087          * We only do one retry, then give up.
1088          */
1089         if (status && (hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) &&
1090             !retry_attempt) {
1091                 i40e_status old_status = status;
1092                 u32 old_asq_status = hw->aq.asq_last_status;
1093                 u32 gtime;
1094
1095                 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
1096                 if (gtime >= hw->nvm.hw_semaphore_timeout) {
1097                         i40e_debug(hw, I40E_DEBUG_ALL,
1098                                    "NVMUPD: write semaphore expired (%d >= %lld), retrying\n",
1099                                    gtime, hw->nvm.hw_semaphore_timeout);
1100                         i40e_release_nvm(hw);
1101                         status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
1102                         if (status) {
1103                                 i40e_debug(hw, I40E_DEBUG_ALL,
1104                                            "NVMUPD: write semaphore reacquire failed aq_err = %d\n",
1105                                            hw->aq.asq_last_status);
1106                                 status = old_status;
1107                                 hw->aq.asq_last_status = old_asq_status;
1108                         } else {
1109                                 retry_attempt = true;
1110                                 goto retry;
1111                         }
1112                 }
1113         }
1114
1115         return status;
1116 }
1117
1118 /**
1119  * i40e_nvmupd_check_wait_event - handle NVM update operation events
1120  * @hw: pointer to the hardware structure
1121  * @opcode: the event that just happened
1122  **/
1123 void i40e_nvmupd_check_wait_event(struct i40e_hw *hw, u16 opcode)
1124 {
1125         if (opcode == hw->nvm_wait_opcode) {
1126                 i40e_debug(hw, I40E_DEBUG_NVM,
1127                            "NVMUPD: clearing wait on opcode 0x%04x\n", opcode);
1128                 if (hw->nvm_release_on_done) {
1129                         i40e_release_nvm(hw);
1130                         hw->nvm_release_on_done = false;
1131                 }
1132                 hw->nvm_wait_opcode = 0;
1133
1134                 if (hw->aq.arq_last_status) {
1135                         hw->nvmupd_state = I40E_NVMUPD_STATE_ERROR;
1136                         return;
1137                 }
1138
1139                 switch (hw->nvmupd_state) {
1140                 case I40E_NVMUPD_STATE_INIT_WAIT:
1141                         hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1142                         break;
1143
1144                 case I40E_NVMUPD_STATE_WRITE_WAIT:
1145                         hw->nvmupd_state = I40E_NVMUPD_STATE_WRITING;
1146                         break;
1147
1148                 default:
1149                         break;
1150                 }
1151         }
1152 }
1153
1154 /**
1155  * i40e_nvmupd_validate_command - Validate given command
1156  * @hw: pointer to hardware structure
1157  * @cmd: pointer to nvm update command buffer
1158  * @perrno: pointer to return error code
1159  *
1160  * Return one of the valid command types or I40E_NVMUPD_INVALID
1161  **/
1162 static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,
1163                                                  struct i40e_nvm_access *cmd,
1164                                                  int *perrno)
1165 {
1166         enum i40e_nvmupd_cmd upd_cmd;
1167         u8 module, transaction;
1168
1169         /* anything that doesn't match a recognized case is an error */
1170         upd_cmd = I40E_NVMUPD_INVALID;
1171
1172         transaction = i40e_nvmupd_get_transaction(cmd->config);
1173         module = i40e_nvmupd_get_module(cmd->config);
1174
1175         /* limits on data size */
1176         if ((cmd->data_size < 1) ||
1177             (cmd->data_size > I40E_NVMUPD_MAX_DATA)) {
1178                 i40e_debug(hw, I40E_DEBUG_NVM,
1179                            "i40e_nvmupd_validate_command data_size %d\n",
1180                            cmd->data_size);
1181                 *perrno = -EFAULT;
1182                 return I40E_NVMUPD_INVALID;
1183         }
1184
1185         switch (cmd->command) {
1186         case I40E_NVM_READ:
1187                 switch (transaction) {
1188                 case I40E_NVM_CON:
1189                         upd_cmd = I40E_NVMUPD_READ_CON;
1190                         break;
1191                 case I40E_NVM_SNT:
1192                         upd_cmd = I40E_NVMUPD_READ_SNT;
1193                         break;
1194                 case I40E_NVM_LCB:
1195                         upd_cmd = I40E_NVMUPD_READ_LCB;
1196                         break;
1197                 case I40E_NVM_SA:
1198                         upd_cmd = I40E_NVMUPD_READ_SA;
1199                         break;
1200                 case I40E_NVM_EXEC:
1201                         if (module == 0xf)
1202                                 upd_cmd = I40E_NVMUPD_STATUS;
1203                         else if (module == 0)
1204                                 upd_cmd = I40E_NVMUPD_GET_AQ_RESULT;
1205                         break;
1206                 }
1207                 break;
1208
1209         case I40E_NVM_WRITE:
1210                 switch (transaction) {
1211                 case I40E_NVM_CON:
1212                         upd_cmd = I40E_NVMUPD_WRITE_CON;
1213                         break;
1214                 case I40E_NVM_SNT:
1215                         upd_cmd = I40E_NVMUPD_WRITE_SNT;
1216                         break;
1217                 case I40E_NVM_LCB:
1218                         upd_cmd = I40E_NVMUPD_WRITE_LCB;
1219                         break;
1220                 case I40E_NVM_SA:
1221                         upd_cmd = I40E_NVMUPD_WRITE_SA;
1222                         break;
1223                 case I40E_NVM_ERA:
1224                         upd_cmd = I40E_NVMUPD_WRITE_ERA;
1225                         break;
1226                 case I40E_NVM_CSUM:
1227                         upd_cmd = I40E_NVMUPD_CSUM_CON;
1228                         break;
1229                 case (I40E_NVM_CSUM|I40E_NVM_SA):
1230                         upd_cmd = I40E_NVMUPD_CSUM_SA;
1231                         break;
1232                 case (I40E_NVM_CSUM|I40E_NVM_LCB):
1233                         upd_cmd = I40E_NVMUPD_CSUM_LCB;
1234                         break;
1235                 case I40E_NVM_EXEC:
1236                         if (module == 0)
1237                                 upd_cmd = I40E_NVMUPD_EXEC_AQ;
1238                         break;
1239                 }
1240                 break;
1241         }
1242
1243         return upd_cmd;
1244 }
1245
1246 /**
1247  * i40e_nvmupd_exec_aq - Run an AQ command
1248  * @hw: pointer to hardware structure
1249  * @cmd: pointer to nvm update command buffer
1250  * @bytes: pointer to the data buffer
1251  * @perrno: pointer to return error code
1252  *
1253  * cmd structure contains identifiers and data buffer
1254  **/
1255 static i40e_status i40e_nvmupd_exec_aq(struct i40e_hw *hw,
1256                                        struct i40e_nvm_access *cmd,
1257                                        u8 *bytes, int *perrno)
1258 {
1259         struct i40e_asq_cmd_details cmd_details;
1260         i40e_status status;
1261         struct i40e_aq_desc *aq_desc;
1262         u32 buff_size = 0;
1263         u8 *buff = NULL;
1264         u32 aq_desc_len;
1265         u32 aq_data_len;
1266
1267         i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__);
1268         memset(&cmd_details, 0, sizeof(cmd_details));
1269         cmd_details.wb_desc = &hw->nvm_wb_desc;
1270
1271         aq_desc_len = sizeof(struct i40e_aq_desc);
1272         memset(&hw->nvm_wb_desc, 0, aq_desc_len);
1273
1274         /* get the aq descriptor */
1275         if (cmd->data_size < aq_desc_len) {
1276                 i40e_debug(hw, I40E_DEBUG_NVM,
1277                            "NVMUPD: not enough aq desc bytes for exec, size %d < %d\n",
1278                            cmd->data_size, aq_desc_len);
1279                 *perrno = -EINVAL;
1280                 return I40E_ERR_PARAM;
1281         }
1282         aq_desc = (struct i40e_aq_desc *)bytes;
1283
1284         /* if data buffer needed, make sure it's ready */
1285         aq_data_len = cmd->data_size - aq_desc_len;
1286         buff_size = max_t(u32, aq_data_len, le16_to_cpu(aq_desc->datalen));
1287         if (buff_size) {
1288                 if (!hw->nvm_buff.va) {
1289                         status = i40e_allocate_virt_mem(hw, &hw->nvm_buff,
1290                                                         hw->aq.asq_buf_size);
1291                         if (status)
1292                                 i40e_debug(hw, I40E_DEBUG_NVM,
1293                                            "NVMUPD: i40e_allocate_virt_mem for exec buff failed, %d\n",
1294                                            status);
1295                 }
1296
1297                 if (hw->nvm_buff.va) {
1298                         buff = hw->nvm_buff.va;
1299                         memcpy(buff, &bytes[aq_desc_len], aq_data_len);
1300                 }
1301         }
1302
1303         /* and away we go! */
1304         status = i40e_asq_send_command(hw, aq_desc, buff,
1305                                        buff_size, &cmd_details);
1306         if (status) {
1307                 i40e_debug(hw, I40E_DEBUG_NVM,
1308                            "i40e_nvmupd_exec_aq err %s aq_err %s\n",
1309                            i40e_stat_str(hw, status),
1310                            i40e_aq_str(hw, hw->aq.asq_last_status));
1311                 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1312         }
1313
1314         /* should we wait for a followup event? */
1315         if (cmd->offset) {
1316                 hw->nvm_wait_opcode = cmd->offset;
1317                 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1318         }
1319
1320         return status;
1321 }
1322
1323 /**
1324  * i40e_nvmupd_get_aq_result - Get the results from the previous exec_aq
1325  * @hw: pointer to hardware structure
1326  * @cmd: pointer to nvm update command buffer
1327  * @bytes: pointer to the data buffer
1328  * @perrno: pointer to return error code
1329  *
1330  * cmd structure contains identifiers and data buffer
1331  **/
1332 static i40e_status i40e_nvmupd_get_aq_result(struct i40e_hw *hw,
1333                                              struct i40e_nvm_access *cmd,
1334                                              u8 *bytes, int *perrno)
1335 {
1336         u32 aq_total_len;
1337         u32 aq_desc_len;
1338         int remainder;
1339         u8 *buff;
1340
1341         i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__);
1342
1343         aq_desc_len = sizeof(struct i40e_aq_desc);
1344         aq_total_len = aq_desc_len + le16_to_cpu(hw->nvm_wb_desc.datalen);
1345
1346         /* check offset range */
1347         if (cmd->offset > aq_total_len) {
1348                 i40e_debug(hw, I40E_DEBUG_NVM, "%s: offset too big %d > %d\n",
1349                            __func__, cmd->offset, aq_total_len);
1350                 *perrno = -EINVAL;
1351                 return I40E_ERR_PARAM;
1352         }
1353
1354         /* check copylength range */
1355         if (cmd->data_size > (aq_total_len - cmd->offset)) {
1356                 int new_len = aq_total_len - cmd->offset;
1357
1358                 i40e_debug(hw, I40E_DEBUG_NVM, "%s: copy length %d too big, trimming to %d\n",
1359                            __func__, cmd->data_size, new_len);
1360                 cmd->data_size = new_len;
1361         }
1362
1363         remainder = cmd->data_size;
1364         if (cmd->offset < aq_desc_len) {
1365                 u32 len = aq_desc_len - cmd->offset;
1366
1367                 len = min(len, cmd->data_size);
1368                 i40e_debug(hw, I40E_DEBUG_NVM, "%s: aq_desc bytes %d to %d\n",
1369                            __func__, cmd->offset, cmd->offset + len);
1370
1371                 buff = ((u8 *)&hw->nvm_wb_desc) + cmd->offset;
1372                 memcpy(bytes, buff, len);
1373
1374                 bytes += len;
1375                 remainder -= len;
1376                 buff = hw->nvm_buff.va;
1377         } else {
1378                 buff = hw->nvm_buff.va + (cmd->offset - aq_desc_len);
1379         }
1380
1381         if (remainder > 0) {
1382                 int start_byte = buff - (u8 *)hw->nvm_buff.va;
1383
1384                 i40e_debug(hw, I40E_DEBUG_NVM, "%s: databuf bytes %d to %d\n",
1385                            __func__, start_byte, start_byte + remainder);
1386                 memcpy(bytes, buff, remainder);
1387         }
1388
1389         return 0;
1390 }
1391
1392 /**
1393  * i40e_nvmupd_nvm_read - Read NVM
1394  * @hw: pointer to hardware structure
1395  * @cmd: pointer to nvm update command buffer
1396  * @bytes: pointer to the data buffer
1397  * @perrno: pointer to return error code
1398  *
1399  * cmd structure contains identifiers and data buffer
1400  **/
1401 static i40e_status i40e_nvmupd_nvm_read(struct i40e_hw *hw,
1402                                         struct i40e_nvm_access *cmd,
1403                                         u8 *bytes, int *perrno)
1404 {
1405         struct i40e_asq_cmd_details cmd_details;
1406         i40e_status status;
1407         u8 module, transaction;
1408         bool last;
1409
1410         transaction = i40e_nvmupd_get_transaction(cmd->config);
1411         module = i40e_nvmupd_get_module(cmd->config);
1412         last = (transaction == I40E_NVM_LCB) || (transaction == I40E_NVM_SA);
1413
1414         memset(&cmd_details, 0, sizeof(cmd_details));
1415         cmd_details.wb_desc = &hw->nvm_wb_desc;
1416
1417         status = i40e_aq_read_nvm(hw, module, cmd->offset, (u16)cmd->data_size,
1418                                   bytes, last, &cmd_details);
1419         if (status) {
1420                 i40e_debug(hw, I40E_DEBUG_NVM,
1421                            "i40e_nvmupd_nvm_read mod 0x%x  off 0x%x  len 0x%x\n",
1422                            module, cmd->offset, cmd->data_size);
1423                 i40e_debug(hw, I40E_DEBUG_NVM,
1424                            "i40e_nvmupd_nvm_read status %d aq %d\n",
1425                            status, hw->aq.asq_last_status);
1426                 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1427         }
1428
1429         return status;
1430 }
1431
1432 /**
1433  * i40e_nvmupd_nvm_erase - Erase an NVM module
1434  * @hw: pointer to hardware structure
1435  * @cmd: pointer to nvm update command buffer
1436  * @perrno: pointer to return error code
1437  *
1438  * module, offset, data_size and data are in cmd structure
1439  **/
1440 static i40e_status i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
1441                                          struct i40e_nvm_access *cmd,
1442                                          int *perrno)
1443 {
1444         i40e_status status = 0;
1445         struct i40e_asq_cmd_details cmd_details;
1446         u8 module, transaction;
1447         bool last;
1448
1449         transaction = i40e_nvmupd_get_transaction(cmd->config);
1450         module = i40e_nvmupd_get_module(cmd->config);
1451         last = (transaction & I40E_NVM_LCB);
1452
1453         memset(&cmd_details, 0, sizeof(cmd_details));
1454         cmd_details.wb_desc = &hw->nvm_wb_desc;
1455
1456         status = i40e_aq_erase_nvm(hw, module, cmd->offset, (u16)cmd->data_size,
1457                                    last, &cmd_details);
1458         if (status) {
1459                 i40e_debug(hw, I40E_DEBUG_NVM,
1460                            "i40e_nvmupd_nvm_erase mod 0x%x  off 0x%x len 0x%x\n",
1461                            module, cmd->offset, cmd->data_size);
1462                 i40e_debug(hw, I40E_DEBUG_NVM,
1463                            "i40e_nvmupd_nvm_erase status %d aq %d\n",
1464                            status, hw->aq.asq_last_status);
1465                 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1466         }
1467
1468         return status;
1469 }
1470
1471 /**
1472  * i40e_nvmupd_nvm_write - Write NVM
1473  * @hw: pointer to hardware structure
1474  * @cmd: pointer to nvm update command buffer
1475  * @bytes: pointer to the data buffer
1476  * @perrno: pointer to return error code
1477  *
1478  * module, offset, data_size and data are in cmd structure
1479  **/
1480 static i40e_status i40e_nvmupd_nvm_write(struct i40e_hw *hw,
1481                                          struct i40e_nvm_access *cmd,
1482                                          u8 *bytes, int *perrno)
1483 {
1484         i40e_status status = 0;
1485         struct i40e_asq_cmd_details cmd_details;
1486         u8 module, transaction;
1487         bool last;
1488
1489         transaction = i40e_nvmupd_get_transaction(cmd->config);
1490         module = i40e_nvmupd_get_module(cmd->config);
1491         last = (transaction & I40E_NVM_LCB);
1492
1493         memset(&cmd_details, 0, sizeof(cmd_details));
1494         cmd_details.wb_desc = &hw->nvm_wb_desc;
1495
1496         status = i40e_aq_update_nvm(hw, module, cmd->offset,
1497                                     (u16)cmd->data_size, bytes, last,
1498                                     &cmd_details);
1499         if (status) {
1500                 i40e_debug(hw, I40E_DEBUG_NVM,
1501                            "i40e_nvmupd_nvm_write mod 0x%x off 0x%x len 0x%x\n",
1502                            module, cmd->offset, cmd->data_size);
1503                 i40e_debug(hw, I40E_DEBUG_NVM,
1504                            "i40e_nvmupd_nvm_write status %d aq %d\n",
1505                            status, hw->aq.asq_last_status);
1506                 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1507         }
1508
1509         return status;
1510 }