1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
27 #include "i40e_status.h"
28 #include "i40e_type.h"
29 #include "i40e_register.h"
30 #include "i40e_adminq.h"
31 #include "i40e_prototype.h"
34 * i40e_is_nvm_update_op - return true if this is an NVM update operation
35 * @desc: API request descriptor
37 static inline bool i40e_is_nvm_update_op(struct i40e_aq_desc *desc)
39 return (desc->opcode == i40e_aqc_opc_nvm_erase) ||
40 (desc->opcode == i40e_aqc_opc_nvm_update);
44 * i40e_adminq_init_regs - Initialize AdminQ registers
45 * @hw: pointer to the hardware structure
47 * This assumes the alloc_asq and alloc_arq functions have already been called
49 static void i40e_adminq_init_regs(struct i40e_hw *hw)
51 /* set head and tail registers in our local struct */
52 if (hw->mac.type == I40E_MAC_VF) {
53 hw->aq.asq.tail = I40E_VF_ATQT1;
54 hw->aq.asq.head = I40E_VF_ATQH1;
55 hw->aq.asq.len = I40E_VF_ATQLEN1;
56 hw->aq.asq.bal = I40E_VF_ATQBAL1;
57 hw->aq.asq.bah = I40E_VF_ATQBAH1;
58 hw->aq.arq.tail = I40E_VF_ARQT1;
59 hw->aq.arq.head = I40E_VF_ARQH1;
60 hw->aq.arq.len = I40E_VF_ARQLEN1;
61 hw->aq.arq.bal = I40E_VF_ARQBAL1;
62 hw->aq.arq.bah = I40E_VF_ARQBAH1;
64 hw->aq.asq.tail = I40E_PF_ATQT;
65 hw->aq.asq.head = I40E_PF_ATQH;
66 hw->aq.asq.len = I40E_PF_ATQLEN;
67 hw->aq.asq.bal = I40E_PF_ATQBAL;
68 hw->aq.asq.bah = I40E_PF_ATQBAH;
69 hw->aq.arq.tail = I40E_PF_ARQT;
70 hw->aq.arq.head = I40E_PF_ARQH;
71 hw->aq.arq.len = I40E_PF_ARQLEN;
72 hw->aq.arq.bal = I40E_PF_ARQBAL;
73 hw->aq.arq.bah = I40E_PF_ARQBAH;
78 * i40e_alloc_adminq_asq_ring - Allocate Admin Queue send rings
79 * @hw: pointer to the hardware structure
81 static i40e_status i40e_alloc_adminq_asq_ring(struct i40e_hw *hw)
85 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,
87 (hw->aq.num_asq_entries *
88 sizeof(struct i40e_aq_desc)),
89 I40E_ADMINQ_DESC_ALIGNMENT);
93 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf,
94 (hw->aq.num_asq_entries *
95 sizeof(struct i40e_asq_cmd_details)));
97 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
105 * i40e_alloc_adminq_arq_ring - Allocate Admin Queue receive rings
106 * @hw: pointer to the hardware structure
108 static i40e_status i40e_alloc_adminq_arq_ring(struct i40e_hw *hw)
110 i40e_status ret_code;
112 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf,
114 (hw->aq.num_arq_entries *
115 sizeof(struct i40e_aq_desc)),
116 I40E_ADMINQ_DESC_ALIGNMENT);
122 * i40e_free_adminq_asq - Free Admin Queue send rings
123 * @hw: pointer to the hardware structure
125 * This assumes the posted send buffers have already been cleaned
128 static void i40e_free_adminq_asq(struct i40e_hw *hw)
130 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
134 * i40e_free_adminq_arq - Free Admin Queue receive rings
135 * @hw: pointer to the hardware structure
137 * This assumes the posted receive buffers have already been cleaned
140 static void i40e_free_adminq_arq(struct i40e_hw *hw)
142 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
146 * i40e_alloc_arq_bufs - Allocate pre-posted buffers for the receive queue
147 * @hw: pointer to the hardware structure
149 static i40e_status i40e_alloc_arq_bufs(struct i40e_hw *hw)
151 i40e_status ret_code;
152 struct i40e_aq_desc *desc;
153 struct i40e_dma_mem *bi;
156 /* We'll be allocating the buffer info memory first, then we can
157 * allocate the mapped buffers for the event processing
160 /* buffer_info structures do not need alignment */
161 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head,
162 (hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem)));
165 hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va;
167 /* allocate the mapped buffers */
168 for (i = 0; i < hw->aq.num_arq_entries; i++) {
169 bi = &hw->aq.arq.r.arq_bi[i];
170 ret_code = i40e_allocate_dma_mem(hw, bi,
173 I40E_ADMINQ_DESC_ALIGNMENT);
175 goto unwind_alloc_arq_bufs;
177 /* now configure the descriptors for use */
178 desc = I40E_ADMINQ_DESC(hw->aq.arq, i);
180 desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF);
181 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
182 desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB);
184 /* This is in accordance with Admin queue design, there is no
185 * register for buffer size configuration
187 desc->datalen = cpu_to_le16((u16)bi->size);
189 desc->cookie_high = 0;
190 desc->cookie_low = 0;
191 desc->params.external.addr_high =
192 cpu_to_le32(upper_32_bits(bi->pa));
193 desc->params.external.addr_low =
194 cpu_to_le32(lower_32_bits(bi->pa));
195 desc->params.external.param0 = 0;
196 desc->params.external.param1 = 0;
202 unwind_alloc_arq_bufs:
203 /* don't try to free the one that failed... */
206 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
207 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
213 * i40e_alloc_asq_bufs - Allocate empty buffer structs for the send queue
214 * @hw: pointer to the hardware structure
216 static i40e_status i40e_alloc_asq_bufs(struct i40e_hw *hw)
218 i40e_status ret_code;
219 struct i40e_dma_mem *bi;
222 /* No mapped memory needed yet, just the buffer info structures */
223 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head,
224 (hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem)));
227 hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va;
229 /* allocate the mapped buffers */
230 for (i = 0; i < hw->aq.num_asq_entries; i++) {
231 bi = &hw->aq.asq.r.asq_bi[i];
232 ret_code = i40e_allocate_dma_mem(hw, bi,
235 I40E_ADMINQ_DESC_ALIGNMENT);
237 goto unwind_alloc_asq_bufs;
242 unwind_alloc_asq_bufs:
243 /* don't try to free the one that failed... */
246 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
247 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
253 * i40e_free_arq_bufs - Free receive queue buffer info elements
254 * @hw: pointer to the hardware structure
256 static void i40e_free_arq_bufs(struct i40e_hw *hw)
260 /* free descriptors */
261 for (i = 0; i < hw->aq.num_arq_entries; i++)
262 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
264 /* free the descriptor memory */
265 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);
267 /* free the dma header */
268 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
272 * i40e_free_asq_bufs - Free send queue buffer info elements
273 * @hw: pointer to the hardware structure
275 static void i40e_free_asq_bufs(struct i40e_hw *hw)
279 /* only unmap if the address is non-NULL */
280 for (i = 0; i < hw->aq.num_asq_entries; i++)
281 if (hw->aq.asq.r.asq_bi[i].pa)
282 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
284 /* free the buffer info list */
285 i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf);
287 /* free the descriptor memory */
288 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);
290 /* free the dma header */
291 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head);
295 * i40e_config_asq_regs - configure ASQ registers
296 * @hw: pointer to the hardware structure
298 * Configure base address and length registers for the transmit queue
300 static i40e_status i40e_config_asq_regs(struct i40e_hw *hw)
302 i40e_status ret_code = 0;
305 /* Clear Head and Tail */
306 wr32(hw, hw->aq.asq.head, 0);
307 wr32(hw, hw->aq.asq.tail, 0);
309 /* set starting point */
310 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
311 I40E_PF_ATQLEN_ATQENABLE_MASK));
312 wr32(hw, hw->aq.asq.bal, lower_32_bits(hw->aq.asq.desc_buf.pa));
313 wr32(hw, hw->aq.asq.bah, upper_32_bits(hw->aq.asq.desc_buf.pa));
315 /* Check one register to verify that config was applied */
316 reg = rd32(hw, hw->aq.asq.bal);
317 if (reg != lower_32_bits(hw->aq.asq.desc_buf.pa))
318 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
324 * i40e_config_arq_regs - ARQ register configuration
325 * @hw: pointer to the hardware structure
327 * Configure base address and length registers for the receive (event queue)
329 static i40e_status i40e_config_arq_regs(struct i40e_hw *hw)
331 i40e_status ret_code = 0;
334 /* Clear Head and Tail */
335 wr32(hw, hw->aq.arq.head, 0);
336 wr32(hw, hw->aq.arq.tail, 0);
338 /* set starting point */
339 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
340 I40E_PF_ARQLEN_ARQENABLE_MASK));
341 wr32(hw, hw->aq.arq.bal, lower_32_bits(hw->aq.arq.desc_buf.pa));
342 wr32(hw, hw->aq.arq.bah, upper_32_bits(hw->aq.arq.desc_buf.pa));
344 /* Update tail in the HW to post pre-allocated buffers */
345 wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
347 /* Check one register to verify that config was applied */
348 reg = rd32(hw, hw->aq.arq.bal);
349 if (reg != lower_32_bits(hw->aq.arq.desc_buf.pa))
350 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
356 * i40e_init_asq - main initialization routine for ASQ
357 * @hw: pointer to the hardware structure
359 * This is the main initialization routine for the Admin Send Queue
360 * Prior to calling this function, drivers *MUST* set the following fields
361 * in the hw->aq structure:
362 * - hw->aq.num_asq_entries
363 * - hw->aq.arq_buf_size
365 * Do *NOT* hold the lock when calling this as the memory allocation routines
366 * called are not going to be atomic context safe
368 static i40e_status i40e_init_asq(struct i40e_hw *hw)
370 i40e_status ret_code = 0;
372 if (hw->aq.asq.count > 0) {
373 /* queue already initialized */
374 ret_code = I40E_ERR_NOT_READY;
375 goto init_adminq_exit;
378 /* verify input for valid configuration */
379 if ((hw->aq.num_asq_entries == 0) ||
380 (hw->aq.asq_buf_size == 0)) {
381 ret_code = I40E_ERR_CONFIG;
382 goto init_adminq_exit;
385 hw->aq.asq.next_to_use = 0;
386 hw->aq.asq.next_to_clean = 0;
387 hw->aq.asq.count = hw->aq.num_asq_entries;
389 /* allocate the ring memory */
390 ret_code = i40e_alloc_adminq_asq_ring(hw);
392 goto init_adminq_exit;
394 /* allocate buffers in the rings */
395 ret_code = i40e_alloc_asq_bufs(hw);
397 goto init_adminq_free_rings;
399 /* initialize base registers */
400 ret_code = i40e_config_asq_regs(hw);
402 goto init_adminq_free_rings;
405 goto init_adminq_exit;
407 init_adminq_free_rings:
408 i40e_free_adminq_asq(hw);
415 * i40e_init_arq - initialize ARQ
416 * @hw: pointer to the hardware structure
418 * The main initialization routine for the Admin Receive (Event) Queue.
419 * Prior to calling this function, drivers *MUST* set the following fields
420 * in the hw->aq structure:
421 * - hw->aq.num_asq_entries
422 * - hw->aq.arq_buf_size
424 * Do *NOT* hold the lock when calling this as the memory allocation routines
425 * called are not going to be atomic context safe
427 static i40e_status i40e_init_arq(struct i40e_hw *hw)
429 i40e_status ret_code = 0;
431 if (hw->aq.arq.count > 0) {
432 /* queue already initialized */
433 ret_code = I40E_ERR_NOT_READY;
434 goto init_adminq_exit;
437 /* verify input for valid configuration */
438 if ((hw->aq.num_arq_entries == 0) ||
439 (hw->aq.arq_buf_size == 0)) {
440 ret_code = I40E_ERR_CONFIG;
441 goto init_adminq_exit;
444 hw->aq.arq.next_to_use = 0;
445 hw->aq.arq.next_to_clean = 0;
446 hw->aq.arq.count = hw->aq.num_arq_entries;
448 /* allocate the ring memory */
449 ret_code = i40e_alloc_adminq_arq_ring(hw);
451 goto init_adminq_exit;
453 /* allocate buffers in the rings */
454 ret_code = i40e_alloc_arq_bufs(hw);
456 goto init_adminq_free_rings;
458 /* initialize base registers */
459 ret_code = i40e_config_arq_regs(hw);
461 goto init_adminq_free_rings;
464 goto init_adminq_exit;
466 init_adminq_free_rings:
467 i40e_free_adminq_arq(hw);
474 * i40e_shutdown_asq - shutdown the ASQ
475 * @hw: pointer to the hardware structure
477 * The main shutdown routine for the Admin Send Queue
479 static i40e_status i40e_shutdown_asq(struct i40e_hw *hw)
481 i40e_status ret_code = 0;
483 if (hw->aq.asq.count == 0)
484 return I40E_ERR_NOT_READY;
486 /* Stop firmware AdminQ processing */
487 wr32(hw, hw->aq.asq.head, 0);
488 wr32(hw, hw->aq.asq.tail, 0);
489 wr32(hw, hw->aq.asq.len, 0);
491 /* make sure lock is available */
492 mutex_lock(&hw->aq.asq_mutex);
494 hw->aq.asq.count = 0; /* to indicate uninitialized queue */
496 /* free ring buffers */
497 i40e_free_asq_bufs(hw);
499 mutex_unlock(&hw->aq.asq_mutex);
505 * i40e_shutdown_arq - shutdown ARQ
506 * @hw: pointer to the hardware structure
508 * The main shutdown routine for the Admin Receive Queue
510 static i40e_status i40e_shutdown_arq(struct i40e_hw *hw)
512 i40e_status ret_code = 0;
514 if (hw->aq.arq.count == 0)
515 return I40E_ERR_NOT_READY;
517 /* Stop firmware AdminQ processing */
518 wr32(hw, hw->aq.arq.head, 0);
519 wr32(hw, hw->aq.arq.tail, 0);
520 wr32(hw, hw->aq.arq.len, 0);
522 /* make sure lock is available */
523 mutex_lock(&hw->aq.arq_mutex);
525 hw->aq.arq.count = 0; /* to indicate uninitialized queue */
527 /* free ring buffers */
528 i40e_free_arq_bufs(hw);
530 mutex_unlock(&hw->aq.arq_mutex);
536 * i40evf_init_adminq - main initialization routine for Admin Queue
537 * @hw: pointer to the hardware structure
539 * Prior to calling this function, drivers *MUST* set the following fields
540 * in the hw->aq structure:
541 * - hw->aq.num_asq_entries
542 * - hw->aq.num_arq_entries
543 * - hw->aq.arq_buf_size
544 * - hw->aq.asq_buf_size
546 i40e_status i40evf_init_adminq(struct i40e_hw *hw)
548 i40e_status ret_code;
550 /* verify input for valid configuration */
551 if ((hw->aq.num_arq_entries == 0) ||
552 (hw->aq.num_asq_entries == 0) ||
553 (hw->aq.arq_buf_size == 0) ||
554 (hw->aq.asq_buf_size == 0)) {
555 ret_code = I40E_ERR_CONFIG;
556 goto init_adminq_exit;
559 /* initialize locks */
560 mutex_init(&hw->aq.asq_mutex);
561 mutex_init(&hw->aq.arq_mutex);
563 /* Set up register offsets */
564 i40e_adminq_init_regs(hw);
566 /* allocate the ASQ */
567 ret_code = i40e_init_asq(hw);
569 goto init_adminq_destroy_locks;
571 /* allocate the ARQ */
572 ret_code = i40e_init_arq(hw);
574 goto init_adminq_free_asq;
577 goto init_adminq_exit;
579 init_adminq_free_asq:
580 i40e_shutdown_asq(hw);
581 init_adminq_destroy_locks:
588 * i40evf_shutdown_adminq - shutdown routine for the Admin Queue
589 * @hw: pointer to the hardware structure
591 i40e_status i40evf_shutdown_adminq(struct i40e_hw *hw)
593 i40e_status ret_code = 0;
595 if (i40evf_check_asq_alive(hw))
596 i40evf_aq_queue_shutdown(hw, true);
598 i40e_shutdown_asq(hw);
599 i40e_shutdown_arq(hw);
601 /* destroy the locks */
607 * i40e_clean_asq - cleans Admin send queue
608 * @hw: pointer to the hardware structure
610 * returns the number of free desc
612 static u16 i40e_clean_asq(struct i40e_hw *hw)
614 struct i40e_adminq_ring *asq = &(hw->aq.asq);
615 struct i40e_asq_cmd_details *details;
616 u16 ntc = asq->next_to_clean;
617 struct i40e_aq_desc desc_cb;
618 struct i40e_aq_desc *desc;
620 desc = I40E_ADMINQ_DESC(*asq, ntc);
621 details = I40E_ADMINQ_DETAILS(*asq, ntc);
622 while (rd32(hw, hw->aq.asq.head) != ntc) {
623 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
624 "%s: ntc %d head %d.\n", __func__, ntc,
625 rd32(hw, hw->aq.asq.head));
627 if (details->callback) {
628 I40E_ADMINQ_CALLBACK cb_func =
629 (I40E_ADMINQ_CALLBACK)details->callback;
631 cb_func(hw, &desc_cb);
633 memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
634 memset((void *)details, 0,
635 sizeof(struct i40e_asq_cmd_details));
637 if (ntc == asq->count)
639 desc = I40E_ADMINQ_DESC(*asq, ntc);
640 details = I40E_ADMINQ_DETAILS(*asq, ntc);
643 asq->next_to_clean = ntc;
645 return I40E_DESC_UNUSED(asq);
649 * i40evf_asq_done - check if FW has processed the Admin Send Queue
650 * @hw: pointer to the hw struct
652 * Returns true if the firmware has processed all descriptors on the
653 * admin send queue. Returns false if there are still requests pending.
655 bool i40evf_asq_done(struct i40e_hw *hw)
657 /* AQ designers suggest use of head for better
658 * timing reliability than DD bit
660 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use;
665 * i40evf_asq_send_command - send command to Admin Queue
666 * @hw: pointer to the hw struct
667 * @desc: prefilled descriptor describing the command (non DMA mem)
668 * @buff: buffer to use for indirect commands
669 * @buff_size: size of buffer for indirect commands
670 * @cmd_details: pointer to command details structure
672 * This is the main send command driver routine for the Admin Queue send
673 * queue. It runs the queue, cleans the queue, etc
675 i40e_status i40evf_asq_send_command(struct i40e_hw *hw,
676 struct i40e_aq_desc *desc,
677 void *buff, /* can be NULL */
679 struct i40e_asq_cmd_details *cmd_details)
681 i40e_status status = 0;
682 struct i40e_dma_mem *dma_buff = NULL;
683 struct i40e_asq_cmd_details *details;
684 struct i40e_aq_desc *desc_on_ring;
685 bool cmd_completed = false;
689 val = rd32(hw, hw->aq.asq.head);
690 if (val >= hw->aq.num_asq_entries) {
691 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
692 "AQTX: head overrun at %d\n", val);
693 status = I40E_ERR_QUEUE_EMPTY;
694 goto asq_send_command_exit;
697 if (hw->aq.asq.count == 0) {
698 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
699 "AQTX: Admin queue not initialized.\n");
700 status = I40E_ERR_QUEUE_EMPTY;
701 goto asq_send_command_exit;
704 if (i40e_is_nvm_update_op(desc) && hw->aq.nvm_busy) {
705 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: NVM busy.\n");
706 status = I40E_ERR_NVM;
707 goto asq_send_command_exit;
710 details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);
712 *details = *cmd_details;
714 /* If the cmd_details are defined copy the cookie. The
715 * cpu_to_le32 is not needed here because the data is ignored
716 * by the FW, only used by the driver
718 if (details->cookie) {
720 cpu_to_le32(upper_32_bits(details->cookie));
722 cpu_to_le32(lower_32_bits(details->cookie));
725 memset(details, 0, sizeof(struct i40e_asq_cmd_details));
728 /* clear requested flags and then set additional flags if defined */
729 desc->flags &= ~cpu_to_le16(details->flags_dis);
730 desc->flags |= cpu_to_le16(details->flags_ena);
732 mutex_lock(&hw->aq.asq_mutex);
734 if (buff_size > hw->aq.asq_buf_size) {
736 I40E_DEBUG_AQ_MESSAGE,
737 "AQTX: Invalid buffer size: %d.\n",
739 status = I40E_ERR_INVALID_SIZE;
740 goto asq_send_command_error;
743 if (details->postpone && !details->async) {
745 I40E_DEBUG_AQ_MESSAGE,
746 "AQTX: Async flag not set along with postpone flag");
747 status = I40E_ERR_PARAM;
748 goto asq_send_command_error;
751 /* call clean and check queue available function to reclaim the
752 * descriptors that were processed by FW, the function returns the
753 * number of desc available
755 /* the clean function called here could be called in a separate thread
756 * in case of asynchronous completions
758 if (i40e_clean_asq(hw) == 0) {
760 I40E_DEBUG_AQ_MESSAGE,
761 "AQTX: Error queue is full.\n");
762 status = I40E_ERR_ADMIN_QUEUE_FULL;
763 goto asq_send_command_error;
766 /* initialize the temp desc pointer with the right desc */
767 desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use);
769 /* if the desc is available copy the temp desc to the right place */
770 *desc_on_ring = *desc;
772 /* if buff is not NULL assume indirect command */
774 dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]);
775 /* copy the user buff into the respective DMA buff */
776 memcpy(dma_buff->va, buff, buff_size);
777 desc_on_ring->datalen = cpu_to_le16(buff_size);
779 /* Update the address values in the desc with the pa value
780 * for respective buffer
782 desc_on_ring->params.external.addr_high =
783 cpu_to_le32(upper_32_bits(dma_buff->pa));
784 desc_on_ring->params.external.addr_low =
785 cpu_to_le32(lower_32_bits(dma_buff->pa));
789 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: desc and buffer:\n");
790 i40evf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, buff);
791 (hw->aq.asq.next_to_use)++;
792 if (hw->aq.asq.next_to_use == hw->aq.asq.count)
793 hw->aq.asq.next_to_use = 0;
794 if (!details->postpone)
795 wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use);
797 /* if cmd_details are not defined or async flag is not set,
798 * we need to wait for desc write back
800 if (!details->async && !details->postpone) {
805 /* AQ designers suggest use of head for better
806 * timing reliability than DD bit
808 if (i40evf_asq_done(hw))
810 /* ugh! delay while spin_lock */
812 total_delay += delay_len;
813 } while (total_delay < I40E_ASQ_CMD_TIMEOUT);
816 /* if ready, copy the desc back to temp */
817 if (i40evf_asq_done(hw)) {
818 *desc = *desc_on_ring;
820 memcpy(buff, dma_buff->va, buff_size);
821 retval = le16_to_cpu(desc->retval);
824 I40E_DEBUG_AQ_MESSAGE,
825 "AQTX: Command completed with error 0x%X.\n",
828 /* strip off FW internal code */
831 cmd_completed = true;
832 if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_OK)
835 status = I40E_ERR_ADMIN_QUEUE_ERROR;
836 hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval;
839 if (i40e_is_nvm_update_op(desc))
840 hw->aq.nvm_busy = true;
842 if (le16_to_cpu(desc->datalen) == buff_size) {
843 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
844 "AQTX: desc and buffer writeback:\n");
845 i40evf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff);
848 /* update the error if time out occurred */
849 if ((!cmd_completed) &&
850 (!details->async && !details->postpone)) {
852 I40E_DEBUG_AQ_MESSAGE,
853 "AQTX: Writeback timeout.\n");
854 status = I40E_ERR_ADMIN_QUEUE_TIMEOUT;
857 asq_send_command_error:
858 mutex_unlock(&hw->aq.asq_mutex);
859 asq_send_command_exit:
864 * i40evf_fill_default_direct_cmd_desc - AQ descriptor helper function
865 * @desc: pointer to the temp descriptor (non DMA mem)
866 * @opcode: the opcode can be used to decide which flags to turn off or on
868 * Fill the desc with default values
870 void i40evf_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
873 /* zero out the desc */
874 memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
875 desc->opcode = cpu_to_le16(opcode);
876 desc->flags = cpu_to_le16(I40E_AQ_FLAG_SI);
880 * i40evf_clean_arq_element
881 * @hw: pointer to the hw struct
882 * @e: event info from the receive descriptor, includes any buffers
883 * @pending: number of events that could be left to process
885 * This function cleans one Admin Receive Queue element and returns
886 * the contents through e. It can also return how many events are
887 * left to process through 'pending'
889 i40e_status i40evf_clean_arq_element(struct i40e_hw *hw,
890 struct i40e_arq_event_info *e,
893 i40e_status ret_code = 0;
894 u16 ntc = hw->aq.arq.next_to_clean;
895 struct i40e_aq_desc *desc;
896 struct i40e_dma_mem *bi;
902 /* take the lock before we start messing with the ring */
903 mutex_lock(&hw->aq.arq_mutex);
905 /* set next_to_use to head */
906 ntu = (rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK);
908 /* nothing to do - shouldn't need to update ring's values */
910 I40E_DEBUG_AQ_MESSAGE,
911 "AQRX: Queue is empty.\n");
912 ret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK;
913 goto clean_arq_element_out;
916 /* now clean the next descriptor */
917 desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);
920 flags = le16_to_cpu(desc->flags);
921 if (flags & I40E_AQ_FLAG_ERR) {
922 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
923 hw->aq.arq_last_status =
924 (enum i40e_admin_queue_err)le16_to_cpu(desc->retval);
926 I40E_DEBUG_AQ_MESSAGE,
927 "AQRX: Event received with error 0x%X.\n",
928 hw->aq.arq_last_status);
931 datalen = le16_to_cpu(desc->datalen);
932 e->msg_size = min(datalen, e->msg_size);
933 if (e->msg_buf != NULL && (e->msg_size != 0))
934 memcpy(e->msg_buf, hw->aq.arq.r.arq_bi[desc_idx].va,
938 if (i40e_is_nvm_update_op(&e->desc))
939 hw->aq.nvm_busy = false;
941 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQRX: desc and buffer:\n");
942 i40evf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf);
944 /* Restore the original datalen and buffer address in the desc,
945 * FW updates datalen to indicate the event message
948 bi = &hw->aq.arq.r.arq_bi[ntc];
949 memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
951 desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF);
952 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
953 desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB);
954 desc->datalen = cpu_to_le16((u16)bi->size);
955 desc->params.external.addr_high = cpu_to_le32(upper_32_bits(bi->pa));
956 desc->params.external.addr_low = cpu_to_le32(lower_32_bits(bi->pa));
958 /* set tail = the last cleaned desc index. */
959 wr32(hw, hw->aq.arq.tail, ntc);
960 /* ntc is updated to tail + 1 */
962 if (ntc == hw->aq.num_arq_entries)
964 hw->aq.arq.next_to_clean = ntc;
965 hw->aq.arq.next_to_use = ntu;
967 clean_arq_element_out:
968 /* Set pending if needed, unlock and return */
970 *pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc);
971 mutex_unlock(&hw->aq.arq_mutex);
976 void i40evf_resume_aq(struct i40e_hw *hw)
978 /* Registers are reset after PF reset */
979 hw->aq.asq.next_to_use = 0;
980 hw->aq.asq.next_to_clean = 0;
982 i40e_config_asq_regs(hw);
984 hw->aq.arq.next_to_use = 0;
985 hw->aq.arq.next_to_clean = 0;
987 i40e_config_arq_regs(hw);