2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/crash_dump.h>
41 #include <linux/mlx5/driver.h>
42 #include <linux/mlx5/qp.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/port.h>
45 #include <linux/mlx5/vport.h>
46 #include <linux/mlx5/transobj.h>
47 #include <linux/mlx5/fs.h>
48 #include <linux/rhashtable.h>
49 #include <net/switchdev.h>
51 #include <linux/net_dim.h>
52 #include <linux/bits.h>
54 #include "mlx5_core.h"
58 extern const struct net_device_ops mlx5e_netdev_ops;
61 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4)
62 #define MLX5E_METADATA_ETHER_LEN 8
64 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
66 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
68 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
69 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))
71 #define MLX5E_MAX_PRIORITY 8
72 #define MLX5E_MAX_DSCP 64
73 #define MLX5E_MAX_NUM_TC 8
75 #define MLX5_RX_HEADROOM NET_SKB_PAD
76 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
77 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
79 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
80 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
81 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
82 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
83 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 6)
84 #define MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 8)
85 #define MLX5E_MPWQE_STRIDE_SZ(mdev, cqe_cmprs) \
86 (cqe_cmprs ? MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) : \
87 MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev))
89 #define MLX5_MPWRQ_LOG_WQE_SZ 18
90 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
91 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
92 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
94 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
95 #define MLX5E_REQUIRED_WQE_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
96 #define MLX5E_LOG_ALIGNED_MPWQE_PPW (ilog2(MLX5E_REQUIRED_WQE_MTTS))
97 #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS)
98 #define MLX5E_MAX_RQ_NUM_MTTS \
99 ((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */
100 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))
101 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \
102 (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS))
103 #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \
104 (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \
105 (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU))
107 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))
108 #define MLX5E_LOG_MAX_RX_WQE_BULK \
109 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))
111 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
112 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
113 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
115 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)
116 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
117 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \
118 MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW)
120 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
122 #define MLX5E_RX_MAX_HEAD (256)
124 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
125 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
126 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
128 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
129 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
130 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
131 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
132 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
133 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
134 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
135 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
137 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
138 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
139 #define MLX5E_MIN_NUM_CHANNELS 0x1
140 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
141 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
142 #define MLX5E_TX_CQ_POLL_BUDGET 128
143 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */
145 #define MLX5E_UMR_WQE_INLINE_SZ \
146 (sizeof(struct mlx5e_umr_wqe) + \
147 ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \
148 MLX5_UMR_MTT_ALIGNMENT))
149 #define MLX5E_UMR_WQEBBS \
150 (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB))
152 #define MLX5E_MSG_LEVEL NETIF_MSG_LINK
154 #define mlx5e_dbg(mlevel, priv, format, ...) \
156 if (NETIF_MSG_##mlevel & (priv)->msglevel) \
157 netdev_warn(priv->netdev, format, \
162 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
165 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
166 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
169 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
174 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */
175 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
177 return is_kdump_kernel() ?
178 MLX5E_MIN_NUM_CHANNELS :
179 min_t(int, mlx5_comp_vectors_count(mdev), MLX5E_MAX_NUM_CHANNELS);
182 /* Use this function to get max num channels after netdev was created */
183 static inline int mlx5e_get_netdev_max_channels(struct net_device *netdev)
185 return min_t(unsigned int, netdev->num_rx_queues,
186 netdev->num_tx_queues);
189 struct mlx5e_tx_wqe {
190 struct mlx5_wqe_ctrl_seg ctrl;
191 struct mlx5_wqe_eth_seg eth;
192 struct mlx5_wqe_data_seg data[0];
195 struct mlx5e_rx_wqe_ll {
196 struct mlx5_wqe_srq_next_seg next;
197 struct mlx5_wqe_data_seg data[0];
200 struct mlx5e_rx_wqe_cyc {
201 struct mlx5_wqe_data_seg data[0];
204 struct mlx5e_umr_wqe {
205 struct mlx5_wqe_ctrl_seg ctrl;
206 struct mlx5_wqe_umr_ctrl_seg uctrl;
207 struct mlx5_mkey_seg mkc;
208 struct mlx5_mtt inline_mtts[0];
211 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
213 enum mlx5e_priv_flag {
214 MLX5E_PFLAG_RX_CQE_BASED_MODER,
215 MLX5E_PFLAG_TX_CQE_BASED_MODER,
216 MLX5E_PFLAG_RX_CQE_COMPRESS,
217 MLX5E_PFLAG_RX_STRIDING_RQ,
218 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,
219 MLX5E_NUM_PFLAGS, /* Keep last */
222 #define MLX5E_SET_PFLAG(params, pflag, enable) \
225 (params)->pflags |= BIT(pflag); \
227 (params)->pflags &= ~(BIT(pflag)); \
230 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag))))
232 #ifdef CONFIG_MLX5_CORE_EN_DCB
233 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
236 struct mlx5e_params {
239 u8 log_rq_mtu_frames;
242 bool rx_cqe_compress_def;
243 struct net_dim_cq_moder rx_cq_moderation;
244 struct net_dim_cq_moder tx_cq_moderation;
247 u8 tx_min_inline_mode;
248 bool vlan_strip_disable;
254 struct bpf_prog *xdp_prog;
259 #ifdef CONFIG_MLX5_CORE_EN_DCB
260 struct mlx5e_cee_config {
261 /* bw pct for priority group */
262 u8 pg_bw_pct[CEE_DCBX_MAX_PGS];
263 u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO];
264 bool pfc_setting[CEE_DCBX_MAX_PRIO];
271 MLX5_DCB_CHG_NO_RESET,
275 enum mlx5_dcbx_oper_mode mode;
276 struct mlx5e_cee_config cee_cfg; /* pending configuration */
279 /* The only setting that cannot be read from FW */
280 u8 tc_tsa[IEEE_8021QAZ_MAX_TCS];
283 /* Buffer configuration */
289 struct mlx5e_dcbx_dp {
290 u8 dscp2prio[MLX5E_MAX_DSCP];
296 MLX5E_RQ_STATE_ENABLED,
298 MLX5E_RQ_STATE_NO_CSUM_COMPLETE,
302 /* data path - accessed per cqe */
305 /* data path - accessed per napi poll */
307 struct napi_struct *napi;
308 struct mlx5_core_cq mcq;
309 struct mlx5e_channel *channel;
311 /* cqe decompression */
312 struct mlx5_cqe64 title;
313 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
316 u16 decmprs_wqe_counter;
319 struct mlx5_core_dev *mdev;
320 struct mlx5_wq_ctrl wq_ctrl;
321 } ____cacheline_aligned_in_smp;
323 struct mlx5e_tx_wqe_info {
330 enum mlx5e_dma_map_type {
331 MLX5E_DMA_MAP_SINGLE,
335 struct mlx5e_sq_dma {
338 enum mlx5e_dma_map_type type;
342 MLX5E_SQ_STATE_ENABLED,
343 MLX5E_SQ_STATE_RECOVERING,
344 MLX5E_SQ_STATE_IPSEC,
349 struct mlx5e_sq_wqe_info {
356 /* dirtied @completion */
359 struct net_dim dim; /* Adaptive Moderation */
362 u16 pc ____cacheline_aligned_in_smp;
368 struct mlx5_wq_cyc wq;
370 struct mlx5e_sq_stats *stats;
372 struct mlx5e_sq_dma *dma_fifo;
373 struct mlx5e_tx_wqe_info *wqe_info;
375 void __iomem *uar_map;
376 struct netdev_queue *txq;
382 struct hwtstamp_config *tstamp;
383 struct mlx5_clock *clock;
386 struct mlx5_wq_ctrl wq_ctrl;
387 struct mlx5e_channel *channel;
390 struct mlx5e_txqsq_recover {
391 struct work_struct recover_work;
394 } ____cacheline_aligned_in_smp;
396 struct mlx5e_dma_info {
401 struct mlx5e_xdp_info {
402 struct xdp_frame *xdpf;
404 struct mlx5e_dma_info di;
407 struct mlx5e_xdp_info_fifo {
408 struct mlx5e_xdp_info *xi;
414 struct mlx5e_xdp_wqe_info {
422 /* dirtied @completion */
428 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp;
430 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
435 struct mlx5_wq_cyc wq;
436 struct mlx5e_xdpsq_stats *stats;
438 struct mlx5e_xdp_wqe_info *wqe_info;
439 struct mlx5e_xdp_info_fifo xdpi_fifo;
441 void __iomem *uar_map;
450 struct mlx5_wq_ctrl wq_ctrl;
451 struct mlx5e_channel *channel;
452 } ____cacheline_aligned_in_smp;
458 u16 pc ____cacheline_aligned_in_smp;
462 /* write@xmit, read@completion */
464 struct mlx5e_sq_wqe_info *ico_wqe;
468 struct mlx5_wq_cyc wq;
469 void __iomem *uar_map;
474 struct mlx5_wq_ctrl wq_ctrl;
475 struct mlx5e_channel *channel;
476 } ____cacheline_aligned_in_smp;
479 mlx5e_wqc_has_room_for(struct mlx5_wq_cyc *wq, u16 cc, u16 pc, u16 n)
481 return (mlx5_wq_cyc_ctr2ix(wq, cc - pc) >= n) || (cc == pc);
484 struct mlx5e_wqe_frag_info {
485 struct mlx5e_dma_info *di;
490 struct mlx5e_umr_dma_info {
491 struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
494 struct mlx5e_mpw_info {
495 struct mlx5e_umr_dma_info umr;
496 u16 consumed_strides;
497 DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
500 #define MLX5E_MAX_RX_FRAGS 4
502 /* a single cache unit is capable to serve one napi call (for non-striding rq)
503 * or a MPWQE (for striding rq).
505 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
506 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
507 #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
508 struct mlx5e_page_cache {
511 struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
515 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
516 typedef struct sk_buff *
517 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
518 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
519 typedef struct sk_buff *
520 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
521 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
522 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
523 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
526 MLX5E_RQ_FLAG_XDP_XMIT = BIT(0),
529 struct mlx5e_rq_frag_info {
534 struct mlx5e_rq_frags_info {
535 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS];
545 struct mlx5_wq_cyc wq;
546 struct mlx5e_wqe_frag_info *frags;
547 struct mlx5e_dma_info *di;
548 struct mlx5e_rq_frags_info info;
549 mlx5e_fp_skb_from_cqe skb_from_cqe;
552 struct mlx5_wq_ll wq;
553 struct mlx5e_umr_wqe umr_wqe;
554 struct mlx5e_mpw_info *info;
555 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq;
558 bool umr_in_progress;
563 u8 map_dir; /* dma map direction */
566 struct mlx5e_channel *channel;
568 struct net_device *netdev;
569 struct mlx5e_rq_stats *stats;
571 struct mlx5e_page_cache page_cache;
572 struct hwtstamp_config *tstamp;
573 struct mlx5_clock *clock;
575 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
576 mlx5e_fp_post_rx_wqes post_wqes;
577 mlx5e_fp_dealloc_wqe dealloc_wqe;
583 struct net_dim dim; /* Dynamic Interrupt Moderation */
586 struct bpf_prog *xdp_prog;
587 struct mlx5e_xdpsq xdpsq;
588 DECLARE_BITMAP(flags, 8);
589 struct page_pool *page_pool;
592 struct mlx5_wq_ctrl wq_ctrl;
596 struct mlx5_core_dev *mdev;
597 struct mlx5_core_mkey umr_mkey;
599 /* XDP read-mostly */
600 struct xdp_rxq_info xdp_rxq;
601 } ____cacheline_aligned_in_smp;
603 struct mlx5e_channel {
606 struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC];
607 struct mlx5e_icosq icosq; /* internal control operations */
609 struct napi_struct napi;
611 struct net_device *netdev;
616 struct mlx5e_xdpsq xdpsq;
618 /* data path - accessed per napi poll */
619 struct irq_desc *irq_desc;
620 struct mlx5e_ch_stats *stats;
623 struct mlx5e_priv *priv;
624 struct mlx5_core_dev *mdev;
625 struct hwtstamp_config *tstamp;
630 struct mlx5e_channels {
631 struct mlx5e_channel **c;
633 struct mlx5e_params params;
636 struct mlx5e_channel_stats {
637 struct mlx5e_ch_stats ch;
638 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
639 struct mlx5e_rq_stats rq;
640 struct mlx5e_xdpsq_stats rq_xdpsq;
641 struct mlx5e_xdpsq_stats xdpsq;
642 } ____cacheline_aligned_in_smp;
646 MLX5E_STATE_DESTROYING,
656 struct mlx5e_rqt rqt;
657 struct list_head list;
665 struct mlx5e_rss_params {
666 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
667 u32 rx_hash_fields[MLX5E_NUM_INDIR_TIRS];
668 u8 toeplitz_hash_key[40];
673 /* priv data path fields - start */
674 struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC];
675 int channel_tc2txq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
676 #ifdef CONFIG_MLX5_CORE_EN_DCB
677 struct mlx5e_dcbx_dp dcbx_dp;
679 /* priv data path fields - end */
683 struct mutex state_lock; /* Protects Interface state */
684 struct mlx5e_rq drop_rq;
686 struct mlx5e_channels channels;
687 u32 tisn[MLX5E_MAX_NUM_TC];
688 struct mlx5e_rqt indir_rqt;
689 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
690 struct mlx5e_tir inner_indir_tir[MLX5E_NUM_INDIR_TIRS];
691 struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
692 struct mlx5e_rss_params rss_params;
693 u32 tx_rates[MLX5E_MAX_NUM_SQS];
695 struct mlx5e_flow_steering fs;
697 struct workqueue_struct *wq;
698 struct work_struct update_carrier_work;
699 struct work_struct set_rx_mode_work;
700 struct work_struct tx_timeout_work;
701 struct work_struct update_stats_work;
702 struct work_struct monitor_counters_work;
703 struct mlx5_nb monitor_counters_nb;
705 struct mlx5_core_dev *mdev;
706 struct net_device *netdev;
707 struct mlx5e_stats stats;
708 struct mlx5e_channel_stats channel_stats[MLX5E_MAX_NUM_CHANNELS];
710 struct hwtstamp_config tstamp;
712 u16 drop_rq_q_counter;
713 struct notifier_block events_nb;
715 #ifdef CONFIG_MLX5_CORE_EN_DCB
716 struct mlx5e_dcbx dcbx;
719 const struct mlx5e_profile *profile;
721 #ifdef CONFIG_MLX5_EN_IPSEC
722 struct mlx5e_ipsec *ipsec;
724 #ifdef CONFIG_MLX5_EN_TLS
725 struct mlx5e_tls *tls;
729 struct mlx5e_profile {
730 int (*init)(struct mlx5_core_dev *mdev,
731 struct net_device *netdev,
732 const struct mlx5e_profile *profile, void *ppriv);
733 void (*cleanup)(struct mlx5e_priv *priv);
734 int (*init_rx)(struct mlx5e_priv *priv);
735 void (*cleanup_rx)(struct mlx5e_priv *priv);
736 int (*init_tx)(struct mlx5e_priv *priv);
737 void (*cleanup_tx)(struct mlx5e_priv *priv);
738 void (*enable)(struct mlx5e_priv *priv);
739 void (*disable)(struct mlx5e_priv *priv);
740 void (*update_stats)(struct mlx5e_priv *priv);
741 void (*update_carrier)(struct mlx5e_priv *priv);
743 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
744 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
749 void mlx5e_build_ptys2ethtool_map(void);
751 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
752 struct net_device *sb_dev,
753 select_queue_fallback_t fallback);
754 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
755 netdev_tx_t mlx5e_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
756 struct mlx5e_tx_wqe *wqe, u16 pi);
758 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
759 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
760 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
761 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
762 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
763 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq);
765 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev);
766 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
767 struct mlx5e_params *params);
769 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info);
770 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
772 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
773 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
774 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
775 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq);
776 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
777 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
779 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
780 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
782 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
783 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
785 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
786 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
788 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
789 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
791 void mlx5e_update_stats(struct mlx5e_priv *priv);
792 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
794 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
795 int mlx5e_self_test_num(struct mlx5e_priv *priv);
796 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
798 void mlx5e_set_rx_mode_work(struct work_struct *work);
800 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
801 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
802 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val);
804 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
806 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
808 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
810 struct mlx5e_redirect_rqt_param {
813 u32 rqn; /* Direct RQN (Non-RSS) */
816 struct mlx5e_channels *channels;
817 } rss; /* RSS data */
821 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
822 struct mlx5e_redirect_rqt_param rrp);
823 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
824 const struct mlx5e_tirc_config *ttconfig,
825 void *tirc, bool inner);
826 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen);
827 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt);
829 int mlx5e_open_locked(struct net_device *netdev);
830 int mlx5e_close_locked(struct net_device *netdev);
832 int mlx5e_open_channels(struct mlx5e_priv *priv,
833 struct mlx5e_channels *chs);
834 void mlx5e_close_channels(struct mlx5e_channels *chs);
836 /* Function pointer to be used to modify WH settings while
839 typedef int (*mlx5e_fp_hw_modify)(struct mlx5e_priv *priv);
840 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
841 struct mlx5e_channels *new_chs,
842 mlx5e_fp_hw_modify hw_modify);
843 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
844 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
846 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
848 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params,
850 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
852 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params);
853 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
854 struct mlx5e_params *params);
856 static inline bool mlx5e_tunnel_inner_ft_supported(struct mlx5_core_dev *mdev)
858 return (MLX5_CAP_ETH(mdev, tunnel_stateless_gre) &&
859 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ft_field_support.inner_ip_version));
862 static inline void mlx5e_sq_fetch_wqe(struct mlx5e_txqsq *sq,
863 struct mlx5e_tx_wqe **wqe,
866 struct mlx5_wq_cyc *wq = &sq->wq;
868 *pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
869 *wqe = mlx5_wq_cyc_get_wqe(wq, *pi);
870 memset(*wqe, 0, sizeof(**wqe));
874 struct mlx5e_tx_wqe *mlx5e_post_nop(struct mlx5_wq_cyc *wq, u32 sqn, u16 *pc)
876 u16 pi = mlx5_wq_cyc_ctr2ix(wq, *pc);
877 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
878 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
880 memset(cseg, 0, sizeof(*cseg));
882 cseg->opmod_idx_opcode = cpu_to_be32((*pc << 8) | MLX5_OPCODE_NOP);
883 cseg->qpn_ds = cpu_to_be32((sqn << 8) | 0x01);
891 void mlx5e_notify_hw(struct mlx5_wq_cyc *wq, u16 pc,
892 void __iomem *uar_map,
893 struct mlx5_wqe_ctrl_seg *ctrl)
895 ctrl->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
896 /* ensure wqe is visible to device before updating doorbell record */
899 *wq->db = cpu_to_be32(pc);
901 /* ensure doorbell record is visible to device before ringing the
906 mlx5_write64((__be32 *)ctrl, uar_map, NULL);
909 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
911 struct mlx5_core_cq *mcq;
914 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc);
917 extern const struct ethtool_ops mlx5e_ethtool_ops;
918 #ifdef CONFIG_MLX5_CORE_EN_DCB
919 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
920 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
921 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv);
922 void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv);
923 void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv);
926 int mlx5e_create_tir(struct mlx5_core_dev *mdev,
927 struct mlx5e_tir *tir, u32 *in, int inlen);
928 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
929 struct mlx5e_tir *tir);
930 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
931 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
932 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb);
934 /* common netdev helpers */
935 void mlx5e_create_q_counters(struct mlx5e_priv *priv);
936 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv);
937 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
938 struct mlx5e_rq *drop_rq);
939 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq);
941 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv);
943 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc);
944 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc);
946 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv);
947 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv);
948 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv);
949 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv);
950 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
952 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
953 u32 underlay_qpn, u32 *tisn);
954 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
956 int mlx5e_create_tises(struct mlx5e_priv *priv);
957 void mlx5e_update_carrier(struct mlx5e_priv *priv);
958 int mlx5e_close(struct net_device *netdev);
959 int mlx5e_open(struct net_device *netdev);
960 void mlx5e_update_ndo_stats(struct mlx5e_priv *priv);
962 void mlx5e_queue_update_stats(struct mlx5e_priv *priv);
963 int mlx5e_bits_invert(unsigned long a, int size);
965 typedef int (*change_hw_mtu_cb)(struct mlx5e_priv *priv);
966 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv);
967 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
968 change_hw_mtu_cb set_mtu_cb);
970 /* ethtool helpers */
971 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
972 struct ethtool_drvinfo *drvinfo);
973 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
974 uint32_t stringset, uint8_t *data);
975 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
976 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
977 struct ethtool_stats *stats, u64 *data);
978 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
979 struct ethtool_ringparam *param);
980 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
981 struct ethtool_ringparam *param);
982 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
983 struct ethtool_channels *ch);
984 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
985 struct ethtool_channels *ch);
986 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
987 struct ethtool_coalesce *coal);
988 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
989 struct ethtool_coalesce *coal);
990 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
991 struct ethtool_link_ksettings *link_ksettings);
992 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
993 const struct ethtool_link_ksettings *link_ksettings);
994 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv);
995 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv);
996 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
997 struct ethtool_ts_info *info);
998 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
999 struct ethtool_flash *flash);
1000 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1001 struct ethtool_pauseparam *pauseparam);
1002 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1003 struct ethtool_pauseparam *pauseparam);
1005 /* mlx5e generic netdev management API */
1006 int mlx5e_netdev_init(struct net_device *netdev,
1007 struct mlx5e_priv *priv,
1008 struct mlx5_core_dev *mdev,
1009 const struct mlx5e_profile *profile,
1011 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv);
1013 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile,
1014 int nch, void *ppriv);
1015 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1016 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1017 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
1018 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
1019 struct mlx5e_rss_params *rss_params,
1020 struct mlx5e_params *params,
1021 u16 max_channels, u16 mtu);
1022 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
1023 struct mlx5e_params *params);
1024 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
1026 u8 mlx5e_params_calculate_tx_min_inline(struct mlx5_core_dev *mdev);
1027 void mlx5e_rx_dim_work(struct work_struct *work);
1028 void mlx5e_tx_dim_work(struct work_struct *work);
1030 void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti);
1031 void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti);
1032 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
1033 struct net_device *netdev,
1034 netdev_features_t features);
1035 #ifdef CONFIG_MLX5_ESWITCH
1036 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
1037 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate);
1038 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi);
1039 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats);
1041 #endif /* __MLX5_EN_H__ */