drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <net/geneve.h>
  38 #include <linux/bpf.h>
  39 #include <linux/if_bridge.h>
  40 #include <net/page_pool.h>
  41 #include <net/xdp_sock.h>
  42 #include "eswitch.h"
  43 #include "en.h"
  44 #include "en/txrx.h"
  45 #include "en_tc.h"
  46 #include "en_rep.h"
  47 #include "en_accel/ipsec.h"
  48 #include "en_accel/ipsec_rxtx.h"
  49 #include "en_accel/en_accel.h"
  50 #include "en_accel/tls.h"
  51 #include "accel/ipsec.h"
  52 #include "accel/tls.h"
  53 #include "lib/vxlan.h"
  54 #include "lib/clock.h"
  55 #include "en/port.h"
  56 #include "en/xdp.h"
  57 #include "lib/eq.h"
  58 #include "en/monitor_stats.h"
  59 #include "en/health.h"
  60 #include "en/params.h"
  61 #include "en/xsk/umem.h"
  62 #include "en/xsk/setup.h"
  63 #include "en/xsk/rx.h"
  64 #include "en/xsk/tx.h"
  65 #include "en/hv_vhca_stats.h"
  66 #include "lib/mlx5.h"
  67
  68
  69 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  70 {
  71         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  72                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  73                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  74         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  75         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  76
  77         if (!striding_rq_umr)
  78                 return false;
  79         if (!inline_umr) {
  80                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  81                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  82                 return false;
  83         }
  84         return true;
  85 }
  86
  87 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
  88                                struct mlx5e_params *params)
  89 {
  90         params->log_rq_mtu_frames = is_kdump_kernel() ?
  91                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
  92                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
  93
  94         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
  95                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
  96                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
  97                        BIT(mlx5e_mpwqe_get_log_rq_size(params, NULL)) :
  98                        BIT(params->log_rq_mtu_frames),
  99                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL)),
 100                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 101 }
 102
 103 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 104                                 struct mlx5e_params *params)
 105 {
 106         if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
 107                 return false;
 108
 109         if (MLX5_IPSEC_DEV(mdev))
 110                 return false;
 111
 112         if (params->xdp_prog) {
 113                 /* XSK params are not considered here. If striding RQ is in use,
 114                  * and an XSK is being opened, mlx5e_rx_mpwqe_is_linear_skb will
 115                  * be called with the known XSK params.
 116                  */
 117                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
 118                         return false;
 119         }
 120
 121         return true;
 122 }
 123
 124 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 125 {
 126         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 127                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 128                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 129                 MLX5_WQ_TYPE_CYCLIC;
 130 }
 131
 132 void mlx5e_update_carrier(struct mlx5e_priv *priv)
 133 {
 134         struct mlx5_core_dev *mdev = priv->mdev;
 135         u8 port_state;
 136
 137         port_state = mlx5_query_vport_state(mdev,
 138                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
 139                                             0);
 140
 141         if (port_state == VPORT_STATE_UP) {
 142                 netdev_info(priv->netdev, "Link up\n");
 143                 netif_carrier_on(priv->netdev);
 144         } else {
 145                 netdev_info(priv->netdev, "Link down\n");
 146                 netif_carrier_off(priv->netdev);
 147         }
 148 }
 149
 150 static void mlx5e_update_carrier_work(struct work_struct *work)
 151 {
 152         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 153                                                update_carrier_work);
 154
 155         mutex_lock(&priv->state_lock);
 156         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 157                 if (priv->profile->update_carrier)
 158                         priv->profile->update_carrier(priv);
 159         mutex_unlock(&priv->state_lock);
 160 }
 161
 162 void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 163 {
 164         int i;
 165
 166         for (i = mlx5e_nic_stats_grps_num(priv) - 1; i >= 0; i--)
 167                 if (mlx5e_nic_stats_grps[i]->update_stats_mask &
 168                     MLX5E_NDO_UPDATE_STATS)
 169                         mlx5e_nic_stats_grps[i]->update_stats(priv);
 170 }
 171
 172 static void mlx5e_update_stats_work(struct work_struct *work)
 173 {
 174         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 175                                                update_stats_work);
 176
 177         mutex_lock(&priv->state_lock);
 178         priv->profile->update_stats(priv);
 179         mutex_unlock(&priv->state_lock);
 180 }
 181
 182 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 183 {
 184         if (!priv->profile->update_stats)
 185                 return;
 186
 187         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 188                 return;
 189
 190         queue_work(priv->wq, &priv->update_stats_work);
 191 }
 192
 193 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 194 {
 195         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 196         struct mlx5_eqe   *eqe = data;
 197
 198         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 199                 return NOTIFY_DONE;
 200
 201         switch (eqe->sub_type) {
 202         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 203         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 204                 queue_work(priv->wq, &priv->update_carrier_work);
 205                 break;
 206         default:
 207                 return NOTIFY_DONE;
 208         }
 209
 210         return NOTIFY_OK;
 211 }
 212
 213 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 214 {
 215         priv->events_nb.notifier_call = async_event;
 216         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 217 }
 218
 219 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 220 {
 221         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 222 }
 223
 224 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 225                                        struct mlx5e_icosq *sq,
 226                                        struct mlx5e_umr_wqe *wqe)
 227 {
 228         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 229         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 230         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 231
 232         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 233                                       ds_cnt);
 234         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 235         cseg->imm       = rq->mkey_be;
 236
 237         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 238         ucseg->xlt_octowords =
 239                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 240         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 241 }
 242
 243 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 244                                      struct mlx5e_channel *c)
 245 {
 246         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 247
 248         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 249                                                   sizeof(*rq->mpwqe.info)),
 250                                        GFP_KERNEL, cpu_to_node(c->cpu));
 251         if (!rq->mpwqe.info)
 252                 return -ENOMEM;
 253
 254         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
 255
 256         return 0;
 257 }
 258
 259 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 260                                  u64 npages, u8 page_shift,
 261                                  struct mlx5_core_mkey *umr_mkey)
 262 {
 263         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 264         void *mkc;
 265         u32 *in;
 266         int err;
 267
 268         in = kvzalloc(inlen, GFP_KERNEL);
 269         if (!in)
 270                 return -ENOMEM;
 271
 272         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 273
 274         MLX5_SET(mkc, mkc, free, 1);
 275         MLX5_SET(mkc, mkc, umr_en, 1);
 276         MLX5_SET(mkc, mkc, lw, 1);
 277         MLX5_SET(mkc, mkc, lr, 1);
 278         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 279
 280         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 281         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 282         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 283         MLX5_SET(mkc, mkc, translations_octword_size,
 284                  MLX5_MTT_OCTW(npages));
 285         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 286
 287         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 288
 289         kvfree(in);
 290         return err;
 291 }
 292
 293 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 294 {
 295         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 296
 297         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 298 }
 299
 300 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 301 {
 302         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
 303 }
 304
 305 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 306 {
 307         struct mlx5e_wqe_frag_info next_frag = {};
 308         struct mlx5e_wqe_frag_info *prev = NULL;
 309         int i;
 310
 311         next_frag.di = &rq->wqe.di[0];
 312
 313         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 314                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 315                 struct mlx5e_wqe_frag_info *frag =
 316                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 317                 int f;
 318
 319                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 320                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 321                                 next_frag.di++;
 322                                 next_frag.offset = 0;
 323                                 if (prev)
 324                                         prev->last_in_page = true;
 325                         }
 326                         *frag = next_frag;
 327
 328                         /* prepare next */
 329                         next_frag.offset += frag_info[f].frag_stride;
 330                         prev = frag;
 331                 }
 332         }
 333
 334         if (prev)
 335                 prev->last_in_page = true;
 336 }
 337
 338 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
 339                               int wq_sz, int cpu)
 340 {
 341         int len = wq_sz << rq->wqe.info.log_num_frags;
 342
 343         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
 344                                    GFP_KERNEL, cpu_to_node(cpu));
 345         if (!rq->wqe.di)
 346                 return -ENOMEM;
 347
 348         mlx5e_init_frags_partition(rq);
 349
 350         return 0;
 351 }
 352
 353 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
 354 {
 355         kvfree(rq->wqe.di);
 356 }
 357
 358 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work)
 359 {
 360         struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work);
 361
 362         mlx5e_reporter_rq_cqe_err(rq);
 363 }
 364
 365 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 366                           struct mlx5e_params *params,
 367                           struct mlx5e_xsk_param *xsk,
 368                           struct xdp_umem *umem,
 369                           struct mlx5e_rq_param *rqp,
 370                           struct mlx5e_rq *rq)
 371 {
 372         struct page_pool_params pp_params = { 0 };
 373         struct mlx5_core_dev *mdev = c->mdev;
 374         void *rqc = rqp->rqc;
 375         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 376         u32 num_xsk_frames = 0;
 377         u32 rq_xdp_ix;
 378         u32 pool_size;
 379         int wq_sz;
 380         int err;
 381         int i;
 382
 383         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 384
 385         rq->wq_type = params->rq_wq_type;
 386         rq->pdev    = c->pdev;
 387         rq->netdev  = c->netdev;
 388         rq->tstamp  = c->tstamp;
 389         rq->clock   = &mdev->clock;
 390         rq->channel = c;
 391         rq->ix      = c->ix;
 392         rq->mdev    = mdev;
 393         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 394         rq->xdpsq   = &c->rq_xdpsq;
 395         rq->umem    = umem;
 396
 397         if (rq->umem)
 398                 rq->stats = &c->priv->channel_stats[c->ix].xskrq;
 399         else
 400                 rq->stats = &c->priv->channel_stats[c->ix].rq;
 401         INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work);
 402
 403         if (params->xdp_prog)
 404                 bpf_prog_inc(params->xdp_prog);
 405         rq->xdp_prog = params->xdp_prog;
 406
 407         rq_xdp_ix = rq->ix;
 408         if (xsk)
 409                 rq_xdp_ix += params->num_channels * MLX5E_RQ_GROUP_XSK;
 410         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq_xdp_ix);
 411         if (err < 0)
 412                 goto err_rq_wq_destroy;
 413
 414         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 415         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk);
 416         rq->buff.umem_headroom = xsk ? xsk->headroom : 0;
 417         pool_size = 1 << params->log_rq_mtu_frames;
 418
 419         switch (rq->wq_type) {
 420         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 421                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 422                                         &rq->wq_ctrl);
 423                 if (err)
 424                         return err;
 425
 426                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 427
 428                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 429
 430                 if (xsk)
 431                         num_xsk_frames = wq_sz <<
 432                                 mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk);
 433
 434                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE <<
 435                         mlx5e_mpwqe_get_log_rq_size(params, xsk);
 436
 437                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 438                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 439
 440                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 441 #ifdef CONFIG_MLX5_EN_IPSEC
 442                 if (MLX5_IPSEC_DEV(mdev)) {
 443                         err = -EINVAL;
 444                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 445                         goto err_rq_wq_destroy;
 446                 }
 447 #endif
 448                 if (!rq->handle_rx_cqe) {
 449                         err = -EINVAL;
 450                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 451                         goto err_rq_wq_destroy;
 452                 }
 453
 454                 rq->mpwqe.skb_from_cqe_mpwrq = xsk ?
 455                         mlx5e_xsk_skb_from_cqe_mpwrq_linear :
 456                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ?
 457                                 mlx5e_skb_from_cqe_mpwrq_linear :
 458                                 mlx5e_skb_from_cqe_mpwrq_nonlinear;
 459
 460                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk);
 461                 rq->mpwqe.num_strides =
 462                         BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk));
 463
 464                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 465                 if (err)
 466                         goto err_rq_wq_destroy;
 467                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 468
 469                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 470                 if (err)
 471                         goto err_free;
 472                 break;
 473         default: /* MLX5_WQ_TYPE_CYCLIC */
 474                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 475                                          &rq->wq_ctrl);
 476                 if (err)
 477                         return err;
 478
 479                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 480
 481                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 482
 483                 if (xsk)
 484                         num_xsk_frames = wq_sz << rq->wqe.info.log_num_frags;
 485
 486                 rq->wqe.info = rqp->frags_info;
 487                 rq->wqe.frags =
 488                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 489                                         (wq_sz << rq->wqe.info.log_num_frags)),
 490                                       GFP_KERNEL, cpu_to_node(c->cpu));
 491                 if (!rq->wqe.frags) {
 492                         err = -ENOMEM;
 493                         goto err_free;
 494                 }
 495
 496                 err = mlx5e_init_di_list(rq, wq_sz, c->cpu);
 497                 if (err)
 498                         goto err_free;
 499
 500                 rq->post_wqes = mlx5e_post_rx_wqes;
 501                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 502
 503 #ifdef CONFIG_MLX5_EN_IPSEC
 504                 if (c->priv->ipsec)
 505                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 506                 else
 507 #endif
 508                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 509                 if (!rq->handle_rx_cqe) {
 510                         err = -EINVAL;
 511                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 512                         goto err_free;
 513                 }
 514
 515                 rq->wqe.skb_from_cqe = xsk ?
 516                         mlx5e_xsk_skb_from_cqe_linear :
 517                         mlx5e_rx_is_linear_skb(params, NULL) ?
 518                                 mlx5e_skb_from_cqe_linear :
 519                                 mlx5e_skb_from_cqe_nonlinear;
 520                 rq->mkey_be = c->mkey_be;
 521         }
 522
 523         if (xsk) {
 524                 err = mlx5e_xsk_resize_reuseq(umem, num_xsk_frames);
 525                 if (unlikely(err)) {
 526                         mlx5_core_err(mdev, "Unable to allocate the Reuse Ring for %u frames\n",
 527                                       num_xsk_frames);
 528                         goto err_free;
 529                 }
 530
 531                 rq->zca.free = mlx5e_xsk_zca_free;
 532                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 533                                                  MEM_TYPE_ZERO_COPY,
 534                                                  &rq->zca);
 535         } else {
 536                 /* Create a page_pool and register it with rxq */
 537                 pp_params.order     = 0;
 538                 pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 539                 pp_params.pool_size = pool_size;
 540                 pp_params.nid       = cpu_to_node(c->cpu);
 541                 pp_params.dev       = c->pdev;
 542                 pp_params.dma_dir   = rq->buff.map_dir;
 543
 544                 /* page_pool can be used even when there is no rq->xdp_prog,
 545                  * given page_pool does not handle DMA mapping there is no
 546                  * required state to clear. And page_pool gracefully handle
 547                  * elevated refcnt.
 548                  */
 549                 rq->page_pool = page_pool_create(&pp_params);
 550                 if (IS_ERR(rq->page_pool)) {
 551                         err = PTR_ERR(rq->page_pool);
 552                         rq->page_pool = NULL;
 553                         goto err_free;
 554                 }
 555                 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 556                                                  MEM_TYPE_PAGE_POOL, rq->page_pool);
 557         }
 558         if (err)
 559                 goto err_free;
 560
 561         for (i = 0; i < wq_sz; i++) {
 562                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 563                         struct mlx5e_rx_wqe_ll *wqe =
 564                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 565                         u32 byte_count =
 566                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 567                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
 568
 569                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 570                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 571                         wqe->data[0].lkey = rq->mkey_be;
 572                 } else {
 573                         struct mlx5e_rx_wqe_cyc *wqe =
 574                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 575                         int f;
 576
 577                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 578                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 579                                         MLX5_HW_START_PADDING;
 580
 581                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 582                                 wqe->data[f].lkey = rq->mkey_be;
 583                         }
 584                         /* check if num_frags is not a pow of two */
 585                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 586                                 wqe->data[f].byte_count = 0;
 587                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 588                                 wqe->data[f].addr = 0;
 589                         }
 590                 }
 591         }
 592
 593         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 594
 595         switch (params->rx_cq_moderation.cq_period_mode) {
 596         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 597                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 598                 break;
 599         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 600         default:
 601                 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 602         }
 603
 604         rq->page_cache.head = 0;
 605         rq->page_cache.tail = 0;
 606
 607         return 0;
 608
 609 err_free:
 610         switch (rq->wq_type) {
 611         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 612                 kvfree(rq->mpwqe.info);
 613                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 614                 break;
 615         default: /* MLX5_WQ_TYPE_CYCLIC */
 616                 kvfree(rq->wqe.frags);
 617                 mlx5e_free_di_list(rq);
 618         }
 619
 620 err_rq_wq_destroy:
 621         if (rq->xdp_prog)
 622                 bpf_prog_put(rq->xdp_prog);
 623         xdp_rxq_info_unreg(&rq->xdp_rxq);
 624         page_pool_destroy(rq->page_pool);
 625         mlx5_wq_destroy(&rq->wq_ctrl);
 626
 627         return err;
 628 }
 629
 630 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 631 {
 632         int i;
 633
 634         if (rq->xdp_prog)
 635                 bpf_prog_put(rq->xdp_prog);
 636
 637         switch (rq->wq_type) {
 638         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 639                 kvfree(rq->mpwqe.info);
 640                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 641                 break;
 642         default: /* MLX5_WQ_TYPE_CYCLIC */
 643                 kvfree(rq->wqe.frags);
 644                 mlx5e_free_di_list(rq);
 645         }
 646
 647         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 648              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 649                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 650
 651                 /* With AF_XDP, page_cache is not used, so this loop is not
 652                  * entered, and it's safe to call mlx5e_page_release_dynamic
 653                  * directly.
 654                  */
 655                 mlx5e_page_release_dynamic(rq, dma_info, false);
 656         }
 657
 658         xdp_rxq_info_unreg(&rq->xdp_rxq);
 659         page_pool_destroy(rq->page_pool);
 660         mlx5_wq_destroy(&rq->wq_ctrl);
 661 }
 662
 663 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 664                            struct mlx5e_rq_param *param)
 665 {
 666         struct mlx5_core_dev *mdev = rq->mdev;
 667
 668         void *in;
 669         void *rqc;
 670         void *wq;
 671         int inlen;
 672         int err;
 673
 674         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 675                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 676         in = kvzalloc(inlen, GFP_KERNEL);
 677         if (!in)
 678                 return -ENOMEM;
 679
 680         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 681         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 682
 683         memcpy(rqc, param->rqc, sizeof(param->rqc));
 684
 685         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 686         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 687         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 688                                                 MLX5_ADAPTER_PAGE_SHIFT);
 689         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 690
 691         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 692                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 693
 694         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 695
 696         kvfree(in);
 697
 698         return err;
 699 }
 700
 701 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state)
 702 {
 703         struct mlx5_core_dev *mdev = rq->mdev;
 704
 705         void *in;
 706         void *rqc;
 707         int inlen;
 708         int err;
 709
 710         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 711         in = kvzalloc(inlen, GFP_KERNEL);
 712         if (!in)
 713                 return -ENOMEM;
 714
 715         if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY)
 716                 mlx5e_rqwq_reset(rq);
 717
 718         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 719
 720         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 721         MLX5_SET(rqc, rqc, state, next_state);
 722
 723         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 724
 725         kvfree(in);
 726
 727         return err;
 728 }
 729
 730 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 731 {
 732         struct mlx5e_channel *c = rq->channel;
 733         struct mlx5e_priv *priv = c->priv;
 734         struct mlx5_core_dev *mdev = priv->mdev;
 735
 736         void *in;
 737         void *rqc;
 738         int inlen;
 739         int err;
 740
 741         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 742         in = kvzalloc(inlen, GFP_KERNEL);
 743         if (!in)
 744                 return -ENOMEM;
 745
 746         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 747
 748         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 749         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 750                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 751         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 752         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 753
 754         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 755
 756         kvfree(in);
 757
 758         return err;
 759 }
 760
 761 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 762 {
 763         struct mlx5e_channel *c = rq->channel;
 764         struct mlx5_core_dev *mdev = c->mdev;
 765         void *in;
 766         void *rqc;
 767         int inlen;
 768         int err;
 769
 770         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 771         in = kvzalloc(inlen, GFP_KERNEL);
 772         if (!in)
 773                 return -ENOMEM;
 774
 775         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 776
 777         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 778         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 779                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 780         MLX5_SET(rqc, rqc, vsd, vsd);
 781         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 782
 783         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 784
 785         kvfree(in);
 786
 787         return err;
 788 }
 789
 790 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 791 {
 792         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 793 }
 794
 795 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 796 {
 797         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 798         struct mlx5e_channel *c = rq->channel;
 799
 800         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 801
 802         do {
 803                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 804                         return 0;
 805
 806                 msleep(20);
 807         } while (time_before(jiffies, exp_time));
 808
 809         netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 810                     c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 811
 812         mlx5e_reporter_rx_timeout(rq);
 813         return -ETIMEDOUT;
 814 }
 815
 816 void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 817 {
 818         __be16 wqe_ix_be;
 819         u16 wqe_ix;
 820
 821         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 822                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 823                 u16 head = wq->head;
 824                 int i;
 825
 826                 /* Outstanding UMR WQEs (in progress) start at wq->head */
 827                 for (i = 0; i < rq->mpwqe.umr_in_progress; i++) {
 828                         rq->dealloc_wqe(rq, head);
 829                         head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 830                 }
 831
 832                 while (!mlx5_wq_ll_is_empty(wq)) {
 833                         struct mlx5e_rx_wqe_ll *wqe;
 834
 835                         wqe_ix_be = *wq->tail_next;
 836                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 837                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 838                         rq->dealloc_wqe(rq, wqe_ix);
 839                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 840                                        &wqe->next.next_wqe_index);
 841                 }
 842         } else {
 843                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 844
 845                 while (!mlx5_wq_cyc_is_empty(wq)) {
 846                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 847                         rq->dealloc_wqe(rq, wqe_ix);
 848                         mlx5_wq_cyc_pop(wq);
 849                 }
 850         }
 851
 852 }
 853
 854 int mlx5e_open_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
 855                   struct mlx5e_rq_param *param, struct mlx5e_xsk_param *xsk,
 856                   struct xdp_umem *umem, struct mlx5e_rq *rq)
 857 {
 858         int err;
 859
 860         err = mlx5e_alloc_rq(c, params, xsk, umem, param, rq);
 861         if (err)
 862                 return err;
 863
 864         err = mlx5e_create_rq(rq, param);
 865         if (err)
 866                 goto err_free_rq;
 867
 868         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 869         if (err)
 870                 goto err_destroy_rq;
 871
 872         if (MLX5_CAP_ETH(c->mdev, cqe_checksum_full))
 873                 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &c->rq.state);
 874
 875         if (params->rx_dim_enabled)
 876                 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 877
 878         /* We disable csum_complete when XDP is enabled since
 879          * XDP programs might manipulate packets which will render
 880          * skb->checksum incorrect.
 881          */
 882         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || c->xdp)
 883                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
 884
 885         return 0;
 886
 887 err_destroy_rq:
 888         mlx5e_destroy_rq(rq);
 889 err_free_rq:
 890         mlx5e_free_rq(rq);
 891
 892         return err;
 893 }
 894
 895 void mlx5e_activate_rq(struct mlx5e_rq *rq)
 896 {
 897         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 898         mlx5e_trigger_irq(&rq->channel->icosq);
 899 }
 900
 901 void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 902 {
 903         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 904         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 905 }
 906
 907 void mlx5e_close_rq(struct mlx5e_rq *rq)
 908 {
 909         cancel_work_sync(&rq->dim.work);
 910         cancel_work_sync(&rq->channel->icosq.recover_work);
 911         cancel_work_sync(&rq->recover_work);
 912         mlx5e_destroy_rq(rq);
 913         mlx5e_free_rx_descs(rq);
 914         mlx5e_free_rq(rq);
 915 }
 916
 917 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 918 {
 919         kvfree(sq->db.xdpi_fifo.xi);
 920         kvfree(sq->db.wqe_info);
 921 }
 922
 923 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
 924 {
 925         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
 926         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
 927         int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 928
 929         xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
 930                                       GFP_KERNEL, numa);
 931         if (!xdpi_fifo->xi)
 932                 return -ENOMEM;
 933
 934         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
 935         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
 936         xdpi_fifo->mask = dsegs_per_wq - 1;
 937
 938         return 0;
 939 }
 940
 941 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 942 {
 943         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 944         int err;
 945
 946         sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
 947                                         GFP_KERNEL, numa);
 948         if (!sq->db.wqe_info)
 949                 return -ENOMEM;
 950
 951         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
 952         if (err) {
 953                 mlx5e_free_xdpsq_db(sq);
 954                 return err;
 955         }
 956
 957         return 0;
 958 }
 959
 960 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
 961                              struct mlx5e_params *params,
 962                              struct xdp_umem *umem,
 963                              struct mlx5e_sq_param *param,
 964                              struct mlx5e_xdpsq *sq,
 965                              bool is_redirect)
 966 {
 967         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
 968         struct mlx5_core_dev *mdev = c->mdev;
 969         struct mlx5_wq_cyc *wq = &sq->wq;
 970         int err;
 971
 972         sq->pdev      = c->pdev;
 973         sq->mkey_be   = c->mkey_be;
 974         sq->channel   = c;
 975         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
 976         sq->min_inline_mode = params->tx_min_inline_mode;
 977         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 978         sq->umem      = umem;
 979
 980         sq->stats = sq->umem ?
 981                 &c->priv->channel_stats[c->ix].xsksq :
 982                 is_redirect ?
 983                         &c->priv->channel_stats[c->ix].xdpsq :
 984                         &c->priv->channel_stats[c->ix].rq_xdpsq;
 985
 986         param->wq.db_numa_node = cpu_to_node(c->cpu);
 987         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
 988         if (err)
 989                 return err;
 990         wq->db = &wq->db[MLX5_SND_DBR];
 991
 992         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
 993         if (err)
 994                 goto err_sq_wq_destroy;
 995
 996         return 0;
 997
 998 err_sq_wq_destroy:
 999         mlx5_wq_destroy(&sq->wq_ctrl);
1000
1001         return err;
1002 }
1003
1004 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1005 {
1006         mlx5e_free_xdpsq_db(sq);
1007         mlx5_wq_destroy(&sq->wq_ctrl);
1008 }
1009
1010 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1011 {
1012         kvfree(sq->db.ico_wqe);
1013 }
1014
1015 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1016 {
1017         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1018
1019         sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
1020                                                   sizeof(*sq->db.ico_wqe)),
1021                                        GFP_KERNEL, numa);
1022         if (!sq->db.ico_wqe)
1023                 return -ENOMEM;
1024
1025         return 0;
1026 }
1027
1028 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work)
1029 {
1030         struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq,
1031                                               recover_work);
1032
1033         mlx5e_reporter_icosq_cqe_err(sq);
1034 }
1035
1036 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1037                              struct mlx5e_sq_param *param,
1038                              struct mlx5e_icosq *sq)
1039 {
1040         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1041         struct mlx5_core_dev *mdev = c->mdev;
1042         struct mlx5_wq_cyc *wq = &sq->wq;
1043         int err;
1044
1045         sq->channel   = c;
1046         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1047
1048         param->wq.db_numa_node = cpu_to_node(c->cpu);
1049         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1050         if (err)
1051                 return err;
1052         wq->db = &wq->db[MLX5_SND_DBR];
1053
1054         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1055         if (err)
1056                 goto err_sq_wq_destroy;
1057
1058         INIT_WORK(&sq->recover_work, mlx5e_icosq_err_cqe_work);
1059
1060         return 0;
1061
1062 err_sq_wq_destroy:
1063         mlx5_wq_destroy(&sq->wq_ctrl);
1064
1065         return err;
1066 }
1067
1068 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1069 {
1070         mlx5e_free_icosq_db(sq);
1071         mlx5_wq_destroy(&sq->wq_ctrl);
1072 }
1073
1074 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1075 {
1076         kvfree(sq->db.wqe_info);
1077         kvfree(sq->db.dma_fifo);
1078 }
1079
1080 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1081 {
1082         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1083         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1084
1085         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1086                                                    sizeof(*sq->db.dma_fifo)),
1087                                         GFP_KERNEL, numa);
1088         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1089                                                    sizeof(*sq->db.wqe_info)),
1090                                         GFP_KERNEL, numa);
1091         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1092                 mlx5e_free_txqsq_db(sq);
1093                 return -ENOMEM;
1094         }
1095
1096         sq->dma_fifo_mask = df_sz - 1;
1097
1098         return 0;
1099 }
1100
1101 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1102 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1103                              int txq_ix,
1104                              struct mlx5e_params *params,
1105                              struct mlx5e_sq_param *param,
1106                              struct mlx5e_txqsq *sq,
1107                              int tc)
1108 {
1109         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1110         struct mlx5_core_dev *mdev = c->mdev;
1111         struct mlx5_wq_cyc *wq = &sq->wq;
1112         int err;
1113
1114         sq->pdev      = c->pdev;
1115         sq->tstamp    = c->tstamp;
1116         sq->clock     = &mdev->clock;
1117         sq->mkey_be   = c->mkey_be;
1118         sq->channel   = c;
1119         sq->ch_ix     = c->ix;
1120         sq->txq_ix    = txq_ix;
1121         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1122         sq->min_inline_mode = params->tx_min_inline_mode;
1123         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1124         sq->stats     = &c->priv->channel_stats[c->ix].sq[tc];
1125         sq->stop_room = MLX5E_SQ_STOP_ROOM;
1126         INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1127         if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
1128                 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
1129         if (MLX5_IPSEC_DEV(c->priv->mdev))
1130                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1131 #ifdef CONFIG_MLX5_EN_TLS
1132         if (mlx5_accel_is_tls_device(c->priv->mdev)) {
1133                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1134                 sq->stop_room += MLX5E_SQ_TLS_ROOM +
1135                         mlx5e_ktls_dumps_num_wqebbs(sq, MAX_SKB_FRAGS,
1136                                                     TLS_MAX_PAYLOAD_SIZE);
1137         }
1138 #endif
1139
1140         param->wq.db_numa_node = cpu_to_node(c->cpu);
1141         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1142         if (err)
1143                 return err;
1144         wq->db    = &wq->db[MLX5_SND_DBR];
1145
1146         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1147         if (err)
1148                 goto err_sq_wq_destroy;
1149
1150         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1151         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1152
1153         return 0;
1154
1155 err_sq_wq_destroy:
1156         mlx5_wq_destroy(&sq->wq_ctrl);
1157
1158         return err;
1159 }
1160
1161 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1162 {
1163         mlx5e_free_txqsq_db(sq);
1164         mlx5_wq_destroy(&sq->wq_ctrl);
1165 }
1166
1167 struct mlx5e_create_sq_param {
1168         struct mlx5_wq_ctrl        *wq_ctrl;
1169         u32                         cqn;
1170         u32                         tisn;
1171         u8                          tis_lst_sz;
1172         u8                          min_inline_mode;
1173 };
1174
1175 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1176                            struct mlx5e_sq_param *param,
1177                            struct mlx5e_create_sq_param *csp,
1178                            u32 *sqn)
1179 {
1180         void *in;
1181         void *sqc;
1182         void *wq;
1183         int inlen;
1184         int err;
1185
1186         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1187                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1188         in = kvzalloc(inlen, GFP_KERNEL);
1189         if (!in)
1190                 return -ENOMEM;
1191
1192         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1193         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1194
1195         memcpy(sqc, param->sqc, sizeof(param->sqc));
1196         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1197         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1198         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1199
1200         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1201                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1202
1203         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1204         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1205
1206         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1207         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1208         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1209                                           MLX5_ADAPTER_PAGE_SHIFT);
1210         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1211
1212         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1213                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1214
1215         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1216
1217         kvfree(in);
1218
1219         return err;
1220 }
1221
1222 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1223                     struct mlx5e_modify_sq_param *p)
1224 {
1225         void *in;
1226         void *sqc;
1227         int inlen;
1228         int err;
1229
1230         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1231         in = kvzalloc(inlen, GFP_KERNEL);
1232         if (!in)
1233                 return -ENOMEM;
1234
1235         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1236
1237         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1238         MLX5_SET(sqc, sqc, state, p->next_state);
1239         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1240                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1241                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1242         }
1243
1244         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1245
1246         kvfree(in);
1247
1248         return err;
1249 }
1250
1251 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1252 {
1253         mlx5_core_destroy_sq(mdev, sqn);
1254 }
1255
1256 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1257                                struct mlx5e_sq_param *param,
1258                                struct mlx5e_create_sq_param *csp,
1259                                u32 *sqn)
1260 {
1261         struct mlx5e_modify_sq_param msp = {0};
1262         int err;
1263
1264         err = mlx5e_create_sq(mdev, param, csp, sqn);
1265         if (err)
1266                 return err;
1267
1268         msp.curr_state = MLX5_SQC_STATE_RST;
1269         msp.next_state = MLX5_SQC_STATE_RDY;
1270         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1271         if (err)
1272                 mlx5e_destroy_sq(mdev, *sqn);
1273
1274         return err;
1275 }
1276
1277 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1278                                 struct mlx5e_txqsq *sq, u32 rate);
1279
1280 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1281                             u32 tisn,
1282                             int txq_ix,
1283                             struct mlx5e_params *params,
1284                             struct mlx5e_sq_param *param,
1285                             struct mlx5e_txqsq *sq,
1286                             int tc)
1287 {
1288         struct mlx5e_create_sq_param csp = {};
1289         u32 tx_rate;
1290         int err;
1291
1292         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1293         if (err)
1294                 return err;
1295
1296         csp.tisn            = tisn;
1297         csp.tis_lst_sz      = 1;
1298         csp.cqn             = sq->cq.mcq.cqn;
1299         csp.wq_ctrl         = &sq->wq_ctrl;
1300         csp.min_inline_mode = sq->min_inline_mode;
1301         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1302         if (err)
1303                 goto err_free_txqsq;
1304
1305         tx_rate = c->priv->tx_rates[sq->txq_ix];
1306         if (tx_rate)
1307                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1308
1309         if (params->tx_dim_enabled)
1310                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1311
1312         return 0;
1313
1314 err_free_txqsq:
1315         mlx5e_free_txqsq(sq);
1316
1317         return err;
1318 }
1319
1320 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1321 {
1322         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1323         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1324         netdev_tx_reset_queue(sq->txq);
1325         netif_tx_start_queue(sq->txq);
1326 }
1327
1328 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1329 {
1330         __netif_tx_lock_bh(txq);
1331         netif_tx_stop_queue(txq);
1332         __netif_tx_unlock_bh(txq);
1333 }
1334
1335 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1336 {
1337         struct mlx5e_channel *c = sq->channel;
1338         struct mlx5_wq_cyc *wq = &sq->wq;
1339
1340         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1341         /* prevent netif_tx_wake_queue */
1342         napi_synchronize(&c->napi);
1343
1344         mlx5e_tx_disable_queue(sq->txq);
1345
1346         /* last doorbell out, godspeed .. */
1347         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1348                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1349                 struct mlx5e_tx_wqe_info *wi;
1350                 struct mlx5e_tx_wqe *nop;
1351
1352                 wi = &sq->db.wqe_info[pi];
1353
1354                 memset(wi, 0, sizeof(*wi));
1355                 wi->num_wqebbs = 1;
1356                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1357                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1358         }
1359 }
1360
1361 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1362 {
1363         struct mlx5e_channel *c = sq->channel;
1364         struct mlx5_core_dev *mdev = c->mdev;
1365         struct mlx5_rate_limit rl = {0};
1366
1367         cancel_work_sync(&sq->dim.work);
1368         cancel_work_sync(&sq->recover_work);
1369         mlx5e_destroy_sq(mdev, sq->sqn);
1370         if (sq->rate_limit) {
1371                 rl.rate = sq->rate_limit;
1372                 mlx5_rl_remove_rate(mdev, &rl);
1373         }
1374         mlx5e_free_txqsq_descs(sq);
1375         mlx5e_free_txqsq(sq);
1376 }
1377
1378 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1379 {
1380         struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1381                                               recover_work);
1382
1383         mlx5e_reporter_tx_err_cqe(sq);
1384 }
1385
1386 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1387                      struct mlx5e_sq_param *param, struct mlx5e_icosq *sq)
1388 {
1389         struct mlx5e_create_sq_param csp = {};
1390         int err;
1391
1392         err = mlx5e_alloc_icosq(c, param, sq);
1393         if (err)
1394                 return err;
1395
1396         csp.cqn             = sq->cq.mcq.cqn;
1397         csp.wq_ctrl         = &sq->wq_ctrl;
1398         csp.min_inline_mode = params->tx_min_inline_mode;
1399         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1400         if (err)
1401                 goto err_free_icosq;
1402
1403         return 0;
1404
1405 err_free_icosq:
1406         mlx5e_free_icosq(sq);
1407
1408         return err;
1409 }
1410
1411 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq)
1412 {
1413         set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1414 }
1415
1416 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq)
1417 {
1418         struct mlx5e_channel *c = icosq->channel;
1419
1420         clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state);
1421         napi_synchronize(&c->napi);
1422 }
1423
1424 void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1425 {
1426         struct mlx5e_channel *c = sq->channel;
1427
1428         mlx5e_destroy_sq(c->mdev, sq->sqn);
1429         mlx5e_free_icosq(sq);
1430 }
1431
1432 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1433                      struct mlx5e_sq_param *param, struct xdp_umem *umem,
1434                      struct mlx5e_xdpsq *sq, bool is_redirect)
1435 {
1436         struct mlx5e_create_sq_param csp = {};
1437         int err;
1438
1439         err = mlx5e_alloc_xdpsq(c, params, umem, param, sq, is_redirect);
1440         if (err)
1441                 return err;
1442
1443         csp.tis_lst_sz      = 1;
1444         csp.tisn            = c->priv->tisn[c->lag_port][0]; /* tc = 0 */
1445         csp.cqn             = sq->cq.mcq.cqn;
1446         csp.wq_ctrl         = &sq->wq_ctrl;
1447         csp.min_inline_mode = sq->min_inline_mode;
1448         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1449         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1450         if (err)
1451                 goto err_free_xdpsq;
1452
1453         mlx5e_set_xmit_fp(sq, param->is_mpw);
1454
1455         if (!param->is_mpw) {
1456                 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1457                 unsigned int inline_hdr_sz = 0;
1458                 int i;
1459
1460                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1461                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1462                         ds_cnt++;
1463                 }
1464
1465                 /* Pre initialize fixed WQE fields */
1466                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1467                         struct mlx5e_xdp_wqe_info *wi  = &sq->db.wqe_info[i];
1468                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1469                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1470                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1471                         struct mlx5_wqe_data_seg *dseg;
1472
1473                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1474                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1475
1476                         dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1477                         dseg->lkey = sq->mkey_be;
1478
1479                         wi->num_wqebbs = 1;
1480                         wi->num_pkts   = 1;
1481                 }
1482         }
1483
1484         return 0;
1485
1486 err_free_xdpsq:
1487         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1488         mlx5e_free_xdpsq(sq);
1489
1490         return err;
1491 }
1492
1493 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1494 {
1495         struct mlx5e_channel *c = sq->channel;
1496
1497         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1498         napi_synchronize(&c->napi);
1499
1500         mlx5e_destroy_sq(c->mdev, sq->sqn);
1501         mlx5e_free_xdpsq_descs(sq);
1502         mlx5e_free_xdpsq(sq);
1503 }
1504
1505 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1506                                  struct mlx5e_cq_param *param,
1507                                  struct mlx5e_cq *cq)
1508 {
1509         struct mlx5_core_cq *mcq = &cq->mcq;
1510         int eqn_not_used;
1511         unsigned int irqn;
1512         int err;
1513         u32 i;
1514
1515         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1516         if (err)
1517                 return err;
1518
1519         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1520                                &cq->wq_ctrl);
1521         if (err)
1522                 return err;
1523
1524         mcq->cqe_sz     = 64;
1525         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1526         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1527         *mcq->set_ci_db = 0;
1528         *mcq->arm_db    = 0;
1529         mcq->vector     = param->eq_ix;
1530         mcq->comp       = mlx5e_completion_event;
1531         mcq->event      = mlx5e_cq_error_event;
1532         mcq->irqn       = irqn;
1533
1534         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1535                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1536
1537                 cqe->op_own = 0xf1;
1538         }
1539
1540         cq->mdev = mdev;
1541
1542         return 0;
1543 }
1544
1545 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1546                           struct mlx5e_cq_param *param,
1547                           struct mlx5e_cq *cq)
1548 {
1549         struct mlx5_core_dev *mdev = c->priv->mdev;
1550         int err;
1551
1552         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1553         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1554         param->eq_ix   = c->ix;
1555
1556         err = mlx5e_alloc_cq_common(mdev, param, cq);
1557
1558         cq->napi    = &c->napi;
1559         cq->channel = c;
1560
1561         return err;
1562 }
1563
1564 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1565 {
1566         mlx5_wq_destroy(&cq->wq_ctrl);
1567 }
1568
1569 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1570 {
1571         u32 out[MLX5_ST_SZ_DW(create_cq_out)];
1572         struct mlx5_core_dev *mdev = cq->mdev;
1573         struct mlx5_core_cq *mcq = &cq->mcq;
1574
1575         void *in;
1576         void *cqc;
1577         int inlen;
1578         unsigned int irqn_not_used;
1579         int eqn;
1580         int err;
1581
1582         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1583         if (err)
1584                 return err;
1585
1586         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1587                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1588         in = kvzalloc(inlen, GFP_KERNEL);
1589         if (!in)
1590                 return -ENOMEM;
1591
1592         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1593
1594         memcpy(cqc, param->cqc, sizeof(param->cqc));
1595
1596         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1597                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1598
1599         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1600         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1601         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1602         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1603                                             MLX5_ADAPTER_PAGE_SHIFT);
1604         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1605
1606         err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out));
1607
1608         kvfree(in);
1609
1610         if (err)
1611                 return err;
1612
1613         mlx5e_cq_arm(cq);
1614
1615         return 0;
1616 }
1617
1618 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1619 {
1620         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1621 }
1622
1623 int mlx5e_open_cq(struct mlx5e_channel *c, struct dim_cq_moder moder,
1624                   struct mlx5e_cq_param *param, struct mlx5e_cq *cq)
1625 {
1626         struct mlx5_core_dev *mdev = c->mdev;
1627         int err;
1628
1629         err = mlx5e_alloc_cq(c, param, cq);
1630         if (err)
1631                 return err;
1632
1633         err = mlx5e_create_cq(cq, param);
1634         if (err)
1635                 goto err_free_cq;
1636
1637         if (MLX5_CAP_GEN(mdev, cq_moderation))
1638                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1639         return 0;
1640
1641 err_free_cq:
1642         mlx5e_free_cq(cq);
1643
1644         return err;
1645 }
1646
1647 void mlx5e_close_cq(struct mlx5e_cq *cq)
1648 {
1649         mlx5e_destroy_cq(cq);
1650         mlx5e_free_cq(cq);
1651 }
1652
1653 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1654                              struct mlx5e_params *params,
1655                              struct mlx5e_channel_param *cparam)
1656 {
1657         int err;
1658         int tc;
1659
1660         for (tc = 0; tc < c->num_tc; tc++) {
1661                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1662                                     &cparam->tx_cq, &c->sq[tc].cq);
1663                 if (err)
1664                         goto err_close_tx_cqs;
1665         }
1666
1667         return 0;
1668
1669 err_close_tx_cqs:
1670         for (tc--; tc >= 0; tc--)
1671                 mlx5e_close_cq(&c->sq[tc].cq);
1672
1673         return err;
1674 }
1675
1676 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1677 {
1678         int tc;
1679
1680         for (tc = 0; tc < c->num_tc; tc++)
1681                 mlx5e_close_cq(&c->sq[tc].cq);
1682 }
1683
1684 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1685                           struct mlx5e_params *params,
1686                           struct mlx5e_channel_param *cparam)
1687 {
1688         int err, tc;
1689
1690         for (tc = 0; tc < params->num_tc; tc++) {
1691                 int txq_ix = c->ix + tc * params->num_channels;
1692
1693                 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,
1694                                        params, &cparam->sq, &c->sq[tc], tc);
1695                 if (err)
1696                         goto err_close_sqs;
1697         }
1698
1699         return 0;
1700
1701 err_close_sqs:
1702         for (tc--; tc >= 0; tc--)
1703                 mlx5e_close_txqsq(&c->sq[tc]);
1704
1705         return err;
1706 }
1707
1708 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1709 {
1710         int tc;
1711
1712         for (tc = 0; tc < c->num_tc; tc++)
1713                 mlx5e_close_txqsq(&c->sq[tc]);
1714 }
1715
1716 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1717                                 struct mlx5e_txqsq *sq, u32 rate)
1718 {
1719         struct mlx5e_priv *priv = netdev_priv(dev);
1720         struct mlx5_core_dev *mdev = priv->mdev;
1721         struct mlx5e_modify_sq_param msp = {0};
1722         struct mlx5_rate_limit rl = {0};
1723         u16 rl_index = 0;
1724         int err;
1725
1726         if (rate == sq->rate_limit)
1727                 /* nothing to do */
1728                 return 0;
1729
1730         if (sq->rate_limit) {
1731                 rl.rate = sq->rate_limit;
1732                 /* remove current rl index to free space to next ones */
1733                 mlx5_rl_remove_rate(mdev, &rl);
1734         }
1735
1736         sq->rate_limit = 0;
1737
1738         if (rate) {
1739                 rl.rate = rate;
1740                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1741                 if (err) {
1742                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1743                                    rate, err);
1744                         return err;
1745                 }
1746         }
1747
1748         msp.curr_state = MLX5_SQC_STATE_RDY;
1749         msp.next_state = MLX5_SQC_STATE_RDY;
1750         msp.rl_index   = rl_index;
1751         msp.rl_update  = true;
1752         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1753         if (err) {
1754                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1755                            rate, err);
1756                 /* remove the rate from the table */
1757                 if (rate)
1758                         mlx5_rl_remove_rate(mdev, &rl);
1759                 return err;
1760         }
1761
1762         sq->rate_limit = rate;
1763         return 0;
1764 }
1765
1766 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1767 {
1768         struct mlx5e_priv *priv = netdev_priv(dev);
1769         struct mlx5_core_dev *mdev = priv->mdev;
1770         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1771         int err = 0;
1772
1773         if (!mlx5_rl_is_supported(mdev)) {
1774                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1775                 return -EINVAL;
1776         }
1777
1778         /* rate is given in Mb/sec, HW config is in Kb/sec */
1779         rate = rate << 10;
1780
1781         /* Check whether rate in valid range, 0 is always valid */
1782         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1783                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1784                 return -ERANGE;
1785         }
1786
1787         mutex_lock(&priv->state_lock);
1788         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1789                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1790         if (!err)
1791                 priv->tx_rates[index] = rate;
1792         mutex_unlock(&priv->state_lock);
1793
1794         return err;
1795 }
1796
1797 static int mlx5e_alloc_xps_cpumask(struct mlx5e_channel *c,
1798                                    struct mlx5e_params *params)
1799 {
1800         int num_comp_vectors = mlx5_comp_vectors_count(c->mdev);
1801         int irq;
1802
1803         if (!zalloc_cpumask_var(&c->xps_cpumask, GFP_KERNEL))
1804                 return -ENOMEM;
1805
1806         for (irq = c->ix; irq < num_comp_vectors; irq += params->num_channels) {
1807                 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(c->mdev, irq));
1808
1809                 cpumask_set_cpu(cpu, c->xps_cpumask);
1810         }
1811
1812         return 0;
1813 }
1814
1815 static void mlx5e_free_xps_cpumask(struct mlx5e_channel *c)
1816 {
1817         free_cpumask_var(c->xps_cpumask);
1818 }
1819
1820 static int mlx5e_open_queues(struct mlx5e_channel *c,
1821                              struct mlx5e_params *params,
1822                              struct mlx5e_channel_param *cparam)
1823 {
1824         struct dim_cq_moder icocq_moder = {0, 0};
1825         int err;
1826
1827         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1828         if (err)
1829                 return err;
1830
1831         err = mlx5e_open_tx_cqs(c, params, cparam);
1832         if (err)
1833                 goto err_close_icosq_cq;
1834
1835         err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
1836         if (err)
1837                 goto err_close_tx_cqs;
1838
1839         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1840         if (err)
1841                 goto err_close_xdp_tx_cqs;
1842
1843         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1844         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1845                                      &cparam->tx_cq, &c->rq_xdpsq.cq) : 0;
1846         if (err)
1847                 goto err_close_rx_cq;
1848
1849         napi_enable(&c->napi);
1850
1851         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1852         if (err)
1853                 goto err_disable_napi;
1854
1855         err = mlx5e_open_sqs(c, params, cparam);
1856         if (err)
1857                 goto err_close_icosq;
1858
1859         if (c->xdp) {
1860                 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL,
1861                                        &c->rq_xdpsq, false);
1862                 if (err)
1863                         goto err_close_sqs;
1864         }
1865
1866         err = mlx5e_open_rq(c, params, &cparam->rq, NULL, NULL, &c->rq);
1867         if (err)
1868                 goto err_close_xdp_sq;
1869
1870         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true);
1871         if (err)
1872                 goto err_close_rq;
1873
1874         return 0;
1875
1876 err_close_rq:
1877         mlx5e_close_rq(&c->rq);
1878
1879 err_close_xdp_sq:
1880         if (c->xdp)
1881                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1882
1883 err_close_sqs:
1884         mlx5e_close_sqs(c);
1885
1886 err_close_icosq:
1887         mlx5e_close_icosq(&c->icosq);
1888
1889 err_disable_napi:
1890         napi_disable(&c->napi);
1891
1892         if (c->xdp)
1893                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1894
1895 err_close_rx_cq:
1896         mlx5e_close_cq(&c->rq.cq);
1897
1898 err_close_xdp_tx_cqs:
1899         mlx5e_close_cq(&c->xdpsq.cq);
1900
1901 err_close_tx_cqs:
1902         mlx5e_close_tx_cqs(c);
1903
1904 err_close_icosq_cq:
1905         mlx5e_close_cq(&c->icosq.cq);
1906
1907         return err;
1908 }
1909
1910 static void mlx5e_close_queues(struct mlx5e_channel *c)
1911 {
1912         mlx5e_close_xdpsq(&c->xdpsq);
1913         mlx5e_close_rq(&c->rq);
1914         if (c->xdp)
1915                 mlx5e_close_xdpsq(&c->rq_xdpsq);
1916         mlx5e_close_sqs(c);
1917         mlx5e_close_icosq(&c->icosq);
1918         napi_disable(&c->napi);
1919         if (c->xdp)
1920                 mlx5e_close_cq(&c->rq_xdpsq.cq);
1921         mlx5e_close_cq(&c->rq.cq);
1922         mlx5e_close_cq(&c->xdpsq.cq);
1923         mlx5e_close_tx_cqs(c);
1924         mlx5e_close_cq(&c->icosq.cq);
1925 }
1926
1927 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix)
1928 {
1929         u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id);
1930
1931         return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev);
1932 }
1933
1934 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1935                               struct mlx5e_params *params,
1936                               struct mlx5e_channel_param *cparam,
1937                               struct xdp_umem *umem,
1938                               struct mlx5e_channel **cp)
1939 {
1940         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1941         struct net_device *netdev = priv->netdev;
1942         struct mlx5e_xsk_param xsk;
1943         struct mlx5e_channel *c;
1944         unsigned int irq;
1945         int err;
1946         int eqn;
1947
1948         err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1949         if (err)
1950                 return err;
1951
1952         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1953         if (!c)
1954                 return -ENOMEM;
1955
1956         c->priv     = priv;
1957         c->mdev     = priv->mdev;
1958         c->tstamp   = &priv->tstamp;
1959         c->ix       = ix;
1960         c->cpu      = cpu;
1961         c->pdev     = priv->mdev->device;
1962         c->netdev   = priv->netdev;
1963         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1964         c->num_tc   = params->num_tc;
1965         c->xdp      = !!params->xdp_prog;
1966         c->stats    = &priv->channel_stats[ix].ch;
1967         c->irq_desc = irq_to_desc(irq);
1968         c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix);
1969
1970         err = mlx5e_alloc_xps_cpumask(c, params);
1971         if (err)
1972                 goto err_free_channel;
1973
1974         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1975
1976         err = mlx5e_open_queues(c, params, cparam);
1977         if (unlikely(err))
1978                 goto err_napi_del;
1979
1980         if (umem) {
1981                 mlx5e_build_xsk_param(umem, &xsk);
1982                 err = mlx5e_open_xsk(priv, params, &xsk, umem, c);
1983                 if (unlikely(err))
1984                         goto err_close_queues;
1985         }
1986
1987         *cp = c;
1988
1989         return 0;
1990
1991 err_close_queues:
1992         mlx5e_close_queues(c);
1993
1994 err_napi_del:
1995         netif_napi_del(&c->napi);
1996         mlx5e_free_xps_cpumask(c);
1997
1998 err_free_channel:
1999         kvfree(c);
2000
2001         return err;
2002 }
2003
2004 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2005 {
2006         int tc;
2007
2008         for (tc = 0; tc < c->num_tc; tc++)
2009                 mlx5e_activate_txqsq(&c->sq[tc]);
2010         mlx5e_activate_icosq(&c->icosq);
2011         mlx5e_activate_rq(&c->rq);
2012         netif_set_xps_queue(c->netdev, c->xps_cpumask, c->ix);
2013
2014         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2015                 mlx5e_activate_xsk(c);
2016 }
2017
2018 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2019 {
2020         int tc;
2021
2022         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2023                 mlx5e_deactivate_xsk(c);
2024
2025         mlx5e_deactivate_rq(&c->rq);
2026         mlx5e_deactivate_icosq(&c->icosq);
2027         for (tc = 0; tc < c->num_tc; tc++)
2028                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2029 }
2030
2031 static void mlx5e_close_channel(struct mlx5e_channel *c)
2032 {
2033         if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state))
2034                 mlx5e_close_xsk(c);
2035         mlx5e_close_queues(c);
2036         netif_napi_del(&c->napi);
2037         mlx5e_free_xps_cpumask(c);
2038
2039         kvfree(c);
2040 }
2041
2042 #define DEFAULT_FRAG_SIZE (2048)
2043
2044 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2045                                       struct mlx5e_params *params,
2046                                       struct mlx5e_xsk_param *xsk,
2047                                       struct mlx5e_rq_frags_info *info)
2048 {
2049         u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2050         int frag_size_max = DEFAULT_FRAG_SIZE;
2051         u32 buf_size = 0;
2052         int i;
2053
2054 #ifdef CONFIG_MLX5_EN_IPSEC
2055         if (MLX5_IPSEC_DEV(mdev))
2056                 byte_count += MLX5E_METADATA_ETHER_LEN;
2057 #endif
2058
2059         if (mlx5e_rx_is_linear_skb(params, xsk)) {
2060                 int frag_stride;
2061
2062                 frag_stride = mlx5e_rx_get_linear_frag_sz(params, xsk);
2063                 frag_stride = roundup_pow_of_two(frag_stride);
2064
2065                 info->arr[0].frag_size = byte_count;
2066                 info->arr[0].frag_stride = frag_stride;
2067                 info->num_frags = 1;
2068                 info->wqe_bulk = PAGE_SIZE / frag_stride;
2069                 goto out;
2070         }
2071
2072         if (byte_count > PAGE_SIZE +
2073             (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2074                 frag_size_max = PAGE_SIZE;
2075
2076         i = 0;
2077         while (buf_size < byte_count) {
2078                 int frag_size = byte_count - buf_size;
2079
2080                 if (i < MLX5E_MAX_RX_FRAGS - 1)
2081                         frag_size = min(frag_size, frag_size_max);
2082
2083                 info->arr[i].frag_size = frag_size;
2084                 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2085
2086                 buf_size += frag_size;
2087                 i++;
2088         }
2089         info->num_frags = i;
2090         /* number of different wqes sharing a page */
2091         info->wqe_bulk = 1 + (info->num_frags % 2);
2092
2093 out:
2094         info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2095         info->log_num_frags = order_base_2(info->num_frags);
2096 }
2097
2098 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2099 {
2100         int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2101
2102         switch (wq_type) {
2103         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2104                 sz += sizeof(struct mlx5e_rx_wqe_ll);
2105                 break;
2106         default: /* MLX5_WQ_TYPE_CYCLIC */
2107                 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2108         }
2109
2110         return order_base_2(sz);
2111 }
2112
2113 static u8 mlx5e_get_rq_log_wq_sz(void *rqc)
2114 {
2115         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2116
2117         return MLX5_GET(wq, wq, log_wq_sz);
2118 }
2119
2120 void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2121                           struct mlx5e_params *params,
2122                           struct mlx5e_xsk_param *xsk,
2123                           struct mlx5e_rq_param *param)
2124 {
2125         struct mlx5_core_dev *mdev = priv->mdev;
2126         void *rqc = param->rqc;
2127         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2128         int ndsegs = 1;
2129
2130         switch (params->rq_wq_type) {
2131         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2132                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2133                          mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk) -
2134                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2135                 MLX5_SET(wq, wq, log_wqe_stride_size,
2136                          mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk) -
2137                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2138                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params, xsk));
2139                 break;
2140         default: /* MLX5_WQ_TYPE_CYCLIC */
2141                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2142                 mlx5e_build_rq_frags_info(mdev, params, xsk, &param->frags_info);
2143                 ndsegs = param->frags_info.num_frags;
2144         }
2145
2146         MLX5_SET(wq, wq, wq_type,          params->rq_wq_type);
2147         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2148         MLX5_SET(wq, wq, log_wq_stride,
2149                  mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2150         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
2151         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2152         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
2153         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
2154
2155         param->wq.buf_numa_node = dev_to_node(mdev->device);
2156 }
2157
2158 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2159                                       struct mlx5e_rq_param *param)
2160 {
2161         struct mlx5_core_dev *mdev = priv->mdev;
2162         void *rqc = param->rqc;
2163         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2164
2165         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2166         MLX5_SET(wq, wq, log_wq_stride,
2167                  mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2168         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2169
2170         param->wq.buf_numa_node = dev_to_node(mdev->device);
2171 }
2172
2173 void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2174                                  struct mlx5e_sq_param *param)
2175 {
2176         void *sqc = param->sqc;
2177         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2178
2179         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2180         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
2181
2182         param->wq.buf_numa_node = dev_to_node(priv->mdev->device);
2183 }
2184
2185 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2186                                  struct mlx5e_params *params,
2187                                  struct mlx5e_sq_param *param)
2188 {
2189         void *sqc = param->sqc;
2190         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2191         bool allow_swp;
2192
2193         allow_swp = mlx5_geneve_tx_allowed(priv->mdev) ||
2194                     !!MLX5_IPSEC_DEV(priv->mdev);
2195         mlx5e_build_sq_param_common(priv, param);
2196         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2197         MLX5_SET(sqc, sqc, allow_swp, allow_swp);
2198 }
2199
2200 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2201                                         struct mlx5e_cq_param *param)
2202 {
2203         void *cqc = param->cqc;
2204
2205         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2206         if (MLX5_CAP_GEN(priv->mdev, cqe_128_always) && cache_line_size() >= 128)
2207                 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD);
2208 }
2209
2210 void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2211                              struct mlx5e_params *params,
2212                              struct mlx5e_xsk_param *xsk,
2213                              struct mlx5e_cq_param *param)
2214 {
2215         struct mlx5_core_dev *mdev = priv->mdev;
2216         void *cqc = param->cqc;
2217         u8 log_cq_size;
2218
2219         switch (params->rq_wq_type) {
2220         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2221                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params, xsk) +
2222                         mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk);
2223                 break;
2224         default: /* MLX5_WQ_TYPE_CYCLIC */
2225                 log_cq_size = params->log_rq_mtu_frames;
2226         }
2227
2228         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2229         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2230                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2231                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2232         }
2233
2234         mlx5e_build_common_cq_param(priv, param);
2235         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2236 }
2237
2238 void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2239                              struct mlx5e_params *params,
2240                              struct mlx5e_cq_param *param)
2241 {
2242         void *cqc = param->cqc;
2243
2244         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2245
2246         mlx5e_build_common_cq_param(priv, param);
2247         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2248 }
2249
2250 void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2251                               u8 log_wq_size,
2252                               struct mlx5e_cq_param *param)
2253 {
2254         void *cqc = param->cqc;
2255
2256         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2257
2258         mlx5e_build_common_cq_param(priv, param);
2259
2260         param->cq_period_mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2261 }
2262
2263 void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2264                              u8 log_wq_size,
2265                              struct mlx5e_sq_param *param)
2266 {
2267         void *sqc = param->sqc;
2268         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2269
2270         mlx5e_build_sq_param_common(priv, param);
2271
2272         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2273         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2274 }
2275
2276 void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2277                              struct mlx5e_params *params,
2278                              struct mlx5e_sq_param *param)
2279 {
2280         void *sqc = param->sqc;
2281         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2282
2283         mlx5e_build_sq_param_common(priv, param);
2284         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2285         param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE);
2286 }
2287
2288 static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5e_params *params,
2289                                       struct mlx5e_rq_param *rqp)
2290 {
2291         switch (params->rq_wq_type) {
2292         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2293                 return order_base_2(MLX5E_UMR_WQEBBS) +
2294                         mlx5e_get_rq_log_wq_sz(rqp->rqc);
2295         default: /* MLX5_WQ_TYPE_CYCLIC */
2296                 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2297         }
2298 }
2299
2300 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2301                                       struct mlx5e_params *params,
2302                                       struct mlx5e_channel_param *cparam)
2303 {
2304         u8 icosq_log_wq_sz;
2305
2306         mlx5e_build_rq_param(priv, params, NULL, &cparam->rq);
2307
2308         icosq_log_wq_sz = mlx5e_build_icosq_log_wq_sz(params, &cparam->rq);
2309
2310         mlx5e_build_sq_param(priv, params, &cparam->sq);
2311         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2312         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2313         mlx5e_build_rx_cq_param(priv, params, NULL, &cparam->rx_cq);
2314         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2315         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2316 }
2317
2318 int mlx5e_open_channels(struct mlx5e_priv *priv,
2319                         struct mlx5e_channels *chs)
2320 {
2321         struct mlx5e_channel_param *cparam;
2322         int err = -ENOMEM;
2323         int i;
2324
2325         chs->num = chs->params.num_channels;
2326
2327         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2328         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2329         if (!chs->c || !cparam)
2330                 goto err_free;
2331
2332         mlx5e_build_channel_param(priv, &chs->params, cparam);
2333         for (i = 0; i < chs->num; i++) {
2334                 struct xdp_umem *umem = NULL;
2335
2336                 if (chs->params.xdp_prog)
2337                         umem = mlx5e_xsk_get_umem(&chs->params, chs->params.xsk, i);
2338
2339                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, umem, &chs->c[i]);
2340                 if (err)
2341                         goto err_close_channels;
2342         }
2343
2344         mlx5e_health_channels_update(priv);
2345         kvfree(cparam);
2346         return 0;
2347
2348 err_close_channels:
2349         for (i--; i >= 0; i--)
2350                 mlx5e_close_channel(chs->c[i]);
2351
2352 err_free:
2353         kfree(chs->c);
2354         kvfree(cparam);
2355         chs->num = 0;
2356         return err;
2357 }
2358
2359 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2360 {
2361         int i;
2362
2363         for (i = 0; i < chs->num; i++)
2364                 mlx5e_activate_channel(chs->c[i]);
2365 }
2366
2367 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */
2368
2369 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2370 {
2371         int err = 0;
2372         int i;
2373
2374         for (i = 0; i < chs->num; i++) {
2375                 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT;
2376
2377                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout);
2378
2379                 /* Don't wait on the XSK RQ, because the newer xdpsock sample
2380                  * doesn't provide any Fill Ring entries at the setup stage.
2381                  */
2382         }
2383
2384         return err ? -ETIMEDOUT : 0;
2385 }
2386
2387 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2388 {
2389         int i;
2390
2391         for (i = 0; i < chs->num; i++)
2392                 mlx5e_deactivate_channel(chs->c[i]);
2393 }
2394
2395 void mlx5e_close_channels(struct mlx5e_channels *chs)
2396 {
2397         int i;
2398
2399         for (i = 0; i < chs->num; i++)
2400                 mlx5e_close_channel(chs->c[i]);
2401
2402         kfree(chs->c);
2403         chs->num = 0;
2404 }
2405
2406 static int
2407 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2408 {
2409         struct mlx5_core_dev *mdev = priv->mdev;
2410         void *rqtc;
2411         int inlen;
2412         int err;
2413         u32 *in;
2414         int i;
2415
2416         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2417         in = kvzalloc(inlen, GFP_KERNEL);
2418         if (!in)
2419                 return -ENOMEM;
2420
2421         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2422
2423         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2424         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2425
2426         for (i = 0; i < sz; i++)
2427                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2428
2429         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2430         if (!err)
2431                 rqt->enabled = true;
2432
2433         kvfree(in);
2434         return err;
2435 }
2436
2437 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2438 {
2439         rqt->enabled = false;
2440         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2441 }
2442
2443 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2444 {
2445         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2446         int err;
2447
2448         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2449         if (err)
2450                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2451         return err;
2452 }
2453
2454 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2455 {
2456         int err;
2457         int ix;
2458
2459         for (ix = 0; ix < priv->max_nch; ix++) {
2460                 err = mlx5e_create_rqt(priv, 1 /*size */, &tirs[ix].rqt);
2461                 if (unlikely(err))
2462                         goto err_destroy_rqts;
2463         }
2464
2465         return 0;
2466
2467 err_destroy_rqts:
2468         mlx5_core_warn(priv->mdev, "create rqts failed, %d\n", err);
2469         for (ix--; ix >= 0; ix--)
2470                 mlx5e_destroy_rqt(priv, &tirs[ix].rqt);
2471
2472         return err;
2473 }
2474
2475 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
2476 {
2477         int i;
2478
2479         for (i = 0; i < priv->max_nch; i++)
2480                 mlx5e_destroy_rqt(priv, &tirs[i].rqt);
2481 }
2482
2483 static int mlx5e_rx_hash_fn(int hfunc)
2484 {
2485         return (hfunc == ETH_RSS_HASH_TOP) ?
2486                MLX5_RX_HASH_FN_TOEPLITZ :
2487                MLX5_RX_HASH_FN_INVERTED_XOR8;
2488 }
2489
2490 int mlx5e_bits_invert(unsigned long a, int size)
2491 {
2492         int inv = 0;
2493         int i;
2494
2495         for (i = 0; i < size; i++)
2496                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2497
2498         return inv;
2499 }
2500
2501 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2502                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2503 {
2504         int i;
2505
2506         for (i = 0; i < sz; i++) {
2507                 u32 rqn;
2508
2509                 if (rrp.is_rss) {
2510                         int ix = i;
2511
2512                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2513                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2514
2515                         ix = priv->rss_params.indirection_rqt[ix];
2516                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2517                 } else {
2518                         rqn = rrp.rqn;
2519                 }
2520                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2521         }
2522 }
2523
2524 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2525                        struct mlx5e_redirect_rqt_param rrp)
2526 {
2527         struct mlx5_core_dev *mdev = priv->mdev;
2528         void *rqtc;
2529         int inlen;
2530         u32 *in;
2531         int err;
2532
2533         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2534         in = kvzalloc(inlen, GFP_KERNEL);
2535         if (!in)
2536                 return -ENOMEM;
2537
2538         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2539
2540         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2541         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2542         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2543         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2544
2545         kvfree(in);
2546         return err;
2547 }
2548
2549 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2550                                 struct mlx5e_redirect_rqt_param rrp)
2551 {
2552         if (!rrp.is_rss)
2553                 return rrp.rqn;
2554
2555         if (ix >= rrp.rss.channels->num)
2556                 return priv->drop_rq.rqn;
2557
2558         return rrp.rss.channels->c[ix]->rq.rqn;
2559 }
2560
2561 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2562                                 struct mlx5e_redirect_rqt_param rrp)
2563 {
2564         u32 rqtn;
2565         int ix;
2566
2567         if (priv->indir_rqt.enabled) {
2568                 /* RSS RQ table */
2569                 rqtn = priv->indir_rqt.rqtn;
2570                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2571         }
2572
2573         for (ix = 0; ix < priv->max_nch; ix++) {
2574                 struct mlx5e_redirect_rqt_param direct_rrp = {
2575                         .is_rss = false,
2576                         {
2577                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2578                         },
2579                 };
2580
2581                 /* Direct RQ Tables */
2582                 if (!priv->direct_tir[ix].rqt.enabled)
2583                         continue;
2584
2585                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2586                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2587         }
2588 }
2589
2590 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2591                                             struct mlx5e_channels *chs)
2592 {
2593         struct mlx5e_redirect_rqt_param rrp = {
2594                 .is_rss        = true,
2595                 {
2596                         .rss = {
2597                                 .channels  = chs,
2598                                 .hfunc     = priv->rss_params.hfunc,
2599                         }
2600                 },
2601         };
2602
2603         mlx5e_redirect_rqts(priv, rrp);
2604 }
2605
2606 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2607 {
2608         struct mlx5e_redirect_rqt_param drop_rrp = {
2609                 .is_rss = false,
2610                 {
2611                         .rqn = priv->drop_rq.rqn,
2612                 },
2613         };
2614
2615         mlx5e_redirect_rqts(priv, drop_rrp);
2616 }
2617
2618 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2619         [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2620                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2621                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2622         },
2623         [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2624                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2625                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2626         },
2627         [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2628                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2629                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2630         },
2631         [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2632                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2633                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2634         },
2635         [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2636                                      .l4_prot_type = 0,
2637                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2638         },
2639         [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2640                                      .l4_prot_type = 0,
2641                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2642         },
2643         [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2644                                       .l4_prot_type = 0,
2645                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2646         },
2647         [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2648                                       .l4_prot_type = 0,
2649                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2650         },
2651         [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2652                             .l4_prot_type = 0,
2653                             .rx_hash_fields = MLX5_HASH_IP,
2654         },
2655         [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2656                             .l4_prot_type = 0,
2657                             .rx_hash_fields = MLX5_HASH_IP,
2658         },
2659 };
2660
2661 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2662 {
2663         return tirc_default_config[tt];
2664 }
2665
2666 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2667 {
2668         if (!params->lro_en)
2669                 return;
2670
2671 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2672
2673         MLX5_SET(tirc, tirc, lro_enable_mask,
2674                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2675                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2676         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2677                  (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2678         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2679 }
2680
2681 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2682                                     const struct mlx5e_tirc_config *ttconfig,
2683                                     void *tirc, bool inner)
2684 {
2685         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2686                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2687
2688         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2689         if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2690                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2691                                              rx_hash_toeplitz_key);
2692                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2693                                                rx_hash_toeplitz_key);
2694
2695                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2696                 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2697         }
2698         MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2699                  ttconfig->l3_prot_type);
2700         MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2701                  ttconfig->l4_prot_type);
2702         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2703                  ttconfig->rx_hash_fields);
2704 }
2705
2706 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2707                                         enum mlx5e_traffic_types tt,
2708                                         u32 rx_hash_fields)
2709 {
2710         *ttconfig                = tirc_default_config[tt];
2711         ttconfig->rx_hash_fields = rx_hash_fields;
2712 }
2713
2714 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
2715 {
2716         void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2717         struct mlx5e_rss_params *rss = &priv->rss_params;
2718         struct mlx5_core_dev *mdev = priv->mdev;
2719         int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2720         struct mlx5e_tirc_config ttconfig;
2721         int tt;
2722
2723         MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2724
2725         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2726                 memset(tirc, 0, ctxlen);
2727                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2728                                             rss->rx_hash_fields[tt]);
2729                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2730                 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
2731         }
2732
2733         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2734                 return;
2735
2736         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2737                 memset(tirc, 0, ctxlen);
2738                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2739                                             rss->rx_hash_fields[tt]);
2740                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2741                 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in,
2742                                      inlen);
2743         }
2744 }
2745
2746 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2747 {
2748         struct mlx5_core_dev *mdev = priv->mdev;
2749
2750         void *in;
2751         void *tirc;
2752         int inlen;
2753         int err;
2754         int tt;
2755         int ix;
2756
2757         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2758         in = kvzalloc(inlen, GFP_KERNEL);
2759         if (!in)
2760                 return -ENOMEM;
2761
2762         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2763         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2764
2765         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2766
2767         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2768                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2769                                            inlen);
2770                 if (err)
2771                         goto free_in;
2772         }
2773
2774         for (ix = 0; ix < priv->max_nch; ix++) {
2775                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2776                                            in, inlen);
2777                 if (err)
2778                         goto free_in;
2779         }
2780
2781 free_in:
2782         kvfree(in);
2783
2784         return err;
2785 }
2786
2787 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2788                          struct mlx5e_params *params, u16 mtu)
2789 {
2790         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2791         int err;
2792
2793         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2794         if (err)
2795                 return err;
2796
2797         /* Update vport context MTU */
2798         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2799         return 0;
2800 }
2801
2802 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2803                             struct mlx5e_params *params, u16 *mtu)
2804 {
2805         u16 hw_mtu = 0;
2806         int err;
2807
2808         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2809         if (err || !hw_mtu) /* fallback to port oper mtu */
2810                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2811
2812         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2813 }
2814
2815 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2816 {
2817         struct mlx5e_params *params = &priv->channels.params;
2818         struct net_device *netdev = priv->netdev;
2819         struct mlx5_core_dev *mdev = priv->mdev;
2820         u16 mtu;
2821         int err;
2822
2823         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2824         if (err)
2825                 return err;
2826
2827         mlx5e_query_mtu(mdev, params, &mtu);
2828         if (mtu != params->sw_mtu)
2829                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2830                             __func__, mtu, params->sw_mtu);
2831
2832         params->sw_mtu = mtu;
2833         return 0;
2834 }
2835
2836 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2837 {
2838         struct mlx5e_params *params = &priv->channels.params;
2839         struct net_device *netdev   = priv->netdev;
2840         struct mlx5_core_dev *mdev  = priv->mdev;
2841         u16 max_mtu;
2842
2843         /* MTU range: 68 - hw-specific max */
2844         netdev->min_mtu = ETH_MIN_MTU;
2845
2846         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2847         netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2848                                 ETH_MAX_MTU);
2849 }
2850
2851 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2852 {
2853         struct mlx5e_priv *priv = netdev_priv(netdev);
2854         int nch = priv->channels.params.num_channels;
2855         int ntc = priv->channels.params.num_tc;
2856         int tc;
2857
2858         netdev_reset_tc(netdev);
2859
2860         if (ntc == 1)
2861                 return;
2862
2863         netdev_set_num_tc(netdev, ntc);
2864
2865         /* Map netdev TCs to offset 0
2866          * We have our own UP to TXQ mapping for QoS
2867          */
2868         for (tc = 0; tc < ntc; tc++)
2869                 netdev_set_tc_queue(netdev, tc, nch, 0);
2870 }
2871
2872 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv)
2873 {
2874         int i, ch;
2875
2876         ch = priv->channels.num;
2877
2878         for (i = 0; i < ch; i++) {
2879                 int tc;
2880
2881                 for (tc = 0; tc < priv->channels.params.num_tc; tc++) {
2882                         struct mlx5e_channel *c = priv->channels.c[i];
2883                         struct mlx5e_txqsq *sq = &c->sq[tc];
2884
2885                         priv->txq2sq[sq->txq_ix] = sq;
2886                         priv->channel_tc2realtxq[i][tc] = i + tc * ch;
2887                 }
2888         }
2889 }
2890
2891 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2892 {
2893         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2894         int num_rxqs = priv->channels.num * priv->profile->rq_groups;
2895         struct net_device *netdev = priv->netdev;
2896
2897         mlx5e_netdev_set_tcs(netdev);
2898         netif_set_real_num_tx_queues(netdev, num_txqs);
2899         netif_set_real_num_rx_queues(netdev, num_rxqs);
2900
2901         mlx5e_build_txq_maps(priv);
2902         mlx5e_activate_channels(&priv->channels);
2903         mlx5e_xdp_tx_enable(priv);
2904         netif_tx_start_all_queues(priv->netdev);
2905
2906         if (mlx5e_is_vport_rep(priv))
2907                 mlx5e_add_sqs_fwd_rules(priv);
2908
2909         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2910         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2911
2912         mlx5e_xsk_redirect_rqts_to_channels(priv, &priv->channels);
2913 }
2914
2915 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2916 {
2917         mlx5e_xsk_redirect_rqts_to_drop(priv, &priv->channels);
2918
2919         mlx5e_redirect_rqts_to_drop(priv);
2920
2921         if (mlx5e_is_vport_rep(priv))
2922                 mlx5e_remove_sqs_fwd_rules(priv);
2923
2924         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2925          * polling for inactive tx queues.
2926          */
2927         netif_tx_stop_all_queues(priv->netdev);
2928         netif_tx_disable(priv->netdev);
2929         mlx5e_xdp_tx_disable(priv);
2930         mlx5e_deactivate_channels(&priv->channels);
2931 }
2932
2933 static void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2934                                        struct mlx5e_channels *new_chs,
2935                                        mlx5e_fp_hw_modify hw_modify)
2936 {
2937         struct net_device *netdev = priv->netdev;
2938         int new_num_txqs;
2939         int carrier_ok;
2940
2941         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2942
2943         carrier_ok = netif_carrier_ok(netdev);
2944         netif_carrier_off(netdev);
2945
2946         if (new_num_txqs < netdev->real_num_tx_queues)
2947                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2948
2949         mlx5e_deactivate_priv_channels(priv);
2950         mlx5e_close_channels(&priv->channels);
2951
2952         priv->channels = *new_chs;
2953
2954         /* New channels are ready to roll, modify HW settings if needed */
2955         if (hw_modify)
2956                 hw_modify(priv);
2957
2958         priv->profile->update_rx(priv);
2959         mlx5e_activate_priv_channels(priv);
2960
2961         /* return carrier back if needed */
2962         if (carrier_ok)
2963                 netif_carrier_on(netdev);
2964 }
2965
2966 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
2967                                struct mlx5e_channels *new_chs,
2968                                mlx5e_fp_hw_modify hw_modify)
2969 {
2970         int err;
2971
2972         err = mlx5e_open_channels(priv, new_chs);
2973         if (err)
2974                 return err;
2975
2976         mlx5e_switch_priv_channels(priv, new_chs, hw_modify);
2977         return 0;
2978 }
2979
2980 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
2981 {
2982         struct mlx5e_channels new_channels = {};
2983
2984         new_channels.params = priv->channels.params;
2985         return mlx5e_safe_switch_channels(priv, &new_channels, NULL);
2986 }
2987
2988 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2989 {
2990         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2991         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2992 }
2993
2994 int mlx5e_open_locked(struct net_device *netdev)
2995 {
2996         struct mlx5e_priv *priv = netdev_priv(netdev);
2997         int err;
2998
2999         set_bit(MLX5E_STATE_OPENED, &priv->state);
3000
3001         err = mlx5e_open_channels(priv, &priv->channels);
3002         if (err)
3003                 goto err_clear_state_opened_flag;
3004
3005         priv->profile->update_rx(priv);
3006         mlx5e_activate_priv_channels(priv);
3007         if (priv->profile->update_carrier)
3008                 priv->profile->update_carrier(priv);
3009
3010         mlx5e_queue_update_stats(priv);
3011         return 0;
3012
3013 err_clear_state_opened_flag:
3014         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3015         return err;
3016 }
3017
3018 int mlx5e_open(struct net_device *netdev)
3019 {
3020         struct mlx5e_priv *priv = netdev_priv(netdev);
3021         int err;
3022
3023         mutex_lock(&priv->state_lock);
3024         err = mlx5e_open_locked(netdev);
3025         if (!err)
3026                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
3027         mutex_unlock(&priv->state_lock);
3028
3029         if (mlx5_vxlan_allowed(priv->mdev->vxlan))
3030                 udp_tunnel_get_rx_info(netdev);
3031
3032         return err;
3033 }
3034
3035 int mlx5e_close_locked(struct net_device *netdev)
3036 {
3037         struct mlx5e_priv *priv = netdev_priv(netdev);
3038
3039         /* May already be CLOSED in case a previous configuration operation
3040          * (e.g RX/TX queue size change) that involves close&open failed.
3041          */
3042         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3043                 return 0;
3044
3045         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3046
3047         netif_carrier_off(priv->netdev);
3048         mlx5e_deactivate_priv_channels(priv);
3049         mlx5e_close_channels(&priv->channels);
3050
3051         return 0;
3052 }
3053
3054 int mlx5e_close(struct net_device *netdev)
3055 {
3056         struct mlx5e_priv *priv = netdev_priv(netdev);
3057         int err;
3058
3059         if (!netif_device_present(netdev))
3060                 return -ENODEV;
3061
3062         mutex_lock(&priv->state_lock);
3063         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
3064         err = mlx5e_close_locked(netdev);
3065         mutex_unlock(&priv->state_lock);
3066
3067         return err;
3068 }
3069
3070 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3071                                struct mlx5e_rq *rq,
3072                                struct mlx5e_rq_param *param)
3073 {
3074         void *rqc = param->rqc;
3075         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3076         int err;
3077
3078         param->wq.db_numa_node = param->wq.buf_numa_node;
3079
3080         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3081                                  &rq->wq_ctrl);
3082         if (err)
3083                 return err;
3084
3085         /* Mark as unused given "Drop-RQ" packets never reach XDP */
3086         xdp_rxq_info_unused(&rq->xdp_rxq);
3087
3088         rq->mdev = mdev;
3089
3090         return 0;
3091 }
3092
3093 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3094                                struct mlx5e_cq *cq,
3095                                struct mlx5e_cq_param *param)
3096 {
3097         param->wq.buf_numa_node = dev_to_node(mdev->device);
3098         param->wq.db_numa_node  = dev_to_node(mdev->device);
3099
3100         return mlx5e_alloc_cq_common(mdev, param, cq);
3101 }
3102
3103 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3104                        struct mlx5e_rq *drop_rq)
3105 {
3106         struct mlx5_core_dev *mdev = priv->mdev;
3107         struct mlx5e_cq_param cq_param = {};
3108         struct mlx5e_rq_param rq_param = {};
3109         struct mlx5e_cq *cq = &drop_rq->cq;
3110         int err;
3111
3112         mlx5e_build_drop_rq_param(priv, &rq_param);
3113
3114         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3115         if (err)
3116                 return err;
3117
3118         err = mlx5e_create_cq(cq, &cq_param);
3119         if (err)
3120                 goto err_free_cq;
3121
3122         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3123         if (err)
3124                 goto err_destroy_cq;
3125
3126         err = mlx5e_create_rq(drop_rq, &rq_param);
3127         if (err)
3128                 goto err_free_rq;
3129
3130         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3131         if (err)
3132                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3133
3134         return 0;
3135
3136 err_free_rq:
3137         mlx5e_free_rq(drop_rq);
3138
3139 err_destroy_cq:
3140         mlx5e_destroy_cq(cq);
3141
3142 err_free_cq:
3143         mlx5e_free_cq(cq);
3144
3145         return err;
3146 }
3147
3148 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3149 {
3150         mlx5e_destroy_rq(drop_rq);
3151         mlx5e_free_rq(drop_rq);
3152         mlx5e_destroy_cq(&drop_rq->cq);
3153         mlx5e_free_cq(&drop_rq->cq);
3154 }
3155
3156 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
3157 {
3158         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3159
3160         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3161
3162         if (MLX5_GET(tisc, tisc, tls_en))
3163                 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.pdn);
3164
3165         if (mlx5_lag_is_lacp_owner(mdev))
3166                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3167
3168         return mlx5_core_create_tis(mdev, in, MLX5_ST_SZ_BYTES(create_tis_in), tisn);
3169 }
3170
3171 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3172 {
3173         mlx5_core_destroy_tis(mdev, tisn);
3174 }
3175
3176 void mlx5e_destroy_tises(struct mlx5e_priv *priv)
3177 {
3178         int tc, i;
3179
3180         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++)
3181                 for (tc = 0; tc < priv->profile->max_tc; tc++)
3182                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3183 }
3184
3185 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
3186 {
3187         return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
3188 }
3189
3190 int mlx5e_create_tises(struct mlx5e_priv *priv)
3191 {
3192         int tc, i;
3193         int err;
3194
3195         for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) {
3196                 for (tc = 0; tc < priv->profile->max_tc; tc++) {
3197                         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
3198                         void *tisc;
3199
3200                         tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3201
3202                         MLX5_SET(tisc, tisc, prio, tc << 1);
3203
3204                         if (mlx5e_lag_should_assign_affinity(priv->mdev))
3205                                 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
3206
3207                         err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]);
3208                         if (err)
3209                                 goto err_close_tises;
3210                 }
3211         }
3212
3213         return 0;
3214
3215 err_close_tises:
3216         for (; i >= 0; i--) {
3217                 for (tc--; tc >= 0; tc--)
3218                         mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]);
3219                 tc = priv->profile->max_tc;
3220         }
3221
3222         return err;
3223 }
3224
3225 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3226 {
3227         mlx5e_destroy_tises(priv);
3228 }
3229
3230 static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv,
3231                                              u32 rqtn, u32 *tirc)
3232 {
3233         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3234         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3235         MLX5_SET(tirc, tirc, indirect_table, rqtn);
3236         MLX5_SET(tirc, tirc, tunneled_offload_en,
3237                  priv->channels.params.tunneled_offload_en);
3238
3239         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3240 }
3241
3242 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3243                                       enum mlx5e_traffic_types tt,
3244                                       u32 *tirc)
3245 {
3246         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3247         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3248                                        &tirc_default_config[tt], tirc, false);
3249 }
3250
3251 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3252 {
3253         mlx5e_build_indir_tir_ctx_common(priv, rqtn, tirc);
3254         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3255 }
3256
3257 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
3258                                             enum mlx5e_traffic_types tt,
3259                                             u32 *tirc)
3260 {
3261         mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
3262         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3263                                        &tirc_default_config[tt], tirc, true);
3264 }
3265
3266 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3267 {
3268         struct mlx5e_tir *tir;
3269         void *tirc;
3270         int inlen;
3271         int i = 0;
3272         int err;
3273         u32 *in;
3274         int tt;
3275
3276         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3277         in = kvzalloc(inlen, GFP_KERNEL);
3278         if (!in)
3279                 return -ENOMEM;
3280
3281         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3282                 memset(in, 0, inlen);
3283                 tir = &priv->indir_tir[tt];
3284                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3285                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3286                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3287                 if (err) {
3288                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3289                         goto err_destroy_inner_tirs;
3290                 }
3291         }
3292
3293         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3294                 goto out;
3295
3296         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3297                 memset(in, 0, inlen);
3298                 tir = &priv->inner_indir_tir[i];
3299                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3300                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3301                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3302                 if (err) {
3303                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3304                         goto err_destroy_inner_tirs;
3305                 }
3306         }
3307
3308 out:
3309         kvfree(in);
3310
3311         return 0;
3312
3313 err_destroy_inner_tirs:
3314         for (i--; i >= 0; i--)
3315                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3316
3317         for (tt--; tt >= 0; tt--)
3318                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3319
3320         kvfree(in);
3321
3322         return err;
3323 }
3324
3325 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3326 {
3327         struct mlx5e_tir *tir;
3328         void *tirc;
3329         int inlen;
3330         int err = 0;
3331         u32 *in;
3332         int ix;
3333
3334         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3335         in = kvzalloc(inlen, GFP_KERNEL);
3336         if (!in)
3337                 return -ENOMEM;
3338
3339         for (ix = 0; ix < priv->max_nch; ix++) {
3340                 memset(in, 0, inlen);
3341                 tir = &tirs[ix];
3342                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3343                 mlx5e_build_direct_tir_ctx(priv, tir->rqt.rqtn, tirc);
3344                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3345                 if (unlikely(err))
3346                         goto err_destroy_ch_tirs;
3347         }
3348
3349         goto out;
3350
3351 err_destroy_ch_tirs:
3352         mlx5_core_warn(priv->mdev, "create tirs failed, %d\n", err);
3353         for (ix--; ix >= 0; ix--)
3354                 mlx5e_destroy_tir(priv->mdev, &tirs[ix]);
3355
3356 out:
3357         kvfree(in);
3358
3359         return err;
3360 }
3361
3362 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3363 {
3364         int i;
3365
3366         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3367                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3368
3369         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3370                 return;
3371
3372         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3373                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3374 }
3375
3376 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs)
3377 {
3378         int i;
3379
3380         for (i = 0; i < priv->max_nch; i++)
3381                 mlx5e_destroy_tir(priv->mdev, &tirs[i]);
3382 }
3383
3384 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3385 {
3386         int err = 0;
3387         int i;
3388
3389         for (i = 0; i < chs->num; i++) {
3390                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3391                 if (err)
3392                         return err;
3393         }
3394
3395         return 0;
3396 }
3397
3398 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3399 {
3400         int err = 0;
3401         int i;
3402
3403         for (i = 0; i < chs->num; i++) {
3404                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3405                 if (err)
3406                         return err;
3407         }
3408
3409         return 0;
3410 }
3411
3412 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv,
3413                                  struct tc_mqprio_qopt *mqprio)
3414 {
3415         struct mlx5e_channels new_channels = {};
3416         u8 tc = mqprio->num_tc;
3417         int err = 0;
3418
3419         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3420
3421         if (tc && tc != MLX5E_MAX_NUM_TC)
3422                 return -EINVAL;
3423
3424         mutex_lock(&priv->state_lock);
3425
3426         new_channels.params = priv->channels.params;
3427         new_channels.params.num_tc = tc ? tc : 1;
3428
3429         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3430                 priv->channels.params = new_channels.params;
3431                 goto out;
3432         }
3433
3434         err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
3435         if (err)
3436                 goto out;
3437
3438         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3439                                     new_channels.params.num_tc);
3440 out:
3441         mutex_unlock(&priv->state_lock);
3442         return err;
3443 }
3444
3445 #ifdef CONFIG_MLX5_ESWITCH
3446 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3447                                      struct flow_cls_offload *cls_flower,
3448                                      unsigned long flags)
3449 {
3450         switch (cls_flower->command) {
3451         case FLOW_CLS_REPLACE:
3452                 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
3453                                               flags);
3454         case FLOW_CLS_DESTROY:
3455                 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
3456                                            flags);
3457         case FLOW_CLS_STATS:
3458                 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
3459                                           flags);
3460         default:
3461                 return -EOPNOTSUPP;
3462         }
3463 }
3464
3465 static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3466                                    void *cb_priv)
3467 {
3468         unsigned long flags = MLX5_TC_FLAG(INGRESS) | MLX5_TC_FLAG(NIC_OFFLOAD);
3469         struct mlx5e_priv *priv = cb_priv;
3470
3471         switch (type) {
3472         case TC_SETUP_CLSFLOWER:
3473                 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
3474         default:
3475                 return -EOPNOTSUPP;
3476         }
3477 }
3478 #endif
3479
3480 static LIST_HEAD(mlx5e_block_cb_list);
3481
3482 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3483                           void *type_data)
3484 {
3485         struct mlx5e_priv *priv = netdev_priv(dev);
3486
3487         switch (type) {
3488 #ifdef CONFIG_MLX5_ESWITCH
3489         case TC_SETUP_BLOCK: {
3490                 struct flow_block_offload *f = type_data;
3491
3492                 f->unlocked_driver_cb = true;
3493                 return flow_block_cb_setup_simple(type_data,
3494                                                   &mlx5e_block_cb_list,
3495                                                   mlx5e_setup_tc_block_cb,
3496                                                   priv, priv, true);
3497         }
3498 #endif
3499         case TC_SETUP_QDISC_MQPRIO:
3500                 return mlx5e_setup_tc_mqprio(priv, type_data);
3501         default:
3502                 return -EOPNOTSUPP;
3503         }
3504 }
3505
3506 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3507 {
3508         int i;
3509
3510         for (i = 0; i < priv->max_nch; i++) {
3511                 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3512                 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq;
3513                 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3514                 int j;
3515
3516                 s->rx_packets   += rq_stats->packets + xskrq_stats->packets;
3517                 s->rx_bytes     += rq_stats->bytes + xskrq_stats->bytes;
3518
3519                 for (j = 0; j < priv->max_opened_tc; j++) {
3520                         struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3521
3522                         s->tx_packets    += sq_stats->packets;
3523                         s->tx_bytes      += sq_stats->bytes;
3524                         s->tx_dropped    += sq_stats->dropped;
3525                 }
3526         }
3527 }
3528
3529 void
3530 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3531 {
3532         struct mlx5e_priv *priv = netdev_priv(dev);
3533         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3534         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3535
3536         if (!mlx5e_monitor_counter_supported(priv)) {
3537                 /* update HW stats in background for next time */
3538                 mlx5e_queue_update_stats(priv);
3539         }
3540
3541         if (mlx5e_is_uplink_rep(priv)) {
3542                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3543                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3544                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3545                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3546         } else {
3547                 mlx5e_fold_sw_stats64(priv, stats);
3548         }
3549
3550         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3551
3552         stats->rx_length_errors =
3553                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3554                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3555                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3556         stats->rx_crc_errors =
3557                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3558         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3559         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3560         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3561                            stats->rx_frame_errors;
3562         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3563
3564         /* vport multicast also counts packets that are dropped due to steering
3565          * or rx out of buffer
3566          */
3567         stats->multicast =
3568                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3569 }
3570
3571 static void mlx5e_set_rx_mode(struct net_device *dev)
3572 {
3573         struct mlx5e_priv *priv = netdev_priv(dev);
3574
3575         queue_work(priv->wq, &priv->set_rx_mode_work);
3576 }
3577
3578 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3579 {
3580         struct mlx5e_priv *priv = netdev_priv(netdev);
3581         struct sockaddr *saddr = addr;
3582
3583         if (!is_valid_ether_addr(saddr->sa_data))
3584                 return -EADDRNOTAVAIL;
3585
3586         netif_addr_lock_bh(netdev);
3587         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3588         netif_addr_unlock_bh(netdev);
3589
3590         queue_work(priv->wq, &priv->set_rx_mode_work);
3591
3592         return 0;
3593 }
3594
3595 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3596         do {                                            \
3597                 if (enable)                             \
3598                         *features |= feature;           \
3599                 else                                    \
3600                         *features &= ~feature;          \
3601         } while (0)
3602
3603 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3604
3605 static int set_feature_lro(struct net_device *netdev, bool enable)
3606 {
3607         struct mlx5e_priv *priv = netdev_priv(netdev);
3608         struct mlx5_core_dev *mdev = priv->mdev;
3609         struct mlx5e_channels new_channels = {};
3610         struct mlx5e_params *old_params;
3611         int err = 0;
3612         bool reset;
3613
3614         mutex_lock(&priv->state_lock);
3615
3616         if (enable && priv->xsk.refcnt) {
3617                 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%hu XSKs are active)\n",
3618                             priv->xsk.refcnt);
3619                 err = -EINVAL;
3620                 goto out;
3621         }
3622
3623         old_params = &priv->channels.params;
3624         if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3625                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3626                 err = -EINVAL;
3627                 goto out;
3628         }
3629
3630         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3631
3632         new_channels.params = *old_params;
3633         new_channels.params.lro_en = enable;
3634
3635         if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3636                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params, NULL) ==
3637                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params, NULL))
3638                         reset = false;
3639         }
3640
3641         if (!reset) {
3642                 *old_params = new_channels.params;
3643                 err = mlx5e_modify_tirs_lro(priv);
3644                 goto out;
3645         }
3646
3647         err = mlx5e_safe_switch_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3648 out:
3649         mutex_unlock(&priv->state_lock);
3650         return err;
3651 }
3652
3653 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3654 {
3655         struct mlx5e_priv *priv = netdev_priv(netdev);
3656
3657         if (enable)
3658                 mlx5e_enable_cvlan_filter(priv);
3659         else
3660                 mlx5e_disable_cvlan_filter(priv);
3661
3662         return 0;
3663 }
3664
3665 #ifdef CONFIG_MLX5_ESWITCH
3666 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3667 {
3668         struct mlx5e_priv *priv = netdev_priv(netdev);
3669
3670         if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) {
3671                 netdev_err(netdev,
3672                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3673                 return -EINVAL;
3674         }
3675
3676         return 0;
3677 }
3678 #endif
3679
3680 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3681 {
3682         struct mlx5e_priv *priv = netdev_priv(netdev);
3683         struct mlx5_core_dev *mdev = priv->mdev;
3684
3685         return mlx5_set_port_fcs(mdev, !enable);
3686 }
3687
3688 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3689 {
3690         struct mlx5e_priv *priv = netdev_priv(netdev);
3691         int err;
3692
3693         mutex_lock(&priv->state_lock);
3694
3695         priv->channels.params.scatter_fcs_en = enable;
3696         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3697         if (err)
3698                 priv->channels.params.scatter_fcs_en = !enable;
3699
3700         mutex_unlock(&priv->state_lock);
3701
3702         return err;
3703 }
3704
3705 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3706 {
3707         struct mlx5e_priv *priv = netdev_priv(netdev);
3708         int err = 0;
3709
3710         mutex_lock(&priv->state_lock);
3711
3712         priv->channels.params.vlan_strip_disable = !enable;
3713         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3714                 goto unlock;
3715
3716         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3717         if (err)
3718                 priv->channels.params.vlan_strip_disable = enable;
3719
3720 unlock:
3721         mutex_unlock(&priv->state_lock);
3722
3723         return err;
3724 }
3725
3726 #ifdef CONFIG_MLX5_EN_ARFS
3727 static int set_feature_arfs(struct net_device *netdev, bool enable)
3728 {
3729         struct mlx5e_priv *priv = netdev_priv(netdev);
3730         int err;
3731
3732         if (enable)
3733                 err = mlx5e_arfs_enable(priv);
3734         else
3735                 err = mlx5e_arfs_disable(priv);
3736
3737         return err;
3738 }
3739 #endif
3740
3741 static int mlx5e_handle_feature(struct net_device *netdev,
3742                                 netdev_features_t *features,
3743                                 netdev_features_t wanted_features,
3744                                 netdev_features_t feature,
3745                                 mlx5e_feature_handler feature_handler)
3746 {
3747         netdev_features_t changes = wanted_features ^ netdev->features;
3748         bool enable = !!(wanted_features & feature);
3749         int err;
3750
3751         if (!(changes & feature))
3752                 return 0;
3753
3754         err = feature_handler(netdev, enable);
3755         if (err) {
3756                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3757                            enable ? "Enable" : "Disable", &feature, err);
3758                 return err;
3759         }
3760
3761         MLX5E_SET_FEATURE(features, feature, enable);
3762         return 0;
3763 }
3764
3765 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features)
3766 {
3767         netdev_features_t oper_features = netdev->features;
3768         int err = 0;
3769
3770 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3771         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3772
3773         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3774         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3775                                     set_feature_cvlan_filter);
3776 #ifdef CONFIG_MLX5_ESWITCH
3777         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3778 #endif
3779         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3780         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3781         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3782 #ifdef CONFIG_MLX5_EN_ARFS
3783         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3784 #endif
3785
3786         if (err) {
3787                 netdev->features = oper_features;
3788                 return -EINVAL;
3789         }
3790
3791         return 0;
3792 }
3793
3794 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3795                                             netdev_features_t features)
3796 {
3797         struct mlx5e_priv *priv = netdev_priv(netdev);
3798         struct mlx5e_params *params;
3799
3800         mutex_lock(&priv->state_lock);
3801         params = &priv->channels.params;
3802         if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3803                 /* HW strips the outer C-tag header, this is a problem
3804                  * for S-tag traffic.
3805                  */
3806                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3807                 if (!params->vlan_strip_disable)
3808                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3809         }
3810         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3811                 if (features & NETIF_F_LRO) {
3812                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3813                         features &= ~NETIF_F_LRO;
3814                 }
3815         }
3816
3817         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
3818                 features &= ~NETIF_F_RXHASH;
3819                 if (netdev->features & NETIF_F_RXHASH)
3820                         netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n");
3821         }
3822
3823         mutex_unlock(&priv->state_lock);
3824
3825         return features;
3826 }
3827
3828 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev,
3829                                    struct mlx5e_channels *chs,
3830                                    struct mlx5e_params *new_params,
3831                                    struct mlx5_core_dev *mdev)
3832 {
3833         u16 ix;
3834
3835         for (ix = 0; ix < chs->params.num_channels; ix++) {
3836                 struct xdp_umem *umem = mlx5e_xsk_get_umem(&chs->params, chs->params.xsk, ix);
3837                 struct mlx5e_xsk_param xsk;
3838
3839                 if (!umem)
3840                         continue;
3841
3842                 mlx5e_build_xsk_param(umem, &xsk);
3843
3844                 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) {
3845                         u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk);
3846                         int max_mtu_frame, max_mtu_page, max_mtu;
3847
3848                         /* Two criteria must be met:
3849                          * 1. HW MTU + all headrooms <= XSK frame size.
3850                          * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE.
3851                          */
3852                         max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr);
3853                         max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk);
3854                         max_mtu = min(max_mtu_frame, max_mtu_page);
3855
3856                         netdev_err(netdev, "MTU %d is too big for an XSK running on channel %hu. Try MTU <= %d\n",
3857                                    new_params->sw_mtu, ix, max_mtu);
3858                         return false;
3859                 }
3860         }
3861
3862         return true;
3863 }
3864
3865 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3866                      change_hw_mtu_cb set_mtu_cb)
3867 {
3868         struct mlx5e_priv *priv = netdev_priv(netdev);
3869         struct mlx5e_channels new_channels = {};
3870         struct mlx5e_params *params;
3871         int err = 0;
3872         bool reset;
3873
3874         mutex_lock(&priv->state_lock);
3875
3876         params = &priv->channels.params;
3877
3878         reset = !params->lro_en;
3879         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3880
3881         new_channels.params = *params;
3882         new_channels.params.sw_mtu = new_mtu;
3883
3884         if (params->xdp_prog &&
3885             !mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
3886                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3887                            new_mtu, mlx5e_xdp_max_mtu(params, NULL));
3888                 err = -EINVAL;
3889                 goto out;
3890         }
3891
3892         if (priv->xsk.refcnt &&
3893             !mlx5e_xsk_validate_mtu(netdev, &priv->channels,
3894                                     &new_channels.params, priv->mdev)) {
3895                 err = -EINVAL;
3896                 goto out;
3897         }
3898
3899         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3900                 bool is_linear = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev,
3901                                                               &new_channels.params,
3902                                                               NULL);
3903                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL);
3904                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params, NULL);
3905
3906                 /* If XSK is active, XSK RQs are linear. */
3907                 is_linear |= priv->xsk.refcnt;
3908
3909                 /* Always reset in linear mode - hw_mtu is used in data path. */
3910                 reset = reset && (is_linear || (ppw_old != ppw_new));
3911         }
3912
3913         if (!reset) {
3914                 params->sw_mtu = new_mtu;
3915                 if (set_mtu_cb)
3916                         set_mtu_cb(priv);
3917                 netdev->mtu = params->sw_mtu;
3918                 goto out;
3919         }
3920
3921         err = mlx5e_safe_switch_channels(priv, &new_channels, set_mtu_cb);
3922         if (err)
3923                 goto out;
3924
3925         netdev->mtu = new_channels.params.sw_mtu;
3926
3927 out:
3928         mutex_unlock(&priv->state_lock);
3929         return err;
3930 }
3931
3932 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3933 {
3934         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3935 }
3936
3937 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3938 {
3939         struct hwtstamp_config config;
3940         int err;
3941
3942         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3943             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
3944                 return -EOPNOTSUPP;
3945
3946         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3947                 return -EFAULT;
3948
3949         /* TX HW timestamp */
3950         switch (config.tx_type) {
3951         case HWTSTAMP_TX_OFF:
3952         case HWTSTAMP_TX_ON:
3953                 break;
3954         default:
3955                 return -ERANGE;
3956         }
3957
3958         mutex_lock(&priv->state_lock);
3959         /* RX HW timestamp */
3960         switch (config.rx_filter) {
3961         case HWTSTAMP_FILTER_NONE:
3962                 /* Reset CQE compression to Admin default */
3963                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3964                 break;
3965         case HWTSTAMP_FILTER_ALL:
3966         case HWTSTAMP_FILTER_SOME:
3967         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3968         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3969         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3970         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3971         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3972         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3973         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3974         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3975         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3976         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3977         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3978         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3979         case HWTSTAMP_FILTER_NTP_ALL:
3980                 /* Disable CQE compression */
3981                 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
3982                         netdev_warn(priv->netdev, "Disabling RX cqe compression\n");
3983                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3984                 if (err) {
3985                         netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3986                         mutex_unlock(&priv->state_lock);
3987                         return err;
3988                 }
3989                 config.rx_filter = HWTSTAMP_FILTER_ALL;
3990                 break;
3991         default:
3992                 mutex_unlock(&priv->state_lock);
3993                 return -ERANGE;
3994         }
3995
3996         memcpy(&priv->tstamp, &config, sizeof(config));
3997         mutex_unlock(&priv->state_lock);
3998
3999         /* might need to fix some features */
4000         netdev_update_features(priv->netdev);
4001
4002         return copy_to_user(ifr->ifr_data, &config,
4003                             sizeof(config)) ? -EFAULT : 0;
4004 }
4005
4006 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
4007 {
4008         struct hwtstamp_config *cfg = &priv->tstamp;
4009
4010         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
4011                 return -EOPNOTSUPP;
4012
4013         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
4014 }
4015
4016 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4017 {
4018         struct mlx5e_priv *priv = netdev_priv(dev);
4019
4020         switch (cmd) {
4021         case SIOCSHWTSTAMP:
4022                 return mlx5e_hwstamp_set(priv, ifr);
4023         case SIOCGHWTSTAMP:
4024                 return mlx5e_hwstamp_get(priv, ifr);
4025         default:
4026                 return -EOPNOTSUPP;
4027         }
4028 }
4029
4030 #ifdef CONFIG_MLX5_ESWITCH
4031 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
4032 {
4033         struct mlx5e_priv *priv = netdev_priv(dev);
4034         struct mlx5_core_dev *mdev = priv->mdev;
4035
4036         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
4037 }
4038
4039 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
4040                              __be16 vlan_proto)
4041 {
4042         struct mlx5e_priv *priv = netdev_priv(dev);
4043         struct mlx5_core_dev *mdev = priv->mdev;
4044
4045         if (vlan_proto != htons(ETH_P_8021Q))
4046                 return -EPROTONOSUPPORT;
4047
4048         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
4049                                            vlan, qos);
4050 }
4051
4052 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
4053 {
4054         struct mlx5e_priv *priv = netdev_priv(dev);
4055         struct mlx5_core_dev *mdev = priv->mdev;
4056
4057         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
4058 }
4059
4060 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
4061 {
4062         struct mlx5e_priv *priv = netdev_priv(dev);
4063         struct mlx5_core_dev *mdev = priv->mdev;
4064
4065         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
4066 }
4067
4068 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
4069                       int max_tx_rate)
4070 {
4071         struct mlx5e_priv *priv = netdev_priv(dev);
4072         struct mlx5_core_dev *mdev = priv->mdev;
4073
4074         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
4075                                            max_tx_rate, min_tx_rate);
4076 }
4077
4078 static int mlx5_vport_link2ifla(u8 esw_link)
4079 {
4080         switch (esw_link) {
4081         case MLX5_VPORT_ADMIN_STATE_DOWN:
4082                 return IFLA_VF_LINK_STATE_DISABLE;
4083         case MLX5_VPORT_ADMIN_STATE_UP:
4084                 return IFLA_VF_LINK_STATE_ENABLE;
4085         }
4086         return IFLA_VF_LINK_STATE_AUTO;
4087 }
4088
4089 static int mlx5_ifla_link2vport(u8 ifla_link)
4090 {
4091         switch (ifla_link) {
4092         case IFLA_VF_LINK_STATE_DISABLE:
4093                 return MLX5_VPORT_ADMIN_STATE_DOWN;
4094         case IFLA_VF_LINK_STATE_ENABLE:
4095                 return MLX5_VPORT_ADMIN_STATE_UP;
4096         }
4097         return MLX5_VPORT_ADMIN_STATE_AUTO;
4098 }
4099
4100 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
4101                                    int link_state)
4102 {
4103         struct mlx5e_priv *priv = netdev_priv(dev);
4104         struct mlx5_core_dev *mdev = priv->mdev;
4105
4106         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4107                                             mlx5_ifla_link2vport(link_state));
4108 }
4109
4110 int mlx5e_get_vf_config(struct net_device *dev,
4111                         int vf, struct ifla_vf_info *ivi)
4112 {
4113         struct mlx5e_priv *priv = netdev_priv(dev);
4114         struct mlx5_core_dev *mdev = priv->mdev;
4115         int err;
4116
4117         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4118         if (err)
4119                 return err;
4120         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4121         return 0;
4122 }
4123
4124 int mlx5e_get_vf_stats(struct net_device *dev,
4125                        int vf, struct ifla_vf_stats *vf_stats)
4126 {
4127         struct mlx5e_priv *priv = netdev_priv(dev);
4128         struct mlx5_core_dev *mdev = priv->mdev;
4129
4130         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4131                                             vf_stats);
4132 }
4133 #endif
4134
4135 struct mlx5e_vxlan_work {
4136         struct work_struct      work;
4137         struct mlx5e_priv       *priv;
4138         u16                     port;
4139 };
4140
4141 static void mlx5e_vxlan_add_work(struct work_struct *work)
4142 {
4143         struct mlx5e_vxlan_work *vxlan_work =
4144                 container_of(work, struct mlx5e_vxlan_work, work);
4145         struct mlx5e_priv *priv = vxlan_work->priv;
4146         u16 port = vxlan_work->port;
4147
4148         mutex_lock(&priv->state_lock);
4149         mlx5_vxlan_add_port(priv->mdev->vxlan, port);
4150         mutex_unlock(&priv->state_lock);
4151
4152         kfree(vxlan_work);
4153 }
4154
4155 static void mlx5e_vxlan_del_work(struct work_struct *work)
4156 {
4157         struct mlx5e_vxlan_work *vxlan_work =
4158                 container_of(work, struct mlx5e_vxlan_work, work);
4159         struct mlx5e_priv *priv         = vxlan_work->priv;
4160         u16 port = vxlan_work->port;
4161
4162         mutex_lock(&priv->state_lock);
4163         mlx5_vxlan_del_port(priv->mdev->vxlan, port);
4164         mutex_unlock(&priv->state_lock);
4165         kfree(vxlan_work);
4166 }
4167
4168 static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
4169 {
4170         struct mlx5e_vxlan_work *vxlan_work;
4171
4172         vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
4173         if (!vxlan_work)
4174                 return;
4175
4176         if (add)
4177                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
4178         else
4179                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4180
4181         vxlan_work->priv = priv;
4182         vxlan_work->port = port;
4183         queue_work(priv->wq, &vxlan_work->work);
4184 }
4185
4186 void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4187 {
4188         struct mlx5e_priv *priv = netdev_priv(netdev);
4189
4190         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4191                 return;
4192
4193         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4194                 return;
4195
4196         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
4197 }
4198
4199 void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4200 {
4201         struct mlx5e_priv *priv = netdev_priv(netdev);
4202
4203         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4204                 return;
4205
4206         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4207                 return;
4208
4209         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
4210 }
4211
4212 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4213                                                      struct sk_buff *skb,
4214                                                      netdev_features_t features)
4215 {
4216         unsigned int offset = 0;
4217         struct udphdr *udph;
4218         u8 proto;
4219         u16 port;
4220
4221         switch (vlan_get_protocol(skb)) {
4222         case htons(ETH_P_IP):
4223                 proto = ip_hdr(skb)->protocol;
4224                 break;
4225         case htons(ETH_P_IPV6):
4226                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4227                 break;
4228         default:
4229                 goto out;
4230         }
4231
4232         switch (proto) {
4233         case IPPROTO_GRE:
4234                 return features;
4235         case IPPROTO_IPIP:
4236         case IPPROTO_IPV6:
4237                 if (mlx5e_tunnel_proto_supported(priv->mdev, IPPROTO_IPIP))
4238                         return features;
4239                 break;
4240         case IPPROTO_UDP:
4241                 udph = udp_hdr(skb);
4242                 port = be16_to_cpu(udph->dest);
4243
4244                 /* Verify if UDP port is being offloaded by HW */
4245                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4246                         return features;
4247
4248 #if IS_ENABLED(CONFIG_GENEVE)
4249                 /* Support Geneve offload for default UDP port */
4250                 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4251                         return features;
4252 #endif
4253         }
4254
4255 out:
4256         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4257         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4258 }
4259
4260 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4261                                        struct net_device *netdev,
4262                                        netdev_features_t features)
4263 {
4264         struct mlx5e_priv *priv = netdev_priv(netdev);
4265
4266         features = vlan_features_check(skb, features);
4267         features = vxlan_features_check(skb, features);
4268
4269 #ifdef CONFIG_MLX5_EN_IPSEC
4270         if (mlx5e_ipsec_feature_check(skb, netdev, features))
4271                 return features;
4272 #endif
4273
4274         /* Validate if the tunneled packet is being offloaded by HW */
4275         if (skb->encapsulation &&
4276             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4277                 return mlx5e_tunnel_features_check(priv, skb, features);
4278
4279         return features;
4280 }
4281
4282 static void mlx5e_tx_timeout_work(struct work_struct *work)
4283 {
4284         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4285                                                tx_timeout_work);
4286         bool report_failed = false;
4287         int err;
4288         int i;
4289
4290         rtnl_lock();
4291         mutex_lock(&priv->state_lock);
4292
4293         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4294                 goto unlock;
4295
4296         for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4297                 struct netdev_queue *dev_queue =
4298                         netdev_get_tx_queue(priv->netdev, i);
4299                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4300
4301                 if (!netif_xmit_stopped(dev_queue))
4302                         continue;
4303
4304                 if (mlx5e_reporter_tx_timeout(sq))
4305                         report_failed = true;
4306         }
4307
4308         if (!report_failed)
4309                 goto unlock;
4310
4311         err = mlx5e_safe_reopen_channels(priv);
4312         if (err)
4313                 netdev_err(priv->netdev,
4314                            "mlx5e_safe_reopen_channels failed recovering from a tx_timeout, err(%d).\n",
4315                            err);
4316
4317 unlock:
4318         mutex_unlock(&priv->state_lock);
4319         rtnl_unlock();
4320 }
4321
4322 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue)
4323 {
4324         struct mlx5e_priv *priv = netdev_priv(dev);
4325
4326         netdev_err(dev, "TX timeout detected\n");
4327         queue_work(priv->wq, &priv->tx_timeout_work);
4328 }
4329
4330 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4331 {
4332         struct net_device *netdev = priv->netdev;
4333         struct mlx5e_channels new_channels = {};
4334
4335         if (priv->channels.params.lro_en) {
4336                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4337                 return -EINVAL;
4338         }
4339
4340         if (MLX5_IPSEC_DEV(priv->mdev)) {
4341                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4342                 return -EINVAL;
4343         }
4344
4345         new_channels.params = priv->channels.params;
4346         new_channels.params.xdp_prog = prog;
4347
4348         /* No XSK params: AF_XDP can't be enabled yet at the point of setting
4349          * the XDP program.
4350          */
4351         if (!mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) {
4352                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4353                             new_channels.params.sw_mtu,
4354                             mlx5e_xdp_max_mtu(&new_channels.params, NULL));
4355                 return -EINVAL;
4356         }
4357
4358         return 0;
4359 }
4360
4361 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4362 {
4363         struct mlx5e_priv *priv = netdev_priv(netdev);
4364         struct bpf_prog *old_prog;
4365         bool reset, was_opened;
4366         int err = 0;
4367         int i;
4368
4369         mutex_lock(&priv->state_lock);
4370
4371         if (prog) {
4372                 err = mlx5e_xdp_allowed(priv, prog);
4373                 if (err)
4374                         goto unlock;
4375         }
4376
4377         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4378         /* no need for full reset when exchanging programs */
4379         reset = (!priv->channels.params.xdp_prog || !prog);
4380
4381         if (was_opened && !reset)
4382                 /* num_channels is invariant here, so we can take the
4383                  * batched reference right upfront.
4384                  */
4385                 bpf_prog_add(prog, priv->channels.num);
4386
4387         if (was_opened && reset) {
4388                 struct mlx5e_channels new_channels = {};
4389
4390                 new_channels.params = priv->channels.params;
4391                 new_channels.params.xdp_prog = prog;
4392                 mlx5e_set_rq_type(priv->mdev, &new_channels.params);
4393                 old_prog = priv->channels.params.xdp_prog;
4394
4395                 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
4396                 if (err)
4397                         goto unlock;
4398         } else {
4399                 /* exchange programs, extra prog reference we got from caller
4400                  * as long as we don't fail from this point onwards.
4401                  */
4402                 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4403         }
4404
4405         if (old_prog)
4406                 bpf_prog_put(old_prog);
4407
4408         if (!was_opened && reset) /* change RQ type according to priv->xdp_prog */
4409                 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4410
4411         if (!was_opened || reset)
4412                 goto unlock;
4413
4414         /* exchanging programs w/o reset, we update ref counts on behalf
4415          * of the channels RQs here.
4416          */
4417         for (i = 0; i < priv->channels.num; i++) {
4418                 struct mlx5e_channel *c = priv->channels.c[i];
4419                 bool xsk_open = test_bit(MLX5E_CHANNEL_STATE_XSK, c->state);
4420
4421                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4422                 if (xsk_open)
4423                         clear_bit(MLX5E_RQ_STATE_ENABLED, &c->xskrq.state);
4424                 napi_synchronize(&c->napi);
4425                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4426
4427                 old_prog = xchg(&c->rq.xdp_prog, prog);
4428                 if (old_prog)
4429                         bpf_prog_put(old_prog);
4430
4431                 if (xsk_open) {
4432                         old_prog = xchg(&c->xskrq.xdp_prog, prog);
4433                         if (old_prog)
4434                                 bpf_prog_put(old_prog);
4435                 }
4436
4437                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4438                 if (xsk_open)
4439                         set_bit(MLX5E_RQ_STATE_ENABLED, &c->xskrq.state);
4440                 /* napi_schedule in case we have missed anything */
4441                 napi_schedule(&c->napi);
4442         }
4443
4444 unlock:
4445         mutex_unlock(&priv->state_lock);
4446         return err;
4447 }
4448
4449 static u32 mlx5e_xdp_query(struct net_device *dev)
4450 {
4451         struct mlx5e_priv *priv = netdev_priv(dev);
4452         const struct bpf_prog *xdp_prog;
4453         u32 prog_id = 0;
4454
4455         mutex_lock(&priv->state_lock);
4456         xdp_prog = priv->channels.params.xdp_prog;
4457         if (xdp_prog)
4458                 prog_id = xdp_prog->aux->id;
4459         mutex_unlock(&priv->state_lock);
4460
4461         return prog_id;
4462 }
4463
4464 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4465 {
4466         switch (xdp->command) {
4467         case XDP_SETUP_PROG:
4468                 return mlx5e_xdp_set(dev, xdp->prog);
4469         case XDP_QUERY_PROG:
4470                 xdp->prog_id = mlx5e_xdp_query(dev);
4471                 return 0;
4472         case XDP_SETUP_XSK_UMEM:
4473                 return mlx5e_xsk_setup_umem(dev, xdp->xsk.umem,
4474                                             xdp->xsk.queue_id);
4475         default:
4476                 return -EINVAL;
4477         }
4478 }
4479
4480 #ifdef CONFIG_MLX5_ESWITCH
4481 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4482                                 struct net_device *dev, u32 filter_mask,
4483                                 int nlflags)
4484 {
4485         struct mlx5e_priv *priv = netdev_priv(dev);
4486         struct mlx5_core_dev *mdev = priv->mdev;
4487         u8 mode, setting;
4488         int err;
4489
4490         err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4491         if (err)
4492                 return err;
4493         mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4494         return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4495                                        mode,
4496                                        0, 0, nlflags, filter_mask, NULL);
4497 }
4498
4499 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4500                                 u16 flags, struct netlink_ext_ack *extack)
4501 {
4502         struct mlx5e_priv *priv = netdev_priv(dev);
4503         struct mlx5_core_dev *mdev = priv->mdev;
4504         struct nlattr *attr, *br_spec;
4505         u16 mode = BRIDGE_MODE_UNDEF;
4506         u8 setting;
4507         int rem;
4508
4509         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4510         if (!br_spec)
4511                 return -EINVAL;
4512
4513         nla_for_each_nested(attr, br_spec, rem) {
4514                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4515                         continue;
4516
4517                 if (nla_len(attr) < sizeof(mode))
4518                         return -EINVAL;
4519
4520                 mode = nla_get_u16(attr);
4521                 if (mode > BRIDGE_MODE_VEPA)
4522                         return -EINVAL;
4523
4524                 break;
4525         }
4526
4527         if (mode == BRIDGE_MODE_UNDEF)
4528                 return -EINVAL;
4529
4530         setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4531         return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4532 }
4533 #endif
4534
4535 const struct net_device_ops mlx5e_netdev_ops = {
4536         .ndo_open                = mlx5e_open,
4537         .ndo_stop                = mlx5e_close,
4538         .ndo_start_xmit          = mlx5e_xmit,
4539         .ndo_setup_tc            = mlx5e_setup_tc,
4540         .ndo_select_queue        = mlx5e_select_queue,
4541         .ndo_get_stats64         = mlx5e_get_stats,
4542         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4543         .ndo_set_mac_address     = mlx5e_set_mac,
4544         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4545         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4546         .ndo_set_features        = mlx5e_set_features,
4547         .ndo_fix_features        = mlx5e_fix_features,
4548         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4549         .ndo_do_ioctl            = mlx5e_ioctl,
4550         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4551         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
4552         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
4553         .ndo_features_check      = mlx5e_features_check,
4554         .ndo_tx_timeout          = mlx5e_tx_timeout,
4555         .ndo_bpf                 = mlx5e_xdp,
4556         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4557         .ndo_xsk_wakeup          = mlx5e_xsk_wakeup,
4558 #ifdef CONFIG_MLX5_EN_ARFS
4559         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4560 #endif
4561 #ifdef CONFIG_MLX5_ESWITCH
4562         .ndo_bridge_setlink      = mlx5e_bridge_setlink,
4563         .ndo_bridge_getlink      = mlx5e_bridge_getlink,
4564
4565         /* SRIOV E-Switch NDOs */
4566         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4567         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4568         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4569         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4570         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4571         .ndo_get_vf_config       = mlx5e_get_vf_config,
4572         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4573         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4574 #endif
4575 };
4576
4577 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4578 {
4579         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4580                 return -EOPNOTSUPP;
4581         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4582             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4583             !MLX5_CAP_ETH(mdev, csum_cap) ||
4584             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4585             !MLX5_CAP_ETH(mdev, vlan_cap) ||
4586             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4587             MLX5_CAP_FLOWTABLE(mdev,
4588                                flow_table_properties_nic_receive.max_ft_level)
4589                                < 3) {
4590                 mlx5_core_warn(mdev,
4591                                "Not creating net device, some required device capabilities are missing\n");
4592                 return -EOPNOTSUPP;
4593         }
4594         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4595                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4596         if (!MLX5_CAP_GEN(mdev, cq_moderation))
4597                 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4598
4599         return 0;
4600 }
4601
4602 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4603                                    int num_channels)
4604 {
4605         int i;
4606
4607         for (i = 0; i < len; i++)
4608                 indirection_rqt[i] = i % num_channels;
4609 }
4610
4611 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4612 {
4613         u32 link_speed = 0;
4614         u32 pci_bw = 0;
4615
4616         mlx5e_port_max_linkspeed(mdev, &link_speed);
4617         pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4618         mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4619                            link_speed, pci_bw);
4620
4621 #define MLX5E_SLOW_PCI_RATIO (2)
4622
4623         return link_speed && pci_bw &&
4624                 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4625 }
4626
4627 static struct dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4628 {
4629         struct dim_cq_moder moder;
4630
4631         moder.cq_period_mode = cq_period_mode;
4632         moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4633         moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4634         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4635                 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4636
4637         return moder;
4638 }
4639
4640 static struct dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4641 {
4642         struct dim_cq_moder moder;
4643
4644         moder.cq_period_mode = cq_period_mode;
4645         moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4646         moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4647         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4648                 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4649
4650         return moder;
4651 }
4652
4653 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4654 {
4655         return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4656                 DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4657                 DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4658 }
4659
4660 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4661 {
4662         if (params->tx_dim_enabled) {
4663                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4664
4665                 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4666         } else {
4667                 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4668         }
4669
4670         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4671                         params->tx_cq_moderation.cq_period_mode ==
4672                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4673 }
4674
4675 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4676 {
4677         if (params->rx_dim_enabled) {
4678                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4679
4680                 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4681         } else {
4682                 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4683         }
4684
4685         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4686                         params->rx_cq_moderation.cq_period_mode ==
4687                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4688 }
4689
4690 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4691 {
4692         int i;
4693
4694         /* The supported periods are organized in ascending order */
4695         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4696                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4697                         break;
4698
4699         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4700 }
4701
4702 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
4703                            struct mlx5e_params *params)
4704 {
4705         /* Prefer Striding RQ, unless any of the following holds:
4706          * - Striding RQ configuration is not possible/supported.
4707          * - Slow PCI heuristic.
4708          * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4709          *
4710          * No XSK params: checking the availability of striding RQ in general.
4711          */
4712         if (!slow_pci_heuristic(mdev) &&
4713             mlx5e_striding_rq_possible(mdev, params) &&
4714             (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ||
4715              !mlx5e_rx_is_linear_skb(params, NULL)))
4716                 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4717         mlx5e_set_rq_type(mdev, params);
4718         mlx5e_init_rq_type_params(mdev, params);
4719 }
4720
4721 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4722                             u16 num_channels)
4723 {
4724         enum mlx5e_traffic_types tt;
4725
4726         rss_params->hfunc = ETH_RSS_HASH_TOP;
4727         netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4728                             sizeof(rss_params->toeplitz_hash_key));
4729         mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4730                                       MLX5E_INDIR_RQT_SIZE, num_channels);
4731         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4732                 rss_params->rx_hash_fields[tt] =
4733                         tirc_default_config[tt].rx_hash_fields;
4734 }
4735
4736 void mlx5e_build_nic_params(struct mlx5e_priv *priv,
4737                             struct mlx5e_xsk *xsk,
4738                             struct mlx5e_rss_params *rss_params,
4739                             struct mlx5e_params *params,
4740                             u16 mtu)
4741 {
4742         struct mlx5_core_dev *mdev = priv->mdev;
4743         u8 rx_cq_period_mode;
4744
4745         params->sw_mtu = mtu;
4746         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4747         params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2,
4748                                      priv->max_nch);
4749         params->num_tc       = 1;
4750
4751         /* SQ */
4752         params->log_sq_size = is_kdump_kernel() ?
4753                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4754                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4755
4756         /* XDP SQ */
4757         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE,
4758                         MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4759
4760         /* set CQE compression */
4761         params->rx_cqe_compress_def = false;
4762         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4763             MLX5_CAP_GEN(mdev, vport_group_manager))
4764                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4765
4766         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4767         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4768
4769         /* RQ */
4770         mlx5e_build_rq_params(mdev, params);
4771
4772         /* HW LRO */
4773
4774         /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4775         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
4776                 /* No XSK params: checking the availability of striding RQ in general. */
4777                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL))
4778                         params->lro_en = !slow_pci_heuristic(mdev);
4779         }
4780         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4781
4782         /* CQ moderation params */
4783         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4784                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4785                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4786         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4787         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4788         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4789         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4790
4791         /* TX inline */
4792         mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
4793
4794         /* RSS */
4795         mlx5e_build_rss_params(rss_params, params->num_channels);
4796         params->tunneled_offload_en =
4797                 mlx5e_tunnel_inner_ft_supported(mdev);
4798
4799         /* AF_XDP */
4800         params->xsk = xsk;
4801 }
4802
4803 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4804 {
4805         struct mlx5e_priv *priv = netdev_priv(netdev);
4806
4807         mlx5_query_mac_address(priv->mdev, netdev->dev_addr);
4808         if (is_zero_ether_addr(netdev->dev_addr) &&
4809             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4810                 eth_hw_addr_random(netdev);
4811                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4812         }
4813 }
4814
4815 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4816 {
4817         struct mlx5e_priv *priv = netdev_priv(netdev);
4818         struct mlx5_core_dev *mdev = priv->mdev;
4819         bool fcs_supported;
4820         bool fcs_enabled;
4821
4822         SET_NETDEV_DEV(netdev, mdev->device);
4823
4824         netdev->netdev_ops = &mlx5e_netdev_ops;
4825
4826 #ifdef CONFIG_MLX5_CORE_EN_DCB
4827         if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4828                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4829 #endif
4830
4831         netdev->watchdog_timeo    = 15 * HZ;
4832
4833         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4834
4835         netdev->vlan_features    |= NETIF_F_SG;
4836         netdev->vlan_features    |= NETIF_F_HW_CSUM;
4837         netdev->vlan_features    |= NETIF_F_GRO;
4838         netdev->vlan_features    |= NETIF_F_TSO;
4839         netdev->vlan_features    |= NETIF_F_TSO6;
4840         netdev->vlan_features    |= NETIF_F_RXCSUM;
4841         netdev->vlan_features    |= NETIF_F_RXHASH;
4842
4843         netdev->mpls_features    |= NETIF_F_SG;
4844         netdev->mpls_features    |= NETIF_F_HW_CSUM;
4845         netdev->mpls_features    |= NETIF_F_TSO;
4846         netdev->mpls_features    |= NETIF_F_TSO6;
4847
4848         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4849         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4850
4851         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4852             mlx5e_check_fragmented_striding_rq_cap(mdev))
4853                 netdev->vlan_features    |= NETIF_F_LRO;
4854
4855         netdev->hw_features       = netdev->vlan_features;
4856         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4857         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4858         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4859         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4860
4861         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev) ||
4862             mlx5e_any_tunnel_proto_supported(mdev)) {
4863                 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
4864                 netdev->hw_enc_features |= NETIF_F_TSO;
4865                 netdev->hw_enc_features |= NETIF_F_TSO6;
4866                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4867         }
4868
4869         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4870                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4871                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4872                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4873                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4874                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4875                 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL |
4876                                          NETIF_F_GSO_UDP_TUNNEL_CSUM;
4877         }
4878
4879         if (mlx5e_tunnel_proto_supported(mdev, IPPROTO_GRE)) {
4880                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4881                                            NETIF_F_GSO_GRE_CSUM;
4882                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4883                                            NETIF_F_GSO_GRE_CSUM;
4884                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4885                                                 NETIF_F_GSO_GRE_CSUM;
4886         }
4887
4888         if (mlx5e_tunnel_proto_supported(mdev, IPPROTO_IPIP)) {
4889                 netdev->hw_features |= NETIF_F_GSO_IPXIP4 |
4890                                        NETIF_F_GSO_IPXIP6;
4891                 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 |
4892                                            NETIF_F_GSO_IPXIP6;
4893                 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 |
4894                                                 NETIF_F_GSO_IPXIP6;
4895         }
4896
4897         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4898         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4899         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4900         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4901
4902         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4903
4904         if (fcs_supported)
4905                 netdev->hw_features |= NETIF_F_RXALL;
4906
4907         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4908                 netdev->hw_features |= NETIF_F_RXFCS;
4909
4910         netdev->features          = netdev->hw_features;
4911         if (!priv->channels.params.lro_en)
4912                 netdev->features  &= ~NETIF_F_LRO;
4913
4914         if (fcs_enabled)
4915                 netdev->features  &= ~NETIF_F_RXALL;
4916
4917         if (!priv->channels.params.scatter_fcs_en)
4918                 netdev->features  &= ~NETIF_F_RXFCS;
4919
4920         /* prefere CQE compression over rxhash */
4921         if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS))
4922                 netdev->features &= ~NETIF_F_RXHASH;
4923
4924 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4925         if (FT_CAP(flow_modify_en) &&
4926             FT_CAP(modify_root) &&
4927             FT_CAP(identified_miss_table_mode) &&
4928             FT_CAP(flow_table_modify)) {
4929 #ifdef CONFIG_MLX5_ESWITCH
4930                 netdev->hw_features      |= NETIF_F_HW_TC;
4931 #endif
4932 #ifdef CONFIG_MLX5_EN_ARFS
4933                 netdev->hw_features      |= NETIF_F_NTUPLE;
4934 #endif
4935         }
4936
4937         netdev->features         |= NETIF_F_HIGHDMA;
4938         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4939
4940         netdev->priv_flags       |= IFF_UNICAST_FLT;
4941
4942         mlx5e_set_netdev_dev_addr(netdev);
4943         mlx5e_ipsec_build_netdev(priv);
4944         mlx5e_tls_build_netdev(priv);
4945 }
4946
4947 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4948 {
4949         struct mlx5_core_dev *mdev = priv->mdev;
4950         int err;
4951
4952         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4953         if (err) {
4954                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4955                 priv->q_counter = 0;
4956         }
4957
4958         err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4959         if (err) {
4960                 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4961                 priv->drop_rq_q_counter = 0;
4962         }
4963 }
4964
4965 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4966 {
4967         if (priv->q_counter)
4968                 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4969
4970         if (priv->drop_rq_q_counter)
4971                 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4972 }
4973
4974 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4975                           struct net_device *netdev,
4976                           const struct mlx5e_profile *profile,
4977                           void *ppriv)
4978 {
4979         struct mlx5e_priv *priv = netdev_priv(netdev);
4980         struct mlx5e_rss_params *rss = &priv->rss_params;
4981         int err;
4982
4983         err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv);
4984         if (err)
4985                 return err;
4986
4987         mlx5e_build_nic_params(priv, &priv->xsk, rss, &priv->channels.params,
4988                                netdev->mtu);
4989
4990         mlx5e_timestamp_init(priv);
4991
4992         err = mlx5e_ipsec_init(priv);
4993         if (err)
4994                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4995         err = mlx5e_tls_init(priv);
4996         if (err)
4997                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4998         mlx5e_build_nic_netdev(netdev);
4999         mlx5e_health_create_reporters(priv);
5000
5001         return 0;
5002 }
5003
5004 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
5005 {
5006         mlx5e_health_destroy_reporters(priv);
5007         mlx5e_tls_cleanup(priv);
5008         mlx5e_ipsec_cleanup(priv);
5009         mlx5e_netdev_cleanup(priv->netdev, priv);
5010 }
5011
5012 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
5013 {
5014         struct mlx5_core_dev *mdev = priv->mdev;
5015         int err;
5016
5017         mlx5e_create_q_counters(priv);
5018
5019         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
5020         if (err) {
5021                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
5022                 goto err_destroy_q_counters;
5023         }
5024
5025         err = mlx5e_create_indirect_rqt(priv);
5026         if (err)
5027                 goto err_close_drop_rq;
5028
5029         err = mlx5e_create_direct_rqts(priv, priv->direct_tir);
5030         if (err)
5031                 goto err_destroy_indirect_rqts;
5032
5033         err = mlx5e_create_indirect_tirs(priv, true);
5034         if (err)
5035                 goto err_destroy_direct_rqts;
5036
5037         err = mlx5e_create_direct_tirs(priv, priv->direct_tir);
5038         if (err)
5039                 goto err_destroy_indirect_tirs;
5040
5041         err = mlx5e_create_direct_rqts(priv, priv->xsk_tir);
5042         if (unlikely(err))
5043                 goto err_destroy_direct_tirs;
5044
5045         err = mlx5e_create_direct_tirs(priv, priv->xsk_tir);
5046         if (unlikely(err))
5047                 goto err_destroy_xsk_rqts;
5048
5049         err = mlx5e_create_flow_steering(priv);
5050         if (err) {
5051                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
5052                 goto err_destroy_xsk_tirs;
5053         }
5054
5055         err = mlx5e_tc_nic_init(priv);
5056         if (err)
5057                 goto err_destroy_flow_steering;
5058
5059         return 0;
5060
5061 err_destroy_flow_steering:
5062         mlx5e_destroy_flow_steering(priv);
5063 err_destroy_xsk_tirs:
5064         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5065 err_destroy_xsk_rqts:
5066         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5067 err_destroy_direct_tirs:
5068         mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5069 err_destroy_indirect_tirs:
5070         mlx5e_destroy_indirect_tirs(priv, true);
5071 err_destroy_direct_rqts:
5072         mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5073 err_destroy_indirect_rqts:
5074         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5075 err_close_drop_rq:
5076         mlx5e_close_drop_rq(&priv->drop_rq);
5077 err_destroy_q_counters:
5078         mlx5e_destroy_q_counters(priv);
5079         return err;
5080 }
5081
5082 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
5083 {
5084         mlx5e_tc_nic_cleanup(priv);
5085         mlx5e_destroy_flow_steering(priv);
5086         mlx5e_destroy_direct_tirs(priv, priv->xsk_tir);
5087         mlx5e_destroy_direct_rqts(priv, priv->xsk_tir);
5088         mlx5e_destroy_direct_tirs(priv, priv->direct_tir);
5089         mlx5e_destroy_indirect_tirs(priv, true);
5090         mlx5e_destroy_direct_rqts(priv, priv->direct_tir);
5091         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
5092         mlx5e_close_drop_rq(&priv->drop_rq);
5093         mlx5e_destroy_q_counters(priv);
5094 }
5095
5096 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
5097 {
5098         int err;
5099
5100         err = mlx5e_create_tises(priv);
5101         if (err) {
5102                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
5103                 return err;
5104         }
5105
5106 #ifdef CONFIG_MLX5_CORE_EN_DCB
5107         mlx5e_dcbnl_initialize(priv);
5108 #endif
5109         return 0;
5110 }
5111
5112 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
5113 {
5114         struct net_device *netdev = priv->netdev;
5115         struct mlx5_core_dev *mdev = priv->mdev;
5116
5117         mlx5e_init_l2_addr(priv);
5118
5119         /* Marking the link as currently not needed by the Driver */
5120         if (!netif_running(netdev))
5121                 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
5122
5123         mlx5e_set_netdev_mtu_boundaries(priv);
5124         mlx5e_set_dev_port_mtu(priv);
5125
5126         mlx5_lag_add(mdev, netdev);
5127
5128         mlx5e_enable_async_events(priv);
5129         if (mlx5e_monitor_counter_supported(priv))
5130                 mlx5e_monitor_counter_init(priv);
5131
5132         mlx5e_hv_vhca_stats_create(priv);
5133         if (netdev->reg_state != NETREG_REGISTERED)
5134                 return;
5135 #ifdef CONFIG_MLX5_CORE_EN_DCB
5136         mlx5e_dcbnl_init_app(priv);
5137 #endif
5138
5139         queue_work(priv->wq, &priv->set_rx_mode_work);
5140
5141         rtnl_lock();
5142         if (netif_running(netdev))
5143                 mlx5e_open(netdev);
5144         netif_device_attach(netdev);
5145         rtnl_unlock();
5146 }
5147
5148 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
5149 {
5150         struct mlx5_core_dev *mdev = priv->mdev;
5151
5152 #ifdef CONFIG_MLX5_CORE_EN_DCB
5153         if (priv->netdev->reg_state == NETREG_REGISTERED)
5154                 mlx5e_dcbnl_delete_app(priv);
5155 #endif
5156
5157         rtnl_lock();
5158         if (netif_running(priv->netdev))
5159                 mlx5e_close(priv->netdev);
5160         netif_device_detach(priv->netdev);
5161         rtnl_unlock();
5162
5163         queue_work(priv->wq, &priv->set_rx_mode_work);
5164
5165         mlx5e_hv_vhca_stats_destroy(priv);
5166         if (mlx5e_monitor_counter_supported(priv))
5167                 mlx5e_monitor_counter_cleanup(priv);
5168
5169         mlx5e_disable_async_events(priv);
5170         mlx5_lag_remove(mdev);
5171 }
5172
5173 int mlx5e_update_nic_rx(struct mlx5e_priv *priv)
5174 {
5175         return mlx5e_refresh_tirs(priv, false);
5176 }
5177
5178 static const struct mlx5e_profile mlx5e_nic_profile = {
5179         .init              = mlx5e_nic_init,
5180         .cleanup           = mlx5e_nic_cleanup,
5181         .init_rx           = mlx5e_init_nic_rx,
5182         .cleanup_rx        = mlx5e_cleanup_nic_rx,
5183         .init_tx           = mlx5e_init_nic_tx,
5184         .cleanup_tx        = mlx5e_cleanup_nic_tx,
5185         .enable            = mlx5e_nic_enable,
5186         .disable           = mlx5e_nic_disable,
5187         .update_rx         = mlx5e_update_nic_rx,
5188         .update_stats      = mlx5e_update_ndo_stats,
5189         .update_carrier    = mlx5e_update_carrier,
5190         .rx_handlers.handle_rx_cqe       = mlx5e_handle_rx_cqe,
5191         .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
5192         .max_tc            = MLX5E_MAX_NUM_TC,
5193         .rq_groups         = MLX5E_NUM_RQ_GROUPS(XSK),
5194         .stats_grps        = mlx5e_nic_stats_grps,
5195         .stats_grps_num    = mlx5e_nic_stats_grps_num,
5196 };
5197
5198 /* mlx5e generic netdev management API (move to en_common.c) */
5199
5200 /* mlx5e_netdev_init/cleanup must be called from profile->init/cleanup callbacks */
5201 int mlx5e_netdev_init(struct net_device *netdev,
5202                       struct mlx5e_priv *priv,
5203                       struct mlx5_core_dev *mdev,
5204                       const struct mlx5e_profile *profile,
5205                       void *ppriv)
5206 {
5207         /* priv init */
5208         priv->mdev        = mdev;
5209         priv->netdev      = netdev;
5210         priv->profile     = profile;
5211         priv->ppriv       = ppriv;
5212         priv->msglevel    = MLX5E_MSG_LEVEL;
5213         priv->max_nch     = netdev->num_rx_queues / max_t(u8, profile->rq_groups, 1);
5214         priv->max_opened_tc = 1;
5215
5216         mutex_init(&priv->state_lock);
5217         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5218         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5219         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5220         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5221
5222         priv->wq = create_singlethread_workqueue("mlx5e");
5223         if (!priv->wq)
5224                 return -ENOMEM;
5225
5226         /* netdev init */
5227         netif_carrier_off(netdev);
5228
5229 #ifdef CONFIG_MLX5_EN_ARFS
5230         netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(mdev);
5231 #endif
5232
5233         return 0;
5234 }
5235
5236 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv)
5237 {
5238         destroy_workqueue(priv->wq);
5239 }
5240
5241 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
5242                                        const struct mlx5e_profile *profile,
5243                                        int nch,
5244                                        void *ppriv)
5245 {
5246         struct net_device *netdev;
5247         int err;
5248
5249         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
5250                                     nch * profile->max_tc,
5251                                     nch * profile->rq_groups);
5252         if (!netdev) {
5253                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5254                 return NULL;
5255         }
5256
5257         err = profile->init(mdev, netdev, profile, ppriv);
5258         if (err) {
5259                 mlx5_core_err(mdev, "failed to init mlx5e profile %d\n", err);
5260                 goto err_free_netdev;
5261         }
5262
5263         return netdev;
5264
5265 err_free_netdev:
5266         free_netdev(netdev);
5267
5268         return NULL;
5269 }
5270
5271 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5272 {
5273         const struct mlx5e_profile *profile;
5274         int max_nch;
5275         int err;
5276
5277         profile = priv->profile;
5278         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5279
5280         /* max number of channels may have changed */
5281         max_nch = mlx5e_get_max_num_channels(priv->mdev);
5282         if (priv->channels.params.num_channels > max_nch) {
5283                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5284                 priv->channels.params.num_channels = max_nch;
5285                 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
5286                                               MLX5E_INDIR_RQT_SIZE, max_nch);
5287         }
5288
5289         err = profile->init_tx(priv);
5290         if (err)
5291                 goto out;
5292
5293         err = profile->init_rx(priv);
5294         if (err)
5295                 goto err_cleanup_tx;
5296
5297         if (profile->enable)
5298                 profile->enable(priv);
5299
5300         return 0;
5301
5302 err_cleanup_tx:
5303         profile->cleanup_tx(priv);
5304
5305 out:
5306         return err;
5307 }
5308
5309 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5310 {
5311         const struct mlx5e_profile *profile = priv->profile;
5312
5313         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5314
5315         if (profile->disable)
5316                 profile->disable(priv);
5317         flush_workqueue(priv->wq);
5318
5319         profile->cleanup_rx(priv);
5320         profile->cleanup_tx(priv);
5321         cancel_work_sync(&priv->update_stats_work);
5322 }
5323
5324 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5325 {
5326         const struct mlx5e_profile *profile = priv->profile;
5327         struct net_device *netdev = priv->netdev;
5328
5329         if (profile->cleanup)
5330                 profile->cleanup(priv);
5331         free_netdev(netdev);
5332 }
5333
5334 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5335  * hardware contexts and to connect it to the current netdev.
5336  */
5337 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5338 {
5339         struct mlx5e_priv *priv = vpriv;
5340         struct net_device *netdev = priv->netdev;
5341         int err;
5342
5343         if (netif_device_present(netdev))
5344                 return 0;
5345
5346         err = mlx5e_create_mdev_resources(mdev);
5347         if (err)
5348                 return err;
5349
5350         err = mlx5e_attach_netdev(priv);
5351         if (err) {
5352                 mlx5e_destroy_mdev_resources(mdev);
5353                 return err;
5354         }
5355
5356         return 0;
5357 }
5358
5359 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5360 {
5361         struct mlx5e_priv *priv = vpriv;
5362         struct net_device *netdev = priv->netdev;
5363
5364 #ifdef CONFIG_MLX5_ESWITCH
5365         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev)
5366                 return;
5367 #endif
5368
5369         if (!netif_device_present(netdev))
5370                 return;
5371
5372         mlx5e_detach_netdev(priv);
5373         mlx5e_destroy_mdev_resources(mdev);
5374 }
5375
5376 static void *mlx5e_add(struct mlx5_core_dev *mdev)
5377 {
5378         struct net_device *netdev;
5379         void *priv;
5380         int err;
5381         int nch;
5382
5383         err = mlx5e_check_required_hca_cap(mdev);
5384         if (err)
5385                 return NULL;
5386
5387 #ifdef CONFIG_MLX5_ESWITCH
5388         if (MLX5_ESWITCH_MANAGER(mdev) &&
5389             mlx5_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) {
5390                 mlx5e_rep_register_vport_reps(mdev);
5391                 return mdev;
5392         }
5393 #endif
5394
5395         nch = mlx5e_get_max_num_channels(mdev);
5396         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, nch, NULL);
5397         if (!netdev) {
5398                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5399                 return NULL;
5400         }
5401
5402         dev_net_set(netdev, mlx5_core_net(mdev));
5403         priv = netdev_priv(netdev);
5404
5405         err = mlx5e_attach(mdev, priv);
5406         if (err) {
5407                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5408                 goto err_destroy_netdev;
5409         }
5410
5411         err = register_netdev(netdev);
5412         if (err) {
5413                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5414                 goto err_detach;
5415         }
5416
5417 #ifdef CONFIG_MLX5_CORE_EN_DCB
5418         mlx5e_dcbnl_init_app(priv);
5419 #endif
5420         return priv;
5421
5422 err_detach:
5423         mlx5e_detach(mdev, priv);
5424 err_destroy_netdev:
5425         mlx5e_destroy_netdev(priv);
5426         return NULL;
5427 }
5428
5429 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5430 {
5431         struct mlx5e_priv *priv;
5432
5433 #ifdef CONFIG_MLX5_ESWITCH
5434         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev) {
5435                 mlx5e_rep_unregister_vport_reps(mdev);
5436                 return;
5437         }
5438 #endif
5439         priv = vpriv;
5440 #ifdef CONFIG_MLX5_CORE_EN_DCB
5441         mlx5e_dcbnl_delete_app(priv);
5442 #endif
5443         unregister_netdev(priv->netdev);
5444         mlx5e_detach(mdev, vpriv);
5445         mlx5e_destroy_netdev(priv);
5446 }
5447
5448 static struct mlx5_interface mlx5e_interface = {
5449         .add       = mlx5e_add,
5450         .remove    = mlx5e_remove,
5451         .attach    = mlx5e_attach,
5452         .detach    = mlx5e_detach,
5453         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
5454 };
5455
5456 void mlx5e_init(void)
5457 {
5458         mlx5e_ipsec_build_inverse_table();
5459         mlx5e_build_ptys2ethtool_map();
5460         mlx5_register_interface(&mlx5e_interface);
5461 }
5462
5463 void mlx5e_cleanup(void)
5464 {
5465         mlx5_unregister_interface(&mlx5e_interface);
5466 }