drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/mlx5/fs.h>
  34 #include <net/vxlan.h>
  35 #include "en.h"
  36 #include "eswitch.h"
  37 #include "vxlan.h"
  38
  39 struct mlx5e_rq_param {
  40         u32                        rqc[MLX5_ST_SZ_DW(rqc)];
  41         struct mlx5_wq_param       wq;
  42 };
  43
  44 struct mlx5e_sq_param {
  45         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  46         struct mlx5_wq_param       wq;
  47         u16                        max_inline;
  48 };
  49
  50 struct mlx5e_cq_param {
  51         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  52         struct mlx5_wq_param       wq;
  53         u16                        eq_ix;
  54 };
  55
  56 struct mlx5e_channel_param {
  57         struct mlx5e_rq_param      rq;
  58         struct mlx5e_sq_param      sq;
  59         struct mlx5e_cq_param      rx_cq;
  60         struct mlx5e_cq_param      tx_cq;
  61 };
  62
  63 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  64 {
  65         struct mlx5_core_dev *mdev = priv->mdev;
  66         u8 port_state;
  67
  68         port_state = mlx5_query_vport_state(mdev,
  69                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
  70
  71         if (port_state == VPORT_STATE_UP)
  72                 netif_carrier_on(priv->netdev);
  73         else
  74                 netif_carrier_off(priv->netdev);
  75 }
  76
  77 static void mlx5e_update_carrier_work(struct work_struct *work)
  78 {
  79         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  80                                                update_carrier_work);
  81
  82         mutex_lock(&priv->state_lock);
  83         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
  84                 mlx5e_update_carrier(priv);
  85         mutex_unlock(&priv->state_lock);
  86 }
  87
  88 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
  89 {
  90         struct mlx5_core_dev *mdev = priv->mdev;
  91         struct mlx5e_pport_stats *s = &priv->stats.pport;
  92         u32 *in;
  93         u32 *out;
  94         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
  95
  96         in  = mlx5_vzalloc(sz);
  97         out = mlx5_vzalloc(sz);
  98         if (!in || !out)
  99                 goto free_out;
 100
 101         MLX5_SET(ppcnt_reg, in, local_port, 1);
 102
 103         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 104         mlx5_core_access_reg(mdev, in, sz, out,
 105                              sz, MLX5_REG_PPCNT, 0, 0);
 106         memcpy(s->IEEE_802_3_counters,
 107                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 108                sizeof(s->IEEE_802_3_counters));
 109
 110         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 111         mlx5_core_access_reg(mdev, in, sz, out,
 112                              sz, MLX5_REG_PPCNT, 0, 0);
 113         memcpy(s->RFC_2863_counters,
 114                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 115                sizeof(s->RFC_2863_counters));
 116
 117         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 118         mlx5_core_access_reg(mdev, in, sz, out,
 119                              sz, MLX5_REG_PPCNT, 0, 0);
 120         memcpy(s->RFC_2819_counters,
 121                MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
 122                sizeof(s->RFC_2819_counters));
 123
 124 free_out:
 125         kvfree(in);
 126         kvfree(out);
 127 }
 128
 129 void mlx5e_update_stats(struct mlx5e_priv *priv)
 130 {
 131         struct mlx5_core_dev *mdev = priv->mdev;
 132         struct mlx5e_vport_stats *s = &priv->stats.vport;
 133         struct mlx5e_rq_stats *rq_stats;
 134         struct mlx5e_sq_stats *sq_stats;
 135         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 136         u32 *out;
 137         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 138         u64 tx_offload_none;
 139         int i, j;
 140
 141         out = mlx5_vzalloc(outlen);
 142         if (!out)
 143                 return;
 144
 145         /* Collect firts the SW counters and then HW for consistency */
 146         s->tso_packets          = 0;
 147         s->tso_bytes            = 0;
 148         s->tx_queue_stopped     = 0;
 149         s->tx_queue_wake        = 0;
 150         s->tx_queue_dropped     = 0;
 151         tx_offload_none         = 0;
 152         s->lro_packets          = 0;
 153         s->lro_bytes            = 0;
 154         s->rx_csum_none         = 0;
 155         s->rx_csum_sw           = 0;
 156         s->rx_wqe_err           = 0;
 157         for (i = 0; i < priv->params.num_channels; i++) {
 158                 rq_stats = &priv->channel[i]->rq.stats;
 159
 160                 s->lro_packets  += rq_stats->lro_packets;
 161                 s->lro_bytes    += rq_stats->lro_bytes;
 162                 s->rx_csum_none += rq_stats->csum_none;
 163                 s->rx_csum_sw   += rq_stats->csum_sw;
 164                 s->rx_wqe_err   += rq_stats->wqe_err;
 165
 166                 for (j = 0; j < priv->params.num_tc; j++) {
 167                         sq_stats = &priv->channel[i]->sq[j].stats;
 168
 169                         s->tso_packets          += sq_stats->tso_packets;
 170                         s->tso_bytes            += sq_stats->tso_bytes;
 171                         s->tx_queue_stopped     += sq_stats->stopped;
 172                         s->tx_queue_wake        += sq_stats->wake;
 173                         s->tx_queue_dropped     += sq_stats->dropped;
 174                         tx_offload_none         += sq_stats->csum_offload_none;
 175                 }
 176         }
 177
 178         /* HW counters */
 179         memset(in, 0, sizeof(in));
 180
 181         MLX5_SET(query_vport_counter_in, in, opcode,
 182                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 183         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 184         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 185
 186         memset(out, 0, outlen);
 187
 188         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 189                 goto free_out;
 190
 191 #define MLX5_GET_CTR(p, x) \
 192         MLX5_GET64(query_vport_counter_out, p, x)
 193
 194         s->rx_error_packets     =
 195                 MLX5_GET_CTR(out, received_errors.packets);
 196         s->rx_error_bytes       =
 197                 MLX5_GET_CTR(out, received_errors.octets);
 198         s->tx_error_packets     =
 199                 MLX5_GET_CTR(out, transmit_errors.packets);
 200         s->tx_error_bytes       =
 201                 MLX5_GET_CTR(out, transmit_errors.octets);
 202
 203         s->rx_unicast_packets   =
 204                 MLX5_GET_CTR(out, received_eth_unicast.packets);
 205         s->rx_unicast_bytes     =
 206                 MLX5_GET_CTR(out, received_eth_unicast.octets);
 207         s->tx_unicast_packets   =
 208                 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 209         s->tx_unicast_bytes     =
 210                 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 211
 212         s->rx_multicast_packets =
 213                 MLX5_GET_CTR(out, received_eth_multicast.packets);
 214         s->rx_multicast_bytes   =
 215                 MLX5_GET_CTR(out, received_eth_multicast.octets);
 216         s->tx_multicast_packets =
 217                 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 218         s->tx_multicast_bytes   =
 219                 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 220
 221         s->rx_broadcast_packets =
 222                 MLX5_GET_CTR(out, received_eth_broadcast.packets);
 223         s->rx_broadcast_bytes   =
 224                 MLX5_GET_CTR(out, received_eth_broadcast.octets);
 225         s->tx_broadcast_packets =
 226                 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 227         s->tx_broadcast_bytes   =
 228                 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 229
 230         s->rx_packets =
 231                 s->rx_unicast_packets +
 232                 s->rx_multicast_packets +
 233                 s->rx_broadcast_packets;
 234         s->rx_bytes =
 235                 s->rx_unicast_bytes +
 236                 s->rx_multicast_bytes +
 237                 s->rx_broadcast_bytes;
 238         s->tx_packets =
 239                 s->tx_unicast_packets +
 240                 s->tx_multicast_packets +
 241                 s->tx_broadcast_packets;
 242         s->tx_bytes =
 243                 s->tx_unicast_bytes +
 244                 s->tx_multicast_bytes +
 245                 s->tx_broadcast_bytes;
 246
 247         /* Update calculated offload counters */
 248         s->tx_csum_offload = s->tx_packets - tx_offload_none;
 249         s->rx_csum_good    = s->rx_packets - s->rx_csum_none -
 250                                s->rx_csum_sw;
 251
 252         mlx5e_update_pport_counters(priv);
 253 free_out:
 254         kvfree(out);
 255 }
 256
 257 static void mlx5e_update_stats_work(struct work_struct *work)
 258 {
 259         struct delayed_work *dwork = to_delayed_work(work);
 260         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 261                                                update_stats_work);
 262         mutex_lock(&priv->state_lock);
 263         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 264                 mlx5e_update_stats(priv);
 265                 schedule_delayed_work(dwork,
 266                                       msecs_to_jiffies(
 267                                               MLX5E_UPDATE_STATS_INTERVAL));
 268         }
 269         mutex_unlock(&priv->state_lock);
 270 }
 271
 272 static void __mlx5e_async_event(struct mlx5e_priv *priv,
 273                                 enum mlx5_dev_event event)
 274 {
 275         switch (event) {
 276         case MLX5_DEV_EVENT_PORT_UP:
 277         case MLX5_DEV_EVENT_PORT_DOWN:
 278                 schedule_work(&priv->update_carrier_work);
 279                 break;
 280
 281         default:
 282                 break;
 283         }
 284 }
 285
 286 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 287                               enum mlx5_dev_event event, unsigned long param)
 288 {
 289         struct mlx5e_priv *priv = vpriv;
 290
 291         spin_lock(&priv->async_events_spinlock);
 292         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 293                 __mlx5e_async_event(priv, event);
 294         spin_unlock(&priv->async_events_spinlock);
 295 }
 296
 297 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 298 {
 299         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 300 }
 301
 302 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 303 {
 304         spin_lock_irq(&priv->async_events_spinlock);
 305         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 306         spin_unlock_irq(&priv->async_events_spinlock);
 307 }
 308
 309 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 310 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 311
 312 static int mlx5e_create_rq(struct mlx5e_channel *c,
 313                            struct mlx5e_rq_param *param,
 314                            struct mlx5e_rq *rq)
 315 {
 316         struct mlx5e_priv *priv = c->priv;
 317         struct mlx5_core_dev *mdev = priv->mdev;
 318         void *rqc = param->rqc;
 319         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 320         int wq_sz;
 321         int err;
 322         int i;
 323
 324         param->wq.db_numa_node = cpu_to_node(c->cpu);
 325
 326         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 327                                 &rq->wq_ctrl);
 328         if (err)
 329                 return err;
 330
 331         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 332
 333         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 334         rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 335                                cpu_to_node(c->cpu));
 336         if (!rq->skb) {
 337                 err = -ENOMEM;
 338                 goto err_rq_wq_destroy;
 339         }
 340
 341         rq->wqe_sz = (priv->params.lro_en) ? priv->params.lro_wqe_sz :
 342                                              MLX5E_SW2HW_MTU(priv->netdev->mtu);
 343         rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN);
 344
 345         for (i = 0; i < wq_sz; i++) {
 346                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 347                 u32 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 348
 349                 wqe->data.lkey       = c->mkey_be;
 350                 wqe->data.byte_count =
 351                         cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 352         }
 353
 354         rq->pdev    = c->pdev;
 355         rq->netdev  = c->netdev;
 356         rq->tstamp  = &priv->tstamp;
 357         rq->channel = c;
 358         rq->ix      = c->ix;
 359         rq->priv    = c->priv;
 360
 361         return 0;
 362
 363 err_rq_wq_destroy:
 364         mlx5_wq_destroy(&rq->wq_ctrl);
 365
 366         return err;
 367 }
 368
 369 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 370 {
 371         kfree(rq->skb);
 372         mlx5_wq_destroy(&rq->wq_ctrl);
 373 }
 374
 375 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 376 {
 377         struct mlx5e_priv *priv = rq->priv;
 378         struct mlx5_core_dev *mdev = priv->mdev;
 379
 380         void *in;
 381         void *rqc;
 382         void *wq;
 383         int inlen;
 384         int err;
 385
 386         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 387                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 388         in = mlx5_vzalloc(inlen);
 389         if (!in)
 390                 return -ENOMEM;
 391
 392         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 393         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 394
 395         memcpy(rqc, param->rqc, sizeof(param->rqc));
 396
 397         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 398         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 399         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
 400         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 401                                                 MLX5_ADAPTER_PAGE_SHIFT);
 402         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 403
 404         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 405                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 406
 407         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 408
 409         kvfree(in);
 410
 411         return err;
 412 }
 413
 414 static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 415 {
 416         struct mlx5e_channel *c = rq->channel;
 417         struct mlx5e_priv *priv = c->priv;
 418         struct mlx5_core_dev *mdev = priv->mdev;
 419
 420         void *in;
 421         void *rqc;
 422         int inlen;
 423         int err;
 424
 425         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 426         in = mlx5_vzalloc(inlen);
 427         if (!in)
 428                 return -ENOMEM;
 429
 430         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 431
 432         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 433         MLX5_SET(rqc, rqc, state, next_state);
 434
 435         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 436
 437         kvfree(in);
 438
 439         return err;
 440 }
 441
 442 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 443 {
 444         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 445 }
 446
 447 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 448 {
 449         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 450         struct mlx5e_channel *c = rq->channel;
 451         struct mlx5e_priv *priv = c->priv;
 452         struct mlx5_wq_ll *wq = &rq->wq;
 453
 454         while (time_before(jiffies, exp_time)) {
 455                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 456                         return 0;
 457
 458                 msleep(20);
 459         }
 460
 461         return -ETIMEDOUT;
 462 }
 463
 464 static int mlx5e_open_rq(struct mlx5e_channel *c,
 465                          struct mlx5e_rq_param *param,
 466                          struct mlx5e_rq *rq)
 467 {
 468         int err;
 469
 470         err = mlx5e_create_rq(c, param, rq);
 471         if (err)
 472                 return err;
 473
 474         err = mlx5e_enable_rq(rq, param);
 475         if (err)
 476                 goto err_destroy_rq;
 477
 478         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 479         if (err)
 480                 goto err_disable_rq;
 481
 482         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 483         mlx5e_send_nop(&c->sq[0], true); /* trigger mlx5e_post_rx_wqes() */
 484
 485         return 0;
 486
 487 err_disable_rq:
 488         mlx5e_disable_rq(rq);
 489 err_destroy_rq:
 490         mlx5e_destroy_rq(rq);
 491
 492         return err;
 493 }
 494
 495 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 496 {
 497         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 498         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 499
 500         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 501         while (!mlx5_wq_ll_is_empty(&rq->wq))
 502                 msleep(20);
 503
 504         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
 505         napi_synchronize(&rq->channel->napi);
 506
 507         mlx5e_disable_rq(rq);
 508         mlx5e_destroy_rq(rq);
 509 }
 510
 511 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 512 {
 513         kfree(sq->wqe_info);
 514         kfree(sq->dma_fifo);
 515         kfree(sq->skb);
 516 }
 517
 518 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 519 {
 520         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 521         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 522
 523         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 524         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 525                                     numa);
 526         sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
 527                                     numa);
 528
 529         if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
 530                 mlx5e_free_sq_db(sq);
 531                 return -ENOMEM;
 532         }
 533
 534         sq->dma_fifo_mask = df_sz - 1;
 535
 536         return 0;
 537 }
 538
 539 static int mlx5e_create_sq(struct mlx5e_channel *c,
 540                            int tc,
 541                            struct mlx5e_sq_param *param,
 542                            struct mlx5e_sq *sq)
 543 {
 544         struct mlx5e_priv *priv = c->priv;
 545         struct mlx5_core_dev *mdev = priv->mdev;
 546
 547         void *sqc = param->sqc;
 548         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 549         int txq_ix;
 550         int err;
 551
 552         err = mlx5_alloc_map_uar(mdev, &sq->uar);
 553         if (err)
 554                 return err;
 555
 556         param->wq.db_numa_node = cpu_to_node(c->cpu);
 557
 558         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 559                                  &sq->wq_ctrl);
 560         if (err)
 561                 goto err_unmap_free_uar;
 562
 563         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 564         sq->uar_map     = sq->uar.map;
 565         sq->uar_bf_map  = sq->uar.bf_map;
 566         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 567         sq->max_inline  = param->max_inline;
 568
 569         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 570         if (err)
 571                 goto err_sq_wq_destroy;
 572
 573         txq_ix = c->ix + tc * priv->params.num_channels;
 574         sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 575
 576         sq->pdev      = c->pdev;
 577         sq->tstamp    = &priv->tstamp;
 578         sq->mkey_be   = c->mkey_be;
 579         sq->channel   = c;
 580         sq->tc        = tc;
 581         sq->edge      = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 582         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 583         priv->txq_to_sq_map[txq_ix] = sq;
 584
 585         return 0;
 586
 587 err_sq_wq_destroy:
 588         mlx5_wq_destroy(&sq->wq_ctrl);
 589
 590 err_unmap_free_uar:
 591         mlx5_unmap_free_uar(mdev, &sq->uar);
 592
 593         return err;
 594 }
 595
 596 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 597 {
 598         struct mlx5e_channel *c = sq->channel;
 599         struct mlx5e_priv *priv = c->priv;
 600
 601         mlx5e_free_sq_db(sq);
 602         mlx5_wq_destroy(&sq->wq_ctrl);
 603         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 604 }
 605
 606 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 607 {
 608         struct mlx5e_channel *c = sq->channel;
 609         struct mlx5e_priv *priv = c->priv;
 610         struct mlx5_core_dev *mdev = priv->mdev;
 611
 612         void *in;
 613         void *sqc;
 614         void *wq;
 615         int inlen;
 616         int err;
 617
 618         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 619                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 620         in = mlx5_vzalloc(inlen);
 621         if (!in)
 622                 return -ENOMEM;
 623
 624         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 625         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 626
 627         memcpy(sqc, param->sqc, sizeof(param->sqc));
 628
 629         MLX5_SET(sqc,  sqc, tis_num_0,          priv->tisn[sq->tc]);
 630         MLX5_SET(sqc,  sqc, cqn,                c->sq[sq->tc].cq.mcq.cqn);
 631         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 632         MLX5_SET(sqc,  sqc, tis_lst_sz,         1);
 633         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 634
 635         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 636         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 637         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 638                                           MLX5_ADAPTER_PAGE_SHIFT);
 639         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 640
 641         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 642                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 643
 644         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 645
 646         kvfree(in);
 647
 648         return err;
 649 }
 650
 651 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
 652 {
 653         struct mlx5e_channel *c = sq->channel;
 654         struct mlx5e_priv *priv = c->priv;
 655         struct mlx5_core_dev *mdev = priv->mdev;
 656
 657         void *in;
 658         void *sqc;
 659         int inlen;
 660         int err;
 661
 662         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 663         in = mlx5_vzalloc(inlen);
 664         if (!in)
 665                 return -ENOMEM;
 666
 667         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 668
 669         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 670         MLX5_SET(sqc, sqc, state, next_state);
 671
 672         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 673
 674         kvfree(in);
 675
 676         return err;
 677 }
 678
 679 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 680 {
 681         struct mlx5e_channel *c = sq->channel;
 682         struct mlx5e_priv *priv = c->priv;
 683         struct mlx5_core_dev *mdev = priv->mdev;
 684
 685         mlx5_core_destroy_sq(mdev, sq->sqn);
 686 }
 687
 688 static int mlx5e_open_sq(struct mlx5e_channel *c,
 689                          int tc,
 690                          struct mlx5e_sq_param *param,
 691                          struct mlx5e_sq *sq)
 692 {
 693         int err;
 694
 695         err = mlx5e_create_sq(c, tc, param, sq);
 696         if (err)
 697                 return err;
 698
 699         err = mlx5e_enable_sq(sq, param);
 700         if (err)
 701                 goto err_destroy_sq;
 702
 703         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
 704         if (err)
 705                 goto err_disable_sq;
 706
 707         set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 708         netdev_tx_reset_queue(sq->txq);
 709         netif_tx_start_queue(sq->txq);
 710
 711         return 0;
 712
 713 err_disable_sq:
 714         mlx5e_disable_sq(sq);
 715 err_destroy_sq:
 716         mlx5e_destroy_sq(sq);
 717
 718         return err;
 719 }
 720
 721 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 722 {
 723         __netif_tx_lock_bh(txq);
 724         netif_tx_stop_queue(txq);
 725         __netif_tx_unlock_bh(txq);
 726 }
 727
 728 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 729 {
 730         clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 731         napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */
 732         netif_tx_disable_queue(sq->txq);
 733
 734         /* ensure hw is notified of all pending wqes */
 735         if (mlx5e_sq_has_room_for(sq, 1))
 736                 mlx5e_send_nop(sq, true);
 737
 738         mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
 739         while (sq->cc != sq->pc) /* wait till sq is empty */
 740                 msleep(20);
 741
 742         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
 743         napi_synchronize(&sq->channel->napi);
 744
 745         mlx5e_disable_sq(sq);
 746         mlx5e_destroy_sq(sq);
 747 }
 748
 749 static int mlx5e_create_cq(struct mlx5e_channel *c,
 750                            struct mlx5e_cq_param *param,
 751                            struct mlx5e_cq *cq)
 752 {
 753         struct mlx5e_priv *priv = c->priv;
 754         struct mlx5_core_dev *mdev = priv->mdev;
 755         struct mlx5_core_cq *mcq = &cq->mcq;
 756         int eqn_not_used;
 757         unsigned int irqn;
 758         int err;
 759         u32 i;
 760
 761         param->wq.buf_numa_node = cpu_to_node(c->cpu);
 762         param->wq.db_numa_node  = cpu_to_node(c->cpu);
 763         param->eq_ix   = c->ix;
 764
 765         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 766                                &cq->wq_ctrl);
 767         if (err)
 768                 return err;
 769
 770         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 771
 772         cq->napi        = &c->napi;
 773
 774         mcq->cqe_sz     = 64;
 775         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 776         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 777         *mcq->set_ci_db = 0;
 778         *mcq->arm_db    = 0;
 779         mcq->vector     = param->eq_ix;
 780         mcq->comp       = mlx5e_completion_event;
 781         mcq->event      = mlx5e_cq_error_event;
 782         mcq->irqn       = irqn;
 783         mcq->uar        = &priv->cq_uar;
 784
 785         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 786                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 787
 788                 cqe->op_own = 0xf1;
 789         }
 790
 791         cq->channel = c;
 792         cq->priv = priv;
 793
 794         return 0;
 795 }
 796
 797 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
 798 {
 799         mlx5_wq_destroy(&cq->wq_ctrl);
 800 }
 801
 802 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
 803 {
 804         struct mlx5e_priv *priv = cq->priv;
 805         struct mlx5_core_dev *mdev = priv->mdev;
 806         struct mlx5_core_cq *mcq = &cq->mcq;
 807
 808         void *in;
 809         void *cqc;
 810         int inlen;
 811         unsigned int irqn_not_used;
 812         int eqn;
 813         int err;
 814
 815         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 816                 sizeof(u64) * cq->wq_ctrl.buf.npages;
 817         in = mlx5_vzalloc(inlen);
 818         if (!in)
 819                 return -ENOMEM;
 820
 821         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
 822
 823         memcpy(cqc, param->cqc, sizeof(param->cqc));
 824
 825         mlx5_fill_page_array(&cq->wq_ctrl.buf,
 826                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
 827
 828         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
 829
 830         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
 831         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
 832         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
 833                                             MLX5_ADAPTER_PAGE_SHIFT);
 834         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
 835
 836         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
 837
 838         kvfree(in);
 839
 840         if (err)
 841                 return err;
 842
 843         mlx5e_cq_arm(cq);
 844
 845         return 0;
 846 }
 847
 848 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
 849 {
 850         struct mlx5e_priv *priv = cq->priv;
 851         struct mlx5_core_dev *mdev = priv->mdev;
 852
 853         mlx5_core_destroy_cq(mdev, &cq->mcq);
 854 }
 855
 856 static int mlx5e_open_cq(struct mlx5e_channel *c,
 857                          struct mlx5e_cq_param *param,
 858                          struct mlx5e_cq *cq,
 859                          u16 moderation_usecs,
 860                          u16 moderation_frames)
 861 {
 862         int err;
 863         struct mlx5e_priv *priv = c->priv;
 864         struct mlx5_core_dev *mdev = priv->mdev;
 865
 866         err = mlx5e_create_cq(c, param, cq);
 867         if (err)
 868                 return err;
 869
 870         err = mlx5e_enable_cq(cq, param);
 871         if (err)
 872                 goto err_destroy_cq;
 873
 874         err = mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
 875                                              moderation_usecs,
 876                                              moderation_frames);
 877         if (err)
 878                 goto err_destroy_cq;
 879
 880         return 0;
 881
 882 err_destroy_cq:
 883         mlx5e_destroy_cq(cq);
 884
 885         return err;
 886 }
 887
 888 static void mlx5e_close_cq(struct mlx5e_cq *cq)
 889 {
 890         mlx5e_disable_cq(cq);
 891         mlx5e_destroy_cq(cq);
 892 }
 893
 894 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
 895 {
 896         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
 897 }
 898
 899 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
 900                              struct mlx5e_channel_param *cparam)
 901 {
 902         struct mlx5e_priv *priv = c->priv;
 903         int err;
 904         int tc;
 905
 906         for (tc = 0; tc < c->num_tc; tc++) {
 907                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
 908                                     priv->params.tx_cq_moderation_usec,
 909                                     priv->params.tx_cq_moderation_pkts);
 910                 if (err)
 911                         goto err_close_tx_cqs;
 912         }
 913
 914         return 0;
 915
 916 err_close_tx_cqs:
 917         for (tc--; tc >= 0; tc--)
 918                 mlx5e_close_cq(&c->sq[tc].cq);
 919
 920         return err;
 921 }
 922
 923 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
 924 {
 925         int tc;
 926
 927         for (tc = 0; tc < c->num_tc; tc++)
 928                 mlx5e_close_cq(&c->sq[tc].cq);
 929 }
 930
 931 static int mlx5e_open_sqs(struct mlx5e_channel *c,
 932                           struct mlx5e_channel_param *cparam)
 933 {
 934         int err;
 935         int tc;
 936
 937         for (tc = 0; tc < c->num_tc; tc++) {
 938                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
 939                 if (err)
 940                         goto err_close_sqs;
 941         }
 942
 943         return 0;
 944
 945 err_close_sqs:
 946         for (tc--; tc >= 0; tc--)
 947                 mlx5e_close_sq(&c->sq[tc]);
 948
 949         return err;
 950 }
 951
 952 static void mlx5e_close_sqs(struct mlx5e_channel *c)
 953 {
 954         int tc;
 955
 956         for (tc = 0; tc < c->num_tc; tc++)
 957                 mlx5e_close_sq(&c->sq[tc]);
 958 }
 959
 960 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
 961 {
 962         int i;
 963
 964         for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
 965                 priv->channeltc_to_txq_map[ix][i] =
 966                         ix + i * priv->params.num_channels;
 967 }
 968
 969 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
 970                               struct mlx5e_channel_param *cparam,
 971                               struct mlx5e_channel **cp)
 972 {
 973         struct net_device *netdev = priv->netdev;
 974         int cpu = mlx5e_get_cpu(priv, ix);
 975         struct mlx5e_channel *c;
 976         int err;
 977
 978         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
 979         if (!c)
 980                 return -ENOMEM;
 981
 982         c->priv     = priv;
 983         c->ix       = ix;
 984         c->cpu      = cpu;
 985         c->pdev     = &priv->mdev->pdev->dev;
 986         c->netdev   = priv->netdev;
 987         c->mkey_be  = cpu_to_be32(priv->mr.key);
 988         c->num_tc   = priv->params.num_tc;
 989
 990         mlx5e_build_channeltc_to_txq_map(priv, ix);
 991
 992         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
 993
 994         err = mlx5e_open_tx_cqs(c, cparam);
 995         if (err)
 996                 goto err_napi_del;
 997
 998         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
 999                             priv->params.rx_cq_moderation_usec,
1000                             priv->params.rx_cq_moderation_pkts);
1001         if (err)
1002                 goto err_close_tx_cqs;
1003
1004         napi_enable(&c->napi);
1005
1006         err = mlx5e_open_sqs(c, cparam);
1007         if (err)
1008                 goto err_disable_napi;
1009
1010         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1011         if (err)
1012                 goto err_close_sqs;
1013
1014         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1015         *cp = c;
1016
1017         return 0;
1018
1019 err_close_sqs:
1020         mlx5e_close_sqs(c);
1021
1022 err_disable_napi:
1023         napi_disable(&c->napi);
1024         mlx5e_close_cq(&c->rq.cq);
1025
1026 err_close_tx_cqs:
1027         mlx5e_close_tx_cqs(c);
1028
1029 err_napi_del:
1030         netif_napi_del(&c->napi);
1031         napi_hash_del(&c->napi);
1032         kfree(c);
1033
1034         return err;
1035 }
1036
1037 static void mlx5e_close_channel(struct mlx5e_channel *c)
1038 {
1039         mlx5e_close_rq(&c->rq);
1040         mlx5e_close_sqs(c);
1041         napi_disable(&c->napi);
1042         mlx5e_close_cq(&c->rq.cq);
1043         mlx5e_close_tx_cqs(c);
1044         netif_napi_del(&c->napi);
1045
1046         napi_hash_del(&c->napi);
1047         synchronize_rcu();
1048
1049         kfree(c);
1050 }
1051
1052 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1053                                  struct mlx5e_rq_param *param)
1054 {
1055         void *rqc = param->rqc;
1056         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1057
1058         MLX5_SET(wq, wq, wq_type,          MLX5_WQ_TYPE_LINKED_LIST);
1059         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1060         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1061         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1062         MLX5_SET(wq, wq, pd,               priv->pdn);
1063
1064         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1065         param->wq.linear = 1;
1066 }
1067
1068 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1069                                  struct mlx5e_sq_param *param)
1070 {
1071         void *sqc = param->sqc;
1072         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1073
1074         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1075         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1076         MLX5_SET(wq, wq, pd,            priv->pdn);
1077
1078         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1079         param->max_inline = priv->params.tx_max_inline;
1080 }
1081
1082 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1083                                         struct mlx5e_cq_param *param)
1084 {
1085         void *cqc = param->cqc;
1086
1087         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1088 }
1089
1090 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1091                                     struct mlx5e_cq_param *param)
1092 {
1093         void *cqc = param->cqc;
1094
1095         MLX5_SET(cqc, cqc, log_cq_size,  priv->params.log_rq_size);
1096
1097         mlx5e_build_common_cq_param(priv, param);
1098 }
1099
1100 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1101                                     struct mlx5e_cq_param *param)
1102 {
1103         void *cqc = param->cqc;
1104
1105         MLX5_SET(cqc, cqc, log_cq_size,  priv->params.log_sq_size);
1106
1107         mlx5e_build_common_cq_param(priv, param);
1108 }
1109
1110 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1111                                       struct mlx5e_channel_param *cparam)
1112 {
1113         memset(cparam, 0, sizeof(*cparam));
1114
1115         mlx5e_build_rq_param(priv, &cparam->rq);
1116         mlx5e_build_sq_param(priv, &cparam->sq);
1117         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1118         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1119 }
1120
1121 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1122 {
1123         struct mlx5e_channel_param cparam;
1124         int nch = priv->params.num_channels;
1125         int err = -ENOMEM;
1126         int i;
1127         int j;
1128
1129         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1130                                 GFP_KERNEL);
1131
1132         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1133                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1134
1135         if (!priv->channel || !priv->txq_to_sq_map)
1136                 goto err_free_txq_to_sq_map;
1137
1138         mlx5e_build_channel_param(priv, &cparam);
1139         for (i = 0; i < nch; i++) {
1140                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1141                 if (err)
1142                         goto err_close_channels;
1143         }
1144
1145         for (j = 0; j < nch; j++) {
1146                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1147                 if (err)
1148                         goto err_close_channels;
1149         }
1150
1151         return 0;
1152
1153 err_close_channels:
1154         for (i--; i >= 0; i--)
1155                 mlx5e_close_channel(priv->channel[i]);
1156
1157 err_free_txq_to_sq_map:
1158         kfree(priv->txq_to_sq_map);
1159         kfree(priv->channel);
1160
1161         return err;
1162 }
1163
1164 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1165 {
1166         int i;
1167
1168         for (i = 0; i < priv->params.num_channels; i++)
1169                 mlx5e_close_channel(priv->channel[i]);
1170
1171         kfree(priv->txq_to_sq_map);
1172         kfree(priv->channel);
1173 }
1174
1175 static int mlx5e_rx_hash_fn(int hfunc)
1176 {
1177         return (hfunc == ETH_RSS_HASH_TOP) ?
1178                MLX5_RX_HASH_FN_TOEPLITZ :
1179                MLX5_RX_HASH_FN_INVERTED_XOR8;
1180 }
1181
1182 static int mlx5e_bits_invert(unsigned long a, int size)
1183 {
1184         int inv = 0;
1185         int i;
1186
1187         for (i = 0; i < size; i++)
1188                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1189
1190         return inv;
1191 }
1192
1193 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1194 {
1195         int i;
1196
1197         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1198                 int ix = i;
1199
1200                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1201                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1202
1203                 ix = priv->params.indirection_rqt[ix];
1204                 ix = ix % priv->params.num_channels;
1205                 MLX5_SET(rqtc, rqtc, rq_num[i],
1206                          test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1207                          priv->channel[ix]->rq.rqn :
1208                          priv->drop_rq.rqn);
1209         }
1210 }
1211
1212 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc,
1213                                 enum mlx5e_rqt_ix rqt_ix)
1214 {
1215
1216         switch (rqt_ix) {
1217         case MLX5E_INDIRECTION_RQT:
1218                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1219
1220                 break;
1221
1222         default: /* MLX5E_SINGLE_RQ_RQT */
1223                 MLX5_SET(rqtc, rqtc, rq_num[0],
1224                          test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1225                          priv->channel[0]->rq.rqn :
1226                          priv->drop_rq.rqn);
1227
1228                 break;
1229         }
1230 }
1231
1232 static int mlx5e_create_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1233 {
1234         struct mlx5_core_dev *mdev = priv->mdev;
1235         u32 *in;
1236         void *rqtc;
1237         int inlen;
1238         int sz;
1239         int err;
1240
1241         sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1242
1243         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1244         in = mlx5_vzalloc(inlen);
1245         if (!in)
1246                 return -ENOMEM;
1247
1248         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1249
1250         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1251         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1252
1253         mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1254
1255         err = mlx5_core_create_rqt(mdev, in, inlen, &priv->rqtn[rqt_ix]);
1256
1257         kvfree(in);
1258
1259         return err;
1260 }
1261
1262 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1263 {
1264         struct mlx5_core_dev *mdev = priv->mdev;
1265         u32 *in;
1266         void *rqtc;
1267         int inlen;
1268         int sz;
1269         int err;
1270
1271         sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE;
1272
1273         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1274         in = mlx5_vzalloc(inlen);
1275         if (!in)
1276                 return -ENOMEM;
1277
1278         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1279
1280         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1281
1282         mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1283
1284         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1285
1286         err = mlx5_core_modify_rqt(mdev, priv->rqtn[rqt_ix], in, inlen);
1287
1288         kvfree(in);
1289
1290         return err;
1291 }
1292
1293 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1294 {
1295         mlx5_core_destroy_rqt(priv->mdev, priv->rqtn[rqt_ix]);
1296 }
1297
1298 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1299 {
1300         mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT);
1301         mlx5e_redirect_rqt(priv, MLX5E_SINGLE_RQ_RQT);
1302 }
1303
1304 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1305 {
1306         if (!priv->params.lro_en)
1307                 return;
1308
1309 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1310
1311         MLX5_SET(tirc, tirc, lro_enable_mask,
1312                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1313                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1314         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1315                  (priv->params.lro_wqe_sz -
1316                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1317         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1318                  MLX5_CAP_ETH(priv->mdev,
1319                               lro_timer_supported_periods[2]));
1320 }
1321
1322 static int mlx5e_modify_tir_lro(struct mlx5e_priv *priv, int tt)
1323 {
1324         struct mlx5_core_dev *mdev = priv->mdev;
1325
1326         void *in;
1327         void *tirc;
1328         int inlen;
1329         int err;
1330
1331         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1332         in = mlx5_vzalloc(inlen);
1333         if (!in)
1334                 return -ENOMEM;
1335
1336         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1337         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1338
1339         mlx5e_build_tir_ctx_lro(tirc, priv);
1340
1341         err = mlx5_core_modify_tir(mdev, priv->tirn[tt], in, inlen);
1342
1343         kvfree(in);
1344
1345         return err;
1346 }
1347
1348 static int mlx5e_refresh_tir_self_loopback_enable(struct mlx5_core_dev *mdev,
1349                                                   u32 tirn)
1350 {
1351         void *in;
1352         int inlen;
1353         int err;
1354
1355         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1356         in = mlx5_vzalloc(inlen);
1357         if (!in)
1358                 return -ENOMEM;
1359
1360         MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1361
1362         err = mlx5_core_modify_tir(mdev, tirn, in, inlen);
1363
1364         kvfree(in);
1365
1366         return err;
1367 }
1368
1369 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1370 {
1371         int err;
1372         int i;
1373
1374         for (i = 0; i < MLX5E_NUM_TT; i++) {
1375                 err = mlx5e_refresh_tir_self_loopback_enable(priv->mdev,
1376                                                              priv->tirn[i]);
1377                 if (err)
1378                         return err;
1379         }
1380
1381         return 0;
1382 }
1383
1384 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1385 {
1386         struct mlx5e_priv *priv = netdev_priv(netdev);
1387         struct mlx5_core_dev *mdev = priv->mdev;
1388         int hw_mtu;
1389         int err;
1390
1391         err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1392         if (err)
1393                 return err;
1394
1395         mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1396
1397         if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1398                 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1399                             __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1400
1401         netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1402         return 0;
1403 }
1404
1405 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1406 {
1407         struct mlx5e_priv *priv = netdev_priv(netdev);
1408         int nch = priv->params.num_channels;
1409         int ntc = priv->params.num_tc;
1410         int tc;
1411
1412         netdev_reset_tc(netdev);
1413
1414         if (ntc == 1)
1415                 return;
1416
1417         netdev_set_num_tc(netdev, ntc);
1418
1419         for (tc = 0; tc < ntc; tc++)
1420                 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1421 }
1422
1423 int mlx5e_open_locked(struct net_device *netdev)
1424 {
1425         struct mlx5e_priv *priv = netdev_priv(netdev);
1426         int num_txqs;
1427         int err;
1428
1429         set_bit(MLX5E_STATE_OPENED, &priv->state);
1430
1431         mlx5e_netdev_set_tcs(netdev);
1432
1433         num_txqs = priv->params.num_channels * priv->params.num_tc;
1434         netif_set_real_num_tx_queues(netdev, num_txqs);
1435         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1436
1437         err = mlx5e_set_dev_port_mtu(netdev);
1438         if (err)
1439                 goto err_clear_state_opened_flag;
1440
1441         err = mlx5e_open_channels(priv);
1442         if (err) {
1443                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1444                            __func__, err);
1445                 goto err_clear_state_opened_flag;
1446         }
1447
1448         err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1449         if (err) {
1450                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1451                            __func__, err);
1452                 goto err_close_channels;
1453         }
1454
1455         mlx5e_update_carrier(priv);
1456         mlx5e_redirect_rqts(priv);
1457         mlx5e_timestamp_init(priv);
1458
1459         schedule_delayed_work(&priv->update_stats_work, 0);
1460
1461         return 0;
1462
1463 err_close_channels:
1464         mlx5e_close_channels(priv);
1465 err_clear_state_opened_flag:
1466         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1467         return err;
1468 }
1469
1470 static int mlx5e_open(struct net_device *netdev)
1471 {
1472         struct mlx5e_priv *priv = netdev_priv(netdev);
1473         int err;
1474
1475         mutex_lock(&priv->state_lock);
1476         err = mlx5e_open_locked(netdev);
1477         mutex_unlock(&priv->state_lock);
1478
1479         return err;
1480 }
1481
1482 int mlx5e_close_locked(struct net_device *netdev)
1483 {
1484         struct mlx5e_priv *priv = netdev_priv(netdev);
1485
1486         /* May already be CLOSED in case a previous configuration operation
1487          * (e.g RX/TX queue size change) that involves close&open failed.
1488          */
1489         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1490                 return 0;
1491
1492         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1493
1494         mlx5e_timestamp_cleanup(priv);
1495         mlx5e_redirect_rqts(priv);
1496         netif_carrier_off(priv->netdev);
1497         mlx5e_close_channels(priv);
1498
1499         return 0;
1500 }
1501
1502 static int mlx5e_close(struct net_device *netdev)
1503 {
1504         struct mlx5e_priv *priv = netdev_priv(netdev);
1505         int err;
1506
1507         mutex_lock(&priv->state_lock);
1508         err = mlx5e_close_locked(netdev);
1509         mutex_unlock(&priv->state_lock);
1510
1511         return err;
1512 }
1513
1514 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1515                                 struct mlx5e_rq *rq,
1516                                 struct mlx5e_rq_param *param)
1517 {
1518         struct mlx5_core_dev *mdev = priv->mdev;
1519         void *rqc = param->rqc;
1520         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1521         int err;
1522
1523         param->wq.db_numa_node = param->wq.buf_numa_node;
1524
1525         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1526                                 &rq->wq_ctrl);
1527         if (err)
1528                 return err;
1529
1530         rq->priv = priv;
1531
1532         return 0;
1533 }
1534
1535 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1536                                 struct mlx5e_cq *cq,
1537                                 struct mlx5e_cq_param *param)
1538 {
1539         struct mlx5_core_dev *mdev = priv->mdev;
1540         struct mlx5_core_cq *mcq = &cq->mcq;
1541         int eqn_not_used;
1542         unsigned int irqn;
1543         int err;
1544
1545         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1546                                &cq->wq_ctrl);
1547         if (err)
1548                 return err;
1549
1550         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1551
1552         mcq->cqe_sz     = 64;
1553         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1554         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1555         *mcq->set_ci_db = 0;
1556         *mcq->arm_db    = 0;
1557         mcq->vector     = param->eq_ix;
1558         mcq->comp       = mlx5e_completion_event;
1559         mcq->event      = mlx5e_cq_error_event;
1560         mcq->irqn       = irqn;
1561         mcq->uar        = &priv->cq_uar;
1562
1563         cq->priv = priv;
1564
1565         return 0;
1566 }
1567
1568 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1569 {
1570         struct mlx5e_cq_param cq_param;
1571         struct mlx5e_rq_param rq_param;
1572         struct mlx5e_rq *rq = &priv->drop_rq;
1573         struct mlx5e_cq *cq = &priv->drop_rq.cq;
1574         int err;
1575
1576         memset(&cq_param, 0, sizeof(cq_param));
1577         memset(&rq_param, 0, sizeof(rq_param));
1578         mlx5e_build_rx_cq_param(priv, &cq_param);
1579         mlx5e_build_rq_param(priv, &rq_param);
1580
1581         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1582         if (err)
1583                 return err;
1584
1585         err = mlx5e_enable_cq(cq, &cq_param);
1586         if (err)
1587                 goto err_destroy_cq;
1588
1589         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1590         if (err)
1591                 goto err_disable_cq;
1592
1593         err = mlx5e_enable_rq(rq, &rq_param);
1594         if (err)
1595                 goto err_destroy_rq;
1596
1597         return 0;
1598
1599 err_destroy_rq:
1600         mlx5e_destroy_rq(&priv->drop_rq);
1601
1602 err_disable_cq:
1603         mlx5e_disable_cq(&priv->drop_rq.cq);
1604
1605 err_destroy_cq:
1606         mlx5e_destroy_cq(&priv->drop_rq.cq);
1607
1608         return err;
1609 }
1610
1611 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1612 {
1613         mlx5e_disable_rq(&priv->drop_rq);
1614         mlx5e_destroy_rq(&priv->drop_rq);
1615         mlx5e_disable_cq(&priv->drop_rq.cq);
1616         mlx5e_destroy_cq(&priv->drop_rq.cq);
1617 }
1618
1619 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1620 {
1621         struct mlx5_core_dev *mdev = priv->mdev;
1622         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1623         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1624
1625         memset(in, 0, sizeof(in));
1626
1627         MLX5_SET(tisc, tisc, prio, tc << 1);
1628         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1629
1630         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1631 }
1632
1633 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1634 {
1635         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1636 }
1637
1638 static int mlx5e_create_tises(struct mlx5e_priv *priv)
1639 {
1640         int err;
1641         int tc;
1642
1643         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
1644                 err = mlx5e_create_tis(priv, tc);
1645                 if (err)
1646                         goto err_close_tises;
1647         }
1648
1649         return 0;
1650
1651 err_close_tises:
1652         for (tc--; tc >= 0; tc--)
1653                 mlx5e_destroy_tis(priv, tc);
1654
1655         return err;
1656 }
1657
1658 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1659 {
1660         int tc;
1661
1662         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
1663                 mlx5e_destroy_tis(priv, tc);
1664 }
1665
1666 static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1667 {
1668         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1669
1670         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1671
1672 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1673                                  MLX5_HASH_FIELD_SEL_DST_IP)
1674
1675 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1676                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1677                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
1678                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
1679
1680 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1681                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1682                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1683
1684         mlx5e_build_tir_ctx_lro(tirc, priv);
1685
1686         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1687
1688         switch (tt) {
1689         case MLX5E_TT_ANY:
1690                 MLX5_SET(tirc, tirc, indirect_table,
1691                          priv->rqtn[MLX5E_SINGLE_RQ_RQT]);
1692                 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
1693                 break;
1694         default:
1695                 MLX5_SET(tirc, tirc, indirect_table,
1696                          priv->rqtn[MLX5E_INDIRECTION_RQT]);
1697                 MLX5_SET(tirc, tirc, rx_hash_fn,
1698                          mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1699                 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1700                         void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1701                                                      rx_hash_toeplitz_key);
1702                         size_t len = MLX5_FLD_SZ_BYTES(tirc,
1703                                                        rx_hash_toeplitz_key);
1704
1705                         MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1706                         memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1707                 }
1708                 break;
1709         }
1710
1711         switch (tt) {
1712         case MLX5E_TT_IPV4_TCP:
1713                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1714                          MLX5_L3_PROT_TYPE_IPV4);
1715                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1716                          MLX5_L4_PROT_TYPE_TCP);
1717                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1718                          MLX5_HASH_IP_L4PORTS);
1719                 break;
1720
1721         case MLX5E_TT_IPV6_TCP:
1722                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1723                          MLX5_L3_PROT_TYPE_IPV6);
1724                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1725                          MLX5_L4_PROT_TYPE_TCP);
1726                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1727                          MLX5_HASH_IP_L4PORTS);
1728                 break;
1729
1730         case MLX5E_TT_IPV4_UDP:
1731                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1732                          MLX5_L3_PROT_TYPE_IPV4);
1733                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1734                          MLX5_L4_PROT_TYPE_UDP);
1735                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1736                          MLX5_HASH_IP_L4PORTS);
1737                 break;
1738
1739         case MLX5E_TT_IPV6_UDP:
1740                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1741                          MLX5_L3_PROT_TYPE_IPV6);
1742                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1743                          MLX5_L4_PROT_TYPE_UDP);
1744                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1745                          MLX5_HASH_IP_L4PORTS);
1746                 break;
1747
1748         case MLX5E_TT_IPV4_IPSEC_AH:
1749                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1750                          MLX5_L3_PROT_TYPE_IPV4);
1751                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1752                          MLX5_HASH_IP_IPSEC_SPI);
1753                 break;
1754
1755         case MLX5E_TT_IPV6_IPSEC_AH:
1756                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1757                          MLX5_L3_PROT_TYPE_IPV6);
1758                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1759                          MLX5_HASH_IP_IPSEC_SPI);
1760                 break;
1761
1762         case MLX5E_TT_IPV4_IPSEC_ESP:
1763                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1764                          MLX5_L3_PROT_TYPE_IPV4);
1765                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1766                          MLX5_HASH_IP_IPSEC_SPI);
1767                 break;
1768
1769         case MLX5E_TT_IPV6_IPSEC_ESP:
1770                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1771                          MLX5_L3_PROT_TYPE_IPV6);
1772                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1773                          MLX5_HASH_IP_IPSEC_SPI);
1774                 break;
1775
1776         case MLX5E_TT_IPV4:
1777                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1778                          MLX5_L3_PROT_TYPE_IPV4);
1779                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1780                          MLX5_HASH_IP);
1781                 break;
1782
1783         case MLX5E_TT_IPV6:
1784                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1785                          MLX5_L3_PROT_TYPE_IPV6);
1786                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1787                          MLX5_HASH_IP);
1788                 break;
1789         }
1790 }
1791
1792 static int mlx5e_create_tir(struct mlx5e_priv *priv, int tt)
1793 {
1794         struct mlx5_core_dev *mdev = priv->mdev;
1795         u32 *in;
1796         void *tirc;
1797         int inlen;
1798         int err;
1799
1800         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1801         in = mlx5_vzalloc(inlen);
1802         if (!in)
1803                 return -ENOMEM;
1804
1805         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1806
1807         mlx5e_build_tir_ctx(priv, tirc, tt);
1808
1809         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
1810
1811         kvfree(in);
1812
1813         return err;
1814 }
1815
1816 static void mlx5e_destroy_tir(struct mlx5e_priv *priv, int tt)
1817 {
1818         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
1819 }
1820
1821 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
1822 {
1823         int err;
1824         int i;
1825
1826         for (i = 0; i < MLX5E_NUM_TT; i++) {
1827                 err = mlx5e_create_tir(priv, i);
1828                 if (err)
1829                         goto err_destroy_tirs;
1830         }
1831
1832         return 0;
1833
1834 err_destroy_tirs:
1835         for (i--; i >= 0; i--)
1836                 mlx5e_destroy_tir(priv, i);
1837
1838         return err;
1839 }
1840
1841 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
1842 {
1843         int i;
1844
1845         for (i = 0; i < MLX5E_NUM_TT; i++)
1846                 mlx5e_destroy_tir(priv, i);
1847 }
1848
1849 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
1850 {
1851         struct mlx5e_priv *priv = netdev_priv(netdev);
1852         bool was_opened;
1853         int err = 0;
1854
1855         if (tc && tc != MLX5E_MAX_NUM_TC)
1856                 return -EINVAL;
1857
1858         mutex_lock(&priv->state_lock);
1859
1860         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1861         if (was_opened)
1862                 mlx5e_close_locked(priv->netdev);
1863
1864         priv->params.num_tc = tc ? tc : 1;
1865
1866         if (was_opened)
1867                 err = mlx5e_open_locked(priv->netdev);
1868
1869         mutex_unlock(&priv->state_lock);
1870
1871         return err;
1872 }
1873
1874 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
1875                               __be16 proto, struct tc_to_netdev *tc)
1876 {
1877         if (handle != TC_H_ROOT || tc->type != TC_SETUP_MQPRIO)
1878                 return -EINVAL;
1879
1880         return mlx5e_setup_tc(dev, tc->tc);
1881 }
1882
1883 static struct rtnl_link_stats64 *
1884 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
1885 {
1886         struct mlx5e_priv *priv = netdev_priv(dev);
1887         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
1888
1889         stats->rx_packets = vstats->rx_packets;
1890         stats->rx_bytes   = vstats->rx_bytes;
1891         stats->tx_packets = vstats->tx_packets;
1892         stats->tx_bytes   = vstats->tx_bytes;
1893         stats->multicast  = vstats->rx_multicast_packets +
1894                             vstats->tx_multicast_packets;
1895         stats->tx_errors  = vstats->tx_error_packets;
1896         stats->rx_errors  = vstats->rx_error_packets;
1897         stats->tx_dropped = vstats->tx_queue_dropped;
1898         stats->rx_crc_errors = 0;
1899         stats->rx_length_errors = 0;
1900
1901         return stats;
1902 }
1903
1904 static void mlx5e_set_rx_mode(struct net_device *dev)
1905 {
1906         struct mlx5e_priv *priv = netdev_priv(dev);
1907
1908         schedule_work(&priv->set_rx_mode_work);
1909 }
1910
1911 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
1912 {
1913         struct mlx5e_priv *priv = netdev_priv(netdev);
1914         struct sockaddr *saddr = addr;
1915
1916         if (!is_valid_ether_addr(saddr->sa_data))
1917                 return -EADDRNOTAVAIL;
1918
1919         netif_addr_lock_bh(netdev);
1920         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
1921         netif_addr_unlock_bh(netdev);
1922
1923         schedule_work(&priv->set_rx_mode_work);
1924
1925         return 0;
1926 }
1927
1928 static int mlx5e_set_features(struct net_device *netdev,
1929                               netdev_features_t features)
1930 {
1931         struct mlx5e_priv *priv = netdev_priv(netdev);
1932         int err = 0;
1933         netdev_features_t changes = features ^ netdev->features;
1934
1935         mutex_lock(&priv->state_lock);
1936
1937         if (changes & NETIF_F_LRO) {
1938                 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1939
1940                 if (was_opened)
1941                         mlx5e_close_locked(priv->netdev);
1942
1943                 priv->params.lro_en = !!(features & NETIF_F_LRO);
1944                 mlx5e_modify_tir_lro(priv, MLX5E_TT_IPV4_TCP);
1945                 mlx5e_modify_tir_lro(priv, MLX5E_TT_IPV6_TCP);
1946
1947                 if (was_opened)
1948                         err = mlx5e_open_locked(priv->netdev);
1949         }
1950
1951         mutex_unlock(&priv->state_lock);
1952
1953         if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
1954                 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1955                         mlx5e_enable_vlan_filter(priv);
1956                 else
1957                         mlx5e_disable_vlan_filter(priv);
1958         }
1959
1960         return err;
1961 }
1962
1963 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
1964 {
1965         struct mlx5e_priv *priv = netdev_priv(netdev);
1966         struct mlx5_core_dev *mdev = priv->mdev;
1967         bool was_opened;
1968         int max_mtu;
1969         int err = 0;
1970
1971         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
1972
1973         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
1974
1975         if (new_mtu > max_mtu) {
1976                 netdev_err(netdev,
1977                            "%s: Bad MTU (%d) > (%d) Max\n",
1978                            __func__, new_mtu, max_mtu);
1979                 return -EINVAL;
1980         }
1981
1982         mutex_lock(&priv->state_lock);
1983
1984         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1985         if (was_opened)
1986                 mlx5e_close_locked(netdev);
1987
1988         netdev->mtu = new_mtu;
1989
1990         if (was_opened)
1991                 err = mlx5e_open_locked(netdev);
1992
1993         mutex_unlock(&priv->state_lock);
1994
1995         return err;
1996 }
1997
1998 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1999 {
2000         switch (cmd) {
2001         case SIOCSHWTSTAMP:
2002                 return mlx5e_hwstamp_set(dev, ifr);
2003         case SIOCGHWTSTAMP:
2004                 return mlx5e_hwstamp_get(dev, ifr);
2005         default:
2006                 return -EOPNOTSUPP;
2007         }
2008 }
2009
2010 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2011 {
2012         struct mlx5e_priv *priv = netdev_priv(dev);
2013         struct mlx5_core_dev *mdev = priv->mdev;
2014
2015         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2016 }
2017
2018 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2019 {
2020         struct mlx5e_priv *priv = netdev_priv(dev);
2021         struct mlx5_core_dev *mdev = priv->mdev;
2022
2023         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2024                                            vlan, qos);
2025 }
2026
2027 static int mlx5_vport_link2ifla(u8 esw_link)
2028 {
2029         switch (esw_link) {
2030         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2031                 return IFLA_VF_LINK_STATE_DISABLE;
2032         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2033                 return IFLA_VF_LINK_STATE_ENABLE;
2034         }
2035         return IFLA_VF_LINK_STATE_AUTO;
2036 }
2037
2038 static int mlx5_ifla_link2vport(u8 ifla_link)
2039 {
2040         switch (ifla_link) {
2041         case IFLA_VF_LINK_STATE_DISABLE:
2042                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2043         case IFLA_VF_LINK_STATE_ENABLE:
2044                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2045         }
2046         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2047 }
2048
2049 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2050                                    int link_state)
2051 {
2052         struct mlx5e_priv *priv = netdev_priv(dev);
2053         struct mlx5_core_dev *mdev = priv->mdev;
2054
2055         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2056                                             mlx5_ifla_link2vport(link_state));
2057 }
2058
2059 static int mlx5e_get_vf_config(struct net_device *dev,
2060                                int vf, struct ifla_vf_info *ivi)
2061 {
2062         struct mlx5e_priv *priv = netdev_priv(dev);
2063         struct mlx5_core_dev *mdev = priv->mdev;
2064         int err;
2065
2066         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2067         if (err)
2068                 return err;
2069         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2070         return 0;
2071 }
2072
2073 static int mlx5e_get_vf_stats(struct net_device *dev,
2074                               int vf, struct ifla_vf_stats *vf_stats)
2075 {
2076         struct mlx5e_priv *priv = netdev_priv(dev);
2077         struct mlx5_core_dev *mdev = priv->mdev;
2078
2079         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2080                                             vf_stats);
2081 }
2082
2083 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2084                                  sa_family_t sa_family, __be16 port)
2085 {
2086         struct mlx5e_priv *priv = netdev_priv(netdev);
2087
2088         if (!mlx5e_vxlan_allowed(priv->mdev))
2089                 return;
2090
2091         mlx5e_vxlan_add_port(priv, be16_to_cpu(port));
2092 }
2093
2094 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2095                                  sa_family_t sa_family, __be16 port)
2096 {
2097         struct mlx5e_priv *priv = netdev_priv(netdev);
2098
2099         if (!mlx5e_vxlan_allowed(priv->mdev))
2100                 return;
2101
2102         mlx5e_vxlan_del_port(priv, be16_to_cpu(port));
2103 }
2104
2105 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2106                                                     struct sk_buff *skb,
2107                                                     netdev_features_t features)
2108 {
2109         struct udphdr *udph;
2110         u16 proto;
2111         u16 port = 0;
2112
2113         switch (vlan_get_protocol(skb)) {
2114         case htons(ETH_P_IP):
2115                 proto = ip_hdr(skb)->protocol;
2116                 break;
2117         case htons(ETH_P_IPV6):
2118                 proto = ipv6_hdr(skb)->nexthdr;
2119                 break;
2120         default:
2121                 goto out;
2122         }
2123
2124         if (proto == IPPROTO_UDP) {
2125                 udph = udp_hdr(skb);
2126                 port = be16_to_cpu(udph->dest);
2127         }
2128
2129         /* Verify if UDP port is being offloaded by HW */
2130         if (port && mlx5e_vxlan_lookup_port(priv, port))
2131                 return features;
2132
2133 out:
2134         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2135         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2136 }
2137
2138 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2139                                               struct net_device *netdev,
2140                                               netdev_features_t features)
2141 {
2142         struct mlx5e_priv *priv = netdev_priv(netdev);
2143
2144         features = vlan_features_check(skb, features);
2145         features = vxlan_features_check(skb, features);
2146
2147         /* Validate if the tunneled packet is being offloaded by HW */
2148         if (skb->encapsulation &&
2149             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2150                 return mlx5e_vxlan_features_check(priv, skb, features);
2151
2152         return features;
2153 }
2154
2155 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2156         .ndo_open                = mlx5e_open,
2157         .ndo_stop                = mlx5e_close,
2158         .ndo_start_xmit          = mlx5e_xmit,
2159         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2160         .ndo_select_queue        = mlx5e_select_queue,
2161         .ndo_get_stats64         = mlx5e_get_stats,
2162         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2163         .ndo_set_mac_address     = mlx5e_set_mac,
2164         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2165         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2166         .ndo_set_features        = mlx5e_set_features,
2167         .ndo_change_mtu          = mlx5e_change_mtu,
2168         .ndo_do_ioctl            = mlx5e_ioctl,
2169 };
2170
2171 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2172         .ndo_open                = mlx5e_open,
2173         .ndo_stop                = mlx5e_close,
2174         .ndo_start_xmit          = mlx5e_xmit,
2175         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2176         .ndo_select_queue        = mlx5e_select_queue,
2177         .ndo_get_stats64         = mlx5e_get_stats,
2178         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2179         .ndo_set_mac_address     = mlx5e_set_mac,
2180         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2181         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2182         .ndo_set_features        = mlx5e_set_features,
2183         .ndo_change_mtu          = mlx5e_change_mtu,
2184         .ndo_do_ioctl            = mlx5e_ioctl,
2185         .ndo_add_vxlan_port      = mlx5e_add_vxlan_port,
2186         .ndo_del_vxlan_port      = mlx5e_del_vxlan_port,
2187         .ndo_features_check      = mlx5e_features_check,
2188         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
2189         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
2190         .ndo_get_vf_config       = mlx5e_get_vf_config,
2191         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
2192         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
2193 };
2194
2195 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2196 {
2197         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2198                 return -ENOTSUPP;
2199         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2200             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2201             !MLX5_CAP_ETH(mdev, csum_cap) ||
2202             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2203             !MLX5_CAP_ETH(mdev, vlan_cap) ||
2204             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2205             MLX5_CAP_FLOWTABLE(mdev,
2206                                flow_table_properties_nic_receive.max_ft_level)
2207                                < 3) {
2208                 mlx5_core_warn(mdev,
2209                                "Not creating net device, some required device capabilities are missing\n");
2210                 return -ENOTSUPP;
2211         }
2212         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2213                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2214
2215         return 0;
2216 }
2217
2218 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2219 {
2220         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2221
2222         return bf_buf_size -
2223                sizeof(struct mlx5e_tx_wqe) +
2224                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2225 }
2226
2227 #ifdef CONFIG_MLX5_CORE_EN_DCB
2228 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2229 {
2230         int i;
2231
2232         priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2233         for (i = 0; i < priv->params.ets.ets_cap; i++) {
2234                 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2235                 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2236                 priv->params.ets.prio_tc[i] = i;
2237         }
2238
2239         /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2240         priv->params.ets.prio_tc[0] = 1;
2241         priv->params.ets.prio_tc[1] = 0;
2242 }
2243 #endif
2244
2245 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2246                                     struct net_device *netdev,
2247                                     int num_channels)
2248 {
2249         struct mlx5e_priv *priv = netdev_priv(netdev);
2250         int i;
2251
2252         priv->params.log_sq_size           =
2253                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2254         priv->params.log_rq_size           =
2255                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2256         priv->params.rx_cq_moderation_usec =
2257                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2258         priv->params.rx_cq_moderation_pkts =
2259                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2260         priv->params.tx_cq_moderation_usec =
2261                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2262         priv->params.tx_cq_moderation_pkts =
2263                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2264         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
2265         priv->params.min_rx_wqes           =
2266                 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
2267         priv->params.num_tc                = 1;
2268         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
2269
2270         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2271                             sizeof(priv->params.toeplitz_hash_key));
2272
2273         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++)
2274                 priv->params.indirection_rqt[i] = i % num_channels;
2275
2276         priv->params.lro_wqe_sz            =
2277                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2278
2279         priv->mdev                         = mdev;
2280         priv->netdev                       = netdev;
2281         priv->params.num_channels          = num_channels;
2282
2283 #ifdef CONFIG_MLX5_CORE_EN_DCB
2284         mlx5e_ets_init(priv);
2285 #endif
2286
2287         spin_lock_init(&priv->async_events_spinlock);
2288         mutex_init(&priv->state_lock);
2289
2290         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2291         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2292         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2293 }
2294
2295 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2296 {
2297         struct mlx5e_priv *priv = netdev_priv(netdev);
2298
2299         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
2300         if (is_zero_ether_addr(netdev->dev_addr) &&
2301             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2302                 eth_hw_addr_random(netdev);
2303                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2304         }
2305 }
2306
2307 static void mlx5e_build_netdev(struct net_device *netdev)
2308 {
2309         struct mlx5e_priv *priv = netdev_priv(netdev);
2310         struct mlx5_core_dev *mdev = priv->mdev;
2311
2312         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2313
2314         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2315                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
2316 #ifdef CONFIG_MLX5_CORE_EN_DCB
2317                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2318 #endif
2319         } else {
2320                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
2321         }
2322
2323         netdev->watchdog_timeo    = 15 * HZ;
2324
2325         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
2326
2327         netdev->vlan_features    |= NETIF_F_SG;
2328         netdev->vlan_features    |= NETIF_F_IP_CSUM;
2329         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
2330         netdev->vlan_features    |= NETIF_F_GRO;
2331         netdev->vlan_features    |= NETIF_F_TSO;
2332         netdev->vlan_features    |= NETIF_F_TSO6;
2333         netdev->vlan_features    |= NETIF_F_RXCSUM;
2334         netdev->vlan_features    |= NETIF_F_RXHASH;
2335
2336         if (!!MLX5_CAP_ETH(mdev, lro_cap))
2337                 netdev->vlan_features    |= NETIF_F_LRO;
2338
2339         netdev->hw_features       = netdev->vlan_features;
2340         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
2341         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
2342         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
2343
2344         if (mlx5e_vxlan_allowed(mdev)) {
2345                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL;
2346                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
2347                 netdev->hw_enc_features |= NETIF_F_RXCSUM;
2348                 netdev->hw_enc_features |= NETIF_F_TSO;
2349                 netdev->hw_enc_features |= NETIF_F_TSO6;
2350                 netdev->hw_enc_features |= NETIF_F_RXHASH;
2351                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
2352         }
2353
2354         netdev->features          = netdev->hw_features;
2355         if (!priv->params.lro_en)
2356                 netdev->features  &= ~NETIF_F_LRO;
2357
2358         netdev->features         |= NETIF_F_HIGHDMA;
2359
2360         netdev->priv_flags       |= IFF_UNICAST_FLT;
2361
2362         mlx5e_set_netdev_dev_addr(netdev);
2363 }
2364
2365 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2366                              struct mlx5_core_mr *mr)
2367 {
2368         struct mlx5_core_dev *mdev = priv->mdev;
2369         struct mlx5_create_mkey_mbox_in *in;
2370         int err;
2371
2372         in = mlx5_vzalloc(sizeof(*in));
2373         if (!in)
2374                 return -ENOMEM;
2375
2376         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2377                         MLX5_PERM_LOCAL_READ  |
2378                         MLX5_ACCESS_MODE_PA;
2379         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2380         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2381
2382         err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
2383                                     NULL);
2384
2385         kvfree(in);
2386
2387         return err;
2388 }
2389
2390 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2391 {
2392         struct net_device *netdev;
2393         struct mlx5e_priv *priv;
2394         int nch = mlx5e_get_max_num_channels(mdev);
2395         int err;
2396
2397         if (mlx5e_check_required_hca_cap(mdev))
2398                 return NULL;
2399
2400         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
2401                                     nch * MLX5E_MAX_NUM_TC,
2402                                     nch);
2403         if (!netdev) {
2404                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2405                 return NULL;
2406         }
2407
2408         mlx5e_build_netdev_priv(mdev, netdev, nch);
2409         mlx5e_build_netdev(netdev);
2410
2411         netif_carrier_off(netdev);
2412
2413         priv = netdev_priv(netdev);
2414
2415         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
2416         if (err) {
2417                 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
2418                 goto err_free_netdev;
2419         }
2420
2421         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2422         if (err) {
2423                 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
2424                 goto err_unmap_free_uar;
2425         }
2426
2427         err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
2428         if (err) {
2429                 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
2430                 goto err_dealloc_pd;
2431         }
2432
2433         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
2434         if (err) {
2435                 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
2436                 goto err_dealloc_transport_domain;
2437         }
2438
2439         err = mlx5e_create_tises(priv);
2440         if (err) {
2441                 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
2442                 goto err_destroy_mkey;
2443         }
2444
2445         err = mlx5e_open_drop_rq(priv);
2446         if (err) {
2447                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
2448                 goto err_destroy_tises;
2449         }
2450
2451         err = mlx5e_create_rqt(priv, MLX5E_INDIRECTION_RQT);
2452         if (err) {
2453                 mlx5_core_warn(mdev, "create rqt(INDIR) failed, %d\n", err);
2454                 goto err_close_drop_rq;
2455         }
2456
2457         err = mlx5e_create_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2458         if (err) {
2459                 mlx5_core_warn(mdev, "create rqt(SINGLE) failed, %d\n", err);
2460                 goto err_destroy_rqt_indir;
2461         }
2462
2463         err = mlx5e_create_tirs(priv);
2464         if (err) {
2465                 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
2466                 goto err_destroy_rqt_single;
2467         }
2468
2469         err = mlx5e_create_flow_tables(priv);
2470         if (err) {
2471                 mlx5_core_warn(mdev, "create flow tables failed, %d\n", err);
2472                 goto err_destroy_tirs;
2473         }
2474
2475         mlx5e_init_eth_addr(priv);
2476
2477         mlx5e_vxlan_init(priv);
2478
2479 #ifdef CONFIG_MLX5_CORE_EN_DCB
2480         mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
2481 #endif
2482
2483         err = register_netdev(netdev);
2484         if (err) {
2485                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
2486                 goto err_destroy_flow_tables;
2487         }
2488
2489         if (mlx5e_vxlan_allowed(mdev))
2490                 vxlan_get_rx_port(netdev);
2491
2492         mlx5e_enable_async_events(priv);
2493         schedule_work(&priv->set_rx_mode_work);
2494
2495         return priv;
2496
2497 err_destroy_flow_tables:
2498         mlx5e_destroy_flow_tables(priv);
2499
2500 err_destroy_tirs:
2501         mlx5e_destroy_tirs(priv);
2502
2503 err_destroy_rqt_single:
2504         mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2505
2506 err_destroy_rqt_indir:
2507         mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2508
2509 err_close_drop_rq:
2510         mlx5e_close_drop_rq(priv);
2511
2512 err_destroy_tises:
2513         mlx5e_destroy_tises(priv);
2514
2515 err_destroy_mkey:
2516         mlx5_core_destroy_mkey(mdev, &priv->mr);
2517
2518 err_dealloc_transport_domain:
2519         mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
2520
2521 err_dealloc_pd:
2522         mlx5_core_dealloc_pd(mdev, priv->pdn);
2523
2524 err_unmap_free_uar:
2525         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
2526
2527 err_free_netdev:
2528         free_netdev(netdev);
2529
2530         return NULL;
2531 }
2532
2533 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
2534 {
2535         struct mlx5e_priv *priv = vpriv;
2536         struct net_device *netdev = priv->netdev;
2537
2538         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
2539
2540         schedule_work(&priv->set_rx_mode_work);
2541         mlx5e_disable_async_events(priv);
2542         flush_scheduled_work();
2543         unregister_netdev(netdev);
2544         mlx5e_vxlan_cleanup(priv);
2545         mlx5e_destroy_flow_tables(priv);
2546         mlx5e_destroy_tirs(priv);
2547         mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2548         mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
2549         mlx5e_close_drop_rq(priv);
2550         mlx5e_destroy_tises(priv);
2551         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
2552         mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
2553         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
2554         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
2555         free_netdev(netdev);
2556 }
2557
2558 static void *mlx5e_get_netdev(void *vpriv)
2559 {
2560         struct mlx5e_priv *priv = vpriv;
2561
2562         return priv->netdev;
2563 }
2564
2565 static struct mlx5_interface mlx5e_interface = {
2566         .add       = mlx5e_create_netdev,
2567         .remove    = mlx5e_destroy_netdev,
2568         .event     = mlx5e_async_event,
2569         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
2570         .get_dev   = mlx5e_get_netdev,
2571 };
2572
2573 void mlx5e_init(void)
2574 {
2575         mlx5_register_interface(&mlx5e_interface);
2576 }
2577
2578 void mlx5e_cleanup(void)
2579 {
2580         mlx5_unregister_interface(&mlx5e_interface);
2581 }