drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <linux/bpf.h>
  38 #include <net/page_pool.h>
  39 #include "eswitch.h"
  40 #include "en.h"
  41 #include "en_tc.h"
  42 #include "en_rep.h"
  43 #include "en_accel/ipsec.h"
  44 #include "en_accel/ipsec_rxtx.h"
  45 #include "en_accel/tls.h"
  46 #include "accel/ipsec.h"
  47 #include "accel/tls.h"
  48 #include "lib/vxlan.h"
  49 #include "lib/clock.h"
  50 #include "en/port.h"
  51 #include "en/xdp.h"
  52 #include "lib/eq.h"
  53 #include "en/monitor_stats.h"
  54
  55 struct mlx5e_rq_param {
  56         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  57         struct mlx5_wq_param    wq;
  58         struct mlx5e_rq_frags_info frags_info;
  59 };
  60
  61 struct mlx5e_sq_param {
  62         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  63         struct mlx5_wq_param       wq;
  64 };
  65
  66 struct mlx5e_cq_param {
  67         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  68         struct mlx5_wq_param       wq;
  69         u16                        eq_ix;
  70         u8                         cq_period_mode;
  71 };
  72
  73 struct mlx5e_channel_param {
  74         struct mlx5e_rq_param      rq;
  75         struct mlx5e_sq_param      sq;
  76         struct mlx5e_sq_param      xdp_sq;
  77         struct mlx5e_sq_param      icosq;
  78         struct mlx5e_cq_param      rx_cq;
  79         struct mlx5e_cq_param      tx_cq;
  80         struct mlx5e_cq_param      icosq_cq;
  81 };
  82
  83 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  84 {
  85         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  86                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  87                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  88         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  89         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  90
  91         if (!striding_rq_umr)
  92                 return false;
  93         if (!inline_umr) {
  94                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
  95                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
  96                 return false;
  97         }
  98         return true;
  99 }
 100
 101 static u32 mlx5e_rx_get_linear_frag_sz(struct mlx5e_params *params)
 102 {
 103         u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 104         u16 linear_rq_headroom = params->xdp_prog ?
 105                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
 106         u32 frag_sz;
 107
 108         linear_rq_headroom += NET_IP_ALIGN;
 109
 110         frag_sz = MLX5_SKB_FRAG_SZ(linear_rq_headroom + hw_mtu);
 111
 112         if (params->xdp_prog && frag_sz < PAGE_SIZE)
 113                 frag_sz = PAGE_SIZE;
 114
 115         return frag_sz;
 116 }
 117
 118 static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params)
 119 {
 120         u32 linear_frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 121
 122         return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
 123 }
 124
 125 static bool mlx5e_rx_is_linear_skb(struct mlx5_core_dev *mdev,
 126                                    struct mlx5e_params *params)
 127 {
 128         u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 129
 130         return !params->lro_en && frag_sz <= PAGE_SIZE;
 131 }
 132
 133 #define MLX5_MAX_MPWQE_LOG_WQE_STRIDE_SZ ((BIT(__mlx5_bit_sz(wq, log_wqe_stride_size)) - 1) + \
 134                                           MLX5_MPWQE_LOG_STRIDE_SZ_BASE)
 135 static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
 136                                          struct mlx5e_params *params)
 137 {
 138         u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 139         s8 signed_log_num_strides_param;
 140         u8 log_num_strides;
 141
 142         if (!mlx5e_rx_is_linear_skb(mdev, params))
 143                 return false;
 144
 145         if (order_base_2(frag_sz) > MLX5_MAX_MPWQE_LOG_WQE_STRIDE_SZ)
 146                 return false;
 147
 148         if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
 149                 return true;
 150
 151         log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz);
 152         signed_log_num_strides_param =
 153                 (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
 154
 155         return signed_log_num_strides_param >= 0;
 156 }
 157
 158 static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params)
 159 {
 160         if (params->log_rq_mtu_frames <
 161             mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
 162                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
 163
 164         return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params);
 165 }
 166
 167 static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
 168                                           struct mlx5e_params *params)
 169 {
 170         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
 171                 return order_base_2(mlx5e_rx_get_linear_frag_sz(params));
 172
 173         return MLX5E_MPWQE_STRIDE_SZ(mdev,
 174                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 175 }
 176
 177 static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
 178                                           struct mlx5e_params *params)
 179 {
 180         return MLX5_MPWRQ_LOG_WQE_SZ -
 181                 mlx5e_mpwqe_get_log_stride_size(mdev, params);
 182 }
 183
 184 static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
 185                                  struct mlx5e_params *params)
 186 {
 187         u16 linear_rq_headroom = params->xdp_prog ?
 188                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
 189         bool is_linear_skb;
 190
 191         linear_rq_headroom += NET_IP_ALIGN;
 192
 193         is_linear_skb = (params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC) ?
 194                 mlx5e_rx_is_linear_skb(mdev, params) :
 195                 mlx5e_rx_mpwqe_is_linear_skb(mdev, params);
 196
 197         return is_linear_skb ? linear_rq_headroom : 0;
 198 }
 199
 200 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
 201                                struct mlx5e_params *params)
 202 {
 203         params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
 204         params->log_rq_mtu_frames = is_kdump_kernel() ?
 205                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
 206                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
 207
 208         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
 209                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
 210                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
 211                        BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
 212                        BIT(params->log_rq_mtu_frames),
 213                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
 214                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 215 }
 216
 217 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 218                                 struct mlx5e_params *params)
 219 {
 220         return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
 221                 !MLX5_IPSEC_DEV(mdev) &&
 222                 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
 223 }
 224
 225 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 226 {
 227         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 228                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 229                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 230                 MLX5_WQ_TYPE_CYCLIC;
 231 }
 232
 233 void mlx5e_update_carrier(struct mlx5e_priv *priv)
 234 {
 235         struct mlx5_core_dev *mdev = priv->mdev;
 236         u8 port_state;
 237
 238         port_state = mlx5_query_vport_state(mdev,
 239                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
 240                                             0);
 241
 242         if (port_state == VPORT_STATE_UP) {
 243                 netdev_info(priv->netdev, "Link up\n");
 244                 netif_carrier_on(priv->netdev);
 245         } else {
 246                 netdev_info(priv->netdev, "Link down\n");
 247                 netif_carrier_off(priv->netdev);
 248         }
 249 }
 250
 251 static void mlx5e_update_carrier_work(struct work_struct *work)
 252 {
 253         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 254                                                update_carrier_work);
 255
 256         mutex_lock(&priv->state_lock);
 257         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 258                 if (priv->profile->update_carrier)
 259                         priv->profile->update_carrier(priv);
 260         mutex_unlock(&priv->state_lock);
 261 }
 262
 263 void mlx5e_update_stats(struct mlx5e_priv *priv)
 264 {
 265         int i;
 266
 267         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 268                 if (mlx5e_stats_grps[i].update_stats)
 269                         mlx5e_stats_grps[i].update_stats(priv);
 270 }
 271
 272 void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 273 {
 274         int i;
 275
 276         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 277                 if (mlx5e_stats_grps[i].update_stats_mask &
 278                     MLX5E_NDO_UPDATE_STATS)
 279                         mlx5e_stats_grps[i].update_stats(priv);
 280 }
 281
 282 static void mlx5e_update_stats_work(struct work_struct *work)
 283 {
 284         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 285                                                update_stats_work);
 286
 287         mutex_lock(&priv->state_lock);
 288         priv->profile->update_stats(priv);
 289         mutex_unlock(&priv->state_lock);
 290 }
 291
 292 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 293 {
 294         if (!priv->profile->update_stats)
 295                 return;
 296
 297         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 298                 return;
 299
 300         queue_work(priv->wq, &priv->update_stats_work);
 301 }
 302
 303 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 304 {
 305         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 306         struct mlx5_eqe   *eqe = data;
 307
 308         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 309                 return NOTIFY_DONE;
 310
 311         switch (eqe->sub_type) {
 312         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 313         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 314                 queue_work(priv->wq, &priv->update_carrier_work);
 315                 break;
 316         default:
 317                 return NOTIFY_DONE;
 318         }
 319
 320         return NOTIFY_OK;
 321 }
 322
 323 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 324 {
 325         priv->events_nb.notifier_call = async_event;
 326         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 327 }
 328
 329 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 330 {
 331         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 332 }
 333
 334 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 335                                        struct mlx5e_icosq *sq,
 336                                        struct mlx5e_umr_wqe *wqe)
 337 {
 338         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 339         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 340         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 341
 342         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 343                                       ds_cnt);
 344         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 345         cseg->imm       = rq->mkey_be;
 346
 347         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 348         ucseg->xlt_octowords =
 349                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 350         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 351 }
 352
 353 static u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
 354 {
 355         switch (rq->wq_type) {
 356         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 357                 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 358         default:
 359                 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
 360         }
 361 }
 362
 363 static u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
 364 {
 365         switch (rq->wq_type) {
 366         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 367                 return rq->mpwqe.wq.cur_sz;
 368         default:
 369                 return rq->wqe.wq.cur_sz;
 370         }
 371 }
 372
 373 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 374                                      struct mlx5e_channel *c)
 375 {
 376         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 377
 378         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 379                                                   sizeof(*rq->mpwqe.info)),
 380                                        GFP_KERNEL, cpu_to_node(c->cpu));
 381         if (!rq->mpwqe.info)
 382                 return -ENOMEM;
 383
 384         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
 385
 386         return 0;
 387 }
 388
 389 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 390                                  u64 npages, u8 page_shift,
 391                                  struct mlx5_core_mkey *umr_mkey)
 392 {
 393         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 394         void *mkc;
 395         u32 *in;
 396         int err;
 397
 398         in = kvzalloc(inlen, GFP_KERNEL);
 399         if (!in)
 400                 return -ENOMEM;
 401
 402         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 403
 404         MLX5_SET(mkc, mkc, free, 1);
 405         MLX5_SET(mkc, mkc, umr_en, 1);
 406         MLX5_SET(mkc, mkc, lw, 1);
 407         MLX5_SET(mkc, mkc, lr, 1);
 408         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 409
 410         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 411         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 412         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 413         MLX5_SET(mkc, mkc, translations_octword_size,
 414                  MLX5_MTT_OCTW(npages));
 415         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 416
 417         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 418
 419         kvfree(in);
 420         return err;
 421 }
 422
 423 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 424 {
 425         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 426
 427         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 428 }
 429
 430 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 431 {
 432         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
 433 }
 434
 435 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 436 {
 437         struct mlx5e_wqe_frag_info next_frag, *prev;
 438         int i;
 439
 440         next_frag.di = &rq->wqe.di[0];
 441         next_frag.offset = 0;
 442         prev = NULL;
 443
 444         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 445                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 446                 struct mlx5e_wqe_frag_info *frag =
 447                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 448                 int f;
 449
 450                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 451                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 452                                 next_frag.di++;
 453                                 next_frag.offset = 0;
 454                                 if (prev)
 455                                         prev->last_in_page = true;
 456                         }
 457                         *frag = next_frag;
 458
 459                         /* prepare next */
 460                         next_frag.offset += frag_info[f].frag_stride;
 461                         prev = frag;
 462                 }
 463         }
 464
 465         if (prev)
 466                 prev->last_in_page = true;
 467 }
 468
 469 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
 470                               struct mlx5e_params *params,
 471                               int wq_sz, int cpu)
 472 {
 473         int len = wq_sz << rq->wqe.info.log_num_frags;
 474
 475         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
 476                                    GFP_KERNEL, cpu_to_node(cpu));
 477         if (!rq->wqe.di)
 478                 return -ENOMEM;
 479
 480         mlx5e_init_frags_partition(rq);
 481
 482         return 0;
 483 }
 484
 485 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
 486 {
 487         kvfree(rq->wqe.di);
 488 }
 489
 490 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 491                           struct mlx5e_params *params,
 492                           struct mlx5e_rq_param *rqp,
 493                           struct mlx5e_rq *rq)
 494 {
 495         struct page_pool_params pp_params = { 0 };
 496         struct mlx5_core_dev *mdev = c->mdev;
 497         void *rqc = rqp->rqc;
 498         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 499         u32 pool_size;
 500         int wq_sz;
 501         int err;
 502         int i;
 503
 504         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 505
 506         rq->wq_type = params->rq_wq_type;
 507         rq->pdev    = c->pdev;
 508         rq->netdev  = c->netdev;
 509         rq->tstamp  = c->tstamp;
 510         rq->clock   = &mdev->clock;
 511         rq->channel = c;
 512         rq->ix      = c->ix;
 513         rq->mdev    = mdev;
 514         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 515         rq->stats   = &c->priv->channel_stats[c->ix].rq;
 516
 517         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
 518         if (IS_ERR(rq->xdp_prog)) {
 519                 err = PTR_ERR(rq->xdp_prog);
 520                 rq->xdp_prog = NULL;
 521                 goto err_rq_wq_destroy;
 522         }
 523
 524         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
 525         if (err < 0)
 526                 goto err_rq_wq_destroy;
 527
 528         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 529         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
 530         pool_size = 1 << params->log_rq_mtu_frames;
 531
 532         switch (rq->wq_type) {
 533         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 534                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 535                                         &rq->wq_ctrl);
 536                 if (err)
 537                         return err;
 538
 539                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 540
 541                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 542
 543                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params);
 544
 545                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 546                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 547
 548                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 549 #ifdef CONFIG_MLX5_EN_IPSEC
 550                 if (MLX5_IPSEC_DEV(mdev)) {
 551                         err = -EINVAL;
 552                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 553                         goto err_rq_wq_destroy;
 554                 }
 555 #endif
 556                 if (!rq->handle_rx_cqe) {
 557                         err = -EINVAL;
 558                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 559                         goto err_rq_wq_destroy;
 560                 }
 561
 562                 rq->mpwqe.skb_from_cqe_mpwrq =
 563                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
 564                         mlx5e_skb_from_cqe_mpwrq_linear :
 565                         mlx5e_skb_from_cqe_mpwrq_nonlinear;
 566                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
 567                 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
 568
 569                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 570                 if (err)
 571                         goto err_rq_wq_destroy;
 572                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 573
 574                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 575                 if (err)
 576                         goto err_free;
 577                 break;
 578         default: /* MLX5_WQ_TYPE_CYCLIC */
 579                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 580                                          &rq->wq_ctrl);
 581                 if (err)
 582                         return err;
 583
 584                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 585
 586                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 587
 588                 rq->wqe.info = rqp->frags_info;
 589                 rq->wqe.frags =
 590                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 591                                         (wq_sz << rq->wqe.info.log_num_frags)),
 592                                       GFP_KERNEL, cpu_to_node(c->cpu));
 593                 if (!rq->wqe.frags) {
 594                         err = -ENOMEM;
 595                         goto err_free;
 596                 }
 597
 598                 err = mlx5e_init_di_list(rq, params, wq_sz, c->cpu);
 599                 if (err)
 600                         goto err_free;
 601                 rq->post_wqes = mlx5e_post_rx_wqes;
 602                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 603
 604 #ifdef CONFIG_MLX5_EN_IPSEC
 605                 if (c->priv->ipsec)
 606                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 607                 else
 608 #endif
 609                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 610                 if (!rq->handle_rx_cqe) {
 611                         err = -EINVAL;
 612                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 613                         goto err_free;
 614                 }
 615
 616                 rq->wqe.skb_from_cqe = mlx5e_rx_is_linear_skb(mdev, params) ?
 617                         mlx5e_skb_from_cqe_linear :
 618                         mlx5e_skb_from_cqe_nonlinear;
 619                 rq->mkey_be = c->mkey_be;
 620         }
 621
 622         /* Create a page_pool and register it with rxq */
 623         pp_params.order     = 0;
 624         pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 625         pp_params.pool_size = pool_size;
 626         pp_params.nid       = cpu_to_node(c->cpu);
 627         pp_params.dev       = c->pdev;
 628         pp_params.dma_dir   = rq->buff.map_dir;
 629
 630         /* page_pool can be used even when there is no rq->xdp_prog,
 631          * given page_pool does not handle DMA mapping there is no
 632          * required state to clear. And page_pool gracefully handle
 633          * elevated refcnt.
 634          */
 635         rq->page_pool = page_pool_create(&pp_params);
 636         if (IS_ERR(rq->page_pool)) {
 637                 err = PTR_ERR(rq->page_pool);
 638                 rq->page_pool = NULL;
 639                 goto err_free;
 640         }
 641         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 642                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
 643         if (err)
 644                 goto err_free;
 645
 646         for (i = 0; i < wq_sz; i++) {
 647                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 648                         struct mlx5e_rx_wqe_ll *wqe =
 649                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 650                         u32 byte_count =
 651                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 652                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
 653
 654                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 655                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 656                         wqe->data[0].lkey = rq->mkey_be;
 657                 } else {
 658                         struct mlx5e_rx_wqe_cyc *wqe =
 659                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 660                         int f;
 661
 662                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 663                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 664                                         MLX5_HW_START_PADDING;
 665
 666                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 667                                 wqe->data[f].lkey = rq->mkey_be;
 668                         }
 669                         /* check if num_frags is not a pow of two */
 670                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 671                                 wqe->data[f].byte_count = 0;
 672                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 673                                 wqe->data[f].addr = 0;
 674                         }
 675                 }
 676         }
 677
 678         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 679
 680         switch (params->rx_cq_moderation.cq_period_mode) {
 681         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 682                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 683                 break;
 684         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 685         default:
 686                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 687         }
 688
 689         rq->page_cache.head = 0;
 690         rq->page_cache.tail = 0;
 691
 692         return 0;
 693
 694 err_free:
 695         switch (rq->wq_type) {
 696         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 697                 kvfree(rq->mpwqe.info);
 698                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 699                 break;
 700         default: /* MLX5_WQ_TYPE_CYCLIC */
 701                 kvfree(rq->wqe.frags);
 702                 mlx5e_free_di_list(rq);
 703         }
 704
 705 err_rq_wq_destroy:
 706         if (rq->xdp_prog)
 707                 bpf_prog_put(rq->xdp_prog);
 708         xdp_rxq_info_unreg(&rq->xdp_rxq);
 709         if (rq->page_pool)
 710                 page_pool_destroy(rq->page_pool);
 711         mlx5_wq_destroy(&rq->wq_ctrl);
 712
 713         return err;
 714 }
 715
 716 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 717 {
 718         int i;
 719
 720         if (rq->xdp_prog)
 721                 bpf_prog_put(rq->xdp_prog);
 722
 723         xdp_rxq_info_unreg(&rq->xdp_rxq);
 724         if (rq->page_pool)
 725                 page_pool_destroy(rq->page_pool);
 726
 727         switch (rq->wq_type) {
 728         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 729                 kvfree(rq->mpwqe.info);
 730                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 731                 break;
 732         default: /* MLX5_WQ_TYPE_CYCLIC */
 733                 kvfree(rq->wqe.frags);
 734                 mlx5e_free_di_list(rq);
 735         }
 736
 737         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 738              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 739                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 740
 741                 mlx5e_page_release(rq, dma_info, false);
 742         }
 743         mlx5_wq_destroy(&rq->wq_ctrl);
 744 }
 745
 746 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 747                            struct mlx5e_rq_param *param)
 748 {
 749         struct mlx5_core_dev *mdev = rq->mdev;
 750
 751         void *in;
 752         void *rqc;
 753         void *wq;
 754         int inlen;
 755         int err;
 756
 757         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 758                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 759         in = kvzalloc(inlen, GFP_KERNEL);
 760         if (!in)
 761                 return -ENOMEM;
 762
 763         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 764         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 765
 766         memcpy(rqc, param->rqc, sizeof(param->rqc));
 767
 768         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 769         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 770         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 771                                                 MLX5_ADAPTER_PAGE_SHIFT);
 772         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 773
 774         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 775                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 776
 777         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 778
 779         kvfree(in);
 780
 781         return err;
 782 }
 783
 784 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 785                                  int next_state)
 786 {
 787         struct mlx5_core_dev *mdev = rq->mdev;
 788
 789         void *in;
 790         void *rqc;
 791         int inlen;
 792         int err;
 793
 794         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 795         in = kvzalloc(inlen, GFP_KERNEL);
 796         if (!in)
 797                 return -ENOMEM;
 798
 799         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 800
 801         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 802         MLX5_SET(rqc, rqc, state, next_state);
 803
 804         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 805
 806         kvfree(in);
 807
 808         return err;
 809 }
 810
 811 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 812 {
 813         struct mlx5e_channel *c = rq->channel;
 814         struct mlx5e_priv *priv = c->priv;
 815         struct mlx5_core_dev *mdev = priv->mdev;
 816
 817         void *in;
 818         void *rqc;
 819         int inlen;
 820         int err;
 821
 822         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 823         in = kvzalloc(inlen, GFP_KERNEL);
 824         if (!in)
 825                 return -ENOMEM;
 826
 827         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 828
 829         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 830         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 831                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 832         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 833         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 834
 835         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 836
 837         kvfree(in);
 838
 839         return err;
 840 }
 841
 842 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 843 {
 844         struct mlx5e_channel *c = rq->channel;
 845         struct mlx5_core_dev *mdev = c->mdev;
 846         void *in;
 847         void *rqc;
 848         int inlen;
 849         int err;
 850
 851         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 852         in = kvzalloc(inlen, GFP_KERNEL);
 853         if (!in)
 854                 return -ENOMEM;
 855
 856         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 857
 858         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 859         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 860                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 861         MLX5_SET(rqc, rqc, vsd, vsd);
 862         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 863
 864         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 865
 866         kvfree(in);
 867
 868         return err;
 869 }
 870
 871 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 872 {
 873         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 874 }
 875
 876 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 877 {
 878         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 879         struct mlx5e_channel *c = rq->channel;
 880
 881         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 882
 883         do {
 884                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 885                         return 0;
 886
 887                 msleep(20);
 888         } while (time_before(jiffies, exp_time));
 889
 890         netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 891                     c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 892
 893         return -ETIMEDOUT;
 894 }
 895
 896 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 897 {
 898         __be16 wqe_ix_be;
 899         u16 wqe_ix;
 900
 901         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 902                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 903
 904                 /* UMR WQE (if in progress) is always at wq->head */
 905                 if (rq->mpwqe.umr_in_progress)
 906                         rq->dealloc_wqe(rq, wq->head);
 907
 908                 while (!mlx5_wq_ll_is_empty(wq)) {
 909                         struct mlx5e_rx_wqe_ll *wqe;
 910
 911                         wqe_ix_be = *wq->tail_next;
 912                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 913                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 914                         rq->dealloc_wqe(rq, wqe_ix);
 915                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 916                                        &wqe->next.next_wqe_index);
 917                 }
 918         } else {
 919                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 920
 921                 while (!mlx5_wq_cyc_is_empty(wq)) {
 922                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 923                         rq->dealloc_wqe(rq, wqe_ix);
 924                         mlx5_wq_cyc_pop(wq);
 925                 }
 926         }
 927
 928 }
 929
 930 static int mlx5e_open_rq(struct mlx5e_channel *c,
 931                          struct mlx5e_params *params,
 932                          struct mlx5e_rq_param *param,
 933                          struct mlx5e_rq *rq)
 934 {
 935         int err;
 936
 937         err = mlx5e_alloc_rq(c, params, param, rq);
 938         if (err)
 939                 return err;
 940
 941         err = mlx5e_create_rq(rq, param);
 942         if (err)
 943                 goto err_free_rq;
 944
 945         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 946         if (err)
 947                 goto err_destroy_rq;
 948
 949         if (params->rx_dim_enabled)
 950                 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 951
 952         if (params->pflags & MLX5E_PFLAG_RX_NO_CSUM_COMPLETE)
 953                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
 954
 955         return 0;
 956
 957 err_destroy_rq:
 958         mlx5e_destroy_rq(rq);
 959 err_free_rq:
 960         mlx5e_free_rq(rq);
 961
 962         return err;
 963 }
 964
 965 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
 966 {
 967         struct mlx5e_icosq *sq = &rq->channel->icosq;
 968         struct mlx5_wq_cyc *wq = &sq->wq;
 969         struct mlx5e_tx_wqe *nopwqe;
 970
 971         u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
 972
 973         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 974         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
 975         nopwqe = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
 976         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
 977 }
 978
 979 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 980 {
 981         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 982         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 983 }
 984
 985 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 986 {
 987         cancel_work_sync(&rq->dim.work);
 988         mlx5e_destroy_rq(rq);
 989         mlx5e_free_rx_descs(rq);
 990         mlx5e_free_rq(rq);
 991 }
 992
 993 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
 994 {
 995         kvfree(sq->db.xdpi);
 996 }
 997
 998 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
 999 {
1000         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1001
1002         sq->db.xdpi = kvzalloc_node(array_size(wq_sz, sizeof(*sq->db.xdpi)),
1003                                     GFP_KERNEL, numa);
1004         if (!sq->db.xdpi) {
1005                 mlx5e_free_xdpsq_db(sq);
1006                 return -ENOMEM;
1007         }
1008
1009         return 0;
1010 }
1011
1012 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
1013                              struct mlx5e_params *params,
1014                              struct mlx5e_sq_param *param,
1015                              struct mlx5e_xdpsq *sq,
1016                              bool is_redirect)
1017 {
1018         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1019         struct mlx5_core_dev *mdev = c->mdev;
1020         struct mlx5_wq_cyc *wq = &sq->wq;
1021         int err;
1022
1023         sq->pdev      = c->pdev;
1024         sq->mkey_be   = c->mkey_be;
1025         sq->channel   = c;
1026         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1027         sq->min_inline_mode = params->tx_min_inline_mode;
1028         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1029         sq->stats     = is_redirect ?
1030                 &c->priv->channel_stats[c->ix].xdpsq :
1031                 &c->priv->channel_stats[c->ix].rq_xdpsq;
1032
1033         param->wq.db_numa_node = cpu_to_node(c->cpu);
1034         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1035         if (err)
1036                 return err;
1037         wq->db = &wq->db[MLX5_SND_DBR];
1038
1039         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1040         if (err)
1041                 goto err_sq_wq_destroy;
1042
1043         return 0;
1044
1045 err_sq_wq_destroy:
1046         mlx5_wq_destroy(&sq->wq_ctrl);
1047
1048         return err;
1049 }
1050
1051 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1052 {
1053         mlx5e_free_xdpsq_db(sq);
1054         mlx5_wq_destroy(&sq->wq_ctrl);
1055 }
1056
1057 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1058 {
1059         kvfree(sq->db.ico_wqe);
1060 }
1061
1062 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1063 {
1064         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1065
1066         sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
1067                                                   sizeof(*sq->db.ico_wqe)),
1068                                        GFP_KERNEL, numa);
1069         if (!sq->db.ico_wqe)
1070                 return -ENOMEM;
1071
1072         return 0;
1073 }
1074
1075 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1076                              struct mlx5e_sq_param *param,
1077                              struct mlx5e_icosq *sq)
1078 {
1079         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1080         struct mlx5_core_dev *mdev = c->mdev;
1081         struct mlx5_wq_cyc *wq = &sq->wq;
1082         int err;
1083
1084         sq->channel   = c;
1085         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1086
1087         param->wq.db_numa_node = cpu_to_node(c->cpu);
1088         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1089         if (err)
1090                 return err;
1091         wq->db = &wq->db[MLX5_SND_DBR];
1092
1093         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1094         if (err)
1095                 goto err_sq_wq_destroy;
1096
1097         return 0;
1098
1099 err_sq_wq_destroy:
1100         mlx5_wq_destroy(&sq->wq_ctrl);
1101
1102         return err;
1103 }
1104
1105 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1106 {
1107         mlx5e_free_icosq_db(sq);
1108         mlx5_wq_destroy(&sq->wq_ctrl);
1109 }
1110
1111 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1112 {
1113         kvfree(sq->db.wqe_info);
1114         kvfree(sq->db.dma_fifo);
1115 }
1116
1117 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1118 {
1119         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1120         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1121
1122         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1123                                                    sizeof(*sq->db.dma_fifo)),
1124                                         GFP_KERNEL, numa);
1125         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1126                                                    sizeof(*sq->db.wqe_info)),
1127                                         GFP_KERNEL, numa);
1128         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1129                 mlx5e_free_txqsq_db(sq);
1130                 return -ENOMEM;
1131         }
1132
1133         sq->dma_fifo_mask = df_sz - 1;
1134
1135         return 0;
1136 }
1137
1138 static void mlx5e_sq_recover(struct work_struct *work);
1139 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1140                              int txq_ix,
1141                              struct mlx5e_params *params,
1142                              struct mlx5e_sq_param *param,
1143                              struct mlx5e_txqsq *sq,
1144                              int tc)
1145 {
1146         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1147         struct mlx5_core_dev *mdev = c->mdev;
1148         struct mlx5_wq_cyc *wq = &sq->wq;
1149         int err;
1150
1151         sq->pdev      = c->pdev;
1152         sq->tstamp    = c->tstamp;
1153         sq->clock     = &mdev->clock;
1154         sq->mkey_be   = c->mkey_be;
1155         sq->channel   = c;
1156         sq->txq_ix    = txq_ix;
1157         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1158         sq->min_inline_mode = params->tx_min_inline_mode;
1159         sq->stats     = &c->priv->channel_stats[c->ix].sq[tc];
1160         INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover);
1161         if (MLX5_IPSEC_DEV(c->priv->mdev))
1162                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1163         if (mlx5_accel_is_tls_device(c->priv->mdev))
1164                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1165
1166         param->wq.db_numa_node = cpu_to_node(c->cpu);
1167         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1168         if (err)
1169                 return err;
1170         wq->db    = &wq->db[MLX5_SND_DBR];
1171
1172         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1173         if (err)
1174                 goto err_sq_wq_destroy;
1175
1176         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1177         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1178
1179         return 0;
1180
1181 err_sq_wq_destroy:
1182         mlx5_wq_destroy(&sq->wq_ctrl);
1183
1184         return err;
1185 }
1186
1187 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1188 {
1189         mlx5e_free_txqsq_db(sq);
1190         mlx5_wq_destroy(&sq->wq_ctrl);
1191 }
1192
1193 struct mlx5e_create_sq_param {
1194         struct mlx5_wq_ctrl        *wq_ctrl;
1195         u32                         cqn;
1196         u32                         tisn;
1197         u8                          tis_lst_sz;
1198         u8                          min_inline_mode;
1199 };
1200
1201 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1202                            struct mlx5e_sq_param *param,
1203                            struct mlx5e_create_sq_param *csp,
1204                            u32 *sqn)
1205 {
1206         void *in;
1207         void *sqc;
1208         void *wq;
1209         int inlen;
1210         int err;
1211
1212         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1213                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1214         in = kvzalloc(inlen, GFP_KERNEL);
1215         if (!in)
1216                 return -ENOMEM;
1217
1218         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1219         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1220
1221         memcpy(sqc, param->sqc, sizeof(param->sqc));
1222         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1223         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1224         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1225
1226         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1227                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1228
1229         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1230         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1231
1232         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1233         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1234         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1235                                           MLX5_ADAPTER_PAGE_SHIFT);
1236         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1237
1238         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1239                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1240
1241         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1242
1243         kvfree(in);
1244
1245         return err;
1246 }
1247
1248 struct mlx5e_modify_sq_param {
1249         int curr_state;
1250         int next_state;
1251         bool rl_update;
1252         int rl_index;
1253 };
1254
1255 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1256                            struct mlx5e_modify_sq_param *p)
1257 {
1258         void *in;
1259         void *sqc;
1260         int inlen;
1261         int err;
1262
1263         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1264         in = kvzalloc(inlen, GFP_KERNEL);
1265         if (!in)
1266                 return -ENOMEM;
1267
1268         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1269
1270         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1271         MLX5_SET(sqc, sqc, state, p->next_state);
1272         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1273                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1274                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1275         }
1276
1277         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1278
1279         kvfree(in);
1280
1281         return err;
1282 }
1283
1284 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1285 {
1286         mlx5_core_destroy_sq(mdev, sqn);
1287 }
1288
1289 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1290                                struct mlx5e_sq_param *param,
1291                                struct mlx5e_create_sq_param *csp,
1292                                u32 *sqn)
1293 {
1294         struct mlx5e_modify_sq_param msp = {0};
1295         int err;
1296
1297         err = mlx5e_create_sq(mdev, param, csp, sqn);
1298         if (err)
1299                 return err;
1300
1301         msp.curr_state = MLX5_SQC_STATE_RST;
1302         msp.next_state = MLX5_SQC_STATE_RDY;
1303         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1304         if (err)
1305                 mlx5e_destroy_sq(mdev, *sqn);
1306
1307         return err;
1308 }
1309
1310 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1311                                 struct mlx5e_txqsq *sq, u32 rate);
1312
1313 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1314                             u32 tisn,
1315                             int txq_ix,
1316                             struct mlx5e_params *params,
1317                             struct mlx5e_sq_param *param,
1318                             struct mlx5e_txqsq *sq,
1319                             int tc)
1320 {
1321         struct mlx5e_create_sq_param csp = {};
1322         u32 tx_rate;
1323         int err;
1324
1325         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1326         if (err)
1327                 return err;
1328
1329         csp.tisn            = tisn;
1330         csp.tis_lst_sz      = 1;
1331         csp.cqn             = sq->cq.mcq.cqn;
1332         csp.wq_ctrl         = &sq->wq_ctrl;
1333         csp.min_inline_mode = sq->min_inline_mode;
1334         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1335         if (err)
1336                 goto err_free_txqsq;
1337
1338         tx_rate = c->priv->tx_rates[sq->txq_ix];
1339         if (tx_rate)
1340                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1341
1342         if (params->tx_dim_enabled)
1343                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1344
1345         return 0;
1346
1347 err_free_txqsq:
1348         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1349         mlx5e_free_txqsq(sq);
1350
1351         return err;
1352 }
1353
1354 static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq)
1355 {
1356         WARN_ONCE(sq->cc != sq->pc,
1357                   "SQ 0x%x: cc (0x%x) != pc (0x%x)\n",
1358                   sq->sqn, sq->cc, sq->pc);
1359         sq->cc = 0;
1360         sq->dma_fifo_cc = 0;
1361         sq->pc = 0;
1362 }
1363
1364 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1365 {
1366         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1367         clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1368         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1369         netdev_tx_reset_queue(sq->txq);
1370         netif_tx_start_queue(sq->txq);
1371 }
1372
1373 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1374 {
1375         __netif_tx_lock_bh(txq);
1376         netif_tx_stop_queue(txq);
1377         __netif_tx_unlock_bh(txq);
1378 }
1379
1380 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1381 {
1382         struct mlx5e_channel *c = sq->channel;
1383         struct mlx5_wq_cyc *wq = &sq->wq;
1384
1385         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1386         /* prevent netif_tx_wake_queue */
1387         napi_synchronize(&c->napi);
1388
1389         netif_tx_disable_queue(sq->txq);
1390
1391         /* last doorbell out, godspeed .. */
1392         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1393                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1394                 struct mlx5e_tx_wqe *nop;
1395
1396                 sq->db.wqe_info[pi].skb = NULL;
1397                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1398                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1399         }
1400 }
1401
1402 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1403 {
1404         struct mlx5e_channel *c = sq->channel;
1405         struct mlx5_core_dev *mdev = c->mdev;
1406         struct mlx5_rate_limit rl = {0};
1407
1408         cancel_work_sync(&sq->dim.work);
1409         mlx5e_destroy_sq(mdev, sq->sqn);
1410         if (sq->rate_limit) {
1411                 rl.rate = sq->rate_limit;
1412                 mlx5_rl_remove_rate(mdev, &rl);
1413         }
1414         mlx5e_free_txqsq_descs(sq);
1415         mlx5e_free_txqsq(sq);
1416 }
1417
1418 static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq)
1419 {
1420         unsigned long exp_time = jiffies + msecs_to_jiffies(2000);
1421
1422         while (time_before(jiffies, exp_time)) {
1423                 if (sq->cc == sq->pc)
1424                         return 0;
1425
1426                 msleep(20);
1427         }
1428
1429         netdev_err(sq->channel->netdev,
1430                    "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n",
1431                    sq->sqn, sq->cc, sq->pc);
1432
1433         return -ETIMEDOUT;
1434 }
1435
1436 static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state)
1437 {
1438         struct mlx5_core_dev *mdev = sq->channel->mdev;
1439         struct net_device *dev = sq->channel->netdev;
1440         struct mlx5e_modify_sq_param msp = {0};
1441         int err;
1442
1443         msp.curr_state = curr_state;
1444         msp.next_state = MLX5_SQC_STATE_RST;
1445
1446         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1447         if (err) {
1448                 netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn);
1449                 return err;
1450         }
1451
1452         memset(&msp, 0, sizeof(msp));
1453         msp.curr_state = MLX5_SQC_STATE_RST;
1454         msp.next_state = MLX5_SQC_STATE_RDY;
1455
1456         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1457         if (err) {
1458                 netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn);
1459                 return err;
1460         }
1461
1462         return 0;
1463 }
1464
1465 static void mlx5e_sq_recover(struct work_struct *work)
1466 {
1467         struct mlx5e_txqsq_recover *recover =
1468                 container_of(work, struct mlx5e_txqsq_recover,
1469                              recover_work);
1470         struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq,
1471                                               recover);
1472         struct mlx5_core_dev *mdev = sq->channel->mdev;
1473         struct net_device *dev = sq->channel->netdev;
1474         u8 state;
1475         int err;
1476
1477         err = mlx5_core_query_sq_state(mdev, sq->sqn, &state);
1478         if (err) {
1479                 netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n",
1480                            sq->sqn, err);
1481                 return;
1482         }
1483
1484         if (state != MLX5_RQC_STATE_ERR) {
1485                 netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn);
1486                 return;
1487         }
1488
1489         netif_tx_disable_queue(sq->txq);
1490
1491         if (mlx5e_wait_for_sq_flush(sq))
1492                 return;
1493
1494         /* If the interval between two consecutive recovers per SQ is too
1495          * short, don't recover to avoid infinite loop of ERR_CQE -> recover.
1496          * If we reached this state, there is probably a bug that needs to be
1497          * fixed. let's keep the queue close and let tx timeout cleanup.
1498          */
1499         if (jiffies_to_msecs(jiffies - recover->last_recover) <
1500             MLX5E_SQ_RECOVER_MIN_INTERVAL) {
1501                 netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n",
1502                            sq->sqn);
1503                 return;
1504         }
1505
1506         /* At this point, no new packets will arrive from the stack as TXQ is
1507          * marked with QUEUE_STATE_DRV_XOFF. In addition, NAPI cleared all
1508          * pending WQEs.  SQ can safely reset the SQ.
1509          */
1510         if (mlx5e_sq_to_ready(sq, state))
1511                 return;
1512
1513         mlx5e_reset_txqsq_cc_pc(sq);
1514         sq->stats->recover++;
1515         recover->last_recover = jiffies;
1516         mlx5e_activate_txqsq(sq);
1517 }
1518
1519 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1520                             struct mlx5e_params *params,
1521                             struct mlx5e_sq_param *param,
1522                             struct mlx5e_icosq *sq)
1523 {
1524         struct mlx5e_create_sq_param csp = {};
1525         int err;
1526
1527         err = mlx5e_alloc_icosq(c, param, sq);
1528         if (err)
1529                 return err;
1530
1531         csp.cqn             = sq->cq.mcq.cqn;
1532         csp.wq_ctrl         = &sq->wq_ctrl;
1533         csp.min_inline_mode = params->tx_min_inline_mode;
1534         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1535         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1536         if (err)
1537                 goto err_free_icosq;
1538
1539         return 0;
1540
1541 err_free_icosq:
1542         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1543         mlx5e_free_icosq(sq);
1544
1545         return err;
1546 }
1547
1548 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1549 {
1550         struct mlx5e_channel *c = sq->channel;
1551
1552         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1553         napi_synchronize(&c->napi);
1554
1555         mlx5e_destroy_sq(c->mdev, sq->sqn);
1556         mlx5e_free_icosq(sq);
1557 }
1558
1559 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1560                             struct mlx5e_params *params,
1561                             struct mlx5e_sq_param *param,
1562                             struct mlx5e_xdpsq *sq,
1563                             bool is_redirect)
1564 {
1565         unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1566         struct mlx5e_create_sq_param csp = {};
1567         unsigned int inline_hdr_sz = 0;
1568         int err;
1569         int i;
1570
1571         err = mlx5e_alloc_xdpsq(c, params, param, sq, is_redirect);
1572         if (err)
1573                 return err;
1574
1575         csp.tis_lst_sz      = 1;
1576         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1577         csp.cqn             = sq->cq.mcq.cqn;
1578         csp.wq_ctrl         = &sq->wq_ctrl;
1579         csp.min_inline_mode = sq->min_inline_mode;
1580         if (is_redirect)
1581                 set_bit(MLX5E_SQ_STATE_REDIRECT, &sq->state);
1582         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1583         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1584         if (err)
1585                 goto err_free_xdpsq;
1586
1587         if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1588                 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1589                 ds_cnt++;
1590         }
1591
1592         /* Pre initialize fixed WQE fields */
1593         for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1594                 struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1595                 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1596                 struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1597                 struct mlx5_wqe_data_seg *dseg;
1598
1599                 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1600                 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1601
1602                 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1603                 dseg->lkey = sq->mkey_be;
1604         }
1605
1606         return 0;
1607
1608 err_free_xdpsq:
1609         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1610         mlx5e_free_xdpsq(sq);
1611
1612         return err;
1613 }
1614
1615 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1616 {
1617         struct mlx5e_channel *c = sq->channel;
1618
1619         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1620         napi_synchronize(&c->napi);
1621
1622         mlx5e_destroy_sq(c->mdev, sq->sqn);
1623         mlx5e_free_xdpsq_descs(sq);
1624         mlx5e_free_xdpsq(sq);
1625 }
1626
1627 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1628                                  struct mlx5e_cq_param *param,
1629                                  struct mlx5e_cq *cq)
1630 {
1631         struct mlx5_core_cq *mcq = &cq->mcq;
1632         int eqn_not_used;
1633         unsigned int irqn;
1634         int err;
1635         u32 i;
1636
1637         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1638         if (err)
1639                 return err;
1640
1641         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1642                                &cq->wq_ctrl);
1643         if (err)
1644                 return err;
1645
1646         mcq->cqe_sz     = 64;
1647         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1648         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1649         *mcq->set_ci_db = 0;
1650         *mcq->arm_db    = 0;
1651         mcq->vector     = param->eq_ix;
1652         mcq->comp       = mlx5e_completion_event;
1653         mcq->event      = mlx5e_cq_error_event;
1654         mcq->irqn       = irqn;
1655
1656         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1657                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1658
1659                 cqe->op_own = 0xf1;
1660         }
1661
1662         cq->mdev = mdev;
1663
1664         return 0;
1665 }
1666
1667 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1668                           struct mlx5e_cq_param *param,
1669                           struct mlx5e_cq *cq)
1670 {
1671         struct mlx5_core_dev *mdev = c->priv->mdev;
1672         int err;
1673
1674         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1675         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1676         param->eq_ix   = c->ix;
1677
1678         err = mlx5e_alloc_cq_common(mdev, param, cq);
1679
1680         cq->napi    = &c->napi;
1681         cq->channel = c;
1682
1683         return err;
1684 }
1685
1686 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1687 {
1688         mlx5_wq_destroy(&cq->wq_ctrl);
1689 }
1690
1691 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1692 {
1693         struct mlx5_core_dev *mdev = cq->mdev;
1694         struct mlx5_core_cq *mcq = &cq->mcq;
1695
1696         void *in;
1697         void *cqc;
1698         int inlen;
1699         unsigned int irqn_not_used;
1700         int eqn;
1701         int err;
1702
1703         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1704         if (err)
1705                 return err;
1706
1707         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1708                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1709         in = kvzalloc(inlen, GFP_KERNEL);
1710         if (!in)
1711                 return -ENOMEM;
1712
1713         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1714
1715         memcpy(cqc, param->cqc, sizeof(param->cqc));
1716
1717         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1718                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1719
1720         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1721         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1722         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1723         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1724                                             MLX5_ADAPTER_PAGE_SHIFT);
1725         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1726
1727         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1728
1729         kvfree(in);
1730
1731         if (err)
1732                 return err;
1733
1734         mlx5e_cq_arm(cq);
1735
1736         return 0;
1737 }
1738
1739 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1740 {
1741         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1742 }
1743
1744 static int mlx5e_open_cq(struct mlx5e_channel *c,
1745                          struct net_dim_cq_moder moder,
1746                          struct mlx5e_cq_param *param,
1747                          struct mlx5e_cq *cq)
1748 {
1749         struct mlx5_core_dev *mdev = c->mdev;
1750         int err;
1751
1752         err = mlx5e_alloc_cq(c, param, cq);
1753         if (err)
1754                 return err;
1755
1756         err = mlx5e_create_cq(cq, param);
1757         if (err)
1758                 goto err_free_cq;
1759
1760         if (MLX5_CAP_GEN(mdev, cq_moderation))
1761                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1762         return 0;
1763
1764 err_free_cq:
1765         mlx5e_free_cq(cq);
1766
1767         return err;
1768 }
1769
1770 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1771 {
1772         mlx5e_destroy_cq(cq);
1773         mlx5e_free_cq(cq);
1774 }
1775
1776 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1777                              struct mlx5e_params *params,
1778                              struct mlx5e_channel_param *cparam)
1779 {
1780         int err;
1781         int tc;
1782
1783         for (tc = 0; tc < c->num_tc; tc++) {
1784                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1785                                     &cparam->tx_cq, &c->sq[tc].cq);
1786                 if (err)
1787                         goto err_close_tx_cqs;
1788         }
1789
1790         return 0;
1791
1792 err_close_tx_cqs:
1793         for (tc--; tc >= 0; tc--)
1794                 mlx5e_close_cq(&c->sq[tc].cq);
1795
1796         return err;
1797 }
1798
1799 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1800 {
1801         int tc;
1802
1803         for (tc = 0; tc < c->num_tc; tc++)
1804                 mlx5e_close_cq(&c->sq[tc].cq);
1805 }
1806
1807 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1808                           struct mlx5e_params *params,
1809                           struct mlx5e_channel_param *cparam)
1810 {
1811         struct mlx5e_priv *priv = c->priv;
1812         int err, tc, max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
1813
1814         for (tc = 0; tc < params->num_tc; tc++) {
1815                 int txq_ix = c->ix + tc * max_nch;
1816
1817                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1818                                        params, &cparam->sq, &c->sq[tc], tc);
1819                 if (err)
1820                         goto err_close_sqs;
1821         }
1822
1823         return 0;
1824
1825 err_close_sqs:
1826         for (tc--; tc >= 0; tc--)
1827                 mlx5e_close_txqsq(&c->sq[tc]);
1828
1829         return err;
1830 }
1831
1832 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1833 {
1834         int tc;
1835
1836         for (tc = 0; tc < c->num_tc; tc++)
1837                 mlx5e_close_txqsq(&c->sq[tc]);
1838 }
1839
1840 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1841                                 struct mlx5e_txqsq *sq, u32 rate)
1842 {
1843         struct mlx5e_priv *priv = netdev_priv(dev);
1844         struct mlx5_core_dev *mdev = priv->mdev;
1845         struct mlx5e_modify_sq_param msp = {0};
1846         struct mlx5_rate_limit rl = {0};
1847         u16 rl_index = 0;
1848         int err;
1849
1850         if (rate == sq->rate_limit)
1851                 /* nothing to do */
1852                 return 0;
1853
1854         if (sq->rate_limit) {
1855                 rl.rate = sq->rate_limit;
1856                 /* remove current rl index to free space to next ones */
1857                 mlx5_rl_remove_rate(mdev, &rl);
1858         }
1859
1860         sq->rate_limit = 0;
1861
1862         if (rate) {
1863                 rl.rate = rate;
1864                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1865                 if (err) {
1866                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1867                                    rate, err);
1868                         return err;
1869                 }
1870         }
1871
1872         msp.curr_state = MLX5_SQC_STATE_RDY;
1873         msp.next_state = MLX5_SQC_STATE_RDY;
1874         msp.rl_index   = rl_index;
1875         msp.rl_update  = true;
1876         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1877         if (err) {
1878                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1879                            rate, err);
1880                 /* remove the rate from the table */
1881                 if (rate)
1882                         mlx5_rl_remove_rate(mdev, &rl);
1883                 return err;
1884         }
1885
1886         sq->rate_limit = rate;
1887         return 0;
1888 }
1889
1890 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1891 {
1892         struct mlx5e_priv *priv = netdev_priv(dev);
1893         struct mlx5_core_dev *mdev = priv->mdev;
1894         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1895         int err = 0;
1896
1897         if (!mlx5_rl_is_supported(mdev)) {
1898                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1899                 return -EINVAL;
1900         }
1901
1902         /* rate is given in Mb/sec, HW config is in Kb/sec */
1903         rate = rate << 10;
1904
1905         /* Check whether rate in valid range, 0 is always valid */
1906         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1907                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1908                 return -ERANGE;
1909         }
1910
1911         mutex_lock(&priv->state_lock);
1912         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1913                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1914         if (!err)
1915                 priv->tx_rates[index] = rate;
1916         mutex_unlock(&priv->state_lock);
1917
1918         return err;
1919 }
1920
1921 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1922                               struct mlx5e_params *params,
1923                               struct mlx5e_channel_param *cparam,
1924                               struct mlx5e_channel **cp)
1925 {
1926         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1927         struct net_dim_cq_moder icocq_moder = {0, 0};
1928         struct net_device *netdev = priv->netdev;
1929         struct mlx5e_channel *c;
1930         unsigned int irq;
1931         int err;
1932         int eqn;
1933
1934         err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1935         if (err)
1936                 return err;
1937
1938         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1939         if (!c)
1940                 return -ENOMEM;
1941
1942         c->priv     = priv;
1943         c->mdev     = priv->mdev;
1944         c->tstamp   = &priv->tstamp;
1945         c->ix       = ix;
1946         c->cpu      = cpu;
1947         c->pdev     = &priv->mdev->pdev->dev;
1948         c->netdev   = priv->netdev;
1949         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1950         c->num_tc   = params->num_tc;
1951         c->xdp      = !!params->xdp_prog;
1952         c->stats    = &priv->channel_stats[ix].ch;
1953
1954         c->irq_desc = irq_to_desc(irq);
1955
1956         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1957
1958         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1959         if (err)
1960                 goto err_napi_del;
1961
1962         err = mlx5e_open_tx_cqs(c, params, cparam);
1963         if (err)
1964                 goto err_close_icosq_cq;
1965
1966         err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
1967         if (err)
1968                 goto err_close_tx_cqs;
1969
1970         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1971         if (err)
1972                 goto err_close_xdp_tx_cqs;
1973
1974         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1975         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1976                                      &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1977         if (err)
1978                 goto err_close_rx_cq;
1979
1980         napi_enable(&c->napi);
1981
1982         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1983         if (err)
1984                 goto err_disable_napi;
1985
1986         err = mlx5e_open_sqs(c, params, cparam);
1987         if (err)
1988                 goto err_close_icosq;
1989
1990         err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq, false) : 0;
1991         if (err)
1992                 goto err_close_sqs;
1993
1994         err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1995         if (err)
1996                 goto err_close_xdp_sq;
1997
1998         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->xdpsq, true);
1999         if (err)
2000                 goto err_close_rq;
2001
2002         *cp = c;
2003
2004         return 0;
2005
2006 err_close_rq:
2007         mlx5e_close_rq(&c->rq);
2008
2009 err_close_xdp_sq:
2010         if (c->xdp)
2011                 mlx5e_close_xdpsq(&c->rq.xdpsq);
2012
2013 err_close_sqs:
2014         mlx5e_close_sqs(c);
2015
2016 err_close_icosq:
2017         mlx5e_close_icosq(&c->icosq);
2018
2019 err_disable_napi:
2020         napi_disable(&c->napi);
2021         if (c->xdp)
2022                 mlx5e_close_cq(&c->rq.xdpsq.cq);
2023
2024 err_close_rx_cq:
2025         mlx5e_close_cq(&c->rq.cq);
2026
2027 err_close_xdp_tx_cqs:
2028         mlx5e_close_cq(&c->xdpsq.cq);
2029
2030 err_close_tx_cqs:
2031         mlx5e_close_tx_cqs(c);
2032
2033 err_close_icosq_cq:
2034         mlx5e_close_cq(&c->icosq.cq);
2035
2036 err_napi_del:
2037         netif_napi_del(&c->napi);
2038         kvfree(c);
2039
2040         return err;
2041 }
2042
2043 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2044 {
2045         int tc;
2046
2047         for (tc = 0; tc < c->num_tc; tc++)
2048                 mlx5e_activate_txqsq(&c->sq[tc]);
2049         mlx5e_activate_rq(&c->rq);
2050         netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
2051 }
2052
2053 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2054 {
2055         int tc;
2056
2057         mlx5e_deactivate_rq(&c->rq);
2058         for (tc = 0; tc < c->num_tc; tc++)
2059                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2060 }
2061
2062 static void mlx5e_close_channel(struct mlx5e_channel *c)
2063 {
2064         mlx5e_close_xdpsq(&c->xdpsq);
2065         mlx5e_close_rq(&c->rq);
2066         if (c->xdp)
2067                 mlx5e_close_xdpsq(&c->rq.xdpsq);
2068         mlx5e_close_sqs(c);
2069         mlx5e_close_icosq(&c->icosq);
2070         napi_disable(&c->napi);
2071         if (c->xdp)
2072                 mlx5e_close_cq(&c->rq.xdpsq.cq);
2073         mlx5e_close_cq(&c->rq.cq);
2074         mlx5e_close_cq(&c->xdpsq.cq);
2075         mlx5e_close_tx_cqs(c);
2076         mlx5e_close_cq(&c->icosq.cq);
2077         netif_napi_del(&c->napi);
2078
2079         kvfree(c);
2080 }
2081
2082 #define DEFAULT_FRAG_SIZE (2048)
2083
2084 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2085                                       struct mlx5e_params *params,
2086                                       struct mlx5e_rq_frags_info *info)
2087 {
2088         u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2089         int frag_size_max = DEFAULT_FRAG_SIZE;
2090         u32 buf_size = 0;
2091         int i;
2092
2093 #ifdef CONFIG_MLX5_EN_IPSEC
2094         if (MLX5_IPSEC_DEV(mdev))
2095                 byte_count += MLX5E_METADATA_ETHER_LEN;
2096 #endif
2097
2098         if (mlx5e_rx_is_linear_skb(mdev, params)) {
2099                 int frag_stride;
2100
2101                 frag_stride = mlx5e_rx_get_linear_frag_sz(params);
2102                 frag_stride = roundup_pow_of_two(frag_stride);
2103
2104                 info->arr[0].frag_size = byte_count;
2105                 info->arr[0].frag_stride = frag_stride;
2106                 info->num_frags = 1;
2107                 info->wqe_bulk = PAGE_SIZE / frag_stride;
2108                 goto out;
2109         }
2110
2111         if (byte_count > PAGE_SIZE +
2112             (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2113                 frag_size_max = PAGE_SIZE;
2114
2115         i = 0;
2116         while (buf_size < byte_count) {
2117                 int frag_size = byte_count - buf_size;
2118
2119                 if (i < MLX5E_MAX_RX_FRAGS - 1)
2120                         frag_size = min(frag_size, frag_size_max);
2121
2122                 info->arr[i].frag_size = frag_size;
2123                 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2124
2125                 buf_size += frag_size;
2126                 i++;
2127         }
2128         info->num_frags = i;
2129         /* number of different wqes sharing a page */
2130         info->wqe_bulk = 1 + (info->num_frags % 2);
2131
2132 out:
2133         info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2134         info->log_num_frags = order_base_2(info->num_frags);
2135 }
2136
2137 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2138 {
2139         int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2140
2141         switch (wq_type) {
2142         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2143                 sz += sizeof(struct mlx5e_rx_wqe_ll);
2144                 break;
2145         default: /* MLX5_WQ_TYPE_CYCLIC */
2146                 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2147         }
2148
2149         return order_base_2(sz);
2150 }
2151
2152 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2153                                  struct mlx5e_params *params,
2154                                  struct mlx5e_rq_param *param)
2155 {
2156         struct mlx5_core_dev *mdev = priv->mdev;
2157         void *rqc = param->rqc;
2158         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2159         int ndsegs = 1;
2160
2161         switch (params->rq_wq_type) {
2162         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2163                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2164                          mlx5e_mpwqe_get_log_num_strides(mdev, params) -
2165                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2166                 MLX5_SET(wq, wq, log_wqe_stride_size,
2167                          mlx5e_mpwqe_get_log_stride_size(mdev, params) -
2168                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2169                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
2170                 break;
2171         default: /* MLX5_WQ_TYPE_CYCLIC */
2172                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2173                 mlx5e_build_rq_frags_info(mdev, params, &param->frags_info);
2174                 ndsegs = param->frags_info.num_frags;
2175         }
2176
2177         MLX5_SET(wq, wq, wq_type,          params->rq_wq_type);
2178         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2179         MLX5_SET(wq, wq, log_wq_stride,
2180                  mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2181         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
2182         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2183         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
2184         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
2185
2186         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2187 }
2188
2189 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2190                                       struct mlx5e_rq_param *param)
2191 {
2192         struct mlx5_core_dev *mdev = priv->mdev;
2193         void *rqc = param->rqc;
2194         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2195
2196         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2197         MLX5_SET(wq, wq, log_wq_stride,
2198                  mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2199         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2200
2201         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2202 }
2203
2204 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2205                                         struct mlx5e_sq_param *param)
2206 {
2207         void *sqc = param->sqc;
2208         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2209
2210         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2211         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
2212
2213         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
2214 }
2215
2216 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2217                                  struct mlx5e_params *params,
2218                                  struct mlx5e_sq_param *param)
2219 {
2220         void *sqc = param->sqc;
2221         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2222
2223         mlx5e_build_sq_param_common(priv, param);
2224         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2225         MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
2226 }
2227
2228 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2229                                         struct mlx5e_cq_param *param)
2230 {
2231         void *cqc = param->cqc;
2232
2233         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2234         if (MLX5_CAP_GEN(priv->mdev, cqe_128_always) && cache_line_size() >= 128)
2235                 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD);
2236 }
2237
2238 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2239                                     struct mlx5e_params *params,
2240                                     struct mlx5e_cq_param *param)
2241 {
2242         struct mlx5_core_dev *mdev = priv->mdev;
2243         void *cqc = param->cqc;
2244         u8 log_cq_size;
2245
2246         switch (params->rq_wq_type) {
2247         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2248                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
2249                         mlx5e_mpwqe_get_log_num_strides(mdev, params);
2250                 break;
2251         default: /* MLX5_WQ_TYPE_CYCLIC */
2252                 log_cq_size = params->log_rq_mtu_frames;
2253         }
2254
2255         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2256         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2257                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2258                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2259         }
2260
2261         mlx5e_build_common_cq_param(priv, param);
2262         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2263 }
2264
2265 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2266                                     struct mlx5e_params *params,
2267                                     struct mlx5e_cq_param *param)
2268 {
2269         void *cqc = param->cqc;
2270
2271         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2272
2273         mlx5e_build_common_cq_param(priv, param);
2274         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2275 }
2276
2277 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2278                                      u8 log_wq_size,
2279                                      struct mlx5e_cq_param *param)
2280 {
2281         void *cqc = param->cqc;
2282
2283         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2284
2285         mlx5e_build_common_cq_param(priv, param);
2286
2287         param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2288 }
2289
2290 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2291                                     u8 log_wq_size,
2292                                     struct mlx5e_sq_param *param)
2293 {
2294         void *sqc = param->sqc;
2295         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2296
2297         mlx5e_build_sq_param_common(priv, param);
2298
2299         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2300         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2301 }
2302
2303 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2304                                     struct mlx5e_params *params,
2305                                     struct mlx5e_sq_param *param)
2306 {
2307         void *sqc = param->sqc;
2308         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2309
2310         mlx5e_build_sq_param_common(priv, param);
2311         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2312 }
2313
2314 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2315                                       struct mlx5e_params *params,
2316                                       struct mlx5e_channel_param *cparam)
2317 {
2318         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2319
2320         mlx5e_build_rq_param(priv, params, &cparam->rq);
2321         mlx5e_build_sq_param(priv, params, &cparam->sq);
2322         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2323         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2324         mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2325         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2326         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2327 }
2328
2329 int mlx5e_open_channels(struct mlx5e_priv *priv,
2330                         struct mlx5e_channels *chs)
2331 {
2332         struct mlx5e_channel_param *cparam;
2333         int err = -ENOMEM;
2334         int i;
2335
2336         chs->num = chs->params.num_channels;
2337
2338         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2339         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2340         if (!chs->c || !cparam)
2341                 goto err_free;
2342
2343         mlx5e_build_channel_param(priv, &chs->params, cparam);
2344         for (i = 0; i < chs->num; i++) {
2345                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2346                 if (err)
2347                         goto err_close_channels;
2348         }
2349
2350         kvfree(cparam);
2351         return 0;
2352
2353 err_close_channels:
2354         for (i--; i >= 0; i--)
2355                 mlx5e_close_channel(chs->c[i]);
2356
2357 err_free:
2358         kfree(chs->c);
2359         kvfree(cparam);
2360         chs->num = 0;
2361         return err;
2362 }
2363
2364 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2365 {
2366         int i;
2367
2368         for (i = 0; i < chs->num; i++)
2369                 mlx5e_activate_channel(chs->c[i]);
2370 }
2371
2372 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2373 {
2374         int err = 0;
2375         int i;
2376
2377         for (i = 0; i < chs->num; i++)
2378                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq,
2379                                                   err ? 0 : 20000);
2380
2381         return err ? -ETIMEDOUT : 0;
2382 }
2383
2384 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2385 {
2386         int i;
2387
2388         for (i = 0; i < chs->num; i++)
2389                 mlx5e_deactivate_channel(chs->c[i]);
2390 }
2391
2392 void mlx5e_close_channels(struct mlx5e_channels *chs)
2393 {
2394         int i;
2395
2396         for (i = 0; i < chs->num; i++)
2397                 mlx5e_close_channel(chs->c[i]);
2398
2399         kfree(chs->c);
2400         chs->num = 0;
2401 }
2402
2403 static int
2404 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2405 {
2406         struct mlx5_core_dev *mdev = priv->mdev;
2407         void *rqtc;
2408         int inlen;
2409         int err;
2410         u32 *in;
2411         int i;
2412
2413         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2414         in = kvzalloc(inlen, GFP_KERNEL);
2415         if (!in)
2416                 return -ENOMEM;
2417
2418         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2419
2420         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2421         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2422
2423         for (i = 0; i < sz; i++)
2424                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2425
2426         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2427         if (!err)
2428                 rqt->enabled = true;
2429
2430         kvfree(in);
2431         return err;
2432 }
2433
2434 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2435 {
2436         rqt->enabled = false;
2437         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2438 }
2439
2440 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2441 {
2442         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2443         int err;
2444
2445         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2446         if (err)
2447                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2448         return err;
2449 }
2450
2451 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2452 {
2453         struct mlx5e_rqt *rqt;
2454         int err;
2455         int ix;
2456
2457         for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2458                 rqt = &priv->direct_tir[ix].rqt;
2459                 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2460                 if (err)
2461                         goto err_destroy_rqts;
2462         }
2463
2464         return 0;
2465
2466 err_destroy_rqts:
2467         mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2468         for (ix--; ix >= 0; ix--)
2469                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2470
2471         return err;
2472 }
2473
2474 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2475 {
2476         int i;
2477
2478         for (i = 0; i < mlx5e_get_netdev_max_channels(priv->netdev); i++)
2479                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2480 }
2481
2482 static int mlx5e_rx_hash_fn(int hfunc)
2483 {
2484         return (hfunc == ETH_RSS_HASH_TOP) ?
2485                MLX5_RX_HASH_FN_TOEPLITZ :
2486                MLX5_RX_HASH_FN_INVERTED_XOR8;
2487 }
2488
2489 int mlx5e_bits_invert(unsigned long a, int size)
2490 {
2491         int inv = 0;
2492         int i;
2493
2494         for (i = 0; i < size; i++)
2495                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2496
2497         return inv;
2498 }
2499
2500 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2501                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2502 {
2503         int i;
2504
2505         for (i = 0; i < sz; i++) {
2506                 u32 rqn;
2507
2508                 if (rrp.is_rss) {
2509                         int ix = i;
2510
2511                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2512                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2513
2514                         ix = priv->rss_params.indirection_rqt[ix];
2515                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2516                 } else {
2517                         rqn = rrp.rqn;
2518                 }
2519                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2520         }
2521 }
2522
2523 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2524                        struct mlx5e_redirect_rqt_param rrp)
2525 {
2526         struct mlx5_core_dev *mdev = priv->mdev;
2527         void *rqtc;
2528         int inlen;
2529         u32 *in;
2530         int err;
2531
2532         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2533         in = kvzalloc(inlen, GFP_KERNEL);
2534         if (!in)
2535                 return -ENOMEM;
2536
2537         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2538
2539         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2540         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2541         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2542         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2543
2544         kvfree(in);
2545         return err;
2546 }
2547
2548 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2549                                 struct mlx5e_redirect_rqt_param rrp)
2550 {
2551         if (!rrp.is_rss)
2552                 return rrp.rqn;
2553
2554         if (ix >= rrp.rss.channels->num)
2555                 return priv->drop_rq.rqn;
2556
2557         return rrp.rss.channels->c[ix]->rq.rqn;
2558 }
2559
2560 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2561                                 struct mlx5e_redirect_rqt_param rrp)
2562 {
2563         u32 rqtn;
2564         int ix;
2565
2566         if (priv->indir_rqt.enabled) {
2567                 /* RSS RQ table */
2568                 rqtn = priv->indir_rqt.rqtn;
2569                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2570         }
2571
2572         for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2573                 struct mlx5e_redirect_rqt_param direct_rrp = {
2574                         .is_rss = false,
2575                         {
2576                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2577                         },
2578                 };
2579
2580                 /* Direct RQ Tables */
2581                 if (!priv->direct_tir[ix].rqt.enabled)
2582                         continue;
2583
2584                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2585                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2586         }
2587 }
2588
2589 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2590                                             struct mlx5e_channels *chs)
2591 {
2592         struct mlx5e_redirect_rqt_param rrp = {
2593                 .is_rss        = true,
2594                 {
2595                         .rss = {
2596                                 .channels  = chs,
2597                                 .hfunc     = priv->rss_params.hfunc,
2598                         }
2599                 },
2600         };
2601
2602         mlx5e_redirect_rqts(priv, rrp);
2603 }
2604
2605 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2606 {
2607         struct mlx5e_redirect_rqt_param drop_rrp = {
2608                 .is_rss = false,
2609                 {
2610                         .rqn = priv->drop_rq.rqn,
2611                 },
2612         };
2613
2614         mlx5e_redirect_rqts(priv, drop_rrp);
2615 }
2616
2617 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2618         [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2619                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2620                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2621         },
2622         [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2623                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2624                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2625         },
2626         [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2627                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2628                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2629         },
2630         [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2631                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2632                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2633         },
2634         [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2635                                      .l4_prot_type = 0,
2636                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2637         },
2638         [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2639                                      .l4_prot_type = 0,
2640                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2641         },
2642         [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2643                                       .l4_prot_type = 0,
2644                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2645         },
2646         [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2647                                       .l4_prot_type = 0,
2648                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2649         },
2650         [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2651                             .l4_prot_type = 0,
2652                             .rx_hash_fields = MLX5_HASH_IP,
2653         },
2654         [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2655                             .l4_prot_type = 0,
2656                             .rx_hash_fields = MLX5_HASH_IP,
2657         },
2658 };
2659
2660 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2661 {
2662         return tirc_default_config[tt];
2663 }
2664
2665 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2666 {
2667         if (!params->lro_en)
2668                 return;
2669
2670 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2671
2672         MLX5_SET(tirc, tirc, lro_enable_mask,
2673                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2674                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2675         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2676                  (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2677         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2678 }
2679
2680 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2681                                     const struct mlx5e_tirc_config *ttconfig,
2682                                     void *tirc, bool inner)
2683 {
2684         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2685                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2686
2687         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2688         if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2689                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2690                                              rx_hash_toeplitz_key);
2691                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2692                                                rx_hash_toeplitz_key);
2693
2694                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2695                 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2696         }
2697         MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2698                  ttconfig->l3_prot_type);
2699         MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2700                  ttconfig->l4_prot_type);
2701         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2702                  ttconfig->rx_hash_fields);
2703 }
2704
2705 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2706                                         enum mlx5e_traffic_types tt,
2707                                         u32 rx_hash_fields)
2708 {
2709         *ttconfig                = tirc_default_config[tt];
2710         ttconfig->rx_hash_fields = rx_hash_fields;
2711 }
2712
2713 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
2714 {
2715         void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2716         struct mlx5e_rss_params *rss = &priv->rss_params;
2717         struct mlx5_core_dev *mdev = priv->mdev;
2718         int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2719         struct mlx5e_tirc_config ttconfig;
2720         int tt;
2721
2722         MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2723
2724         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2725                 memset(tirc, 0, ctxlen);
2726                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2727                                             rss->rx_hash_fields[tt]);
2728                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2729                 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
2730         }
2731
2732         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2733                 return;
2734
2735         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2736                 memset(tirc, 0, ctxlen);
2737                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2738                                             rss->rx_hash_fields[tt]);
2739                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2740                 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in,
2741                                      inlen);
2742         }
2743 }
2744
2745 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2746 {
2747         struct mlx5_core_dev *mdev = priv->mdev;
2748
2749         void *in;
2750         void *tirc;
2751         int inlen;
2752         int err;
2753         int tt;
2754         int ix;
2755
2756         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2757         in = kvzalloc(inlen, GFP_KERNEL);
2758         if (!in)
2759                 return -ENOMEM;
2760
2761         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2762         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2763
2764         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2765
2766         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2767                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2768                                            inlen);
2769                 if (err)
2770                         goto free_in;
2771         }
2772
2773         for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2774                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2775                                            in, inlen);
2776                 if (err)
2777                         goto free_in;
2778         }
2779
2780 free_in:
2781         kvfree(in);
2782
2783         return err;
2784 }
2785
2786 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2787                                             enum mlx5e_traffic_types tt,
2788                                             u32 *tirc)
2789 {
2790         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2791
2792         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2793
2794         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2795         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2796         MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2797
2798         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
2799                                        &tirc_default_config[tt], tirc, true);
2800 }
2801
2802 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2803                          struct mlx5e_params *params, u16 mtu)
2804 {
2805         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2806         int err;
2807
2808         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2809         if (err)
2810                 return err;
2811
2812         /* Update vport context MTU */
2813         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2814         return 0;
2815 }
2816
2817 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2818                             struct mlx5e_params *params, u16 *mtu)
2819 {
2820         u16 hw_mtu = 0;
2821         int err;
2822
2823         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2824         if (err || !hw_mtu) /* fallback to port oper mtu */
2825                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2826
2827         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2828 }
2829
2830 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2831 {
2832         struct mlx5e_params *params = &priv->channels.params;
2833         struct net_device *netdev = priv->netdev;
2834         struct mlx5_core_dev *mdev = priv->mdev;
2835         u16 mtu;
2836         int err;
2837
2838         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2839         if (err)
2840                 return err;
2841
2842         mlx5e_query_mtu(mdev, params, &mtu);
2843         if (mtu != params->sw_mtu)
2844                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2845                             __func__, mtu, params->sw_mtu);
2846
2847         params->sw_mtu = mtu;
2848         return 0;
2849 }
2850
2851 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2852 {
2853         struct mlx5e_priv *priv = netdev_priv(netdev);
2854         int nch = priv->channels.params.num_channels;
2855         int ntc = priv->channels.params.num_tc;
2856         int tc;
2857
2858         netdev_reset_tc(netdev);
2859
2860         if (ntc == 1)
2861                 return;
2862
2863         netdev_set_num_tc(netdev, ntc);
2864
2865         /* Map netdev TCs to offset 0
2866          * We have our own UP to TXQ mapping for QoS
2867          */
2868         for (tc = 0; tc < ntc; tc++)
2869                 netdev_set_tc_queue(netdev, tc, nch, 0);
2870 }
2871
2872 static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
2873 {
2874         int max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
2875         int i, tc;
2876
2877         for (i = 0; i < max_nch; i++)
2878                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2879                         priv->channel_tc2txq[i][tc] = i + tc * max_nch;
2880 }
2881
2882 static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2883 {
2884         struct mlx5e_channel *c;
2885         struct mlx5e_txqsq *sq;
2886         int i, tc;
2887
2888         for (i = 0; i < priv->channels.num; i++) {
2889                 c = priv->channels.c[i];
2890                 for (tc = 0; tc < c->num_tc; tc++) {
2891                         sq = &c->sq[tc];
2892                         priv->txq2sq[sq->txq_ix] = sq;
2893                 }
2894         }
2895 }
2896
2897 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2898 {
2899         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2900         struct net_device *netdev = priv->netdev;
2901
2902         mlx5e_netdev_set_tcs(netdev);
2903         netif_set_real_num_tx_queues(netdev, num_txqs);
2904         netif_set_real_num_rx_queues(netdev, priv->channels.num);
2905
2906         mlx5e_build_tx2sq_maps(priv);
2907         mlx5e_activate_channels(&priv->channels);
2908         netif_tx_start_all_queues(priv->netdev);
2909
2910         if (mlx5e_is_vport_rep(priv))
2911                 mlx5e_add_sqs_fwd_rules(priv);
2912
2913         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2914         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2915 }
2916
2917 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2918 {
2919         mlx5e_redirect_rqts_to_drop(priv);
2920
2921         if (mlx5e_is_vport_rep(priv))
2922                 mlx5e_remove_sqs_fwd_rules(priv);
2923
2924         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2925          * polling for inactive tx queues.
2926          */
2927         netif_tx_stop_all_queues(priv->netdev);
2928         netif_tx_disable(priv->netdev);
2929         mlx5e_deactivate_channels(&priv->channels);
2930 }
2931
2932 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2933                                 struct mlx5e_channels *new_chs,
2934                                 mlx5e_fp_hw_modify hw_modify)
2935 {
2936         struct net_device *netdev = priv->netdev;
2937         int new_num_txqs;
2938         int carrier_ok;
2939         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2940
2941         carrier_ok = netif_carrier_ok(netdev);
2942         netif_carrier_off(netdev);
2943
2944         if (new_num_txqs < netdev->real_num_tx_queues)
2945                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2946
2947         mlx5e_deactivate_priv_channels(priv);
2948         mlx5e_close_channels(&priv->channels);
2949
2950         priv->channels = *new_chs;
2951
2952         /* New channels are ready to roll, modify HW settings if needed */
2953         if (hw_modify)
2954                 hw_modify(priv);
2955
2956         mlx5e_refresh_tirs(priv, false);
2957         mlx5e_activate_priv_channels(priv);
2958
2959         /* return carrier back if needed */
2960         if (carrier_ok)
2961                 netif_carrier_on(netdev);
2962 }
2963
2964 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2965 {
2966         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2967         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2968 }
2969
2970 int mlx5e_open_locked(struct net_device *netdev)
2971 {
2972         struct mlx5e_priv *priv = netdev_priv(netdev);
2973         int err;
2974
2975         set_bit(MLX5E_STATE_OPENED, &priv->state);
2976
2977         err = mlx5e_open_channels(priv, &priv->channels);
2978         if (err)
2979                 goto err_clear_state_opened_flag;
2980
2981         mlx5e_refresh_tirs(priv, false);
2982         mlx5e_activate_priv_channels(priv);
2983         if (priv->profile->update_carrier)
2984                 priv->profile->update_carrier(priv);
2985
2986         mlx5e_queue_update_stats(priv);
2987         return 0;
2988
2989 err_clear_state_opened_flag:
2990         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2991         return err;
2992 }
2993
2994 int mlx5e_open(struct net_device *netdev)
2995 {
2996         struct mlx5e_priv *priv = netdev_priv(netdev);
2997         int err;
2998
2999         mutex_lock(&priv->state_lock);
3000         err = mlx5e_open_locked(netdev);
3001         if (!err)
3002                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
3003         mutex_unlock(&priv->state_lock);
3004
3005         if (mlx5_vxlan_allowed(priv->mdev->vxlan))
3006                 udp_tunnel_get_rx_info(netdev);
3007
3008         return err;
3009 }
3010
3011 int mlx5e_close_locked(struct net_device *netdev)
3012 {
3013         struct mlx5e_priv *priv = netdev_priv(netdev);
3014
3015         /* May already be CLOSED in case a previous configuration operation
3016          * (e.g RX/TX queue size change) that involves close&open failed.
3017          */
3018         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3019                 return 0;
3020
3021         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3022
3023         netif_carrier_off(priv->netdev);
3024         mlx5e_deactivate_priv_channels(priv);
3025         mlx5e_close_channels(&priv->channels);
3026
3027         return 0;
3028 }
3029
3030 int mlx5e_close(struct net_device *netdev)
3031 {
3032         struct mlx5e_priv *priv = netdev_priv(netdev);
3033         int err;
3034
3035         if (!netif_device_present(netdev))
3036                 return -ENODEV;
3037
3038         mutex_lock(&priv->state_lock);
3039         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
3040         err = mlx5e_close_locked(netdev);
3041         mutex_unlock(&priv->state_lock);
3042
3043         return err;
3044 }
3045
3046 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3047                                struct mlx5e_rq *rq,
3048                                struct mlx5e_rq_param *param)
3049 {
3050         void *rqc = param->rqc;
3051         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3052         int err;
3053
3054         param->wq.db_numa_node = param->wq.buf_numa_node;
3055
3056         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3057                                  &rq->wq_ctrl);
3058         if (err)
3059                 return err;
3060
3061         /* Mark as unused given "Drop-RQ" packets never reach XDP */
3062         xdp_rxq_info_unused(&rq->xdp_rxq);
3063
3064         rq->mdev = mdev;
3065
3066         return 0;
3067 }
3068
3069 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3070                                struct mlx5e_cq *cq,
3071                                struct mlx5e_cq_param *param)
3072 {
3073         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
3074         param->wq.db_numa_node  = dev_to_node(&mdev->pdev->dev);
3075
3076         return mlx5e_alloc_cq_common(mdev, param, cq);
3077 }
3078
3079 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3080                        struct mlx5e_rq *drop_rq)
3081 {
3082         struct mlx5_core_dev *mdev = priv->mdev;
3083         struct mlx5e_cq_param cq_param = {};
3084         struct mlx5e_rq_param rq_param = {};
3085         struct mlx5e_cq *cq = &drop_rq->cq;
3086         int err;
3087
3088         mlx5e_build_drop_rq_param(priv, &rq_param);
3089
3090         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3091         if (err)
3092                 return err;
3093
3094         err = mlx5e_create_cq(cq, &cq_param);
3095         if (err)
3096                 goto err_free_cq;
3097
3098         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3099         if (err)
3100                 goto err_destroy_cq;
3101
3102         err = mlx5e_create_rq(drop_rq, &rq_param);
3103         if (err)
3104                 goto err_free_rq;
3105
3106         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3107         if (err)
3108                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3109
3110         return 0;
3111
3112 err_free_rq:
3113         mlx5e_free_rq(drop_rq);
3114
3115 err_destroy_cq:
3116         mlx5e_destroy_cq(cq);
3117
3118 err_free_cq:
3119         mlx5e_free_cq(cq);
3120
3121         return err;
3122 }
3123
3124 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3125 {
3126         mlx5e_destroy_rq(drop_rq);
3127         mlx5e_free_rq(drop_rq);
3128         mlx5e_destroy_cq(&drop_rq->cq);
3129         mlx5e_free_cq(&drop_rq->cq);
3130 }
3131
3132 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
3133                      u32 underlay_qpn, u32 *tisn)
3134 {
3135         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
3136         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3137
3138         MLX5_SET(tisc, tisc, prio, tc << 1);
3139         MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
3140         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3141
3142         if (mlx5_lag_is_lacp_owner(mdev))
3143                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3144
3145         return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
3146 }
3147
3148 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3149 {
3150         mlx5_core_destroy_tis(mdev, tisn);
3151 }
3152
3153 int mlx5e_create_tises(struct mlx5e_priv *priv)
3154 {
3155         int err;
3156         int tc;
3157
3158         for (tc = 0; tc < priv->profile->max_tc; tc++) {
3159                 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
3160                 if (err)
3161                         goto err_close_tises;
3162         }
3163
3164         return 0;
3165
3166 err_close_tises:
3167         for (tc--; tc >= 0; tc--)
3168                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3169
3170         return err;
3171 }
3172
3173 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3174 {
3175         int tc;
3176
3177         for (tc = 0; tc < priv->profile->max_tc; tc++)
3178                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3179 }
3180
3181 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3182                                       enum mlx5e_traffic_types tt,
3183                                       u32 *tirc)
3184 {
3185         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3186
3187         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3188
3189         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3190         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
3191
3192         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3193                                        &tirc_default_config[tt], tirc, false);
3194 }
3195
3196 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3197 {
3198         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3199
3200         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3201
3202         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3203         MLX5_SET(tirc, tirc, indirect_table, rqtn);
3204         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3205 }
3206
3207 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3208 {
3209         struct mlx5e_tir *tir;
3210         void *tirc;
3211         int inlen;
3212         int i = 0;
3213         int err;
3214         u32 *in;
3215         int tt;
3216
3217         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3218         in = kvzalloc(inlen, GFP_KERNEL);
3219         if (!in)
3220                 return -ENOMEM;
3221
3222         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3223                 memset(in, 0, inlen);
3224                 tir = &priv->indir_tir[tt];
3225                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3226                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3227                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3228                 if (err) {
3229                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3230                         goto err_destroy_inner_tirs;
3231                 }
3232         }
3233
3234         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3235                 goto out;
3236
3237         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3238                 memset(in, 0, inlen);
3239                 tir = &priv->inner_indir_tir[i];
3240                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3241                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3242                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3243                 if (err) {
3244                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3245                         goto err_destroy_inner_tirs;
3246                 }
3247         }
3248
3249 out:
3250         kvfree(in);
3251
3252         return 0;
3253
3254 err_destroy_inner_tirs:
3255         for (i--; i >= 0; i--)
3256                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3257
3258         for (tt--; tt >= 0; tt--)
3259                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3260
3261         kvfree(in);
3262
3263         return err;
3264 }
3265
3266 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
3267 {
3268         int nch = mlx5e_get_netdev_max_channels(priv->netdev);
3269         struct mlx5e_tir *tir;
3270         void *tirc;
3271         int inlen;
3272         int err;
3273         u32 *in;
3274         int ix;
3275
3276         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3277         in = kvzalloc(inlen, GFP_KERNEL);
3278         if (!in)
3279                 return -ENOMEM;
3280
3281         for (ix = 0; ix < nch; ix++) {
3282                 memset(in, 0, inlen);
3283                 tir = &priv->direct_tir[ix];
3284                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3285                 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
3286                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3287                 if (err)
3288                         goto err_destroy_ch_tirs;
3289         }
3290
3291         kvfree(in);
3292
3293         return 0;
3294
3295 err_destroy_ch_tirs:
3296         mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
3297         for (ix--; ix >= 0; ix--)
3298                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
3299
3300         kvfree(in);
3301
3302         return err;
3303 }
3304
3305 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3306 {
3307         int i;
3308
3309         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3310                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3311
3312         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3313                 return;
3314
3315         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3316                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3317 }
3318
3319 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3320 {
3321         int nch = mlx5e_get_netdev_max_channels(priv->netdev);
3322         int i;
3323
3324         for (i = 0; i < nch; i++)
3325                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3326 }
3327
3328 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3329 {
3330         int err = 0;
3331         int i;
3332
3333         for (i = 0; i < chs->num; i++) {
3334                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3335                 if (err)
3336                         return err;
3337         }
3338
3339         return 0;
3340 }
3341
3342 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3343 {
3344         int err = 0;
3345         int i;
3346
3347         for (i = 0; i < chs->num; i++) {
3348                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3349                 if (err)
3350                         return err;
3351         }
3352
3353         return 0;
3354 }
3355
3356 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3357                                  struct tc_mqprio_qopt *mqprio)
3358 {
3359         struct mlx5e_priv *priv = netdev_priv(netdev);
3360         struct mlx5e_channels new_channels = {};
3361         u8 tc = mqprio->num_tc;
3362         int err = 0;
3363
3364         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3365
3366         if (tc && tc != MLX5E_MAX_NUM_TC)
3367                 return -EINVAL;
3368
3369         mutex_lock(&priv->state_lock);
3370
3371         new_channels.params = priv->channels.params;
3372         new_channels.params.num_tc = tc ? tc : 1;
3373
3374         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3375                 priv->channels.params = new_channels.params;
3376                 goto out;
3377         }
3378
3379         err = mlx5e_open_channels(priv, &new_channels);
3380         if (err)
3381                 goto out;
3382
3383         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3384                                     new_channels.params.num_tc);
3385         mlx5e_switch_priv_channels(priv, &new_channels, NULL);
3386 out:
3387         mutex_unlock(&priv->state_lock);
3388         return err;
3389 }
3390
3391 #ifdef CONFIG_MLX5_ESWITCH
3392 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3393                                      struct tc_cls_flower_offload *cls_flower,
3394                                      int flags)
3395 {
3396         switch (cls_flower->command) {
3397         case TC_CLSFLOWER_REPLACE:
3398                 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
3399                                               flags);
3400         case TC_CLSFLOWER_DESTROY:
3401                 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
3402                                            flags);
3403         case TC_CLSFLOWER_STATS:
3404                 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
3405                                           flags);
3406         default:
3407                 return -EOPNOTSUPP;
3408         }
3409 }
3410
3411 static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3412                                    void *cb_priv)
3413 {
3414         struct mlx5e_priv *priv = cb_priv;
3415
3416         switch (type) {
3417         case TC_SETUP_CLSFLOWER:
3418                 return mlx5e_setup_tc_cls_flower(priv, type_data, MLX5E_TC_INGRESS |
3419                                                  MLX5E_TC_NIC_OFFLOAD);
3420         default:
3421                 return -EOPNOTSUPP;
3422         }
3423 }
3424
3425 static int mlx5e_setup_tc_block(struct net_device *dev,
3426                                 struct tc_block_offload *f)
3427 {
3428         struct mlx5e_priv *priv = netdev_priv(dev);
3429
3430         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3431                 return -EOPNOTSUPP;
3432
3433         switch (f->command) {
3434         case TC_BLOCK_BIND:
3435                 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3436                                              priv, priv, f->extack);
3437         case TC_BLOCK_UNBIND:
3438                 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3439                                         priv);
3440                 return 0;
3441         default:
3442                 return -EOPNOTSUPP;
3443         }
3444 }
3445 #endif
3446
3447 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3448                           void *type_data)
3449 {
3450         switch (type) {
3451 #ifdef CONFIG_MLX5_ESWITCH
3452         case TC_SETUP_BLOCK:
3453                 return mlx5e_setup_tc_block(dev, type_data);
3454 #endif
3455         case TC_SETUP_QDISC_MQPRIO:
3456                 return mlx5e_setup_tc_mqprio(dev, type_data);
3457         default:
3458                 return -EOPNOTSUPP;
3459         }
3460 }
3461
3462 void
3463 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3464 {
3465         struct mlx5e_priv *priv = netdev_priv(dev);
3466         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
3467         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3468         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3469
3470         if (!mlx5e_monitor_counter_supported(priv)) {
3471                 /* update HW stats in background for next time */
3472                 mlx5e_queue_update_stats(priv);
3473         }
3474
3475         if (mlx5e_is_uplink_rep(priv)) {
3476                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3477                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3478                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3479                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3480         } else {
3481                 mlx5e_grp_sw_update_stats(priv);
3482                 stats->rx_packets = sstats->rx_packets;
3483                 stats->rx_bytes   = sstats->rx_bytes;
3484                 stats->tx_packets = sstats->tx_packets;
3485                 stats->tx_bytes   = sstats->tx_bytes;
3486                 stats->tx_dropped = sstats->tx_queue_dropped;
3487         }
3488
3489         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3490
3491         stats->rx_length_errors =
3492                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3493                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3494                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3495         stats->rx_crc_errors =
3496                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3497         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3498         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3499         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3500                            stats->rx_frame_errors;
3501         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3502
3503         /* vport multicast also counts packets that are dropped due to steering
3504          * or rx out of buffer
3505          */
3506         stats->multicast =
3507                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3508 }
3509
3510 static void mlx5e_set_rx_mode(struct net_device *dev)
3511 {
3512         struct mlx5e_priv *priv = netdev_priv(dev);
3513
3514         queue_work(priv->wq, &priv->set_rx_mode_work);
3515 }
3516
3517 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3518 {
3519         struct mlx5e_priv *priv = netdev_priv(netdev);
3520         struct sockaddr *saddr = addr;
3521
3522         if (!is_valid_ether_addr(saddr->sa_data))
3523                 return -EADDRNOTAVAIL;
3524
3525         netif_addr_lock_bh(netdev);
3526         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3527         netif_addr_unlock_bh(netdev);
3528
3529         queue_work(priv->wq, &priv->set_rx_mode_work);
3530
3531         return 0;
3532 }
3533
3534 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3535         do {                                            \
3536                 if (enable)                             \
3537                         *features |= feature;           \
3538                 else                                    \
3539                         *features &= ~feature;          \
3540         } while (0)
3541
3542 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3543
3544 static int set_feature_lro(struct net_device *netdev, bool enable)
3545 {
3546         struct mlx5e_priv *priv = netdev_priv(netdev);
3547         struct mlx5_core_dev *mdev = priv->mdev;
3548         struct mlx5e_channels new_channels = {};
3549         struct mlx5e_params *old_params;
3550         int err = 0;
3551         bool reset;
3552
3553         mutex_lock(&priv->state_lock);
3554
3555         old_params = &priv->channels.params;
3556         if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3557                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3558                 err = -EINVAL;
3559                 goto out;
3560         }
3561
3562         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3563
3564         new_channels.params = *old_params;
3565         new_channels.params.lro_en = enable;
3566
3567         if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3568                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params) ==
3569                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params))
3570                         reset = false;
3571         }
3572
3573         if (!reset) {
3574                 *old_params = new_channels.params;
3575                 err = mlx5e_modify_tirs_lro(priv);
3576                 goto out;
3577         }
3578
3579         err = mlx5e_open_channels(priv, &new_channels);
3580         if (err)
3581                 goto out;
3582
3583         mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3584 out:
3585         mutex_unlock(&priv->state_lock);
3586         return err;
3587 }
3588
3589 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3590 {
3591         struct mlx5e_priv *priv = netdev_priv(netdev);
3592
3593         if (enable)
3594                 mlx5e_enable_cvlan_filter(priv);
3595         else
3596                 mlx5e_disable_cvlan_filter(priv);
3597
3598         return 0;
3599 }
3600
3601 #ifdef CONFIG_MLX5_ESWITCH
3602 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3603 {
3604         struct mlx5e_priv *priv = netdev_priv(netdev);
3605
3606         if (!enable && mlx5e_tc_num_filters(priv, MLX5E_TC_NIC_OFFLOAD)) {
3607                 netdev_err(netdev,
3608                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3609                 return -EINVAL;
3610         }
3611
3612         return 0;
3613 }
3614 #endif
3615
3616 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3617 {
3618         struct mlx5e_priv *priv = netdev_priv(netdev);
3619         struct mlx5_core_dev *mdev = priv->mdev;
3620
3621         return mlx5_set_port_fcs(mdev, !enable);
3622 }
3623
3624 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3625 {
3626         struct mlx5e_priv *priv = netdev_priv(netdev);
3627         int err;
3628
3629         mutex_lock(&priv->state_lock);
3630
3631         priv->channels.params.scatter_fcs_en = enable;
3632         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3633         if (err)
3634                 priv->channels.params.scatter_fcs_en = !enable;
3635
3636         mutex_unlock(&priv->state_lock);
3637
3638         return err;
3639 }
3640
3641 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3642 {
3643         struct mlx5e_priv *priv = netdev_priv(netdev);
3644         int err = 0;
3645
3646         mutex_lock(&priv->state_lock);
3647
3648         priv->channels.params.vlan_strip_disable = !enable;
3649         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3650                 goto unlock;
3651
3652         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3653         if (err)
3654                 priv->channels.params.vlan_strip_disable = enable;
3655
3656 unlock:
3657         mutex_unlock(&priv->state_lock);
3658
3659         return err;
3660 }
3661
3662 #ifdef CONFIG_MLX5_EN_ARFS
3663 static int set_feature_arfs(struct net_device *netdev, bool enable)
3664 {
3665         struct mlx5e_priv *priv = netdev_priv(netdev);
3666         int err;
3667
3668         if (enable)
3669                 err = mlx5e_arfs_enable(priv);
3670         else
3671                 err = mlx5e_arfs_disable(priv);
3672
3673         return err;
3674 }
3675 #endif
3676
3677 static int mlx5e_handle_feature(struct net_device *netdev,
3678                                 netdev_features_t *features,
3679                                 netdev_features_t wanted_features,
3680                                 netdev_features_t feature,
3681                                 mlx5e_feature_handler feature_handler)
3682 {
3683         netdev_features_t changes = wanted_features ^ netdev->features;
3684         bool enable = !!(wanted_features & feature);
3685         int err;
3686
3687         if (!(changes & feature))
3688                 return 0;
3689
3690         err = feature_handler(netdev, enable);
3691         if (err) {
3692                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3693                            enable ? "Enable" : "Disable", &feature, err);
3694                 return err;
3695         }
3696
3697         MLX5E_SET_FEATURE(features, feature, enable);
3698         return 0;
3699 }
3700
3701 static int mlx5e_set_features(struct net_device *netdev,
3702                               netdev_features_t features)
3703 {
3704         netdev_features_t oper_features = netdev->features;
3705         int err = 0;
3706
3707 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3708         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3709
3710         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3711         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3712                                     set_feature_cvlan_filter);
3713 #ifdef CONFIG_MLX5_ESWITCH
3714         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3715 #endif
3716         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3717         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3718         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3719 #ifdef CONFIG_MLX5_EN_ARFS
3720         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3721 #endif
3722
3723         if (err) {
3724                 netdev->features = oper_features;
3725                 return -EINVAL;
3726         }
3727
3728         return 0;
3729 }
3730
3731 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3732                                             netdev_features_t features)
3733 {
3734         struct mlx5e_priv *priv = netdev_priv(netdev);
3735         struct mlx5e_params *params;
3736
3737         mutex_lock(&priv->state_lock);
3738         params = &priv->channels.params;
3739         if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3740                 /* HW strips the outer C-tag header, this is a problem
3741                  * for S-tag traffic.
3742                  */
3743                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3744                 if (!params->vlan_strip_disable)
3745                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3746         }
3747         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3748                 features &= ~NETIF_F_LRO;
3749                 if (params->lro_en)
3750                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3751         }
3752
3753         mutex_unlock(&priv->state_lock);
3754
3755         return features;
3756 }
3757
3758 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3759                      change_hw_mtu_cb set_mtu_cb)
3760 {
3761         struct mlx5e_priv *priv = netdev_priv(netdev);
3762         struct mlx5e_channels new_channels = {};
3763         struct mlx5e_params *params;
3764         int err = 0;
3765         bool reset;
3766
3767         mutex_lock(&priv->state_lock);
3768
3769         params = &priv->channels.params;
3770
3771         reset = !params->lro_en;
3772         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3773
3774         new_channels.params = *params;
3775         new_channels.params.sw_mtu = new_mtu;
3776
3777         if (params->xdp_prog &&
3778             !mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) {
3779                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3780                            new_mtu, MLX5E_XDP_MAX_MTU);
3781                 err = -EINVAL;
3782                 goto out;
3783         }
3784
3785         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3786                 bool is_linear = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, &new_channels.params);
3787                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params);
3788                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params);
3789
3790                 reset = reset && (is_linear || (ppw_old != ppw_new));
3791         }
3792
3793         if (!reset) {
3794                 params->sw_mtu = new_mtu;
3795                 if (set_mtu_cb)
3796                         set_mtu_cb(priv);
3797                 netdev->mtu = params->sw_mtu;
3798                 goto out;
3799         }
3800
3801         err = mlx5e_open_channels(priv, &new_channels);
3802         if (err)
3803                 goto out;
3804
3805         mlx5e_switch_priv_channels(priv, &new_channels, set_mtu_cb);
3806         netdev->mtu = new_channels.params.sw_mtu;
3807
3808 out:
3809         mutex_unlock(&priv->state_lock);
3810         return err;
3811 }
3812
3813 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3814 {
3815         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3816 }
3817
3818 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3819 {
3820         struct hwtstamp_config config;
3821         int err;
3822
3823         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3824             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
3825                 return -EOPNOTSUPP;
3826
3827         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3828                 return -EFAULT;
3829
3830         /* TX HW timestamp */
3831         switch (config.tx_type) {
3832         case HWTSTAMP_TX_OFF:
3833         case HWTSTAMP_TX_ON:
3834                 break;
3835         default:
3836                 return -ERANGE;
3837         }
3838
3839         mutex_lock(&priv->state_lock);
3840         /* RX HW timestamp */
3841         switch (config.rx_filter) {
3842         case HWTSTAMP_FILTER_NONE:
3843                 /* Reset CQE compression to Admin default */
3844                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3845                 break;
3846         case HWTSTAMP_FILTER_ALL:
3847         case HWTSTAMP_FILTER_SOME:
3848         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3849         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3850         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3851         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3852         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3853         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3854         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3855         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3856         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3857         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3858         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3859         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3860         case HWTSTAMP_FILTER_NTP_ALL:
3861                 /* Disable CQE compression */
3862                 netdev_warn(priv->netdev, "Disabling cqe compression");
3863                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3864                 if (err) {
3865                         netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3866                         mutex_unlock(&priv->state_lock);
3867                         return err;
3868                 }
3869                 config.rx_filter = HWTSTAMP_FILTER_ALL;
3870                 break;
3871         default:
3872                 mutex_unlock(&priv->state_lock);
3873                 return -ERANGE;
3874         }
3875
3876         memcpy(&priv->tstamp, &config, sizeof(config));
3877         mutex_unlock(&priv->state_lock);
3878
3879         return copy_to_user(ifr->ifr_data, &config,
3880                             sizeof(config)) ? -EFAULT : 0;
3881 }
3882
3883 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3884 {
3885         struct hwtstamp_config *cfg = &priv->tstamp;
3886
3887         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3888                 return -EOPNOTSUPP;
3889
3890         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3891 }
3892
3893 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3894 {
3895         struct mlx5e_priv *priv = netdev_priv(dev);
3896
3897         switch (cmd) {
3898         case SIOCSHWTSTAMP:
3899                 return mlx5e_hwstamp_set(priv, ifr);
3900         case SIOCGHWTSTAMP:
3901                 return mlx5e_hwstamp_get(priv, ifr);
3902         default:
3903                 return -EOPNOTSUPP;
3904         }
3905 }
3906
3907 #ifdef CONFIG_MLX5_ESWITCH
3908 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3909 {
3910         struct mlx5e_priv *priv = netdev_priv(dev);
3911         struct mlx5_core_dev *mdev = priv->mdev;
3912
3913         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3914 }
3915
3916 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3917                              __be16 vlan_proto)
3918 {
3919         struct mlx5e_priv *priv = netdev_priv(dev);
3920         struct mlx5_core_dev *mdev = priv->mdev;
3921
3922         if (vlan_proto != htons(ETH_P_8021Q))
3923                 return -EPROTONOSUPPORT;
3924
3925         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3926                                            vlan, qos);
3927 }
3928
3929 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3930 {
3931         struct mlx5e_priv *priv = netdev_priv(dev);
3932         struct mlx5_core_dev *mdev = priv->mdev;
3933
3934         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3935 }
3936
3937 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3938 {
3939         struct mlx5e_priv *priv = netdev_priv(dev);
3940         struct mlx5_core_dev *mdev = priv->mdev;
3941
3942         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3943 }
3944
3945 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3946                       int max_tx_rate)
3947 {
3948         struct mlx5e_priv *priv = netdev_priv(dev);
3949         struct mlx5_core_dev *mdev = priv->mdev;
3950
3951         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3952                                            max_tx_rate, min_tx_rate);
3953 }
3954
3955 static int mlx5_vport_link2ifla(u8 esw_link)
3956 {
3957         switch (esw_link) {
3958         case MLX5_VPORT_ADMIN_STATE_DOWN:
3959                 return IFLA_VF_LINK_STATE_DISABLE;
3960         case MLX5_VPORT_ADMIN_STATE_UP:
3961                 return IFLA_VF_LINK_STATE_ENABLE;
3962         }
3963         return IFLA_VF_LINK_STATE_AUTO;
3964 }
3965
3966 static int mlx5_ifla_link2vport(u8 ifla_link)
3967 {
3968         switch (ifla_link) {
3969         case IFLA_VF_LINK_STATE_DISABLE:
3970                 return MLX5_VPORT_ADMIN_STATE_DOWN;
3971         case IFLA_VF_LINK_STATE_ENABLE:
3972                 return MLX5_VPORT_ADMIN_STATE_UP;
3973         }
3974         return MLX5_VPORT_ADMIN_STATE_AUTO;
3975 }
3976
3977 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3978                                    int link_state)
3979 {
3980         struct mlx5e_priv *priv = netdev_priv(dev);
3981         struct mlx5_core_dev *mdev = priv->mdev;
3982
3983         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3984                                             mlx5_ifla_link2vport(link_state));
3985 }
3986
3987 int mlx5e_get_vf_config(struct net_device *dev,
3988                         int vf, struct ifla_vf_info *ivi)
3989 {
3990         struct mlx5e_priv *priv = netdev_priv(dev);
3991         struct mlx5_core_dev *mdev = priv->mdev;
3992         int err;
3993
3994         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3995         if (err)
3996                 return err;
3997         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3998         return 0;
3999 }
4000
4001 int mlx5e_get_vf_stats(struct net_device *dev,
4002                        int vf, struct ifla_vf_stats *vf_stats)
4003 {
4004         struct mlx5e_priv *priv = netdev_priv(dev);
4005         struct mlx5_core_dev *mdev = priv->mdev;
4006
4007         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4008                                             vf_stats);
4009 }
4010 #endif
4011
4012 struct mlx5e_vxlan_work {
4013         struct work_struct      work;
4014         struct mlx5e_priv       *priv;
4015         u16                     port;
4016 };
4017
4018 static void mlx5e_vxlan_add_work(struct work_struct *work)
4019 {
4020         struct mlx5e_vxlan_work *vxlan_work =
4021                 container_of(work, struct mlx5e_vxlan_work, work);
4022         struct mlx5e_priv *priv = vxlan_work->priv;
4023         u16 port = vxlan_work->port;
4024
4025         mutex_lock(&priv->state_lock);
4026         mlx5_vxlan_add_port(priv->mdev->vxlan, port);
4027         mutex_unlock(&priv->state_lock);
4028
4029         kfree(vxlan_work);
4030 }
4031
4032 static void mlx5e_vxlan_del_work(struct work_struct *work)
4033 {
4034         struct mlx5e_vxlan_work *vxlan_work =
4035                 container_of(work, struct mlx5e_vxlan_work, work);
4036         struct mlx5e_priv *priv         = vxlan_work->priv;
4037         u16 port = vxlan_work->port;
4038
4039         mutex_lock(&priv->state_lock);
4040         mlx5_vxlan_del_port(priv->mdev->vxlan, port);
4041         mutex_unlock(&priv->state_lock);
4042         kfree(vxlan_work);
4043 }
4044
4045 static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
4046 {
4047         struct mlx5e_vxlan_work *vxlan_work;
4048
4049         vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
4050         if (!vxlan_work)
4051                 return;
4052
4053         if (add)
4054                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
4055         else
4056                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4057
4058         vxlan_work->priv = priv;
4059         vxlan_work->port = port;
4060         queue_work(priv->wq, &vxlan_work->work);
4061 }
4062
4063 void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4064 {
4065         struct mlx5e_priv *priv = netdev_priv(netdev);
4066
4067         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4068                 return;
4069
4070         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4071                 return;
4072
4073         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
4074 }
4075
4076 void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4077 {
4078         struct mlx5e_priv *priv = netdev_priv(netdev);
4079
4080         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4081                 return;
4082
4083         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4084                 return;
4085
4086         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
4087 }
4088
4089 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4090                                                      struct sk_buff *skb,
4091                                                      netdev_features_t features)
4092 {
4093         unsigned int offset = 0;
4094         struct udphdr *udph;
4095         u8 proto;
4096         u16 port;
4097
4098         switch (vlan_get_protocol(skb)) {
4099         case htons(ETH_P_IP):
4100                 proto = ip_hdr(skb)->protocol;
4101                 break;
4102         case htons(ETH_P_IPV6):
4103                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4104                 break;
4105         default:
4106                 goto out;
4107         }
4108
4109         switch (proto) {
4110         case IPPROTO_GRE:
4111                 return features;
4112         case IPPROTO_UDP:
4113                 udph = udp_hdr(skb);
4114                 port = be16_to_cpu(udph->dest);
4115
4116                 /* Verify if UDP port is being offloaded by HW */
4117                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4118                         return features;
4119         }
4120
4121 out:
4122         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4123         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4124 }
4125
4126 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4127                                        struct net_device *netdev,
4128                                        netdev_features_t features)
4129 {
4130         struct mlx5e_priv *priv = netdev_priv(netdev);
4131
4132         features = vlan_features_check(skb, features);
4133         features = vxlan_features_check(skb, features);
4134
4135 #ifdef CONFIG_MLX5_EN_IPSEC
4136         if (mlx5e_ipsec_feature_check(skb, netdev, features))
4137                 return features;
4138 #endif
4139
4140         /* Validate if the tunneled packet is being offloaded by HW */
4141         if (skb->encapsulation &&
4142             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4143                 return mlx5e_tunnel_features_check(priv, skb, features);
4144
4145         return features;
4146 }
4147
4148 static bool mlx5e_tx_timeout_eq_recover(struct net_device *dev,
4149                                         struct mlx5e_txqsq *sq)
4150 {
4151         struct mlx5_eq_comp *eq = sq->cq.mcq.eq;
4152         u32 eqe_count;
4153
4154         netdev_err(dev, "EQ 0x%x: Cons = 0x%x, irqn = 0x%x\n",
4155                    eq->core.eqn, eq->core.cons_index, eq->core.irqn);
4156
4157         eqe_count = mlx5_eq_poll_irq_disabled(eq);
4158         if (!eqe_count)
4159                 return false;
4160
4161         netdev_err(dev, "Recover %d eqes on EQ 0x%x\n", eqe_count, eq->core.eqn);
4162         sq->channel->stats->eq_rearm++;
4163         return true;
4164 }
4165
4166 static void mlx5e_tx_timeout_work(struct work_struct *work)
4167 {
4168         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4169                                                tx_timeout_work);
4170         struct net_device *dev = priv->netdev;
4171         bool reopen_channels = false;
4172         int i, err;
4173
4174         rtnl_lock();
4175         mutex_lock(&priv->state_lock);
4176
4177         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4178                 goto unlock;
4179
4180         for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4181                 struct netdev_queue *dev_queue = netdev_get_tx_queue(dev, i);
4182                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4183
4184                 if (!netif_xmit_stopped(dev_queue))
4185                         continue;
4186
4187                 netdev_err(dev,
4188                            "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x, usecs since last trans: %u\n",
4189                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc,
4190                            jiffies_to_usecs(jiffies - dev_queue->trans_start));
4191
4192                 /* If we recover a lost interrupt, most likely TX timeout will
4193                  * be resolved, skip reopening channels
4194                  */
4195                 if (!mlx5e_tx_timeout_eq_recover(dev, sq)) {
4196                         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
4197                         reopen_channels = true;
4198                 }
4199         }
4200
4201         if (!reopen_channels)
4202                 goto unlock;
4203
4204         mlx5e_close_locked(dev);
4205         err = mlx5e_open_locked(dev);
4206         if (err)
4207                 netdev_err(priv->netdev,
4208                            "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
4209                            err);
4210
4211 unlock:
4212         mutex_unlock(&priv->state_lock);
4213         rtnl_unlock();
4214 }
4215
4216 static void mlx5e_tx_timeout(struct net_device *dev)
4217 {
4218         struct mlx5e_priv *priv = netdev_priv(dev);
4219
4220         netdev_err(dev, "TX timeout detected\n");
4221         queue_work(priv->wq, &priv->tx_timeout_work);
4222 }
4223
4224 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4225 {
4226         struct net_device *netdev = priv->netdev;
4227         struct mlx5e_channels new_channels = {};
4228
4229         if (priv->channels.params.lro_en) {
4230                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4231                 return -EINVAL;
4232         }
4233
4234         if (MLX5_IPSEC_DEV(priv->mdev)) {
4235                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4236                 return -EINVAL;
4237         }
4238
4239         new_channels.params = priv->channels.params;
4240         new_channels.params.xdp_prog = prog;
4241
4242         if (!mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) {
4243                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4244                             new_channels.params.sw_mtu, MLX5E_XDP_MAX_MTU);
4245                 return -EINVAL;
4246         }
4247
4248         return 0;
4249 }
4250
4251 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4252 {
4253         struct mlx5e_priv *priv = netdev_priv(netdev);
4254         struct bpf_prog *old_prog;
4255         bool reset, was_opened;
4256         int err = 0;
4257         int i;
4258
4259         mutex_lock(&priv->state_lock);
4260
4261         if (prog) {
4262                 err = mlx5e_xdp_allowed(priv, prog);
4263                 if (err)
4264                         goto unlock;
4265         }
4266
4267         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4268         /* no need for full reset when exchanging programs */
4269         reset = (!priv->channels.params.xdp_prog || !prog);
4270
4271         if (was_opened && reset)
4272                 mlx5e_close_locked(netdev);
4273         if (was_opened && !reset) {
4274                 /* num_channels is invariant here, so we can take the
4275                  * batched reference right upfront.
4276                  */
4277                 prog = bpf_prog_add(prog, priv->channels.num);
4278                 if (IS_ERR(prog)) {
4279                         err = PTR_ERR(prog);
4280                         goto unlock;
4281                 }
4282         }
4283
4284         /* exchange programs, extra prog reference we got from caller
4285          * as long as we don't fail from this point onwards.
4286          */
4287         old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4288         if (old_prog)
4289                 bpf_prog_put(old_prog);
4290
4291         if (reset) /* change RQ type according to priv->xdp_prog */
4292                 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4293
4294         if (was_opened && reset)
4295                 mlx5e_open_locked(netdev);
4296
4297         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4298                 goto unlock;
4299
4300         /* exchanging programs w/o reset, we update ref counts on behalf
4301          * of the channels RQs here.
4302          */
4303         for (i = 0; i < priv->channels.num; i++) {
4304                 struct mlx5e_channel *c = priv->channels.c[i];
4305
4306                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4307                 napi_synchronize(&c->napi);
4308                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4309
4310                 old_prog = xchg(&c->rq.xdp_prog, prog);
4311
4312                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4313                 /* napi_schedule in case we have missed anything */
4314                 napi_schedule(&c->napi);
4315
4316                 if (old_prog)
4317                         bpf_prog_put(old_prog);
4318         }
4319
4320 unlock:
4321         mutex_unlock(&priv->state_lock);
4322         return err;
4323 }
4324
4325 static u32 mlx5e_xdp_query(struct net_device *dev)
4326 {
4327         struct mlx5e_priv *priv = netdev_priv(dev);
4328         const struct bpf_prog *xdp_prog;
4329         u32 prog_id = 0;
4330
4331         mutex_lock(&priv->state_lock);
4332         xdp_prog = priv->channels.params.xdp_prog;
4333         if (xdp_prog)
4334                 prog_id = xdp_prog->aux->id;
4335         mutex_unlock(&priv->state_lock);
4336
4337         return prog_id;
4338 }
4339
4340 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4341 {
4342         switch (xdp->command) {
4343         case XDP_SETUP_PROG:
4344                 return mlx5e_xdp_set(dev, xdp->prog);
4345         case XDP_QUERY_PROG:
4346                 xdp->prog_id = mlx5e_xdp_query(dev);
4347                 return 0;
4348         default:
4349                 return -EINVAL;
4350         }
4351 }
4352
4353 const struct net_device_ops mlx5e_netdev_ops = {
4354         .ndo_open                = mlx5e_open,
4355         .ndo_stop                = mlx5e_close,
4356         .ndo_start_xmit          = mlx5e_xmit,
4357         .ndo_setup_tc            = mlx5e_setup_tc,
4358         .ndo_select_queue        = mlx5e_select_queue,
4359         .ndo_get_stats64         = mlx5e_get_stats,
4360         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4361         .ndo_set_mac_address     = mlx5e_set_mac,
4362         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4363         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4364         .ndo_set_features        = mlx5e_set_features,
4365         .ndo_fix_features        = mlx5e_fix_features,
4366         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4367         .ndo_do_ioctl            = mlx5e_ioctl,
4368         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4369         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
4370         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
4371         .ndo_features_check      = mlx5e_features_check,
4372         .ndo_tx_timeout          = mlx5e_tx_timeout,
4373         .ndo_bpf                 = mlx5e_xdp,
4374         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4375 #ifdef CONFIG_MLX5_EN_ARFS
4376         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4377 #endif
4378 #ifdef CONFIG_MLX5_ESWITCH
4379         /* SRIOV E-Switch NDOs */
4380         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4381         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4382         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4383         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4384         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4385         .ndo_get_vf_config       = mlx5e_get_vf_config,
4386         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4387         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4388 #endif
4389 };
4390
4391 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4392 {
4393         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4394                 return -EOPNOTSUPP;
4395         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4396             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4397             !MLX5_CAP_ETH(mdev, csum_cap) ||
4398             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4399             !MLX5_CAP_ETH(mdev, vlan_cap) ||
4400             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4401             MLX5_CAP_FLOWTABLE(mdev,
4402                                flow_table_properties_nic_receive.max_ft_level)
4403                                < 3) {
4404                 mlx5_core_warn(mdev,
4405                                "Not creating net device, some required device capabilities are missing\n");
4406                 return -EOPNOTSUPP;
4407         }
4408         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4409                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4410         if (!MLX5_CAP_GEN(mdev, cq_moderation))
4411                 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4412
4413         return 0;
4414 }
4415
4416 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4417                                    int num_channels)
4418 {
4419         int i;
4420
4421         for (i = 0; i < len; i++)
4422                 indirection_rqt[i] = i % num_channels;
4423 }
4424
4425 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4426 {
4427         u32 link_speed = 0;
4428         u32 pci_bw = 0;
4429
4430         mlx5e_port_max_linkspeed(mdev, &link_speed);
4431         pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4432         mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4433                            link_speed, pci_bw);
4434
4435 #define MLX5E_SLOW_PCI_RATIO (2)
4436
4437         return link_speed && pci_bw &&
4438                 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4439 }
4440
4441 static struct net_dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4442 {
4443         struct net_dim_cq_moder moder;
4444
4445         moder.cq_period_mode = cq_period_mode;
4446         moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4447         moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4448         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4449                 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4450
4451         return moder;
4452 }
4453
4454 static struct net_dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4455 {
4456         struct net_dim_cq_moder moder;
4457
4458         moder.cq_period_mode = cq_period_mode;
4459         moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4460         moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4461         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4462                 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4463
4464         return moder;
4465 }
4466
4467 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4468 {
4469         return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4470                 NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4471                 NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4472 }
4473
4474 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4475 {
4476         if (params->tx_dim_enabled) {
4477                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4478
4479                 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4480         } else {
4481                 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4482         }
4483
4484         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4485                         params->tx_cq_moderation.cq_period_mode ==
4486                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4487 }
4488
4489 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4490 {
4491         if (params->rx_dim_enabled) {
4492                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4493
4494                 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4495         } else {
4496                 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4497         }
4498
4499         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4500                         params->rx_cq_moderation.cq_period_mode ==
4501                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4502 }
4503
4504 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4505 {
4506         int i;
4507
4508         /* The supported periods are organized in ascending order */
4509         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4510                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4511                         break;
4512
4513         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4514 }
4515
4516 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
4517                            struct mlx5e_params *params)
4518 {
4519         /* Prefer Striding RQ, unless any of the following holds:
4520          * - Striding RQ configuration is not possible/supported.
4521          * - Slow PCI heuristic.
4522          * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4523          */
4524         if (!slow_pci_heuristic(mdev) &&
4525             mlx5e_striding_rq_possible(mdev, params) &&
4526             (mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ||
4527              !mlx5e_rx_is_linear_skb(mdev, params)))
4528                 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4529         mlx5e_set_rq_type(mdev, params);
4530         mlx5e_init_rq_type_params(mdev, params);
4531 }
4532
4533 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4534                             u16 num_channels)
4535 {
4536         enum mlx5e_traffic_types tt;
4537
4538         rss_params->hfunc = ETH_RSS_HASH_XOR;
4539         netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4540                             sizeof(rss_params->toeplitz_hash_key));
4541         mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4542                                       MLX5E_INDIR_RQT_SIZE, num_channels);
4543         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4544                 rss_params->rx_hash_fields[tt] =
4545                         tirc_default_config[tt].rx_hash_fields;
4546 }
4547
4548 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4549                             struct mlx5e_rss_params *rss_params,
4550                             struct mlx5e_params *params,
4551                             u16 max_channels, u16 mtu)
4552 {
4553         u8 rx_cq_period_mode;
4554
4555         params->sw_mtu = mtu;
4556         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4557         params->num_channels = max_channels;
4558         params->num_tc       = 1;
4559
4560         /* SQ */
4561         params->log_sq_size = is_kdump_kernel() ?
4562                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4563                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4564
4565         /* set CQE compression */
4566         params->rx_cqe_compress_def = false;
4567         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4568             MLX5_CAP_GEN(mdev, vport_group_manager))
4569                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4570
4571         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4572         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4573
4574         /* RQ */
4575         mlx5e_build_rq_params(mdev, params);
4576
4577         /* HW LRO */
4578
4579         /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4580         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
4581                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
4582                         params->lro_en = !slow_pci_heuristic(mdev);
4583         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4584
4585         /* CQ moderation params */
4586         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4587                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4588                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4589         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4590         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4591         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4592         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4593
4594         /* TX inline */
4595         params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
4596
4597         /* RSS */
4598         mlx5e_build_rss_params(rss_params, params->num_channels);
4599 }
4600
4601 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4602 {
4603         struct mlx5e_priv *priv = netdev_priv(netdev);
4604
4605         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
4606         if (is_zero_ether_addr(netdev->dev_addr) &&
4607             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4608                 eth_hw_addr_random(netdev);
4609                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4610         }
4611 }
4612
4613 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4614 {
4615         struct mlx5e_priv *priv = netdev_priv(netdev);
4616         struct mlx5_core_dev *mdev = priv->mdev;
4617         bool fcs_supported;
4618         bool fcs_enabled;
4619
4620         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4621
4622         netdev->netdev_ops = &mlx5e_netdev_ops;
4623
4624 #ifdef CONFIG_MLX5_CORE_EN_DCB
4625         if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4626                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4627 #endif
4628
4629         netdev->watchdog_timeo    = 15 * HZ;
4630
4631         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4632
4633         netdev->vlan_features    |= NETIF_F_SG;
4634         netdev->vlan_features    |= NETIF_F_IP_CSUM;
4635         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
4636         netdev->vlan_features    |= NETIF_F_GRO;
4637         netdev->vlan_features    |= NETIF_F_TSO;
4638         netdev->vlan_features    |= NETIF_F_TSO6;
4639         netdev->vlan_features    |= NETIF_F_RXCSUM;
4640         netdev->vlan_features    |= NETIF_F_RXHASH;
4641
4642         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4643         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4644
4645         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4646             mlx5e_check_fragmented_striding_rq_cap(mdev))
4647                 netdev->vlan_features    |= NETIF_F_LRO;
4648
4649         netdev->hw_features       = netdev->vlan_features;
4650         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4651         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4652         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4653         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4654
4655         if (mlx5_vxlan_allowed(mdev->vxlan) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4656                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4657                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4658                 netdev->hw_enc_features |= NETIF_F_TSO;
4659                 netdev->hw_enc_features |= NETIF_F_TSO6;
4660                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4661         }
4662
4663         if (mlx5_vxlan_allowed(mdev->vxlan)) {
4664                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4665                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4666                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4667                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4668                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4669         }
4670
4671         if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4672                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4673                                            NETIF_F_GSO_GRE_CSUM;
4674                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4675                                            NETIF_F_GSO_GRE_CSUM;
4676                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4677                                                 NETIF_F_GSO_GRE_CSUM;
4678         }
4679
4680         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4681         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4682         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4683         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4684
4685         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4686
4687         if (fcs_supported)
4688                 netdev->hw_features |= NETIF_F_RXALL;
4689
4690         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4691                 netdev->hw_features |= NETIF_F_RXFCS;
4692
4693         netdev->features          = netdev->hw_features;
4694         if (!priv->channels.params.lro_en)
4695                 netdev->features  &= ~NETIF_F_LRO;
4696
4697         if (fcs_enabled)
4698                 netdev->features  &= ~NETIF_F_RXALL;
4699
4700         if (!priv->channels.params.scatter_fcs_en)
4701                 netdev->features  &= ~NETIF_F_RXFCS;
4702
4703 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4704         if (FT_CAP(flow_modify_en) &&
4705             FT_CAP(modify_root) &&
4706             FT_CAP(identified_miss_table_mode) &&
4707             FT_CAP(flow_table_modify)) {
4708 #ifdef CONFIG_MLX5_ESWITCH
4709                 netdev->hw_features      |= NETIF_F_HW_TC;
4710 #endif
4711 #ifdef CONFIG_MLX5_EN_ARFS
4712                 netdev->hw_features      |= NETIF_F_NTUPLE;
4713 #endif
4714         }
4715
4716         netdev->features         |= NETIF_F_HIGHDMA;
4717         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4718
4719         netdev->priv_flags       |= IFF_UNICAST_FLT;
4720
4721         mlx5e_set_netdev_dev_addr(netdev);
4722         mlx5e_ipsec_build_netdev(priv);
4723         mlx5e_tls_build_netdev(priv);
4724 }
4725
4726 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4727 {
4728         struct mlx5_core_dev *mdev = priv->mdev;
4729         int err;
4730
4731         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4732         if (err) {
4733                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4734                 priv->q_counter = 0;
4735         }
4736
4737         err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4738         if (err) {
4739                 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4740                 priv->drop_rq_q_counter = 0;
4741         }
4742 }
4743
4744 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4745 {
4746         if (priv->q_counter)
4747                 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4748
4749         if (priv->drop_rq_q_counter)
4750                 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4751 }
4752
4753 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4754                           struct net_device *netdev,
4755                           const struct mlx5e_profile *profile,
4756                           void *ppriv)
4757 {
4758         struct mlx5e_priv *priv = netdev_priv(netdev);
4759         struct mlx5e_rss_params *rss = &priv->rss_params;
4760         int err;
4761
4762         err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv);
4763         if (err)
4764                 return err;
4765
4766         mlx5e_build_nic_params(mdev, rss, &priv->channels.params,
4767                                mlx5e_get_netdev_max_channels(netdev),
4768                                netdev->mtu);
4769
4770         mlx5e_timestamp_init(priv);
4771
4772         err = mlx5e_ipsec_init(priv);
4773         if (err)
4774                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4775         err = mlx5e_tls_init(priv);
4776         if (err)
4777                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4778         mlx5e_build_nic_netdev(netdev);
4779         mlx5e_build_tc2txq_maps(priv);
4780
4781         return 0;
4782 }
4783
4784 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4785 {
4786         mlx5e_tls_cleanup(priv);
4787         mlx5e_ipsec_cleanup(priv);
4788         mlx5e_netdev_cleanup(priv->netdev, priv);
4789 }
4790
4791 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4792 {
4793         struct mlx5_core_dev *mdev = priv->mdev;
4794         int err;
4795
4796         mlx5e_create_q_counters(priv);
4797
4798         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4799         if (err) {
4800                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4801                 goto err_destroy_q_counters;
4802         }
4803
4804         err = mlx5e_create_indirect_rqt(priv);
4805         if (err)
4806                 goto err_close_drop_rq;
4807
4808         err = mlx5e_create_direct_rqts(priv);
4809         if (err)
4810                 goto err_destroy_indirect_rqts;
4811
4812         err = mlx5e_create_indirect_tirs(priv, true);
4813         if (err)
4814                 goto err_destroy_direct_rqts;
4815
4816         err = mlx5e_create_direct_tirs(priv);
4817         if (err)
4818                 goto err_destroy_indirect_tirs;
4819
4820         err = mlx5e_create_flow_steering(priv);
4821         if (err) {
4822                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4823                 goto err_destroy_direct_tirs;
4824         }
4825
4826         err = mlx5e_tc_nic_init(priv);
4827         if (err)
4828                 goto err_destroy_flow_steering;
4829
4830         return 0;
4831
4832 err_destroy_flow_steering:
4833         mlx5e_destroy_flow_steering(priv);
4834 err_destroy_direct_tirs:
4835         mlx5e_destroy_direct_tirs(priv);
4836 err_destroy_indirect_tirs:
4837         mlx5e_destroy_indirect_tirs(priv, true);
4838 err_destroy_direct_rqts:
4839         mlx5e_destroy_direct_rqts(priv);
4840 err_destroy_indirect_rqts:
4841         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4842 err_close_drop_rq:
4843         mlx5e_close_drop_rq(&priv->drop_rq);
4844 err_destroy_q_counters:
4845         mlx5e_destroy_q_counters(priv);
4846         return err;
4847 }
4848
4849 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4850 {
4851         mlx5e_tc_nic_cleanup(priv);
4852         mlx5e_destroy_flow_steering(priv);
4853         mlx5e_destroy_direct_tirs(priv);
4854         mlx5e_destroy_indirect_tirs(priv, true);
4855         mlx5e_destroy_direct_rqts(priv);
4856         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4857         mlx5e_close_drop_rq(&priv->drop_rq);
4858         mlx5e_destroy_q_counters(priv);
4859 }
4860
4861 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4862 {
4863         int err;
4864
4865         err = mlx5e_create_tises(priv);
4866         if (err) {
4867                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4868                 return err;
4869         }
4870
4871 #ifdef CONFIG_MLX5_CORE_EN_DCB
4872         mlx5e_dcbnl_initialize(priv);
4873 #endif
4874         return 0;
4875 }
4876
4877 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4878 {
4879         struct net_device *netdev = priv->netdev;
4880         struct mlx5_core_dev *mdev = priv->mdev;
4881         u16 max_mtu;
4882
4883         mlx5e_init_l2_addr(priv);
4884
4885         /* Marking the link as currently not needed by the Driver */
4886         if (!netif_running(netdev))
4887                 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4888
4889         /* MTU range: 68 - hw-specific max */
4890         netdev->min_mtu = ETH_MIN_MTU;
4891         mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4892         netdev->max_mtu = MLX5E_HW2SW_MTU(&priv->channels.params, max_mtu);
4893         mlx5e_set_dev_port_mtu(priv);
4894
4895         mlx5_lag_add(mdev, netdev);
4896
4897         mlx5e_enable_async_events(priv);
4898         if (mlx5e_monitor_counter_supported(priv))
4899                 mlx5e_monitor_counter_init(priv);
4900
4901         if (netdev->reg_state != NETREG_REGISTERED)
4902                 return;
4903 #ifdef CONFIG_MLX5_CORE_EN_DCB
4904         mlx5e_dcbnl_init_app(priv);
4905 #endif
4906
4907         queue_work(priv->wq, &priv->set_rx_mode_work);
4908
4909         rtnl_lock();
4910         if (netif_running(netdev))
4911                 mlx5e_open(netdev);
4912         netif_device_attach(netdev);
4913         rtnl_unlock();
4914 }
4915
4916 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4917 {
4918         struct mlx5_core_dev *mdev = priv->mdev;
4919
4920 #ifdef CONFIG_MLX5_CORE_EN_DCB
4921         if (priv->netdev->reg_state == NETREG_REGISTERED)
4922                 mlx5e_dcbnl_delete_app(priv);
4923 #endif
4924
4925         rtnl_lock();
4926         if (netif_running(priv->netdev))
4927                 mlx5e_close(priv->netdev);
4928         netif_device_detach(priv->netdev);
4929         rtnl_unlock();
4930
4931         queue_work(priv->wq, &priv->set_rx_mode_work);
4932
4933         if (mlx5e_monitor_counter_supported(priv))
4934                 mlx5e_monitor_counter_cleanup(priv);
4935
4936         mlx5e_disable_async_events(priv);
4937         mlx5_lag_remove(mdev);
4938 }
4939
4940 static const struct mlx5e_profile mlx5e_nic_profile = {
4941         .init              = mlx5e_nic_init,
4942         .cleanup           = mlx5e_nic_cleanup,
4943         .init_rx           = mlx5e_init_nic_rx,
4944         .cleanup_rx        = mlx5e_cleanup_nic_rx,
4945         .init_tx           = mlx5e_init_nic_tx,
4946         .cleanup_tx        = mlx5e_cleanup_nic_tx,
4947         .enable            = mlx5e_nic_enable,
4948         .disable           = mlx5e_nic_disable,
4949         .update_stats      = mlx5e_update_ndo_stats,
4950         .update_carrier    = mlx5e_update_carrier,
4951         .rx_handlers.handle_rx_cqe       = mlx5e_handle_rx_cqe,
4952         .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4953         .max_tc            = MLX5E_MAX_NUM_TC,
4954 };
4955
4956 /* mlx5e generic netdev management API (move to en_common.c) */
4957
4958 /* mlx5e_netdev_init/cleanup must be called from profile->init/cleanup callbacks */
4959 int mlx5e_netdev_init(struct net_device *netdev,
4960                       struct mlx5e_priv *priv,
4961                       struct mlx5_core_dev *mdev,
4962                       const struct mlx5e_profile *profile,
4963                       void *ppriv)
4964 {
4965         /* priv init */
4966         priv->mdev        = mdev;
4967         priv->netdev      = netdev;
4968         priv->profile     = profile;
4969         priv->ppriv       = ppriv;
4970         priv->msglevel    = MLX5E_MSG_LEVEL;
4971         priv->max_opened_tc = 1;
4972
4973         mutex_init(&priv->state_lock);
4974         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4975         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4976         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
4977         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4978
4979         priv->wq = create_singlethread_workqueue("mlx5e");
4980         if (!priv->wq)
4981                 return -ENOMEM;
4982
4983         /* netdev init */
4984         netif_carrier_off(netdev);
4985
4986 #ifdef CONFIG_MLX5_EN_ARFS
4987         netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(mdev);
4988 #endif
4989
4990         return 0;
4991 }
4992
4993 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv)
4994 {
4995         destroy_workqueue(priv->wq);
4996 }
4997
4998 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4999                                        const struct mlx5e_profile *profile,
5000                                        int nch,
5001                                        void *ppriv)
5002 {
5003         struct net_device *netdev;
5004         int err;
5005
5006         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
5007                                     nch * profile->max_tc,
5008                                     nch);
5009         if (!netdev) {
5010                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5011                 return NULL;
5012         }
5013
5014         err = profile->init(mdev, netdev, profile, ppriv);
5015         if (err) {
5016                 mlx5_core_err(mdev, "failed to init mlx5e profile %d\n", err);
5017                 goto err_free_netdev;
5018         }
5019
5020         return netdev;
5021
5022 err_free_netdev:
5023         free_netdev(netdev);
5024
5025         return NULL;
5026 }
5027
5028 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5029 {
5030         const struct mlx5e_profile *profile;
5031         int max_nch;
5032         int err;
5033
5034         profile = priv->profile;
5035         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5036
5037         /* max number of channels may have changed */
5038         max_nch = mlx5e_get_max_num_channels(priv->mdev);
5039         if (priv->channels.params.num_channels > max_nch) {
5040                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5041                 priv->channels.params.num_channels = max_nch;
5042                 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
5043                                               MLX5E_INDIR_RQT_SIZE, max_nch);
5044         }
5045
5046         err = profile->init_tx(priv);
5047         if (err)
5048                 goto out;
5049
5050         err = profile->init_rx(priv);
5051         if (err)
5052                 goto err_cleanup_tx;
5053
5054         if (profile->enable)
5055                 profile->enable(priv);
5056
5057         return 0;
5058
5059 err_cleanup_tx:
5060         profile->cleanup_tx(priv);
5061
5062 out:
5063         return err;
5064 }
5065
5066 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5067 {
5068         const struct mlx5e_profile *profile = priv->profile;
5069
5070         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5071
5072         if (profile->disable)
5073                 profile->disable(priv);
5074         flush_workqueue(priv->wq);
5075
5076         profile->cleanup_rx(priv);
5077         profile->cleanup_tx(priv);
5078         cancel_work_sync(&priv->update_stats_work);
5079 }
5080
5081 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5082 {
5083         const struct mlx5e_profile *profile = priv->profile;
5084         struct net_device *netdev = priv->netdev;
5085
5086         if (profile->cleanup)
5087                 profile->cleanup(priv);
5088         free_netdev(netdev);
5089 }
5090
5091 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5092  * hardware contexts and to connect it to the current netdev.
5093  */
5094 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5095 {
5096         struct mlx5e_priv *priv = vpriv;
5097         struct net_device *netdev = priv->netdev;
5098         int err;
5099
5100         if (netif_device_present(netdev))
5101                 return 0;
5102
5103         err = mlx5e_create_mdev_resources(mdev);
5104         if (err)
5105                 return err;
5106
5107         err = mlx5e_attach_netdev(priv);
5108         if (err) {
5109                 mlx5e_destroy_mdev_resources(mdev);
5110                 return err;
5111         }
5112
5113         return 0;
5114 }
5115
5116 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5117 {
5118         struct mlx5e_priv *priv = vpriv;
5119         struct net_device *netdev = priv->netdev;
5120
5121         if (!netif_device_present(netdev))
5122                 return;
5123
5124         mlx5e_detach_netdev(priv);
5125         mlx5e_destroy_mdev_resources(mdev);
5126 }
5127
5128 static void *mlx5e_add(struct mlx5_core_dev *mdev)
5129 {
5130         struct net_device *netdev;
5131         void *priv;
5132         int err;
5133         int nch;
5134
5135         err = mlx5e_check_required_hca_cap(mdev);
5136         if (err)
5137                 return NULL;
5138
5139 #ifdef CONFIG_MLX5_ESWITCH
5140         if (MLX5_ESWITCH_MANAGER(mdev) &&
5141             mlx5_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
5142                 mlx5e_rep_register_vport_reps(mdev);
5143                 return mdev;
5144         }
5145 #endif
5146
5147         nch = mlx5e_get_max_num_channels(mdev);
5148         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, nch, NULL);
5149         if (!netdev) {
5150                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5151                 return NULL;
5152         }
5153
5154         priv = netdev_priv(netdev);
5155
5156         err = mlx5e_attach(mdev, priv);
5157         if (err) {
5158                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5159                 goto err_destroy_netdev;
5160         }
5161
5162         err = register_netdev(netdev);
5163         if (err) {
5164                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5165                 goto err_detach;
5166         }
5167
5168 #ifdef CONFIG_MLX5_CORE_EN_DCB
5169         mlx5e_dcbnl_init_app(priv);
5170 #endif
5171         return priv;
5172
5173 err_detach:
5174         mlx5e_detach(mdev, priv);
5175 err_destroy_netdev:
5176         mlx5e_destroy_netdev(priv);
5177         return NULL;
5178 }
5179
5180 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5181 {
5182         struct mlx5e_priv *priv;
5183
5184 #ifdef CONFIG_MLX5_ESWITCH
5185         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev) {
5186                 mlx5e_rep_unregister_vport_reps(mdev);
5187                 return;
5188         }
5189 #endif
5190         priv = vpriv;
5191 #ifdef CONFIG_MLX5_CORE_EN_DCB
5192         mlx5e_dcbnl_delete_app(priv);
5193 #endif
5194         unregister_netdev(priv->netdev);
5195         mlx5e_detach(mdev, vpriv);
5196         mlx5e_destroy_netdev(priv);
5197 }
5198
5199 static struct mlx5_interface mlx5e_interface = {
5200         .add       = mlx5e_add,
5201         .remove    = mlx5e_remove,
5202         .attach    = mlx5e_attach,
5203         .detach    = mlx5e_detach,
5204         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
5205 };
5206
5207 void mlx5e_init(void)
5208 {
5209         mlx5e_ipsec_build_inverse_table();
5210         mlx5e_build_ptys2ethtool_map();
5211         mlx5_register_interface(&mlx5e_interface);
5212 }
5213
5214 void mlx5e_cleanup(void)
5215 {
5216         mlx5_unregister_interface(&mlx5e_interface);
5217 }