2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <linux/bpf.h>
42 #include "en_accel/ipsec.h"
43 #include "en_accel/ipsec_rxtx.h"
44 #include "accel/ipsec.h"
47 struct mlx5e_rq_param {
48 u32 rqc[MLX5_ST_SZ_DW(rqc)];
49 struct mlx5_wq_param wq;
52 struct mlx5e_sq_param {
53 u32 sqc[MLX5_ST_SZ_DW(sqc)];
54 struct mlx5_wq_param wq;
57 struct mlx5e_cq_param {
58 u32 cqc[MLX5_ST_SZ_DW(cqc)];
59 struct mlx5_wq_param wq;
64 struct mlx5e_channel_param {
65 struct mlx5e_rq_param rq;
66 struct mlx5e_sq_param sq;
67 struct mlx5e_sq_param xdp_sq;
68 struct mlx5e_sq_param icosq;
69 struct mlx5e_cq_param rx_cq;
70 struct mlx5e_cq_param tx_cq;
71 struct mlx5e_cq_param icosq_cq;
74 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
76 return MLX5_CAP_GEN(mdev, striding_rq) &&
77 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
78 MLX5_CAP_ETH(mdev, reg_umr_sq);
81 void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev,
82 struct mlx5e_params *params, u8 rq_type)
84 params->rq_wq_type = rq_type;
85 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
86 switch (params->rq_wq_type) {
87 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
88 params->log_rq_size = is_kdump_kernel() ?
89 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
90 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
91 params->mpwqe_log_stride_sz =
92 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
93 MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) :
94 MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev);
95 params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
96 params->mpwqe_log_stride_sz;
98 default: /* MLX5_WQ_TYPE_LINKED_LIST */
99 params->log_rq_size = is_kdump_kernel() ?
100 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
101 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
102 params->rq_headroom = params->xdp_prog ?
103 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
104 params->rq_headroom += NET_IP_ALIGN;
106 /* Extra room needed for build_skb */
107 params->lro_wqe_sz -= params->rq_headroom +
108 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
111 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
112 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
113 BIT(params->log_rq_size),
114 BIT(params->mpwqe_log_stride_sz),
115 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
118 static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
120 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) &&
121 !params->xdp_prog && !MLX5_IPSEC_DEV(mdev) ?
122 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
123 MLX5_WQ_TYPE_LINKED_LIST;
124 mlx5e_set_rq_type_params(mdev, params, rq_type);
127 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
129 struct mlx5_core_dev *mdev = priv->mdev;
132 port_state = mlx5_query_vport_state(mdev,
133 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
136 if (port_state == VPORT_STATE_UP) {
137 netdev_info(priv->netdev, "Link up\n");
138 netif_carrier_on(priv->netdev);
140 netdev_info(priv->netdev, "Link down\n");
141 netif_carrier_off(priv->netdev);
145 static void mlx5e_update_carrier_work(struct work_struct *work)
147 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
148 update_carrier_work);
150 mutex_lock(&priv->state_lock);
151 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
152 if (priv->profile->update_carrier)
153 priv->profile->update_carrier(priv);
154 mutex_unlock(&priv->state_lock);
157 static void mlx5e_tx_timeout_work(struct work_struct *work)
159 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
164 mutex_lock(&priv->state_lock);
165 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
167 mlx5e_close_locked(priv->netdev);
168 err = mlx5e_open_locked(priv->netdev);
170 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
173 mutex_unlock(&priv->state_lock);
177 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
179 struct mlx5e_sw_stats temp, *s = &temp;
180 struct mlx5e_rq_stats *rq_stats;
181 struct mlx5e_sq_stats *sq_stats;
182 u64 tx_offload_none = 0;
185 memset(s, 0, sizeof(*s));
186 for (i = 0; i < priv->channels.num; i++) {
187 struct mlx5e_channel *c = priv->channels.c[i];
189 rq_stats = &c->rq.stats;
191 s->rx_packets += rq_stats->packets;
192 s->rx_bytes += rq_stats->bytes;
193 s->rx_lro_packets += rq_stats->lro_packets;
194 s->rx_lro_bytes += rq_stats->lro_bytes;
195 s->rx_csum_none += rq_stats->csum_none;
196 s->rx_csum_complete += rq_stats->csum_complete;
197 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
198 s->rx_xdp_drop += rq_stats->xdp_drop;
199 s->rx_xdp_tx += rq_stats->xdp_tx;
200 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
201 s->rx_wqe_err += rq_stats->wqe_err;
202 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
203 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
204 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
205 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
206 s->rx_page_reuse += rq_stats->page_reuse;
207 s->rx_cache_reuse += rq_stats->cache_reuse;
208 s->rx_cache_full += rq_stats->cache_full;
209 s->rx_cache_empty += rq_stats->cache_empty;
210 s->rx_cache_busy += rq_stats->cache_busy;
212 for (j = 0; j < priv->channels.params.num_tc; j++) {
213 sq_stats = &c->sq[j].stats;
215 s->tx_packets += sq_stats->packets;
216 s->tx_bytes += sq_stats->bytes;
217 s->tx_tso_packets += sq_stats->tso_packets;
218 s->tx_tso_bytes += sq_stats->tso_bytes;
219 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
220 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
221 s->tx_queue_stopped += sq_stats->stopped;
222 s->tx_queue_wake += sq_stats->wake;
223 s->tx_queue_dropped += sq_stats->dropped;
224 s->tx_xmit_more += sq_stats->xmit_more;
225 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
226 tx_offload_none += sq_stats->csum_none;
230 /* Update calculated offload counters */
231 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
232 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
234 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
235 priv->stats.pport.phy_counters,
236 counter_set.phys_layer_cntrs.link_down_events);
237 memcpy(&priv->stats.sw, s, sizeof(*s));
240 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
242 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
243 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
244 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
245 struct mlx5_core_dev *mdev = priv->mdev;
247 MLX5_SET(query_vport_counter_in, in, opcode,
248 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
249 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
250 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
252 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
255 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv, bool full)
257 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
258 struct mlx5_core_dev *mdev = priv->mdev;
259 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
260 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
264 MLX5_SET(ppcnt_reg, in, local_port, 1);
266 out = pstats->IEEE_802_3_counters;
267 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
268 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
273 out = pstats->RFC_2863_counters;
274 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
275 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
277 out = pstats->RFC_2819_counters;
278 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
279 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
281 out = pstats->phy_counters;
282 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
283 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
285 if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
286 out = pstats->phy_statistical_counters;
287 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
288 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
291 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
292 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
293 out = pstats->per_prio_counters[prio];
294 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
295 mlx5_core_access_reg(mdev, in, sz, out, sz,
296 MLX5_REG_PPCNT, 0, 0);
300 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
302 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
303 u32 out[MLX5_ST_SZ_DW(query_q_counter_out)];
306 if (!priv->q_counter)
309 err = mlx5_core_query_q_counter(priv->mdev, priv->q_counter, 0, out, sizeof(out));
313 qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out, out, out_of_buffer);
316 static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
318 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
319 struct mlx5_core_dev *mdev = priv->mdev;
320 u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0};
321 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
324 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
327 out = pcie_stats->pcie_perf_counters;
328 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
329 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
332 void mlx5e_update_stats(struct mlx5e_priv *priv, bool full)
335 mlx5e_update_pcie_counters(priv);
336 mlx5e_ipsec_update_stats(priv);
338 mlx5e_update_pport_counters(priv, full);
339 mlx5e_update_vport_counters(priv);
340 mlx5e_update_q_counter(priv);
341 mlx5e_update_sw_counters(priv);
344 static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
346 mlx5e_update_stats(priv, false);
349 void mlx5e_update_stats_work(struct work_struct *work)
351 struct delayed_work *dwork = to_delayed_work(work);
352 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
354 mutex_lock(&priv->state_lock);
355 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
356 priv->profile->update_stats(priv);
357 queue_delayed_work(priv->wq, dwork,
358 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
360 mutex_unlock(&priv->state_lock);
363 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
364 enum mlx5_dev_event event, unsigned long param)
366 struct mlx5e_priv *priv = vpriv;
367 struct ptp_clock_event ptp_event;
368 struct mlx5_eqe *eqe = NULL;
370 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
374 case MLX5_DEV_EVENT_PORT_UP:
375 case MLX5_DEV_EVENT_PORT_DOWN:
376 queue_work(priv->wq, &priv->update_carrier_work);
378 case MLX5_DEV_EVENT_PPS:
379 eqe = (struct mlx5_eqe *)param;
380 ptp_event.type = PTP_CLOCK_EXTTS;
381 ptp_event.index = eqe->data.pps.pin;
382 ptp_event.timestamp =
383 timecounter_cyc2time(&priv->tstamp.clock,
384 be64_to_cpu(eqe->data.pps.time_stamp));
385 mlx5e_pps_event_handler(vpriv, &ptp_event);
392 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
394 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
397 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
399 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
400 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
403 static inline int mlx5e_get_wqe_mtt_sz(void)
405 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
406 * To avoid copying garbage after the mtt array, we allocate
409 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
410 MLX5_UMR_MTT_ALIGNMENT);
413 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
414 struct mlx5e_icosq *sq,
415 struct mlx5e_umr_wqe *wqe,
418 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
419 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
420 struct mlx5_wqe_data_seg *dseg = &wqe->data;
421 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
422 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
423 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
425 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
427 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
428 cseg->imm = rq->mkey_be;
430 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
431 ucseg->xlt_octowords =
432 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
433 ucseg->bsf_octowords =
434 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
435 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
437 dseg->lkey = sq->mkey_be;
438 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
441 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
442 struct mlx5e_channel *c)
444 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
445 int mtt_sz = mlx5e_get_wqe_mtt_sz();
446 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
449 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
450 GFP_KERNEL, cpu_to_node(c->cpu));
454 /* We allocate more than mtt_sz as we will align the pointer */
455 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
456 cpu_to_node(c->cpu));
457 if (unlikely(!rq->mpwqe.mtt_no_align))
458 goto err_free_wqe_info;
460 for (i = 0; i < wq_sz; i++) {
461 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
463 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
465 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
467 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
470 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
477 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
479 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
482 kfree(rq->mpwqe.mtt_no_align);
484 kfree(rq->mpwqe.info);
490 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
492 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
493 int mtt_sz = mlx5e_get_wqe_mtt_sz();
496 for (i = 0; i < wq_sz; i++) {
497 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
499 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
502 kfree(rq->mpwqe.mtt_no_align);
503 kfree(rq->mpwqe.info);
506 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
507 u64 npages, u8 page_shift,
508 struct mlx5_core_mkey *umr_mkey)
510 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
515 if (!MLX5E_VALID_NUM_MTTS(npages))
518 in = kvzalloc(inlen, GFP_KERNEL);
522 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
524 MLX5_SET(mkc, mkc, free, 1);
525 MLX5_SET(mkc, mkc, umr_en, 1);
526 MLX5_SET(mkc, mkc, lw, 1);
527 MLX5_SET(mkc, mkc, lr, 1);
528 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
530 MLX5_SET(mkc, mkc, qpn, 0xffffff);
531 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
532 MLX5_SET64(mkc, mkc, len, npages << page_shift);
533 MLX5_SET(mkc, mkc, translations_octword_size,
534 MLX5_MTT_OCTW(npages));
535 MLX5_SET(mkc, mkc, log_page_size, page_shift);
537 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
543 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
545 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
547 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
550 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
551 struct mlx5e_params *params,
552 struct mlx5e_rq_param *rqp,
555 struct mlx5_core_dev *mdev = c->mdev;
556 void *rqc = rqp->rqc;
557 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
564 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
566 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
571 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
573 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
575 rq->wq_type = params->rq_wq_type;
577 rq->netdev = c->netdev;
578 rq->tstamp = c->tstamp;
583 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
584 if (IS_ERR(rq->xdp_prog)) {
585 err = PTR_ERR(rq->xdp_prog);
587 goto err_rq_wq_destroy;
590 rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
591 rq->rx_headroom = params->rq_headroom;
593 switch (rq->wq_type) {
594 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
596 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
597 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
599 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
600 #ifdef CONFIG_MLX5_EN_IPSEC
601 if (MLX5_IPSEC_DEV(mdev)) {
603 netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
604 goto err_rq_wq_destroy;
607 if (!rq->handle_rx_cqe) {
609 netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
610 goto err_rq_wq_destroy;
613 rq->mpwqe_stride_sz = BIT(params->mpwqe_log_stride_sz);
614 rq->mpwqe_num_strides = BIT(params->mpwqe_log_num_strides);
616 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
617 byte_count = rq->buff.wqe_sz;
619 err = mlx5e_create_rq_umr_mkey(mdev, rq);
621 goto err_rq_wq_destroy;
622 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
624 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
626 goto err_destroy_umr_mkey;
628 default: /* MLX5_WQ_TYPE_LINKED_LIST */
630 kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info),
631 GFP_KERNEL, cpu_to_node(c->cpu));
632 if (!rq->wqe.frag_info) {
634 goto err_rq_wq_destroy;
636 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
637 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
639 #ifdef CONFIG_MLX5_EN_IPSEC
641 rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
644 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
645 if (!rq->handle_rx_cqe) {
646 kfree(rq->wqe.frag_info);
648 netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
649 goto err_rq_wq_destroy;
652 rq->buff.wqe_sz = params->lro_en ?
654 MLX5E_SW2HW_MTU(c->priv, c->netdev->mtu);
655 #ifdef CONFIG_MLX5_EN_IPSEC
656 if (MLX5_IPSEC_DEV(mdev))
657 rq->buff.wqe_sz += MLX5E_METADATA_ETHER_LEN;
659 rq->wqe.page_reuse = !params->xdp_prog && !params->lro_en;
660 byte_count = rq->buff.wqe_sz;
662 /* calc the required page order */
663 rq->wqe.frag_sz = MLX5_SKB_FRAG_SZ(rq->rx_headroom + byte_count);
664 npages = DIV_ROUND_UP(rq->wqe.frag_sz, PAGE_SIZE);
665 rq->buff.page_order = order_base_2(npages);
667 byte_count |= MLX5_HW_START_PADDING;
668 rq->mkey_be = c->mkey_be;
671 for (i = 0; i < wq_sz; i++) {
672 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
674 wqe->data.byte_count = cpu_to_be32(byte_count);
675 wqe->data.lkey = rq->mkey_be;
678 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
679 rq->am.mode = params->rx_cq_period_mode;
680 rq->page_cache.head = 0;
681 rq->page_cache.tail = 0;
685 err_destroy_umr_mkey:
686 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
690 bpf_prog_put(rq->xdp_prog);
691 mlx5_wq_destroy(&rq->wq_ctrl);
696 static void mlx5e_free_rq(struct mlx5e_rq *rq)
701 bpf_prog_put(rq->xdp_prog);
703 switch (rq->wq_type) {
704 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
705 mlx5e_rq_free_mpwqe_info(rq);
706 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
708 default: /* MLX5_WQ_TYPE_LINKED_LIST */
709 kfree(rq->wqe.frag_info);
712 for (i = rq->page_cache.head; i != rq->page_cache.tail;
713 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
714 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
716 mlx5e_page_release(rq, dma_info, false);
718 mlx5_wq_destroy(&rq->wq_ctrl);
721 static int mlx5e_create_rq(struct mlx5e_rq *rq,
722 struct mlx5e_rq_param *param)
724 struct mlx5_core_dev *mdev = rq->mdev;
732 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
733 sizeof(u64) * rq->wq_ctrl.buf.npages;
734 in = kvzalloc(inlen, GFP_KERNEL);
738 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
739 wq = MLX5_ADDR_OF(rqc, rqc, wq);
741 memcpy(rqc, param->rqc, sizeof(param->rqc));
743 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
744 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
745 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
746 MLX5_ADAPTER_PAGE_SHIFT);
747 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
749 mlx5_fill_page_array(&rq->wq_ctrl.buf,
750 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
752 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
759 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
762 struct mlx5e_channel *c = rq->channel;
763 struct mlx5_core_dev *mdev = c->mdev;
770 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
771 in = kvzalloc(inlen, GFP_KERNEL);
775 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
777 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
778 MLX5_SET(rqc, rqc, state, next_state);
780 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
787 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
789 struct mlx5e_channel *c = rq->channel;
790 struct mlx5e_priv *priv = c->priv;
791 struct mlx5_core_dev *mdev = priv->mdev;
798 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
799 in = kvzalloc(inlen, GFP_KERNEL);
803 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
805 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
806 MLX5_SET64(modify_rq_in, in, modify_bitmask,
807 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
808 MLX5_SET(rqc, rqc, scatter_fcs, enable);
809 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
811 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
818 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
820 struct mlx5e_channel *c = rq->channel;
821 struct mlx5_core_dev *mdev = c->mdev;
827 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
828 in = kvzalloc(inlen, GFP_KERNEL);
832 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
834 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
835 MLX5_SET64(modify_rq_in, in, modify_bitmask,
836 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
837 MLX5_SET(rqc, rqc, vsd, vsd);
838 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
840 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
847 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
849 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
852 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
854 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
855 struct mlx5e_channel *c = rq->channel;
857 struct mlx5_wq_ll *wq = &rq->wq;
858 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
860 while (time_before(jiffies, exp_time)) {
861 if (wq->cur_sz >= min_wqes)
867 netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
868 rq->rqn, wq->cur_sz, min_wqes);
872 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
874 struct mlx5_wq_ll *wq = &rq->wq;
875 struct mlx5e_rx_wqe *wqe;
879 /* UMR WQE (if in progress) is always at wq->head */
880 if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
881 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
883 while (!mlx5_wq_ll_is_empty(wq)) {
884 wqe_ix_be = *wq->tail_next;
885 wqe_ix = be16_to_cpu(wqe_ix_be);
886 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
887 rq->dealloc_wqe(rq, wqe_ix);
888 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
889 &wqe->next.next_wqe_index);
892 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST && rq->wqe.page_reuse) {
893 /* Clean outstanding pages on handled WQEs that decided to do page-reuse,
894 * but yet to be re-posted.
896 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
898 for (wqe_ix = 0; wqe_ix < wq_sz; wqe_ix++)
899 rq->dealloc_wqe(rq, wqe_ix);
903 static int mlx5e_open_rq(struct mlx5e_channel *c,
904 struct mlx5e_params *params,
905 struct mlx5e_rq_param *param,
910 err = mlx5e_alloc_rq(c, params, param, rq);
914 err = mlx5e_create_rq(rq, param);
918 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
922 if (params->rx_am_enabled)
923 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
928 mlx5e_destroy_rq(rq);
935 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
937 struct mlx5e_icosq *sq = &rq->channel->icosq;
938 u16 pi = sq->pc & sq->wq.sz_m1;
939 struct mlx5e_tx_wqe *nopwqe;
941 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
942 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
943 sq->db.ico_wqe[pi].num_wqebbs = 1;
944 nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
945 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
948 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
950 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
951 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
954 static void mlx5e_close_rq(struct mlx5e_rq *rq)
956 cancel_work_sync(&rq->am.work);
957 mlx5e_destroy_rq(rq);
958 mlx5e_free_rx_descs(rq);
962 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
967 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
969 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
971 sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
974 mlx5e_free_xdpsq_db(sq);
981 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
982 struct mlx5e_params *params,
983 struct mlx5e_sq_param *param,
984 struct mlx5e_xdpsq *sq)
986 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
987 struct mlx5_core_dev *mdev = c->mdev;
991 sq->mkey_be = c->mkey_be;
993 sq->uar_map = mdev->mlx5e_res.bfreg.map;
994 sq->min_inline_mode = params->tx_min_inline_mode;
996 param->wq.db_numa_node = cpu_to_node(c->cpu);
997 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1000 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1002 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1004 goto err_sq_wq_destroy;
1009 mlx5_wq_destroy(&sq->wq_ctrl);
1014 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1016 mlx5e_free_xdpsq_db(sq);
1017 mlx5_wq_destroy(&sq->wq_ctrl);
1020 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1022 kfree(sq->db.ico_wqe);
1025 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1027 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1029 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
1031 if (!sq->db.ico_wqe)
1037 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1038 struct mlx5e_sq_param *param,
1039 struct mlx5e_icosq *sq)
1041 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1042 struct mlx5_core_dev *mdev = c->mdev;
1046 sq->mkey_be = c->mkey_be;
1048 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1050 param->wq.db_numa_node = cpu_to_node(c->cpu);
1051 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1054 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1056 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1058 goto err_sq_wq_destroy;
1060 sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
1065 mlx5_wq_destroy(&sq->wq_ctrl);
1070 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1072 mlx5e_free_icosq_db(sq);
1073 mlx5_wq_destroy(&sq->wq_ctrl);
1076 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1078 kfree(sq->db.wqe_info);
1079 kfree(sq->db.dma_fifo);
1082 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1084 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1085 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1087 sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
1089 sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
1091 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1092 mlx5e_free_txqsq_db(sq);
1096 sq->dma_fifo_mask = df_sz - 1;
1101 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1103 struct mlx5e_params *params,
1104 struct mlx5e_sq_param *param,
1105 struct mlx5e_txqsq *sq)
1107 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1108 struct mlx5_core_dev *mdev = c->mdev;
1112 sq->tstamp = c->tstamp;
1113 sq->mkey_be = c->mkey_be;
1115 sq->txq_ix = txq_ix;
1116 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1117 sq->max_inline = params->tx_max_inline;
1118 sq->min_inline_mode = params->tx_min_inline_mode;
1119 if (MLX5_IPSEC_DEV(c->priv->mdev))
1120 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1122 param->wq.db_numa_node = cpu_to_node(c->cpu);
1123 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1126 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1128 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1130 goto err_sq_wq_destroy;
1132 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
1137 mlx5_wq_destroy(&sq->wq_ctrl);
1142 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1144 mlx5e_free_txqsq_db(sq);
1145 mlx5_wq_destroy(&sq->wq_ctrl);
1148 struct mlx5e_create_sq_param {
1149 struct mlx5_wq_ctrl *wq_ctrl;
1156 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1157 struct mlx5e_sq_param *param,
1158 struct mlx5e_create_sq_param *csp,
1167 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1168 sizeof(u64) * csp->wq_ctrl->buf.npages;
1169 in = kvzalloc(inlen, GFP_KERNEL);
1173 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1174 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1176 memcpy(sqc, param->sqc, sizeof(param->sqc));
1177 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1178 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1179 MLX5_SET(sqc, sqc, cqn, csp->cqn);
1181 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1182 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
1184 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1186 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1187 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
1188 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
1189 MLX5_ADAPTER_PAGE_SHIFT);
1190 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
1192 mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1194 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1201 struct mlx5e_modify_sq_param {
1208 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1209 struct mlx5e_modify_sq_param *p)
1216 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1217 in = kvzalloc(inlen, GFP_KERNEL);
1221 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1223 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1224 MLX5_SET(sqc, sqc, state, p->next_state);
1225 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1226 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1227 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1230 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1237 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1239 mlx5_core_destroy_sq(mdev, sqn);
1242 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1243 struct mlx5e_sq_param *param,
1244 struct mlx5e_create_sq_param *csp,
1247 struct mlx5e_modify_sq_param msp = {0};
1250 err = mlx5e_create_sq(mdev, param, csp, sqn);
1254 msp.curr_state = MLX5_SQC_STATE_RST;
1255 msp.next_state = MLX5_SQC_STATE_RDY;
1256 err = mlx5e_modify_sq(mdev, *sqn, &msp);
1258 mlx5e_destroy_sq(mdev, *sqn);
1263 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1264 struct mlx5e_txqsq *sq, u32 rate);
1266 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1269 struct mlx5e_params *params,
1270 struct mlx5e_sq_param *param,
1271 struct mlx5e_txqsq *sq)
1273 struct mlx5e_create_sq_param csp = {};
1277 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
1283 csp.cqn = sq->cq.mcq.cqn;
1284 csp.wq_ctrl = &sq->wq_ctrl;
1285 csp.min_inline_mode = sq->min_inline_mode;
1286 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1288 goto err_free_txqsq;
1290 tx_rate = c->priv->tx_rates[sq->txq_ix];
1292 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1297 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1298 mlx5e_free_txqsq(sq);
1303 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1305 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1306 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1307 netdev_tx_reset_queue(sq->txq);
1308 netif_tx_start_queue(sq->txq);
1311 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1313 __netif_tx_lock_bh(txq);
1314 netif_tx_stop_queue(txq);
1315 __netif_tx_unlock_bh(txq);
1318 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1320 struct mlx5e_channel *c = sq->channel;
1322 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1323 /* prevent netif_tx_wake_queue */
1324 napi_synchronize(&c->napi);
1326 netif_tx_disable_queue(sq->txq);
1328 /* last doorbell out, godspeed .. */
1329 if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1330 struct mlx5e_tx_wqe *nop;
1332 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
1333 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1334 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
1338 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1340 struct mlx5e_channel *c = sq->channel;
1341 struct mlx5_core_dev *mdev = c->mdev;
1343 mlx5e_destroy_sq(mdev, sq->sqn);
1345 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1346 mlx5e_free_txqsq_descs(sq);
1347 mlx5e_free_txqsq(sq);
1350 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1351 struct mlx5e_params *params,
1352 struct mlx5e_sq_param *param,
1353 struct mlx5e_icosq *sq)
1355 struct mlx5e_create_sq_param csp = {};
1358 err = mlx5e_alloc_icosq(c, param, sq);
1362 csp.cqn = sq->cq.mcq.cqn;
1363 csp.wq_ctrl = &sq->wq_ctrl;
1364 csp.min_inline_mode = params->tx_min_inline_mode;
1365 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1366 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1368 goto err_free_icosq;
1373 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1374 mlx5e_free_icosq(sq);
1379 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1381 struct mlx5e_channel *c = sq->channel;
1383 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1384 napi_synchronize(&c->napi);
1386 mlx5e_destroy_sq(c->mdev, sq->sqn);
1387 mlx5e_free_icosq(sq);
1390 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1391 struct mlx5e_params *params,
1392 struct mlx5e_sq_param *param,
1393 struct mlx5e_xdpsq *sq)
1395 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1396 struct mlx5e_create_sq_param csp = {};
1397 unsigned int inline_hdr_sz = 0;
1401 err = mlx5e_alloc_xdpsq(c, params, param, sq);
1406 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
1407 csp.cqn = sq->cq.mcq.cqn;
1408 csp.wq_ctrl = &sq->wq_ctrl;
1409 csp.min_inline_mode = sq->min_inline_mode;
1410 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1411 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1413 goto err_free_xdpsq;
1415 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1416 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1420 /* Pre initialize fixed WQE fields */
1421 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1422 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1423 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1424 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1425 struct mlx5_wqe_data_seg *dseg;
1427 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1428 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1430 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1431 dseg->lkey = sq->mkey_be;
1437 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1438 mlx5e_free_xdpsq(sq);
1443 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1445 struct mlx5e_channel *c = sq->channel;
1447 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1448 napi_synchronize(&c->napi);
1450 mlx5e_destroy_sq(c->mdev, sq->sqn);
1451 mlx5e_free_xdpsq_descs(sq);
1452 mlx5e_free_xdpsq(sq);
1455 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1456 struct mlx5e_cq_param *param,
1457 struct mlx5e_cq *cq)
1459 struct mlx5_core_cq *mcq = &cq->mcq;
1465 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1470 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1473 mcq->set_ci_db = cq->wq_ctrl.db.db;
1474 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1475 *mcq->set_ci_db = 0;
1477 mcq->vector = param->eq_ix;
1478 mcq->comp = mlx5e_completion_event;
1479 mcq->event = mlx5e_cq_error_event;
1482 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1483 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1493 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1494 struct mlx5e_cq_param *param,
1495 struct mlx5e_cq *cq)
1497 struct mlx5_core_dev *mdev = c->priv->mdev;
1500 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1501 param->wq.db_numa_node = cpu_to_node(c->cpu);
1502 param->eq_ix = c->ix;
1504 err = mlx5e_alloc_cq_common(mdev, param, cq);
1506 cq->napi = &c->napi;
1512 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1514 mlx5_cqwq_destroy(&cq->wq_ctrl);
1517 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1519 struct mlx5_core_dev *mdev = cq->mdev;
1520 struct mlx5_core_cq *mcq = &cq->mcq;
1525 unsigned int irqn_not_used;
1529 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1530 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1531 in = kvzalloc(inlen, GFP_KERNEL);
1535 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1537 memcpy(cqc, param->cqc, sizeof(param->cqc));
1539 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1540 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1542 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1544 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
1545 MLX5_SET(cqc, cqc, c_eqn, eqn);
1546 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1547 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
1548 MLX5_ADAPTER_PAGE_SHIFT);
1549 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1551 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1563 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1565 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1568 static int mlx5e_open_cq(struct mlx5e_channel *c,
1569 struct mlx5e_cq_moder moder,
1570 struct mlx5e_cq_param *param,
1571 struct mlx5e_cq *cq)
1573 struct mlx5_core_dev *mdev = c->mdev;
1576 err = mlx5e_alloc_cq(c, param, cq);
1580 err = mlx5e_create_cq(cq, param);
1584 if (MLX5_CAP_GEN(mdev, cq_moderation))
1585 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1594 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1596 mlx5e_destroy_cq(cq);
1600 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1602 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1605 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1606 struct mlx5e_params *params,
1607 struct mlx5e_channel_param *cparam)
1612 for (tc = 0; tc < c->num_tc; tc++) {
1613 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1614 &cparam->tx_cq, &c->sq[tc].cq);
1616 goto err_close_tx_cqs;
1622 for (tc--; tc >= 0; tc--)
1623 mlx5e_close_cq(&c->sq[tc].cq);
1628 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1632 for (tc = 0; tc < c->num_tc; tc++)
1633 mlx5e_close_cq(&c->sq[tc].cq);
1636 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1637 struct mlx5e_params *params,
1638 struct mlx5e_channel_param *cparam)
1643 for (tc = 0; tc < params->num_tc; tc++) {
1644 int txq_ix = c->ix + tc * params->num_channels;
1646 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1647 params, &cparam->sq, &c->sq[tc]);
1655 for (tc--; tc >= 0; tc--)
1656 mlx5e_close_txqsq(&c->sq[tc]);
1661 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1665 for (tc = 0; tc < c->num_tc; tc++)
1666 mlx5e_close_txqsq(&c->sq[tc]);
1669 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1670 struct mlx5e_txqsq *sq, u32 rate)
1672 struct mlx5e_priv *priv = netdev_priv(dev);
1673 struct mlx5_core_dev *mdev = priv->mdev;
1674 struct mlx5e_modify_sq_param msp = {0};
1678 if (rate == sq->rate_limit)
1683 /* remove current rl index to free space to next ones */
1684 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1689 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1691 netdev_err(dev, "Failed configuring rate %u: %d\n",
1697 msp.curr_state = MLX5_SQC_STATE_RDY;
1698 msp.next_state = MLX5_SQC_STATE_RDY;
1699 msp.rl_index = rl_index;
1700 msp.rl_update = true;
1701 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1703 netdev_err(dev, "Failed configuring rate %u: %d\n",
1705 /* remove the rate from the table */
1707 mlx5_rl_remove_rate(mdev, rate);
1711 sq->rate_limit = rate;
1715 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1717 struct mlx5e_priv *priv = netdev_priv(dev);
1718 struct mlx5_core_dev *mdev = priv->mdev;
1719 struct mlx5e_txqsq *sq = priv->txq2sq[index];
1722 if (!mlx5_rl_is_supported(mdev)) {
1723 netdev_err(dev, "Rate limiting is not supported on this device\n");
1727 /* rate is given in Mb/sec, HW config is in Kb/sec */
1730 /* Check whether rate in valid range, 0 is always valid */
1731 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1732 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1736 mutex_lock(&priv->state_lock);
1737 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1738 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1740 priv->tx_rates[index] = rate;
1741 mutex_unlock(&priv->state_lock);
1746 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1747 struct mlx5e_params *params,
1748 struct mlx5e_channel_param *cparam,
1749 struct mlx5e_channel **cp)
1751 struct mlx5e_cq_moder icocq_moder = {0, 0};
1752 struct net_device *netdev = priv->netdev;
1753 int cpu = mlx5e_get_cpu(priv, ix);
1754 struct mlx5e_channel *c;
1757 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1762 c->mdev = priv->mdev;
1763 c->tstamp = &priv->tstamp;
1766 c->pdev = &priv->mdev->pdev->dev;
1767 c->netdev = priv->netdev;
1768 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1769 c->num_tc = params->num_tc;
1770 c->xdp = !!params->xdp_prog;
1772 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1774 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1778 err = mlx5e_open_tx_cqs(c, params, cparam);
1780 goto err_close_icosq_cq;
1782 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1784 goto err_close_tx_cqs;
1786 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1787 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1788 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1790 goto err_close_rx_cq;
1792 napi_enable(&c->napi);
1794 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1796 goto err_disable_napi;
1798 err = mlx5e_open_sqs(c, params, cparam);
1800 goto err_close_icosq;
1802 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
1806 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1808 goto err_close_xdp_sq;
1815 mlx5e_close_xdpsq(&c->rq.xdpsq);
1821 mlx5e_close_icosq(&c->icosq);
1824 napi_disable(&c->napi);
1826 mlx5e_close_cq(&c->rq.xdpsq.cq);
1829 mlx5e_close_cq(&c->rq.cq);
1832 mlx5e_close_tx_cqs(c);
1835 mlx5e_close_cq(&c->icosq.cq);
1838 netif_napi_del(&c->napi);
1844 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1848 for (tc = 0; tc < c->num_tc; tc++)
1849 mlx5e_activate_txqsq(&c->sq[tc]);
1850 mlx5e_activate_rq(&c->rq);
1851 netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
1854 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1858 mlx5e_deactivate_rq(&c->rq);
1859 for (tc = 0; tc < c->num_tc; tc++)
1860 mlx5e_deactivate_txqsq(&c->sq[tc]);
1863 static void mlx5e_close_channel(struct mlx5e_channel *c)
1865 mlx5e_close_rq(&c->rq);
1867 mlx5e_close_xdpsq(&c->rq.xdpsq);
1869 mlx5e_close_icosq(&c->icosq);
1870 napi_disable(&c->napi);
1872 mlx5e_close_cq(&c->rq.xdpsq.cq);
1873 mlx5e_close_cq(&c->rq.cq);
1874 mlx5e_close_tx_cqs(c);
1875 mlx5e_close_cq(&c->icosq.cq);
1876 netif_napi_del(&c->napi);
1881 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1882 struct mlx5e_params *params,
1883 struct mlx5e_rq_param *param)
1885 void *rqc = param->rqc;
1886 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1888 switch (params->rq_wq_type) {
1889 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1890 MLX5_SET(wq, wq, log_wqe_num_of_strides, params->mpwqe_log_num_strides - 9);
1891 MLX5_SET(wq, wq, log_wqe_stride_size, params->mpwqe_log_stride_sz - 6);
1892 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1894 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1895 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1898 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1899 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1900 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_size);
1901 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1902 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1903 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
1904 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
1906 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1907 param->wq.linear = 1;
1910 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1912 void *rqc = param->rqc;
1913 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1915 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1916 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1919 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1920 struct mlx5e_sq_param *param)
1922 void *sqc = param->sqc;
1923 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1925 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1926 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1928 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1931 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1932 struct mlx5e_params *params,
1933 struct mlx5e_sq_param *param)
1935 void *sqc = param->sqc;
1936 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1938 mlx5e_build_sq_param_common(priv, param);
1939 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
1940 MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
1943 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1944 struct mlx5e_cq_param *param)
1946 void *cqc = param->cqc;
1948 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
1951 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1952 struct mlx5e_params *params,
1953 struct mlx5e_cq_param *param)
1955 void *cqc = param->cqc;
1958 switch (params->rq_wq_type) {
1959 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1960 log_cq_size = params->log_rq_size + params->mpwqe_log_num_strides;
1962 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1963 log_cq_size = params->log_rq_size;
1966 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1967 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
1968 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1969 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1972 mlx5e_build_common_cq_param(priv, param);
1975 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1976 struct mlx5e_params *params,
1977 struct mlx5e_cq_param *param)
1979 void *cqc = param->cqc;
1981 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
1983 mlx5e_build_common_cq_param(priv, param);
1985 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1988 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1990 struct mlx5e_cq_param *param)
1992 void *cqc = param->cqc;
1994 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1996 mlx5e_build_common_cq_param(priv, param);
1998 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2001 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2003 struct mlx5e_sq_param *param)
2005 void *sqc = param->sqc;
2006 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2008 mlx5e_build_sq_param_common(priv, param);
2010 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2011 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2014 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2015 struct mlx5e_params *params,
2016 struct mlx5e_sq_param *param)
2018 void *sqc = param->sqc;
2019 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2021 mlx5e_build_sq_param_common(priv, param);
2022 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2025 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2026 struct mlx5e_params *params,
2027 struct mlx5e_channel_param *cparam)
2029 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2031 mlx5e_build_rq_param(priv, params, &cparam->rq);
2032 mlx5e_build_sq_param(priv, params, &cparam->sq);
2033 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2034 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2035 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2036 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2037 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2040 int mlx5e_open_channels(struct mlx5e_priv *priv,
2041 struct mlx5e_channels *chs)
2043 struct mlx5e_channel_param *cparam;
2047 chs->num = chs->params.num_channels;
2049 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2050 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2051 if (!chs->c || !cparam)
2054 mlx5e_build_channel_param(priv, &chs->params, cparam);
2055 for (i = 0; i < chs->num; i++) {
2056 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2058 goto err_close_channels;
2065 for (i--; i >= 0; i--)
2066 mlx5e_close_channel(chs->c[i]);
2075 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2079 for (i = 0; i < chs->num; i++)
2080 mlx5e_activate_channel(chs->c[i]);
2083 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2088 for (i = 0; i < chs->num; i++) {
2089 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
2097 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2101 for (i = 0; i < chs->num; i++)
2102 mlx5e_deactivate_channel(chs->c[i]);
2105 void mlx5e_close_channels(struct mlx5e_channels *chs)
2109 for (i = 0; i < chs->num; i++)
2110 mlx5e_close_channel(chs->c[i]);
2117 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2119 struct mlx5_core_dev *mdev = priv->mdev;
2126 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2127 in = kvzalloc(inlen, GFP_KERNEL);
2131 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2133 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2134 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2136 for (i = 0; i < sz; i++)
2137 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2139 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2141 rqt->enabled = true;
2147 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2149 rqt->enabled = false;
2150 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2153 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2155 struct mlx5e_rqt *rqt = &priv->indir_rqt;
2158 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2160 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2164 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2166 struct mlx5e_rqt *rqt;
2170 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2171 rqt = &priv->direct_tir[ix].rqt;
2172 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2174 goto err_destroy_rqts;
2180 mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2181 for (ix--; ix >= 0; ix--)
2182 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2187 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2191 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2192 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2195 static int mlx5e_rx_hash_fn(int hfunc)
2197 return (hfunc == ETH_RSS_HASH_TOP) ?
2198 MLX5_RX_HASH_FN_TOEPLITZ :
2199 MLX5_RX_HASH_FN_INVERTED_XOR8;
2202 static int mlx5e_bits_invert(unsigned long a, int size)
2207 for (i = 0; i < size; i++)
2208 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2213 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2214 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2218 for (i = 0; i < sz; i++) {
2224 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2225 ix = mlx5e_bits_invert(i, ilog2(sz));
2227 ix = priv->channels.params.indirection_rqt[ix];
2228 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2232 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2236 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2237 struct mlx5e_redirect_rqt_param rrp)
2239 struct mlx5_core_dev *mdev = priv->mdev;
2245 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2246 in = kvzalloc(inlen, GFP_KERNEL);
2250 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2252 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2253 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2254 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2255 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2261 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2262 struct mlx5e_redirect_rqt_param rrp)
2267 if (ix >= rrp.rss.channels->num)
2268 return priv->drop_rq.rqn;
2270 return rrp.rss.channels->c[ix]->rq.rqn;
2273 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2274 struct mlx5e_redirect_rqt_param rrp)
2279 if (priv->indir_rqt.enabled) {
2281 rqtn = priv->indir_rqt.rqtn;
2282 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2285 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2286 struct mlx5e_redirect_rqt_param direct_rrp = {
2289 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2293 /* Direct RQ Tables */
2294 if (!priv->direct_tir[ix].rqt.enabled)
2297 rqtn = priv->direct_tir[ix].rqt.rqtn;
2298 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2302 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2303 struct mlx5e_channels *chs)
2305 struct mlx5e_redirect_rqt_param rrp = {
2310 .hfunc = chs->params.rss_hfunc,
2315 mlx5e_redirect_rqts(priv, rrp);
2318 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2320 struct mlx5e_redirect_rqt_param drop_rrp = {
2323 .rqn = priv->drop_rq.rqn,
2327 mlx5e_redirect_rqts(priv, drop_rrp);
2330 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2332 if (!params->lro_en)
2335 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2337 MLX5_SET(tirc, tirc, lro_enable_mask,
2338 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2339 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2340 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2341 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2342 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2345 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2346 enum mlx5e_traffic_types tt,
2349 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2351 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2352 MLX5_HASH_FIELD_SEL_DST_IP)
2354 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2355 MLX5_HASH_FIELD_SEL_DST_IP |\
2356 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2357 MLX5_HASH_FIELD_SEL_L4_DPORT)
2359 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2360 MLX5_HASH_FIELD_SEL_DST_IP |\
2361 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2363 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2364 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2365 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2366 rx_hash_toeplitz_key);
2367 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2368 rx_hash_toeplitz_key);
2370 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2371 memcpy(rss_key, params->toeplitz_hash_key, len);
2375 case MLX5E_TT_IPV4_TCP:
2376 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2377 MLX5_L3_PROT_TYPE_IPV4);
2378 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2379 MLX5_L4_PROT_TYPE_TCP);
2380 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2381 MLX5_HASH_IP_L4PORTS);
2384 case MLX5E_TT_IPV6_TCP:
2385 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2386 MLX5_L3_PROT_TYPE_IPV6);
2387 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2388 MLX5_L4_PROT_TYPE_TCP);
2389 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2390 MLX5_HASH_IP_L4PORTS);
2393 case MLX5E_TT_IPV4_UDP:
2394 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2395 MLX5_L3_PROT_TYPE_IPV4);
2396 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2397 MLX5_L4_PROT_TYPE_UDP);
2398 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2399 MLX5_HASH_IP_L4PORTS);
2402 case MLX5E_TT_IPV6_UDP:
2403 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2404 MLX5_L3_PROT_TYPE_IPV6);
2405 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2406 MLX5_L4_PROT_TYPE_UDP);
2407 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2408 MLX5_HASH_IP_L4PORTS);
2411 case MLX5E_TT_IPV4_IPSEC_AH:
2412 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2413 MLX5_L3_PROT_TYPE_IPV4);
2414 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2415 MLX5_HASH_IP_IPSEC_SPI);
2418 case MLX5E_TT_IPV6_IPSEC_AH:
2419 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2420 MLX5_L3_PROT_TYPE_IPV6);
2421 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2422 MLX5_HASH_IP_IPSEC_SPI);
2425 case MLX5E_TT_IPV4_IPSEC_ESP:
2426 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2427 MLX5_L3_PROT_TYPE_IPV4);
2428 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2429 MLX5_HASH_IP_IPSEC_SPI);
2432 case MLX5E_TT_IPV6_IPSEC_ESP:
2433 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2434 MLX5_L3_PROT_TYPE_IPV6);
2435 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2436 MLX5_HASH_IP_IPSEC_SPI);
2440 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2441 MLX5_L3_PROT_TYPE_IPV4);
2442 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2447 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2448 MLX5_L3_PROT_TYPE_IPV6);
2449 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2453 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2457 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2459 struct mlx5_core_dev *mdev = priv->mdev;
2468 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2469 in = kvzalloc(inlen, GFP_KERNEL);
2473 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2474 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2476 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2478 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2479 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2485 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2486 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2498 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
2500 struct mlx5_core_dev *mdev = priv->mdev;
2501 u16 hw_mtu = MLX5E_SW2HW_MTU(priv, mtu);
2504 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2508 /* Update vport context MTU */
2509 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2513 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2515 struct mlx5_core_dev *mdev = priv->mdev;
2519 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2520 if (err || !hw_mtu) /* fallback to port oper mtu */
2521 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2523 *mtu = MLX5E_HW2SW_MTU(priv, hw_mtu);
2526 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2528 struct net_device *netdev = priv->netdev;
2532 err = mlx5e_set_mtu(priv, netdev->mtu);
2536 mlx5e_query_mtu(priv, &mtu);
2537 if (mtu != netdev->mtu)
2538 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2539 __func__, mtu, netdev->mtu);
2545 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2547 struct mlx5e_priv *priv = netdev_priv(netdev);
2548 int nch = priv->channels.params.num_channels;
2549 int ntc = priv->channels.params.num_tc;
2552 netdev_reset_tc(netdev);
2557 netdev_set_num_tc(netdev, ntc);
2559 /* Map netdev TCs to offset 0
2560 * We have our own UP to TXQ mapping for QoS
2562 for (tc = 0; tc < ntc; tc++)
2563 netdev_set_tc_queue(netdev, tc, nch, 0);
2566 static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2568 struct mlx5e_channel *c;
2569 struct mlx5e_txqsq *sq;
2572 for (i = 0; i < priv->channels.num; i++)
2573 for (tc = 0; tc < priv->profile->max_tc; tc++)
2574 priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2576 for (i = 0; i < priv->channels.num; i++) {
2577 c = priv->channels.c[i];
2578 for (tc = 0; tc < c->num_tc; tc++) {
2580 priv->txq2sq[sq->txq_ix] = sq;
2585 static bool mlx5e_is_eswitch_vport_mngr(struct mlx5_core_dev *mdev)
2587 return (MLX5_CAP_GEN(mdev, vport_group_manager) &&
2588 MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH);
2591 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2593 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2594 struct net_device *netdev = priv->netdev;
2596 mlx5e_netdev_set_tcs(netdev);
2597 netif_set_real_num_tx_queues(netdev, num_txqs);
2598 netif_set_real_num_rx_queues(netdev, priv->channels.num);
2600 mlx5e_build_channels_tx_maps(priv);
2601 mlx5e_activate_channels(&priv->channels);
2602 netif_tx_start_all_queues(priv->netdev);
2604 if (mlx5e_is_eswitch_vport_mngr(priv->mdev))
2605 mlx5e_add_sqs_fwd_rules(priv);
2607 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2608 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2611 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2613 mlx5e_redirect_rqts_to_drop(priv);
2615 if (mlx5e_is_eswitch_vport_mngr(priv->mdev))
2616 mlx5e_remove_sqs_fwd_rules(priv);
2618 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2619 * polling for inactive tx queues.
2621 netif_tx_stop_all_queues(priv->netdev);
2622 netif_tx_disable(priv->netdev);
2623 mlx5e_deactivate_channels(&priv->channels);
2626 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2627 struct mlx5e_channels *new_chs,
2628 mlx5e_fp_hw_modify hw_modify)
2630 struct net_device *netdev = priv->netdev;
2633 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2635 carrier_ok = netif_carrier_ok(netdev);
2636 netif_carrier_off(netdev);
2638 if (new_num_txqs < netdev->real_num_tx_queues)
2639 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2641 mlx5e_deactivate_priv_channels(priv);
2642 mlx5e_close_channels(&priv->channels);
2644 priv->channels = *new_chs;
2646 /* New channels are ready to roll, modify HW settings if needed */
2650 mlx5e_refresh_tirs(priv, false);
2651 mlx5e_activate_priv_channels(priv);
2653 /* return carrier back if needed */
2655 netif_carrier_on(netdev);
2658 int mlx5e_open_locked(struct net_device *netdev)
2660 struct mlx5e_priv *priv = netdev_priv(netdev);
2663 set_bit(MLX5E_STATE_OPENED, &priv->state);
2665 err = mlx5e_open_channels(priv, &priv->channels);
2667 goto err_clear_state_opened_flag;
2669 mlx5e_refresh_tirs(priv, false);
2670 mlx5e_activate_priv_channels(priv);
2671 if (priv->profile->update_carrier)
2672 priv->profile->update_carrier(priv);
2673 mlx5e_timestamp_init(priv);
2675 if (priv->profile->update_stats)
2676 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2680 err_clear_state_opened_flag:
2681 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2685 int mlx5e_open(struct net_device *netdev)
2687 struct mlx5e_priv *priv = netdev_priv(netdev);
2690 mutex_lock(&priv->state_lock);
2691 err = mlx5e_open_locked(netdev);
2692 mutex_unlock(&priv->state_lock);
2697 int mlx5e_close_locked(struct net_device *netdev)
2699 struct mlx5e_priv *priv = netdev_priv(netdev);
2701 /* May already be CLOSED in case a previous configuration operation
2702 * (e.g RX/TX queue size change) that involves close&open failed.
2704 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2707 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2709 mlx5e_timestamp_cleanup(priv);
2710 netif_carrier_off(priv->netdev);
2711 mlx5e_deactivate_priv_channels(priv);
2712 mlx5e_close_channels(&priv->channels);
2717 int mlx5e_close(struct net_device *netdev)
2719 struct mlx5e_priv *priv = netdev_priv(netdev);
2722 if (!netif_device_present(netdev))
2725 mutex_lock(&priv->state_lock);
2726 err = mlx5e_close_locked(netdev);
2727 mutex_unlock(&priv->state_lock);
2732 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2733 struct mlx5e_rq *rq,
2734 struct mlx5e_rq_param *param)
2736 void *rqc = param->rqc;
2737 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2740 param->wq.db_numa_node = param->wq.buf_numa_node;
2742 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
2752 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
2753 struct mlx5e_cq *cq,
2754 struct mlx5e_cq_param *param)
2756 return mlx5e_alloc_cq_common(mdev, param, cq);
2759 static int mlx5e_open_drop_rq(struct mlx5_core_dev *mdev,
2760 struct mlx5e_rq *drop_rq)
2762 struct mlx5e_cq_param cq_param = {};
2763 struct mlx5e_rq_param rq_param = {};
2764 struct mlx5e_cq *cq = &drop_rq->cq;
2767 mlx5e_build_drop_rq_param(&rq_param);
2769 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
2773 err = mlx5e_create_cq(cq, &cq_param);
2777 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
2779 goto err_destroy_cq;
2781 err = mlx5e_create_rq(drop_rq, &rq_param);
2788 mlx5e_free_rq(drop_rq);
2791 mlx5e_destroy_cq(cq);
2799 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
2801 mlx5e_destroy_rq(drop_rq);
2802 mlx5e_free_rq(drop_rq);
2803 mlx5e_destroy_cq(&drop_rq->cq);
2804 mlx5e_free_cq(&drop_rq->cq);
2807 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2808 u32 underlay_qpn, u32 *tisn)
2810 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2811 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2813 MLX5_SET(tisc, tisc, prio, tc << 1);
2814 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
2815 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2817 if (mlx5_lag_is_lacp_owner(mdev))
2818 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2820 return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
2823 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
2825 mlx5_core_destroy_tis(mdev, tisn);
2828 int mlx5e_create_tises(struct mlx5e_priv *priv)
2833 for (tc = 0; tc < priv->profile->max_tc; tc++) {
2834 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
2836 goto err_close_tises;
2842 for (tc--; tc >= 0; tc--)
2843 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2848 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2852 for (tc = 0; tc < priv->profile->max_tc; tc++)
2853 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2856 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2857 enum mlx5e_traffic_types tt,
2860 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2862 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2864 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2865 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2866 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc);
2869 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
2871 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2873 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2875 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2876 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2877 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2880 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2882 struct mlx5e_tir *tir;
2889 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2890 in = kvzalloc(inlen, GFP_KERNEL);
2894 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2895 memset(in, 0, inlen);
2896 tir = &priv->indir_tir[tt];
2897 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2898 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
2899 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2901 goto err_destroy_tirs;
2909 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
2910 for (tt--; tt >= 0; tt--)
2911 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2918 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2920 int nch = priv->profile->max_nch(priv->mdev);
2921 struct mlx5e_tir *tir;
2928 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2929 in = kvzalloc(inlen, GFP_KERNEL);
2933 for (ix = 0; ix < nch; ix++) {
2934 memset(in, 0, inlen);
2935 tir = &priv->direct_tir[ix];
2936 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2937 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
2938 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2940 goto err_destroy_ch_tirs;
2947 err_destroy_ch_tirs:
2948 mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
2949 for (ix--; ix >= 0; ix--)
2950 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2957 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2961 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2962 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2965 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2967 int nch = priv->profile->max_nch(priv->mdev);
2970 for (i = 0; i < nch; i++)
2971 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2974 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
2979 for (i = 0; i < chs->num; i++) {
2980 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
2988 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
2993 for (i = 0; i < chs->num; i++) {
2994 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3002 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
3004 struct mlx5e_priv *priv = netdev_priv(netdev);
3005 struct mlx5e_channels new_channels = {};
3008 if (tc && tc != MLX5E_MAX_NUM_TC)
3011 mutex_lock(&priv->state_lock);
3013 new_channels.params = priv->channels.params;
3014 new_channels.params.num_tc = tc ? tc : 1;
3016 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3017 priv->channels.params = new_channels.params;
3021 err = mlx5e_open_channels(priv, &new_channels);
3025 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
3027 mutex_unlock(&priv->state_lock);
3031 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
3032 u32 chain_index, __be16 proto,
3033 struct tc_to_netdev *tc)
3035 struct mlx5e_priv *priv = netdev_priv(dev);
3037 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
3044 case TC_SETUP_CLSFLOWER:
3045 switch (tc->cls_flower->command) {
3046 case TC_CLSFLOWER_REPLACE:
3047 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
3048 case TC_CLSFLOWER_DESTROY:
3049 return mlx5e_delete_flower(priv, tc->cls_flower);
3050 case TC_CLSFLOWER_STATS:
3051 return mlx5e_stats_flower(priv, tc->cls_flower);
3058 if (tc->type != TC_SETUP_MQPRIO)
3061 tc->mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3063 return mlx5e_setup_tc(dev, tc->mqprio->num_tc);
3067 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3069 struct mlx5e_priv *priv = netdev_priv(dev);
3070 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
3071 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3072 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3074 if (mlx5e_is_uplink_rep(priv)) {
3075 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3076 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3077 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3078 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3080 stats->rx_packets = sstats->rx_packets;
3081 stats->rx_bytes = sstats->rx_bytes;
3082 stats->tx_packets = sstats->tx_packets;
3083 stats->tx_bytes = sstats->tx_bytes;
3084 stats->tx_dropped = sstats->tx_queue_dropped;
3087 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3089 stats->rx_length_errors =
3090 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3091 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3092 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3093 stats->rx_crc_errors =
3094 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3095 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3096 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3097 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3098 stats->rx_frame_errors;
3099 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3101 /* vport multicast also counts packets that are dropped due to steering
3102 * or rx out of buffer
3105 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3108 static void mlx5e_set_rx_mode(struct net_device *dev)
3110 struct mlx5e_priv *priv = netdev_priv(dev);
3112 queue_work(priv->wq, &priv->set_rx_mode_work);
3115 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3117 struct mlx5e_priv *priv = netdev_priv(netdev);
3118 struct sockaddr *saddr = addr;
3120 if (!is_valid_ether_addr(saddr->sa_data))
3121 return -EADDRNOTAVAIL;
3123 netif_addr_lock_bh(netdev);
3124 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3125 netif_addr_unlock_bh(netdev);
3127 queue_work(priv->wq, &priv->set_rx_mode_work);
3132 #define MLX5E_SET_FEATURE(netdev, feature, enable) \
3135 netdev->features |= feature; \
3137 netdev->features &= ~feature; \
3140 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3142 static int set_feature_lro(struct net_device *netdev, bool enable)
3144 struct mlx5e_priv *priv = netdev_priv(netdev);
3145 struct mlx5e_channels new_channels = {};
3149 mutex_lock(&priv->state_lock);
3151 reset = (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST);
3152 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3154 new_channels.params = priv->channels.params;
3155 new_channels.params.lro_en = enable;
3158 priv->channels.params = new_channels.params;
3159 err = mlx5e_modify_tirs_lro(priv);
3163 err = mlx5e_open_channels(priv, &new_channels);
3167 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3169 mutex_unlock(&priv->state_lock);
3173 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
3175 struct mlx5e_priv *priv = netdev_priv(netdev);
3178 mlx5e_enable_vlan_filter(priv);
3180 mlx5e_disable_vlan_filter(priv);
3185 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3187 struct mlx5e_priv *priv = netdev_priv(netdev);
3189 if (!enable && mlx5e_tc_num_filters(priv)) {
3191 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3198 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3200 struct mlx5e_priv *priv = netdev_priv(netdev);
3201 struct mlx5_core_dev *mdev = priv->mdev;
3203 return mlx5_set_port_fcs(mdev, !enable);
3206 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3208 struct mlx5e_priv *priv = netdev_priv(netdev);
3211 mutex_lock(&priv->state_lock);
3213 priv->channels.params.scatter_fcs_en = enable;
3214 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3216 priv->channels.params.scatter_fcs_en = !enable;
3218 mutex_unlock(&priv->state_lock);
3223 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3225 struct mlx5e_priv *priv = netdev_priv(netdev);
3228 mutex_lock(&priv->state_lock);
3230 priv->channels.params.vlan_strip_disable = !enable;
3231 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3234 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3236 priv->channels.params.vlan_strip_disable = enable;
3239 mutex_unlock(&priv->state_lock);
3244 #ifdef CONFIG_RFS_ACCEL
3245 static int set_feature_arfs(struct net_device *netdev, bool enable)
3247 struct mlx5e_priv *priv = netdev_priv(netdev);
3251 err = mlx5e_arfs_enable(priv);
3253 err = mlx5e_arfs_disable(priv);
3259 static int mlx5e_handle_feature(struct net_device *netdev,
3260 netdev_features_t wanted_features,
3261 netdev_features_t feature,
3262 mlx5e_feature_handler feature_handler)
3264 netdev_features_t changes = wanted_features ^ netdev->features;
3265 bool enable = !!(wanted_features & feature);
3268 if (!(changes & feature))
3271 err = feature_handler(netdev, enable);
3273 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
3274 enable ? "Enable" : "Disable", feature, err);
3278 MLX5E_SET_FEATURE(netdev, feature, enable);
3282 static int mlx5e_set_features(struct net_device *netdev,
3283 netdev_features_t features)
3287 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
3289 err |= mlx5e_handle_feature(netdev, features,
3290 NETIF_F_HW_VLAN_CTAG_FILTER,
3291 set_feature_vlan_filter);
3292 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
3293 set_feature_tc_num_filters);
3294 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
3295 set_feature_rx_all);
3296 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXFCS,
3297 set_feature_rx_fcs);
3298 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
3299 set_feature_rx_vlan);
3300 #ifdef CONFIG_RFS_ACCEL
3301 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
3305 return err ? -EINVAL : 0;
3308 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
3310 struct mlx5e_priv *priv = netdev_priv(netdev);
3311 struct mlx5e_channels new_channels = {};
3316 mutex_lock(&priv->state_lock);
3318 reset = !priv->channels.params.lro_en &&
3319 (priv->channels.params.rq_wq_type !=
3320 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
3322 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3324 curr_mtu = netdev->mtu;
3325 netdev->mtu = new_mtu;
3328 mlx5e_set_dev_port_mtu(priv);
3332 new_channels.params = priv->channels.params;
3333 err = mlx5e_open_channels(priv, &new_channels);
3335 netdev->mtu = curr_mtu;
3339 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu);
3342 mutex_unlock(&priv->state_lock);
3346 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3348 struct mlx5e_priv *priv = netdev_priv(dev);
3352 return mlx5e_hwstamp_set(priv, ifr);
3354 return mlx5e_hwstamp_get(priv, ifr);
3360 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3362 struct mlx5e_priv *priv = netdev_priv(dev);
3363 struct mlx5_core_dev *mdev = priv->mdev;
3365 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3368 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3371 struct mlx5e_priv *priv = netdev_priv(dev);
3372 struct mlx5_core_dev *mdev = priv->mdev;
3374 if (vlan_proto != htons(ETH_P_8021Q))
3375 return -EPROTONOSUPPORT;
3377 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3381 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3383 struct mlx5e_priv *priv = netdev_priv(dev);
3384 struct mlx5_core_dev *mdev = priv->mdev;
3386 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3389 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3391 struct mlx5e_priv *priv = netdev_priv(dev);
3392 struct mlx5_core_dev *mdev = priv->mdev;
3394 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3397 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3400 struct mlx5e_priv *priv = netdev_priv(dev);
3401 struct mlx5_core_dev *mdev = priv->mdev;
3403 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3404 max_tx_rate, min_tx_rate);
3407 static int mlx5_vport_link2ifla(u8 esw_link)
3410 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3411 return IFLA_VF_LINK_STATE_DISABLE;
3412 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3413 return IFLA_VF_LINK_STATE_ENABLE;
3415 return IFLA_VF_LINK_STATE_AUTO;
3418 static int mlx5_ifla_link2vport(u8 ifla_link)
3420 switch (ifla_link) {
3421 case IFLA_VF_LINK_STATE_DISABLE:
3422 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3423 case IFLA_VF_LINK_STATE_ENABLE:
3424 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3426 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3429 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3432 struct mlx5e_priv *priv = netdev_priv(dev);
3433 struct mlx5_core_dev *mdev = priv->mdev;
3435 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3436 mlx5_ifla_link2vport(link_state));
3439 static int mlx5e_get_vf_config(struct net_device *dev,
3440 int vf, struct ifla_vf_info *ivi)
3442 struct mlx5e_priv *priv = netdev_priv(dev);
3443 struct mlx5_core_dev *mdev = priv->mdev;
3446 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3449 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3453 static int mlx5e_get_vf_stats(struct net_device *dev,
3454 int vf, struct ifla_vf_stats *vf_stats)
3456 struct mlx5e_priv *priv = netdev_priv(dev);
3457 struct mlx5_core_dev *mdev = priv->mdev;
3459 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3463 static void mlx5e_add_vxlan_port(struct net_device *netdev,
3464 struct udp_tunnel_info *ti)
3466 struct mlx5e_priv *priv = netdev_priv(netdev);
3468 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3471 if (!mlx5e_vxlan_allowed(priv->mdev))
3474 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3477 static void mlx5e_del_vxlan_port(struct net_device *netdev,
3478 struct udp_tunnel_info *ti)
3480 struct mlx5e_priv *priv = netdev_priv(netdev);
3482 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3485 if (!mlx5e_vxlan_allowed(priv->mdev))
3488 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3491 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3492 struct sk_buff *skb,
3493 netdev_features_t features)
3495 struct udphdr *udph;
3499 switch (vlan_get_protocol(skb)) {
3500 case htons(ETH_P_IP):
3501 proto = ip_hdr(skb)->protocol;
3503 case htons(ETH_P_IPV6):
3504 proto = ipv6_hdr(skb)->nexthdr;
3510 if (proto == IPPROTO_UDP) {
3511 udph = udp_hdr(skb);
3512 port = be16_to_cpu(udph->dest);
3515 /* Verify if UDP port is being offloaded by HW */
3516 if (port && mlx5e_vxlan_lookup_port(priv, port))
3520 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3521 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3524 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3525 struct net_device *netdev,
3526 netdev_features_t features)
3528 struct mlx5e_priv *priv = netdev_priv(netdev);
3530 features = vlan_features_check(skb, features);
3531 features = vxlan_features_check(skb, features);
3533 #ifdef CONFIG_MLX5_EN_IPSEC
3534 if (mlx5e_ipsec_feature_check(skb, netdev, features))
3538 /* Validate if the tunneled packet is being offloaded by HW */
3539 if (skb->encapsulation &&
3540 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3541 return mlx5e_vxlan_features_check(priv, skb, features);
3546 static void mlx5e_tx_timeout(struct net_device *dev)
3548 struct mlx5e_priv *priv = netdev_priv(dev);
3549 bool sched_work = false;
3552 netdev_err(dev, "TX timeout detected\n");
3554 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
3555 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3557 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3560 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3561 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3562 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3565 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3566 schedule_work(&priv->tx_timeout_work);
3569 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3571 struct mlx5e_priv *priv = netdev_priv(netdev);
3572 struct bpf_prog *old_prog;
3574 bool reset, was_opened;
3577 mutex_lock(&priv->state_lock);
3579 if ((netdev->features & NETIF_F_LRO) && prog) {
3580 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3585 if ((netdev->features & NETIF_F_HW_ESP) && prog) {
3586 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
3591 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3592 /* no need for full reset when exchanging programs */
3593 reset = (!priv->channels.params.xdp_prog || !prog);
3595 if (was_opened && reset)
3596 mlx5e_close_locked(netdev);
3597 if (was_opened && !reset) {
3598 /* num_channels is invariant here, so we can take the
3599 * batched reference right upfront.
3601 prog = bpf_prog_add(prog, priv->channels.num);
3603 err = PTR_ERR(prog);
3608 /* exchange programs, extra prog reference we got from caller
3609 * as long as we don't fail from this point onwards.
3611 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
3613 bpf_prog_put(old_prog);
3615 if (reset) /* change RQ type according to priv->xdp_prog */
3616 mlx5e_set_rq_params(priv->mdev, &priv->channels.params);
3618 if (was_opened && reset)
3619 mlx5e_open_locked(netdev);
3621 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3624 /* exchanging programs w/o reset, we update ref counts on behalf
3625 * of the channels RQs here.
3627 for (i = 0; i < priv->channels.num; i++) {
3628 struct mlx5e_channel *c = priv->channels.c[i];
3630 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3631 napi_synchronize(&c->napi);
3632 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3634 old_prog = xchg(&c->rq.xdp_prog, prog);
3636 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3637 /* napi_schedule in case we have missed anything */
3638 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3639 napi_schedule(&c->napi);
3642 bpf_prog_put(old_prog);
3646 mutex_unlock(&priv->state_lock);
3650 static u32 mlx5e_xdp_query(struct net_device *dev)
3652 struct mlx5e_priv *priv = netdev_priv(dev);
3653 const struct bpf_prog *xdp_prog;
3656 mutex_lock(&priv->state_lock);
3657 xdp_prog = priv->channels.params.xdp_prog;
3659 prog_id = xdp_prog->aux->id;
3660 mutex_unlock(&priv->state_lock);
3665 static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3667 switch (xdp->command) {
3668 case XDP_SETUP_PROG:
3669 return mlx5e_xdp_set(dev, xdp->prog);
3670 case XDP_QUERY_PROG:
3671 xdp->prog_id = mlx5e_xdp_query(dev);
3672 xdp->prog_attached = !!xdp->prog_id;
3679 #ifdef CONFIG_NET_POLL_CONTROLLER
3680 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3681 * reenabling interrupts.
3683 static void mlx5e_netpoll(struct net_device *dev)
3685 struct mlx5e_priv *priv = netdev_priv(dev);
3686 struct mlx5e_channels *chs = &priv->channels;
3690 for (i = 0; i < chs->num; i++)
3691 napi_schedule(&chs->c[i]->napi);
3695 static const struct net_device_ops mlx5e_netdev_ops_basic = {
3696 .ndo_open = mlx5e_open,
3697 .ndo_stop = mlx5e_close,
3698 .ndo_start_xmit = mlx5e_xmit,
3699 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3700 .ndo_select_queue = mlx5e_select_queue,
3701 .ndo_get_stats64 = mlx5e_get_stats,
3702 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3703 .ndo_set_mac_address = mlx5e_set_mac,
3704 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3705 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3706 .ndo_set_features = mlx5e_set_features,
3707 .ndo_change_mtu = mlx5e_change_mtu,
3708 .ndo_do_ioctl = mlx5e_ioctl,
3709 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
3710 #ifdef CONFIG_RFS_ACCEL
3711 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3713 .ndo_tx_timeout = mlx5e_tx_timeout,
3714 .ndo_xdp = mlx5e_xdp,
3715 #ifdef CONFIG_NET_POLL_CONTROLLER
3716 .ndo_poll_controller = mlx5e_netpoll,
3720 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3721 .ndo_open = mlx5e_open,
3722 .ndo_stop = mlx5e_close,
3723 .ndo_start_xmit = mlx5e_xmit,
3724 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3725 .ndo_select_queue = mlx5e_select_queue,
3726 .ndo_get_stats64 = mlx5e_get_stats,
3727 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3728 .ndo_set_mac_address = mlx5e_set_mac,
3729 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3730 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3731 .ndo_set_features = mlx5e_set_features,
3732 .ndo_change_mtu = mlx5e_change_mtu,
3733 .ndo_do_ioctl = mlx5e_ioctl,
3734 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3735 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
3736 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
3737 .ndo_features_check = mlx5e_features_check,
3738 #ifdef CONFIG_RFS_ACCEL
3739 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3741 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3742 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
3743 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
3744 .ndo_set_vf_trust = mlx5e_set_vf_trust,
3745 .ndo_set_vf_rate = mlx5e_set_vf_rate,
3746 .ndo_get_vf_config = mlx5e_get_vf_config,
3747 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3748 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3749 .ndo_tx_timeout = mlx5e_tx_timeout,
3750 .ndo_xdp = mlx5e_xdp,
3751 #ifdef CONFIG_NET_POLL_CONTROLLER
3752 .ndo_poll_controller = mlx5e_netpoll,
3754 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3755 .ndo_get_offload_stats = mlx5e_get_offload_stats,
3758 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3760 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3762 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3763 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3764 !MLX5_CAP_ETH(mdev, csum_cap) ||
3765 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3766 !MLX5_CAP_ETH(mdev, vlan_cap) ||
3767 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3768 MLX5_CAP_FLOWTABLE(mdev,
3769 flow_table_properties_nic_receive.max_ft_level)
3771 mlx5_core_warn(mdev,
3772 "Not creating net device, some required device capabilities are missing\n");
3775 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3776 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
3777 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3778 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
3783 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3785 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3787 return bf_buf_size -
3788 sizeof(struct mlx5e_tx_wqe) +
3789 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3792 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3793 u32 *indirection_rqt, int len,
3796 int node = mdev->priv.numa_node;
3797 int node_num_of_cores;
3801 node = first_online_node;
3803 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3805 if (node_num_of_cores)
3806 num_channels = min_t(int, num_channels, node_num_of_cores);
3808 for (i = 0; i < len; i++)
3809 indirection_rqt[i] = i % num_channels;
3812 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3814 enum pcie_link_width width;
3815 enum pci_bus_speed speed;
3818 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3822 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3826 case PCIE_SPEED_2_5GT:
3827 *pci_bw = 2500 * width;
3829 case PCIE_SPEED_5_0GT:
3830 *pci_bw = 5000 * width;
3832 case PCIE_SPEED_8_0GT:
3833 *pci_bw = 8000 * width;
3842 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3844 return (link_speed && pci_bw &&
3845 (pci_bw < 40000) && (pci_bw < link_speed));
3848 static bool hw_lro_heuristic(u32 link_speed, u32 pci_bw)
3850 return !(link_speed && pci_bw &&
3851 (pci_bw <= 16000) && (pci_bw < link_speed));
3854 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3856 params->rx_cq_period_mode = cq_period_mode;
3858 params->rx_cq_moderation.pkts =
3859 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3860 params->rx_cq_moderation.usec =
3861 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3863 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3864 params->rx_cq_moderation.usec =
3865 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3867 if (params->rx_am_enabled)
3868 params->rx_cq_moderation =
3869 mlx5e_am_get_def_profile(params->rx_cq_period_mode);
3871 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3872 params->rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3875 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3879 /* The supported periods are organized in ascending order */
3880 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3881 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3884 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3887 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
3888 struct mlx5e_params *params,
3891 u8 cq_period_mode = 0;
3895 params->num_channels = max_channels;
3898 mlx5e_get_max_linkspeed(mdev, &link_speed);
3899 mlx5e_get_pci_bw(mdev, &pci_bw);
3900 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3901 link_speed, pci_bw);
3904 params->log_sq_size = is_kdump_kernel() ?
3905 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
3906 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3908 /* set CQE compression */
3909 params->rx_cqe_compress_def = false;
3910 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3911 MLX5_CAP_GEN(mdev, vport_group_manager))
3912 params->rx_cqe_compress_def = cqe_compress_heuristic(link_speed, pci_bw);
3914 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
3917 mlx5e_set_rq_params(mdev, params);
3921 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
3922 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
3923 params->lro_en = hw_lro_heuristic(link_speed, pci_bw);
3924 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
3926 /* CQ moderation params */
3927 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3928 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3929 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3930 params->rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3931 mlx5e_set_rx_cq_mode_params(params, cq_period_mode);
3933 params->tx_cq_moderation.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3934 params->tx_cq_moderation.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3937 params->tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3938 mlx5_query_min_inline(mdev, ¶ms->tx_min_inline_mode);
3939 if (params->tx_min_inline_mode == MLX5_INLINE_MODE_NONE &&
3940 !MLX5_CAP_ETH(mdev, wqe_vlan_insert))
3941 params->tx_min_inline_mode = MLX5_INLINE_MODE_L2;
3944 params->rss_hfunc = ETH_RSS_HASH_XOR;
3945 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
3946 mlx5e_build_default_indir_rqt(mdev, params->indirection_rqt,
3947 MLX5E_INDIR_RQT_SIZE, max_channels);
3950 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3951 struct net_device *netdev,
3952 const struct mlx5e_profile *profile,
3955 struct mlx5e_priv *priv = netdev_priv(netdev);
3958 priv->netdev = netdev;
3959 priv->profile = profile;
3960 priv->ppriv = ppriv;
3961 priv->hard_mtu = MLX5E_ETH_HARD_MTU;
3963 mlx5e_build_nic_params(mdev, &priv->channels.params, profile->max_nch(mdev));
3965 mutex_init(&priv->state_lock);
3967 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3968 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3969 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
3970 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3973 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3975 struct mlx5e_priv *priv = netdev_priv(netdev);
3977 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
3978 if (is_zero_ether_addr(netdev->dev_addr) &&
3979 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3980 eth_hw_addr_random(netdev);
3981 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3985 static const struct switchdev_ops mlx5e_switchdev_ops = {
3986 .switchdev_port_attr_get = mlx5e_attr_get,
3989 static void mlx5e_build_nic_netdev(struct net_device *netdev)
3991 struct mlx5e_priv *priv = netdev_priv(netdev);
3992 struct mlx5_core_dev *mdev = priv->mdev;
3996 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3998 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3999 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
4000 #ifdef CONFIG_MLX5_CORE_EN_DCB
4001 if (MLX5_CAP_GEN(mdev, qos))
4002 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4005 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
4008 netdev->watchdog_timeo = 15 * HZ;
4010 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4012 netdev->vlan_features |= NETIF_F_SG;
4013 netdev->vlan_features |= NETIF_F_IP_CSUM;
4014 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
4015 netdev->vlan_features |= NETIF_F_GRO;
4016 netdev->vlan_features |= NETIF_F_TSO;
4017 netdev->vlan_features |= NETIF_F_TSO6;
4018 netdev->vlan_features |= NETIF_F_RXCSUM;
4019 netdev->vlan_features |= NETIF_F_RXHASH;
4021 if (!!MLX5_CAP_ETH(mdev, lro_cap))
4022 netdev->vlan_features |= NETIF_F_LRO;
4024 netdev->hw_features = netdev->vlan_features;
4025 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
4026 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4027 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4029 if (mlx5e_vxlan_allowed(mdev)) {
4030 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
4031 NETIF_F_GSO_UDP_TUNNEL_CSUM |
4032 NETIF_F_GSO_PARTIAL;
4033 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4034 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4035 netdev->hw_enc_features |= NETIF_F_TSO;
4036 netdev->hw_enc_features |= NETIF_F_TSO6;
4037 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
4038 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
4039 NETIF_F_GSO_PARTIAL;
4040 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4043 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4046 netdev->hw_features |= NETIF_F_RXALL;
4048 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4049 netdev->hw_features |= NETIF_F_RXFCS;
4051 netdev->features = netdev->hw_features;
4052 if (!priv->channels.params.lro_en)
4053 netdev->features &= ~NETIF_F_LRO;
4056 netdev->features &= ~NETIF_F_RXALL;
4058 if (!priv->channels.params.scatter_fcs_en)
4059 netdev->features &= ~NETIF_F_RXFCS;
4061 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4062 if (FT_CAP(flow_modify_en) &&
4063 FT_CAP(modify_root) &&
4064 FT_CAP(identified_miss_table_mode) &&
4065 FT_CAP(flow_table_modify)) {
4066 netdev->hw_features |= NETIF_F_HW_TC;
4067 #ifdef CONFIG_RFS_ACCEL
4068 netdev->hw_features |= NETIF_F_NTUPLE;
4072 netdev->features |= NETIF_F_HIGHDMA;
4074 netdev->priv_flags |= IFF_UNICAST_FLT;
4076 mlx5e_set_netdev_dev_addr(netdev);
4078 #ifdef CONFIG_NET_SWITCHDEV
4079 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4080 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4083 mlx5e_ipsec_build_netdev(priv);
4086 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
4088 struct mlx5_core_dev *mdev = priv->mdev;
4091 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4093 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4094 priv->q_counter = 0;
4098 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
4100 if (!priv->q_counter)
4103 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4106 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4107 struct net_device *netdev,
4108 const struct mlx5e_profile *profile,
4111 struct mlx5e_priv *priv = netdev_priv(netdev);
4114 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
4115 err = mlx5e_ipsec_init(priv);
4117 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4118 mlx5e_build_nic_netdev(netdev);
4119 mlx5e_vxlan_init(priv);
4122 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4124 mlx5e_ipsec_cleanup(priv);
4125 mlx5e_vxlan_cleanup(priv);
4127 if (priv->channels.params.xdp_prog)
4128 bpf_prog_put(priv->channels.params.xdp_prog);
4131 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4133 struct mlx5_core_dev *mdev = priv->mdev;
4136 err = mlx5e_create_indirect_rqt(priv);
4140 err = mlx5e_create_direct_rqts(priv);
4142 goto err_destroy_indirect_rqts;
4144 err = mlx5e_create_indirect_tirs(priv);
4146 goto err_destroy_direct_rqts;
4148 err = mlx5e_create_direct_tirs(priv);
4150 goto err_destroy_indirect_tirs;
4152 err = mlx5e_create_flow_steering(priv);
4154 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4155 goto err_destroy_direct_tirs;
4158 err = mlx5e_tc_init(priv);
4160 goto err_destroy_flow_steering;
4164 err_destroy_flow_steering:
4165 mlx5e_destroy_flow_steering(priv);
4166 err_destroy_direct_tirs:
4167 mlx5e_destroy_direct_tirs(priv);
4168 err_destroy_indirect_tirs:
4169 mlx5e_destroy_indirect_tirs(priv);
4170 err_destroy_direct_rqts:
4171 mlx5e_destroy_direct_rqts(priv);
4172 err_destroy_indirect_rqts:
4173 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4177 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4179 mlx5e_tc_cleanup(priv);
4180 mlx5e_destroy_flow_steering(priv);
4181 mlx5e_destroy_direct_tirs(priv);
4182 mlx5e_destroy_indirect_tirs(priv);
4183 mlx5e_destroy_direct_rqts(priv);
4184 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4187 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4191 err = mlx5e_create_tises(priv);
4193 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4197 #ifdef CONFIG_MLX5_CORE_EN_DCB
4198 mlx5e_dcbnl_initialize(priv);
4203 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4205 struct net_device *netdev = priv->netdev;
4206 struct mlx5_core_dev *mdev = priv->mdev;
4209 mlx5e_init_l2_addr(priv);
4211 /* MTU range: 68 - hw-specific max */
4212 netdev->min_mtu = ETH_MIN_MTU;
4213 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4214 netdev->max_mtu = MLX5E_HW2SW_MTU(priv, max_mtu);
4215 mlx5e_set_dev_port_mtu(priv);
4217 mlx5_lag_add(mdev, netdev);
4219 mlx5e_enable_async_events(priv);
4221 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4222 mlx5e_register_vport_reps(priv);
4224 if (netdev->reg_state != NETREG_REGISTERED)
4227 /* Device already registered: sync netdev system state */
4228 if (mlx5e_vxlan_allowed(mdev)) {
4230 udp_tunnel_get_rx_info(netdev);
4234 queue_work(priv->wq, &priv->set_rx_mode_work);
4237 if (netif_running(netdev))
4239 netif_device_attach(netdev);
4243 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4245 struct mlx5_core_dev *mdev = priv->mdev;
4248 if (netif_running(priv->netdev))
4249 mlx5e_close(priv->netdev);
4250 netif_device_detach(priv->netdev);
4253 queue_work(priv->wq, &priv->set_rx_mode_work);
4255 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4256 mlx5e_unregister_vport_reps(priv);
4258 mlx5e_disable_async_events(priv);
4259 mlx5_lag_remove(mdev);
4262 static const struct mlx5e_profile mlx5e_nic_profile = {
4263 .init = mlx5e_nic_init,
4264 .cleanup = mlx5e_nic_cleanup,
4265 .init_rx = mlx5e_init_nic_rx,
4266 .cleanup_rx = mlx5e_cleanup_nic_rx,
4267 .init_tx = mlx5e_init_nic_tx,
4268 .cleanup_tx = mlx5e_cleanup_nic_tx,
4269 .enable = mlx5e_nic_enable,
4270 .disable = mlx5e_nic_disable,
4271 .update_stats = mlx5e_update_ndo_stats,
4272 .max_nch = mlx5e_get_max_num_channels,
4273 .update_carrier = mlx5e_update_carrier,
4274 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
4275 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4276 .max_tc = MLX5E_MAX_NUM_TC,
4279 /* mlx5e generic netdev management API (move to en_common.c) */
4281 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4282 const struct mlx5e_profile *profile,
4285 int nch = profile->max_nch(mdev);
4286 struct net_device *netdev;
4287 struct mlx5e_priv *priv;
4289 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
4290 nch * profile->max_tc,
4293 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4297 #ifdef CONFIG_RFS_ACCEL
4298 netdev->rx_cpu_rmap = mdev->rmap;
4301 profile->init(mdev, netdev, profile, ppriv);
4303 netif_carrier_off(netdev);
4305 priv = netdev_priv(netdev);
4307 priv->wq = create_singlethread_workqueue("mlx5e");
4309 goto err_cleanup_nic;
4314 if (profile->cleanup)
4315 profile->cleanup(priv);
4316 free_netdev(netdev);
4321 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
4323 struct mlx5_core_dev *mdev = priv->mdev;
4324 const struct mlx5e_profile *profile;
4327 profile = priv->profile;
4328 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
4330 err = profile->init_tx(priv);
4334 err = mlx5e_open_drop_rq(mdev, &priv->drop_rq);
4336 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4337 goto err_cleanup_tx;
4340 err = profile->init_rx(priv);
4342 goto err_close_drop_rq;
4344 mlx5e_create_q_counter(priv);
4346 if (profile->enable)
4347 profile->enable(priv);
4352 mlx5e_close_drop_rq(&priv->drop_rq);
4355 profile->cleanup_tx(priv);
4361 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
4363 const struct mlx5e_profile *profile = priv->profile;
4365 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
4367 if (profile->disable)
4368 profile->disable(priv);
4369 flush_workqueue(priv->wq);
4371 mlx5e_destroy_q_counter(priv);
4372 profile->cleanup_rx(priv);
4373 mlx5e_close_drop_rq(&priv->drop_rq);
4374 profile->cleanup_tx(priv);
4375 cancel_delayed_work_sync(&priv->update_stats_work);
4378 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4380 const struct mlx5e_profile *profile = priv->profile;
4381 struct net_device *netdev = priv->netdev;
4383 destroy_workqueue(priv->wq);
4384 if (profile->cleanup)
4385 profile->cleanup(priv);
4386 free_netdev(netdev);
4389 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4390 * hardware contexts and to connect it to the current netdev.
4392 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4394 struct mlx5e_priv *priv = vpriv;
4395 struct net_device *netdev = priv->netdev;
4398 if (netif_device_present(netdev))
4401 err = mlx5e_create_mdev_resources(mdev);
4405 err = mlx5e_attach_netdev(priv);
4407 mlx5e_destroy_mdev_resources(mdev);
4414 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4416 struct mlx5e_priv *priv = vpriv;
4417 struct net_device *netdev = priv->netdev;
4419 if (!netif_device_present(netdev))
4422 mlx5e_detach_netdev(priv);
4423 mlx5e_destroy_mdev_resources(mdev);
4426 static void *mlx5e_add(struct mlx5_core_dev *mdev)
4428 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4429 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
4430 struct mlx5e_rep_priv *rpriv = NULL;
4434 struct net_device *netdev;
4436 err = mlx5e_check_required_hca_cap(mdev);
4440 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
4441 rpriv = kzalloc(sizeof(*rpriv), GFP_KERNEL);
4443 mlx5_core_warn(mdev,
4444 "Not creating net device, Failed to alloc rep priv data\n");
4447 rpriv->rep = &esw->offloads.vport_reps[0];
4450 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
4452 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4453 goto err_unregister_reps;
4456 priv = netdev_priv(netdev);
4458 err = mlx5e_attach(mdev, priv);
4460 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4461 goto err_destroy_netdev;
4464 err = register_netdev(netdev);
4466 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4473 mlx5e_detach(mdev, priv);
4476 mlx5e_destroy_netdev(priv);
4478 err_unregister_reps:
4479 for (vport = 1; vport < total_vfs; vport++)
4480 mlx5_eswitch_unregister_vport_rep(esw, vport);
4486 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4488 struct mlx5e_priv *priv = vpriv;
4489 void *ppriv = priv->ppriv;
4491 unregister_netdev(priv->netdev);
4492 mlx5e_detach(mdev, vpriv);
4493 mlx5e_destroy_netdev(priv);
4497 static void *mlx5e_get_netdev(void *vpriv)
4499 struct mlx5e_priv *priv = vpriv;
4501 return priv->netdev;
4504 static struct mlx5_interface mlx5e_interface = {
4506 .remove = mlx5e_remove,
4507 .attach = mlx5e_attach,
4508 .detach = mlx5e_detach,
4509 .event = mlx5e_async_event,
4510 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4511 .get_dev = mlx5e_get_netdev,
4514 void mlx5e_init(void)
4516 mlx5e_ipsec_build_inverse_table();
4517 mlx5e_build_ptys2ethtool_map();
4518 mlx5_register_interface(&mlx5e_interface);
4521 void mlx5e_cleanup(void)
4523 mlx5_unregister_interface(&mlx5e_interface);