drivers/net/ethernet/mellanox/mlx5/core/en_rx.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/prefetch.h>
  34 #include <linux/ip.h>
  35 #include <linux/ipv6.h>
  36 #include <linux/tcp.h>
  37 #include <linux/indirect_call_wrapper.h>
  38 #include <net/ip6_checksum.h>
  39 #include <net/page_pool.h>
  40 #include <net/inet_ecn.h>
  41 #include "en.h"
  42 #include "en_tc.h"
  43 #include "eswitch.h"
  44 #include "en_rep.h"
  45 #include "ipoib/ipoib.h"
  46 #include "en_accel/ipsec_rxtx.h"
  47 #include "en_accel/tls_rxtx.h"
  48 #include "lib/clock.h"
  49 #include "en/xdp.h"
  50
  51 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
  52 {
  53         return config->rx_filter == HWTSTAMP_FILTER_ALL;
  54 }
  55
  56 static inline void mlx5e_read_cqe_slot(struct mlx5_cqwq *wq,
  57                                        u32 cqcc, void *data)
  58 {
  59         u32 ci = mlx5_cqwq_ctr2ix(wq, cqcc);
  60
  61         memcpy(data, mlx5_cqwq_get_wqe(wq, ci), sizeof(struct mlx5_cqe64));
  62 }
  63
  64 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
  65                                          struct mlx5_cqwq *wq,
  66                                          u32 cqcc)
  67 {
  68         struct mlx5e_cq_decomp *cqd = &rq->cqd;
  69         struct mlx5_cqe64 *title = &cqd->title;
  70
  71         mlx5e_read_cqe_slot(wq, cqcc, title);
  72         cqd->left        = be32_to_cpu(title->byte_cnt);
  73         cqd->wqe_counter = be16_to_cpu(title->wqe_counter);
  74         rq->stats->cqe_compress_blks++;
  75 }
  76
  77 static inline void mlx5e_read_mini_arr_slot(struct mlx5_cqwq *wq,
  78                                             struct mlx5e_cq_decomp *cqd,
  79                                             u32 cqcc)
  80 {
  81         mlx5e_read_cqe_slot(wq, cqcc, cqd->mini_arr);
  82         cqd->mini_arr_idx = 0;
  83 }
  84
  85 static inline void mlx5e_cqes_update_owner(struct mlx5_cqwq *wq, int n)
  86 {
  87         u32 cqcc   = wq->cc;
  88         u8  op_own = mlx5_cqwq_get_ctr_wrap_cnt(wq, cqcc) & 1;
  89         u32 ci     = mlx5_cqwq_ctr2ix(wq, cqcc);
  90         u32 wq_sz  = mlx5_cqwq_get_size(wq);
  91         u32 ci_top = min_t(u32, wq_sz, ci + n);
  92
  93         for (; ci < ci_top; ci++, n--) {
  94                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci);
  95
  96                 cqe->op_own = op_own;
  97         }
  98
  99         if (unlikely(ci == wq_sz)) {
 100                 op_own = !op_own;
 101                 for (ci = 0; ci < n; ci++) {
 102                         struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci);
 103
 104                         cqe->op_own = op_own;
 105                 }
 106         }
 107 }
 108
 109 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
 110                                         struct mlx5_cqwq *wq,
 111                                         u32 cqcc)
 112 {
 113         struct mlx5e_cq_decomp *cqd = &rq->cqd;
 114         struct mlx5_mini_cqe8 *mini_cqe = &cqd->mini_arr[cqd->mini_arr_idx];
 115         struct mlx5_cqe64 *title = &cqd->title;
 116
 117         title->byte_cnt     = mini_cqe->byte_cnt;
 118         title->check_sum    = mini_cqe->checksum;
 119         title->op_own      &= 0xf0;
 120         title->op_own      |= 0x01 & (cqcc >> wq->fbc.log_sz);
 121         title->wqe_counter  = cpu_to_be16(cqd->wqe_counter);
 122
 123         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 124                 cqd->wqe_counter += mpwrq_get_cqe_consumed_strides(title);
 125         else
 126                 cqd->wqe_counter =
 127                         mlx5_wq_cyc_ctr2ix(&rq->wqe.wq, cqd->wqe_counter + 1);
 128 }
 129
 130 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
 131                                                 struct mlx5_cqwq *wq,
 132                                                 u32 cqcc)
 133 {
 134         struct mlx5e_cq_decomp *cqd = &rq->cqd;
 135
 136         mlx5e_decompress_cqe(rq, wq, cqcc);
 137         cqd->title.rss_hash_type   = 0;
 138         cqd->title.rss_hash_result = 0;
 139 }
 140
 141 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
 142                                              struct mlx5_cqwq *wq,
 143                                              int update_owner_only,
 144                                              int budget_rem)
 145 {
 146         struct mlx5e_cq_decomp *cqd = &rq->cqd;
 147         u32 cqcc = wq->cc + update_owner_only;
 148         u32 cqe_count;
 149         u32 i;
 150
 151         cqe_count = min_t(u32, cqd->left, budget_rem);
 152
 153         for (i = update_owner_only; i < cqe_count;
 154              i++, cqd->mini_arr_idx++, cqcc++) {
 155                 if (cqd->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
 156                         mlx5e_read_mini_arr_slot(wq, cqd, cqcc);
 157
 158                 mlx5e_decompress_cqe_no_hash(rq, wq, cqcc);
 159                 rq->handle_rx_cqe(rq, &cqd->title);
 160         }
 161         mlx5e_cqes_update_owner(wq, cqcc - wq->cc);
 162         wq->cc = cqcc;
 163         cqd->left -= cqe_count;
 164         rq->stats->cqe_compress_pkts += cqe_count;
 165
 166         return cqe_count;
 167 }
 168
 169 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
 170                                               struct mlx5_cqwq *wq,
 171                                               int budget_rem)
 172 {
 173         struct mlx5e_cq_decomp *cqd = &rq->cqd;
 174         u32 cc = wq->cc;
 175
 176         mlx5e_read_title_slot(rq, wq, cc);
 177         mlx5e_read_mini_arr_slot(wq, cqd, cc + 1);
 178         mlx5e_decompress_cqe(rq, wq, cc);
 179         rq->handle_rx_cqe(rq, &cqd->title);
 180         cqd->mini_arr_idx++;
 181
 182         return mlx5e_decompress_cqes_cont(rq, wq, 1, budget_rem) - 1;
 183 }
 184
 185 static inline bool mlx5e_page_is_reserved(struct page *page)
 186 {
 187         return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
 188 }
 189
 190 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
 191                                       struct mlx5e_dma_info *dma_info)
 192 {
 193         struct mlx5e_page_cache *cache = &rq->page_cache;
 194         u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
 195         struct mlx5e_rq_stats *stats = rq->stats;
 196
 197         if (tail_next == cache->head) {
 198                 stats->cache_full++;
 199                 return false;
 200         }
 201
 202         if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
 203                 stats->cache_waive++;
 204                 return false;
 205         }
 206
 207         cache->page_cache[cache->tail] = *dma_info;
 208         cache->tail = tail_next;
 209         return true;
 210 }
 211
 212 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
 213                                       struct mlx5e_dma_info *dma_info)
 214 {
 215         struct mlx5e_page_cache *cache = &rq->page_cache;
 216         struct mlx5e_rq_stats *stats = rq->stats;
 217
 218         if (unlikely(cache->head == cache->tail)) {
 219                 stats->cache_empty++;
 220                 return false;
 221         }
 222
 223         if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
 224                 stats->cache_busy++;
 225                 return false;
 226         }
 227
 228         *dma_info = cache->page_cache[cache->head];
 229         cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
 230         stats->cache_reuse++;
 231
 232         dma_sync_single_for_device(rq->pdev, dma_info->addr,
 233                                    PAGE_SIZE,
 234                                    DMA_FROM_DEVICE);
 235         return true;
 236 }
 237
 238 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq,
 239                                           struct mlx5e_dma_info *dma_info)
 240 {
 241         if (mlx5e_rx_cache_get(rq, dma_info))
 242                 return 0;
 243
 244         dma_info->page = page_pool_dev_alloc_pages(rq->page_pool);
 245         if (unlikely(!dma_info->page))
 246                 return -ENOMEM;
 247
 248         dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
 249                                       PAGE_SIZE, rq->buff.map_dir);
 250         if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
 251                 put_page(dma_info->page);
 252                 dma_info->page = NULL;
 253                 return -ENOMEM;
 254         }
 255
 256         return 0;
 257 }
 258
 259 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info)
 260 {
 261         dma_unmap_page(rq->pdev, dma_info->addr, PAGE_SIZE, rq->buff.map_dir);
 262 }
 263
 264 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
 265                         bool recycle)
 266 {
 267         if (likely(recycle)) {
 268                 if (mlx5e_rx_cache_put(rq, dma_info))
 269                         return;
 270
 271                 mlx5e_page_dma_unmap(rq, dma_info);
 272                 page_pool_recycle_direct(rq->page_pool, dma_info->page);
 273         } else {
 274                 mlx5e_page_dma_unmap(rq, dma_info);
 275                 put_page(dma_info->page);
 276         }
 277 }
 278
 279 static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq,
 280                                     struct mlx5e_wqe_frag_info *frag)
 281 {
 282         int err = 0;
 283
 284         if (!frag->offset)
 285                 /* On first frag (offset == 0), replenish page (dma_info actually).
 286                  * Other frags that point to the same dma_info (with a different
 287                  * offset) should just use the new one without replenishing again
 288                  * by themselves.
 289                  */
 290                 err = mlx5e_page_alloc_mapped(rq, frag->di);
 291
 292         return err;
 293 }
 294
 295 static inline void mlx5e_put_rx_frag(struct mlx5e_rq *rq,
 296                                      struct mlx5e_wqe_frag_info *frag,
 297                                      bool recycle)
 298 {
 299         if (frag->last_in_page)
 300                 mlx5e_page_release(rq, frag->di, recycle);
 301 }
 302
 303 static inline struct mlx5e_wqe_frag_info *get_frag(struct mlx5e_rq *rq, u16 ix)
 304 {
 305         return &rq->wqe.frags[ix << rq->wqe.info.log_num_frags];
 306 }
 307
 308 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe_cyc *wqe,
 309                               u16 ix)
 310 {
 311         struct mlx5e_wqe_frag_info *frag = get_frag(rq, ix);
 312         int err;
 313         int i;
 314
 315         for (i = 0; i < rq->wqe.info.num_frags; i++, frag++) {
 316                 err = mlx5e_get_rx_frag(rq, frag);
 317                 if (unlikely(err))
 318                         goto free_frags;
 319
 320                 wqe->data[i].addr = cpu_to_be64(frag->di->addr +
 321                                                 frag->offset + rq->buff.headroom);
 322         }
 323
 324         return 0;
 325
 326 free_frags:
 327         while (--i >= 0)
 328                 mlx5e_put_rx_frag(rq, --frag, true);
 329
 330         return err;
 331 }
 332
 333 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
 334                                      struct mlx5e_wqe_frag_info *wi,
 335                                      bool recycle)
 336 {
 337         int i;
 338
 339         for (i = 0; i < rq->wqe.info.num_frags; i++, wi++)
 340                 mlx5e_put_rx_frag(rq, wi, recycle);
 341 }
 342
 343 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
 344 {
 345         struct mlx5e_wqe_frag_info *wi = get_frag(rq, ix);
 346
 347         mlx5e_free_rx_wqe(rq, wi, false);
 348 }
 349
 350 static int mlx5e_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, u8 wqe_bulk)
 351 {
 352         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 353         int err;
 354         int i;
 355
 356         for (i = 0; i < wqe_bulk; i++) {
 357                 struct mlx5e_rx_wqe_cyc *wqe = mlx5_wq_cyc_get_wqe(wq, ix + i);
 358
 359                 err = mlx5e_alloc_rx_wqe(rq, wqe, ix + i);
 360                 if (unlikely(err))
 361                         goto free_wqes;
 362         }
 363
 364         return 0;
 365
 366 free_wqes:
 367         while (--i >= 0)
 368                 mlx5e_dealloc_rx_wqe(rq, ix + i);
 369
 370         return err;
 371 }
 372
 373 static inline void
 374 mlx5e_add_skb_frag(struct mlx5e_rq *rq, struct sk_buff *skb,
 375                    struct mlx5e_dma_info *di, u32 frag_offset, u32 len,
 376                    unsigned int truesize)
 377 {
 378         dma_sync_single_for_cpu(rq->pdev,
 379                                 di->addr + frag_offset,
 380                                 len, DMA_FROM_DEVICE);
 381         page_ref_inc(di->page);
 382         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
 383                         di->page, frag_offset, len, truesize);
 384 }
 385
 386 static inline void
 387 mlx5e_copy_skb_header(struct device *pdev, struct sk_buff *skb,
 388                       struct mlx5e_dma_info *dma_info,
 389                       int offset_from, u32 headlen)
 390 {
 391         const void *from = page_address(dma_info->page) + offset_from;
 392         /* Aligning len to sizeof(long) optimizes memcpy performance */
 393         unsigned int len = ALIGN(headlen, sizeof(long));
 394
 395         dma_sync_single_for_cpu(pdev, dma_info->addr + offset_from, len,
 396                                 DMA_FROM_DEVICE);
 397         skb_copy_to_linear_data(skb, from, len);
 398 }
 399
 400 static void
 401 mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, bool recycle)
 402 {
 403         const bool no_xdp_xmit =
 404                 bitmap_empty(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
 405         struct mlx5e_dma_info *dma_info = wi->umr.dma_info;
 406         int i;
 407
 408         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++)
 409                 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap))
 410                         mlx5e_page_release(rq, &dma_info[i], recycle);
 411 }
 412
 413 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq, u8 n)
 414 {
 415         struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 416
 417         do {
 418                 u16 next_wqe_index = mlx5_wq_ll_get_wqe_next_ix(wq, wq->head);
 419
 420                 mlx5_wq_ll_push(wq, next_wqe_index);
 421         } while (--n);
 422
 423         /* ensure wqes are visible to device before updating doorbell record */
 424         dma_wmb();
 425
 426         mlx5_wq_ll_update_db_record(wq);
 427 }
 428
 429 static inline u16 mlx5e_icosq_wrap_cnt(struct mlx5e_icosq *sq)
 430 {
 431         return mlx5_wq_cyc_get_ctr_wrap_cnt(&sq->wq, sq->pc);
 432 }
 433
 434 static inline void mlx5e_fill_icosq_frag_edge(struct mlx5e_icosq *sq,
 435                                               struct mlx5_wq_cyc *wq,
 436                                               u16 pi, u16 nnops)
 437 {
 438         struct mlx5e_sq_wqe_info *edge_wi, *wi = &sq->db.ico_wqe[pi];
 439
 440         edge_wi = wi + nnops;
 441
 442         /* fill sq frag edge with nops to avoid wqe wrapping two pages */
 443         for (; wi < edge_wi; wi++) {
 444                 wi->opcode = MLX5_OPCODE_NOP;
 445                 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
 446         }
 447 }
 448
 449 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 450 {
 451         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 452         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
 453         struct mlx5e_icosq *sq = &rq->channel->icosq;
 454         struct mlx5_wq_cyc *wq = &sq->wq;
 455         struct mlx5e_umr_wqe *umr_wqe;
 456         u16 xlt_offset = ix << (MLX5E_LOG_ALIGNED_MPWQE_PPW - 1);
 457         u16 pi, contig_wqebbs_room;
 458         int err;
 459         int i;
 460
 461         pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
 462         contig_wqebbs_room = mlx5_wq_cyc_get_contig_wqebbs(wq, pi);
 463         if (unlikely(contig_wqebbs_room < MLX5E_UMR_WQEBBS)) {
 464                 mlx5e_fill_icosq_frag_edge(sq, wq, pi, contig_wqebbs_room);
 465                 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
 466         }
 467
 468         umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi);
 469         if (unlikely(mlx5e_icosq_wrap_cnt(sq) < 2))
 470                 memcpy(umr_wqe, &rq->mpwqe.umr_wqe,
 471                        offsetof(struct mlx5e_umr_wqe, inline_mtts));
 472
 473         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
 474                 err = mlx5e_page_alloc_mapped(rq, dma_info);
 475                 if (unlikely(err))
 476                         goto err_unmap;
 477                 umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
 478         }
 479
 480         bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
 481         wi->consumed_strides = 0;
 482
 483         umr_wqe->ctrl.opmod_idx_opcode =
 484                 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
 485                             MLX5_OPCODE_UMR);
 486         umr_wqe->uctrl.xlt_offset = cpu_to_be16(xlt_offset);
 487
 488         sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
 489         sq->pc += MLX5E_UMR_WQEBBS;
 490
 491         sq->doorbell_cseg = &umr_wqe->ctrl;
 492
 493         return 0;
 494
 495 err_unmap:
 496         while (--i >= 0) {
 497                 dma_info--;
 498                 mlx5e_page_release(rq, dma_info, true);
 499         }
 500         rq->stats->buff_alloc_err++;
 501
 502         return err;
 503 }
 504
 505 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 506 {
 507         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 508         /* Don't recycle, this function is called on rq/netdev close */
 509         mlx5e_free_rx_mpwqe(rq, wi, false);
 510 }
 511
 512 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
 513 {
 514         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 515         u8 wqe_bulk;
 516         int err;
 517
 518         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
 519                 return false;
 520
 521         wqe_bulk = rq->wqe.info.wqe_bulk;
 522
 523         if (mlx5_wq_cyc_missing(wq) < wqe_bulk)
 524                 return false;
 525
 526         do {
 527                 u16 head = mlx5_wq_cyc_get_head(wq);
 528
 529                 err = mlx5e_alloc_rx_wqes(rq, head, wqe_bulk);
 530                 if (unlikely(err)) {
 531                         rq->stats->buff_alloc_err++;
 532                         break;
 533                 }
 534
 535                 mlx5_wq_cyc_push_n(wq, wqe_bulk);
 536         } while (mlx5_wq_cyc_missing(wq) >= wqe_bulk);
 537
 538         /* ensure wqes are visible to device before updating doorbell record */
 539         dma_wmb();
 540
 541         mlx5_wq_cyc_update_db_record(wq);
 542
 543         return !!err;
 544 }
 545
 546 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq)
 547 {
 548         struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
 549         struct mlx5_cqe64 *cqe;
 550         u8  completed_umr = 0;
 551         u16 sqcc;
 552         int i;
 553
 554         if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
 555                 return;
 556
 557         cqe = mlx5_cqwq_get_cqe(&cq->wq);
 558         if (likely(!cqe))
 559                 return;
 560
 561         /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
 562          * otherwise a cq overrun may occur
 563          */
 564         sqcc = sq->cc;
 565
 566         i = 0;
 567         do {
 568                 u16 wqe_counter;
 569                 bool last_wqe;
 570
 571                 mlx5_cqwq_pop(&cq->wq);
 572
 573                 wqe_counter = be16_to_cpu(cqe->wqe_counter);
 574
 575                 if (unlikely(get_cqe_opcode(cqe) != MLX5_CQE_REQ)) {
 576                         netdev_WARN_ONCE(cq->channel->netdev,
 577                                          "Bad OP in ICOSQ CQE: 0x%x\n", get_cqe_opcode(cqe));
 578                         break;
 579                 }
 580                 do {
 581                         struct mlx5e_sq_wqe_info *wi;
 582                         u16 ci;
 583
 584                         last_wqe = (sqcc == wqe_counter);
 585
 586                         ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
 587                         wi = &sq->db.ico_wqe[ci];
 588
 589                         if (likely(wi->opcode == MLX5_OPCODE_UMR)) {
 590                                 sqcc += MLX5E_UMR_WQEBBS;
 591                                 completed_umr++;
 592                         } else if (likely(wi->opcode == MLX5_OPCODE_NOP)) {
 593                                 sqcc++;
 594                         } else {
 595                                 netdev_WARN_ONCE(cq->channel->netdev,
 596                                                  "Bad OPCODE in ICOSQ WQE info: 0x%x\n",
 597                                                  wi->opcode);
 598                         }
 599
 600                 } while (!last_wqe);
 601
 602         } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
 603
 604         sq->cc = sqcc;
 605
 606         mlx5_cqwq_update_db_record(&cq->wq);
 607
 608         if (likely(completed_umr)) {
 609                 mlx5e_post_rx_mpwqe(rq, completed_umr);
 610                 rq->mpwqe.umr_in_progress -= completed_umr;
 611         }
 612 }
 613
 614 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
 615 {
 616         struct mlx5e_icosq *sq = &rq->channel->icosq;
 617         struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 618         u8  missing, i;
 619         u16 head;
 620
 621         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
 622                 return false;
 623
 624         mlx5e_poll_ico_cq(&sq->cq, rq);
 625
 626         missing = mlx5_wq_ll_missing(wq) - rq->mpwqe.umr_in_progress;
 627
 628         if (unlikely(rq->mpwqe.umr_in_progress > rq->mpwqe.umr_last_bulk))
 629                 rq->stats->congst_umr++;
 630
 631 #define UMR_WQE_BULK (2)
 632         if (likely(missing < UMR_WQE_BULK))
 633                 return false;
 634
 635         head = rq->mpwqe.actual_wq_head;
 636         i = missing;
 637         do {
 638                 if (unlikely(mlx5e_alloc_rx_mpwqe(rq, head)))
 639                         break;
 640                 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 641         } while (--i);
 642
 643         rq->mpwqe.umr_last_bulk    = missing - i;
 644         if (sq->doorbell_cseg) {
 645                 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, sq->doorbell_cseg);
 646                 sq->doorbell_cseg = NULL;
 647         }
 648
 649         rq->mpwqe.umr_in_progress += rq->mpwqe.umr_last_bulk;
 650         rq->mpwqe.actual_wq_head   = head;
 651
 652         return false;
 653 }
 654
 655 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
 656 {
 657         u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
 658         u8 tcp_ack     = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
 659                          (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
 660
 661         tcp->check                      = 0;
 662         tcp->psh                        = get_cqe_lro_tcppsh(cqe);
 663
 664         if (tcp_ack) {
 665                 tcp->ack                = 1;
 666                 tcp->ack_seq            = cqe->lro_ack_seq_num;
 667                 tcp->window             = cqe->lro_tcp_win;
 668         }
 669 }
 670
 671 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
 672                                  u32 cqe_bcnt)
 673 {
 674         struct ethhdr   *eth = (struct ethhdr *)(skb->data);
 675         struct tcphdr   *tcp;
 676         int network_depth = 0;
 677         __wsum check;
 678         __be16 proto;
 679         u16 tot_len;
 680         void *ip_p;
 681
 682         proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
 683
 684         tot_len = cqe_bcnt - network_depth;
 685         ip_p = skb->data + network_depth;
 686
 687         if (proto == htons(ETH_P_IP)) {
 688                 struct iphdr *ipv4 = ip_p;
 689
 690                 tcp = ip_p + sizeof(struct iphdr);
 691                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
 692
 693                 ipv4->ttl               = cqe->lro_min_ttl;
 694                 ipv4->tot_len           = cpu_to_be16(tot_len);
 695                 ipv4->check             = 0;
 696                 ipv4->check             = ip_fast_csum((unsigned char *)ipv4,
 697                                                        ipv4->ihl);
 698
 699                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 700                 check = csum_partial(tcp, tcp->doff * 4,
 701                                      csum_unfold((__force __sum16)cqe->check_sum));
 702                 /* Almost done, don't forget the pseudo header */
 703                 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
 704                                                tot_len - sizeof(struct iphdr),
 705                                                IPPROTO_TCP, check);
 706         } else {
 707                 u16 payload_len = tot_len - sizeof(struct ipv6hdr);
 708                 struct ipv6hdr *ipv6 = ip_p;
 709
 710                 tcp = ip_p + sizeof(struct ipv6hdr);
 711                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
 712
 713                 ipv6->hop_limit         = cqe->lro_min_ttl;
 714                 ipv6->payload_len       = cpu_to_be16(payload_len);
 715
 716                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 717                 check = csum_partial(tcp, tcp->doff * 4,
 718                                      csum_unfold((__force __sum16)cqe->check_sum));
 719                 /* Almost done, don't forget the pseudo header */
 720                 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
 721                                              IPPROTO_TCP, check);
 722         }
 723 }
 724
 725 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
 726                                       struct sk_buff *skb)
 727 {
 728         u8 cht = cqe->rss_hash_type;
 729         int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
 730                  (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
 731                                             PKT_HASH_TYPE_NONE;
 732         skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
 733 }
 734
 735 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth,
 736                                         __be16 *proto)
 737 {
 738         *proto = ((struct ethhdr *)skb->data)->h_proto;
 739         *proto = __vlan_get_protocol(skb, *proto, network_depth);
 740
 741         if (*proto == htons(ETH_P_IP))
 742                 return pskb_may_pull(skb, *network_depth + sizeof(struct iphdr));
 743
 744         if (*proto == htons(ETH_P_IPV6))
 745                 return pskb_may_pull(skb, *network_depth + sizeof(struct ipv6hdr));
 746
 747         return false;
 748 }
 749
 750 static inline void mlx5e_enable_ecn(struct mlx5e_rq *rq, struct sk_buff *skb)
 751 {
 752         int network_depth = 0;
 753         __be16 proto;
 754         void *ip;
 755         int rc;
 756
 757         if (unlikely(!is_last_ethertype_ip(skb, &network_depth, &proto)))
 758                 return;
 759
 760         ip = skb->data + network_depth;
 761         rc = ((proto == htons(ETH_P_IP)) ? IP_ECN_set_ce((struct iphdr *)ip) :
 762                                          IP6_ECN_set_ce(skb, (struct ipv6hdr *)ip));
 763
 764         rq->stats->ecn_mark += !!rc;
 765 }
 766
 767 static u8 get_ip_proto(struct sk_buff *skb, int network_depth, __be16 proto)
 768 {
 769         void *ip_p = skb->data + network_depth;
 770
 771         return (proto == htons(ETH_P_IP)) ? ((struct iphdr *)ip_p)->protocol :
 772                                             ((struct ipv6hdr *)ip_p)->nexthdr;
 773 }
 774
 775 #define short_frame(size) ((size) <= ETH_ZLEN + ETH_FCS_LEN)
 776
 777 #define MAX_PADDING 8
 778
 779 static void
 780 tail_padding_csum_slow(struct sk_buff *skb, int offset, int len,
 781                        struct mlx5e_rq_stats *stats)
 782 {
 783         stats->csum_complete_tail_slow++;
 784         skb->csum = csum_block_add(skb->csum,
 785                                    skb_checksum(skb, offset, len, 0),
 786                                    offset);
 787 }
 788
 789 static void
 790 tail_padding_csum(struct sk_buff *skb, int offset,
 791                   struct mlx5e_rq_stats *stats)
 792 {
 793         u8 tail_padding[MAX_PADDING];
 794         int len = skb->len - offset;
 795         void *tail;
 796
 797         if (unlikely(len > MAX_PADDING)) {
 798                 tail_padding_csum_slow(skb, offset, len, stats);
 799                 return;
 800         }
 801
 802         tail = skb_header_pointer(skb, offset, len, tail_padding);
 803         if (unlikely(!tail)) {
 804                 tail_padding_csum_slow(skb, offset, len, stats);
 805                 return;
 806         }
 807
 808         stats->csum_complete_tail++;
 809         skb->csum = csum_block_add(skb->csum, csum_partial(tail, len, 0), offset);
 810 }
 811
 812 static void
 813 mlx5e_skb_padding_csum(struct sk_buff *skb, int network_depth, __be16 proto,
 814                        struct mlx5e_rq_stats *stats)
 815 {
 816         struct ipv6hdr *ip6;
 817         struct iphdr   *ip4;
 818         int pkt_len;
 819
 820         switch (proto) {
 821         case htons(ETH_P_IP):
 822                 ip4 = (struct iphdr *)(skb->data + network_depth);
 823                 pkt_len = network_depth + ntohs(ip4->tot_len);
 824                 break;
 825         case htons(ETH_P_IPV6):
 826                 ip6 = (struct ipv6hdr *)(skb->data + network_depth);
 827                 pkt_len = network_depth + sizeof(*ip6) + ntohs(ip6->payload_len);
 828                 break;
 829         default:
 830                 return;
 831         }
 832
 833         if (likely(pkt_len >= skb->len))
 834                 return;
 835
 836         tail_padding_csum(skb, pkt_len, stats);
 837 }
 838
 839 static inline void mlx5e_handle_csum(struct net_device *netdev,
 840                                      struct mlx5_cqe64 *cqe,
 841                                      struct mlx5e_rq *rq,
 842                                      struct sk_buff *skb,
 843                                      bool   lro)
 844 {
 845         struct mlx5e_rq_stats *stats = rq->stats;
 846         int network_depth = 0;
 847         __be16 proto;
 848
 849         if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
 850                 goto csum_none;
 851
 852         if (lro) {
 853                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 854                 stats->csum_unnecessary++;
 855                 return;
 856         }
 857
 858         /* True when explicitly set via priv flag, or XDP prog is loaded */
 859         if (test_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state))
 860                 goto csum_unnecessary;
 861
 862         /* CQE csum doesn't cover padding octets in short ethernet
 863          * frames. And the pad field is appended prior to calculating
 864          * and appending the FCS field.
 865          *
 866          * Detecting these padded frames requires to verify and parse
 867          * IP headers, so we simply force all those small frames to be
 868          * CHECKSUM_UNNECESSARY even if they are not padded.
 869          */
 870         if (short_frame(skb->len))
 871                 goto csum_unnecessary;
 872
 873         if (likely(is_last_ethertype_ip(skb, &network_depth, &proto))) {
 874                 if (unlikely(get_ip_proto(skb, network_depth, proto) == IPPROTO_SCTP))
 875                         goto csum_unnecessary;
 876
 877                 skb->ip_summed = CHECKSUM_COMPLETE;
 878                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
 879                 if (network_depth > ETH_HLEN)
 880                         /* CQE csum is calculated from the IP header and does
 881                          * not cover VLAN headers (if present). This will add
 882                          * the checksum manually.
 883                          */
 884                         skb->csum = csum_partial(skb->data + ETH_HLEN,
 885                                                  network_depth - ETH_HLEN,
 886                                                  skb->csum);
 887
 888                 mlx5e_skb_padding_csum(skb, network_depth, proto, stats);
 889                 stats->csum_complete++;
 890                 return;
 891         }
 892
 893 csum_unnecessary:
 894         if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
 895                    (cqe->hds_ip_ext & CQE_L4_OK))) {
 896                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 897                 if (cqe_is_tunneled(cqe)) {
 898                         skb->csum_level = 1;
 899                         skb->encapsulation = 1;
 900                         stats->csum_unnecessary_inner++;
 901                         return;
 902                 }
 903                 stats->csum_unnecessary++;
 904                 return;
 905         }
 906 csum_none:
 907         skb->ip_summed = CHECKSUM_NONE;
 908         stats->csum_none++;
 909 }
 910
 911 #define MLX5E_CE_BIT_MASK 0x80
 912
 913 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
 914                                       u32 cqe_bcnt,
 915                                       struct mlx5e_rq *rq,
 916                                       struct sk_buff *skb)
 917 {
 918         u8 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
 919         struct mlx5e_rq_stats *stats = rq->stats;
 920         struct net_device *netdev = rq->netdev;
 921
 922         skb->mac_len = ETH_HLEN;
 923
 924 #ifdef CONFIG_MLX5_EN_TLS
 925         mlx5e_tls_handle_rx_skb(netdev, skb, &cqe_bcnt);
 926 #endif
 927
 928         if (lro_num_seg > 1) {
 929                 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
 930                 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
 931                 /* Subtract one since we already counted this as one
 932                  * "regular" packet in mlx5e_complete_rx_cqe()
 933                  */
 934                 stats->packets += lro_num_seg - 1;
 935                 stats->lro_packets++;
 936                 stats->lro_bytes += cqe_bcnt;
 937         }
 938
 939         if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
 940                 skb_hwtstamps(skb)->hwtstamp =
 941                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
 942
 943         skb_record_rx_queue(skb, rq->ix);
 944
 945         if (likely(netdev->features & NETIF_F_RXHASH))
 946                 mlx5e_skb_set_hash(cqe, skb);
 947
 948         if (cqe_has_vlan(cqe)) {
 949                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
 950                                        be16_to_cpu(cqe->vlan_info));
 951                 stats->removed_vlan_packets++;
 952         }
 953
 954         skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
 955
 956         mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
 957         /* checking CE bit in cqe - MSB in ml_path field */
 958         if (unlikely(cqe->ml_path & MLX5E_CE_BIT_MASK))
 959                 mlx5e_enable_ecn(rq, skb);
 960
 961         skb->protocol = eth_type_trans(skb, netdev);
 962 }
 963
 964 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
 965                                          struct mlx5_cqe64 *cqe,
 966                                          u32 cqe_bcnt,
 967                                          struct sk_buff *skb)
 968 {
 969         struct mlx5e_rq_stats *stats = rq->stats;
 970
 971         stats->packets++;
 972         stats->bytes += cqe_bcnt;
 973         mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
 974 }
 975
 976 static inline
 977 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va,
 978                                        u32 frag_size, u16 headroom,
 979                                        u32 cqe_bcnt)
 980 {
 981         struct sk_buff *skb = build_skb(va, frag_size);
 982
 983         if (unlikely(!skb)) {
 984                 rq->stats->buff_alloc_err++;
 985                 return NULL;
 986         }
 987
 988         skb_reserve(skb, headroom);
 989         skb_put(skb, cqe_bcnt);
 990
 991         return skb;
 992 }
 993
 994 struct sk_buff *
 995 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
 996                           struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
 997 {
 998         struct mlx5e_dma_info *di = wi->di;
 999         u16 rx_headroom = rq->buff.headroom;
1000         struct sk_buff *skb;
1001         void *va, *data;
1002         bool consumed;
1003         u32 frag_size;
1004
1005         va             = page_address(di->page) + wi->offset;
1006         data           = va + rx_headroom;
1007         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
1008
1009         dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset,
1010                                       frag_size, DMA_FROM_DEVICE);
1011         prefetchw(va); /* xdp_frame data area */
1012         prefetch(data);
1013
1014         if (unlikely(get_cqe_opcode(cqe) != MLX5_CQE_RESP_SEND)) {
1015                 rq->stats->wqe_err++;
1016                 return NULL;
1017         }
1018
1019         rcu_read_lock();
1020         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt);
1021         rcu_read_unlock();
1022         if (consumed)
1023                 return NULL; /* page/packet was consumed by XDP */
1024
1025         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt);
1026         if (unlikely(!skb))
1027                 return NULL;
1028
1029         /* queue up for recycling/reuse */
1030         page_ref_inc(di->page);
1031
1032         return skb;
1033 }
1034
1035 struct sk_buff *
1036 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
1037                              struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
1038 {
1039         struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
1040         struct mlx5e_wqe_frag_info *head_wi = wi;
1041         u16 headlen      = min_t(u32, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1042         u16 frag_headlen = headlen;
1043         u16 byte_cnt     = cqe_bcnt - headlen;
1044         struct sk_buff *skb;
1045
1046         if (unlikely(get_cqe_opcode(cqe) != MLX5_CQE_RESP_SEND)) {
1047                 rq->stats->wqe_err++;
1048                 return NULL;
1049         }
1050
1051         /* XDP is not supported in this configuration, as incoming packets
1052          * might spread among multiple pages.
1053          */
1054         skb = napi_alloc_skb(rq->cq.napi,
1055                              ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1056         if (unlikely(!skb)) {
1057                 rq->stats->buff_alloc_err++;
1058                 return NULL;
1059         }
1060
1061         prefetchw(skb->data);
1062
1063         while (byte_cnt) {
1064                 u16 frag_consumed_bytes =
1065                         min_t(u16, frag_info->frag_size - frag_headlen, byte_cnt);
1066
1067                 mlx5e_add_skb_frag(rq, skb, wi->di, wi->offset + frag_headlen,
1068                                    frag_consumed_bytes, frag_info->frag_stride);
1069                 byte_cnt -= frag_consumed_bytes;
1070                 frag_headlen = 0;
1071                 frag_info++;
1072                 wi++;
1073         }
1074
1075         /* copy header */
1076         mlx5e_copy_skb_header(rq->pdev, skb, head_wi->di, head_wi->offset, headlen);
1077         /* skb linear part was allocated with headlen and aligned to long */
1078         skb->tail += headlen;
1079         skb->len  += headlen;
1080
1081         return skb;
1082 }
1083
1084 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1085 {
1086         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1087         struct mlx5e_wqe_frag_info *wi;
1088         struct sk_buff *skb;
1089         u32 cqe_bcnt;
1090         u16 ci;
1091
1092         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1093         wi       = get_frag(rq, ci);
1094         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1095
1096         skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1097                               mlx5e_skb_from_cqe_linear,
1098                               mlx5e_skb_from_cqe_nonlinear,
1099                               rq, cqe, wi, cqe_bcnt);
1100         if (!skb) {
1101                 /* probably for XDP */
1102                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1103                         /* do not return page to cache,
1104                          * it will be returned on XDP_TX completion.
1105                          */
1106                         goto wq_cyc_pop;
1107                 }
1108                 goto free_wqe;
1109         }
1110
1111         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1112         napi_gro_receive(rq->cq.napi, skb);
1113
1114 free_wqe:
1115         mlx5e_free_rx_wqe(rq, wi, true);
1116 wq_cyc_pop:
1117         mlx5_wq_cyc_pop(wq);
1118 }
1119
1120 #ifdef CONFIG_MLX5_ESWITCH
1121 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1122 {
1123         struct net_device *netdev = rq->netdev;
1124         struct mlx5e_priv *priv = netdev_priv(netdev);
1125         struct mlx5e_rep_priv *rpriv  = priv->ppriv;
1126         struct mlx5_eswitch_rep *rep = rpriv->rep;
1127         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1128         struct mlx5e_wqe_frag_info *wi;
1129         struct sk_buff *skb;
1130         u32 cqe_bcnt;
1131         u16 ci;
1132
1133         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1134         wi       = get_frag(rq, ci);
1135         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1136
1137         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1138         if (!skb) {
1139                 /* probably for XDP */
1140                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1141                         /* do not return page to cache,
1142                          * it will be returned on XDP_TX completion.
1143                          */
1144                         goto wq_cyc_pop;
1145                 }
1146                 goto free_wqe;
1147         }
1148
1149         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1150
1151         if (rep->vlan && skb_vlan_tag_present(skb))
1152                 skb_vlan_pop(skb);
1153
1154         napi_gro_receive(rq->cq.napi, skb);
1155
1156 free_wqe:
1157         mlx5e_free_rx_wqe(rq, wi, true);
1158 wq_cyc_pop:
1159         mlx5_wq_cyc_pop(wq);
1160 }
1161 #endif
1162
1163 struct sk_buff *
1164 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1165                                    u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1166 {
1167         u16 headlen = min_t(u16, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1168         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1169         u32 frag_offset    = head_offset + headlen;
1170         u32 byte_cnt       = cqe_bcnt - headlen;
1171         struct mlx5e_dma_info *head_di = di;
1172         struct sk_buff *skb;
1173
1174         skb = napi_alloc_skb(rq->cq.napi,
1175                              ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1176         if (unlikely(!skb)) {
1177                 rq->stats->buff_alloc_err++;
1178                 return NULL;
1179         }
1180
1181         prefetchw(skb->data);
1182
1183         if (unlikely(frag_offset >= PAGE_SIZE)) {
1184                 di++;
1185                 frag_offset -= PAGE_SIZE;
1186         }
1187
1188         while (byte_cnt) {
1189                 u32 pg_consumed_bytes =
1190                         min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
1191                 unsigned int truesize =
1192                         ALIGN(pg_consumed_bytes, BIT(rq->mpwqe.log_stride_sz));
1193
1194                 mlx5e_add_skb_frag(rq, skb, di, frag_offset,
1195                                    pg_consumed_bytes, truesize);
1196                 byte_cnt -= pg_consumed_bytes;
1197                 frag_offset = 0;
1198                 di++;
1199         }
1200         /* copy header */
1201         mlx5e_copy_skb_header(rq->pdev, skb, head_di, head_offset, headlen);
1202         /* skb linear part was allocated with headlen and aligned to long */
1203         skb->tail += headlen;
1204         skb->len  += headlen;
1205
1206         return skb;
1207 }
1208
1209 struct sk_buff *
1210 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1211                                 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1212 {
1213         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1214         u16 rx_headroom = rq->buff.headroom;
1215         u32 cqe_bcnt32 = cqe_bcnt;
1216         struct sk_buff *skb;
1217         void *va, *data;
1218         u32 frag_size;
1219         bool consumed;
1220
1221         /* Check packet size. Note LRO doesn't use linear SKB */
1222         if (unlikely(cqe_bcnt > rq->hw_mtu)) {
1223                 rq->stats->oversize_pkts_sw_drop++;
1224                 return NULL;
1225         }
1226
1227         va             = page_address(di->page) + head_offset;
1228         data           = va + rx_headroom;
1229         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1230
1231         dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset,
1232                                       frag_size, DMA_FROM_DEVICE);
1233         prefetchw(va); /* xdp_frame data area */
1234         prefetch(data);
1235
1236         rcu_read_lock();
1237         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt32);
1238         rcu_read_unlock();
1239         if (consumed) {
1240                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags))
1241                         __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */
1242                 return NULL; /* page/packet was consumed by XDP */
1243         }
1244
1245         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32);
1246         if (unlikely(!skb))
1247                 return NULL;
1248
1249         /* queue up for recycling/reuse */
1250         page_ref_inc(di->page);
1251
1252         return skb;
1253 }
1254
1255 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1256 {
1257         u16 cstrides       = mpwrq_get_cqe_consumed_strides(cqe);
1258         u16 wqe_id         = be16_to_cpu(cqe->wqe_id);
1259         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1260         u16 stride_ix      = mpwrq_get_cqe_stride_index(cqe);
1261         u32 wqe_offset     = stride_ix << rq->mpwqe.log_stride_sz;
1262         u32 head_offset    = wqe_offset & (PAGE_SIZE - 1);
1263         u32 page_idx       = wqe_offset >> PAGE_SHIFT;
1264         struct mlx5e_rx_wqe_ll *wqe;
1265         struct mlx5_wq_ll *wq;
1266         struct sk_buff *skb;
1267         u16 cqe_bcnt;
1268
1269         wi->consumed_strides += cstrides;
1270
1271         if (unlikely(get_cqe_opcode(cqe) != MLX5_CQE_RESP_SEND)) {
1272                 rq->stats->wqe_err++;
1273                 goto mpwrq_cqe_out;
1274         }
1275
1276         if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1277                 struct mlx5e_rq_stats *stats = rq->stats;
1278
1279                 stats->mpwqe_filler_cqes++;
1280                 stats->mpwqe_filler_strides += cstrides;
1281                 goto mpwrq_cqe_out;
1282         }
1283
1284         cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1285
1286         skb = INDIRECT_CALL_2(rq->mpwqe.skb_from_cqe_mpwrq,
1287                               mlx5e_skb_from_cqe_mpwrq_linear,
1288                               mlx5e_skb_from_cqe_mpwrq_nonlinear,
1289                               rq, wi, cqe_bcnt, head_offset, page_idx);
1290         if (!skb)
1291                 goto mpwrq_cqe_out;
1292
1293         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1294         napi_gro_receive(rq->cq.napi, skb);
1295
1296 mpwrq_cqe_out:
1297         if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1298                 return;
1299
1300         wq  = &rq->mpwqe.wq;
1301         wqe = mlx5_wq_ll_get_wqe(wq, wqe_id);
1302         mlx5e_free_rx_mpwqe(rq, wi, true);
1303         mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1304 }
1305
1306 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1307 {
1308         struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1309         struct mlx5_cqwq *cqwq = &cq->wq;
1310         struct mlx5_cqe64 *cqe;
1311         int work_done = 0;
1312
1313         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
1314                 return 0;
1315
1316         if (rq->cqd.left)
1317                 work_done += mlx5e_decompress_cqes_cont(rq, cqwq, 0, budget);
1318
1319         cqe = mlx5_cqwq_get_cqe(cqwq);
1320         if (!cqe) {
1321                 if (unlikely(work_done))
1322                         goto out;
1323                 return 0;
1324         }
1325
1326         do {
1327                 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1328                         work_done +=
1329                                 mlx5e_decompress_cqes_start(rq, cqwq,
1330                                                             budget - work_done);
1331                         continue;
1332                 }
1333
1334                 mlx5_cqwq_pop(cqwq);
1335
1336                 rq->handle_rx_cqe(rq, cqe);
1337         } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(cqwq)));
1338
1339 out:
1340         if (rq->xdp_prog)
1341                 mlx5e_xdp_rx_poll_complete(rq);
1342
1343         mlx5_cqwq_update_db_record(cqwq);
1344
1345         /* ensure cq space is freed before enabling more cqes */
1346         wmb();
1347
1348         return work_done;
1349 }
1350
1351 #ifdef CONFIG_MLX5_CORE_IPOIB
1352
1353 #define MLX5_IB_GRH_DGID_OFFSET 24
1354 #define MLX5_GID_SIZE           16
1355
1356 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1357                                          struct mlx5_cqe64 *cqe,
1358                                          u32 cqe_bcnt,
1359                                          struct sk_buff *skb)
1360 {
1361         struct hwtstamp_config *tstamp;
1362         struct mlx5e_rq_stats *stats;
1363         struct net_device *netdev;
1364         struct mlx5e_priv *priv;
1365         char *pseudo_header;
1366         u32 qpn;
1367         u8 *dgid;
1368         u8 g;
1369
1370         qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1371         netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1372
1373         /* No mapping present, cannot process SKB. This might happen if a child
1374          * interface is going down while having unprocessed CQEs on parent RQ
1375          */
1376         if (unlikely(!netdev)) {
1377                 /* TODO: add drop counters support */
1378                 skb->dev = NULL;
1379                 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1380                 return;
1381         }
1382
1383         priv = mlx5i_epriv(netdev);
1384         tstamp = &priv->tstamp;
1385         stats = &priv->channel_stats[rq->ix].rq;
1386
1387         g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
1388         dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1389         if ((!g) || dgid[0] != 0xff)
1390                 skb->pkt_type = PACKET_HOST;
1391         else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1392                 skb->pkt_type = PACKET_BROADCAST;
1393         else
1394                 skb->pkt_type = PACKET_MULTICAST;
1395
1396         /* TODO: IB/ipoib: Allow mcast packets from other VFs
1397          * 68996a6e760e5c74654723eeb57bf65628ae87f4
1398          */
1399
1400         skb_pull(skb, MLX5_IB_GRH_BYTES);
1401
1402         skb->protocol = *((__be16 *)(skb->data));
1403
1404         if (netdev->features & NETIF_F_RXCSUM) {
1405                 skb->ip_summed = CHECKSUM_COMPLETE;
1406                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1407                 stats->csum_complete++;
1408         } else {
1409                 skb->ip_summed = CHECKSUM_NONE;
1410                 stats->csum_none++;
1411         }
1412
1413         if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1414                 skb_hwtstamps(skb)->hwtstamp =
1415                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1416
1417         skb_record_rx_queue(skb, rq->ix);
1418
1419         if (likely(netdev->features & NETIF_F_RXHASH))
1420                 mlx5e_skb_set_hash(cqe, skb);
1421
1422         /* 20 bytes of ipoib header and 4 for encap existing */
1423         pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1424         memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1425         skb_reset_mac_header(skb);
1426         skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1427
1428         skb->dev = netdev;
1429
1430         stats->packets++;
1431         stats->bytes += cqe_bcnt;
1432 }
1433
1434 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1435 {
1436         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1437         struct mlx5e_wqe_frag_info *wi;
1438         struct sk_buff *skb;
1439         u32 cqe_bcnt;
1440         u16 ci;
1441
1442         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1443         wi       = get_frag(rq, ci);
1444         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1445
1446         skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1447                               mlx5e_skb_from_cqe_linear,
1448                               mlx5e_skb_from_cqe_nonlinear,
1449                               rq, cqe, wi, cqe_bcnt);
1450         if (!skb)
1451                 goto wq_free_wqe;
1452
1453         mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1454         if (unlikely(!skb->dev)) {
1455                 dev_kfree_skb_any(skb);
1456                 goto wq_free_wqe;
1457         }
1458         napi_gro_receive(rq->cq.napi, skb);
1459
1460 wq_free_wqe:
1461         mlx5e_free_rx_wqe(rq, wi, true);
1462         mlx5_wq_cyc_pop(wq);
1463 }
1464
1465 #endif /* CONFIG_MLX5_CORE_IPOIB */
1466
1467 #ifdef CONFIG_MLX5_EN_IPSEC
1468
1469 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1470 {
1471         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1472         struct mlx5e_wqe_frag_info *wi;
1473         struct sk_buff *skb;
1474         u32 cqe_bcnt;
1475         u16 ci;
1476
1477         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1478         wi       = get_frag(rq, ci);
1479         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1480
1481         skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1482                               mlx5e_skb_from_cqe_linear,
1483                               mlx5e_skb_from_cqe_nonlinear,
1484                               rq, cqe, wi, cqe_bcnt);
1485         if (unlikely(!skb)) {
1486                 /* a DROP, save the page-reuse checks */
1487                 mlx5e_free_rx_wqe(rq, wi, true);
1488                 goto wq_cyc_pop;
1489         }
1490         skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb, &cqe_bcnt);
1491         if (unlikely(!skb)) {
1492                 mlx5e_free_rx_wqe(rq, wi, true);
1493                 goto wq_cyc_pop;
1494         }
1495
1496         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1497         napi_gro_receive(rq->cq.napi, skb);
1498
1499         mlx5e_free_rx_wqe(rq, wi, true);
1500 wq_cyc_pop:
1501         mlx5_wq_cyc_pop(wq);
1502 }
1503
1504 #endif /* CONFIG_MLX5_EN_IPSEC */