drivers/net/ethernet/mellanox/mlx5/core/en_rx.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/prefetch.h>
  34 #include <linux/ip.h>
  35 #include <linux/ipv6.h>
  36 #include <linux/tcp.h>
  37 #include <linux/indirect_call_wrapper.h>
  38 #include <net/ip6_checksum.h>
  39 #include <net/page_pool.h>
  40 #include <net/inet_ecn.h>
  41 #include "en.h"
  42 #include "en_tc.h"
  43 #include "eswitch.h"
  44 #include "en_rep.h"
  45 #include "ipoib/ipoib.h"
  46 #include "en_accel/ipsec_rxtx.h"
  47 #include "en_accel/tls_rxtx.h"
  48 #include "lib/clock.h"
  49 #include "en/xdp.h"
  50 #include "en/xsk/rx.h"
  51 #include "en/health.h"
  52
  53 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
  54 {
  55         return config->rx_filter == HWTSTAMP_FILTER_ALL;
  56 }
  57
  58 static inline void mlx5e_read_cqe_slot(struct mlx5_cqwq *wq,
  59                                        u32 cqcc, void *data)
  60 {
  61         u32 ci = mlx5_cqwq_ctr2ix(wq, cqcc);
  62
  63         memcpy(data, mlx5_cqwq_get_wqe(wq, ci), sizeof(struct mlx5_cqe64));
  64 }
  65
  66 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
  67                                          struct mlx5_cqwq *wq,
  68                                          u32 cqcc)
  69 {
  70         struct mlx5e_cq_decomp *cqd = &rq->cqd;
  71         struct mlx5_cqe64 *title = &cqd->title;
  72
  73         mlx5e_read_cqe_slot(wq, cqcc, title);
  74         cqd->left        = be32_to_cpu(title->byte_cnt);
  75         cqd->wqe_counter = be16_to_cpu(title->wqe_counter);
  76         rq->stats->cqe_compress_blks++;
  77 }
  78
  79 static inline void mlx5e_read_mini_arr_slot(struct mlx5_cqwq *wq,
  80                                             struct mlx5e_cq_decomp *cqd,
  81                                             u32 cqcc)
  82 {
  83         mlx5e_read_cqe_slot(wq, cqcc, cqd->mini_arr);
  84         cqd->mini_arr_idx = 0;
  85 }
  86
  87 static inline void mlx5e_cqes_update_owner(struct mlx5_cqwq *wq, int n)
  88 {
  89         u32 cqcc   = wq->cc;
  90         u8  op_own = mlx5_cqwq_get_ctr_wrap_cnt(wq, cqcc) & 1;
  91         u32 ci     = mlx5_cqwq_ctr2ix(wq, cqcc);
  92         u32 wq_sz  = mlx5_cqwq_get_size(wq);
  93         u32 ci_top = min_t(u32, wq_sz, ci + n);
  94
  95         for (; ci < ci_top; ci++, n--) {
  96                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci);
  97
  98                 cqe->op_own = op_own;
  99         }
 100
 101         if (unlikely(ci == wq_sz)) {
 102                 op_own = !op_own;
 103                 for (ci = 0; ci < n; ci++) {
 104                         struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci);
 105
 106                         cqe->op_own = op_own;
 107                 }
 108         }
 109 }
 110
 111 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
 112                                         struct mlx5_cqwq *wq,
 113                                         u32 cqcc)
 114 {
 115         struct mlx5e_cq_decomp *cqd = &rq->cqd;
 116         struct mlx5_mini_cqe8 *mini_cqe = &cqd->mini_arr[cqd->mini_arr_idx];
 117         struct mlx5_cqe64 *title = &cqd->title;
 118
 119         title->byte_cnt     = mini_cqe->byte_cnt;
 120         title->check_sum    = mini_cqe->checksum;
 121         title->op_own      &= 0xf0;
 122         title->op_own      |= 0x01 & (cqcc >> wq->fbc.log_sz);
 123         title->wqe_counter  = cpu_to_be16(cqd->wqe_counter);
 124
 125         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 126                 cqd->wqe_counter += mpwrq_get_cqe_consumed_strides(title);
 127         else
 128                 cqd->wqe_counter =
 129                         mlx5_wq_cyc_ctr2ix(&rq->wqe.wq, cqd->wqe_counter + 1);
 130 }
 131
 132 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
 133                                                 struct mlx5_cqwq *wq,
 134                                                 u32 cqcc)
 135 {
 136         struct mlx5e_cq_decomp *cqd = &rq->cqd;
 137
 138         mlx5e_decompress_cqe(rq, wq, cqcc);
 139         cqd->title.rss_hash_type   = 0;
 140         cqd->title.rss_hash_result = 0;
 141 }
 142
 143 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
 144                                              struct mlx5_cqwq *wq,
 145                                              int update_owner_only,
 146                                              int budget_rem)
 147 {
 148         struct mlx5e_cq_decomp *cqd = &rq->cqd;
 149         u32 cqcc = wq->cc + update_owner_only;
 150         u32 cqe_count;
 151         u32 i;
 152
 153         cqe_count = min_t(u32, cqd->left, budget_rem);
 154
 155         for (i = update_owner_only; i < cqe_count;
 156              i++, cqd->mini_arr_idx++, cqcc++) {
 157                 if (cqd->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
 158                         mlx5e_read_mini_arr_slot(wq, cqd, cqcc);
 159
 160                 mlx5e_decompress_cqe_no_hash(rq, wq, cqcc);
 161                 INDIRECT_CALL_2(rq->handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq,
 162                                 mlx5e_handle_rx_cqe, rq, &cqd->title);
 163         }
 164         mlx5e_cqes_update_owner(wq, cqcc - wq->cc);
 165         wq->cc = cqcc;
 166         cqd->left -= cqe_count;
 167         rq->stats->cqe_compress_pkts += cqe_count;
 168
 169         return cqe_count;
 170 }
 171
 172 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
 173                                               struct mlx5_cqwq *wq,
 174                                               int budget_rem)
 175 {
 176         struct mlx5e_cq_decomp *cqd = &rq->cqd;
 177         u32 cc = wq->cc;
 178
 179         mlx5e_read_title_slot(rq, wq, cc);
 180         mlx5e_read_mini_arr_slot(wq, cqd, cc + 1);
 181         mlx5e_decompress_cqe(rq, wq, cc);
 182         INDIRECT_CALL_2(rq->handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq,
 183                         mlx5e_handle_rx_cqe, rq, &cqd->title);
 184         cqd->mini_arr_idx++;
 185
 186         return mlx5e_decompress_cqes_cont(rq, wq, 1, budget_rem) - 1;
 187 }
 188
 189 static inline bool mlx5e_page_is_reserved(struct page *page)
 190 {
 191         return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
 192 }
 193
 194 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
 195                                       struct mlx5e_dma_info *dma_info)
 196 {
 197         struct mlx5e_page_cache *cache = &rq->page_cache;
 198         u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
 199         struct mlx5e_rq_stats *stats = rq->stats;
 200
 201         if (tail_next == cache->head) {
 202                 stats->cache_full++;
 203                 return false;
 204         }
 205
 206         if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
 207                 stats->cache_waive++;
 208                 return false;
 209         }
 210
 211         cache->page_cache[cache->tail] = *dma_info;
 212         cache->tail = tail_next;
 213         return true;
 214 }
 215
 216 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
 217                                       struct mlx5e_dma_info *dma_info)
 218 {
 219         struct mlx5e_page_cache *cache = &rq->page_cache;
 220         struct mlx5e_rq_stats *stats = rq->stats;
 221
 222         if (unlikely(cache->head == cache->tail)) {
 223                 stats->cache_empty++;
 224                 return false;
 225         }
 226
 227         if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
 228                 stats->cache_busy++;
 229                 return false;
 230         }
 231
 232         *dma_info = cache->page_cache[cache->head];
 233         cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
 234         stats->cache_reuse++;
 235
 236         dma_sync_single_for_device(rq->pdev, dma_info->addr,
 237                                    PAGE_SIZE,
 238                                    DMA_FROM_DEVICE);
 239         return true;
 240 }
 241
 242 static inline int mlx5e_page_alloc_pool(struct mlx5e_rq *rq,
 243                                         struct mlx5e_dma_info *dma_info)
 244 {
 245         if (mlx5e_rx_cache_get(rq, dma_info))
 246                 return 0;
 247
 248         dma_info->page = page_pool_dev_alloc_pages(rq->page_pool);
 249         if (unlikely(!dma_info->page))
 250                 return -ENOMEM;
 251
 252         dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
 253                                       PAGE_SIZE, rq->buff.map_dir);
 254         if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
 255                 page_pool_recycle_direct(rq->page_pool, dma_info->page);
 256                 dma_info->page = NULL;
 257                 return -ENOMEM;
 258         }
 259
 260         return 0;
 261 }
 262
 263 static inline int mlx5e_page_alloc(struct mlx5e_rq *rq,
 264                                    struct mlx5e_dma_info *dma_info)
 265 {
 266         if (rq->umem)
 267                 return mlx5e_xsk_page_alloc_umem(rq, dma_info);
 268         else
 269                 return mlx5e_page_alloc_pool(rq, dma_info);
 270 }
 271
 272 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info)
 273 {
 274         dma_unmap_page(rq->pdev, dma_info->addr, PAGE_SIZE, rq->buff.map_dir);
 275 }
 276
 277 void mlx5e_page_release_dynamic(struct mlx5e_rq *rq,
 278                                 struct mlx5e_dma_info *dma_info,
 279                                 bool recycle)
 280 {
 281         if (likely(recycle)) {
 282                 if (mlx5e_rx_cache_put(rq, dma_info))
 283                         return;
 284
 285                 mlx5e_page_dma_unmap(rq, dma_info);
 286                 page_pool_recycle_direct(rq->page_pool, dma_info->page);
 287         } else {
 288                 mlx5e_page_dma_unmap(rq, dma_info);
 289                 page_pool_release_page(rq->page_pool, dma_info->page);
 290                 put_page(dma_info->page);
 291         }
 292 }
 293
 294 static inline void mlx5e_page_release(struct mlx5e_rq *rq,
 295                                       struct mlx5e_dma_info *dma_info,
 296                                       bool recycle)
 297 {
 298         if (rq->umem)
 299                 /* The `recycle` parameter is ignored, and the page is always
 300                  * put into the Reuse Ring, because there is no way to return
 301                  * the page to the userspace when the interface goes down.
 302                  */
 303                 mlx5e_xsk_page_release(rq, dma_info);
 304         else
 305                 mlx5e_page_release_dynamic(rq, dma_info, recycle);
 306 }
 307
 308 static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq,
 309                                     struct mlx5e_wqe_frag_info *frag)
 310 {
 311         int err = 0;
 312
 313         if (!frag->offset)
 314                 /* On first frag (offset == 0), replenish page (dma_info actually).
 315                  * Other frags that point to the same dma_info (with a different
 316                  * offset) should just use the new one without replenishing again
 317                  * by themselves.
 318                  */
 319                 err = mlx5e_page_alloc(rq, frag->di);
 320
 321         return err;
 322 }
 323
 324 static inline void mlx5e_put_rx_frag(struct mlx5e_rq *rq,
 325                                      struct mlx5e_wqe_frag_info *frag,
 326                                      bool recycle)
 327 {
 328         if (frag->last_in_page)
 329                 mlx5e_page_release(rq, frag->di, recycle);
 330 }
 331
 332 static inline struct mlx5e_wqe_frag_info *get_frag(struct mlx5e_rq *rq, u16 ix)
 333 {
 334         return &rq->wqe.frags[ix << rq->wqe.info.log_num_frags];
 335 }
 336
 337 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe_cyc *wqe,
 338                               u16 ix)
 339 {
 340         struct mlx5e_wqe_frag_info *frag = get_frag(rq, ix);
 341         int err;
 342         int i;
 343
 344         for (i = 0; i < rq->wqe.info.num_frags; i++, frag++) {
 345                 err = mlx5e_get_rx_frag(rq, frag);
 346                 if (unlikely(err))
 347                         goto free_frags;
 348
 349                 wqe->data[i].addr = cpu_to_be64(frag->di->addr +
 350                                                 frag->offset + rq->buff.headroom);
 351         }
 352
 353         return 0;
 354
 355 free_frags:
 356         while (--i >= 0)
 357                 mlx5e_put_rx_frag(rq, --frag, true);
 358
 359         return err;
 360 }
 361
 362 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
 363                                      struct mlx5e_wqe_frag_info *wi,
 364                                      bool recycle)
 365 {
 366         int i;
 367
 368         for (i = 0; i < rq->wqe.info.num_frags; i++, wi++)
 369                 mlx5e_put_rx_frag(rq, wi, recycle);
 370 }
 371
 372 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
 373 {
 374         struct mlx5e_wqe_frag_info *wi = get_frag(rq, ix);
 375
 376         mlx5e_free_rx_wqe(rq, wi, false);
 377 }
 378
 379 static int mlx5e_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, u8 wqe_bulk)
 380 {
 381         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 382         int err;
 383         int i;
 384
 385         if (rq->umem) {
 386                 int pages_desired = wqe_bulk << rq->wqe.info.log_num_frags;
 387
 388                 if (unlikely(!mlx5e_xsk_pages_enough_umem(rq, pages_desired)))
 389                         return -ENOMEM;
 390         }
 391
 392         for (i = 0; i < wqe_bulk; i++) {
 393                 struct mlx5e_rx_wqe_cyc *wqe = mlx5_wq_cyc_get_wqe(wq, ix + i);
 394
 395                 err = mlx5e_alloc_rx_wqe(rq, wqe, ix + i);
 396                 if (unlikely(err))
 397                         goto free_wqes;
 398         }
 399
 400         return 0;
 401
 402 free_wqes:
 403         while (--i >= 0)
 404                 mlx5e_dealloc_rx_wqe(rq, ix + i);
 405
 406         return err;
 407 }
 408
 409 static inline void
 410 mlx5e_add_skb_frag(struct mlx5e_rq *rq, struct sk_buff *skb,
 411                    struct mlx5e_dma_info *di, u32 frag_offset, u32 len,
 412                    unsigned int truesize)
 413 {
 414         dma_sync_single_for_cpu(rq->pdev,
 415                                 di->addr + frag_offset,
 416                                 len, DMA_FROM_DEVICE);
 417         page_ref_inc(di->page);
 418         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
 419                         di->page, frag_offset, len, truesize);
 420 }
 421
 422 static inline void
 423 mlx5e_copy_skb_header(struct device *pdev, struct sk_buff *skb,
 424                       struct mlx5e_dma_info *dma_info,
 425                       int offset_from, u32 headlen)
 426 {
 427         const void *from = page_address(dma_info->page) + offset_from;
 428         /* Aligning len to sizeof(long) optimizes memcpy performance */
 429         unsigned int len = ALIGN(headlen, sizeof(long));
 430
 431         dma_sync_single_for_cpu(pdev, dma_info->addr + offset_from, len,
 432                                 DMA_FROM_DEVICE);
 433         skb_copy_to_linear_data(skb, from, len);
 434 }
 435
 436 static void
 437 mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, bool recycle)
 438 {
 439         bool no_xdp_xmit;
 440         struct mlx5e_dma_info *dma_info = wi->umr.dma_info;
 441         int i;
 442
 443         /* A common case for AF_XDP. */
 444         if (bitmap_full(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE))
 445                 return;
 446
 447         no_xdp_xmit = bitmap_empty(wi->xdp_xmit_bitmap,
 448                                    MLX5_MPWRQ_PAGES_PER_WQE);
 449
 450         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++)
 451                 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap))
 452                         mlx5e_page_release(rq, &dma_info[i], recycle);
 453 }
 454
 455 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq, u8 n)
 456 {
 457         struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 458
 459         do {
 460                 u16 next_wqe_index = mlx5_wq_ll_get_wqe_next_ix(wq, wq->head);
 461
 462                 mlx5_wq_ll_push(wq, next_wqe_index);
 463         } while (--n);
 464
 465         /* ensure wqes are visible to device before updating doorbell record */
 466         dma_wmb();
 467
 468         mlx5_wq_ll_update_db_record(wq);
 469 }
 470
 471 static inline void mlx5e_fill_icosq_frag_edge(struct mlx5e_icosq *sq,
 472                                               struct mlx5_wq_cyc *wq,
 473                                               u16 pi, u16 nnops)
 474 {
 475         struct mlx5e_sq_wqe_info *edge_wi, *wi = &sq->db.ico_wqe[pi];
 476
 477         edge_wi = wi + nnops;
 478
 479         /* fill sq frag edge with nops to avoid wqe wrapping two pages */
 480         for (; wi < edge_wi; wi++) {
 481                 wi->opcode = MLX5_OPCODE_NOP;
 482                 wi->num_wqebbs = 1;
 483                 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
 484         }
 485 }
 486
 487 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 488 {
 489         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 490         struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
 491         struct mlx5e_icosq *sq = &rq->channel->icosq;
 492         struct mlx5_wq_cyc *wq = &sq->wq;
 493         struct mlx5e_umr_wqe *umr_wqe;
 494         u16 xlt_offset = ix << (MLX5E_LOG_ALIGNED_MPWQE_PPW - 1);
 495         u16 pi, contig_wqebbs_room;
 496         int err;
 497         int i;
 498
 499         if (rq->umem &&
 500             unlikely(!mlx5e_xsk_pages_enough_umem(rq, MLX5_MPWRQ_PAGES_PER_WQE))) {
 501                 err = -ENOMEM;
 502                 goto err;
 503         }
 504
 505         pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
 506         contig_wqebbs_room = mlx5_wq_cyc_get_contig_wqebbs(wq, pi);
 507         if (unlikely(contig_wqebbs_room < MLX5E_UMR_WQEBBS)) {
 508                 mlx5e_fill_icosq_frag_edge(sq, wq, pi, contig_wqebbs_room);
 509                 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
 510         }
 511
 512         umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi);
 513         memcpy(umr_wqe, &rq->mpwqe.umr_wqe, offsetof(struct mlx5e_umr_wqe, inline_mtts));
 514
 515         for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
 516                 err = mlx5e_page_alloc(rq, dma_info);
 517                 if (unlikely(err))
 518                         goto err_unmap;
 519                 umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
 520         }
 521
 522         bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
 523         wi->consumed_strides = 0;
 524
 525         umr_wqe->ctrl.opmod_idx_opcode =
 526                 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
 527                             MLX5_OPCODE_UMR);
 528         umr_wqe->uctrl.xlt_offset = cpu_to_be16(xlt_offset);
 529
 530         sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
 531         sq->db.ico_wqe[pi].num_wqebbs = MLX5E_UMR_WQEBBS;
 532         sq->db.ico_wqe[pi].umr.rq = rq;
 533         sq->pc += MLX5E_UMR_WQEBBS;
 534
 535         sq->doorbell_cseg = &umr_wqe->ctrl;
 536
 537         return 0;
 538
 539 err_unmap:
 540         while (--i >= 0) {
 541                 dma_info--;
 542                 mlx5e_page_release(rq, dma_info, true);
 543         }
 544
 545 err:
 546         rq->stats->buff_alloc_err++;
 547
 548         return err;
 549 }
 550
 551 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
 552 {
 553         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 554         /* Don't recycle, this function is called on rq/netdev close */
 555         mlx5e_free_rx_mpwqe(rq, wi, false);
 556 }
 557
 558 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
 559 {
 560         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 561         u8 wqe_bulk;
 562         int err;
 563
 564         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
 565                 return false;
 566
 567         wqe_bulk = rq->wqe.info.wqe_bulk;
 568
 569         if (mlx5_wq_cyc_missing(wq) < wqe_bulk)
 570                 return false;
 571
 572         do {
 573                 u16 head = mlx5_wq_cyc_get_head(wq);
 574
 575                 err = mlx5e_alloc_rx_wqes(rq, head, wqe_bulk);
 576                 if (unlikely(err)) {
 577                         rq->stats->buff_alloc_err++;
 578                         break;
 579                 }
 580
 581                 mlx5_wq_cyc_push_n(wq, wqe_bulk);
 582         } while (mlx5_wq_cyc_missing(wq) >= wqe_bulk);
 583
 584         /* ensure wqes are visible to device before updating doorbell record */
 585         dma_wmb();
 586
 587         mlx5_wq_cyc_update_db_record(wq);
 588
 589         return !!err;
 590 }
 591
 592 void mlx5e_poll_ico_cq(struct mlx5e_cq *cq)
 593 {
 594         struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
 595         struct mlx5_cqe64 *cqe;
 596         u16 sqcc;
 597         int i;
 598
 599         if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
 600                 return;
 601
 602         cqe = mlx5_cqwq_get_cqe(&cq->wq);
 603         if (likely(!cqe))
 604                 return;
 605
 606         /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
 607          * otherwise a cq overrun may occur
 608          */
 609         sqcc = sq->cc;
 610
 611         i = 0;
 612         do {
 613                 u16 wqe_counter;
 614                 bool last_wqe;
 615
 616                 mlx5_cqwq_pop(&cq->wq);
 617
 618                 wqe_counter = be16_to_cpu(cqe->wqe_counter);
 619
 620                 do {
 621                         struct mlx5e_sq_wqe_info *wi;
 622                         u16 ci;
 623
 624                         last_wqe = (sqcc == wqe_counter);
 625
 626                         ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
 627                         wi = &sq->db.ico_wqe[ci];
 628                         sqcc += wi->num_wqebbs;
 629
 630                         if (last_wqe && unlikely(get_cqe_opcode(cqe) != MLX5_CQE_REQ)) {
 631                                 netdev_WARN_ONCE(cq->channel->netdev,
 632                                                  "Bad OP in ICOSQ CQE: 0x%x\n",
 633                                                  get_cqe_opcode(cqe));
 634                                 if (!test_and_set_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state))
 635                                         queue_work(cq->channel->priv->wq, &sq->recover_work);
 636                                 break;
 637                         }
 638
 639                         if (likely(wi->opcode == MLX5_OPCODE_UMR))
 640                                 wi->umr.rq->mpwqe.umr_completed++;
 641                         else if (unlikely(wi->opcode != MLX5_OPCODE_NOP))
 642                                 netdev_WARN_ONCE(cq->channel->netdev,
 643                                                  "Bad OPCODE in ICOSQ WQE info: 0x%x\n",
 644                                                  wi->opcode);
 645
 646                 } while (!last_wqe);
 647
 648         } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
 649
 650         sq->cc = sqcc;
 651
 652         mlx5_cqwq_update_db_record(&cq->wq);
 653 }
 654
 655 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
 656 {
 657         struct mlx5e_icosq *sq = &rq->channel->icosq;
 658         struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 659         u8  umr_completed = rq->mpwqe.umr_completed;
 660         int alloc_err = 0;
 661         u8  missing, i;
 662         u16 head;
 663
 664         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
 665                 return false;
 666
 667         if (umr_completed) {
 668                 mlx5e_post_rx_mpwqe(rq, umr_completed);
 669                 rq->mpwqe.umr_in_progress -= umr_completed;
 670                 rq->mpwqe.umr_completed = 0;
 671         }
 672
 673         missing = mlx5_wq_ll_missing(wq) - rq->mpwqe.umr_in_progress;
 674
 675         if (unlikely(rq->mpwqe.umr_in_progress > rq->mpwqe.umr_last_bulk))
 676                 rq->stats->congst_umr++;
 677
 678 #define UMR_WQE_BULK (2)
 679         if (likely(missing < UMR_WQE_BULK))
 680                 return false;
 681
 682         head = rq->mpwqe.actual_wq_head;
 683         i = missing;
 684         do {
 685                 alloc_err = mlx5e_alloc_rx_mpwqe(rq, head);
 686
 687                 if (unlikely(alloc_err))
 688                         break;
 689                 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
 690         } while (--i);
 691
 692         rq->mpwqe.umr_last_bulk    = missing - i;
 693         if (sq->doorbell_cseg) {
 694                 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, sq->doorbell_cseg);
 695                 sq->doorbell_cseg = NULL;
 696         }
 697
 698         rq->mpwqe.umr_in_progress += rq->mpwqe.umr_last_bulk;
 699         rq->mpwqe.actual_wq_head   = head;
 700
 701         /* If XSK Fill Ring doesn't have enough frames, report the error, so
 702          * that one of the actions can be performed:
 703          * 1. If need_wakeup is used, signal that the application has to kick
 704          * the driver when it refills the Fill Ring.
 705          * 2. Otherwise, busy poll by rescheduling the NAPI poll.
 706          */
 707         if (unlikely(alloc_err == -ENOMEM && rq->umem))
 708                 return true;
 709
 710         return false;
 711 }
 712
 713 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
 714 {
 715         u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
 716         u8 tcp_ack     = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
 717                          (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
 718
 719         tcp->check                      = 0;
 720         tcp->psh                        = get_cqe_lro_tcppsh(cqe);
 721
 722         if (tcp_ack) {
 723                 tcp->ack                = 1;
 724                 tcp->ack_seq            = cqe->lro_ack_seq_num;
 725                 tcp->window             = cqe->lro_tcp_win;
 726         }
 727 }
 728
 729 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
 730                                  u32 cqe_bcnt)
 731 {
 732         struct ethhdr   *eth = (struct ethhdr *)(skb->data);
 733         struct tcphdr   *tcp;
 734         int network_depth = 0;
 735         __wsum check;
 736         __be16 proto;
 737         u16 tot_len;
 738         void *ip_p;
 739
 740         proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
 741
 742         tot_len = cqe_bcnt - network_depth;
 743         ip_p = skb->data + network_depth;
 744
 745         if (proto == htons(ETH_P_IP)) {
 746                 struct iphdr *ipv4 = ip_p;
 747
 748                 tcp = ip_p + sizeof(struct iphdr);
 749                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
 750
 751                 ipv4->ttl               = cqe->lro_min_ttl;
 752                 ipv4->tot_len           = cpu_to_be16(tot_len);
 753                 ipv4->check             = 0;
 754                 ipv4->check             = ip_fast_csum((unsigned char *)ipv4,
 755                                                        ipv4->ihl);
 756
 757                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 758                 check = csum_partial(tcp, tcp->doff * 4,
 759                                      csum_unfold((__force __sum16)cqe->check_sum));
 760                 /* Almost done, don't forget the pseudo header */
 761                 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
 762                                                tot_len - sizeof(struct iphdr),
 763                                                IPPROTO_TCP, check);
 764         } else {
 765                 u16 payload_len = tot_len - sizeof(struct ipv6hdr);
 766                 struct ipv6hdr *ipv6 = ip_p;
 767
 768                 tcp = ip_p + sizeof(struct ipv6hdr);
 769                 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
 770
 771                 ipv6->hop_limit         = cqe->lro_min_ttl;
 772                 ipv6->payload_len       = cpu_to_be16(payload_len);
 773
 774                 mlx5e_lro_update_tcp_hdr(cqe, tcp);
 775                 check = csum_partial(tcp, tcp->doff * 4,
 776                                      csum_unfold((__force __sum16)cqe->check_sum));
 777                 /* Almost done, don't forget the pseudo header */
 778                 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
 779                                              IPPROTO_TCP, check);
 780         }
 781 }
 782
 783 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
 784                                       struct sk_buff *skb)
 785 {
 786         u8 cht = cqe->rss_hash_type;
 787         int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
 788                  (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
 789                                             PKT_HASH_TYPE_NONE;
 790         skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
 791 }
 792
 793 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth,
 794                                         __be16 *proto)
 795 {
 796         *proto = ((struct ethhdr *)skb->data)->h_proto;
 797         *proto = __vlan_get_protocol(skb, *proto, network_depth);
 798
 799         if (*proto == htons(ETH_P_IP))
 800                 return pskb_may_pull(skb, *network_depth + sizeof(struct iphdr));
 801
 802         if (*proto == htons(ETH_P_IPV6))
 803                 return pskb_may_pull(skb, *network_depth + sizeof(struct ipv6hdr));
 804
 805         return false;
 806 }
 807
 808 static inline void mlx5e_enable_ecn(struct mlx5e_rq *rq, struct sk_buff *skb)
 809 {
 810         int network_depth = 0;
 811         __be16 proto;
 812         void *ip;
 813         int rc;
 814
 815         if (unlikely(!is_last_ethertype_ip(skb, &network_depth, &proto)))
 816                 return;
 817
 818         ip = skb->data + network_depth;
 819         rc = ((proto == htons(ETH_P_IP)) ? IP_ECN_set_ce((struct iphdr *)ip) :
 820                                          IP6_ECN_set_ce(skb, (struct ipv6hdr *)ip));
 821
 822         rq->stats->ecn_mark += !!rc;
 823 }
 824
 825 static u8 get_ip_proto(struct sk_buff *skb, int network_depth, __be16 proto)
 826 {
 827         void *ip_p = skb->data + network_depth;
 828
 829         return (proto == htons(ETH_P_IP)) ? ((struct iphdr *)ip_p)->protocol :
 830                                             ((struct ipv6hdr *)ip_p)->nexthdr;
 831 }
 832
 833 #define short_frame(size) ((size) <= ETH_ZLEN + ETH_FCS_LEN)
 834
 835 #define MAX_PADDING 8
 836
 837 static void
 838 tail_padding_csum_slow(struct sk_buff *skb, int offset, int len,
 839                        struct mlx5e_rq_stats *stats)
 840 {
 841         stats->csum_complete_tail_slow++;
 842         skb->csum = csum_block_add(skb->csum,
 843                                    skb_checksum(skb, offset, len, 0),
 844                                    offset);
 845 }
 846
 847 static void
 848 tail_padding_csum(struct sk_buff *skb, int offset,
 849                   struct mlx5e_rq_stats *stats)
 850 {
 851         u8 tail_padding[MAX_PADDING];
 852         int len = skb->len - offset;
 853         void *tail;
 854
 855         if (unlikely(len > MAX_PADDING)) {
 856                 tail_padding_csum_slow(skb, offset, len, stats);
 857                 return;
 858         }
 859
 860         tail = skb_header_pointer(skb, offset, len, tail_padding);
 861         if (unlikely(!tail)) {
 862                 tail_padding_csum_slow(skb, offset, len, stats);
 863                 return;
 864         }
 865
 866         stats->csum_complete_tail++;
 867         skb->csum = csum_block_add(skb->csum, csum_partial(tail, len, 0), offset);
 868 }
 869
 870 static void
 871 mlx5e_skb_csum_fixup(struct sk_buff *skb, int network_depth, __be16 proto,
 872                      struct mlx5e_rq_stats *stats)
 873 {
 874         struct ipv6hdr *ip6;
 875         struct iphdr   *ip4;
 876         int pkt_len;
 877
 878         /* Fixup vlan headers, if any */
 879         if (network_depth > ETH_HLEN)
 880                 /* CQE csum is calculated from the IP header and does
 881                  * not cover VLAN headers (if present). This will add
 882                  * the checksum manually.
 883                  */
 884                 skb->csum = csum_partial(skb->data + ETH_HLEN,
 885                                          network_depth - ETH_HLEN,
 886                                          skb->csum);
 887
 888         /* Fixup tail padding, if any */
 889         switch (proto) {
 890         case htons(ETH_P_IP):
 891                 ip4 = (struct iphdr *)(skb->data + network_depth);
 892                 pkt_len = network_depth + ntohs(ip4->tot_len);
 893                 break;
 894         case htons(ETH_P_IPV6):
 895                 ip6 = (struct ipv6hdr *)(skb->data + network_depth);
 896                 pkt_len = network_depth + sizeof(*ip6) + ntohs(ip6->payload_len);
 897                 break;
 898         default:
 899                 return;
 900         }
 901
 902         if (likely(pkt_len >= skb->len))
 903                 return;
 904
 905         tail_padding_csum(skb, pkt_len, stats);
 906 }
 907
 908 static inline void mlx5e_handle_csum(struct net_device *netdev,
 909                                      struct mlx5_cqe64 *cqe,
 910                                      struct mlx5e_rq *rq,
 911                                      struct sk_buff *skb,
 912                                      bool   lro)
 913 {
 914         struct mlx5e_rq_stats *stats = rq->stats;
 915         int network_depth = 0;
 916         __be16 proto;
 917
 918         if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
 919                 goto csum_none;
 920
 921         if (lro) {
 922                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 923                 stats->csum_unnecessary++;
 924                 return;
 925         }
 926
 927         /* True when explicitly set via priv flag, or XDP prog is loaded */
 928         if (test_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state))
 929                 goto csum_unnecessary;
 930
 931         /* CQE csum doesn't cover padding octets in short ethernet
 932          * frames. And the pad field is appended prior to calculating
 933          * and appending the FCS field.
 934          *
 935          * Detecting these padded frames requires to verify and parse
 936          * IP headers, so we simply force all those small frames to be
 937          * CHECKSUM_UNNECESSARY even if they are not padded.
 938          */
 939         if (short_frame(skb->len))
 940                 goto csum_unnecessary;
 941
 942         if (likely(is_last_ethertype_ip(skb, &network_depth, &proto))) {
 943                 if (unlikely(get_ip_proto(skb, network_depth, proto) == IPPROTO_SCTP))
 944                         goto csum_unnecessary;
 945
 946                 stats->csum_complete++;
 947                 skb->ip_summed = CHECKSUM_COMPLETE;
 948                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
 949
 950                 if (test_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state))
 951                         return; /* CQE csum covers all received bytes */
 952
 953                 /* csum might need some fixups ...*/
 954                 mlx5e_skb_csum_fixup(skb, network_depth, proto, stats);
 955                 return;
 956         }
 957
 958 csum_unnecessary:
 959         if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
 960                    (cqe->hds_ip_ext & CQE_L4_OK))) {
 961                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 962                 if (cqe_is_tunneled(cqe)) {
 963                         skb->csum_level = 1;
 964                         skb->encapsulation = 1;
 965                         stats->csum_unnecessary_inner++;
 966                         return;
 967                 }
 968                 stats->csum_unnecessary++;
 969                 return;
 970         }
 971 csum_none:
 972         skb->ip_summed = CHECKSUM_NONE;
 973         stats->csum_none++;
 974 }
 975
 976 #define MLX5E_CE_BIT_MASK 0x80
 977
 978 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
 979                                       u32 cqe_bcnt,
 980                                       struct mlx5e_rq *rq,
 981                                       struct sk_buff *skb)
 982 {
 983         u8 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
 984         struct mlx5e_rq_stats *stats = rq->stats;
 985         struct net_device *netdev = rq->netdev;
 986
 987         skb->mac_len = ETH_HLEN;
 988
 989 #ifdef CONFIG_MLX5_EN_TLS
 990         mlx5e_tls_handle_rx_skb(netdev, skb, &cqe_bcnt);
 991 #endif
 992
 993         if (lro_num_seg > 1) {
 994                 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
 995                 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
 996                 /* Subtract one since we already counted this as one
 997                  * "regular" packet in mlx5e_complete_rx_cqe()
 998                  */
 999                 stats->packets += lro_num_seg - 1;
1000                 stats->lro_packets++;
1001                 stats->lro_bytes += cqe_bcnt;
1002         }
1003
1004         if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
1005                 skb_hwtstamps(skb)->hwtstamp =
1006                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1007
1008         skb_record_rx_queue(skb, rq->ix);
1009
1010         if (likely(netdev->features & NETIF_F_RXHASH))
1011                 mlx5e_skb_set_hash(cqe, skb);
1012
1013         if (cqe_has_vlan(cqe)) {
1014                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1015                                        be16_to_cpu(cqe->vlan_info));
1016                 stats->removed_vlan_packets++;
1017         }
1018
1019         skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
1020
1021         mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
1022         /* checking CE bit in cqe - MSB in ml_path field */
1023         if (unlikely(cqe->ml_path & MLX5E_CE_BIT_MASK))
1024                 mlx5e_enable_ecn(rq, skb);
1025
1026         skb->protocol = eth_type_trans(skb, netdev);
1027 }
1028
1029 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
1030                                          struct mlx5_cqe64 *cqe,
1031                                          u32 cqe_bcnt,
1032                                          struct sk_buff *skb)
1033 {
1034         struct mlx5e_rq_stats *stats = rq->stats;
1035
1036         stats->packets++;
1037         stats->bytes += cqe_bcnt;
1038         mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
1039 }
1040
1041 static inline
1042 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va,
1043                                        u32 frag_size, u16 headroom,
1044                                        u32 cqe_bcnt)
1045 {
1046         struct sk_buff *skb = build_skb(va, frag_size);
1047
1048         if (unlikely(!skb)) {
1049                 rq->stats->buff_alloc_err++;
1050                 return NULL;
1051         }
1052
1053         skb_reserve(skb, headroom);
1054         skb_put(skb, cqe_bcnt);
1055
1056         return skb;
1057 }
1058
1059 struct sk_buff *
1060 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
1061                           struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
1062 {
1063         struct mlx5e_dma_info *di = wi->di;
1064         u16 rx_headroom = rq->buff.headroom;
1065         struct sk_buff *skb;
1066         void *va, *data;
1067         bool consumed;
1068         u32 frag_size;
1069
1070         va             = page_address(di->page) + wi->offset;
1071         data           = va + rx_headroom;
1072         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
1073
1074         dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset,
1075                                       frag_size, DMA_FROM_DEVICE);
1076         prefetchw(va); /* xdp_frame data area */
1077         prefetch(data);
1078
1079         rcu_read_lock();
1080         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt, false);
1081         rcu_read_unlock();
1082         if (consumed)
1083                 return NULL; /* page/packet was consumed by XDP */
1084
1085         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt);
1086         if (unlikely(!skb))
1087                 return NULL;
1088
1089         /* queue up for recycling/reuse */
1090         page_ref_inc(di->page);
1091
1092         return skb;
1093 }
1094
1095 struct sk_buff *
1096 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
1097                              struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
1098 {
1099         struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
1100         struct mlx5e_wqe_frag_info *head_wi = wi;
1101         u16 headlen      = min_t(u32, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1102         u16 frag_headlen = headlen;
1103         u16 byte_cnt     = cqe_bcnt - headlen;
1104         struct sk_buff *skb;
1105
1106         /* XDP is not supported in this configuration, as incoming packets
1107          * might spread among multiple pages.
1108          */
1109         skb = napi_alloc_skb(rq->cq.napi,
1110                              ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1111         if (unlikely(!skb)) {
1112                 rq->stats->buff_alloc_err++;
1113                 return NULL;
1114         }
1115
1116         prefetchw(skb->data);
1117
1118         while (byte_cnt) {
1119                 u16 frag_consumed_bytes =
1120                         min_t(u16, frag_info->frag_size - frag_headlen, byte_cnt);
1121
1122                 mlx5e_add_skb_frag(rq, skb, wi->di, wi->offset + frag_headlen,
1123                                    frag_consumed_bytes, frag_info->frag_stride);
1124                 byte_cnt -= frag_consumed_bytes;
1125                 frag_headlen = 0;
1126                 frag_info++;
1127                 wi++;
1128         }
1129
1130         /* copy header */
1131         mlx5e_copy_skb_header(rq->pdev, skb, head_wi->di, head_wi->offset, headlen);
1132         /* skb linear part was allocated with headlen and aligned to long */
1133         skb->tail += headlen;
1134         skb->len  += headlen;
1135
1136         return skb;
1137 }
1138
1139 static void trigger_report(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1140 {
1141         struct mlx5_err_cqe *err_cqe = (struct mlx5_err_cqe *)cqe;
1142
1143         if (cqe_syndrome_needs_recover(err_cqe->syndrome) &&
1144             !test_and_set_bit(MLX5E_RQ_STATE_RECOVERING, &rq->state))
1145                 queue_work(rq->channel->priv->wq, &rq->recover_work);
1146 }
1147
1148 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1149 {
1150         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1151         struct mlx5e_wqe_frag_info *wi;
1152         struct sk_buff *skb;
1153         u32 cqe_bcnt;
1154         u16 ci;
1155
1156         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1157         wi       = get_frag(rq, ci);
1158         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1159
1160         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1161                 trigger_report(rq, cqe);
1162                 rq->stats->wqe_err++;
1163                 goto free_wqe;
1164         }
1165
1166         skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1167                               mlx5e_skb_from_cqe_linear,
1168                               mlx5e_skb_from_cqe_nonlinear,
1169                               rq, cqe, wi, cqe_bcnt);
1170         if (!skb) {
1171                 /* probably for XDP */
1172                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1173                         /* do not return page to cache,
1174                          * it will be returned on XDP_TX completion.
1175                          */
1176                         goto wq_cyc_pop;
1177                 }
1178                 goto free_wqe;
1179         }
1180
1181         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1182         napi_gro_receive(rq->cq.napi, skb);
1183
1184 free_wqe:
1185         mlx5e_free_rx_wqe(rq, wi, true);
1186 wq_cyc_pop:
1187         mlx5_wq_cyc_pop(wq);
1188 }
1189
1190 #ifdef CONFIG_MLX5_ESWITCH
1191 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1192 {
1193         struct net_device *netdev = rq->netdev;
1194         struct mlx5e_priv *priv = netdev_priv(netdev);
1195         struct mlx5e_rep_priv *rpriv  = priv->ppriv;
1196         struct mlx5_eswitch_rep *rep = rpriv->rep;
1197         struct mlx5e_tc_update_priv tc_priv = {};
1198         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1199         struct mlx5e_wqe_frag_info *wi;
1200         struct sk_buff *skb;
1201         u32 cqe_bcnt;
1202         u16 ci;
1203
1204         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1205         wi       = get_frag(rq, ci);
1206         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1207
1208         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1209                 rq->stats->wqe_err++;
1210                 goto free_wqe;
1211         }
1212
1213         skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1214         if (!skb) {
1215                 /* probably for XDP */
1216                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1217                         /* do not return page to cache,
1218                          * it will be returned on XDP_TX completion.
1219                          */
1220                         goto wq_cyc_pop;
1221                 }
1222                 goto free_wqe;
1223         }
1224
1225         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1226
1227         if (rep->vlan && skb_vlan_tag_present(skb))
1228                 skb_vlan_pop(skb);
1229
1230         if (!mlx5e_tc_rep_update_skb(cqe, skb, &tc_priv))
1231                 goto free_wqe;
1232
1233         napi_gro_receive(rq->cq.napi, skb);
1234
1235         mlx5_tc_rep_post_napi_receive(&tc_priv);
1236
1237 free_wqe:
1238         mlx5e_free_rx_wqe(rq, wi, true);
1239 wq_cyc_pop:
1240         mlx5_wq_cyc_pop(wq);
1241 }
1242
1243 void mlx5e_handle_rx_cqe_mpwrq_rep(struct mlx5e_rq *rq,
1244                                    struct mlx5_cqe64 *cqe)
1245 {
1246         u16 cstrides       = mpwrq_get_cqe_consumed_strides(cqe);
1247         u16 wqe_id         = be16_to_cpu(cqe->wqe_id);
1248         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1249         u16 stride_ix      = mpwrq_get_cqe_stride_index(cqe);
1250         u32 wqe_offset     = stride_ix << rq->mpwqe.log_stride_sz;
1251         u32 head_offset    = wqe_offset & (PAGE_SIZE - 1);
1252         u32 page_idx       = wqe_offset >> PAGE_SHIFT;
1253         struct mlx5e_tc_update_priv tc_priv = {};
1254         struct mlx5e_rx_wqe_ll *wqe;
1255         struct mlx5_wq_ll *wq;
1256         struct sk_buff *skb;
1257         u16 cqe_bcnt;
1258
1259         wi->consumed_strides += cstrides;
1260
1261         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1262                 trigger_report(rq, cqe);
1263                 rq->stats->wqe_err++;
1264                 goto mpwrq_cqe_out;
1265         }
1266
1267         if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1268                 struct mlx5e_rq_stats *stats = rq->stats;
1269
1270                 stats->mpwqe_filler_cqes++;
1271                 stats->mpwqe_filler_strides += cstrides;
1272                 goto mpwrq_cqe_out;
1273         }
1274
1275         cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1276
1277         skb = INDIRECT_CALL_2(rq->mpwqe.skb_from_cqe_mpwrq,
1278                               mlx5e_skb_from_cqe_mpwrq_linear,
1279                               mlx5e_skb_from_cqe_mpwrq_nonlinear,
1280                               rq, wi, cqe_bcnt, head_offset, page_idx);
1281         if (!skb)
1282                 goto mpwrq_cqe_out;
1283
1284         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1285
1286         if (!mlx5e_tc_rep_update_skb(cqe, skb, &tc_priv))
1287                 goto mpwrq_cqe_out;
1288
1289         napi_gro_receive(rq->cq.napi, skb);
1290
1291         mlx5_tc_rep_post_napi_receive(&tc_priv);
1292
1293 mpwrq_cqe_out:
1294         if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1295                 return;
1296
1297         wq  = &rq->mpwqe.wq;
1298         wqe = mlx5_wq_ll_get_wqe(wq, wqe_id);
1299         mlx5e_free_rx_mpwqe(rq, wi, true);
1300         mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1301 }
1302 #endif
1303
1304 struct sk_buff *
1305 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1306                                    u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1307 {
1308         u16 headlen = min_t(u16, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1309         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1310         u32 frag_offset    = head_offset + headlen;
1311         u32 byte_cnt       = cqe_bcnt - headlen;
1312         struct mlx5e_dma_info *head_di = di;
1313         struct sk_buff *skb;
1314
1315         skb = napi_alloc_skb(rq->cq.napi,
1316                              ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1317         if (unlikely(!skb)) {
1318                 rq->stats->buff_alloc_err++;
1319                 return NULL;
1320         }
1321
1322         prefetchw(skb->data);
1323
1324         if (unlikely(frag_offset >= PAGE_SIZE)) {
1325                 di++;
1326                 frag_offset -= PAGE_SIZE;
1327         }
1328
1329         while (byte_cnt) {
1330                 u32 pg_consumed_bytes =
1331                         min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
1332                 unsigned int truesize =
1333                         ALIGN(pg_consumed_bytes, BIT(rq->mpwqe.log_stride_sz));
1334
1335                 mlx5e_add_skb_frag(rq, skb, di, frag_offset,
1336                                    pg_consumed_bytes, truesize);
1337                 byte_cnt -= pg_consumed_bytes;
1338                 frag_offset = 0;
1339                 di++;
1340         }
1341         /* copy header */
1342         mlx5e_copy_skb_header(rq->pdev, skb, head_di, head_offset, headlen);
1343         /* skb linear part was allocated with headlen and aligned to long */
1344         skb->tail += headlen;
1345         skb->len  += headlen;
1346
1347         return skb;
1348 }
1349
1350 struct sk_buff *
1351 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1352                                 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1353 {
1354         struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1355         u16 rx_headroom = rq->buff.headroom;
1356         u32 cqe_bcnt32 = cqe_bcnt;
1357         struct sk_buff *skb;
1358         void *va, *data;
1359         u32 frag_size;
1360         bool consumed;
1361
1362         /* Check packet size. Note LRO doesn't use linear SKB */
1363         if (unlikely(cqe_bcnt > rq->hw_mtu)) {
1364                 rq->stats->oversize_pkts_sw_drop++;
1365                 return NULL;
1366         }
1367
1368         va             = page_address(di->page) + head_offset;
1369         data           = va + rx_headroom;
1370         frag_size      = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1371
1372         dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset,
1373                                       frag_size, DMA_FROM_DEVICE);
1374         prefetchw(va); /* xdp_frame data area */
1375         prefetch(data);
1376
1377         rcu_read_lock();
1378         consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt32, false);
1379         rcu_read_unlock();
1380         if (consumed) {
1381                 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags))
1382                         __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */
1383                 return NULL; /* page/packet was consumed by XDP */
1384         }
1385
1386         skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32);
1387         if (unlikely(!skb))
1388                 return NULL;
1389
1390         /* queue up for recycling/reuse */
1391         page_ref_inc(di->page);
1392
1393         return skb;
1394 }
1395
1396 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1397 {
1398         u16 cstrides       = mpwrq_get_cqe_consumed_strides(cqe);
1399         u16 wqe_id         = be16_to_cpu(cqe->wqe_id);
1400         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1401         u16 stride_ix      = mpwrq_get_cqe_stride_index(cqe);
1402         u32 wqe_offset     = stride_ix << rq->mpwqe.log_stride_sz;
1403         u32 head_offset    = wqe_offset & (PAGE_SIZE - 1);
1404         u32 page_idx       = wqe_offset >> PAGE_SHIFT;
1405         struct mlx5e_rx_wqe_ll *wqe;
1406         struct mlx5_wq_ll *wq;
1407         struct sk_buff *skb;
1408         u16 cqe_bcnt;
1409
1410         wi->consumed_strides += cstrides;
1411
1412         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1413                 trigger_report(rq, cqe);
1414                 rq->stats->wqe_err++;
1415                 goto mpwrq_cqe_out;
1416         }
1417
1418         if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1419                 struct mlx5e_rq_stats *stats = rq->stats;
1420
1421                 stats->mpwqe_filler_cqes++;
1422                 stats->mpwqe_filler_strides += cstrides;
1423                 goto mpwrq_cqe_out;
1424         }
1425
1426         cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1427
1428         skb = INDIRECT_CALL_2(rq->mpwqe.skb_from_cqe_mpwrq,
1429                               mlx5e_skb_from_cqe_mpwrq_linear,
1430                               mlx5e_skb_from_cqe_mpwrq_nonlinear,
1431                               rq, wi, cqe_bcnt, head_offset, page_idx);
1432         if (!skb)
1433                 goto mpwrq_cqe_out;
1434
1435         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1436         napi_gro_receive(rq->cq.napi, skb);
1437
1438 mpwrq_cqe_out:
1439         if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1440                 return;
1441
1442         wq  = &rq->mpwqe.wq;
1443         wqe = mlx5_wq_ll_get_wqe(wq, wqe_id);
1444         mlx5e_free_rx_mpwqe(rq, wi, true);
1445         mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1446 }
1447
1448 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1449 {
1450         struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1451         struct mlx5_cqwq *cqwq = &cq->wq;
1452         struct mlx5_cqe64 *cqe;
1453         int work_done = 0;
1454
1455         if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
1456                 return 0;
1457
1458         if (rq->page_pool)
1459                 page_pool_nid_changed(rq->page_pool, numa_mem_id());
1460
1461         if (rq->cqd.left) {
1462                 work_done += mlx5e_decompress_cqes_cont(rq, cqwq, 0, budget);
1463                 if (rq->cqd.left || work_done >= budget)
1464                         goto out;
1465         }
1466
1467         cqe = mlx5_cqwq_get_cqe(cqwq);
1468         if (!cqe) {
1469                 if (unlikely(work_done))
1470                         goto out;
1471                 return 0;
1472         }
1473
1474         do {
1475                 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1476                         work_done +=
1477                                 mlx5e_decompress_cqes_start(rq, cqwq,
1478                                                             budget - work_done);
1479                         continue;
1480                 }
1481
1482                 mlx5_cqwq_pop(cqwq);
1483
1484                 INDIRECT_CALL_2(rq->handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq,
1485                                 mlx5e_handle_rx_cqe, rq, cqe);
1486         } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(cqwq)));
1487
1488 out:
1489         if (rq->xdp_prog)
1490                 mlx5e_xdp_rx_poll_complete(rq);
1491
1492         mlx5_cqwq_update_db_record(cqwq);
1493
1494         /* ensure cq space is freed before enabling more cqes */
1495         wmb();
1496
1497         return work_done;
1498 }
1499
1500 #ifdef CONFIG_MLX5_CORE_IPOIB
1501
1502 #define MLX5_IB_GRH_DGID_OFFSET 24
1503 #define MLX5_GID_SIZE           16
1504
1505 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1506                                          struct mlx5_cqe64 *cqe,
1507                                          u32 cqe_bcnt,
1508                                          struct sk_buff *skb)
1509 {
1510         struct hwtstamp_config *tstamp;
1511         struct mlx5e_rq_stats *stats;
1512         struct net_device *netdev;
1513         struct mlx5e_priv *priv;
1514         char *pseudo_header;
1515         u32 qpn;
1516         u8 *dgid;
1517         u8 g;
1518
1519         qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1520         netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1521
1522         /* No mapping present, cannot process SKB. This might happen if a child
1523          * interface is going down while having unprocessed CQEs on parent RQ
1524          */
1525         if (unlikely(!netdev)) {
1526                 /* TODO: add drop counters support */
1527                 skb->dev = NULL;
1528                 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1529                 return;
1530         }
1531
1532         priv = mlx5i_epriv(netdev);
1533         tstamp = &priv->tstamp;
1534         stats = &priv->channel_stats[rq->ix].rq;
1535
1536         g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
1537         dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1538         if ((!g) || dgid[0] != 0xff)
1539                 skb->pkt_type = PACKET_HOST;
1540         else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1541                 skb->pkt_type = PACKET_BROADCAST;
1542         else
1543                 skb->pkt_type = PACKET_MULTICAST;
1544
1545         /* TODO: IB/ipoib: Allow mcast packets from other VFs
1546          * 68996a6e760e5c74654723eeb57bf65628ae87f4
1547          */
1548
1549         skb_pull(skb, MLX5_IB_GRH_BYTES);
1550
1551         skb->protocol = *((__be16 *)(skb->data));
1552
1553         if (netdev->features & NETIF_F_RXCSUM) {
1554                 skb->ip_summed = CHECKSUM_COMPLETE;
1555                 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1556                 stats->csum_complete++;
1557         } else {
1558                 skb->ip_summed = CHECKSUM_NONE;
1559                 stats->csum_none++;
1560         }
1561
1562         if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1563                 skb_hwtstamps(skb)->hwtstamp =
1564                                 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1565
1566         skb_record_rx_queue(skb, rq->ix);
1567
1568         if (likely(netdev->features & NETIF_F_RXHASH))
1569                 mlx5e_skb_set_hash(cqe, skb);
1570
1571         /* 20 bytes of ipoib header and 4 for encap existing */
1572         pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1573         memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1574         skb_reset_mac_header(skb);
1575         skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1576
1577         skb->dev = netdev;
1578
1579         stats->packets++;
1580         stats->bytes += cqe_bcnt;
1581 }
1582
1583 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1584 {
1585         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1586         struct mlx5e_wqe_frag_info *wi;
1587         struct sk_buff *skb;
1588         u32 cqe_bcnt;
1589         u16 ci;
1590
1591         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1592         wi       = get_frag(rq, ci);
1593         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1594
1595         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1596                 rq->stats->wqe_err++;
1597                 goto wq_free_wqe;
1598         }
1599
1600         skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1601                               mlx5e_skb_from_cqe_linear,
1602                               mlx5e_skb_from_cqe_nonlinear,
1603                               rq, cqe, wi, cqe_bcnt);
1604         if (!skb)
1605                 goto wq_free_wqe;
1606
1607         mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1608         if (unlikely(!skb->dev)) {
1609                 dev_kfree_skb_any(skb);
1610                 goto wq_free_wqe;
1611         }
1612         napi_gro_receive(rq->cq.napi, skb);
1613
1614 wq_free_wqe:
1615         mlx5e_free_rx_wqe(rq, wi, true);
1616         mlx5_wq_cyc_pop(wq);
1617 }
1618
1619 #endif /* CONFIG_MLX5_CORE_IPOIB */
1620
1621 #ifdef CONFIG_MLX5_EN_IPSEC
1622
1623 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1624 {
1625         struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1626         struct mlx5e_wqe_frag_info *wi;
1627         struct sk_buff *skb;
1628         u32 cqe_bcnt;
1629         u16 ci;
1630
1631         ci       = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1632         wi       = get_frag(rq, ci);
1633         cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1634
1635         if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1636                 rq->stats->wqe_err++;
1637                 goto wq_free_wqe;
1638         }
1639
1640         skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1641                               mlx5e_skb_from_cqe_linear,
1642                               mlx5e_skb_from_cqe_nonlinear,
1643                               rq, cqe, wi, cqe_bcnt);
1644         if (unlikely(!skb)) /* a DROP, save the page-reuse checks */
1645                 goto wq_free_wqe;
1646
1647         skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb, &cqe_bcnt);
1648         if (unlikely(!skb))
1649                 goto wq_free_wqe;
1650
1651         mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1652         napi_gro_receive(rq->cq.napi, skb);
1653
1654 wq_free_wqe:
1655         mlx5e_free_rx_wqe(rq, wi, true);
1656         mlx5_wq_cyc_pop(wq);
1657 }
1658
1659 #endif /* CONFIG_MLX5_EN_IPSEC */