drivers/net/ethernet/mellanox/mlx5/core/en_tc.c

   1 /*
   2  * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/flow_dissector.h>
  34 #include <net/sch_generic.h>
  35 #include <net/pkt_cls.h>
  36 #include <net/tc_act/tc_gact.h>
  37 #include <net/tc_act/tc_skbedit.h>
  38 #include <linux/mlx5/fs.h>
  39 #include <linux/mlx5/device.h>
  40 #include <linux/rhashtable.h>
  41 #include <linux/refcount.h>
  42 #include <linux/completion.h>
  43 #include <net/tc_act/tc_mirred.h>
  44 #include <net/tc_act/tc_vlan.h>
  45 #include <net/tc_act/tc_tunnel_key.h>
  46 #include <net/tc_act/tc_pedit.h>
  47 #include <net/tc_act/tc_csum.h>
  48 #include <net/arp.h>
  49 #include <net/ipv6_stubs.h>
  50 #include "en.h"
  51 #include "en_rep.h"
  52 #include "en_tc.h"
  53 #include "eswitch.h"
  54 #include "esw/chains.h"
  55 #include "fs_core.h"
  56 #include "en/port.h"
  57 #include "en/tc_tun.h"
  58 #include "en/mapping.h"
  59 #include "en/tc_ct.h"
  60 #include "lib/devcom.h"
  61 #include "lib/geneve.h"
  62 #include "diag/en_tc_tracepoint.h"
  63
  64 #define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
  65
  66 struct mlx5_nic_flow_attr {
  67         u32 action;
  68         u32 flow_tag;
  69         struct mlx5_modify_hdr *modify_hdr;
  70         u32 hairpin_tirn;
  71         u8 match_level;
  72         struct mlx5_flow_table  *hairpin_ft;
  73         struct mlx5_fc          *counter;
  74 };
  75
  76 #define MLX5E_TC_FLOW_BASE (MLX5E_TC_FLAG_LAST_EXPORTED_BIT + 1)
  77
  78 enum {
  79         MLX5E_TC_FLOW_FLAG_INGRESS      = MLX5E_TC_FLAG_INGRESS_BIT,
  80         MLX5E_TC_FLOW_FLAG_EGRESS       = MLX5E_TC_FLAG_EGRESS_BIT,
  81         MLX5E_TC_FLOW_FLAG_ESWITCH      = MLX5E_TC_FLAG_ESW_OFFLOAD_BIT,
  82         MLX5E_TC_FLOW_FLAG_FT           = MLX5E_TC_FLAG_FT_OFFLOAD_BIT,
  83         MLX5E_TC_FLOW_FLAG_NIC          = MLX5E_TC_FLAG_NIC_OFFLOAD_BIT,
  84         MLX5E_TC_FLOW_FLAG_OFFLOADED    = MLX5E_TC_FLOW_BASE,
  85         MLX5E_TC_FLOW_FLAG_HAIRPIN      = MLX5E_TC_FLOW_BASE + 1,
  86         MLX5E_TC_FLOW_FLAG_HAIRPIN_RSS  = MLX5E_TC_FLOW_BASE + 2,
  87         MLX5E_TC_FLOW_FLAG_SLOW         = MLX5E_TC_FLOW_BASE + 3,
  88         MLX5E_TC_FLOW_FLAG_DUP          = MLX5E_TC_FLOW_BASE + 4,
  89         MLX5E_TC_FLOW_FLAG_NOT_READY    = MLX5E_TC_FLOW_BASE + 5,
  90         MLX5E_TC_FLOW_FLAG_DELETED      = MLX5E_TC_FLOW_BASE + 6,
  91         MLX5E_TC_FLOW_FLAG_CT           = MLX5E_TC_FLOW_BASE + 7,
  92 };
  93
  94 #define MLX5E_TC_MAX_SPLITS 1
  95
  96 /* Helper struct for accessing a struct containing list_head array.
  97  * Containing struct
  98  *   |- Helper array
  99  *      [0] Helper item 0
 100  *          |- list_head item 0
 101  *          |- index (0)
 102  *      [1] Helper item 1
 103  *          |- list_head item 1
 104  *          |- index (1)
 105  * To access the containing struct from one of the list_head items:
 106  * 1. Get the helper item from the list_head item using
 107  *    helper item =
 108  *        container_of(list_head item, helper struct type, list_head field)
 109  * 2. Get the contining struct from the helper item and its index in the array:
 110  *    containing struct =
 111  *        container_of(helper item, containing struct type, helper field[index])
 112  */
 113 struct encap_flow_item {
 114         struct mlx5e_encap_entry *e; /* attached encap instance */
 115         struct list_head list;
 116         int index;
 117 };
 118
 119 struct mlx5e_tc_flow {
 120         struct rhash_head       node;
 121         struct mlx5e_priv       *priv;
 122         u64                     cookie;
 123         unsigned long           flags;
 124         struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
 125         /* Flow can be associated with multiple encap IDs.
 126          * The number of encaps is bounded by the number of supported
 127          * destinations.
 128          */
 129         struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS];
 130         struct mlx5e_tc_flow    *peer_flow;
 131         struct mlx5e_mod_hdr_entry *mh; /* attached mod header instance */
 132         struct list_head        mod_hdr; /* flows sharing the same mod hdr ID */
 133         struct mlx5e_hairpin_entry *hpe; /* attached hairpin instance */
 134         struct list_head        hairpin; /* flows sharing the same hairpin */
 135         struct list_head        peer;    /* flows with peer flow */
 136         struct list_head        unready; /* flows not ready to be offloaded (e.g due to missing route) */
 137         int                     tmp_efi_index;
 138         struct list_head        tmp_list; /* temporary flow list used by neigh update */
 139         refcount_t              refcnt;
 140         struct rcu_head         rcu_head;
 141         struct completion       init_done;
 142         int tunnel_id; /* the mapped tunnel id of this flow */
 143
 144         union {
 145                 struct mlx5_esw_flow_attr esw_attr[0];
 146                 struct mlx5_nic_flow_attr nic_attr[0];
 147         };
 148 };
 149
 150 struct mlx5e_tc_flow_parse_attr {
 151         const struct ip_tunnel_info *tun_info[MLX5_MAX_FLOW_FWD_VPORTS];
 152         struct net_device *filter_dev;
 153         struct mlx5_flow_spec spec;
 154         struct mlx5e_tc_mod_hdr_acts mod_hdr_acts;
 155         int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS];
 156 };
 157
 158 #define MLX5E_TC_TABLE_NUM_GROUPS 4
 159 #define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
 160
 161 struct tunnel_match_key {
 162         struct flow_dissector_key_control enc_control;
 163         struct flow_dissector_key_keyid enc_key_id;
 164         struct flow_dissector_key_ports enc_tp;
 165         struct flow_dissector_key_ip enc_ip;
 166         union {
 167                 struct flow_dissector_key_ipv4_addrs enc_ipv4;
 168                 struct flow_dissector_key_ipv6_addrs enc_ipv6;
 169         };
 170
 171         int filter_ifindex;
 172 };
 173
 174 /* Tunnel_id mapping is TUNNEL_INFO_BITS + ENC_OPTS_BITS.
 175  * Upper TUNNEL_INFO_BITS for general tunnel info.
 176  * Lower ENC_OPTS_BITS bits for enc_opts.
 177  */
 178 #define TUNNEL_INFO_BITS 6
 179 #define TUNNEL_INFO_BITS_MASK GENMASK(TUNNEL_INFO_BITS - 1, 0)
 180 #define ENC_OPTS_BITS 2
 181 #define ENC_OPTS_BITS_MASK GENMASK(ENC_OPTS_BITS - 1, 0)
 182 #define TUNNEL_ID_BITS (TUNNEL_INFO_BITS + ENC_OPTS_BITS)
 183 #define TUNNEL_ID_MASK GENMASK(TUNNEL_ID_BITS - 1, 0)
 184
 185 struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
 186         [CHAIN_TO_REG] = {
 187                 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
 188                 .moffset = 0,
 189                 .mlen = 2,
 190         },
 191         [TUNNEL_TO_REG] = {
 192                 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
 193                 .moffset = 3,
 194                 .mlen = 1,
 195                 .soffset = MLX5_BYTE_OFF(fte_match_param,
 196                                          misc_parameters_2.metadata_reg_c_1),
 197         },
 198         [ZONE_TO_REG] = zone_to_reg_ct,
 199         [CTSTATE_TO_REG] = ctstate_to_reg_ct,
 200         [MARK_TO_REG] = mark_to_reg_ct,
 201         [LABELS_TO_REG] = labels_to_reg_ct,
 202         [FTEID_TO_REG] = fteid_to_reg_ct,
 203         [TUPLEID_TO_REG] = tupleid_to_reg_ct,
 204 };
 205
 206 static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
 207
 208 void
 209 mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
 210                             enum mlx5e_tc_attr_to_reg type,
 211                             u32 data,
 212                             u32 mask)
 213 {
 214         int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
 215         int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
 216         void *headers_c = spec->match_criteria;
 217         void *headers_v = spec->match_value;
 218         void *fmask, *fval;
 219
 220         fmask = headers_c + soffset;
 221         fval = headers_v + soffset;
 222
 223         mask = cpu_to_be32(mask) >> (32 - (match_len * 8));
 224         data = cpu_to_be32(data) >> (32 - (match_len * 8));
 225
 226         memcpy(fmask, &mask, match_len);
 227         memcpy(fval, &data, match_len);
 228
 229         spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
 230 }
 231
 232 int
 233 mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
 234                           struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
 235                           enum mlx5e_tc_attr_to_reg type,
 236                           u32 data)
 237 {
 238         int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
 239         int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
 240         int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
 241         char *modact;
 242         int err;
 243
 244         err = alloc_mod_hdr_actions(mdev, MLX5_FLOW_NAMESPACE_FDB,
 245                                     mod_hdr_acts);
 246         if (err)
 247                 return err;
 248
 249         modact = mod_hdr_acts->actions +
 250                  (mod_hdr_acts->num_actions * MLX5_MH_ACT_SZ);
 251
 252         /* Firmware has 5bit length field and 0 means 32bits */
 253         if (mlen == 4)
 254                 mlen = 0;
 255
 256         MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
 257         MLX5_SET(set_action_in, modact, field, mfield);
 258         MLX5_SET(set_action_in, modact, offset, moffset * 8);
 259         MLX5_SET(set_action_in, modact, length, mlen * 8);
 260         MLX5_SET(set_action_in, modact, data, data);
 261         mod_hdr_acts->num_actions++;
 262
 263         return 0;
 264 }
 265
 266 struct mlx5e_hairpin {
 267         struct mlx5_hairpin *pair;
 268
 269         struct mlx5_core_dev *func_mdev;
 270         struct mlx5e_priv *func_priv;
 271         u32 tdn;
 272         u32 tirn;
 273
 274         int num_channels;
 275         struct mlx5e_rqt indir_rqt;
 276         u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
 277         struct mlx5e_ttc_table ttc;
 278 };
 279
 280 struct mlx5e_hairpin_entry {
 281         /* a node of a hash table which keeps all the  hairpin entries */
 282         struct hlist_node hairpin_hlist;
 283
 284         /* protects flows list */
 285         spinlock_t flows_lock;
 286         /* flows sharing the same hairpin */
 287         struct list_head flows;
 288         /* hpe's that were not fully initialized when dead peer update event
 289          * function traversed them.
 290          */
 291         struct list_head dead_peer_wait_list;
 292
 293         u16 peer_vhca_id;
 294         u8 prio;
 295         struct mlx5e_hairpin *hp;
 296         refcount_t refcnt;
 297         struct completion res_ready;
 298 };
 299
 300 struct mod_hdr_key {
 301         int num_actions;
 302         void *actions;
 303 };
 304
 305 struct mlx5e_mod_hdr_entry {
 306         /* a node of a hash table which keeps all the mod_hdr entries */
 307         struct hlist_node mod_hdr_hlist;
 308
 309         /* protects flows list */
 310         spinlock_t flows_lock;
 311         /* flows sharing the same mod_hdr entry */
 312         struct list_head flows;
 313
 314         struct mod_hdr_key key;
 315
 316         struct mlx5_modify_hdr *modify_hdr;
 317
 318         refcount_t refcnt;
 319         struct completion res_ready;
 320         int compl_result;
 321 };
 322
 323 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
 324                               struct mlx5e_tc_flow *flow);
 325
 326 static struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
 327 {
 328         if (!flow || !refcount_inc_not_zero(&flow->refcnt))
 329                 return ERR_PTR(-EINVAL);
 330         return flow;
 331 }
 332
 333 static void mlx5e_flow_put(struct mlx5e_priv *priv,
 334                            struct mlx5e_tc_flow *flow)
 335 {
 336         if (refcount_dec_and_test(&flow->refcnt)) {
 337                 mlx5e_tc_del_flow(priv, flow);
 338                 kfree_rcu(flow, rcu_head);
 339         }
 340 }
 341
 342 static void __flow_flag_set(struct mlx5e_tc_flow *flow, unsigned long flag)
 343 {
 344         /* Complete all memory stores before setting bit. */
 345         smp_mb__before_atomic();
 346         set_bit(flag, &flow->flags);
 347 }
 348
 349 #define flow_flag_set(flow, flag) __flow_flag_set(flow, MLX5E_TC_FLOW_FLAG_##flag)
 350
 351 static bool __flow_flag_test_and_set(struct mlx5e_tc_flow *flow,
 352                                      unsigned long flag)
 353 {
 354         /* test_and_set_bit() provides all necessary barriers */
 355         return test_and_set_bit(flag, &flow->flags);
 356 }
 357
 358 #define flow_flag_test_and_set(flow, flag)                      \
 359         __flow_flag_test_and_set(flow,                          \
 360                                  MLX5E_TC_FLOW_FLAG_##flag)
 361
 362 static void __flow_flag_clear(struct mlx5e_tc_flow *flow, unsigned long flag)
 363 {
 364         /* Complete all memory stores before clearing bit. */
 365         smp_mb__before_atomic();
 366         clear_bit(flag, &flow->flags);
 367 }
 368
 369 #define flow_flag_clear(flow, flag) __flow_flag_clear(flow, \
 370                                                       MLX5E_TC_FLOW_FLAG_##flag)
 371
 372 static bool __flow_flag_test(struct mlx5e_tc_flow *flow, unsigned long flag)
 373 {
 374         bool ret = test_bit(flag, &flow->flags);
 375
 376         /* Read fields of flow structure only after checking flags. */
 377         smp_mb__after_atomic();
 378         return ret;
 379 }
 380
 381 #define flow_flag_test(flow, flag) __flow_flag_test(flow, \
 382                                                     MLX5E_TC_FLOW_FLAG_##flag)
 383
 384 static bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
 385 {
 386         return flow_flag_test(flow, ESWITCH);
 387 }
 388
 389 static bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
 390 {
 391         return flow_flag_test(flow, FT);
 392 }
 393
 394 static bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
 395 {
 396         return flow_flag_test(flow, OFFLOADED);
 397 }
 398
 399 static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
 400 {
 401         return jhash(key->actions,
 402                      key->num_actions * MLX5_MH_ACT_SZ, 0);
 403 }
 404
 405 static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
 406                                    struct mod_hdr_key *b)
 407 {
 408         if (a->num_actions != b->num_actions)
 409                 return 1;
 410
 411         return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
 412 }
 413
 414 static struct mod_hdr_tbl *
 415 get_mod_hdr_table(struct mlx5e_priv *priv, int namespace)
 416 {
 417         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
 418
 419         return namespace == MLX5_FLOW_NAMESPACE_FDB ? &esw->offloads.mod_hdr :
 420                 &priv->fs.tc.mod_hdr;
 421 }
 422
 423 static struct mlx5e_mod_hdr_entry *
 424 mlx5e_mod_hdr_get(struct mod_hdr_tbl *tbl, struct mod_hdr_key *key, u32 hash_key)
 425 {
 426         struct mlx5e_mod_hdr_entry *mh, *found = NULL;
 427
 428         hash_for_each_possible(tbl->hlist, mh, mod_hdr_hlist, hash_key) {
 429                 if (!cmp_mod_hdr_info(&mh->key, key)) {
 430                         refcount_inc(&mh->refcnt);
 431                         found = mh;
 432                         break;
 433                 }
 434         }
 435
 436         return found;
 437 }
 438
 439 static void mlx5e_mod_hdr_put(struct mlx5e_priv *priv,
 440                               struct mlx5e_mod_hdr_entry *mh,
 441                               int namespace)
 442 {
 443         struct mod_hdr_tbl *tbl = get_mod_hdr_table(priv, namespace);
 444
 445         if (!refcount_dec_and_mutex_lock(&mh->refcnt, &tbl->lock))
 446                 return;
 447         hash_del(&mh->mod_hdr_hlist);
 448         mutex_unlock(&tbl->lock);
 449
 450         WARN_ON(!list_empty(&mh->flows));
 451         if (mh->compl_result > 0)
 452                 mlx5_modify_header_dealloc(priv->mdev, mh->modify_hdr);
 453
 454         kfree(mh);
 455 }
 456
 457 static int get_flow_name_space(struct mlx5e_tc_flow *flow)
 458 {
 459         return mlx5e_is_eswitch_flow(flow) ?
 460                 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
 461 }
 462 static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
 463                                 struct mlx5e_tc_flow *flow,
 464                                 struct mlx5e_tc_flow_parse_attr *parse_attr)
 465 {
 466         int num_actions, actions_size, namespace, err;
 467         struct mlx5e_mod_hdr_entry *mh;
 468         struct mod_hdr_tbl *tbl;
 469         struct mod_hdr_key key;
 470         u32 hash_key;
 471
 472         num_actions  = parse_attr->mod_hdr_acts.num_actions;
 473         actions_size = MLX5_MH_ACT_SZ * num_actions;
 474
 475         key.actions = parse_attr->mod_hdr_acts.actions;
 476         key.num_actions = num_actions;
 477
 478         hash_key = hash_mod_hdr_info(&key);
 479
 480         namespace = get_flow_name_space(flow);
 481         tbl = get_mod_hdr_table(priv, namespace);
 482
 483         mutex_lock(&tbl->lock);
 484         mh = mlx5e_mod_hdr_get(tbl, &key, hash_key);
 485         if (mh) {
 486                 mutex_unlock(&tbl->lock);
 487                 wait_for_completion(&mh->res_ready);
 488
 489                 if (mh->compl_result < 0) {
 490                         err = -EREMOTEIO;
 491                         goto attach_header_err;
 492                 }
 493                 goto attach_flow;
 494         }
 495
 496         mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
 497         if (!mh) {
 498                 mutex_unlock(&tbl->lock);
 499                 return -ENOMEM;
 500         }
 501
 502         mh->key.actions = (void *)mh + sizeof(*mh);
 503         memcpy(mh->key.actions, key.actions, actions_size);
 504         mh->key.num_actions = num_actions;
 505         spin_lock_init(&mh->flows_lock);
 506         INIT_LIST_HEAD(&mh->flows);
 507         refcount_set(&mh->refcnt, 1);
 508         init_completion(&mh->res_ready);
 509
 510         hash_add(tbl->hlist, &mh->mod_hdr_hlist, hash_key);
 511         mutex_unlock(&tbl->lock);
 512
 513         mh->modify_hdr = mlx5_modify_header_alloc(priv->mdev, namespace,
 514                                                   mh->key.num_actions,
 515                                                   mh->key.actions);
 516         if (IS_ERR(mh->modify_hdr)) {
 517                 err = PTR_ERR(mh->modify_hdr);
 518                 mh->compl_result = err;
 519                 goto alloc_header_err;
 520         }
 521         mh->compl_result = 1;
 522         complete_all(&mh->res_ready);
 523
 524 attach_flow:
 525         flow->mh = mh;
 526         spin_lock(&mh->flows_lock);
 527         list_add(&flow->mod_hdr, &mh->flows);
 528         spin_unlock(&mh->flows_lock);
 529         if (mlx5e_is_eswitch_flow(flow))
 530                 flow->esw_attr->modify_hdr = mh->modify_hdr;
 531         else
 532                 flow->nic_attr->modify_hdr = mh->modify_hdr;
 533
 534         return 0;
 535
 536 alloc_header_err:
 537         complete_all(&mh->res_ready);
 538 attach_header_err:
 539         mlx5e_mod_hdr_put(priv, mh, namespace);
 540         return err;
 541 }
 542
 543 static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
 544                                  struct mlx5e_tc_flow *flow)
 545 {
 546         /* flow wasn't fully initialized */
 547         if (!flow->mh)
 548                 return;
 549
 550         spin_lock(&flow->mh->flows_lock);
 551         list_del(&flow->mod_hdr);
 552         spin_unlock(&flow->mh->flows_lock);
 553
 554         mlx5e_mod_hdr_put(priv, flow->mh, get_flow_name_space(flow));
 555         flow->mh = NULL;
 556 }
 557
 558 static
 559 struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
 560 {
 561         struct net_device *netdev;
 562         struct mlx5e_priv *priv;
 563
 564         netdev = __dev_get_by_index(net, ifindex);
 565         priv = netdev_priv(netdev);
 566         return priv->mdev;
 567 }
 568
 569 static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
 570 {
 571         u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
 572         void *tirc;
 573         int err;
 574
 575         err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
 576         if (err)
 577                 goto alloc_tdn_err;
 578
 579         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
 580
 581         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
 582         MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
 583         MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
 584
 585         err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
 586         if (err)
 587                 goto create_tir_err;
 588
 589         return 0;
 590
 591 create_tir_err:
 592         mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
 593 alloc_tdn_err:
 594         return err;
 595 }
 596
 597 static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
 598 {
 599         mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
 600         mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
 601 }
 602
 603 static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
 604 {
 605         u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
 606         struct mlx5e_priv *priv = hp->func_priv;
 607         int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
 608
 609         mlx5e_build_default_indir_rqt(indirection_rqt, sz,
 610                                       hp->num_channels);
 611
 612         for (i = 0; i < sz; i++) {
 613                 ix = i;
 614                 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
 615                         ix = mlx5e_bits_invert(i, ilog2(sz));
 616                 ix = indirection_rqt[ix];
 617                 rqn = hp->pair->rqn[ix];
 618                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
 619         }
 620 }
 621
 622 static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
 623 {
 624         int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
 625         struct mlx5e_priv *priv = hp->func_priv;
 626         struct mlx5_core_dev *mdev = priv->mdev;
 627         void *rqtc;
 628         u32 *in;
 629
 630         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
 631         in = kvzalloc(inlen, GFP_KERNEL);
 632         if (!in)
 633                 return -ENOMEM;
 634
 635         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
 636
 637         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
 638         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
 639
 640         mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
 641
 642         err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
 643         if (!err)
 644                 hp->indir_rqt.enabled = true;
 645
 646         kvfree(in);
 647         return err;
 648 }
 649
 650 static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
 651 {
 652         struct mlx5e_priv *priv = hp->func_priv;
 653         u32 in[MLX5_ST_SZ_DW(create_tir_in)];
 654         int tt, i, err;
 655         void *tirc;
 656
 657         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
 658                 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
 659
 660                 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
 661                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
 662
 663                 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
 664                 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
 665                 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
 666                 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
 667
 668                 err = mlx5_core_create_tir(hp->func_mdev, in,
 669                                            MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
 670                 if (err) {
 671                         mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
 672                         goto err_destroy_tirs;
 673                 }
 674         }
 675         return 0;
 676
 677 err_destroy_tirs:
 678         for (i = 0; i < tt; i++)
 679                 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
 680         return err;
 681 }
 682
 683 static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
 684 {
 685         int tt;
 686
 687         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
 688                 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
 689 }
 690
 691 static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
 692                                          struct ttc_params *ttc_params)
 693 {
 694         struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
 695         int tt;
 696
 697         memset(ttc_params, 0, sizeof(*ttc_params));
 698
 699         ttc_params->any_tt_tirn = hp->tirn;
 700
 701         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
 702                 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
 703
 704         ft_attr->max_fte = MLX5E_TTC_TABLE_SIZE;
 705         ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
 706         ft_attr->prio = MLX5E_TC_PRIO;
 707 }
 708
 709 static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
 710 {
 711         struct mlx5e_priv *priv = hp->func_priv;
 712         struct ttc_params ttc_params;
 713         int err;
 714
 715         err = mlx5e_hairpin_create_indirect_rqt(hp);
 716         if (err)
 717                 return err;
 718
 719         err = mlx5e_hairpin_create_indirect_tirs(hp);
 720         if (err)
 721                 goto err_create_indirect_tirs;
 722
 723         mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
 724         err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
 725         if (err)
 726                 goto err_create_ttc_table;
 727
 728         netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
 729                    hp->num_channels, hp->ttc.ft.t->id);
 730
 731         return 0;
 732
 733 err_create_ttc_table:
 734         mlx5e_hairpin_destroy_indirect_tirs(hp);
 735 err_create_indirect_tirs:
 736         mlx5e_destroy_rqt(priv, &hp->indir_rqt);
 737
 738         return err;
 739 }
 740
 741 static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
 742 {
 743         struct mlx5e_priv *priv = hp->func_priv;
 744
 745         mlx5e_destroy_ttc_table(priv, &hp->ttc);
 746         mlx5e_hairpin_destroy_indirect_tirs(hp);
 747         mlx5e_destroy_rqt(priv, &hp->indir_rqt);
 748 }
 749
 750 static struct mlx5e_hairpin *
 751 mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
 752                      int peer_ifindex)
 753 {
 754         struct mlx5_core_dev *func_mdev, *peer_mdev;
 755         struct mlx5e_hairpin *hp;
 756         struct mlx5_hairpin *pair;
 757         int err;
 758
 759         hp = kzalloc(sizeof(*hp), GFP_KERNEL);
 760         if (!hp)
 761                 return ERR_PTR(-ENOMEM);
 762
 763         func_mdev = priv->mdev;
 764         peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
 765
 766         pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
 767         if (IS_ERR(pair)) {
 768                 err = PTR_ERR(pair);
 769                 goto create_pair_err;
 770         }
 771         hp->pair = pair;
 772         hp->func_mdev = func_mdev;
 773         hp->func_priv = priv;
 774         hp->num_channels = params->num_channels;
 775
 776         err = mlx5e_hairpin_create_transport(hp);
 777         if (err)
 778                 goto create_transport_err;
 779
 780         if (hp->num_channels > 1) {
 781                 err = mlx5e_hairpin_rss_init(hp);
 782                 if (err)
 783                         goto rss_init_err;
 784         }
 785
 786         return hp;
 787
 788 rss_init_err:
 789         mlx5e_hairpin_destroy_transport(hp);
 790 create_transport_err:
 791         mlx5_core_hairpin_destroy(hp->pair);
 792 create_pair_err:
 793         kfree(hp);
 794         return ERR_PTR(err);
 795 }
 796
 797 static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
 798 {
 799         if (hp->num_channels > 1)
 800                 mlx5e_hairpin_rss_cleanup(hp);
 801         mlx5e_hairpin_destroy_transport(hp);
 802         mlx5_core_hairpin_destroy(hp->pair);
 803         kvfree(hp);
 804 }
 805
 806 static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
 807 {
 808         return (peer_vhca_id << 16 | prio);
 809 }
 810
 811 static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
 812                                                      u16 peer_vhca_id, u8 prio)
 813 {
 814         struct mlx5e_hairpin_entry *hpe;
 815         u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
 816
 817         hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
 818                                hairpin_hlist, hash_key) {
 819                 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
 820                         refcount_inc(&hpe->refcnt);
 821                         return hpe;
 822                 }
 823         }
 824
 825         return NULL;
 826 }
 827
 828 static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
 829                               struct mlx5e_hairpin_entry *hpe)
 830 {
 831         /* no more hairpin flows for us, release the hairpin pair */
 832         if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
 833                 return;
 834         hash_del(&hpe->hairpin_hlist);
 835         mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
 836
 837         if (!IS_ERR_OR_NULL(hpe->hp)) {
 838                 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
 839                            dev_name(hpe->hp->pair->peer_mdev->device));
 840
 841                 mlx5e_hairpin_destroy(hpe->hp);
 842         }
 843
 844         WARN_ON(!list_empty(&hpe->flows));
 845         kfree(hpe);
 846 }
 847
 848 #define UNKNOWN_MATCH_PRIO 8
 849
 850 static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
 851                                   struct mlx5_flow_spec *spec, u8 *match_prio,
 852                                   struct netlink_ext_ack *extack)
 853 {
 854         void *headers_c, *headers_v;
 855         u8 prio_val, prio_mask = 0;
 856         bool vlan_present;
 857
 858 #ifdef CONFIG_MLX5_CORE_EN_DCB
 859         if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
 860                 NL_SET_ERR_MSG_MOD(extack,
 861                                    "only PCP trust state supported for hairpin");
 862                 return -EOPNOTSUPP;
 863         }
 864 #endif
 865         headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
 866         headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
 867
 868         vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
 869         if (vlan_present) {
 870                 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
 871                 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
 872         }
 873
 874         if (!vlan_present || !prio_mask) {
 875                 prio_val = UNKNOWN_MATCH_PRIO;
 876         } else if (prio_mask != 0x7) {
 877                 NL_SET_ERR_MSG_MOD(extack,
 878                                    "masked priority match not supported for hairpin");
 879                 return -EOPNOTSUPP;
 880         }
 881
 882         *match_prio = prio_val;
 883         return 0;
 884 }
 885
 886 static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
 887                                   struct mlx5e_tc_flow *flow,
 888                                   struct mlx5e_tc_flow_parse_attr *parse_attr,
 889                                   struct netlink_ext_ack *extack)
 890 {
 891         int peer_ifindex = parse_attr->mirred_ifindex[0];
 892         struct mlx5_hairpin_params params;
 893         struct mlx5_core_dev *peer_mdev;
 894         struct mlx5e_hairpin_entry *hpe;
 895         struct mlx5e_hairpin *hp;
 896         u64 link_speed64;
 897         u32 link_speed;
 898         u8 match_prio;
 899         u16 peer_id;
 900         int err;
 901
 902         peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
 903         if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
 904                 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
 905                 return -EOPNOTSUPP;
 906         }
 907
 908         peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
 909         err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
 910                                      extack);
 911         if (err)
 912                 return err;
 913
 914         mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
 915         hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
 916         if (hpe) {
 917                 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
 918                 wait_for_completion(&hpe->res_ready);
 919
 920                 if (IS_ERR(hpe->hp)) {
 921                         err = -EREMOTEIO;
 922                         goto out_err;
 923                 }
 924                 goto attach_flow;
 925         }
 926
 927         hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
 928         if (!hpe) {
 929                 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
 930                 return -ENOMEM;
 931         }
 932
 933         spin_lock_init(&hpe->flows_lock);
 934         INIT_LIST_HEAD(&hpe->flows);
 935         INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
 936         hpe->peer_vhca_id = peer_id;
 937         hpe->prio = match_prio;
 938         refcount_set(&hpe->refcnt, 1);
 939         init_completion(&hpe->res_ready);
 940
 941         hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
 942                  hash_hairpin_info(peer_id, match_prio));
 943         mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
 944
 945         params.log_data_size = 15;
 946         params.log_data_size = min_t(u8, params.log_data_size,
 947                                      MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
 948         params.log_data_size = max_t(u8, params.log_data_size,
 949                                      MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
 950
 951         params.log_num_packets = params.log_data_size -
 952                                  MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
 953         params.log_num_packets = min_t(u8, params.log_num_packets,
 954                                        MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
 955
 956         params.q_counter = priv->q_counter;
 957         /* set hairpin pair per each 50Gbs share of the link */
 958         mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
 959         link_speed = max_t(u32, link_speed, 50000);
 960         link_speed64 = link_speed;
 961         do_div(link_speed64, 50000);
 962         params.num_channels = link_speed64;
 963
 964         hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
 965         hpe->hp = hp;
 966         complete_all(&hpe->res_ready);
 967         if (IS_ERR(hp)) {
 968                 err = PTR_ERR(hp);
 969                 goto out_err;
 970         }
 971
 972         netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
 973                    hp->tirn, hp->pair->rqn[0],
 974                    dev_name(hp->pair->peer_mdev->device),
 975                    hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
 976
 977 attach_flow:
 978         if (hpe->hp->num_channels > 1) {
 979                 flow_flag_set(flow, HAIRPIN_RSS);
 980                 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
 981         } else {
 982                 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
 983         }
 984
 985         flow->hpe = hpe;
 986         spin_lock(&hpe->flows_lock);
 987         list_add(&flow->hairpin, &hpe->flows);
 988         spin_unlock(&hpe->flows_lock);
 989
 990         return 0;
 991
 992 out_err:
 993         mlx5e_hairpin_put(priv, hpe);
 994         return err;
 995 }
 996
 997 static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
 998                                    struct mlx5e_tc_flow *flow)
 999 {
1000         /* flow wasn't fully initialized */
1001         if (!flow->hpe)
1002                 return;
1003
1004         spin_lock(&flow->hpe->flows_lock);
1005         list_del(&flow->hairpin);
1006         spin_unlock(&flow->hpe->flows_lock);
1007
1008         mlx5e_hairpin_put(priv, flow->hpe);
1009         flow->hpe = NULL;
1010 }
1011
1012 static int
1013 mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
1014                       struct mlx5e_tc_flow_parse_attr *parse_attr,
1015                       struct mlx5e_tc_flow *flow,
1016                       struct netlink_ext_ack *extack)
1017 {
1018         struct mlx5_flow_context *flow_context = &parse_attr->spec.flow_context;
1019         struct mlx5_nic_flow_attr *attr = flow->nic_attr;
1020         struct mlx5_core_dev *dev = priv->mdev;
1021         struct mlx5_flow_destination dest[2] = {};
1022         struct mlx5_flow_act flow_act = {
1023                 .action = attr->action,
1024                 .flags    = FLOW_ACT_NO_APPEND,
1025         };
1026         struct mlx5_fc *counter = NULL;
1027         int err, dest_ix = 0;
1028
1029         flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1030         flow_context->flow_tag = attr->flow_tag;
1031
1032         if (flow_flag_test(flow, HAIRPIN)) {
1033                 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
1034                 if (err)
1035                         return err;
1036
1037                 if (flow_flag_test(flow, HAIRPIN_RSS)) {
1038                         dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1039                         dest[dest_ix].ft = attr->hairpin_ft;
1040                 } else {
1041                         dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
1042                         dest[dest_ix].tir_num = attr->hairpin_tirn;
1043                 }
1044                 dest_ix++;
1045         } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
1046                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1047                 dest[dest_ix].ft = priv->fs.vlan.ft.t;
1048                 dest_ix++;
1049         }
1050
1051         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1052                 counter = mlx5_fc_create(dev, true);
1053                 if (IS_ERR(counter))
1054                         return PTR_ERR(counter);
1055
1056                 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
1057                 dest[dest_ix].counter_id = mlx5_fc_id(counter);
1058                 dest_ix++;
1059                 attr->counter = counter;
1060         }
1061
1062         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1063                 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1064                 flow_act.modify_hdr = attr->modify_hdr;
1065                 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
1066                 if (err)
1067                         return err;
1068         }
1069
1070         mutex_lock(&priv->fs.tc.t_lock);
1071         if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
1072                 struct mlx5_flow_table_attr ft_attr = {};
1073                 int tc_grp_size, tc_tbl_size, tc_num_grps;
1074                 u32 max_flow_counter;
1075
1076                 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
1077                                     MLX5_CAP_GEN(dev, max_flow_counter_15_0);
1078
1079                 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
1080
1081                 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
1082                                     BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
1083                 tc_num_grps = MLX5E_TC_TABLE_NUM_GROUPS;
1084
1085                 ft_attr.prio = MLX5E_TC_PRIO;
1086                 ft_attr.max_fte = tc_tbl_size;
1087                 ft_attr.level = MLX5E_TC_FT_LEVEL;
1088                 ft_attr.autogroup.max_num_groups = tc_num_grps;
1089                 priv->fs.tc.t =
1090                         mlx5_create_auto_grouped_flow_table(priv->fs.ns,
1091                                                             &ft_attr);
1092                 if (IS_ERR(priv->fs.tc.t)) {
1093                         mutex_unlock(&priv->fs.tc.t_lock);
1094                         NL_SET_ERR_MSG_MOD(extack,
1095                                            "Failed to create tc offload table\n");
1096                         netdev_err(priv->netdev,
1097                                    "Failed to create tc offload table\n");
1098                         return PTR_ERR(priv->fs.tc.t);
1099                 }
1100         }
1101
1102         if (attr->match_level != MLX5_MATCH_NONE)
1103                 parse_attr->spec.match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
1104
1105         flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
1106                                             &flow_act, dest, dest_ix);
1107         mutex_unlock(&priv->fs.tc.t_lock);
1108
1109         return PTR_ERR_OR_ZERO(flow->rule[0]);
1110 }
1111
1112 static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1113                                   struct mlx5e_tc_flow *flow)
1114 {
1115         struct mlx5_nic_flow_attr *attr = flow->nic_attr;
1116         struct mlx5_fc *counter = NULL;
1117
1118         counter = attr->counter;
1119         if (!IS_ERR_OR_NULL(flow->rule[0]))
1120                 mlx5_del_flow_rules(flow->rule[0]);
1121         mlx5_fc_destroy(priv->mdev, counter);
1122
1123         mutex_lock(&priv->fs.tc.t_lock);
1124         if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) && priv->fs.tc.t) {
1125                 mlx5_destroy_flow_table(priv->fs.tc.t);
1126                 priv->fs.tc.t = NULL;
1127         }
1128         mutex_unlock(&priv->fs.tc.t_lock);
1129
1130         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1131                 mlx5e_detach_mod_hdr(priv, flow);
1132
1133         if (flow_flag_test(flow, HAIRPIN))
1134                 mlx5e_hairpin_flow_del(priv, flow);
1135 }
1136
1137 static void mlx5e_detach_encap(struct mlx5e_priv *priv,
1138                                struct mlx5e_tc_flow *flow, int out_index);
1139
1140 static int mlx5e_attach_encap(struct mlx5e_priv *priv,
1141                               struct mlx5e_tc_flow *flow,
1142                               struct net_device *mirred_dev,
1143                               int out_index,
1144                               struct netlink_ext_ack *extack,
1145                               struct net_device **encap_dev,
1146                               bool *encap_valid);
1147
1148 static struct mlx5_flow_handle *
1149 mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1150                            struct mlx5e_tc_flow *flow,
1151                            struct mlx5_flow_spec *spec,
1152                            struct mlx5_esw_flow_attr *attr)
1153 {
1154         struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
1155         struct mlx5_flow_handle *rule;
1156
1157         if (flow_flag_test(flow, CT)) {
1158                 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1159
1160                 return mlx5_tc_ct_flow_offload(flow->priv, flow, spec, attr,
1161                                                mod_hdr_acts);
1162         }
1163
1164         rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1165         if (IS_ERR(rule))
1166                 return rule;
1167
1168         if (attr->split_count) {
1169                 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1170                 if (IS_ERR(flow->rule[1])) {
1171                         mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
1172                         return flow->rule[1];
1173                 }
1174         }
1175
1176         return rule;
1177 }
1178
1179 static void
1180 mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1181                              struct mlx5e_tc_flow *flow,
1182                              struct mlx5_esw_flow_attr *attr)
1183 {
1184         flow_flag_clear(flow, OFFLOADED);
1185
1186         if (flow_flag_test(flow, CT)) {
1187                 mlx5_tc_ct_delete_flow(flow->priv, flow, attr);
1188                 return;
1189         }
1190
1191         if (attr->split_count)
1192                 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1193
1194         mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1195 }
1196
1197 static struct mlx5_flow_handle *
1198 mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1199                               struct mlx5e_tc_flow *flow,
1200                               struct mlx5_flow_spec *spec)
1201 {
1202         struct mlx5_esw_flow_attr slow_attr;
1203         struct mlx5_flow_handle *rule;
1204
1205         memcpy(&slow_attr, flow->esw_attr, sizeof(slow_attr));
1206         slow_attr.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1207         slow_attr.split_count = 0;
1208         slow_attr.flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1209
1210         rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, &slow_attr);
1211         if (!IS_ERR(rule))
1212                 flow_flag_set(flow, SLOW);
1213
1214         return rule;
1215 }
1216
1217 static void
1218 mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1219                                   struct mlx5e_tc_flow *flow)
1220 {
1221         struct mlx5_esw_flow_attr slow_attr;
1222
1223         memcpy(&slow_attr, flow->esw_attr, sizeof(slow_attr));
1224         slow_attr.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1225         slow_attr.split_count = 0;
1226         slow_attr.flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1227         mlx5e_tc_unoffload_fdb_rules(esw, flow, &slow_attr);
1228         flow_flag_clear(flow, SLOW);
1229 }
1230
1231 /* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1232  * function.
1233  */
1234 static void unready_flow_add(struct mlx5e_tc_flow *flow,
1235                              struct list_head *unready_flows)
1236 {
1237         flow_flag_set(flow, NOT_READY);
1238         list_add_tail(&flow->unready, unready_flows);
1239 }
1240
1241 /* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1242  * function.
1243  */
1244 static void unready_flow_del(struct mlx5e_tc_flow *flow)
1245 {
1246         list_del(&flow->unready);
1247         flow_flag_clear(flow, NOT_READY);
1248 }
1249
1250 static void add_unready_flow(struct mlx5e_tc_flow *flow)
1251 {
1252         struct mlx5_rep_uplink_priv *uplink_priv;
1253         struct mlx5e_rep_priv *rpriv;
1254         struct mlx5_eswitch *esw;
1255
1256         esw = flow->priv->mdev->priv.eswitch;
1257         rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1258         uplink_priv = &rpriv->uplink_priv;
1259
1260         mutex_lock(&uplink_priv->unready_flows_lock);
1261         unready_flow_add(flow, &uplink_priv->unready_flows);
1262         mutex_unlock(&uplink_priv->unready_flows_lock);
1263 }
1264
1265 static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1266 {
1267         struct mlx5_rep_uplink_priv *uplink_priv;
1268         struct mlx5e_rep_priv *rpriv;
1269         struct mlx5_eswitch *esw;
1270
1271         esw = flow->priv->mdev->priv.eswitch;
1272         rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1273         uplink_priv = &rpriv->uplink_priv;
1274
1275         mutex_lock(&uplink_priv->unready_flows_lock);
1276         unready_flow_del(flow);
1277         mutex_unlock(&uplink_priv->unready_flows_lock);
1278 }
1279
1280 static int
1281 mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
1282                       struct mlx5e_tc_flow *flow,
1283                       struct netlink_ext_ack *extack)
1284 {
1285         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1286         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1287         struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
1288         struct net_device *out_dev, *encap_dev = NULL;
1289         struct mlx5_fc *counter = NULL;
1290         struct mlx5e_rep_priv *rpriv;
1291         struct mlx5e_priv *out_priv;
1292         bool encap_valid = true;
1293         u32 max_prio, max_chain;
1294         int err = 0;
1295         int out_index;
1296
1297         if (!mlx5_esw_chains_prios_supported(esw) && attr->prio != 1) {
1298                 NL_SET_ERR_MSG_MOD(extack,
1299                                    "E-switch priorities unsupported, upgrade FW");
1300                 return -EOPNOTSUPP;
1301         }
1302
1303         /* We check chain range only for tc flows.
1304          * For ft flows, we checked attr->chain was originally 0 and set it to
1305          * FDB_FT_CHAIN which is outside tc range.
1306          * See mlx5e_rep_setup_ft_cb().
1307          */
1308         max_chain = mlx5_esw_chains_get_chain_range(esw);
1309         if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
1310                 NL_SET_ERR_MSG_MOD(extack,
1311                                    "Requested chain is out of supported range");
1312                 return -EOPNOTSUPP;
1313         }
1314
1315         max_prio = mlx5_esw_chains_get_prio_range(esw);
1316         if (attr->prio > max_prio) {
1317                 NL_SET_ERR_MSG_MOD(extack,
1318                                    "Requested priority is out of supported range");
1319                 return -EOPNOTSUPP;
1320         }
1321
1322         for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
1323                 int mirred_ifindex;
1324
1325                 if (!(attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
1326                         continue;
1327
1328                 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
1329                 out_dev = __dev_get_by_index(dev_net(priv->netdev),
1330                                              mirred_ifindex);
1331                 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
1332                                          extack, &encap_dev, &encap_valid);
1333                 if (err)
1334                         return err;
1335
1336                 out_priv = netdev_priv(encap_dev);
1337                 rpriv = out_priv->ppriv;
1338                 attr->dests[out_index].rep = rpriv->rep;
1339                 attr->dests[out_index].mdev = out_priv->mdev;
1340         }
1341
1342         err = mlx5_eswitch_add_vlan_action(esw, attr);
1343         if (err)
1344                 return err;
1345
1346         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
1347             !(attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR)) {
1348                 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1349                 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
1350                 if (err)
1351                         return err;
1352         }
1353
1354         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1355                 counter = mlx5_fc_create(attr->counter_dev, true);
1356                 if (IS_ERR(counter))
1357                         return PTR_ERR(counter);
1358
1359                 attr->counter = counter;
1360         }
1361
1362         /* we get here if one of the following takes place:
1363          * (1) there's no error
1364          * (2) there's an encap action and we don't have valid neigh
1365          */
1366         if (!encap_valid)
1367                 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
1368         else
1369                 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
1370
1371         if (IS_ERR(flow->rule[0]))
1372                 return PTR_ERR(flow->rule[0]);
1373         else
1374                 flow_flag_set(flow, OFFLOADED);
1375
1376         return 0;
1377 }
1378
1379 static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1380 {
1381         struct mlx5_flow_spec *spec = &flow->esw_attr->parse_attr->spec;
1382         void *headers_v = MLX5_ADDR_OF(fte_match_param,
1383                                        spec->match_value,
1384                                        misc_parameters_3);
1385         u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1386                                              headers_v,
1387                                              geneve_tlv_option_0_data);
1388
1389         return !!geneve_tlv_opt_0_data;
1390 }
1391
1392 static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1393                                   struct mlx5e_tc_flow *flow)
1394 {
1395         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1396         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1397         int out_index;
1398
1399         mlx5e_put_flow_tunnel_id(flow);
1400
1401         if (flow_flag_test(flow, NOT_READY)) {
1402                 remove_unready_flow(flow);
1403                 kvfree(attr->parse_attr);
1404                 return;
1405         }
1406
1407         if (mlx5e_is_offloaded_flow(flow)) {
1408                 if (flow_flag_test(flow, SLOW))
1409                         mlx5e_tc_unoffload_from_slow_path(esw, flow);
1410                 else
1411                         mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1412         }
1413
1414         if (mlx5_flow_has_geneve_opt(flow))
1415                 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1416
1417         mlx5_eswitch_del_vlan_action(esw, attr);
1418
1419         for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
1420                 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
1421                         mlx5e_detach_encap(priv, flow, out_index);
1422                         kfree(attr->parse_attr->tun_info[out_index]);
1423                 }
1424         kvfree(attr->parse_attr);
1425
1426         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1427                 mlx5e_detach_mod_hdr(priv, flow);
1428
1429         if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
1430                 mlx5_fc_destroy(attr->counter_dev, attr->counter);
1431 }
1432
1433 void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
1434                               struct mlx5e_encap_entry *e,
1435                               struct list_head *flow_list)
1436 {
1437         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1438         struct mlx5_esw_flow_attr *esw_attr;
1439         struct mlx5_flow_handle *rule;
1440         struct mlx5_flow_spec *spec;
1441         struct mlx5e_tc_flow *flow;
1442         int err;
1443
1444         e->pkt_reformat = mlx5_packet_reformat_alloc(priv->mdev,
1445                                                      e->reformat_type,
1446                                                      e->encap_size, e->encap_header,
1447                                                      MLX5_FLOW_NAMESPACE_FDB);
1448         if (IS_ERR(e->pkt_reformat)) {
1449                 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %lu\n",
1450                                PTR_ERR(e->pkt_reformat));
1451                 return;
1452         }
1453         e->flags |= MLX5_ENCAP_ENTRY_VALID;
1454         mlx5e_rep_queue_neigh_stats_work(priv);
1455
1456         list_for_each_entry(flow, flow_list, tmp_list) {
1457                 bool all_flow_encaps_valid = true;
1458                 int i;
1459
1460                 if (!mlx5e_is_offloaded_flow(flow))
1461                         continue;
1462                 esw_attr = flow->esw_attr;
1463                 spec = &esw_attr->parse_attr->spec;
1464
1465                 esw_attr->dests[flow->tmp_efi_index].pkt_reformat = e->pkt_reformat;
1466                 esw_attr->dests[flow->tmp_efi_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
1467                 /* Flow can be associated with multiple encap entries.
1468                  * Before offloading the flow verify that all of them have
1469                  * a valid neighbour.
1470                  */
1471                 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
1472                         if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
1473                                 continue;
1474                         if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) {
1475                                 all_flow_encaps_valid = false;
1476                                 break;
1477                         }
1478                 }
1479                 /* Do not offload flows with unresolved neighbors */
1480                 if (!all_flow_encaps_valid)
1481                         continue;
1482                 /* update from slow path rule to encap rule */
1483                 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr);
1484                 if (IS_ERR(rule)) {
1485                         err = PTR_ERR(rule);
1486                         mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1487                                        err);
1488                         continue;
1489                 }
1490
1491                 mlx5e_tc_unoffload_from_slow_path(esw, flow);
1492                 flow->rule[0] = rule;
1493                 /* was unset when slow path rule removed */
1494                 flow_flag_set(flow, OFFLOADED);
1495         }
1496 }
1497
1498 void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
1499                               struct mlx5e_encap_entry *e,
1500                               struct list_head *flow_list)
1501 {
1502         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1503         struct mlx5_flow_handle *rule;
1504         struct mlx5_flow_spec *spec;
1505         struct mlx5e_tc_flow *flow;
1506         int err;
1507
1508         list_for_each_entry(flow, flow_list, tmp_list) {
1509                 if (!mlx5e_is_offloaded_flow(flow))
1510                         continue;
1511                 spec = &flow->esw_attr->parse_attr->spec;
1512
1513                 /* update from encap rule to slow path rule */
1514                 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec);
1515                 /* mark the flow's encap dest as non-valid */
1516                 flow->esw_attr->dests[flow->tmp_efi_index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;
1517
1518                 if (IS_ERR(rule)) {
1519                         err = PTR_ERR(rule);
1520                         mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1521                                        err);
1522                         continue;
1523                 }
1524
1525                 mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr);
1526                 flow->rule[0] = rule;
1527                 /* was unset when fast path rule removed */
1528                 flow_flag_set(flow, OFFLOADED);
1529         }
1530
1531         /* we know that the encap is valid */
1532         e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
1533         mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
1534 }
1535
1536 static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1537 {
1538         if (mlx5e_is_eswitch_flow(flow))
1539                 return flow->esw_attr->counter;
1540         else
1541                 return flow->nic_attr->counter;
1542 }
1543
1544 /* Takes reference to all flows attached to encap and adds the flows to
1545  * flow_list using 'tmp_list' list_head in mlx5e_tc_flow.
1546  */
1547 void mlx5e_take_all_encap_flows(struct mlx5e_encap_entry *e, struct list_head *flow_list)
1548 {
1549         struct encap_flow_item *efi;
1550         struct mlx5e_tc_flow *flow;
1551
1552         list_for_each_entry(efi, &e->flows, list) {
1553                 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
1554                 if (IS_ERR(mlx5e_flow_get(flow)))
1555                         continue;
1556                 wait_for_completion(&flow->init_done);
1557
1558                 flow->tmp_efi_index = efi->index;
1559                 list_add(&flow->tmp_list, flow_list);
1560         }
1561 }
1562
1563 /* Iterate over tmp_list of flows attached to flow_list head. */
1564 void mlx5e_put_encap_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
1565 {
1566         struct mlx5e_tc_flow *flow, *tmp;
1567
1568         list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1569                 mlx5e_flow_put(priv, flow);
1570 }
1571
1572 static struct mlx5e_encap_entry *
1573 mlx5e_get_next_valid_encap(struct mlx5e_neigh_hash_entry *nhe,
1574                            struct mlx5e_encap_entry *e)
1575 {
1576         struct mlx5e_encap_entry *next = NULL;
1577
1578 retry:
1579         rcu_read_lock();
1580
1581         /* find encap with non-zero reference counter value */
1582         for (next = e ?
1583                      list_next_or_null_rcu(&nhe->encap_list,
1584                                            &e->encap_list,
1585                                            struct mlx5e_encap_entry,
1586                                            encap_list) :
1587                      list_first_or_null_rcu(&nhe->encap_list,
1588                                             struct mlx5e_encap_entry,
1589                                             encap_list);
1590              next;
1591              next = list_next_or_null_rcu(&nhe->encap_list,
1592                                           &next->encap_list,
1593                                           struct mlx5e_encap_entry,
1594                                           encap_list))
1595                 if (mlx5e_encap_take(next))
1596                         break;
1597
1598         rcu_read_unlock();
1599
1600         /* release starting encap */
1601         if (e)
1602                 mlx5e_encap_put(netdev_priv(e->out_dev), e);
1603         if (!next)
1604                 return next;
1605
1606         /* wait for encap to be fully initialized */
1607         wait_for_completion(&next->res_ready);
1608         /* continue searching if encap entry is not in valid state after completion */
1609         if (!(next->flags & MLX5_ENCAP_ENTRY_VALID)) {
1610                 e = next;
1611                 goto retry;
1612         }
1613
1614         return next;
1615 }
1616
1617 void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1618 {
1619         struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
1620         struct mlx5e_encap_entry *e = NULL;
1621         struct mlx5e_tc_flow *flow;
1622         struct mlx5_fc *counter;
1623         struct neigh_table *tbl;
1624         bool neigh_used = false;
1625         struct neighbour *n;
1626         u64 lastuse;
1627
1628         if (m_neigh->family == AF_INET)
1629                 tbl = &arp_tbl;
1630 #if IS_ENABLED(CONFIG_IPV6)
1631         else if (m_neigh->family == AF_INET6)
1632                 tbl = ipv6_stub->nd_tbl;
1633 #endif
1634         else
1635                 return;
1636
1637         /* mlx5e_get_next_valid_encap() releases previous encap before returning
1638          * next one.
1639          */
1640         while ((e = mlx5e_get_next_valid_encap(nhe, e)) != NULL) {
1641                 struct mlx5e_priv *priv = netdev_priv(e->out_dev);
1642                 struct encap_flow_item *efi, *tmp;
1643                 struct mlx5_eswitch *esw;
1644                 LIST_HEAD(flow_list);
1645
1646                 esw = priv->mdev->priv.eswitch;
1647                 mutex_lock(&esw->offloads.encap_tbl_lock);
1648                 list_for_each_entry_safe(efi, tmp, &e->flows, list) {
1649                         flow = container_of(efi, struct mlx5e_tc_flow,
1650                                             encaps[efi->index]);
1651                         if (IS_ERR(mlx5e_flow_get(flow)))
1652                                 continue;
1653                         list_add(&flow->tmp_list, &flow_list);
1654
1655                         if (mlx5e_is_offloaded_flow(flow)) {
1656                                 counter = mlx5e_tc_get_counter(flow);
1657                                 lastuse = mlx5_fc_query_lastuse(counter);
1658                                 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1659                                         neigh_used = true;
1660                                         break;
1661                                 }
1662                         }
1663                 }
1664                 mutex_unlock(&esw->offloads.encap_tbl_lock);
1665
1666                 mlx5e_put_encap_flow_list(priv, &flow_list);
1667                 if (neigh_used) {
1668                         /* release current encap before breaking the loop */
1669                         mlx5e_encap_put(priv, e);
1670                         break;
1671                 }
1672         }
1673
1674         trace_mlx5e_tc_update_neigh_used_value(nhe, neigh_used);
1675
1676         if (neigh_used) {
1677                 nhe->reported_lastuse = jiffies;
1678
1679                 /* find the relevant neigh according to the cached device and
1680                  * dst ip pair
1681                  */
1682                 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
1683                 if (!n)
1684                         return;
1685
1686                 neigh_event_send(n, NULL);
1687                 neigh_release(n);
1688         }
1689 }
1690
1691 static void mlx5e_encap_dealloc(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
1692 {
1693         WARN_ON(!list_empty(&e->flows));
1694
1695         if (e->compl_result > 0) {
1696                 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1697
1698                 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
1699                         mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
1700         }
1701
1702         kfree(e->tun_info);
1703         kfree(e->encap_header);
1704         kfree_rcu(e, rcu);
1705 }
1706
1707 void mlx5e_encap_put(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
1708 {
1709         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1710
1711         if (!refcount_dec_and_mutex_lock(&e->refcnt, &esw->offloads.encap_tbl_lock))
1712                 return;
1713         hash_del_rcu(&e->encap_hlist);
1714         mutex_unlock(&esw->offloads.encap_tbl_lock);
1715
1716         mlx5e_encap_dealloc(priv, e);
1717 }
1718
1719 static void mlx5e_detach_encap(struct mlx5e_priv *priv,
1720                                struct mlx5e_tc_flow *flow, int out_index)
1721 {
1722         struct mlx5e_encap_entry *e = flow->encaps[out_index].e;
1723         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1724
1725         /* flow wasn't fully initialized */
1726         if (!e)
1727                 return;
1728
1729         mutex_lock(&esw->offloads.encap_tbl_lock);
1730         list_del(&flow->encaps[out_index].list);
1731         flow->encaps[out_index].e = NULL;
1732         if (!refcount_dec_and_test(&e->refcnt)) {
1733                 mutex_unlock(&esw->offloads.encap_tbl_lock);
1734                 return;
1735         }
1736         hash_del_rcu(&e->encap_hlist);
1737         mutex_unlock(&esw->offloads.encap_tbl_lock);
1738
1739         mlx5e_encap_dealloc(priv, e);
1740 }
1741
1742 static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1743 {
1744         struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1745
1746         if (!flow_flag_test(flow, ESWITCH) ||
1747             !flow_flag_test(flow, DUP))
1748                 return;
1749
1750         mutex_lock(&esw->offloads.peer_mutex);
1751         list_del(&flow->peer);
1752         mutex_unlock(&esw->offloads.peer_mutex);
1753
1754         flow_flag_clear(flow, DUP);
1755
1756         if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1757                 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1758                 kfree(flow->peer_flow);
1759         }
1760
1761         flow->peer_flow = NULL;
1762 }
1763
1764 static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1765 {
1766         struct mlx5_core_dev *dev = flow->priv->mdev;
1767         struct mlx5_devcom *devcom = dev->priv.devcom;
1768         struct mlx5_eswitch *peer_esw;
1769
1770         peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1771         if (!peer_esw)
1772                 return;
1773
1774         __mlx5e_tc_del_fdb_peer_flow(flow);
1775         mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1776 }
1777
1778 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
1779                               struct mlx5e_tc_flow *flow)
1780 {
1781         if (mlx5e_is_eswitch_flow(flow)) {
1782                 mlx5e_tc_del_fdb_peer_flow(flow);
1783                 mlx5e_tc_del_fdb_flow(priv, flow);
1784         } else {
1785                 mlx5e_tc_del_nic_flow(priv, flow);
1786         }
1787 }
1788
1789 static int flow_has_tc_fwd_action(struct flow_cls_offload *f)
1790 {
1791         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1792         struct flow_action *flow_action = &rule->action;
1793         const struct flow_action_entry *act;
1794         int i;
1795
1796         flow_action_for_each(i, act, flow_action) {
1797                 switch (act->id) {
1798                 case FLOW_ACTION_GOTO:
1799                         return true;
1800                 default:
1801                         continue;
1802                 }
1803         }
1804
1805         return false;
1806 }
1807
1808 static int
1809 enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
1810                                     struct flow_dissector_key_enc_opts *opts,
1811                                     struct netlink_ext_ack *extack,
1812                                     bool *dont_care)
1813 {
1814         struct geneve_opt *opt;
1815         int off = 0;
1816
1817         *dont_care = true;
1818
1819         while (opts->len > off) {
1820                 opt = (struct geneve_opt *)&opts->data[off];
1821
1822                 if (!(*dont_care) || opt->opt_class || opt->type ||
1823                     memchr_inv(opt->opt_data, 0, opt->length * 4)) {
1824                         *dont_care = false;
1825
1826                         if (opt->opt_class != U16_MAX ||
1827                             opt->type != U8_MAX ||
1828                             memchr_inv(opt->opt_data, 0xFF,
1829                                        opt->length * 4)) {
1830                                 NL_SET_ERR_MSG(extack,
1831                                                "Partial match of tunnel options in chain > 0 isn't supported");
1832                                 netdev_warn(priv->netdev,
1833                                             "Partial match of tunnel options in chain > 0 isn't supported");
1834                                 return -EOPNOTSUPP;
1835                         }
1836                 }
1837
1838                 off += sizeof(struct geneve_opt) + opt->length * 4;
1839         }
1840
1841         return 0;
1842 }
1843
1844 #define COPY_DISSECTOR(rule, diss_key, dst)\
1845 ({ \
1846         struct flow_rule *__rule = (rule);\
1847         typeof(dst) __dst = dst;\
1848 \
1849         memcpy(__dst,\
1850                skb_flow_dissector_target(__rule->match.dissector,\
1851                                          diss_key,\
1852                                          __rule->match.key),\
1853                sizeof(*__dst));\
1854 })
1855
1856 static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
1857                                     struct mlx5e_tc_flow *flow,
1858                                     struct flow_cls_offload *f,
1859                                     struct net_device *filter_dev)
1860 {
1861         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1862         struct netlink_ext_ack *extack = f->common.extack;
1863         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1864         struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
1865         struct flow_match_enc_opts enc_opts_match;
1866         struct mlx5_rep_uplink_priv *uplink_priv;
1867         struct mlx5e_rep_priv *uplink_rpriv;
1868         struct tunnel_match_key tunnel_key;
1869         bool enc_opts_is_dont_care = true;
1870         u32 tun_id, enc_opts_id = 0;
1871         struct mlx5_eswitch *esw;
1872         u32 value, mask;
1873         int err;
1874
1875         esw = priv->mdev->priv.eswitch;
1876         uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1877         uplink_priv = &uplink_rpriv->uplink_priv;
1878
1879         memset(&tunnel_key, 0, sizeof(tunnel_key));
1880         COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
1881                        &tunnel_key.enc_control);
1882         if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
1883                 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1884                                &tunnel_key.enc_ipv4);
1885         else
1886                 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1887                                &tunnel_key.enc_ipv6);
1888         COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
1889         COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
1890                        &tunnel_key.enc_tp);
1891         COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
1892                        &tunnel_key.enc_key_id);
1893         tunnel_key.filter_ifindex = filter_dev->ifindex;
1894
1895         err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
1896         if (err)
1897                 return err;
1898
1899         flow_rule_match_enc_opts(rule, &enc_opts_match);
1900         err = enc_opts_is_dont_care_or_full_match(priv,
1901                                                   enc_opts_match.mask,
1902                                                   extack,
1903                                                   &enc_opts_is_dont_care);
1904         if (err)
1905                 goto err_enc_opts;
1906
1907         if (!enc_opts_is_dont_care) {
1908                 err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
1909                                   enc_opts_match.key, &enc_opts_id);
1910                 if (err)
1911                         goto err_enc_opts;
1912         }
1913
1914         value = tun_id << ENC_OPTS_BITS | enc_opts_id;
1915         mask = enc_opts_id ? TUNNEL_ID_MASK :
1916                              (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
1917
1918         if (attr->chain) {
1919                 mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
1920                                             TUNNEL_TO_REG, value, mask);
1921         } else {
1922                 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1923                 err = mlx5e_tc_match_to_reg_set(priv->mdev,
1924                                                 mod_hdr_acts,
1925                                                 TUNNEL_TO_REG, value);
1926                 if (err)
1927                         goto err_set;
1928
1929                 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1930         }
1931
1932         flow->tunnel_id = value;
1933         return 0;
1934
1935 err_set:
1936         if (enc_opts_id)
1937                 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1938                                enc_opts_id);
1939 err_enc_opts:
1940         mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1941         return err;
1942 }
1943
1944 static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
1945 {
1946         u32 enc_opts_id = flow->tunnel_id & ENC_OPTS_BITS_MASK;
1947         u32 tun_id = flow->tunnel_id >> ENC_OPTS_BITS;
1948         struct mlx5_rep_uplink_priv *uplink_priv;
1949         struct mlx5e_rep_priv *uplink_rpriv;
1950         struct mlx5_eswitch *esw;
1951
1952         esw = flow->priv->mdev->priv.eswitch;
1953         uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1954         uplink_priv = &uplink_rpriv->uplink_priv;
1955
1956         if (tun_id)
1957                 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1958         if (enc_opts_id)
1959                 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1960                                enc_opts_id);
1961 }
1962
1963 u32 mlx5e_tc_get_flow_tun_id(struct mlx5e_tc_flow *flow)
1964 {
1965         return flow->tunnel_id;
1966 }
1967
1968 static int parse_tunnel_attr(struct mlx5e_priv *priv,
1969                              struct mlx5e_tc_flow *flow,
1970                              struct mlx5_flow_spec *spec,
1971                              struct flow_cls_offload *f,
1972                              struct net_device *filter_dev,
1973                              u8 *match_level,
1974                              bool *match_inner)
1975 {
1976         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1977         struct netlink_ext_ack *extack = f->common.extack;
1978         bool needs_mapping, sets_mapping;
1979         int err;
1980
1981         if (!mlx5e_is_eswitch_flow(flow))
1982                 return -EOPNOTSUPP;
1983
1984         needs_mapping = !!flow->esw_attr->chain;
1985         sets_mapping = !flow->esw_attr->chain && flow_has_tc_fwd_action(f);
1986         *match_inner = !needs_mapping;
1987
1988         if ((needs_mapping || sets_mapping) &&
1989             !mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
1990                 NL_SET_ERR_MSG(extack,
1991                                "Chains on tunnel devices isn't supported without register loopback support");
1992                 netdev_warn(priv->netdev,
1993                             "Chains on tunnel devices isn't supported without register loopback support");
1994                 return -EOPNOTSUPP;
1995         }
1996
1997         if (!flow->esw_attr->chain) {
1998                 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
1999                                          match_level);
2000                 if (err) {
2001                         NL_SET_ERR_MSG_MOD(extack,
2002                                            "Failed to parse tunnel attributes");
2003                         netdev_warn(priv->netdev,
2004                                     "Failed to parse tunnel attributes");
2005                         return err;
2006                 }
2007
2008                 flow->esw_attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2009         }
2010
2011         if (!needs_mapping && !sets_mapping)
2012                 return 0;
2013
2014         return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
2015 }
2016
2017 static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
2018 {
2019         return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2020                             inner_headers);
2021 }
2022
2023 static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
2024 {
2025         return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2026                             inner_headers);
2027 }
2028
2029 static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
2030 {
2031         return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2032                             outer_headers);
2033 }
2034
2035 static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
2036 {
2037         return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2038                             outer_headers);
2039 }
2040
2041 static void *get_match_headers_value(u32 flags,
2042                                      struct mlx5_flow_spec *spec)
2043 {
2044         return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2045                 get_match_inner_headers_value(spec) :
2046                 get_match_outer_headers_value(spec);
2047 }
2048
2049 static void *get_match_headers_criteria(u32 flags,
2050                                         struct mlx5_flow_spec *spec)
2051 {
2052         return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2053                 get_match_inner_headers_criteria(spec) :
2054                 get_match_outer_headers_criteria(spec);
2055 }
2056
2057 static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
2058                                    struct flow_cls_offload *f)
2059 {
2060         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2061         struct netlink_ext_ack *extack = f->common.extack;
2062         struct net_device *ingress_dev;
2063         struct flow_match_meta match;
2064
2065         if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
2066                 return 0;
2067
2068         flow_rule_match_meta(rule, &match);
2069         if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
2070                 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
2071                 return -EINVAL;
2072         }
2073
2074         ingress_dev = __dev_get_by_index(dev_net(filter_dev),
2075                                          match.key->ingress_ifindex);
2076         if (!ingress_dev) {
2077                 NL_SET_ERR_MSG_MOD(extack,
2078                                    "Can't find the ingress port to match on");
2079                 return -EINVAL;
2080         }
2081
2082         if (ingress_dev != filter_dev) {
2083                 NL_SET_ERR_MSG_MOD(extack,
2084                                    "Can't match on the ingress filter port");
2085                 return -EINVAL;
2086         }
2087
2088         return 0;
2089 }
2090
2091 static int __parse_cls_flower(struct mlx5e_priv *priv,
2092                               struct mlx5e_tc_flow *flow,
2093                               struct mlx5_flow_spec *spec,
2094                               struct flow_cls_offload *f,
2095                               struct net_device *filter_dev,
2096                               u8 *inner_match_level, u8 *outer_match_level)
2097 {
2098         struct netlink_ext_ack *extack = f->common.extack;
2099         void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2100                                        outer_headers);
2101         void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2102                                        outer_headers);
2103         void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2104                                     misc_parameters);
2105         void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2106                                     misc_parameters);
2107         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2108         struct flow_dissector *dissector = rule->match.dissector;
2109         u16 addr_type = 0;
2110         u8 ip_proto = 0;
2111         u8 *match_level;
2112         int err;
2113
2114         match_level = outer_match_level;
2115
2116         if (dissector->used_keys &
2117             ~(BIT(FLOW_DISSECTOR_KEY_META) |
2118               BIT(FLOW_DISSECTOR_KEY_CONTROL) |
2119               BIT(FLOW_DISSECTOR_KEY_BASIC) |
2120               BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
2121               BIT(FLOW_DISSECTOR_KEY_VLAN) |
2122               BIT(FLOW_DISSECTOR_KEY_CVLAN) |
2123               BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
2124               BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
2125               BIT(FLOW_DISSECTOR_KEY_PORTS) |
2126               BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
2127               BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
2128               BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
2129               BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
2130               BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
2131               BIT(FLOW_DISSECTOR_KEY_TCP) |
2132               BIT(FLOW_DISSECTOR_KEY_IP)  |
2133               BIT(FLOW_DISSECTOR_KEY_CT) |
2134               BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
2135               BIT(FLOW_DISSECTOR_KEY_ENC_OPTS))) {
2136                 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
2137                 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
2138                             dissector->used_keys);
2139                 return -EOPNOTSUPP;
2140         }
2141
2142         if (mlx5e_get_tc_tun(filter_dev)) {
2143                 bool match_inner = false;
2144
2145                 err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
2146                                         outer_match_level, &match_inner);
2147                 if (err)
2148                         return err;
2149
2150                 if (match_inner) {
2151                         /* header pointers should point to the inner headers
2152                          * if the packet was decapsulated already.
2153                          * outer headers are set by parse_tunnel_attr.
2154                          */
2155                         match_level = inner_match_level;
2156                         headers_c = get_match_inner_headers_criteria(spec);
2157                         headers_v = get_match_inner_headers_value(spec);
2158                 }
2159         }
2160
2161         err = mlx5e_flower_parse_meta(filter_dev, f);
2162         if (err)
2163                 return err;
2164
2165         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2166                 struct flow_match_basic match;
2167
2168                 flow_rule_match_basic(rule, &match);
2169                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
2170                          ntohs(match.mask->n_proto));
2171                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
2172                          ntohs(match.key->n_proto));
2173
2174                 if (match.mask->n_proto)
2175                         *match_level = MLX5_MATCH_L2;
2176         }
2177         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2178             is_vlan_dev(filter_dev)) {
2179                 struct flow_dissector_key_vlan filter_dev_mask;
2180                 struct flow_dissector_key_vlan filter_dev_key;
2181                 struct flow_match_vlan match;
2182
2183                 if (is_vlan_dev(filter_dev)) {
2184                         match.key = &filter_dev_key;
2185                         match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2186                         match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2187                         match.key->vlan_priority = 0;
2188                         match.mask = &filter_dev_mask;
2189                         memset(match.mask, 0xff, sizeof(*match.mask));
2190                         match.mask->vlan_priority = 0;
2191                 } else {
2192                         flow_rule_match_vlan(rule, &match);
2193                 }
2194                 if (match.mask->vlan_id ||
2195                     match.mask->vlan_priority ||
2196                     match.mask->vlan_tpid) {
2197                         if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
2198                                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2199                                          svlan_tag, 1);
2200                                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2201                                          svlan_tag, 1);
2202                         } else {
2203                                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2204                                          cvlan_tag, 1);
2205                                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2206                                          cvlan_tag, 1);
2207                         }
2208
2209                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2210                                  match.mask->vlan_id);
2211                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2212                                  match.key->vlan_id);
2213
2214                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2215                                  match.mask->vlan_priority);
2216                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2217                                  match.key->vlan_priority);
2218
2219                         *match_level = MLX5_MATCH_L2;
2220                 }
2221         } else if (*match_level != MLX5_MATCH_NONE) {
2222                 /* cvlan_tag enabled in match criteria and
2223                  * disabled in match value means both S & C tags
2224                  * don't exist (untagged of both)
2225                  */
2226                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
2227                 *match_level = MLX5_MATCH_L2;
2228         }
2229
2230         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2231                 struct flow_match_vlan match;
2232
2233                 flow_rule_match_cvlan(rule, &match);
2234                 if (match.mask->vlan_id ||
2235                     match.mask->vlan_priority ||
2236                     match.mask->vlan_tpid) {
2237                         if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
2238                                 MLX5_SET(fte_match_set_misc, misc_c,
2239                                          outer_second_svlan_tag, 1);
2240                                 MLX5_SET(fte_match_set_misc, misc_v,
2241                                          outer_second_svlan_tag, 1);
2242                         } else {
2243                                 MLX5_SET(fte_match_set_misc, misc_c,
2244                                          outer_second_cvlan_tag, 1);
2245                                 MLX5_SET(fte_match_set_misc, misc_v,
2246                                          outer_second_cvlan_tag, 1);
2247                         }
2248
2249                         MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
2250                                  match.mask->vlan_id);
2251                         MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
2252                                  match.key->vlan_id);
2253                         MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
2254                                  match.mask->vlan_priority);
2255                         MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
2256                                  match.key->vlan_priority);
2257
2258                         *match_level = MLX5_MATCH_L2;
2259                 }
2260         }
2261
2262         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2263                 struct flow_match_eth_addrs match;
2264
2265                 flow_rule_match_eth_addrs(rule, &match);
2266                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2267                                              dmac_47_16),
2268                                 match.mask->dst);
2269                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2270                                              dmac_47_16),
2271                                 match.key->dst);
2272
2273                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2274                                              smac_47_16),
2275                                 match.mask->src);
2276                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2277                                              smac_47_16),
2278                                 match.key->src);
2279
2280                 if (!is_zero_ether_addr(match.mask->src) ||
2281                     !is_zero_ether_addr(match.mask->dst))
2282                         *match_level = MLX5_MATCH_L2;
2283         }
2284
2285         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2286                 struct flow_match_control match;
2287
2288                 flow_rule_match_control(rule, &match);
2289                 addr_type = match.key->addr_type;
2290
2291                 /* the HW doesn't support frag first/later */
2292                 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
2293                         return -EOPNOTSUPP;
2294
2295                 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
2296                         MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2297                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
2298                                  match.key->flags & FLOW_DIS_IS_FRAGMENT);
2299
2300                         /* the HW doesn't need L3 inline to match on frag=no */
2301                         if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
2302                                 *match_level = MLX5_MATCH_L2;
2303         /* ***  L2 attributes parsing up to here *** */
2304                         else
2305                                 *match_level = MLX5_MATCH_L3;
2306                 }
2307         }
2308
2309         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2310                 struct flow_match_basic match;
2311
2312                 flow_rule_match_basic(rule, &match);
2313                 ip_proto = match.key->ip_proto;
2314
2315                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2316                          match.mask->ip_proto);
2317                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2318                          match.key->ip_proto);
2319
2320                 if (match.mask->ip_proto)
2321                         *match_level = MLX5_MATCH_L3;
2322         }
2323
2324         if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
2325                 struct flow_match_ipv4_addrs match;
2326
2327                 flow_rule_match_ipv4_addrs(rule, &match);
2328                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2329                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2330                        &match.mask->src, sizeof(match.mask->src));
2331                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2332                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2333                        &match.key->src, sizeof(match.key->src));
2334                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2335                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2336                        &match.mask->dst, sizeof(match.mask->dst));
2337                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2338                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2339                        &match.key->dst, sizeof(match.key->dst));
2340
2341                 if (match.mask->src || match.mask->dst)
2342                         *match_level = MLX5_MATCH_L3;
2343         }
2344
2345         if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
2346                 struct flow_match_ipv6_addrs match;
2347
2348                 flow_rule_match_ipv6_addrs(rule, &match);
2349                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2350                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2351                        &match.mask->src, sizeof(match.mask->src));
2352                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2353                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2354                        &match.key->src, sizeof(match.key->src));
2355
2356                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2357                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2358                        &match.mask->dst, sizeof(match.mask->dst));
2359                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2360                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2361                        &match.key->dst, sizeof(match.key->dst));
2362
2363                 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2364                     ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
2365                         *match_level = MLX5_MATCH_L3;
2366         }
2367
2368         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2369                 struct flow_match_ip match;
2370
2371                 flow_rule_match_ip(rule, &match);
2372                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2373                          match.mask->tos & 0x3);
2374                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2375                          match.key->tos & 0x3);
2376
2377                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2378                          match.mask->tos >> 2);
2379                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2380                          match.key->tos  >> 2);
2381
2382                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2383                          match.mask->ttl);
2384                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2385                          match.key->ttl);
2386
2387                 if (match.mask->ttl &&
2388                     !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
2389                                                 ft_field_support.outer_ipv4_ttl)) {
2390                         NL_SET_ERR_MSG_MOD(extack,
2391                                            "Matching on TTL is not supported");
2392                         return -EOPNOTSUPP;
2393                 }
2394
2395                 if (match.mask->tos || match.mask->ttl)
2396                         *match_level = MLX5_MATCH_L3;
2397         }
2398
2399         /* ***  L3 attributes parsing up to here *** */
2400
2401         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2402                 struct flow_match_ports match;
2403
2404                 flow_rule_match_ports(rule, &match);
2405                 switch (ip_proto) {
2406                 case IPPROTO_TCP:
2407                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2408                                  tcp_sport, ntohs(match.mask->src));
2409                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2410                                  tcp_sport, ntohs(match.key->src));
2411
2412                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2413                                  tcp_dport, ntohs(match.mask->dst));
2414                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2415                                  tcp_dport, ntohs(match.key->dst));
2416                         break;
2417
2418                 case IPPROTO_UDP:
2419                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2420                                  udp_sport, ntohs(match.mask->src));
2421                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2422                                  udp_sport, ntohs(match.key->src));
2423
2424                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2425                                  udp_dport, ntohs(match.mask->dst));
2426                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2427                                  udp_dport, ntohs(match.key->dst));
2428                         break;
2429                 default:
2430                         NL_SET_ERR_MSG_MOD(extack,
2431                                            "Only UDP and TCP transports are supported for L4 matching");
2432                         netdev_err(priv->netdev,
2433                                    "Only UDP and TCP transport are supported\n");
2434                         return -EINVAL;
2435                 }
2436
2437                 if (match.mask->src || match.mask->dst)
2438                         *match_level = MLX5_MATCH_L4;
2439         }
2440
2441         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2442                 struct flow_match_tcp match;
2443
2444                 flow_rule_match_tcp(rule, &match);
2445                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
2446                          ntohs(match.mask->flags));
2447                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
2448                          ntohs(match.key->flags));
2449
2450                 if (match.mask->flags)
2451                         *match_level = MLX5_MATCH_L4;
2452         }
2453
2454         return 0;
2455 }
2456
2457 static int parse_cls_flower(struct mlx5e_priv *priv,
2458                             struct mlx5e_tc_flow *flow,
2459                             struct mlx5_flow_spec *spec,
2460                             struct flow_cls_offload *f,
2461                             struct net_device *filter_dev)
2462 {
2463         u8 inner_match_level, outer_match_level, non_tunnel_match_level;
2464         struct netlink_ext_ack *extack = f->common.extack;
2465         struct mlx5_core_dev *dev = priv->mdev;
2466         struct mlx5_eswitch *esw = dev->priv.eswitch;
2467         struct mlx5e_rep_priv *rpriv = priv->ppriv;
2468         struct mlx5_eswitch_rep *rep;
2469         bool is_eswitch_flow;
2470         int err;
2471
2472         inner_match_level = MLX5_MATCH_NONE;
2473         outer_match_level = MLX5_MATCH_NONE;
2474
2475         err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
2476                                  &inner_match_level, &outer_match_level);
2477         non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2478                                  outer_match_level : inner_match_level;
2479
2480         is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2481         if (!err && is_eswitch_flow) {
2482                 rep = rpriv->rep;
2483                 if (rep->vport != MLX5_VPORT_UPLINK &&
2484                     (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
2485                     esw->offloads.inline_mode < non_tunnel_match_level)) {
2486                         NL_SET_ERR_MSG_MOD(extack,
2487                                            "Flow is not offloaded due to min inline setting");
2488                         netdev_warn(priv->netdev,
2489                                     "Flow is not offloaded due to min inline setting, required %d actual %d\n",
2490                                     non_tunnel_match_level, esw->offloads.inline_mode);
2491                         return -EOPNOTSUPP;
2492                 }
2493         }
2494
2495         if (is_eswitch_flow) {
2496                 flow->esw_attr->inner_match_level = inner_match_level;
2497                 flow->esw_attr->outer_match_level = outer_match_level;
2498         } else {
2499                 flow->nic_attr->match_level = non_tunnel_match_level;
2500         }
2501
2502         return err;
2503 }
2504
2505 struct pedit_headers {
2506         struct ethhdr  eth;
2507         struct vlan_hdr vlan;
2508         struct iphdr   ip4;
2509         struct ipv6hdr ip6;
2510         struct tcphdr  tcp;
2511         struct udphdr  udp;
2512 };
2513
2514 struct pedit_headers_action {
2515         struct pedit_headers    vals;
2516         struct pedit_headers    masks;
2517         u32                     pedits;
2518 };
2519
2520 static int pedit_header_offsets[] = {
2521         [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2522         [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2523         [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2524         [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2525         [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
2526 };
2527
2528 #define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2529
2530 static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
2531                          struct pedit_headers_action *hdrs)
2532 {
2533         u32 *curr_pmask, *curr_pval;
2534
2535         curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2536         curr_pval  = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
2537
2538         if (*curr_pmask & mask)  /* disallow acting twice on the same location */
2539                 goto out_err;
2540
2541         *curr_pmask |= mask;
2542         *curr_pval  |= (val & mask);
2543
2544         return 0;
2545
2546 out_err:
2547         return -EOPNOTSUPP;
2548 }
2549
2550 struct mlx5_fields {
2551         u8  field;
2552         u8  field_bsize;
2553         u32 field_mask;
2554         u32 offset;
2555         u32 match_offset;
2556 };
2557
2558 #define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
2559                 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
2560                  offsetof(struct pedit_headers, field) + (off), \
2561                  MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2562
2563 /* masked values are the same and there are no rewrites that do not have a
2564  * match.
2565  */
2566 #define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2567         type matchmaskx = *(type *)(matchmaskp); \
2568         type matchvalx = *(type *)(matchvalp); \
2569         type maskx = *(type *)(maskp); \
2570         type valx = *(type *)(valp); \
2571         \
2572         (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2573                                                                  matchmaskx)); \
2574 })
2575
2576 static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
2577                          void *matchmaskp, u8 bsize)
2578 {
2579         bool same = false;
2580
2581         switch (bsize) {
2582         case 8:
2583                 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
2584                 break;
2585         case 16:
2586                 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
2587                 break;
2588         case 32:
2589                 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
2590                 break;
2591         }
2592
2593         return same;
2594 }
2595
2596 static struct mlx5_fields fields[] = {
2597         OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
2598         OFFLOAD(DMAC_15_0,  16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
2599         OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
2600         OFFLOAD(SMAC_15_0,  16, U16_MAX, eth.h_source[4], 0, smac_15_0),
2601         OFFLOAD(ETHERTYPE,  16, U16_MAX, eth.h_proto, 0, ethertype),
2602         OFFLOAD(FIRST_VID,  16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
2603
2604         OFFLOAD(IP_DSCP, 8,    0xfc, ip4.tos,   0, ip_dscp),
2605         OFFLOAD(IP_TTL,  8,  U8_MAX, ip4.ttl,   0, ttl_hoplimit),
2606         OFFLOAD(SIPV4,  32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2607         OFFLOAD(DIPV4,  32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2608
2609         OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
2610                 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
2611         OFFLOAD(SIPV6_95_64,  32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
2612                 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
2613         OFFLOAD(SIPV6_63_32,  32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
2614                 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
2615         OFFLOAD(SIPV6_31_0,   32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
2616                 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
2617         OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
2618                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
2619         OFFLOAD(DIPV6_95_64,  32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
2620                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
2621         OFFLOAD(DIPV6_63_32,  32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
2622                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
2623         OFFLOAD(DIPV6_31_0,   32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
2624                 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
2625         OFFLOAD(IPV6_HOPLIMIT, 8,  U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
2626
2627         OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source,  0, tcp_sport),
2628         OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest,    0, tcp_dport),
2629         /* in linux iphdr tcp_flags is 8 bits long */
2630         OFFLOAD(TCP_FLAGS,  8,  U8_MAX, tcp.ack_seq, 5, tcp_flags),
2631
2632         OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
2633         OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest,   0, udp_dport),
2634 };
2635
2636 static int offload_pedit_fields(struct mlx5e_priv *priv,
2637                                 int namespace,
2638                                 struct pedit_headers_action *hdrs,
2639                                 struct mlx5e_tc_flow_parse_attr *parse_attr,
2640                                 u32 *action_flags,
2641                                 struct netlink_ext_ack *extack)
2642 {
2643         struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
2644         int i, action_size, first, last, next_z;
2645         void *headers_c, *headers_v, *action, *vals_p;
2646         u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
2647         struct mlx5e_tc_mod_hdr_acts *mod_acts;
2648         struct mlx5_fields *f;
2649         unsigned long mask;
2650         __be32 mask_be32;
2651         __be16 mask_be16;
2652         int err;
2653         u8 cmd;
2654
2655         mod_acts = &parse_attr->mod_hdr_acts;
2656         headers_c = get_match_headers_criteria(*action_flags, &parse_attr->spec);
2657         headers_v = get_match_headers_value(*action_flags, &parse_attr->spec);
2658
2659         set_masks = &hdrs[0].masks;
2660         add_masks = &hdrs[1].masks;
2661         set_vals = &hdrs[0].vals;
2662         add_vals = &hdrs[1].vals;
2663
2664         action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2665
2666         for (i = 0; i < ARRAY_SIZE(fields); i++) {
2667                 bool skip;
2668
2669                 f = &fields[i];
2670                 /* avoid seeing bits set from previous iterations */
2671                 s_mask = 0;
2672                 a_mask = 0;
2673
2674                 s_masks_p = (void *)set_masks + f->offset;
2675                 a_masks_p = (void *)add_masks + f->offset;
2676
2677                 s_mask = *s_masks_p & f->field_mask;
2678                 a_mask = *a_masks_p & f->field_mask;
2679
2680                 if (!s_mask && !a_mask) /* nothing to offload here */
2681                         continue;
2682
2683                 if (s_mask && a_mask) {
2684                         NL_SET_ERR_MSG_MOD(extack,
2685                                            "can't set and add to the same HW field");
2686                         printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
2687                         return -EOPNOTSUPP;
2688                 }
2689
2690                 skip = false;
2691                 if (s_mask) {
2692                         void *match_mask = headers_c + f->match_offset;
2693                         void *match_val = headers_v + f->match_offset;
2694
2695                         cmd  = MLX5_ACTION_TYPE_SET;
2696                         mask = s_mask;
2697                         vals_p = (void *)set_vals + f->offset;
2698                         /* don't rewrite if we have a match on the same value */
2699                         if (cmp_val_mask(vals_p, s_masks_p, match_val,
2700                                          match_mask, f->field_bsize))
2701                                 skip = true;
2702                         /* clear to denote we consumed this field */
2703                         *s_masks_p &= ~f->field_mask;
2704                 } else {
2705                         cmd  = MLX5_ACTION_TYPE_ADD;
2706                         mask = a_mask;
2707                         vals_p = (void *)add_vals + f->offset;
2708                         /* add 0 is no change */
2709                         if ((*(u32 *)vals_p & f->field_mask) == 0)
2710                                 skip = true;
2711                         /* clear to denote we consumed this field */
2712                         *a_masks_p &= ~f->field_mask;
2713                 }
2714                 if (skip)
2715                         continue;
2716
2717                 if (f->field_bsize == 32) {
2718                         mask_be32 = (__be32)mask;
2719                         mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2720                 } else if (f->field_bsize == 16) {
2721                         mask_be32 = (__be32)mask;
2722                         mask_be16 = *(__be16 *)&mask_be32;
2723                         mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2724                 }
2725
2726                 first = find_first_bit(&mask, f->field_bsize);
2727                 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
2728                 last  = find_last_bit(&mask, f->field_bsize);
2729                 if (first < next_z && next_z < last) {
2730                         NL_SET_ERR_MSG_MOD(extack,
2731                                            "rewrite of few sub-fields isn't supported");
2732                         printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
2733                                mask);
2734                         return -EOPNOTSUPP;
2735                 }
2736
2737                 err = alloc_mod_hdr_actions(priv->mdev, namespace, mod_acts);
2738                 if (err) {
2739                         NL_SET_ERR_MSG_MOD(extack,
2740                                            "too many pedit actions, can't offload");
2741                         mlx5_core_warn(priv->mdev,
2742                                        "mlx5: parsed %d pedit actions, can't do more\n",
2743                                        mod_acts->num_actions);
2744                         return err;
2745                 }
2746
2747                 action = mod_acts->actions +
2748                          (mod_acts->num_actions * action_size);
2749                 MLX5_SET(set_action_in, action, action_type, cmd);
2750                 MLX5_SET(set_action_in, action, field, f->field);
2751
2752                 if (cmd == MLX5_ACTION_TYPE_SET) {
2753                         int start;
2754
2755                         /* if field is bit sized it can start not from first bit */
2756                         start = find_first_bit((unsigned long *)&f->field_mask,
2757                                                f->field_bsize);
2758
2759                         MLX5_SET(set_action_in, action, offset, first - start);
2760                         /* length is num of bits to be written, zero means length of 32 */
2761                         MLX5_SET(set_action_in, action, length, (last - first + 1));
2762                 }
2763
2764                 if (f->field_bsize == 32)
2765                         MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
2766                 else if (f->field_bsize == 16)
2767                         MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
2768                 else if (f->field_bsize == 8)
2769                         MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
2770
2771                 ++mod_acts->num_actions;
2772         }
2773
2774         return 0;
2775 }
2776
2777 static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2778                                                   int namespace)
2779 {
2780         if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2781                 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2782         else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2783                 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2784 }
2785
2786 int alloc_mod_hdr_actions(struct mlx5_core_dev *mdev,
2787                           int namespace,
2788                           struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
2789 {
2790         int action_size, new_num_actions, max_hw_actions;
2791         size_t new_sz, old_sz;
2792         void *ret;
2793
2794         if (mod_hdr_acts->num_actions < mod_hdr_acts->max_actions)
2795                 return 0;
2796
2797         action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2798
2799         max_hw_actions = mlx5e_flow_namespace_max_modify_action(mdev,
2800                                                                 namespace);
2801         new_num_actions = min(max_hw_actions,
2802                               mod_hdr_acts->actions ?
2803                               mod_hdr_acts->max_actions * 2 : 1);
2804         if (mod_hdr_acts->max_actions == new_num_actions)
2805                 return -ENOSPC;
2806
2807         new_sz = action_size * new_num_actions;
2808         old_sz = mod_hdr_acts->max_actions * action_size;
2809         ret = krealloc(mod_hdr_acts->actions, new_sz, GFP_KERNEL);
2810         if (!ret)
2811                 return -ENOMEM;
2812
2813         memset(ret + old_sz, 0, new_sz - old_sz);
2814         mod_hdr_acts->actions = ret;
2815         mod_hdr_acts->max_actions = new_num_actions;
2816
2817         return 0;
2818 }
2819
2820 void dealloc_mod_hdr_actions(struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
2821 {
2822         kfree(mod_hdr_acts->actions);
2823         mod_hdr_acts->actions = NULL;
2824         mod_hdr_acts->num_actions = 0;
2825         mod_hdr_acts->max_actions = 0;
2826 }
2827
2828 static const struct pedit_headers zero_masks = {};
2829
2830 static int parse_tc_pedit_action(struct mlx5e_priv *priv,
2831                                  const struct flow_action_entry *act, int namespace,
2832                                  struct pedit_headers_action *hdrs,
2833                                  struct netlink_ext_ack *extack)
2834 {
2835         u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2836         int err = -EOPNOTSUPP;
2837         u32 mask, val, offset;
2838         u8 htype;
2839
2840         htype = act->mangle.htype;
2841         err = -EOPNOTSUPP; /* can't be all optimistic */
2842
2843         if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2844                 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2845                 goto out_err;
2846         }
2847
2848         if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2849                 NL_SET_ERR_MSG_MOD(extack,
2850                                    "The pedit offload action is not supported");
2851                 goto out_err;
2852         }
2853
2854         mask = act->mangle.mask;
2855         val = act->mangle.val;
2856         offset = act->mangle.offset;
2857
2858         err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2859         if (err)
2860                 goto out_err;
2861
2862         hdrs[cmd].pedits++;
2863
2864         return 0;
2865 out_err:
2866         return err;
2867 }
2868
2869 static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2870                                  struct mlx5e_tc_flow_parse_attr *parse_attr,
2871                                  struct pedit_headers_action *hdrs,
2872                                  u32 *action_flags,
2873                                  struct netlink_ext_ack *extack)
2874 {
2875         struct pedit_headers *cmd_masks;
2876         int err;
2877         u8 cmd;
2878
2879         err = offload_pedit_fields(priv, namespace, hdrs, parse_attr,
2880                                    action_flags, extack);
2881         if (err < 0)
2882                 goto out_dealloc_parsed_actions;
2883
2884         for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
2885                 cmd_masks = &hdrs[cmd].masks;
2886                 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
2887                         NL_SET_ERR_MSG_MOD(extack,
2888                                            "attempt to offload an unsupported field");
2889                         netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
2890                         print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2891                                        16, 1, cmd_masks, sizeof(zero_masks), true);
2892                         err = -EOPNOTSUPP;
2893                         goto out_dealloc_parsed_actions;
2894                 }
2895         }
2896
2897         return 0;
2898
2899 out_dealloc_parsed_actions:
2900         dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
2901         return err;
2902 }
2903
2904 static bool csum_offload_supported(struct mlx5e_priv *priv,
2905                                    u32 action,
2906                                    u32 update_flags,
2907                                    struct netlink_ext_ack *extack)
2908 {
2909         u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2910                          TCA_CSUM_UPDATE_FLAG_UDP;
2911
2912         /*  The HW recalcs checksums only if re-writing headers */
2913         if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
2914                 NL_SET_ERR_MSG_MOD(extack,
2915                                    "TC csum action is only offloaded with pedit");
2916                 netdev_warn(priv->netdev,
2917                             "TC csum action is only offloaded with pedit\n");
2918                 return false;
2919         }
2920
2921         if (update_flags & ~prot_flags) {
2922                 NL_SET_ERR_MSG_MOD(extack,
2923                                    "can't offload TC csum action for some header/s");
2924                 netdev_warn(priv->netdev,
2925                             "can't offload TC csum action for some header/s - flags %#x\n",
2926                             update_flags);
2927                 return false;
2928         }
2929
2930         return true;
2931 }
2932
2933 struct ip_ttl_word {
2934         __u8    ttl;
2935         __u8    protocol;
2936         __sum16 check;
2937 };
2938
2939 struct ipv6_hoplimit_word {
2940         __be16  payload_len;
2941         __u8    nexthdr;
2942         __u8    hop_limit;
2943 };
2944
2945 static int is_action_keys_supported(const struct flow_action_entry *act,
2946                                     bool ct_flow, bool *modify_ip_header,
2947                                     struct netlink_ext_ack *extack)
2948 {
2949         u32 mask, offset;
2950         u8 htype;
2951
2952         htype = act->mangle.htype;
2953         offset = act->mangle.offset;
2954         mask = ~act->mangle.mask;
2955         /* For IPv4 & IPv6 header check 4 byte word,
2956          * to determine that modified fields
2957          * are NOT ttl & hop_limit only.
2958          */
2959         if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
2960                 struct ip_ttl_word *ttl_word =
2961                         (struct ip_ttl_word *)&mask;
2962
2963                 if (offset != offsetof(struct iphdr, ttl) ||
2964                     ttl_word->protocol ||
2965                     ttl_word->check) {
2966                         *modify_ip_header = true;
2967                 }
2968
2969                 if (ct_flow && offset >= offsetof(struct iphdr, saddr)) {
2970                         NL_SET_ERR_MSG_MOD(extack,
2971                                            "can't offload re-write of ipv4 address with action ct");
2972                         return -EOPNOTSUPP;
2973                 }
2974         } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
2975                 struct ipv6_hoplimit_word *hoplimit_word =
2976                         (struct ipv6_hoplimit_word *)&mask;
2977
2978                 if (offset != offsetof(struct ipv6hdr, payload_len) ||
2979                     hoplimit_word->payload_len ||
2980                     hoplimit_word->nexthdr) {
2981                         *modify_ip_header = true;
2982                 }
2983
2984                 if (ct_flow && offset >= offsetof(struct ipv6hdr, saddr)) {
2985                         NL_SET_ERR_MSG_MOD(extack,
2986                                            "can't offload re-write of ipv6 address with action ct");
2987                         return -EOPNOTSUPP;
2988                 }
2989         } else if (ct_flow && (htype == FLOW_ACT_MANGLE_HDR_TYPE_TCP ||
2990                                htype == FLOW_ACT_MANGLE_HDR_TYPE_UDP)) {
2991                 NL_SET_ERR_MSG_MOD(extack,
2992                                    "can't offload re-write of transport header ports with action ct");
2993                 return -EOPNOTSUPP;
2994         }
2995
2996         return 0;
2997 }
2998
2999 static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
3000                                           struct flow_action *flow_action,
3001                                           u32 actions, bool ct_flow,
3002                                           struct netlink_ext_ack *extack)
3003 {
3004         const struct flow_action_entry *act;
3005         bool modify_ip_header;
3006         void *headers_v;
3007         u16 ethertype;
3008         u8 ip_proto;
3009         int i, err;
3010
3011         headers_v = get_match_headers_value(actions, spec);
3012         ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
3013
3014         /* for non-IP we only re-write MACs, so we're okay */
3015         if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
3016                 goto out_ok;
3017
3018         modify_ip_header = false;
3019         flow_action_for_each(i, act, flow_action) {
3020                 if (act->id != FLOW_ACTION_MANGLE &&
3021                     act->id != FLOW_ACTION_ADD)
3022                         continue;
3023
3024                 err = is_action_keys_supported(act, ct_flow,
3025                                                &modify_ip_header, extack);
3026                 if (err)
3027                         return err;
3028         }
3029
3030         ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
3031         if (modify_ip_header && ip_proto != IPPROTO_TCP &&
3032             ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
3033                 NL_SET_ERR_MSG_MOD(extack,
3034                                    "can't offload re-write of non TCP/UDP");
3035                 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
3036                 return false;
3037         }
3038
3039 out_ok:
3040         return true;
3041 }
3042
3043 static bool actions_match_supported(struct mlx5e_priv *priv,
3044                                     struct flow_action *flow_action,
3045                                     struct mlx5e_tc_flow_parse_attr *parse_attr,
3046                                     struct mlx5e_tc_flow *flow,
3047                                     struct netlink_ext_ack *extack)
3048 {
3049         bool ct_flow;
3050         u32 actions;
3051
3052         ct_flow = flow_flag_test(flow, CT);
3053         if (mlx5e_is_eswitch_flow(flow)) {
3054                 actions = flow->esw_attr->action;
3055
3056                 if (flow->esw_attr->split_count && ct_flow) {
3057                         /* All registers used by ct are cleared when using
3058                          * split rules.
3059                          */
3060                         NL_SET_ERR_MSG_MOD(extack,
3061                                            "Can't offload mirroring with action ct");
3062                         return false;
3063                 }
3064         } else {
3065                 actions = flow->nic_attr->action;
3066         }
3067
3068         if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3069                 return modify_header_match_supported(&parse_attr->spec,
3070                                                      flow_action, actions,
3071                                                      ct_flow, extack);
3072
3073         return true;
3074 }
3075
3076 static bool same_port_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3077 {
3078         return priv->mdev == peer_priv->mdev;
3079 }
3080
3081 static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3082 {
3083         struct mlx5_core_dev *fmdev, *pmdev;
3084         u64 fsystem_guid, psystem_guid;
3085
3086         fmdev = priv->mdev;
3087         pmdev = peer_priv->mdev;
3088
3089         fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3090         psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
3091
3092         return (fsystem_guid == psystem_guid);
3093 }
3094
3095 static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
3096                                    const struct flow_action_entry *act,
3097                                    struct mlx5e_tc_flow_parse_attr *parse_attr,
3098                                    struct pedit_headers_action *hdrs,
3099                                    u32 *action, struct netlink_ext_ack *extack)
3100 {
3101         u16 mask16 = VLAN_VID_MASK;
3102         u16 val16 = act->vlan.vid & VLAN_VID_MASK;
3103         const struct flow_action_entry pedit_act = {
3104                 .id = FLOW_ACTION_MANGLE,
3105                 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
3106                 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
3107                 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
3108                 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
3109         };
3110         u8 match_prio_mask, match_prio_val;
3111         void *headers_c, *headers_v;
3112         int err;
3113
3114         headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
3115         headers_v = get_match_headers_value(*action, &parse_attr->spec);
3116
3117         if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
3118               MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
3119                 NL_SET_ERR_MSG_MOD(extack,
3120                                    "VLAN rewrite action must have VLAN protocol match");
3121                 return -EOPNOTSUPP;
3122         }
3123
3124         match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
3125         match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
3126         if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
3127                 NL_SET_ERR_MSG_MOD(extack,
3128                                    "Changing VLAN prio is not supported");
3129                 return -EOPNOTSUPP;
3130         }
3131
3132         err = parse_tc_pedit_action(priv, &pedit_act, namespace, hdrs, NULL);
3133         *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3134
3135         return err;
3136 }
3137
3138 static int
3139 add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
3140                                  struct mlx5e_tc_flow_parse_attr *parse_attr,
3141                                  struct pedit_headers_action *hdrs,
3142                                  u32 *action, struct netlink_ext_ack *extack)
3143 {
3144         const struct flow_action_entry prio_tag_act = {
3145                 .vlan.vid = 0,
3146                 .vlan.prio =
3147                         MLX5_GET(fte_match_set_lyr_2_4,
3148                                  get_match_headers_value(*action,
3149                                                          &parse_attr->spec),
3150                                  first_prio) &
3151                         MLX5_GET(fte_match_set_lyr_2_4,
3152                                  get_match_headers_criteria(*action,
3153                                                             &parse_attr->spec),
3154                                  first_prio),
3155         };
3156
3157         return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
3158                                        &prio_tag_act, parse_attr, hdrs, action,
3159                                        extack);
3160 }
3161
3162 static int parse_tc_nic_actions(struct mlx5e_priv *priv,
3163                                 struct flow_action *flow_action,
3164                                 struct mlx5e_tc_flow_parse_attr *parse_attr,
3165                                 struct mlx5e_tc_flow *flow,
3166                                 struct netlink_ext_ack *extack)
3167 {
3168         struct mlx5_nic_flow_attr *attr = flow->nic_attr;
3169         struct pedit_headers_action hdrs[2] = {};
3170         const struct flow_action_entry *act;
3171         u32 action = 0;
3172         int err, i;
3173
3174         if (!flow_action_has_entries(flow_action))
3175                 return -EINVAL;
3176
3177         if (!flow_action_hw_stats_check(flow_action, extack,
3178                                         FLOW_ACTION_HW_STATS_DELAYED_BIT))
3179                 return -EOPNOTSUPP;
3180
3181         attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
3182
3183         flow_action_for_each(i, act, flow_action) {
3184                 switch (act->id) {
3185                 case FLOW_ACTION_ACCEPT:
3186                         action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3187                                   MLX5_FLOW_CONTEXT_ACTION_COUNT;
3188                         break;
3189                 case FLOW_ACTION_DROP:
3190                         action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
3191                         if (MLX5_CAP_FLOWTABLE(priv->mdev,
3192                                                flow_table_properties_nic_receive.flow_counter))
3193                                 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3194                         break;
3195                 case FLOW_ACTION_MANGLE:
3196                 case FLOW_ACTION_ADD:
3197                         err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
3198                                                     hdrs, extack);
3199                         if (err)
3200                                 return err;
3201
3202                         action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
3203                                   MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3204                         break;
3205                 case FLOW_ACTION_VLAN_MANGLE:
3206                         err = add_vlan_rewrite_action(priv,
3207                                                       MLX5_FLOW_NAMESPACE_KERNEL,
3208                                                       act, parse_attr, hdrs,
3209                                                       &action, extack);
3210                         if (err)
3211                                 return err;
3212
3213                         break;
3214                 case FLOW_ACTION_CSUM:
3215                         if (csum_offload_supported(priv, action,
3216                                                    act->csum_flags,
3217                                                    extack))
3218                                 break;
3219
3220                         return -EOPNOTSUPP;
3221                 case FLOW_ACTION_REDIRECT: {
3222                         struct net_device *peer_dev = act->dev;
3223
3224                         if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
3225                             same_hw_devs(priv, netdev_priv(peer_dev))) {
3226                                 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
3227                                 flow_flag_set(flow, HAIRPIN);
3228                                 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3229                                           MLX5_FLOW_CONTEXT_ACTION_COUNT;
3230                         } else {
3231                                 NL_SET_ERR_MSG_MOD(extack,
3232                                                    "device is not on same HW, can't offload");
3233                                 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
3234                                             peer_dev->name);
3235                                 return -EINVAL;
3236                         }
3237                         }
3238                         break;
3239                 case FLOW_ACTION_MARK: {
3240                         u32 mark = act->mark;
3241
3242                         if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
3243                                 NL_SET_ERR_MSG_MOD(extack,
3244                                                    "Bad flow mark - only 16 bit is supported");
3245                                 return -EINVAL;
3246                         }
3247
3248                         attr->flow_tag = mark;
3249                         action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3250                         }
3251                         break;
3252                 default:
3253                         NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3254                         return -EOPNOTSUPP;
3255                 }
3256         }
3257
3258         if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3259             hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
3260                 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
3261                                             parse_attr, hdrs, &action, extack);
3262                 if (err)
3263                         return err;
3264                 /* in case all pedit actions are skipped, remove the MOD_HDR
3265                  * flag.
3266                  */
3267                 if (parse_attr->mod_hdr_acts.num_actions == 0) {
3268                         action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3269                         dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
3270                 }
3271         }
3272
3273         attr->action = action;
3274         if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
3275                 return -EOPNOTSUPP;
3276
3277         return 0;
3278 }
3279
3280 struct encap_key {
3281         const struct ip_tunnel_key *ip_tun_key;
3282         struct mlx5e_tc_tunnel *tc_tunnel;
3283 };
3284
3285 static inline int cmp_encap_info(struct encap_key *a,
3286                                  struct encap_key *b)
3287 {
3288         return memcmp(a->ip_tun_key, b->ip_tun_key, sizeof(*a->ip_tun_key)) ||
3289                a->tc_tunnel->tunnel_type != b->tc_tunnel->tunnel_type;
3290 }
3291
3292 static inline int hash_encap_info(struct encap_key *key)
3293 {
3294         return jhash(key->ip_tun_key, sizeof(*key->ip_tun_key),
3295                      key->tc_tunnel->tunnel_type);
3296 }
3297
3298
3299 static bool is_merged_eswitch_vfs(struct mlx5e_priv *priv,
3300                                   struct net_device *peer_netdev)
3301 {
3302         struct mlx5e_priv *peer_priv;
3303
3304         peer_priv = netdev_priv(peer_netdev);
3305
3306         return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
3307                 mlx5e_eswitch_vf_rep(priv->netdev) &&
3308                 mlx5e_eswitch_vf_rep(peer_netdev) &&
3309                 same_hw_devs(priv, peer_priv));
3310 }
3311
3312 bool mlx5e_encap_take(struct mlx5e_encap_entry *e)
3313 {
3314         return refcount_inc_not_zero(&e->refcnt);
3315 }
3316
3317 static struct mlx5e_encap_entry *
3318 mlx5e_encap_get(struct mlx5e_priv *priv, struct encap_key *key,
3319                 uintptr_t hash_key)
3320 {
3321         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3322         struct mlx5e_encap_entry *e;
3323         struct encap_key e_key;
3324
3325         hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
3326                                    encap_hlist, hash_key) {
3327                 e_key.ip_tun_key = &e->tun_info->key;
3328                 e_key.tc_tunnel = e->tunnel;
3329                 if (!cmp_encap_info(&e_key, key) &&
3330                     mlx5e_encap_take(e))
3331                         return e;
3332         }
3333
3334         return NULL;
3335 }
3336
3337 static struct ip_tunnel_info *dup_tun_info(const struct ip_tunnel_info *tun_info)
3338 {
3339         size_t tun_size = sizeof(*tun_info) + tun_info->options_len;
3340
3341         return kmemdup(tun_info, tun_size, GFP_KERNEL);
3342 }
3343
3344 static bool is_duplicated_encap_entry(struct mlx5e_priv *priv,
3345                                       struct mlx5e_tc_flow *flow,
3346                                       int out_index,
3347                                       struct mlx5e_encap_entry *e,
3348                                       struct netlink_ext_ack *extack)
3349 {
3350         int i;
3351
3352         for (i = 0; i < out_index; i++) {
3353                 if (flow->encaps[i].e != e)
3354                         continue;
3355                 NL_SET_ERR_MSG_MOD(extack, "can't duplicate encap action");
3356                 netdev_err(priv->netdev, "can't duplicate encap action\n");
3357                 return true;
3358         }
3359
3360         return false;
3361 }
3362
3363 static int mlx5e_attach_encap(struct mlx5e_priv *priv,
3364                               struct mlx5e_tc_flow *flow,
3365                               struct net_device *mirred_dev,
3366                               int out_index,
3367                               struct netlink_ext_ack *extack,
3368                               struct net_device **encap_dev,
3369                               bool *encap_valid)
3370 {
3371         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3372         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3373         struct mlx5e_tc_flow_parse_attr *parse_attr;
3374         const struct ip_tunnel_info *tun_info;
3375         struct encap_key key;
3376         struct mlx5e_encap_entry *e;
3377         unsigned short family;
3378         uintptr_t hash_key;
3379         int err = 0;
3380
3381         parse_attr = attr->parse_attr;
3382         tun_info = parse_attr->tun_info[out_index];
3383         family = ip_tunnel_info_af(tun_info);
3384         key.ip_tun_key = &tun_info->key;
3385         key.tc_tunnel = mlx5e_get_tc_tun(mirred_dev);
3386         if (!key.tc_tunnel) {
3387                 NL_SET_ERR_MSG_MOD(extack, "Unsupported tunnel");
3388                 return -EOPNOTSUPP;
3389         }
3390
3391         hash_key = hash_encap_info(&key);
3392
3393         mutex_lock(&esw->offloads.encap_tbl_lock);
3394         e = mlx5e_encap_get(priv, &key, hash_key);
3395
3396         /* must verify if encap is valid or not */
3397         if (e) {
3398                 /* Check that entry was not already attached to this flow */
3399                 if (is_duplicated_encap_entry(priv, flow, out_index, e, extack)) {
3400                         err = -EOPNOTSUPP;
3401                         goto out_err;
3402                 }
3403
3404                 mutex_unlock(&esw->offloads.encap_tbl_lock);
3405                 wait_for_completion(&e->res_ready);
3406
3407                 /* Protect against concurrent neigh update. */
3408                 mutex_lock(&esw->offloads.encap_tbl_lock);
3409                 if (e->compl_result < 0) {
3410                         err = -EREMOTEIO;
3411                         goto out_err;
3412                 }
3413                 goto attach_flow;
3414         }
3415
3416         e = kzalloc(sizeof(*e), GFP_KERNEL);
3417         if (!e) {
3418                 err = -ENOMEM;
3419                 goto out_err;
3420         }
3421
3422         refcount_set(&e->refcnt, 1);
3423         init_completion(&e->res_ready);
3424
3425         tun_info = dup_tun_info(tun_info);
3426         if (!tun_info) {
3427                 err = -ENOMEM;
3428                 goto out_err_init;
3429         }
3430         e->tun_info = tun_info;
3431         err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack);
3432         if (err)
3433                 goto out_err_init;
3434
3435         INIT_LIST_HEAD(&e->flows);
3436         hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
3437         mutex_unlock(&esw->offloads.encap_tbl_lock);
3438
3439         if (family == AF_INET)
3440                 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e);
3441         else if (family == AF_INET6)
3442                 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e);
3443
3444         /* Protect against concurrent neigh update. */
3445         mutex_lock(&esw->offloads.encap_tbl_lock);
3446         complete_all(&e->res_ready);
3447         if (err) {
3448                 e->compl_result = err;
3449                 goto out_err;
3450         }
3451         e->compl_result = 1;
3452
3453 attach_flow:
3454         flow->encaps[out_index].e = e;
3455         list_add(&flow->encaps[out_index].list, &e->flows);
3456         flow->encaps[out_index].index = out_index;
3457         *encap_dev = e->out_dev;
3458         if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
3459                 attr->dests[out_index].pkt_reformat = e->pkt_reformat;
3460                 attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
3461                 *encap_valid = true;
3462         } else {
3463                 *encap_valid = false;
3464         }
3465         mutex_unlock(&esw->offloads.encap_tbl_lock);
3466
3467         return err;
3468
3469 out_err:
3470         mutex_unlock(&esw->offloads.encap_tbl_lock);
3471         if (e)
3472                 mlx5e_encap_put(priv, e);
3473         return err;
3474
3475 out_err_init:
3476         mutex_unlock(&esw->offloads.encap_tbl_lock);
3477         kfree(tun_info);
3478         kfree(e);
3479         return err;
3480 }
3481
3482 static int parse_tc_vlan_action(struct mlx5e_priv *priv,
3483                                 const struct flow_action_entry *act,
3484                                 struct mlx5_esw_flow_attr *attr,
3485                                 u32 *action)
3486 {
3487         u8 vlan_idx = attr->total_vlan;
3488
3489         if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
3490                 return -EOPNOTSUPP;
3491
3492         switch (act->id) {
3493         case FLOW_ACTION_VLAN_POP:
3494                 if (vlan_idx) {
3495                         if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3496                                                                  MLX5_FS_VLAN_DEPTH))
3497                                 return -EOPNOTSUPP;
3498
3499                         *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
3500                 } else {
3501                         *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3502                 }
3503                 break;
3504         case FLOW_ACTION_VLAN_PUSH:
3505                 attr->vlan_vid[vlan_idx] = act->vlan.vid;
3506                 attr->vlan_prio[vlan_idx] = act->vlan.prio;
3507                 attr->vlan_proto[vlan_idx] = act->vlan.proto;
3508                 if (!attr->vlan_proto[vlan_idx])
3509                         attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
3510
3511                 if (vlan_idx) {
3512                         if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
3513                                                                  MLX5_FS_VLAN_DEPTH))
3514                                 return -EOPNOTSUPP;
3515
3516                         *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
3517                 } else {
3518                         if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
3519                             (act->vlan.proto != htons(ETH_P_8021Q) ||
3520                              act->vlan.prio))
3521                                 return -EOPNOTSUPP;
3522
3523                         *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
3524                 }
3525                 break;
3526         default:
3527                 return -EINVAL;
3528         }
3529
3530         attr->total_vlan = vlan_idx + 1;
3531
3532         return 0;
3533 }
3534
3535 static int add_vlan_push_action(struct mlx5e_priv *priv,
3536                                 struct mlx5_esw_flow_attr *attr,
3537                                 struct net_device **out_dev,
3538                                 u32 *action)
3539 {
3540         struct net_device *vlan_dev = *out_dev;
3541         struct flow_action_entry vlan_act = {
3542                 .id = FLOW_ACTION_VLAN_PUSH,
3543                 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
3544                 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
3545                 .vlan.prio = 0,
3546         };
3547         int err;
3548
3549         err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
3550         if (err)
3551                 return err;
3552
3553         *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev),
3554                                         dev_get_iflink(vlan_dev));
3555         if (is_vlan_dev(*out_dev))
3556                 err = add_vlan_push_action(priv, attr, out_dev, action);
3557
3558         return err;
3559 }
3560
3561 static int add_vlan_pop_action(struct mlx5e_priv *priv,
3562                                struct mlx5_esw_flow_attr *attr,
3563                                u32 *action)
3564 {
3565         struct flow_action_entry vlan_act = {
3566                 .id = FLOW_ACTION_VLAN_POP,
3567         };
3568         int nest_level, err = 0;
3569
3570         nest_level = attr->parse_attr->filter_dev->lower_level -
3571                                                 priv->netdev->lower_level;
3572         while (nest_level--) {
3573                 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
3574                 if (err)
3575                         return err;
3576         }
3577
3578         return err;
3579 }
3580
3581 static bool same_hw_reps(struct mlx5e_priv *priv,
3582                          struct net_device *peer_netdev)
3583 {
3584         struct mlx5e_priv *peer_priv;
3585
3586         peer_priv = netdev_priv(peer_netdev);
3587
3588         return mlx5e_eswitch_rep(priv->netdev) &&
3589                mlx5e_eswitch_rep(peer_netdev) &&
3590                same_hw_devs(priv, peer_priv);
3591 }
3592
3593 static bool is_lag_dev(struct mlx5e_priv *priv,
3594                        struct net_device *peer_netdev)
3595 {
3596         return ((mlx5_lag_is_sriov(priv->mdev) ||
3597                  mlx5_lag_is_multipath(priv->mdev)) &&
3598                  same_hw_reps(priv, peer_netdev));
3599 }
3600
3601 bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
3602                                     struct net_device *out_dev)
3603 {
3604         if (is_merged_eswitch_vfs(priv, out_dev))
3605                 return true;
3606
3607         if (is_lag_dev(priv, out_dev))
3608                 return true;
3609
3610         return mlx5e_eswitch_rep(out_dev) &&
3611                same_port_devs(priv, netdev_priv(out_dev));
3612 }
3613
3614 static bool is_duplicated_output_device(struct net_device *dev,
3615                                         struct net_device *out_dev,
3616                                         int *ifindexes, int if_count,
3617                                         struct netlink_ext_ack *extack)
3618 {
3619         int i;
3620
3621         for (i = 0; i < if_count; i++) {
3622                 if (ifindexes[i] == out_dev->ifindex) {
3623                         NL_SET_ERR_MSG_MOD(extack,
3624                                            "can't duplicate output to same device");
3625                         netdev_err(dev, "can't duplicate output to same device: %s\n",
3626                                    out_dev->name);
3627                         return true;
3628                 }
3629         }
3630
3631         return false;
3632 }
3633
3634 static int mlx5_validate_goto_chain(struct mlx5_eswitch *esw,
3635                                     struct mlx5e_tc_flow *flow,
3636                                     const struct flow_action_entry *act,
3637                                     u32 actions,
3638                                     struct netlink_ext_ack *extack)
3639 {
3640         u32 max_chain = mlx5_esw_chains_get_chain_range(esw);
3641         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3642         bool ft_flow = mlx5e_is_ft_flow(flow);
3643         u32 dest_chain = act->chain_index;
3644
3645         if (ft_flow) {
3646                 NL_SET_ERR_MSG_MOD(extack, "Goto action is not supported");
3647                 return -EOPNOTSUPP;
3648         }
3649
3650         if (!mlx5_esw_chains_backwards_supported(esw) &&
3651             dest_chain <= attr->chain) {
3652                 NL_SET_ERR_MSG_MOD(extack,
3653                                    "Goto lower numbered chain isn't supported");
3654                 return -EOPNOTSUPP;
3655         }
3656         if (dest_chain > max_chain) {
3657                 NL_SET_ERR_MSG_MOD(extack,
3658                                    "Requested destination chain is out of supported range");
3659                 return -EOPNOTSUPP;
3660         }
3661
3662         if (actions & (MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT |
3663                        MLX5_FLOW_CONTEXT_ACTION_DECAP) &&
3664             !MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, reformat_and_fwd_to_table)) {
3665                 NL_SET_ERR_MSG_MOD(extack,
3666                                    "Goto chain is not allowed if action has reformat or decap");
3667                 return -EOPNOTSUPP;
3668         }
3669
3670         return 0;
3671 }
3672
3673 static int verify_uplink_forwarding(struct mlx5e_priv *priv,
3674                                     struct mlx5e_tc_flow *flow,
3675                                     struct net_device *out_dev,
3676                                     struct netlink_ext_ack *extack)
3677 {
3678         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3679         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3680         struct mlx5e_rep_priv *rep_priv;
3681
3682         /* Forwarding non encapsulated traffic between
3683          * uplink ports is allowed only if
3684          * termination_table_raw_traffic cap is set.
3685          *
3686          * Input vport was stored esw_attr->in_rep.
3687          * In LAG case, *priv* is the private data of
3688          * uplink which may be not the input vport.
3689          */
3690         rep_priv = mlx5e_rep_to_rep_priv(attr->in_rep);
3691
3692         if (!(mlx5e_eswitch_uplink_rep(rep_priv->netdev) &&
3693               mlx5e_eswitch_uplink_rep(out_dev)))
3694                 return 0;
3695
3696         if (!MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev,
3697                                         termination_table_raw_traffic)) {
3698                 NL_SET_ERR_MSG_MOD(extack,
3699                                    "devices are both uplink, can't offload forwarding");
3700                         pr_err("devices %s %s are both uplink, can't offload forwarding\n",
3701                                priv->netdev->name, out_dev->name);
3702                         return -EOPNOTSUPP;
3703         } else if (out_dev != rep_priv->netdev) {
3704                 NL_SET_ERR_MSG_MOD(extack,
3705                                    "devices are not the same uplink, can't offload forwarding");
3706                 pr_err("devices %s %s are both uplink but not the same, can't offload forwarding\n",
3707                        priv->netdev->name, out_dev->name);
3708                 return -EOPNOTSUPP;
3709         }
3710         return 0;
3711 }
3712
3713 static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
3714                                 struct flow_action *flow_action,
3715                                 struct mlx5e_tc_flow *flow,
3716                                 struct netlink_ext_ack *extack)
3717 {
3718         struct pedit_headers_action hdrs[2] = {};
3719         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3720         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3721         struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
3722         struct mlx5e_rep_priv *rpriv = priv->ppriv;
3723         const struct ip_tunnel_info *info = NULL;
3724         int ifindexes[MLX5_MAX_FLOW_FWD_VPORTS];
3725         bool ft_flow = mlx5e_is_ft_flow(flow);
3726         const struct flow_action_entry *act;
3727         bool encap = false, decap = false;
3728         u32 action = attr->action;
3729         int err, i, if_count = 0;
3730
3731         if (!flow_action_has_entries(flow_action))
3732                 return -EINVAL;
3733
3734         if (!flow_action_hw_stats_check(flow_action, extack,
3735                                         FLOW_ACTION_HW_STATS_DELAYED_BIT))
3736                 return -EOPNOTSUPP;
3737
3738         flow_action_for_each(i, act, flow_action) {
3739                 switch (act->id) {
3740                 case FLOW_ACTION_DROP:
3741                         action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3742                                   MLX5_FLOW_CONTEXT_ACTION_COUNT;
3743                         break;
3744                 case FLOW_ACTION_MANGLE:
3745                 case FLOW_ACTION_ADD:
3746                         err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
3747                                                     hdrs, extack);
3748                         if (err)
3749                                 return err;
3750
3751                         action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3752                         attr->split_count = attr->out_count;
3753                         break;
3754                 case FLOW_ACTION_CSUM:
3755                         if (csum_offload_supported(priv, action,
3756                                                    act->csum_flags, extack))
3757                                 break;
3758
3759                         return -EOPNOTSUPP;
3760                 case FLOW_ACTION_REDIRECT:
3761                 case FLOW_ACTION_MIRRED: {
3762                         struct mlx5e_priv *out_priv;
3763                         struct net_device *out_dev;
3764
3765                         out_dev = act->dev;
3766                         if (!out_dev) {
3767                                 /* out_dev is NULL when filters with
3768                                  * non-existing mirred device are replayed to
3769                                  * the driver.
3770                                  */
3771                                 return -EINVAL;
3772                         }
3773
3774                         if (ft_flow && out_dev == priv->netdev) {
3775                                 /* Ignore forward to self rules generated
3776                                  * by adding both mlx5 devs to the flow table
3777                                  * block on a normal nft offload setup.
3778                                  */
3779                                 return -EOPNOTSUPP;
3780                         }
3781
3782                         if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
3783                                 NL_SET_ERR_MSG_MOD(extack,
3784                                                    "can't support more output ports, can't offload forwarding");
3785                                 netdev_warn(priv->netdev,
3786                                             "can't support more than %d output ports, can't offload forwarding\n",
3787                                             attr->out_count);
3788                                 return -EOPNOTSUPP;
3789                         }
3790
3791                         action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3792                                   MLX5_FLOW_CONTEXT_ACTION_COUNT;
3793                         if (encap) {
3794                                 parse_attr->mirred_ifindex[attr->out_count] =
3795                                         out_dev->ifindex;
3796                                 parse_attr->tun_info[attr->out_count] = dup_tun_info(info);
3797                                 if (!parse_attr->tun_info[attr->out_count])
3798                                         return -ENOMEM;
3799                                 encap = false;
3800                                 attr->dests[attr->out_count].flags |=
3801                                         MLX5_ESW_DEST_ENCAP;
3802                                 attr->out_count++;
3803                                 /* attr->dests[].rep is resolved when we
3804                                  * handle encap
3805                                  */
3806                         } else if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
3807                                 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3808                                 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
3809                                 struct net_device *uplink_upper;
3810
3811                                 if (is_duplicated_output_device(priv->netdev,
3812                                                                 out_dev,
3813                                                                 ifindexes,
3814                                                                 if_count,
3815                                                                 extack))
3816                                         return -EOPNOTSUPP;
3817
3818                                 ifindexes[if_count] = out_dev->ifindex;
3819                                 if_count++;
3820
3821                                 rcu_read_lock();
3822                                 uplink_upper =
3823                                         netdev_master_upper_dev_get_rcu(uplink_dev);
3824                                 if (uplink_upper &&
3825                                     netif_is_lag_master(uplink_upper) &&
3826                                     uplink_upper == out_dev)
3827                                         out_dev = uplink_dev;
3828                                 rcu_read_unlock();
3829
3830                                 if (is_vlan_dev(out_dev)) {
3831                                         err = add_vlan_push_action(priv, attr,
3832                                                                    &out_dev,
3833                                                                    &action);
3834                                         if (err)
3835                                                 return err;
3836                                 }
3837
3838                                 if (is_vlan_dev(parse_attr->filter_dev)) {
3839                                         err = add_vlan_pop_action(priv, attr,
3840                                                                   &action);
3841                                         if (err)
3842                                                 return err;
3843                                 }
3844
3845                                 err = verify_uplink_forwarding(priv, flow, out_dev, extack);
3846                                 if (err)
3847                                         return err;
3848
3849                                 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
3850                                         NL_SET_ERR_MSG_MOD(extack,
3851                                                            "devices are not on same switch HW, can't offload forwarding");
3852                                         netdev_warn(priv->netdev,
3853                                                     "devices %s %s not on same switch HW, can't offload forwarding\n",
3854                                                     priv->netdev->name,
3855                                                     out_dev->name);
3856                                         return -EOPNOTSUPP;
3857                                 }
3858
3859                                 out_priv = netdev_priv(out_dev);
3860                                 rpriv = out_priv->ppriv;
3861                                 attr->dests[attr->out_count].rep = rpriv->rep;
3862                                 attr->dests[attr->out_count].mdev = out_priv->mdev;
3863                                 attr->out_count++;
3864                         } else if (parse_attr->filter_dev != priv->netdev) {
3865                                 /* All mlx5 devices are called to configure
3866                                  * high level device filters. Therefore, the
3867                                  * *attempt* to  install a filter on invalid
3868                                  * eswitch should not trigger an explicit error
3869                                  */
3870                                 return -EINVAL;
3871                         } else {
3872                                 NL_SET_ERR_MSG_MOD(extack,
3873                                                    "devices are not on same switch HW, can't offload forwarding");
3874                                 netdev_warn(priv->netdev,
3875                                             "devices %s %s not on same switch HW, can't offload forwarding\n",
3876                                             priv->netdev->name,
3877                                             out_dev->name);
3878                                 return -EINVAL;
3879                         }
3880                         }
3881                         break;
3882                 case FLOW_ACTION_TUNNEL_ENCAP:
3883                         info = act->tunnel;
3884                         if (info)
3885                                 encap = true;
3886                         else
3887                                 return -EOPNOTSUPP;
3888
3889                         break;
3890                 case FLOW_ACTION_VLAN_PUSH:
3891                 case FLOW_ACTION_VLAN_POP:
3892                         if (act->id == FLOW_ACTION_VLAN_PUSH &&
3893                             (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
3894                                 /* Replace vlan pop+push with vlan modify */
3895                                 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3896                                 err = add_vlan_rewrite_action(priv,
3897                                                               MLX5_FLOW_NAMESPACE_FDB,
3898                                                               act, parse_attr, hdrs,
3899                                                               &action, extack);
3900                         } else {
3901                                 err = parse_tc_vlan_action(priv, act, attr, &action);
3902                         }
3903                         if (err)
3904                                 return err;
3905
3906                         attr->split_count = attr->out_count;
3907                         break;
3908                 case FLOW_ACTION_VLAN_MANGLE:
3909                         err = add_vlan_rewrite_action(priv,
3910                                                       MLX5_FLOW_NAMESPACE_FDB,
3911                                                       act, parse_attr, hdrs,
3912                                                       &action, extack);
3913                         if (err)
3914                                 return err;
3915
3916                         attr->split_count = attr->out_count;
3917                         break;
3918                 case FLOW_ACTION_TUNNEL_DECAP:
3919                         decap = true;
3920                         break;
3921                 case FLOW_ACTION_GOTO:
3922                         err = mlx5_validate_goto_chain(esw, flow, act, action,
3923                                                        extack);
3924                         if (err)
3925                                 return err;
3926
3927                         action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3928                         attr->dest_chain = act->chain_index;
3929                         break;
3930                 case FLOW_ACTION_CT:
3931                         err = mlx5_tc_ct_parse_action(priv, attr, act, extack);
3932                         if (err)
3933                                 return err;
3934
3935                         flow_flag_set(flow, CT);
3936                         break;
3937                 default:
3938                         NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3939                         return -EOPNOTSUPP;
3940                 }
3941         }
3942
3943         if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
3944             action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
3945                 /* For prio tag mode, replace vlan pop with rewrite vlan prio
3946                  * tag rewrite.
3947                  */
3948                 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3949                 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
3950                                                        &action, extack);
3951                 if (err)
3952                         return err;
3953         }
3954
3955         if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3956             hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
3957                 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
3958                                             parse_attr, hdrs, &action, extack);
3959                 if (err)
3960                         return err;
3961                 /* in case all pedit actions are skipped, remove the MOD_HDR
3962                  * flag. we might have set split_count either by pedit or
3963                  * pop/push. if there is no pop/push either, reset it too.
3964                  */
3965                 if (parse_attr->mod_hdr_acts.num_actions == 0) {
3966                         action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3967                         dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
3968                         if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3969                               (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
3970                                 attr->split_count = 0;
3971                 }
3972         }
3973
3974         attr->action = action;
3975         if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
3976                 return -EOPNOTSUPP;
3977
3978         if (attr->dest_chain) {
3979                 if (decap) {
3980                         /* It can be supported if we'll create a mapping for
3981                          * the tunnel device only (without tunnel), and set
3982                          * this tunnel id with this decap flow.
3983                          *
3984                          * On restore (miss), we'll just set this saved tunnel
3985                          * device.
3986                          */
3987
3988                         NL_SET_ERR_MSG(extack,
3989                                        "Decap with goto isn't supported");
3990                         netdev_warn(priv->netdev,
3991                                     "Decap with goto isn't supported");
3992                         return -EOPNOTSUPP;
3993                 }
3994
3995                 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
3996                         NL_SET_ERR_MSG_MOD(extack,
3997                                            "Mirroring goto chain rules isn't supported");
3998                         return -EOPNOTSUPP;
3999                 }
4000                 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4001         }
4002
4003         if (!(attr->action &
4004               (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
4005                 NL_SET_ERR_MSG_MOD(extack,
4006                                    "Rule must have at least one forward/drop action");
4007                 return -EOPNOTSUPP;
4008         }
4009
4010         if (attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
4011                 NL_SET_ERR_MSG_MOD(extack,
4012                                    "current firmware doesn't support split rule for port mirroring");
4013                 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
4014                 return -EOPNOTSUPP;
4015         }
4016
4017         return 0;
4018 }
4019
4020 static void get_flags(int flags, unsigned long *flow_flags)
4021 {
4022         unsigned long __flow_flags = 0;
4023
4024         if (flags & MLX5_TC_FLAG(INGRESS))
4025                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
4026         if (flags & MLX5_TC_FLAG(EGRESS))
4027                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
4028
4029         if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
4030                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4031         if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
4032                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
4033         if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
4034                 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
4035
4036         *flow_flags = __flow_flags;
4037 }
4038
4039 static const struct rhashtable_params tc_ht_params = {
4040         .head_offset = offsetof(struct mlx5e_tc_flow, node),
4041         .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
4042         .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
4043         .automatic_shrinking = true,
4044 };
4045
4046 static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
4047                                     unsigned long flags)
4048 {
4049         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4050         struct mlx5e_rep_priv *uplink_rpriv;
4051
4052         if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
4053                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
4054                 return &uplink_rpriv->uplink_priv.tc_ht;
4055         } else /* NIC offload */
4056                 return &priv->fs.tc.ht;
4057 }
4058
4059 static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
4060 {
4061         struct mlx5_esw_flow_attr *attr = flow->esw_attr;
4062         bool is_rep_ingress = attr->in_rep->vport != MLX5_VPORT_UPLINK &&
4063                 flow_flag_test(flow, INGRESS);
4064         bool act_is_encap = !!(attr->action &
4065                                MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
4066         bool esw_paired = mlx5_devcom_is_paired(attr->in_mdev->priv.devcom,
4067                                                 MLX5_DEVCOM_ESW_OFFLOADS);
4068
4069         if (!esw_paired)
4070                 return false;
4071
4072         if ((mlx5_lag_is_sriov(attr->in_mdev) ||
4073              mlx5_lag_is_multipath(attr->in_mdev)) &&
4074             (is_rep_ingress || act_is_encap))
4075                 return true;
4076
4077         return false;
4078 }
4079
4080 static int
4081 mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
4082                  struct flow_cls_offload *f, unsigned long flow_flags,
4083                  struct mlx5e_tc_flow_parse_attr **__parse_attr,
4084                  struct mlx5e_tc_flow **__flow)
4085 {
4086         struct mlx5e_tc_flow_parse_attr *parse_attr;
4087         struct mlx5e_tc_flow *flow;
4088         int out_index, err;
4089
4090         flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
4091         parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
4092         if (!parse_attr || !flow) {
4093                 err = -ENOMEM;
4094                 goto err_free;
4095         }
4096
4097         flow->cookie = f->cookie;
4098         flow->flags = flow_flags;
4099         flow->priv = priv;
4100         for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
4101                 INIT_LIST_HEAD(&flow->encaps[out_index].list);
4102         INIT_LIST_HEAD(&flow->mod_hdr);
4103         INIT_LIST_HEAD(&flow->hairpin);
4104         refcount_set(&flow->refcnt, 1);
4105         init_completion(&flow->init_done);
4106
4107         *__flow = flow;
4108         *__parse_attr = parse_attr;
4109
4110         return 0;
4111
4112 err_free:
4113         kfree(flow);
4114         kvfree(parse_attr);
4115         return err;
4116 }
4117
4118 static void
4119 mlx5e_flow_esw_attr_init(struct mlx5_esw_flow_attr *esw_attr,
4120                          struct mlx5e_priv *priv,
4121                          struct mlx5e_tc_flow_parse_attr *parse_attr,
4122                          struct flow_cls_offload *f,
4123                          struct mlx5_eswitch_rep *in_rep,
4124                          struct mlx5_core_dev *in_mdev)
4125 {
4126         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4127
4128         esw_attr->parse_attr = parse_attr;
4129         esw_attr->chain = f->common.chain_index;
4130         esw_attr->prio = f->common.prio;
4131
4132         esw_attr->in_rep = in_rep;
4133         esw_attr->in_mdev = in_mdev;
4134
4135         if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
4136             MLX5_COUNTER_SOURCE_ESWITCH)
4137                 esw_attr->counter_dev = in_mdev;
4138         else
4139                 esw_attr->counter_dev = priv->mdev;
4140 }
4141
4142 static struct mlx5e_tc_flow *
4143 __mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
4144                      struct flow_cls_offload *f,
4145                      unsigned long flow_flags,
4146                      struct net_device *filter_dev,
4147                      struct mlx5_eswitch_rep *in_rep,
4148                      struct mlx5_core_dev *in_mdev)
4149 {
4150         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
4151         struct netlink_ext_ack *extack = f->common.extack;
4152         struct mlx5e_tc_flow_parse_attr *parse_attr;
4153         struct mlx5e_tc_flow *flow;
4154         int attr_size, err;
4155
4156         flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4157         attr_size  = sizeof(struct mlx5_esw_flow_attr);
4158         err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4159                                &parse_attr, &flow);
4160         if (err)
4161                 goto out;
4162
4163         parse_attr->filter_dev = filter_dev;
4164         mlx5e_flow_esw_attr_init(flow->esw_attr,
4165                                  priv, parse_attr,
4166                                  f, in_rep, in_mdev);
4167
4168         err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4169                                f, filter_dev);
4170         if (err)
4171                 goto err_free;
4172
4173         err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
4174         if (err)
4175                 goto err_free;
4176
4177         err = mlx5_tc_ct_parse_match(priv, &parse_attr->spec, f, extack);
4178         if (err)
4179                 goto err_free;
4180
4181         err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
4182         complete_all(&flow->init_done);
4183         if (err) {
4184                 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
4185                         goto err_free;
4186
4187                 add_unready_flow(flow);
4188         }
4189
4190         return flow;
4191
4192 err_free:
4193         mlx5e_flow_put(priv, flow);
4194 out:
4195         return ERR_PTR(err);
4196 }
4197
4198 static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
4199                                       struct mlx5e_tc_flow *flow,
4200                                       unsigned long flow_flags)
4201 {
4202         struct mlx5e_priv *priv = flow->priv, *peer_priv;
4203         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
4204         struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4205         struct mlx5e_tc_flow_parse_attr *parse_attr;
4206         struct mlx5e_rep_priv *peer_urpriv;
4207         struct mlx5e_tc_flow *peer_flow;
4208         struct mlx5_core_dev *in_mdev;
4209         int err = 0;
4210
4211         peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4212         if (!peer_esw)
4213                 return -ENODEV;
4214
4215         peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
4216         peer_priv = netdev_priv(peer_urpriv->netdev);
4217
4218         /* in_mdev is assigned of which the packet originated from.
4219          * So packets redirected to uplink use the same mdev of the
4220          * original flow and packets redirected from uplink use the
4221          * peer mdev.
4222          */
4223         if (flow->esw_attr->in_rep->vport == MLX5_VPORT_UPLINK)
4224                 in_mdev = peer_priv->mdev;
4225         else
4226                 in_mdev = priv->mdev;
4227
4228         parse_attr = flow->esw_attr->parse_attr;
4229         peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
4230                                          parse_attr->filter_dev,
4231                                          flow->esw_attr->in_rep, in_mdev);
4232         if (IS_ERR(peer_flow)) {
4233                 err = PTR_ERR(peer_flow);
4234                 goto out;
4235         }
4236
4237         flow->peer_flow = peer_flow;
4238         flow_flag_set(flow, DUP);
4239         mutex_lock(&esw->offloads.peer_mutex);
4240         list_add_tail(&flow->peer, &esw->offloads.peer_flows);
4241         mutex_unlock(&esw->offloads.peer_mutex);
4242
4243 out:
4244         mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4245         return err;
4246 }
4247
4248 static int
4249 mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
4250                    struct flow_cls_offload *f,
4251                    unsigned long flow_flags,
4252                    struct net_device *filter_dev,
4253                    struct mlx5e_tc_flow **__flow)
4254 {
4255         struct mlx5e_rep_priv *rpriv = priv->ppriv;
4256         struct mlx5_eswitch_rep *in_rep = rpriv->rep;
4257         struct mlx5_core_dev *in_mdev = priv->mdev;
4258         struct mlx5e_tc_flow *flow;
4259         int err;
4260
4261         flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
4262                                     in_mdev);
4263         if (IS_ERR(flow))
4264                 return PTR_ERR(flow);
4265
4266         if (is_peer_flow_needed(flow)) {
4267                 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
4268                 if (err) {
4269                         mlx5e_tc_del_fdb_flow(priv, flow);
4270                         goto out;
4271                 }
4272         }
4273
4274         *__flow = flow;
4275
4276         return 0;
4277
4278 out:
4279         return err;
4280 }
4281
4282 static int
4283 mlx5e_add_nic_flow(struct mlx5e_priv *priv,
4284                    struct flow_cls_offload *f,
4285                    unsigned long flow_flags,
4286                    struct net_device *filter_dev,
4287                    struct mlx5e_tc_flow **__flow)
4288 {
4289         struct flow_rule *rule = flow_cls_offload_flow_rule(f);
4290         struct netlink_ext_ack *extack = f->common.extack;
4291         struct mlx5e_tc_flow_parse_attr *parse_attr;
4292         struct mlx5e_tc_flow *flow;
4293         int attr_size, err;
4294
4295         /* multi-chain not supported for NIC rules */
4296         if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
4297                 return -EOPNOTSUPP;
4298
4299         flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
4300         attr_size  = sizeof(struct mlx5_nic_flow_attr);
4301         err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4302                                &parse_attr, &flow);
4303         if (err)
4304                 goto out;
4305
4306         parse_attr->filter_dev = filter_dev;
4307         err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4308                                f, filter_dev);
4309         if (err)
4310                 goto err_free;
4311
4312         err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
4313         if (err)
4314                 goto err_free;
4315
4316         err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
4317         if (err)
4318                 goto err_free;
4319
4320         flow_flag_set(flow, OFFLOADED);
4321         kvfree(parse_attr);
4322         *__flow = flow;
4323
4324         return 0;
4325
4326 err_free:
4327         mlx5e_flow_put(priv, flow);
4328         kvfree(parse_attr);
4329 out:
4330         return err;
4331 }
4332
4333 static int
4334 mlx5e_tc_add_flow(struct mlx5e_priv *priv,
4335                   struct flow_cls_offload *f,
4336                   unsigned long flags,
4337                   struct net_device *filter_dev,
4338                   struct mlx5e_tc_flow **flow)
4339 {
4340         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4341         unsigned long flow_flags;
4342         int err;
4343
4344         get_flags(flags, &flow_flags);
4345
4346         if (!tc_can_offload_extack(priv->netdev, f->common.extack))
4347                 return -EOPNOTSUPP;
4348
4349         if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
4350                 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
4351                                          filter_dev, flow);
4352         else
4353                 err = mlx5e_add_nic_flow(priv, f, flow_flags,
4354                                          filter_dev, flow);
4355
4356         return err;
4357 }
4358
4359 int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
4360                            struct flow_cls_offload *f, unsigned long flags)
4361 {
4362         struct netlink_ext_ack *extack = f->common.extack;
4363         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4364         struct mlx5e_tc_flow *flow;
4365         int err = 0;
4366
4367         rcu_read_lock();
4368         flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
4369         rcu_read_unlock();
4370         if (flow) {
4371                 NL_SET_ERR_MSG_MOD(extack,
4372                                    "flow cookie already exists, ignoring");
4373                 netdev_warn_once(priv->netdev,
4374                                  "flow cookie %lx already exists, ignoring\n",
4375                                  f->cookie);
4376                 err = -EEXIST;
4377                 goto out;
4378         }
4379
4380         trace_mlx5e_configure_flower(f);
4381         err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
4382         if (err)
4383                 goto out;
4384
4385         err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
4386         if (err)
4387                 goto err_free;
4388
4389         return 0;
4390
4391 err_free:
4392         mlx5e_flow_put(priv, flow);
4393 out:
4394         return err;
4395 }
4396
4397 static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4398 {
4399         bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4400         bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
4401
4402         return flow_flag_test(flow, INGRESS) == dir_ingress &&
4403                 flow_flag_test(flow, EGRESS) == dir_egress;
4404 }
4405
4406 int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
4407                         struct flow_cls_offload *f, unsigned long flags)
4408 {
4409         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4410         struct mlx5e_tc_flow *flow;
4411         int err;
4412
4413         rcu_read_lock();
4414         flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
4415         if (!flow || !same_flow_direction(flow, flags)) {
4416                 err = -EINVAL;
4417                 goto errout;
4418         }
4419
4420         /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4421          * set.
4422          */
4423         if (flow_flag_test_and_set(flow, DELETED)) {
4424                 err = -EINVAL;
4425                 goto errout;
4426         }
4427         rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
4428         rcu_read_unlock();
4429
4430         trace_mlx5e_delete_flower(f);
4431         mlx5e_flow_put(priv, flow);
4432
4433         return 0;
4434
4435 errout:
4436         rcu_read_unlock();
4437         return err;
4438 }
4439
4440 int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
4441                        struct flow_cls_offload *f, unsigned long flags)
4442 {
4443         struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4444         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4445         struct mlx5_eswitch *peer_esw;
4446         struct mlx5e_tc_flow *flow;
4447         struct mlx5_fc *counter;
4448         u64 lastuse = 0;
4449         u64 packets = 0;
4450         u64 bytes = 0;
4451         int err = 0;
4452
4453         rcu_read_lock();
4454         flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4455                                                 tc_ht_params));
4456         rcu_read_unlock();
4457         if (IS_ERR(flow))
4458                 return PTR_ERR(flow);
4459
4460         if (!same_flow_direction(flow, flags)) {
4461                 err = -EINVAL;
4462                 goto errout;
4463         }
4464
4465         if (mlx5e_is_offloaded_flow(flow) || flow_flag_test(flow, CT)) {
4466                 counter = mlx5e_tc_get_counter(flow);
4467                 if (!counter)
4468                         goto errout;
4469
4470                 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4471         }
4472
4473         /* Under multipath it's possible for one rule to be currently
4474          * un-offloaded while the other rule is offloaded.
4475          */
4476         peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4477         if (!peer_esw)
4478                 goto out;
4479
4480         if (flow_flag_test(flow, DUP) &&
4481             flow_flag_test(flow->peer_flow, OFFLOADED)) {
4482                 u64 bytes2;
4483                 u64 packets2;
4484                 u64 lastuse2;
4485
4486                 counter = mlx5e_tc_get_counter(flow->peer_flow);
4487                 if (!counter)
4488                         goto no_peer_counter;
4489                 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
4490
4491                 bytes += bytes2;
4492                 packets += packets2;
4493                 lastuse = max_t(u64, lastuse, lastuse2);
4494         }
4495
4496 no_peer_counter:
4497         mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4498 out:
4499         flow_stats_update(&f->stats, bytes, packets, lastuse,
4500                           FLOW_ACTION_HW_STATS_DELAYED);
4501         trace_mlx5e_stats_flower(f);
4502 errout:
4503         mlx5e_flow_put(priv, flow);
4504         return err;
4505 }
4506
4507 static int apply_police_params(struct mlx5e_priv *priv, u32 rate,
4508                                struct netlink_ext_ack *extack)
4509 {
4510         struct mlx5e_rep_priv *rpriv = priv->ppriv;
4511         struct mlx5_eswitch *esw;
4512         u16 vport_num;
4513         u32 rate_mbps;
4514         int err;
4515
4516         vport_num = rpriv->rep->vport;
4517         if (vport_num >= MLX5_VPORT_ECPF) {
4518                 NL_SET_ERR_MSG_MOD(extack,
4519                                    "Ingress rate limit is supported only for Eswitch ports connected to VFs");
4520                 return -EOPNOTSUPP;
4521         }
4522
4523         esw = priv->mdev->priv.eswitch;
4524         /* rate is given in bytes/sec.
4525          * First convert to bits/sec and then round to the nearest mbit/secs.
4526          * mbit means million bits.
4527          * Moreover, if rate is non zero we choose to configure to a minimum of
4528          * 1 mbit/sec.
4529          */
4530         rate_mbps = rate ? max_t(u32, (rate * 8 + 500000) / 1000000, 1) : 0;
4531         err = mlx5_esw_modify_vport_rate(esw, vport_num, rate_mbps);
4532         if (err)
4533                 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
4534
4535         return err;
4536 }
4537
4538 static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
4539                                         struct flow_action *flow_action,
4540                                         struct netlink_ext_ack *extack)
4541 {
4542         struct mlx5e_rep_priv *rpriv = priv->ppriv;
4543         const struct flow_action_entry *act;
4544         int err;
4545         int i;
4546
4547         if (!flow_action_has_entries(flow_action)) {
4548                 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
4549                 return -EINVAL;
4550         }
4551
4552         if (!flow_offload_has_one_action(flow_action)) {
4553                 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
4554                 return -EOPNOTSUPP;
4555         }
4556
4557         if (!flow_action_basic_hw_stats_check(flow_action, extack))
4558                 return -EOPNOTSUPP;
4559
4560         flow_action_for_each(i, act, flow_action) {
4561                 switch (act->id) {
4562                 case FLOW_ACTION_POLICE:
4563                         err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
4564                         if (err)
4565                                 return err;
4566
4567                         rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
4568                         break;
4569                 default:
4570                         NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
4571                         return -EOPNOTSUPP;
4572                 }
4573         }
4574
4575         return 0;
4576 }
4577
4578 int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
4579                                 struct tc_cls_matchall_offload *ma)
4580 {
4581         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4582         struct netlink_ext_ack *extack = ma->common.extack;
4583
4584         if (!mlx5_esw_qos_enabled(esw)) {
4585                 NL_SET_ERR_MSG_MOD(extack, "QoS is not supported on this device");
4586                 return -EOPNOTSUPP;
4587         }
4588
4589         if (ma->common.prio != 1) {
4590                 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
4591                 return -EINVAL;
4592         }
4593
4594         return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
4595 }
4596
4597 int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
4598                              struct tc_cls_matchall_offload *ma)
4599 {
4600         struct netlink_ext_ack *extack = ma->common.extack;
4601
4602         return apply_police_params(priv, 0, extack);
4603 }
4604
4605 void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
4606                              struct tc_cls_matchall_offload *ma)
4607 {
4608         struct mlx5e_rep_priv *rpriv = priv->ppriv;
4609         struct rtnl_link_stats64 cur_stats;
4610         u64 dbytes;
4611         u64 dpkts;
4612
4613         cur_stats = priv->stats.vf_vport;
4614         dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
4615         dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
4616         rpriv->prev_vf_vport_stats = cur_stats;
4617         flow_stats_update(&ma->stats, dbytes, dpkts, jiffies,
4618                           FLOW_ACTION_HW_STATS_DELAYED);
4619 }
4620
4621 static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
4622                                               struct mlx5e_priv *peer_priv)
4623 {
4624         struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
4625         struct mlx5e_hairpin_entry *hpe, *tmp;
4626         LIST_HEAD(init_wait_list);
4627         u16 peer_vhca_id;
4628         int bkt;
4629
4630         if (!same_hw_devs(priv, peer_priv))
4631                 return;
4632
4633         peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
4634
4635         mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
4636         hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
4637                 if (refcount_inc_not_zero(&hpe->refcnt))
4638                         list_add(&hpe->dead_peer_wait_list, &init_wait_list);
4639         mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
4640
4641         list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
4642                 wait_for_completion(&hpe->res_ready);
4643                 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
4644                         hpe->hp->pair->peer_gone = true;
4645
4646                 mlx5e_hairpin_put(priv, hpe);
4647         }
4648 }
4649
4650 static int mlx5e_tc_netdev_event(struct notifier_block *this,
4651                                  unsigned long event, void *ptr)
4652 {
4653         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
4654         struct mlx5e_flow_steering *fs;
4655         struct mlx5e_priv *peer_priv;
4656         struct mlx5e_tc_table *tc;
4657         struct mlx5e_priv *priv;
4658
4659         if (ndev->netdev_ops != &mlx5e_netdev_ops ||
4660             event != NETDEV_UNREGISTER ||
4661             ndev->reg_state == NETREG_REGISTERED)
4662                 return NOTIFY_DONE;
4663
4664         tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
4665         fs = container_of(tc, struct mlx5e_flow_steering, tc);
4666         priv = container_of(fs, struct mlx5e_priv, fs);
4667         peer_priv = netdev_priv(ndev);
4668         if (priv == peer_priv ||
4669             !(priv->netdev->features & NETIF_F_HW_TC))
4670                 return NOTIFY_DONE;
4671
4672         mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
4673
4674         return NOTIFY_DONE;
4675 }
4676
4677 int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
4678 {
4679         struct mlx5e_tc_table *tc = &priv->fs.tc;
4680         int err;
4681
4682         mutex_init(&tc->t_lock);
4683         mutex_init(&tc->mod_hdr.lock);
4684         hash_init(tc->mod_hdr.hlist);
4685         mutex_init(&tc->hairpin_tbl_lock);
4686         hash_init(tc->hairpin_tbl);
4687
4688         err = rhashtable_init(&tc->ht, &tc_ht_params);
4689         if (err)
4690                 return err;
4691
4692         tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
4693         err = register_netdevice_notifier_dev_net(priv->netdev,
4694                                                   &tc->netdevice_nb,
4695                                                   &tc->netdevice_nn);
4696         if (err) {
4697                 tc->netdevice_nb.notifier_call = NULL;
4698                 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
4699         }
4700
4701         return err;
4702 }
4703
4704 static void _mlx5e_tc_del_flow(void *ptr, void *arg)
4705 {
4706         struct mlx5e_tc_flow *flow = ptr;
4707         struct mlx5e_priv *priv = flow->priv;
4708
4709         mlx5e_tc_del_flow(priv, flow);
4710         kfree(flow);
4711 }
4712
4713 void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
4714 {
4715         struct mlx5e_tc_table *tc = &priv->fs.tc;
4716
4717         if (tc->netdevice_nb.notifier_call)
4718                 unregister_netdevice_notifier_dev_net(priv->netdev,
4719                                                       &tc->netdevice_nb,
4720                                                       &tc->netdevice_nn);
4721
4722         mutex_destroy(&tc->mod_hdr.lock);
4723         mutex_destroy(&tc->hairpin_tbl_lock);
4724
4725         rhashtable_destroy(&tc->ht);
4726
4727         if (!IS_ERR_OR_NULL(tc->t)) {
4728                 mlx5_destroy_flow_table(tc->t);
4729                 tc->t = NULL;
4730         }
4731         mutex_destroy(&tc->t_lock);
4732 }
4733
4734 int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
4735 {
4736         const size_t sz_enc_opts = sizeof(struct flow_dissector_key_enc_opts);
4737         struct mlx5_rep_uplink_priv *uplink_priv;
4738         struct mlx5e_rep_priv *priv;
4739         struct mapping_ctx *mapping;
4740         int err;
4741
4742         uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
4743         priv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
4744
4745         err = mlx5_tc_ct_init(uplink_priv);
4746         if (err)
4747                 goto err_ct;
4748
4749         mapping = mapping_create(sizeof(struct tunnel_match_key),
4750                                  TUNNEL_INFO_BITS_MASK, true);
4751         if (IS_ERR(mapping)) {
4752                 err = PTR_ERR(mapping);
4753                 goto err_tun_mapping;
4754         }
4755         uplink_priv->tunnel_mapping = mapping;
4756
4757         mapping = mapping_create(sz_enc_opts, ENC_OPTS_BITS_MASK, true);
4758         if (IS_ERR(mapping)) {
4759                 err = PTR_ERR(mapping);
4760                 goto err_enc_opts_mapping;
4761         }
4762         uplink_priv->tunnel_enc_opts_mapping = mapping;
4763
4764         err = rhashtable_init(tc_ht, &tc_ht_params);
4765         if (err)
4766                 goto err_ht_init;
4767
4768         return err;
4769
4770 err_ht_init:
4771         mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
4772 err_enc_opts_mapping:
4773         mapping_destroy(uplink_priv->tunnel_mapping);
4774 err_tun_mapping:
4775         mlx5_tc_ct_clean(uplink_priv);
4776 err_ct:
4777         netdev_warn(priv->netdev,
4778                     "Failed to initialize tc (eswitch), err: %d", err);
4779         return err;
4780 }
4781
4782 void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
4783 {
4784         struct mlx5_rep_uplink_priv *uplink_priv;
4785
4786         rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
4787
4788         uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
4789         mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
4790         mapping_destroy(uplink_priv->tunnel_mapping);
4791
4792         mlx5_tc_ct_clean(uplink_priv);
4793 }
4794
4795 int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
4796 {
4797         struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4798
4799         return atomic_read(&tc_ht->nelems);
4800 }
4801
4802 void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
4803 {
4804         struct mlx5e_tc_flow *flow, *tmp;
4805
4806         list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
4807                 __mlx5e_tc_del_fdb_peer_flow(flow);
4808 }
4809
4810 void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
4811 {
4812         struct mlx5_rep_uplink_priv *rpriv =
4813                 container_of(work, struct mlx5_rep_uplink_priv,
4814                              reoffload_flows_work);
4815         struct mlx5e_tc_flow *flow, *tmp;
4816
4817         mutex_lock(&rpriv->unready_flows_lock);
4818         list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
4819                 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
4820                         unready_flow_del(flow);
4821         }
4822         mutex_unlock(&rpriv->unready_flows_lock);
4823 }
4824
4825 #if IS_ENABLED(CONFIG_NET_TC_SKB_EXT)
4826 static bool mlx5e_restore_tunnel(struct mlx5e_priv *priv, struct sk_buff *skb,
4827                                  struct mlx5e_tc_update_priv *tc_priv,
4828                                  u32 tunnel_id)
4829 {
4830         struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4831         struct flow_dissector_key_enc_opts enc_opts = {};
4832         struct mlx5_rep_uplink_priv *uplink_priv;
4833         struct mlx5e_rep_priv *uplink_rpriv;
4834         struct metadata_dst *tun_dst;
4835         struct tunnel_match_key key;
4836         u32 tun_id, enc_opts_id;
4837         struct net_device *dev;
4838         int err;
4839
4840         enc_opts_id = tunnel_id & ENC_OPTS_BITS_MASK;
4841         tun_id = tunnel_id >> ENC_OPTS_BITS;
4842
4843         if (!tun_id)
4844                 return true;
4845
4846         uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
4847         uplink_priv = &uplink_rpriv->uplink_priv;
4848
4849         err = mapping_find(uplink_priv->tunnel_mapping, tun_id, &key);
4850         if (err) {
4851                 WARN_ON_ONCE(true);
4852                 netdev_dbg(priv->netdev,
4853                            "Couldn't find tunnel for tun_id: %d, err: %d\n",
4854                            tun_id, err);
4855                 return false;
4856         }
4857
4858         if (enc_opts_id) {
4859                 err = mapping_find(uplink_priv->tunnel_enc_opts_mapping,
4860                                    enc_opts_id, &enc_opts);
4861                 if (err) {
4862                         netdev_dbg(priv->netdev,
4863                                    "Couldn't find tunnel (opts) for tun_id: %d, err: %d\n",
4864                                    enc_opts_id, err);
4865                         return false;
4866                 }
4867         }
4868
4869         tun_dst = tun_rx_dst(enc_opts.len);
4870         if (!tun_dst) {
4871                 WARN_ON_ONCE(true);
4872                 return false;
4873         }
4874
4875         ip_tunnel_key_init(&tun_dst->u.tun_info.key,
4876                            key.enc_ipv4.src, key.enc_ipv4.dst,
4877                            key.enc_ip.tos, key.enc_ip.ttl,
4878                            0, /* label */
4879                            key.enc_tp.src, key.enc_tp.dst,
4880                            key32_to_tunnel_id(key.enc_key_id.keyid),
4881                            TUNNEL_KEY);
4882
4883         if (enc_opts.len)
4884                 ip_tunnel_info_opts_set(&tun_dst->u.tun_info, enc_opts.data,
4885                                         enc_opts.len, enc_opts.dst_opt_type);
4886
4887         skb_dst_set(skb, (struct dst_entry *)tun_dst);
4888         dev = dev_get_by_index(&init_net, key.filter_ifindex);
4889         if (!dev) {
4890                 netdev_dbg(priv->netdev,
4891                            "Couldn't find tunnel device with ifindex: %d\n",
4892                            key.filter_ifindex);
4893                 return false;
4894         }
4895
4896         /* Set tun_dev so we do dev_put() after datapath */
4897         tc_priv->tun_dev = dev;
4898
4899         skb->dev = dev;
4900
4901         return true;
4902 }
4903 #endif /* CONFIG_NET_TC_SKB_EXT */
4904
4905 bool mlx5e_tc_rep_update_skb(struct mlx5_cqe64 *cqe,
4906                              struct sk_buff *skb,
4907                              struct mlx5e_tc_update_priv *tc_priv)
4908 {
4909 #if IS_ENABLED(CONFIG_NET_TC_SKB_EXT)
4910         u32 chain = 0, reg_c0, reg_c1, tunnel_id, tuple_id;
4911         struct mlx5_rep_uplink_priv *uplink_priv;
4912         struct mlx5e_rep_priv *uplink_rpriv;
4913         struct tc_skb_ext *tc_skb_ext;
4914         struct mlx5_eswitch *esw;
4915         struct mlx5e_priv *priv;
4916         int tunnel_moffset;
4917         int err;
4918
4919         reg_c0 = (be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK);
4920         if (reg_c0 == MLX5_FS_DEFAULT_FLOW_TAG)
4921                 reg_c0 = 0;
4922         reg_c1 = be32_to_cpu(cqe->imm_inval_pkey);
4923
4924         if (!reg_c0)
4925                 return true;
4926
4927         priv = netdev_priv(skb->dev);
4928         esw = priv->mdev->priv.eswitch;
4929
4930         err = mlx5_eswitch_get_chain_for_tag(esw, reg_c0, &chain);
4931         if (err) {
4932                 netdev_dbg(priv->netdev,
4933                            "Couldn't find chain for chain tag: %d, err: %d\n",
4934                            reg_c0, err);
4935                 return false;
4936         }
4937
4938         if (chain) {
4939                 tc_skb_ext = skb_ext_add(skb, TC_SKB_EXT);
4940                 if (!tc_skb_ext) {
4941                         WARN_ON(1);
4942                         return false;
4943                 }
4944
4945                 tc_skb_ext->chain = chain;
4946
4947                 tuple_id = reg_c1 & TUPLE_ID_MAX;
4948
4949                 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
4950                 uplink_priv = &uplink_rpriv->uplink_priv;
4951                 if (!mlx5e_tc_ct_restore_flow(uplink_priv, skb, tuple_id))
4952                         return false;
4953         }
4954
4955         tunnel_moffset = mlx5e_tc_attr_to_reg_mappings[TUNNEL_TO_REG].moffset;
4956         tunnel_id = reg_c1 >> (8 * tunnel_moffset);
4957         return mlx5e_restore_tunnel(priv, skb, tc_priv, tunnel_id);
4958 #endif /* CONFIG_NET_TC_SKB_EXT */
4959
4960         return true;
4961 }
4962
4963 void mlx5_tc_rep_post_napi_receive(struct mlx5e_tc_update_priv *tc_priv)
4964 {
4965         if (tc_priv->tun_dev)
4966                 dev_put(tc_priv->tun_dev);
4967 }