drivers/net/ethernet/mellanox/mlx5/core/health.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/kernel.h>
  34 #include <linux/module.h>
  35 #include <linux/random.h>
  36 #include <linux/vmalloc.h>
  37 #include <linux/hardirq.h>
  38 #include <linux/mlx5/driver.h>
  39 #include <linux/mlx5/cmd.h>
  40 #include "mlx5_core.h"
  41 #include "lib/eq.h"
  42 #include "lib/mlx5.h"
  43
  44 enum {
  45         MLX5_HEALTH_POLL_INTERVAL       = 2 * HZ,
  46         MAX_MISSES                      = 3,
  47 };
  48
  49 enum {
  50         MLX5_HEALTH_SYNDR_FW_ERR                = 0x1,
  51         MLX5_HEALTH_SYNDR_IRISC_ERR             = 0x7,
  52         MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR  = 0x8,
  53         MLX5_HEALTH_SYNDR_CRC_ERR               = 0x9,
  54         MLX5_HEALTH_SYNDR_FETCH_PCI_ERR         = 0xa,
  55         MLX5_HEALTH_SYNDR_HW_FTL_ERR            = 0xb,
  56         MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR  = 0xc,
  57         MLX5_HEALTH_SYNDR_EQ_ERR                = 0xd,
  58         MLX5_HEALTH_SYNDR_EQ_INV                = 0xe,
  59         MLX5_HEALTH_SYNDR_FFSER_ERR             = 0xf,
  60         MLX5_HEALTH_SYNDR_HIGH_TEMP             = 0x10
  61 };
  62
  63 enum {
  64         MLX5_DROP_NEW_HEALTH_WORK,
  65         MLX5_DROP_NEW_RECOVERY_WORK,
  66 };
  67
  68 u8 mlx5_get_nic_state(struct mlx5_core_dev *dev)
  69 {
  70         return (ioread32be(&dev->iseg->cmdq_addr_l_sz) >> 8) & 3;
  71 }
  72
  73 void mlx5_set_nic_state(struct mlx5_core_dev *dev, u8 state)
  74 {
  75         u32 cur_cmdq_addr_l_sz;
  76
  77         cur_cmdq_addr_l_sz = ioread32be(&dev->iseg->cmdq_addr_l_sz);
  78         iowrite32be((cur_cmdq_addr_l_sz & 0xFFFFF000) |
  79                     state << MLX5_NIC_IFC_OFFSET,
  80                     &dev->iseg->cmdq_addr_l_sz);
  81 }
  82
  83 static int in_fatal(struct mlx5_core_dev *dev)
  84 {
  85         struct mlx5_core_health *health = &dev->priv.health;
  86         struct health_buffer __iomem *h = health->health;
  87
  88         if (mlx5_get_nic_state(dev) == MLX5_NIC_IFC_DISABLED)
  89                 return 1;
  90
  91         if (ioread32be(&h->fw_ver) == 0xffffffff)
  92                 return 1;
  93
  94         return 0;
  95 }
  96
  97 void mlx5_enter_error_state(struct mlx5_core_dev *dev, bool force)
  98 {
  99         mutex_lock(&dev->intf_state_mutex);
 100         if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
 101                 goto unlock;
 102
 103         mlx5_core_err(dev, "start\n");
 104         if (pci_channel_offline(dev->pdev) || in_fatal(dev) || force) {
 105                 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
 106                 mlx5_cmd_trigger_completions(dev);
 107         }
 108
 109         mlx5_notifier_call_chain(dev->priv.events, MLX5_DEV_EVENT_SYS_ERROR, (void *)1);
 110         mlx5_core_err(dev, "end\n");
 111
 112 unlock:
 113         mutex_unlock(&dev->intf_state_mutex);
 114 }
 115
 116 static void mlx5_handle_bad_state(struct mlx5_core_dev *dev)
 117 {
 118         u8 nic_interface = mlx5_get_nic_state(dev);
 119
 120         switch (nic_interface) {
 121         case MLX5_NIC_IFC_FULL:
 122                 mlx5_core_warn(dev, "Expected to see disabled NIC but it is full driver\n");
 123                 break;
 124
 125         case MLX5_NIC_IFC_DISABLED:
 126                 mlx5_core_warn(dev, "starting teardown\n");
 127                 break;
 128
 129         case MLX5_NIC_IFC_NO_DRAM_NIC:
 130                 mlx5_core_warn(dev, "Expected to see disabled NIC but it is no dram nic\n");
 131                 break;
 132         default:
 133                 mlx5_core_warn(dev, "Expected to see disabled NIC but it is has invalid value %d\n",
 134                                nic_interface);
 135         }
 136
 137         mlx5_disable_device(dev);
 138 }
 139
 140 static void health_recover(struct work_struct *work)
 141 {
 142         struct mlx5_core_health *health;
 143         struct delayed_work *dwork;
 144         struct mlx5_core_dev *dev;
 145         struct mlx5_priv *priv;
 146         u8 nic_state;
 147
 148         dwork = container_of(work, struct delayed_work, work);
 149         health = container_of(dwork, struct mlx5_core_health, recover_work);
 150         priv = container_of(health, struct mlx5_priv, health);
 151         dev = container_of(priv, struct mlx5_core_dev, priv);
 152
 153         nic_state = mlx5_get_nic_state(dev);
 154         if (nic_state == MLX5_NIC_IFC_INVALID) {
 155                 dev_err(&dev->pdev->dev, "health recovery flow aborted since the nic state is invalid\n");
 156                 return;
 157         }
 158
 159         dev_err(&dev->pdev->dev, "starting health recovery flow\n");
 160         mlx5_recover_device(dev);
 161 }
 162
 163 /* How much time to wait until health resetting the driver (in msecs) */
 164 #define MLX5_RECOVERY_DELAY_MSECS 60000
 165 static void health_care(struct work_struct *work)
 166 {
 167         unsigned long recover_delay = msecs_to_jiffies(MLX5_RECOVERY_DELAY_MSECS);
 168         struct mlx5_core_health *health;
 169         struct mlx5_core_dev *dev;
 170         struct mlx5_priv *priv;
 171         unsigned long flags;
 172
 173         health = container_of(work, struct mlx5_core_health, work);
 174         priv = container_of(health, struct mlx5_priv, health);
 175         dev = container_of(priv, struct mlx5_core_dev, priv);
 176         mlx5_core_warn(dev, "handling bad device here\n");
 177         mlx5_handle_bad_state(dev);
 178
 179         spin_lock_irqsave(&health->wq_lock, flags);
 180         if (!test_bit(MLX5_DROP_NEW_RECOVERY_WORK, &health->flags))
 181                 schedule_delayed_work(&health->recover_work, recover_delay);
 182         else
 183                 dev_err(&dev->pdev->dev,
 184                         "new health works are not permitted at this stage\n");
 185         spin_unlock_irqrestore(&health->wq_lock, flags);
 186 }
 187
 188 static const char *hsynd_str(u8 synd)
 189 {
 190         switch (synd) {
 191         case MLX5_HEALTH_SYNDR_FW_ERR:
 192                 return "firmware internal error";
 193         case MLX5_HEALTH_SYNDR_IRISC_ERR:
 194                 return "irisc not responding";
 195         case MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR:
 196                 return "unrecoverable hardware error";
 197         case MLX5_HEALTH_SYNDR_CRC_ERR:
 198                 return "firmware CRC error";
 199         case MLX5_HEALTH_SYNDR_FETCH_PCI_ERR:
 200                 return "ICM fetch PCI error";
 201         case MLX5_HEALTH_SYNDR_HW_FTL_ERR:
 202                 return "HW fatal error\n";
 203         case MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR:
 204                 return "async EQ buffer overrun";
 205         case MLX5_HEALTH_SYNDR_EQ_ERR:
 206                 return "EQ error";
 207         case MLX5_HEALTH_SYNDR_EQ_INV:
 208                 return "Invalid EQ referenced";
 209         case MLX5_HEALTH_SYNDR_FFSER_ERR:
 210                 return "FFSER error";
 211         case MLX5_HEALTH_SYNDR_HIGH_TEMP:
 212                 return "High temperature";
 213         default:
 214                 return "unrecognized error";
 215         }
 216 }
 217
 218 static void print_health_info(struct mlx5_core_dev *dev)
 219 {
 220         struct mlx5_core_health *health = &dev->priv.health;
 221         struct health_buffer __iomem *h = health->health;
 222         char fw_str[18];
 223         u32 fw;
 224         int i;
 225
 226         /* If the syndrome is 0, the device is OK and no need to print buffer */
 227         if (!ioread8(&h->synd))
 228                 return;
 229
 230         for (i = 0; i < ARRAY_SIZE(h->assert_var); i++)
 231                 dev_err(&dev->pdev->dev, "assert_var[%d] 0x%08x\n", i, ioread32be(h->assert_var + i));
 232
 233         dev_err(&dev->pdev->dev, "assert_exit_ptr 0x%08x\n", ioread32be(&h->assert_exit_ptr));
 234         dev_err(&dev->pdev->dev, "assert_callra 0x%08x\n", ioread32be(&h->assert_callra));
 235         sprintf(fw_str, "%d.%d.%d", fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev));
 236         dev_err(&dev->pdev->dev, "fw_ver %s\n", fw_str);
 237         dev_err(&dev->pdev->dev, "hw_id 0x%08x\n", ioread32be(&h->hw_id));
 238         dev_err(&dev->pdev->dev, "irisc_index %d\n", ioread8(&h->irisc_index));
 239         dev_err(&dev->pdev->dev, "synd 0x%x: %s\n", ioread8(&h->synd), hsynd_str(ioread8(&h->synd)));
 240         dev_err(&dev->pdev->dev, "ext_synd 0x%04x\n", ioread16be(&h->ext_synd));
 241         fw = ioread32be(&h->fw_ver);
 242         dev_err(&dev->pdev->dev, "raw fw_ver 0x%08x\n", fw);
 243 }
 244
 245 static unsigned long get_next_poll_jiffies(void)
 246 {
 247         unsigned long next;
 248
 249         get_random_bytes(&next, sizeof(next));
 250         next %= HZ;
 251         next += jiffies + MLX5_HEALTH_POLL_INTERVAL;
 252
 253         return next;
 254 }
 255
 256 void mlx5_trigger_health_work(struct mlx5_core_dev *dev)
 257 {
 258         struct mlx5_core_health *health = &dev->priv.health;
 259         unsigned long flags;
 260
 261         spin_lock_irqsave(&health->wq_lock, flags);
 262         if (!test_bit(MLX5_DROP_NEW_HEALTH_WORK, &health->flags))
 263                 queue_work(health->wq, &health->work);
 264         else
 265                 dev_err(&dev->pdev->dev,
 266                         "new health works are not permitted at this stage\n");
 267         spin_unlock_irqrestore(&health->wq_lock, flags);
 268 }
 269
 270 static void poll_health(struct timer_list *t)
 271 {
 272         struct mlx5_core_dev *dev = from_timer(dev, t, priv.health.timer);
 273         struct mlx5_core_health *health = &dev->priv.health;
 274         u32 count;
 275
 276         if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
 277                 goto out;
 278
 279         count = ioread32be(health->health_counter);
 280         if (count == health->prev)
 281                 ++health->miss_counter;
 282         else
 283                 health->miss_counter = 0;
 284
 285         health->prev = count;
 286         if (health->miss_counter == MAX_MISSES) {
 287                 dev_err(&dev->pdev->dev, "device's health compromised - reached miss count\n");
 288                 print_health_info(dev);
 289         }
 290
 291         if (in_fatal(dev) && !health->sick) {
 292                 health->sick = true;
 293                 print_health_info(dev);
 294                 mlx5_trigger_health_work(dev);
 295         }
 296
 297 out:
 298         mod_timer(&health->timer, get_next_poll_jiffies());
 299 }
 300
 301 void mlx5_start_health_poll(struct mlx5_core_dev *dev)
 302 {
 303         struct mlx5_core_health *health = &dev->priv.health;
 304
 305         timer_setup(&health->timer, poll_health, 0);
 306         health->sick = 0;
 307         clear_bit(MLX5_DROP_NEW_HEALTH_WORK, &health->flags);
 308         clear_bit(MLX5_DROP_NEW_RECOVERY_WORK, &health->flags);
 309         health->health = &dev->iseg->health;
 310         health->health_counter = &dev->iseg->health_counter;
 311
 312         health->timer.expires = round_jiffies(jiffies + MLX5_HEALTH_POLL_INTERVAL);
 313         add_timer(&health->timer);
 314 }
 315
 316 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health)
 317 {
 318         struct mlx5_core_health *health = &dev->priv.health;
 319         unsigned long flags;
 320
 321         if (disable_health) {
 322                 spin_lock_irqsave(&health->wq_lock, flags);
 323                 set_bit(MLX5_DROP_NEW_HEALTH_WORK, &health->flags);
 324                 set_bit(MLX5_DROP_NEW_RECOVERY_WORK, &health->flags);
 325                 spin_unlock_irqrestore(&health->wq_lock, flags);
 326         }
 327
 328         del_timer_sync(&health->timer);
 329 }
 330
 331 void mlx5_drain_health_wq(struct mlx5_core_dev *dev)
 332 {
 333         struct mlx5_core_health *health = &dev->priv.health;
 334         unsigned long flags;
 335
 336         spin_lock_irqsave(&health->wq_lock, flags);
 337         set_bit(MLX5_DROP_NEW_HEALTH_WORK, &health->flags);
 338         set_bit(MLX5_DROP_NEW_RECOVERY_WORK, &health->flags);
 339         spin_unlock_irqrestore(&health->wq_lock, flags);
 340         cancel_delayed_work_sync(&health->recover_work);
 341         cancel_work_sync(&health->work);
 342 }
 343
 344 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev)
 345 {
 346         struct mlx5_core_health *health = &dev->priv.health;
 347         unsigned long flags;
 348
 349         spin_lock_irqsave(&health->wq_lock, flags);
 350         set_bit(MLX5_DROP_NEW_RECOVERY_WORK, &health->flags);
 351         spin_unlock_irqrestore(&health->wq_lock, flags);
 352         cancel_delayed_work_sync(&dev->priv.health.recover_work);
 353 }
 354
 355 void mlx5_health_cleanup(struct mlx5_core_dev *dev)
 356 {
 357         struct mlx5_core_health *health = &dev->priv.health;
 358
 359         destroy_workqueue(health->wq);
 360 }
 361
 362 int mlx5_health_init(struct mlx5_core_dev *dev)
 363 {
 364         struct mlx5_core_health *health;
 365         char *name;
 366
 367         health = &dev->priv.health;
 368         name = kmalloc(64, GFP_KERNEL);
 369         if (!name)
 370                 return -ENOMEM;
 371
 372         strcpy(name, "mlx5_health");
 373         strcat(name, dev_name(&dev->pdev->dev));
 374         health->wq = create_singlethread_workqueue(name);
 375         kfree(name);
 376         if (!health->wq)
 377                 return -ENOMEM;
 378         spin_lock_init(&health->wq_lock);
 379         INIT_WORK(&health->work, health_care);
 380         INIT_DELAYED_WORK(&health->recover_work, health_recover);
 381
 382         return 0;
 383 }