drivers/net/ethernet/pensando/ionic/ionic_if.h

   1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB OR BSD-2-Clause */
   2 /* Copyright (c) 2017-2019 Pensando Systems, Inc.  All rights reserved. */
   3
   4 #ifndef _IONIC_IF_H_
   5 #define _IONIC_IF_H_
   6
   7 #pragma pack(push, 1)
   8
   9 #define IONIC_DEV_INFO_SIGNATURE                0x44455649      /* 'DEVI' */
  10 #define IONIC_DEV_INFO_VERSION                  1
  11 #define IONIC_IFNAMSIZ                          16
  12
  13 /**
  14  * Commands
  15  */
  16 enum ionic_cmd_opcode {
  17         IONIC_CMD_NOP                           = 0,
  18
  19         /* Device commands */
  20         IONIC_CMD_IDENTIFY                      = 1,
  21         IONIC_CMD_INIT                          = 2,
  22         IONIC_CMD_RESET                         = 3,
  23         IONIC_CMD_GETATTR                       = 4,
  24         IONIC_CMD_SETATTR                       = 5,
  25
  26         /* Port commands */
  27         IONIC_CMD_PORT_IDENTIFY                 = 10,
  28         IONIC_CMD_PORT_INIT                     = 11,
  29         IONIC_CMD_PORT_RESET                    = 12,
  30         IONIC_CMD_PORT_GETATTR                  = 13,
  31         IONIC_CMD_PORT_SETATTR                  = 14,
  32
  33         /* LIF commands */
  34         IONIC_CMD_LIF_IDENTIFY                  = 20,
  35         IONIC_CMD_LIF_INIT                      = 21,
  36         IONIC_CMD_LIF_RESET                     = 22,
  37         IONIC_CMD_LIF_GETATTR                   = 23,
  38         IONIC_CMD_LIF_SETATTR                   = 24,
  39
  40         IONIC_CMD_RX_MODE_SET                   = 30,
  41         IONIC_CMD_RX_FILTER_ADD                 = 31,
  42         IONIC_CMD_RX_FILTER_DEL                 = 32,
  43
  44         /* Queue commands */
  45         IONIC_CMD_Q_INIT                        = 40,
  46         IONIC_CMD_Q_CONTROL                     = 41,
  47
  48         /* RDMA commands */
  49         IONIC_CMD_RDMA_RESET_LIF                = 50,
  50         IONIC_CMD_RDMA_CREATE_EQ                = 51,
  51         IONIC_CMD_RDMA_CREATE_CQ                = 52,
  52         IONIC_CMD_RDMA_CREATE_ADMINQ            = 53,
  53
  54         /* SR/IOV commands */
  55         IONIC_CMD_VF_GETATTR                    = 60,
  56         IONIC_CMD_VF_SETATTR                    = 61,
  57
  58         /* QoS commands */
  59         IONIC_CMD_QOS_CLASS_IDENTIFY            = 240,
  60         IONIC_CMD_QOS_CLASS_INIT                = 241,
  61         IONIC_CMD_QOS_CLASS_RESET               = 242,
  62
  63         /* Firmware commands */
  64         IONIC_CMD_FW_DOWNLOAD                   = 254,
  65         IONIC_CMD_FW_CONTROL                    = 255,
  66 };
  67
  68 /**
  69  * Command Return codes
  70  */
  71 enum ionic_status_code {
  72         IONIC_RC_SUCCESS        = 0,    /* Success */
  73         IONIC_RC_EVERSION       = 1,    /* Incorrect version for request */
  74         IONIC_RC_EOPCODE        = 2,    /* Invalid cmd opcode */
  75         IONIC_RC_EIO            = 3,    /* I/O error */
  76         IONIC_RC_EPERM          = 4,    /* Permission denied */
  77         IONIC_RC_EQID           = 5,    /* Bad qid */
  78         IONIC_RC_EQTYPE         = 6,    /* Bad qtype */
  79         IONIC_RC_ENOENT         = 7,    /* No such element */
  80         IONIC_RC_EINTR          = 8,    /* operation interrupted */
  81         IONIC_RC_EAGAIN         = 9,    /* Try again */
  82         IONIC_RC_ENOMEM         = 10,   /* Out of memory */
  83         IONIC_RC_EFAULT         = 11,   /* Bad address */
  84         IONIC_RC_EBUSY          = 12,   /* Device or resource busy */
  85         IONIC_RC_EEXIST         = 13,   /* object already exists */
  86         IONIC_RC_EINVAL         = 14,   /* Invalid argument */
  87         IONIC_RC_ENOSPC         = 15,   /* No space left or alloc failure */
  88         IONIC_RC_ERANGE         = 16,   /* Parameter out of range */
  89         IONIC_RC_BAD_ADDR       = 17,   /* Descriptor contains a bad ptr */
  90         IONIC_RC_DEV_CMD        = 18,   /* Device cmd attempted on AdminQ */
  91         IONIC_RC_ENOSUPP        = 19,   /* Operation not supported */
  92         IONIC_RC_ERROR          = 29,   /* Generic error */
  93
  94         IONIC_RC_ERDMA          = 30,   /* Generic RDMA error */
  95 };
  96
  97 enum ionic_notifyq_opcode {
  98         IONIC_EVENT_LINK_CHANGE         = 1,
  99         IONIC_EVENT_RESET               = 2,
 100         IONIC_EVENT_HEARTBEAT           = 3,
 101         IONIC_EVENT_LOG                 = 4,
 102 };
 103
 104 /**
 105  * struct cmd - General admin command format
 106  * @opcode:     Opcode for the command
 107  * @lif_index:  LIF index
 108  * @cmd_data:   Opcode-specific command bytes
 109  */
 110 struct ionic_admin_cmd {
 111         u8     opcode;
 112         u8     rsvd;
 113         __le16 lif_index;
 114         u8     cmd_data[60];
 115 };
 116
 117 /**
 118  * struct ionic_admin_comp - General admin command completion format
 119  * @status:     The status of the command (enum status_code)
 120  * @comp_index: The index in the descriptor ring for which this
 121  *              is the completion.
 122  * @cmd_data:   Command-specific bytes.
 123  * @color:      Color bit.  (Always 0 for commands issued to the
 124  *              Device Cmd Registers.)
 125  */
 126 struct ionic_admin_comp {
 127         u8     status;
 128         u8     rsvd;
 129         __le16 comp_index;
 130         u8     cmd_data[11];
 131         u8     color;
 132 #define IONIC_COMP_COLOR_MASK  0x80
 133 };
 134
 135 static inline u8 color_match(u8 color, u8 done_color)
 136 {
 137         return (!!(color & IONIC_COMP_COLOR_MASK)) == done_color;
 138 }
 139
 140 /**
 141  * struct ionic_nop_cmd - NOP command
 142  * @opcode: opcode
 143  */
 144 struct ionic_nop_cmd {
 145         u8 opcode;
 146         u8 rsvd[63];
 147 };
 148
 149 /**
 150  * struct ionic_nop_comp - NOP command completion
 151  * @status: The status of the command (enum status_code)
 152  */
 153 struct ionic_nop_comp {
 154         u8 status;
 155         u8 rsvd[15];
 156 };
 157
 158 /**
 159  * struct ionic_dev_init_cmd - Device init command
 160  * @opcode:    opcode
 161  * @type:      device type
 162  */
 163 struct ionic_dev_init_cmd {
 164         u8     opcode;
 165         u8     type;
 166         u8     rsvd[62];
 167 };
 168
 169 /**
 170  * struct init_comp - Device init command completion
 171  * @status: The status of the command (enum status_code)
 172  */
 173 struct ionic_dev_init_comp {
 174         u8 status;
 175         u8 rsvd[15];
 176 };
 177
 178 /**
 179  * struct ionic_dev_reset_cmd - Device reset command
 180  * @opcode: opcode
 181  */
 182 struct ionic_dev_reset_cmd {
 183         u8 opcode;
 184         u8 rsvd[63];
 185 };
 186
 187 /**
 188  * struct reset_comp - Reset command completion
 189  * @status: The status of the command (enum status_code)
 190  */
 191 struct ionic_dev_reset_comp {
 192         u8 status;
 193         u8 rsvd[15];
 194 };
 195
 196 #define IONIC_IDENTITY_VERSION_1        1
 197
 198 /**
 199  * struct ionic_dev_identify_cmd - Driver/device identify command
 200  * @opcode:  opcode
 201  * @ver:     Highest version of identify supported by driver
 202  */
 203 struct ionic_dev_identify_cmd {
 204         u8 opcode;
 205         u8 ver;
 206         u8 rsvd[62];
 207 };
 208
 209 /**
 210  * struct dev_identify_comp - Driver/device identify command completion
 211  * @status: The status of the command (enum status_code)
 212  * @ver:    Version of identify returned by device
 213  */
 214 struct ionic_dev_identify_comp {
 215         u8 status;
 216         u8 ver;
 217         u8 rsvd[14];
 218 };
 219
 220 enum ionic_os_type {
 221         IONIC_OS_TYPE_LINUX   = 1,
 222         IONIC_OS_TYPE_WIN     = 2,
 223         IONIC_OS_TYPE_DPDK    = 3,
 224         IONIC_OS_TYPE_FREEBSD = 4,
 225         IONIC_OS_TYPE_IPXE    = 5,
 226         IONIC_OS_TYPE_ESXI    = 6,
 227 };
 228
 229 /**
 230  * union drv_identity - driver identity information
 231  * @os_type:          OS type (see enum os_type)
 232  * @os_dist:          OS distribution, numeric format
 233  * @os_dist_str:      OS distribution, string format
 234  * @kernel_ver:       Kernel version, numeric format
 235  * @kernel_ver_str:   Kernel version, string format
 236  * @driver_ver_str:   Driver version, string format
 237  */
 238 union ionic_drv_identity {
 239         struct {
 240                 __le32 os_type;
 241                 __le32 os_dist;
 242                 char   os_dist_str[128];
 243                 __le32 kernel_ver;
 244                 char   kernel_ver_str[32];
 245                 char   driver_ver_str[32];
 246         };
 247         __le32 words[512];
 248 };
 249
 250 /**
 251  * union dev_identity - device identity information
 252  * @version:          Version of device identify
 253  * @type:             Identify type (0 for now)
 254  * @nports:           Number of ports provisioned
 255  * @nlifs:            Number of LIFs provisioned
 256  * @nintrs:           Number of interrupts provisioned
 257  * @ndbpgs_per_lif:   Number of doorbell pages per LIF
 258  * @intr_coal_mult:   Interrupt coalescing multiplication factor.
 259  *                    Scale user-supplied interrupt coalescing
 260  *                    value in usecs to device units using:
 261  *                    device units = usecs * mult / div
 262  * @intr_coal_div:    Interrupt coalescing division factor.
 263  *                    Scale user-supplied interrupt coalescing
 264  *                    value in usecs to device units using:
 265  *                    device units = usecs * mult / div
 266  *
 267  */
 268 union ionic_dev_identity {
 269         struct {
 270                 u8     version;
 271                 u8     type;
 272                 u8     rsvd[2];
 273                 u8     nports;
 274                 u8     rsvd2[3];
 275                 __le32 nlifs;
 276                 __le32 nintrs;
 277                 __le32 ndbpgs_per_lif;
 278                 __le32 intr_coal_mult;
 279                 __le32 intr_coal_div;
 280         };
 281         __le32 words[512];
 282 };
 283
 284 enum ionic_lif_type {
 285         IONIC_LIF_TYPE_CLASSIC = 0,
 286         IONIC_LIF_TYPE_MACVLAN = 1,
 287         IONIC_LIF_TYPE_NETQUEUE = 2,
 288 };
 289
 290 /**
 291  * struct ionic_lif_identify_cmd - lif identify command
 292  * @opcode:  opcode
 293  * @type:    lif type (enum lif_type)
 294  * @ver:     version of identify returned by device
 295  */
 296 struct ionic_lif_identify_cmd {
 297         u8 opcode;
 298         u8 type;
 299         u8 ver;
 300         u8 rsvd[61];
 301 };
 302
 303 /**
 304  * struct ionic_lif_identify_comp - lif identify command completion
 305  * @status:  status of the command (enum status_code)
 306  * @ver:     version of identify returned by device
 307  */
 308 struct ionic_lif_identify_comp {
 309         u8 status;
 310         u8 ver;
 311         u8 rsvd2[14];
 312 };
 313
 314 enum ionic_lif_capability {
 315         IONIC_LIF_CAP_ETH        = BIT(0),
 316         IONIC_LIF_CAP_RDMA       = BIT(1),
 317 };
 318
 319 /**
 320  * Logical Queue Types
 321  */
 322 enum ionic_logical_qtype {
 323         IONIC_QTYPE_ADMINQ  = 0,
 324         IONIC_QTYPE_NOTIFYQ = 1,
 325         IONIC_QTYPE_RXQ     = 2,
 326         IONIC_QTYPE_TXQ     = 3,
 327         IONIC_QTYPE_EQ      = 4,
 328         IONIC_QTYPE_MAX     = 16,
 329 };
 330
 331 /**
 332  * struct ionic_lif_logical_qtype - Descriptor of logical to hardware queue type.
 333  * @qtype:          Hardware Queue Type.
 334  * @qid_count:      Number of Queue IDs of the logical type.
 335  * @qid_base:       Minimum Queue ID of the logical type.
 336  */
 337 struct ionic_lif_logical_qtype {
 338         u8     qtype;
 339         u8     rsvd[3];
 340         __le32 qid_count;
 341         __le32 qid_base;
 342 };
 343
 344 enum ionic_lif_state {
 345         IONIC_LIF_DISABLE       = 0,
 346         IONIC_LIF_ENABLE        = 1,
 347         IONIC_LIF_HANG_RESET    = 2,
 348 };
 349
 350 /**
 351  * LIF configuration
 352  * @state:          lif state (enum lif_state)
 353  * @name:           lif name
 354  * @mtu:            mtu
 355  * @mac:            station mac address
 356  * @features:       features (enum ionic_eth_hw_features)
 357  * @queue_count:    queue counts per queue-type
 358  */
 359 union ionic_lif_config {
 360         struct {
 361                 u8     state;
 362                 u8     rsvd[3];
 363                 char   name[IONIC_IFNAMSIZ];
 364                 __le32 mtu;
 365                 u8     mac[6];
 366                 u8     rsvd2[2];
 367                 __le64 features;
 368                 __le32 queue_count[IONIC_QTYPE_MAX];
 369         };
 370         __le32 words[64];
 371 };
 372
 373 /**
 374  * struct ionic_lif_identity - lif identity information (type-specific)
 375  *
 376  * @capabilities    LIF capabilities
 377  *
 378  * Ethernet:
 379  *     @version:          Ethernet identify structure version.
 380  *     @features:         Ethernet features supported on this lif type.
 381  *     @max_ucast_filters:  Number of perfect unicast addresses supported.
 382  *     @max_mcast_filters:  Number of perfect multicast addresses supported.
 383  *     @min_frame_size:   Minimum size of frames to be sent
 384  *     @max_frame_size:   Maximim size of frames to be sent
 385  *     @config:           LIF config struct with features, mtu, mac, q counts
 386  *
 387  * RDMA:
 388  *     @version:         RDMA version of opcodes and queue descriptors.
 389  *     @qp_opcodes:      Number of rdma queue pair opcodes supported.
 390  *     @admin_opcodes:   Number of rdma admin opcodes supported.
 391  *     @npts_per_lif:    Page table size per lif
 392  *     @nmrs_per_lif:    Number of memory regions per lif
 393  *     @nahs_per_lif:    Number of address handles per lif
 394  *     @max_stride:      Max work request stride.
 395  *     @cl_stride:       Cache line stride.
 396  *     @pte_stride:      Page table entry stride.
 397  *     @rrq_stride:      Remote RQ work request stride.
 398  *     @rsq_stride:      Remote SQ work request stride.
 399  *     @dcqcn_profiles:  Number of DCQCN profiles
 400  *     @aq_qtype:        RDMA Admin Qtype.
 401  *     @sq_qtype:        RDMA Send Qtype.
 402  *     @rq_qtype:        RDMA Receive Qtype.
 403  *     @cq_qtype:        RDMA Completion Qtype.
 404  *     @eq_qtype:        RDMA Event Qtype.
 405  */
 406 union ionic_lif_identity {
 407         struct {
 408                 __le64 capabilities;
 409
 410                 struct {
 411                         u8 version;
 412                         u8 rsvd[3];
 413                         __le32 max_ucast_filters;
 414                         __le32 max_mcast_filters;
 415                         __le16 rss_ind_tbl_sz;
 416                         __le32 min_frame_size;
 417                         __le32 max_frame_size;
 418                         u8 rsvd2[106];
 419                         union ionic_lif_config config;
 420                 } eth;
 421
 422                 struct {
 423                         u8 version;
 424                         u8 qp_opcodes;
 425                         u8 admin_opcodes;
 426                         u8 rsvd;
 427                         __le32 npts_per_lif;
 428                         __le32 nmrs_per_lif;
 429                         __le32 nahs_per_lif;
 430                         u8 max_stride;
 431                         u8 cl_stride;
 432                         u8 pte_stride;
 433                         u8 rrq_stride;
 434                         u8 rsq_stride;
 435                         u8 dcqcn_profiles;
 436                         u8 rsvd_dimensions[10];
 437                         struct ionic_lif_logical_qtype aq_qtype;
 438                         struct ionic_lif_logical_qtype sq_qtype;
 439                         struct ionic_lif_logical_qtype rq_qtype;
 440                         struct ionic_lif_logical_qtype cq_qtype;
 441                         struct ionic_lif_logical_qtype eq_qtype;
 442                 } rdma;
 443         };
 444         __le32 words[512];
 445 };
 446
 447 /**
 448  * struct ionic_lif_init_cmd - LIF init command
 449  * @opcode:       opcode
 450  * @type:         LIF type (enum lif_type)
 451  * @index:        LIF index
 452  * @info_pa:      destination address for lif info (struct ionic_lif_info)
 453  */
 454 struct ionic_lif_init_cmd {
 455         u8     opcode;
 456         u8     type;
 457         __le16 index;
 458         __le32 rsvd;
 459         __le64 info_pa;
 460         u8     rsvd2[48];
 461 };
 462
 463 /**
 464  * struct ionic_lif_init_comp - LIF init command completion
 465  * @status: The status of the command (enum status_code)
 466  */
 467 struct ionic_lif_init_comp {
 468         u8 status;
 469         u8 rsvd;
 470         __le16 hw_index;
 471         u8 rsvd2[12];
 472 };
 473
 474 /**
 475  * struct ionic_q_init_cmd - Queue init command
 476  * @opcode:       opcode
 477  * @type:         Logical queue type
 478  * @ver:          Queue version (defines opcode/descriptor scope)
 479  * @lif_index:    LIF index
 480  * @index:        (lif, qtype) relative admin queue index
 481  * @intr_index:   Interrupt control register index
 482  * @pid:          Process ID
 483  * @flags:
 484  *    IRQ:        Interrupt requested on completion
 485  *    ENA:        Enable the queue.  If ENA=0 the queue is initialized
 486  *                but remains disabled, to be later enabled with the
 487  *                Queue Enable command.  If ENA=1, then queue is
 488  *                initialized and then enabled.
 489  *    SG:         Enable Scatter-Gather on the queue.
 490  *                in number of descs.  The actual ring size is
 491  *                (1 << ring_size).  For example, to
 492  *                select a ring size of 64 descriptors write
 493  *                ring_size = 6.  The minimum ring_size value is 2
 494  *                for a ring size of 4 descriptors.  The maximum
 495  *                ring_size value is 16 for a ring size of 64k
 496  *                descriptors.  Values of ring_size <2 and >16 are
 497  *                reserved.
 498  *    EQ:         Enable the Event Queue
 499  * @cos:          Class of service for this queue.
 500  * @ring_size:    Queue ring size, encoded as a log2(size)
 501  * @ring_base:    Queue ring base address
 502  * @cq_ring_base: Completion queue ring base address
 503  * @sg_ring_base: Scatter/Gather ring base address
 504  * @eq_index:     Event queue index
 505  */
 506 struct ionic_q_init_cmd {
 507         u8     opcode;
 508         u8     rsvd;
 509         __le16 lif_index;
 510         u8     type;
 511         u8     ver;
 512         u8     rsvd1[2];
 513         __le32 index;
 514         __le16 pid;
 515         __le16 intr_index;
 516         __le16 flags;
 517 #define IONIC_QINIT_F_IRQ       0x01    /* Request interrupt on completion */
 518 #define IONIC_QINIT_F_ENA       0x02    /* Enable the queue */
 519 #define IONIC_QINIT_F_SG        0x04    /* Enable scatter/gather on the queue */
 520 #define IONIC_QINIT_F_EQ        0x08    /* Enable event queue */
 521 #define IONIC_QINIT_F_DEBUG 0x80        /* Enable queue debugging */
 522         u8     cos;
 523         u8     ring_size;
 524         __le64 ring_base;
 525         __le64 cq_ring_base;
 526         __le64 sg_ring_base;
 527         __le32 eq_index;
 528         u8     rsvd2[16];
 529 };
 530
 531 /**
 532  * struct ionic_q_init_comp - Queue init command completion
 533  * @status:     The status of the command (enum status_code)
 534  * @ver:        Queue version (defines opcode/descriptor scope)
 535  * @comp_index: The index in the descriptor ring for which this
 536  *              is the completion.
 537  * @hw_index:   Hardware Queue ID
 538  * @hw_type:    Hardware Queue type
 539  * @color:      Color
 540  */
 541 struct ionic_q_init_comp {
 542         u8     status;
 543         u8     ver;
 544         __le16 comp_index;
 545         __le32 hw_index;
 546         u8     hw_type;
 547         u8     rsvd2[6];
 548         u8     color;
 549 };
 550
 551 /* the device's internal addressing uses up to 52 bits */
 552 #define IONIC_ADDR_LEN          52
 553 #define IONIC_ADDR_MASK         (BIT_ULL(IONIC_ADDR_LEN) - 1)
 554
 555 enum ionic_txq_desc_opcode {
 556         IONIC_TXQ_DESC_OPCODE_CSUM_NONE = 0,
 557         IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL = 1,
 558         IONIC_TXQ_DESC_OPCODE_CSUM_HW = 2,
 559         IONIC_TXQ_DESC_OPCODE_TSO = 3,
 560 };
 561
 562 /**
 563  * struct ionic_txq_desc - Ethernet Tx queue descriptor format
 564  * @opcode:       Tx operation, see TXQ_DESC_OPCODE_*:
 565  *
 566  *                   IONIC_TXQ_DESC_OPCODE_CSUM_NONE:
 567  *
 568  *                      Non-offload send.  No segmentation,
 569  *                      fragmentation or checksum calc/insertion is
 570  *                      performed by device; packet is prepared
 571  *                      to send by software stack and requires
 572  *                      no further manipulation from device.
 573  *
 574  *                   IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL:
 575  *
 576  *                      Offload 16-bit L4 checksum
 577  *                      calculation/insertion.  The device will
 578  *                      calculate the L4 checksum value and
 579  *                      insert the result in the packet's L4
 580  *                      header checksum field.  The L4 checksum
 581  *                      is calculated starting at @csum_start bytes
 582  *                      into the packet to the end of the packet.
 583  *                      The checksum insertion position is given
 584  *                      in @csum_offset.  This feature is only
 585  *                      applicable to protocols such as TCP, UDP
 586  *                      and ICMP where a standard (i.e. the
 587  *                      'IP-style' checksum) one's complement
 588  *                      16-bit checksum is used, using an IP
 589  *                      pseudo-header to seed the calculation.
 590  *                      Software will preload the L4 checksum
 591  *                      field with the IP pseudo-header checksum.
 592  *
 593  *                      For tunnel encapsulation, @csum_start and
 594  *                      @csum_offset refer to the inner L4
 595  *                      header.  Supported tunnels encapsulations
 596  *                      are: IPIP, GRE, and UDP.  If the @encap
 597  *                      is clear, no further processing by the
 598  *                      device is required; software will
 599  *                      calculate the outer header checksums.  If
 600  *                      the @encap is set, the device will
 601  *                      offload the outer header checksums using
 602  *                      LCO (local checksum offload) (see
 603  *                      Documentation/networking/checksum-offloads.rst
 604  *                      for more info).
 605  *
 606  *                   IONIC_TXQ_DESC_OPCODE_CSUM_HW:
 607  *
 608  *                      Offload 16-bit checksum computation to hardware.
 609  *                      If @csum_l3 is set then the packet's L3 checksum is
 610  *                      updated. Similarly, if @csum_l4 is set the the L4
 611  *                      checksum is updated. If @encap is set then encap header
 612  *                      checksums are also updated.
 613  *
 614  *                   IONIC_TXQ_DESC_OPCODE_TSO:
 615  *
 616  *                      Device preforms TCP segmentation offload
 617  *                      (TSO).  @hdr_len is the number of bytes
 618  *                      to the end of TCP header (the offset to
 619  *                      the TCP payload).  @mss is the desired
 620  *                      MSS, the TCP payload length for each
 621  *                      segment.  The device will calculate/
 622  *                      insert IP (IPv4 only) and TCP checksums
 623  *                      for each segment.  In the first data
 624  *                      buffer containing the header template,
 625  *                      the driver will set IPv4 checksum to 0
 626  *                      and preload TCP checksum with the IP
 627  *                      pseudo header calculated with IP length = 0.
 628  *
 629  *                      Supported tunnel encapsulations are IPIP,
 630  *                      layer-3 GRE, and UDP. @hdr_len includes
 631  *                      both outer and inner headers.  The driver
 632  *                      will set IPv4 checksum to zero and
 633  *                      preload TCP checksum with IP pseudo
 634  *                      header on the inner header.
 635  *
 636  *                      TCP ECN offload is supported.  The device
 637  *                      will set CWR flag in the first segment if
 638  *                      CWR is set in the template header, and
 639  *                      clear CWR in remaining segments.
 640  * @flags:
 641  *                vlan:
 642  *                    Insert an L2 VLAN header using @vlan_tci.
 643  *                encap:
 644  *                    Calculate encap header checksum.
 645  *                csum_l3:
 646  *                    Compute L3 header checksum.
 647  *                csum_l4:
 648  *                    Compute L4 header checksum.
 649  *                tso_sot:
 650  *                    TSO start
 651  *                tso_eot:
 652  *                    TSO end
 653  * @num_sg_elems: Number of scatter-gather elements in SG
 654  *                descriptor
 655  * @addr:         First data buffer's DMA address.
 656  *                (Subsequent data buffers are on txq_sg_desc).
 657  * @len:          First data buffer's length, in bytes
 658  * @vlan_tci:     VLAN tag to insert in the packet (if requested
 659  *                by @V-bit).  Includes .1p and .1q tags
 660  * @hdr_len:      Length of packet headers, including
 661  *                encapsulating outer header, if applicable.
 662  *                Valid for opcodes TXQ_DESC_OPCODE_CALC_CSUM and
 663  *                TXQ_DESC_OPCODE_TSO.  Should be set to zero for
 664  *                all other modes.  For
 665  *                TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length
 666  *                of headers up to inner-most L4 header.  For
 667  *                TXQ_DESC_OPCODE_TSO, @hdr_len is up to
 668  *                inner-most L4 payload, so inclusive of
 669  *                inner-most L4 header.
 670  * @mss:          Desired MSS value for TSO.  Only applicable for
 671  *                TXQ_DESC_OPCODE_TSO.
 672  * @csum_start:   Offset into inner-most L3 header of checksum
 673  * @csum_offset:  Offset into inner-most L4 header of checksum
 674  */
 675
 676 #define IONIC_TXQ_DESC_OPCODE_MASK              0xf
 677 #define IONIC_TXQ_DESC_OPCODE_SHIFT             4
 678 #define IONIC_TXQ_DESC_FLAGS_MASK               0xf
 679 #define IONIC_TXQ_DESC_FLAGS_SHIFT              0
 680 #define IONIC_TXQ_DESC_NSGE_MASK                0xf
 681 #define IONIC_TXQ_DESC_NSGE_SHIFT               8
 682 #define IONIC_TXQ_DESC_ADDR_MASK                (BIT_ULL(IONIC_ADDR_LEN) - 1)
 683 #define IONIC_TXQ_DESC_ADDR_SHIFT               12
 684
 685 /* common flags */
 686 #define IONIC_TXQ_DESC_FLAG_VLAN                0x1
 687 #define IONIC_TXQ_DESC_FLAG_ENCAP               0x2
 688
 689 /* flags for csum_hw opcode */
 690 #define IONIC_TXQ_DESC_FLAG_CSUM_L3             0x4
 691 #define IONIC_TXQ_DESC_FLAG_CSUM_L4             0x8
 692
 693 /* flags for tso opcode */
 694 #define IONIC_TXQ_DESC_FLAG_TSO_SOT             0x4
 695 #define IONIC_TXQ_DESC_FLAG_TSO_EOT             0x8
 696
 697 struct ionic_txq_desc {
 698         __le64  cmd;
 699         __le16  len;
 700         union {
 701                 __le16  vlan_tci;
 702                 __le16  hword0;
 703         };
 704         union {
 705                 __le16  csum_start;
 706                 __le16  hdr_len;
 707                 __le16  hword1;
 708         };
 709         union {
 710                 __le16  csum_offset;
 711                 __le16  mss;
 712                 __le16  hword2;
 713         };
 714 };
 715
 716 static inline u64 encode_txq_desc_cmd(u8 opcode, u8 flags,
 717                                       u8 nsge, u64 addr)
 718 {
 719         u64 cmd;
 720
 721         cmd = (opcode & IONIC_TXQ_DESC_OPCODE_MASK) << IONIC_TXQ_DESC_OPCODE_SHIFT;
 722         cmd |= (flags & IONIC_TXQ_DESC_FLAGS_MASK) << IONIC_TXQ_DESC_FLAGS_SHIFT;
 723         cmd |= (nsge & IONIC_TXQ_DESC_NSGE_MASK) << IONIC_TXQ_DESC_NSGE_SHIFT;
 724         cmd |= (addr & IONIC_TXQ_DESC_ADDR_MASK) << IONIC_TXQ_DESC_ADDR_SHIFT;
 725
 726         return cmd;
 727 };
 728
 729 static inline void decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags,
 730                                        u8 *nsge, u64 *addr)
 731 {
 732         *opcode = (cmd >> IONIC_TXQ_DESC_OPCODE_SHIFT) & IONIC_TXQ_DESC_OPCODE_MASK;
 733         *flags = (cmd >> IONIC_TXQ_DESC_FLAGS_SHIFT) & IONIC_TXQ_DESC_FLAGS_MASK;
 734         *nsge = (cmd >> IONIC_TXQ_DESC_NSGE_SHIFT) & IONIC_TXQ_DESC_NSGE_MASK;
 735         *addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) & IONIC_TXQ_DESC_ADDR_MASK;
 736 };
 737
 738 #define IONIC_TX_MAX_SG_ELEMS   8
 739 #define IONIC_RX_MAX_SG_ELEMS   8
 740
 741 /**
 742  * struct ionic_txq_sg_desc - Transmit scatter-gather (SG) list
 743  * @addr:      DMA address of SG element data buffer
 744  * @len:       Length of SG element data buffer, in bytes
 745  */
 746 struct ionic_txq_sg_desc {
 747         struct ionic_txq_sg_elem {
 748                 __le64 addr;
 749                 __le16 len;
 750                 __le16 rsvd[3];
 751         } elems[IONIC_TX_MAX_SG_ELEMS];
 752 };
 753
 754 /**
 755  * struct ionic_txq_comp - Ethernet transmit queue completion descriptor
 756  * @status:     The status of the command (enum status_code)
 757  * @comp_index: The index in the descriptor ring for which this
 758  *                 is the completion.
 759  * @color:      Color bit.
 760  */
 761 struct ionic_txq_comp {
 762         u8     status;
 763         u8     rsvd;
 764         __le16 comp_index;
 765         u8     rsvd2[11];
 766         u8     color;
 767 };
 768
 769 enum ionic_rxq_desc_opcode {
 770         IONIC_RXQ_DESC_OPCODE_SIMPLE = 0,
 771         IONIC_RXQ_DESC_OPCODE_SG = 1,
 772 };
 773
 774 /**
 775  * struct ionic_rxq_desc - Ethernet Rx queue descriptor format
 776  * @opcode:       Rx operation, see RXQ_DESC_OPCODE_*:
 777  *
 778  *                   RXQ_DESC_OPCODE_SIMPLE:
 779  *
 780  *                      Receive full packet into data buffer
 781  *                      starting at @addr.  Results of
 782  *                      receive, including actual bytes received,
 783  *                      are recorded in Rx completion descriptor.
 784  *
 785  * @len:          Data buffer's length, in bytes.
 786  * @addr:         Data buffer's DMA address
 787  */
 788 struct ionic_rxq_desc {
 789         u8     opcode;
 790         u8     rsvd[5];
 791         __le16 len;
 792         __le64 addr;
 793 };
 794
 795 /**
 796  * struct ionic_rxq_sg_desc - Receive scatter-gather (SG) list
 797  * @addr:      DMA address of SG element data buffer
 798  * @len:       Length of SG element data buffer, in bytes
 799  */
 800 struct ionic_rxq_sg_desc {
 801         struct ionic_rxq_sg_elem {
 802                 __le64 addr;
 803                 __le16 len;
 804                 __le16 rsvd[3];
 805         } elems[IONIC_RX_MAX_SG_ELEMS];
 806 };
 807
 808 /**
 809  * struct ionic_rxq_comp - Ethernet receive queue completion descriptor
 810  * @status:       The status of the command (enum status_code)
 811  * @num_sg_elems: Number of SG elements used by this descriptor
 812  * @comp_index:   The index in the descriptor ring for which this
 813  *                is the completion.
 814  * @rss_hash:     32-bit RSS hash
 815  * @csum:         16-bit sum of the packet's L2 payload.
 816  *                If the packet's L2 payload is odd length, an extra
 817  *                zero-value byte is included in the @csum calculation but
 818  *                not included in @len.
 819  * @vlan_tci:     VLAN tag stripped from the packet.  Valid if @VLAN is
 820  *                set.  Includes .1p and .1q tags.
 821  * @len:          Received packet length, in bytes.  Excludes FCS.
 822  * @csum_calc     L2 payload checksum is computed or not
 823  * @csum_tcp_ok:  The TCP checksum calculated by the device
 824  *                matched the checksum in the receive packet's
 825  *                TCP header
 826  * @csum_tcp_bad: The TCP checksum calculated by the device did
 827  *                not match the checksum in the receive packet's
 828  *                TCP header.
 829  * @csum_udp_ok:  The UDP checksum calculated by the device
 830  *                matched the checksum in the receive packet's
 831  *                UDP header
 832  * @csum_udp_bad: The UDP checksum calculated by the device did
 833  *                not match the checksum in the receive packet's
 834  *                UDP header.
 835  * @csum_ip_ok:   The IPv4 checksum calculated by the device
 836  *                matched the checksum in the receive packet's
 837  *                first IPv4 header.  If the receive packet
 838  *                contains both a tunnel IPv4 header and a
 839  *                transport IPv4 header, the device validates the
 840  *                checksum for the both IPv4 headers.
 841  * @csum_ip_bad:  The IPv4 checksum calculated by the device did
 842  *                not match the checksum in the receive packet's
 843  *                first IPv4 header. If the receive packet
 844  *                contains both a tunnel IPv4 header and a
 845  *                transport IPv4 header, the device validates the
 846  *                checksum for both IP headers.
 847  * @VLAN:         VLAN header was stripped and placed in @vlan_tci.
 848  * @pkt_type:     Packet type
 849  * @color:        Color bit.
 850  */
 851 struct ionic_rxq_comp {
 852         u8     status;
 853         u8     num_sg_elems;
 854         __le16 comp_index;
 855         __le32 rss_hash;
 856         __le16 csum;
 857         __le16 vlan_tci;
 858         __le16 len;
 859         u8     csum_flags;
 860 #define IONIC_RXQ_COMP_CSUM_F_TCP_OK    0x01
 861 #define IONIC_RXQ_COMP_CSUM_F_TCP_BAD   0x02
 862 #define IONIC_RXQ_COMP_CSUM_F_UDP_OK    0x04
 863 #define IONIC_RXQ_COMP_CSUM_F_UDP_BAD   0x08
 864 #define IONIC_RXQ_COMP_CSUM_F_IP_OK     0x10
 865 #define IONIC_RXQ_COMP_CSUM_F_IP_BAD    0x20
 866 #define IONIC_RXQ_COMP_CSUM_F_VLAN      0x40
 867 #define IONIC_RXQ_COMP_CSUM_F_CALC      0x80
 868         u8     pkt_type_color;
 869 #define IONIC_RXQ_COMP_PKT_TYPE_MASK    0x7f
 870 };
 871
 872 enum ionic_pkt_type {
 873         IONIC_PKT_TYPE_NON_IP     = 0x000,
 874         IONIC_PKT_TYPE_IPV4       = 0x001,
 875         IONIC_PKT_TYPE_IPV4_TCP   = 0x003,
 876         IONIC_PKT_TYPE_IPV4_UDP   = 0x005,
 877         IONIC_PKT_TYPE_IPV6       = 0x008,
 878         IONIC_PKT_TYPE_IPV6_TCP   = 0x018,
 879         IONIC_PKT_TYPE_IPV6_UDP   = 0x028,
 880 };
 881
 882 enum ionic_eth_hw_features {
 883         IONIC_ETH_HW_VLAN_TX_TAG        = BIT(0),
 884         IONIC_ETH_HW_VLAN_RX_STRIP      = BIT(1),
 885         IONIC_ETH_HW_VLAN_RX_FILTER     = BIT(2),
 886         IONIC_ETH_HW_RX_HASH            = BIT(3),
 887         IONIC_ETH_HW_RX_CSUM            = BIT(4),
 888         IONIC_ETH_HW_TX_SG              = BIT(5),
 889         IONIC_ETH_HW_RX_SG              = BIT(6),
 890         IONIC_ETH_HW_TX_CSUM            = BIT(7),
 891         IONIC_ETH_HW_TSO                = BIT(8),
 892         IONIC_ETH_HW_TSO_IPV6           = BIT(9),
 893         IONIC_ETH_HW_TSO_ECN            = BIT(10),
 894         IONIC_ETH_HW_TSO_GRE            = BIT(11),
 895         IONIC_ETH_HW_TSO_GRE_CSUM       = BIT(12),
 896         IONIC_ETH_HW_TSO_IPXIP4 = BIT(13),
 897         IONIC_ETH_HW_TSO_IPXIP6 = BIT(14),
 898         IONIC_ETH_HW_TSO_UDP            = BIT(15),
 899         IONIC_ETH_HW_TSO_UDP_CSUM       = BIT(16),
 900 };
 901
 902 /**
 903  * struct ionic_q_control_cmd - Queue control command
 904  * @opcode:     opcode
 905  * @type:       Queue type
 906  * @lif_index:  LIF index
 907  * @index:      Queue index
 908  * @oper:       Operation (enum q_control_oper)
 909  */
 910 struct ionic_q_control_cmd {
 911         u8     opcode;
 912         u8     type;
 913         __le16 lif_index;
 914         __le32 index;
 915         u8     oper;
 916         u8     rsvd[55];
 917 };
 918
 919 typedef struct ionic_admin_comp ionic_q_control_comp;
 920
 921 enum q_control_oper {
 922         IONIC_Q_DISABLE         = 0,
 923         IONIC_Q_ENABLE          = 1,
 924         IONIC_Q_HANG_RESET      = 2,
 925 };
 926
 927 /**
 928  * Physical connection type
 929  */
 930 enum ionic_phy_type {
 931         IONIC_PHY_TYPE_NONE     = 0,
 932         IONIC_PHY_TYPE_COPPER   = 1,
 933         IONIC_PHY_TYPE_FIBER    = 2,
 934 };
 935
 936 /**
 937  * Transceiver status
 938  */
 939 enum ionic_xcvr_state {
 940         IONIC_XCVR_STATE_REMOVED         = 0,
 941         IONIC_XCVR_STATE_INSERTED        = 1,
 942         IONIC_XCVR_STATE_PENDING         = 2,
 943         IONIC_XCVR_STATE_SPROM_READ      = 3,
 944         IONIC_XCVR_STATE_SPROM_READ_ERR  = 4,
 945 };
 946
 947 /**
 948  * Supported link modes
 949  */
 950 enum ionic_xcvr_pid {
 951         IONIC_XCVR_PID_UNKNOWN           = 0,
 952
 953         /* CU */
 954         IONIC_XCVR_PID_QSFP_100G_CR4     = 1,
 955         IONIC_XCVR_PID_QSFP_40GBASE_CR4  = 2,
 956         IONIC_XCVR_PID_SFP_25GBASE_CR_S  = 3,
 957         IONIC_XCVR_PID_SFP_25GBASE_CR_L  = 4,
 958         IONIC_XCVR_PID_SFP_25GBASE_CR_N  = 5,
 959
 960         /* Fiber */
 961         IONIC_XCVR_PID_QSFP_100G_AOC    = 50,
 962         IONIC_XCVR_PID_QSFP_100G_ACC    = 51,
 963         IONIC_XCVR_PID_QSFP_100G_SR4    = 52,
 964         IONIC_XCVR_PID_QSFP_100G_LR4    = 53,
 965         IONIC_XCVR_PID_QSFP_100G_ER4    = 54,
 966         IONIC_XCVR_PID_QSFP_40GBASE_ER4 = 55,
 967         IONIC_XCVR_PID_QSFP_40GBASE_SR4 = 56,
 968         IONIC_XCVR_PID_QSFP_40GBASE_LR4 = 57,
 969         IONIC_XCVR_PID_QSFP_40GBASE_AOC = 58,
 970         IONIC_XCVR_PID_SFP_25GBASE_SR   = 59,
 971         IONIC_XCVR_PID_SFP_25GBASE_LR   = 60,
 972         IONIC_XCVR_PID_SFP_25GBASE_ER   = 61,
 973         IONIC_XCVR_PID_SFP_25GBASE_AOC  = 62,
 974         IONIC_XCVR_PID_SFP_10GBASE_SR   = 63,
 975         IONIC_XCVR_PID_SFP_10GBASE_LR   = 64,
 976         IONIC_XCVR_PID_SFP_10GBASE_LRM  = 65,
 977         IONIC_XCVR_PID_SFP_10GBASE_ER   = 66,
 978         IONIC_XCVR_PID_SFP_10GBASE_AOC  = 67,
 979         IONIC_XCVR_PID_SFP_10GBASE_CU   = 68,
 980         IONIC_XCVR_PID_QSFP_100G_CWDM4  = 69,
 981         IONIC_XCVR_PID_QSFP_100G_PSM4   = 70,
 982 };
 983
 984 /**
 985  * Port types
 986  */
 987 enum ionic_port_type {
 988         IONIC_PORT_TYPE_NONE = 0,  /* port type not configured */
 989         IONIC_PORT_TYPE_ETH  = 1,  /* port carries ethernet traffic (inband) */
 990         IONIC_PORT_TYPE_MGMT = 2,  /* port carries mgmt traffic (out-of-band) */
 991 };
 992
 993 /**
 994  * Port config state
 995  */
 996 enum ionic_port_admin_state {
 997         IONIC_PORT_ADMIN_STATE_NONE = 0,   /* port admin state not configured */
 998         IONIC_PORT_ADMIN_STATE_DOWN = 1,   /* port is admin disabled */
 999         IONIC_PORT_ADMIN_STATE_UP   = 2,   /* port is admin enabled */
1000 };
1001
1002 /**
1003  * Port operational status
1004  */
1005 enum ionic_port_oper_status {
1006         IONIC_PORT_OPER_STATUS_NONE  = 0,       /* port is disabled */
1007         IONIC_PORT_OPER_STATUS_UP    = 1,       /* port is linked up */
1008         IONIC_PORT_OPER_STATUS_DOWN  = 2,       /* port link status is down */
1009 };
1010
1011 /**
1012  * Ethernet Forward error correction (fec) modes
1013  */
1014 enum ionic_port_fec_type {
1015         IONIC_PORT_FEC_TYPE_NONE = 0,           /* Disabled */
1016         IONIC_PORT_FEC_TYPE_FC   = 1,           /* FireCode */
1017         IONIC_PORT_FEC_TYPE_RS   = 2,           /* ReedSolomon */
1018 };
1019
1020 /**
1021  * Ethernet pause (flow control) modes
1022  */
1023 enum ionic_port_pause_type {
1024         IONIC_PORT_PAUSE_TYPE_NONE = 0, /* Disable Pause */
1025         IONIC_PORT_PAUSE_TYPE_LINK = 1, /* Link level pause */
1026         IONIC_PORT_PAUSE_TYPE_PFC  = 2, /* Priority-Flow control */
1027 };
1028
1029 /**
1030  * Loopback modes
1031  */
1032 enum ionic_port_loopback_mode {
1033         IONIC_PORT_LOOPBACK_MODE_NONE = 0,      /* Disable loopback */
1034         IONIC_PORT_LOOPBACK_MODE_MAC  = 1,      /* MAC loopback */
1035         IONIC_PORT_LOOPBACK_MODE_PHY  = 2,      /* PHY/Serdes loopback */
1036 };
1037
1038 /**
1039  * Transceiver Status information
1040  * @state:    Transceiver status (enum ionic_xcvr_state)
1041  * @phy:      Physical connection type (enum ionic_phy_type)
1042  * @pid:      Transceiver link mode (enum pid)
1043  * @sprom:    Transceiver sprom contents
1044  */
1045 struct ionic_xcvr_status {
1046         u8     state;
1047         u8     phy;
1048         __le16 pid;
1049         u8     sprom[256];
1050 };
1051
1052 /**
1053  * Port configuration
1054  * @speed:              port speed (in Mbps)
1055  * @mtu:                mtu
1056  * @state:              port admin state (enum port_admin_state)
1057  * @an_enable:          autoneg enable
1058  * @fec_type:           fec type (enum ionic_port_fec_type)
1059  * @pause_type:         pause type (enum ionic_port_pause_type)
1060  * @loopback_mode:      loopback mode (enum ionic_port_loopback_mode)
1061  */
1062 union ionic_port_config {
1063         struct {
1064 #define IONIC_SPEED_100G        100000  /* 100G in Mbps */
1065 #define IONIC_SPEED_50G         50000   /* 50G in Mbps */
1066 #define IONIC_SPEED_40G         40000   /* 40G in Mbps */
1067 #define IONIC_SPEED_25G         25000   /* 25G in Mbps */
1068 #define IONIC_SPEED_10G         10000   /* 10G in Mbps */
1069 #define IONIC_SPEED_1G          1000    /* 1G in Mbps */
1070                 __le32 speed;
1071                 __le32 mtu;
1072                 u8     state;
1073                 u8     an_enable;
1074                 u8     fec_type;
1075 #define IONIC_PAUSE_TYPE_MASK           0x0f
1076 #define IONIC_PAUSE_FLAGS_MASK          0xf0
1077 #define IONIC_PAUSE_F_TX                0x10
1078 #define IONIC_PAUSE_F_RX                0x20
1079                 u8     pause_type;
1080                 u8     loopback_mode;
1081         };
1082         __le32 words[64];
1083 };
1084
1085 /**
1086  * Port Status information
1087  * @status:             link status (enum ionic_port_oper_status)
1088  * @id:                 port id
1089  * @speed:              link speed (in Mbps)
1090  * @xcvr:               tranceiver status
1091  */
1092 struct ionic_port_status {
1093         __le32 id;
1094         __le32 speed;
1095         u8     status;
1096         u8     rsvd[51];
1097         struct ionic_xcvr_status  xcvr;
1098 };
1099
1100 /**
1101  * struct ionic_port_identify_cmd - Port identify command
1102  * @opcode:     opcode
1103  * @index:      port index
1104  * @ver:        Highest version of identify supported by driver
1105  */
1106 struct ionic_port_identify_cmd {
1107         u8 opcode;
1108         u8 index;
1109         u8 ver;
1110         u8 rsvd[61];
1111 };
1112
1113 /**
1114  * struct ionic_port_identify_comp - Port identify command completion
1115  * @status: The status of the command (enum status_code)
1116  * @ver:    Version of identify returned by device
1117  */
1118 struct ionic_port_identify_comp {
1119         u8 status;
1120         u8 ver;
1121         u8 rsvd[14];
1122 };
1123
1124 /**
1125  * struct ionic_port_init_cmd - Port initialization command
1126  * @opcode:     opcode
1127  * @index:      port index
1128  * @info_pa:    destination address for port info (struct ionic_port_info)
1129  */
1130 struct ionic_port_init_cmd {
1131         u8     opcode;
1132         u8     index;
1133         u8     rsvd[6];
1134         __le64 info_pa;
1135         u8     rsvd2[48];
1136 };
1137
1138 /**
1139  * struct ionic_port_init_comp - Port initialization command completion
1140  * @status: The status of the command (enum status_code)
1141  */
1142 struct ionic_port_init_comp {
1143         u8 status;
1144         u8 rsvd[15];
1145 };
1146
1147 /**
1148  * struct ionic_port_reset_cmd - Port reset command
1149  * @opcode:     opcode
1150  * @index:      port index
1151  */
1152 struct ionic_port_reset_cmd {
1153         u8 opcode;
1154         u8 index;
1155         u8 rsvd[62];
1156 };
1157
1158 /**
1159  * struct ionic_port_reset_comp - Port reset command completion
1160  * @status: The status of the command (enum status_code)
1161  */
1162 struct ionic_port_reset_comp {
1163         u8 status;
1164         u8 rsvd[15];
1165 };
1166
1167 /**
1168  * enum stats_ctl_cmd - List of commands for stats control
1169  */
1170 enum ionic_stats_ctl_cmd {
1171         IONIC_STATS_CTL_RESET           = 0,
1172 };
1173
1174
1175 /**
1176  * enum ionic_port_attr - List of device attributes
1177  */
1178 enum ionic_port_attr {
1179         IONIC_PORT_ATTR_STATE           = 0,
1180         IONIC_PORT_ATTR_SPEED           = 1,
1181         IONIC_PORT_ATTR_MTU             = 2,
1182         IONIC_PORT_ATTR_AUTONEG         = 3,
1183         IONIC_PORT_ATTR_FEC             = 4,
1184         IONIC_PORT_ATTR_PAUSE           = 5,
1185         IONIC_PORT_ATTR_LOOPBACK        = 6,
1186         IONIC_PORT_ATTR_STATS_CTRL      = 7,
1187 };
1188
1189 /**
1190  * struct ionic_port_setattr_cmd - Set port attributes on the NIC
1191  * @opcode:     Opcode
1192  * @index:      port index
1193  * @attr:       Attribute type (enum ionic_port_attr)
1194  */
1195 struct ionic_port_setattr_cmd {
1196         u8     opcode;
1197         u8     index;
1198         u8     attr;
1199         u8     rsvd;
1200         union {
1201                 u8      state;
1202                 __le32  speed;
1203                 __le32  mtu;
1204                 u8      an_enable;
1205                 u8      fec_type;
1206                 u8      pause_type;
1207                 u8      loopback_mode;
1208                 u8      stats_ctl;
1209                 u8      rsvd2[60];
1210         };
1211 };
1212
1213 /**
1214  * struct ionic_port_setattr_comp - Port set attr command completion
1215  * @status:     The status of the command (enum status_code)
1216  * @color:      Color bit
1217  */
1218 struct ionic_port_setattr_comp {
1219         u8     status;
1220         u8     rsvd[14];
1221         u8     color;
1222 };
1223
1224 /**
1225  * struct ionic_port_getattr_cmd - Get port attributes from the NIC
1226  * @opcode:     Opcode
1227  * @index:      port index
1228  * @attr:       Attribute type (enum ionic_port_attr)
1229  */
1230 struct ionic_port_getattr_cmd {
1231         u8     opcode;
1232         u8     index;
1233         u8     attr;
1234         u8     rsvd[61];
1235 };
1236
1237 /**
1238  * struct ionic_port_getattr_comp - Port get attr command completion
1239  * @status:     The status of the command (enum status_code)
1240  * @color:      Color bit
1241  */
1242 struct ionic_port_getattr_comp {
1243         u8     status;
1244         u8     rsvd[3];
1245         union {
1246                 u8      state;
1247                 __le32  speed;
1248                 __le32  mtu;
1249                 u8      an_enable;
1250                 u8      fec_type;
1251                 u8      pause_type;
1252                 u8      loopback_mode;
1253                 u8      rsvd2[11];
1254         };
1255         u8     color;
1256 };
1257
1258 /**
1259  * struct ionic_lif_status - Lif status register
1260  * @eid:             most recent NotifyQ event id
1261  * @port_num:        port the lif is connected to
1262  * @link_status:     port status (enum ionic_port_oper_status)
1263  * @link_speed:      speed of link in Mbps
1264  * @link_down_count: number of times link status changes
1265  */
1266 struct ionic_lif_status {
1267         __le64 eid;
1268         u8     port_num;
1269         u8     rsvd;
1270         __le16 link_status;
1271         __le32 link_speed;              /* units of 1Mbps: eg 10000 = 10Gbps */
1272         __le16 link_down_count;
1273         u8      rsvd2[46];
1274 };
1275
1276 /**
1277  * struct ionic_lif_reset_cmd - LIF reset command
1278  * @opcode:    opcode
1279  * @index:     LIF index
1280  */
1281 struct ionic_lif_reset_cmd {
1282         u8     opcode;
1283         u8     rsvd;
1284         __le16 index;
1285         __le32 rsvd2[15];
1286 };
1287
1288 typedef struct ionic_admin_comp ionic_lif_reset_comp;
1289
1290 enum ionic_dev_state {
1291         IONIC_DEV_DISABLE       = 0,
1292         IONIC_DEV_ENABLE        = 1,
1293         IONIC_DEV_HANG_RESET    = 2,
1294 };
1295
1296 /**
1297  * enum ionic_dev_attr - List of device attributes
1298  */
1299 enum ionic_dev_attr {
1300         IONIC_DEV_ATTR_STATE    = 0,
1301         IONIC_DEV_ATTR_NAME     = 1,
1302         IONIC_DEV_ATTR_FEATURES = 2,
1303 };
1304
1305 /**
1306  * struct ionic_dev_setattr_cmd - Set Device attributes on the NIC
1307  * @opcode:     Opcode
1308  * @attr:       Attribute type (enum ionic_dev_attr)
1309  * @state:      Device state (enum ionic_dev_state)
1310  * @name:       The bus info, e.g. PCI slot-device-function, 0 terminated
1311  * @features:   Device features
1312  */
1313 struct ionic_dev_setattr_cmd {
1314         u8     opcode;
1315         u8     attr;
1316         __le16 rsvd;
1317         union {
1318                 u8      state;
1319                 char    name[IONIC_IFNAMSIZ];
1320                 __le64  features;
1321                 u8      rsvd2[60];
1322         };
1323 };
1324
1325 /**
1326  * struct ionic_dev_setattr_comp - Device set attr command completion
1327  * @status:     The status of the command (enum status_code)
1328  * @features:   Device features
1329  * @color:      Color bit
1330  */
1331 struct ionic_dev_setattr_comp {
1332         u8     status;
1333         u8     rsvd[3];
1334         union {
1335                 __le64  features;
1336                 u8      rsvd2[11];
1337         };
1338         u8     color;
1339 };
1340
1341 /**
1342  * struct ionic_dev_getattr_cmd - Get Device attributes from the NIC
1343  * @opcode:     opcode
1344  * @attr:       Attribute type (enum ionic_dev_attr)
1345  */
1346 struct ionic_dev_getattr_cmd {
1347         u8     opcode;
1348         u8     attr;
1349         u8     rsvd[62];
1350 };
1351
1352 /**
1353  * struct ionic_dev_setattr_comp - Device set attr command completion
1354  * @status:     The status of the command (enum status_code)
1355  * @features:   Device features
1356  * @color:      Color bit
1357  */
1358 struct ionic_dev_getattr_comp {
1359         u8     status;
1360         u8     rsvd[3];
1361         union {
1362                 __le64  features;
1363                 u8      rsvd2[11];
1364         };
1365         u8     color;
1366 };
1367
1368 /**
1369  * RSS parameters
1370  */
1371 #define IONIC_RSS_HASH_KEY_SIZE         40
1372
1373 enum ionic_rss_hash_types {
1374         IONIC_RSS_TYPE_IPV4     = BIT(0),
1375         IONIC_RSS_TYPE_IPV4_TCP = BIT(1),
1376         IONIC_RSS_TYPE_IPV4_UDP = BIT(2),
1377         IONIC_RSS_TYPE_IPV6     = BIT(3),
1378         IONIC_RSS_TYPE_IPV6_TCP = BIT(4),
1379         IONIC_RSS_TYPE_IPV6_UDP = BIT(5),
1380 };
1381
1382 /**
1383  * enum ionic_lif_attr - List of LIF attributes
1384  */
1385 enum ionic_lif_attr {
1386         IONIC_LIF_ATTR_STATE        = 0,
1387         IONIC_LIF_ATTR_NAME         = 1,
1388         IONIC_LIF_ATTR_MTU          = 2,
1389         IONIC_LIF_ATTR_MAC          = 3,
1390         IONIC_LIF_ATTR_FEATURES     = 4,
1391         IONIC_LIF_ATTR_RSS          = 5,
1392         IONIC_LIF_ATTR_STATS_CTRL   = 6,
1393 };
1394
1395 /**
1396  * struct ionic_lif_setattr_cmd - Set LIF attributes on the NIC
1397  * @opcode:     Opcode
1398  * @type:       Attribute type (enum ionic_lif_attr)
1399  * @index:      LIF index
1400  * @state:      lif state (enum lif_state)
1401  * @name:       The netdev name string, 0 terminated
1402  * @mtu:        Mtu
1403  * @mac:        Station mac
1404  * @features:   Features (enum ionic_eth_hw_features)
1405  * @rss:        RSS properties
1406  *              @types:     The hash types to enable (see rss_hash_types).
1407  *              @key:       The hash secret key.
1408  *              @addr:      Address for the indirection table shared memory.
1409  * @stats_ctl:  stats control commands (enum stats_ctl_cmd)
1410  */
1411 struct ionic_lif_setattr_cmd {
1412         u8     opcode;
1413         u8     attr;
1414         __le16 index;
1415         union {
1416                 u8      state;
1417                 char    name[IONIC_IFNAMSIZ];
1418                 __le32  mtu;
1419                 u8      mac[6];
1420                 __le64  features;
1421                 struct {
1422                         __le16 types;
1423                         u8     key[IONIC_RSS_HASH_KEY_SIZE];
1424                         u8     rsvd[6];
1425                         __le64 addr;
1426                 } rss;
1427                 u8      stats_ctl;
1428                 u8      rsvd[60];
1429         };
1430 };
1431
1432 /**
1433  * struct ionic_lif_setattr_comp - LIF set attr command completion
1434  * @status:     The status of the command (enum status_code)
1435  * @comp_index: The index in the descriptor ring for which this
1436  *              is the completion.
1437  * @features:   features (enum ionic_eth_hw_features)
1438  * @color:      Color bit
1439  */
1440 struct ionic_lif_setattr_comp {
1441         u8     status;
1442         u8     rsvd;
1443         __le16 comp_index;
1444         union {
1445                 __le64  features;
1446                 u8      rsvd2[11];
1447         };
1448         u8     color;
1449 };
1450
1451 /**
1452  * struct ionic_lif_getattr_cmd - Get LIF attributes from the NIC
1453  * @opcode:     Opcode
1454  * @attr:       Attribute type (enum ionic_lif_attr)
1455  * @index:      LIF index
1456  */
1457 struct ionic_lif_getattr_cmd {
1458         u8     opcode;
1459         u8     attr;
1460         __le16 index;
1461         u8     rsvd[60];
1462 };
1463
1464 /**
1465  * struct ionic_lif_getattr_comp - LIF get attr command completion
1466  * @status:     The status of the command (enum status_code)
1467  * @comp_index: The index in the descriptor ring for which this
1468  *              is the completion.
1469  * @state:      lif state (enum lif_state)
1470  * @name:       The netdev name string, 0 terminated
1471  * @mtu:        Mtu
1472  * @mac:        Station mac
1473  * @features:   Features (enum ionic_eth_hw_features)
1474  * @color:      Color bit
1475  */
1476 struct ionic_lif_getattr_comp {
1477         u8     status;
1478         u8     rsvd;
1479         __le16 comp_index;
1480         union {
1481                 u8      state;
1482                 __le32  mtu;
1483                 u8      mac[6];
1484                 __le64  features;
1485                 u8      rsvd2[11];
1486         };
1487         u8     color;
1488 };
1489
1490 enum ionic_rx_mode {
1491         IONIC_RX_MODE_F_UNICAST    = BIT(0),
1492         IONIC_RX_MODE_F_MULTICAST  = BIT(1),
1493         IONIC_RX_MODE_F_BROADCAST  = BIT(2),
1494         IONIC_RX_MODE_F_PROMISC    = BIT(3),
1495         IONIC_RX_MODE_F_ALLMULTI   = BIT(4),
1496 };
1497
1498 /**
1499  * struct ionic_rx_mode_set_cmd - Set LIF's Rx mode command
1500  * @opcode:     opcode
1501  * @lif_index:  LIF index
1502  * @rx_mode:    Rx mode flags:
1503  *                  IONIC_RX_MODE_F_UNICAST: Accept known unicast packets.
1504  *                  IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets.
1505  *                  IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets.
1506  *                  IONIC_RX_MODE_F_PROMISC: Accept any packets.
1507  *                  IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets.
1508  */
1509 struct ionic_rx_mode_set_cmd {
1510         u8     opcode;
1511         u8     rsvd;
1512         __le16 lif_index;
1513         __le16 rx_mode;
1514         __le16 rsvd2[29];
1515 };
1516
1517 typedef struct ionic_admin_comp ionic_rx_mode_set_comp;
1518
1519 enum ionic_rx_filter_match_type {
1520         IONIC_RX_FILTER_MATCH_VLAN = 0,
1521         IONIC_RX_FILTER_MATCH_MAC,
1522         IONIC_RX_FILTER_MATCH_MAC_VLAN,
1523 };
1524
1525 /**
1526  * struct ionic_rx_filter_add_cmd - Add LIF Rx filter command
1527  * @opcode:     opcode
1528  * @qtype:      Queue type
1529  * @lif_index:  LIF index
1530  * @qid:        Queue ID
1531  * @match:      Rx filter match type.  (See IONIC_RX_FILTER_MATCH_xxx)
1532  * @vlan:       VLAN ID
1533  * @addr:       MAC address (network-byte order)
1534  */
1535 struct ionic_rx_filter_add_cmd {
1536         u8     opcode;
1537         u8     qtype;
1538         __le16 lif_index;
1539         __le32 qid;
1540         __le16 match;
1541         union {
1542                 struct {
1543                         __le16 vlan;
1544                 } vlan;
1545                 struct {
1546                         u8     addr[6];
1547                 } mac;
1548                 struct {
1549                         __le16 vlan;
1550                         u8     addr[6];
1551                 } mac_vlan;
1552                 u8 rsvd[54];
1553         };
1554 };
1555
1556 /**
1557  * struct ionic_rx_filter_add_comp - Add LIF Rx filter command completion
1558  * @status:     The status of the command (enum status_code)
1559  * @comp_index: The index in the descriptor ring for which this
1560  *              is the completion.
1561  * @filter_id:  Filter ID
1562  * @color:      Color bit.
1563  */
1564 struct ionic_rx_filter_add_comp {
1565         u8     status;
1566         u8     rsvd;
1567         __le16 comp_index;
1568         __le32 filter_id;
1569         u8     rsvd2[7];
1570         u8     color;
1571 };
1572
1573 /**
1574  * struct ionic_rx_filter_del_cmd - Delete LIF Rx filter command
1575  * @opcode:     opcode
1576  * @lif_index:  LIF index
1577  * @filter_id:  Filter ID
1578  */
1579 struct ionic_rx_filter_del_cmd {
1580         u8     opcode;
1581         u8     rsvd;
1582         __le16 lif_index;
1583         __le32 filter_id;
1584         u8     rsvd2[56];
1585 };
1586
1587 typedef struct ionic_admin_comp ionic_rx_filter_del_comp;
1588
1589 /**
1590  * struct ionic_qos_identify_cmd - QoS identify command
1591  * @opcode:    opcode
1592  * @ver:     Highest version of identify supported by driver
1593  *
1594  */
1595 struct ionic_qos_identify_cmd {
1596         u8 opcode;
1597         u8 ver;
1598         u8 rsvd[62];
1599 };
1600
1601 /**
1602  * struct ionic_qos_identify_comp - QoS identify command completion
1603  * @status: The status of the command (enum status_code)
1604  * @ver:    Version of identify returned by device
1605  */
1606 struct ionic_qos_identify_comp {
1607         u8 status;
1608         u8 ver;
1609         u8 rsvd[14];
1610 };
1611
1612 #define IONIC_QOS_CLASS_MAX             7
1613 #define IONIC_QOS_CLASS_NAME_SZ         32
1614 #define IONIC_QOS_DSCP_MAX_VALUES       64
1615
1616 /**
1617  * enum ionic_qos_class
1618  */
1619 enum ionic_qos_class {
1620         IONIC_QOS_CLASS_DEFAULT         = 0,
1621         IONIC_QOS_CLASS_USER_DEFINED_1  = 1,
1622         IONIC_QOS_CLASS_USER_DEFINED_2  = 2,
1623         IONIC_QOS_CLASS_USER_DEFINED_3  = 3,
1624         IONIC_QOS_CLASS_USER_DEFINED_4  = 4,
1625         IONIC_QOS_CLASS_USER_DEFINED_5  = 5,
1626         IONIC_QOS_CLASS_USER_DEFINED_6  = 6,
1627 };
1628
1629 /**
1630  * enum ionic_qos_class_type - Traffic classification criteria
1631  */
1632 enum ionic_qos_class_type {
1633         IONIC_QOS_CLASS_TYPE_NONE       = 0,
1634         IONIC_QOS_CLASS_TYPE_PCP        = 1,    /* Dot1Q pcp */
1635         IONIC_QOS_CLASS_TYPE_DSCP       = 2,    /* IP dscp */
1636 };
1637
1638 /**
1639  * enum ionic_qos_sched_type - Qos class scheduling type
1640  */
1641 enum ionic_qos_sched_type {
1642         IONIC_QOS_SCHED_TYPE_STRICT     = 0,    /* Strict priority */
1643         IONIC_QOS_SCHED_TYPE_DWRR       = 1,    /* Deficit weighted round-robin */
1644 };
1645
1646 enum ionic_vf_attr {
1647         IONIC_VF_ATTR_SPOOFCHK  = 1,
1648         IONIC_VF_ATTR_TRUST     = 2,
1649         IONIC_VF_ATTR_MAC       = 3,
1650         IONIC_VF_ATTR_LINKSTATE = 4,
1651         IONIC_VF_ATTR_VLAN      = 5,
1652         IONIC_VF_ATTR_RATE      = 6,
1653         IONIC_VF_ATTR_STATSADDR = 7,
1654 };
1655
1656 /**
1657  * VF link status
1658  */
1659 enum ionic_vf_link_status {
1660         IONIC_VF_LINK_STATUS_AUTO = 0,  /* link state of the uplink */
1661         IONIC_VF_LINK_STATUS_UP   = 1,  /* link is always up */
1662         IONIC_VF_LINK_STATUS_DOWN = 2,  /* link is always down */
1663 };
1664
1665 /**
1666  * struct ionic_vf_setattr_cmd - Set VF attributes on the NIC
1667  * @opcode:     Opcode
1668  * @index:      VF index
1669  * @attr:       Attribute type (enum ionic_vf_attr)
1670  *      macaddr         mac address
1671  *      vlanid          vlan ID
1672  *      maxrate         max Tx rate in Mbps
1673  *      spoofchk        enable address spoof checking
1674  *      trust           enable VF trust
1675  *      linkstate       set link up or down
1676  *      stats_pa        set DMA address for VF stats
1677  */
1678 struct ionic_vf_setattr_cmd {
1679         u8     opcode;
1680         u8     attr;
1681         __le16 vf_index;
1682         union {
1683                 u8     macaddr[6];
1684                 __le16 vlanid;
1685                 __le32 maxrate;
1686                 u8     spoofchk;
1687                 u8     trust;
1688                 u8     linkstate;
1689                 __le64 stats_pa;
1690                 u8     pad[60];
1691         };
1692 };
1693
1694 struct ionic_vf_setattr_comp {
1695         u8     status;
1696         u8     attr;
1697         __le16 vf_index;
1698         __le16 comp_index;
1699         u8     rsvd[9];
1700         u8     color;
1701 };
1702
1703 /**
1704  * struct ionic_vf_getattr_cmd - Get VF attributes from the NIC
1705  * @opcode:     Opcode
1706  * @index:      VF index
1707  * @attr:       Attribute type (enum ionic_vf_attr)
1708  */
1709 struct ionic_vf_getattr_cmd {
1710         u8     opcode;
1711         u8     attr;
1712         __le16 vf_index;
1713         u8     rsvd[60];
1714 };
1715
1716 struct ionic_vf_getattr_comp {
1717         u8     status;
1718         u8     attr;
1719         __le16 vf_index;
1720         union {
1721                 u8     macaddr[6];
1722                 __le16 vlanid;
1723                 __le32 maxrate;
1724                 u8     spoofchk;
1725                 u8     trust;
1726                 u8     linkstate;
1727                 __le64 stats_pa;
1728                 u8     pad[11];
1729         };
1730         u8     color;
1731 };
1732
1733 /**
1734  * union ionic_qos_config - Qos configuration structure
1735  * @flags:              Configuration flags
1736  *      IONIC_QOS_CONFIG_F_ENABLE               enable
1737  *      IONIC_QOS_CONFIG_F_DROP                 drop/nodrop
1738  *      IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP         enable dot1q pcp rewrite
1739  *      IONIC_QOS_CONFIG_F_RW_IP_DSCP           enable ip dscp rewrite
1740  * @sched_type:         Qos class scheduling type (enum ionic_qos_sched_type)
1741  * @class_type:         Qos class type (enum ionic_qos_class_type)
1742  * @pause_type:         Qos pause type (enum ionic_qos_pause_type)
1743  * @name:               Qos class name
1744  * @mtu:                MTU of the class
1745  * @pfc_dot1q_pcp:      Pcp value for pause frames (valid iff F_NODROP)
1746  * @dwrr_weight:        Qos class scheduling weight
1747  * @strict_rlmt:        Rate limit for strict priority scheduling
1748  * @rw_dot1q_pcp:       Rewrite dot1q pcp to this value (valid iff F_RW_DOT1Q_PCP)
1749  * @rw_ip_dscp:         Rewrite ip dscp to this value   (valid iff F_RW_IP_DSCP)
1750  * @dot1q_pcp:          Dot1q pcp value
1751  * @ndscp:              Number of valid dscp values in the ip_dscp field
1752  * @ip_dscp:            IP dscp values
1753  */
1754 union ionic_qos_config {
1755         struct {
1756 #define IONIC_QOS_CONFIG_F_ENABLE               BIT(0)
1757 #define IONIC_QOS_CONFIG_F_DROP                 BIT(1)
1758 #define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP         BIT(2)
1759 #define IONIC_QOS_CONFIG_F_RW_IP_DSCP           BIT(3)
1760                 u8      flags;
1761                 u8      sched_type;
1762                 u8      class_type;
1763                 u8      pause_type;
1764                 char    name[IONIC_QOS_CLASS_NAME_SZ];
1765                 __le32  mtu;
1766                 /* flow control */
1767                 u8      pfc_cos;
1768                 /* scheduler */
1769                 union {
1770                         u8      dwrr_weight;
1771                         __le64  strict_rlmt;
1772                 };
1773                 /* marking */
1774                 union {
1775                         u8      rw_dot1q_pcp;
1776                         u8      rw_ip_dscp;
1777                 };
1778                 /* classification */
1779                 union {
1780                         u8      dot1q_pcp;
1781                         struct {
1782                                 u8      ndscp;
1783                                 u8      ip_dscp[IONIC_QOS_DSCP_MAX_VALUES];
1784                         };
1785                 };
1786         };
1787         __le32  words[64];
1788 };
1789
1790 /**
1791  * union ionic_qos_identity - QoS identity structure
1792  * @version:    Version of the identify structure
1793  * @type:       QoS system type
1794  * @nclasses:   Number of usable QoS classes
1795  * @config:     Current configuration of classes
1796  */
1797 union ionic_qos_identity {
1798         struct {
1799                 u8     version;
1800                 u8     type;
1801                 u8     rsvd[62];
1802                 union  ionic_qos_config config[IONIC_QOS_CLASS_MAX];
1803         };
1804         __le32 words[512];
1805 };
1806
1807 /**
1808  * struct qos_init_cmd - QoS config init command
1809  * @opcode:     Opcode
1810  * @group:      Qos class id
1811  * @info_pa:    destination address for qos info
1812  */
1813 struct ionic_qos_init_cmd {
1814         u8     opcode;
1815         u8     group;
1816         u8     rsvd[6];
1817         __le64 info_pa;
1818         u8     rsvd1[48];
1819 };
1820
1821 typedef struct ionic_admin_comp ionic_qos_init_comp;
1822
1823 /**
1824  * struct ionic_qos_reset_cmd - Qos config reset command
1825  * @opcode:     Opcode
1826  */
1827 struct ionic_qos_reset_cmd {
1828         u8    opcode;
1829         u8    group;
1830         u8    rsvd[62];
1831 };
1832
1833 typedef struct ionic_admin_comp ionic_qos_reset_comp;
1834
1835 /**
1836  * struct ionic_fw_download_cmd - Firmware download command
1837  * @opcode:     opcode
1838  * @addr:       dma address of the firmware buffer
1839  * @offset:     offset of the firmware buffer within the full image
1840  * @length:     number of valid bytes in the firmware buffer
1841  */
1842 struct ionic_fw_download_cmd {
1843         u8     opcode;
1844         u8     rsvd[3];
1845         __le32 offset;
1846         __le64 addr;
1847         __le32 length;
1848 };
1849
1850 typedef struct ionic_admin_comp ionic_fw_download_comp;
1851
1852 enum ionic_fw_control_oper {
1853         IONIC_FW_RESET          = 0,    /* Reset firmware */
1854         IONIC_FW_INSTALL        = 1,    /* Install firmware */
1855         IONIC_FW_ACTIVATE       = 2,    /* Activate firmware */
1856 };
1857
1858 /**
1859  * struct ionic_fw_control_cmd - Firmware control command
1860  * @opcode:    opcode
1861  * @oper:      firmware control operation (enum ionic_fw_control_oper)
1862  * @slot:      slot to activate
1863  */
1864 struct ionic_fw_control_cmd {
1865         u8  opcode;
1866         u8  rsvd[3];
1867         u8  oper;
1868         u8  slot;
1869         u8  rsvd1[58];
1870 };
1871
1872 /**
1873  * struct ionic_fw_control_comp - Firmware control copletion
1874  * @opcode:    opcode
1875  * @slot:      slot where the firmware was installed
1876  */
1877 struct ionic_fw_control_comp {
1878         u8     status;
1879         u8     rsvd;
1880         __le16 comp_index;
1881         u8     slot;
1882         u8     rsvd1[10];
1883         u8     color;
1884 };
1885
1886 /******************************************************************
1887  ******************* RDMA Commands ********************************
1888  ******************************************************************/
1889
1890 /**
1891  * struct ionic_rdma_reset_cmd - Reset RDMA LIF cmd
1892  * @opcode:        opcode
1893  * @lif_index:     lif index
1894  *
1895  * There is no rdma specific dev command completion struct.  Completion uses
1896  * the common struct ionic_admin_comp.  Only the status is indicated.
1897  * Nonzero status means the LIF does not support rdma.
1898  **/
1899 struct ionic_rdma_reset_cmd {
1900         u8     opcode;
1901         u8     rsvd;
1902         __le16 lif_index;
1903         u8     rsvd2[60];
1904 };
1905
1906 /**
1907  * struct ionic_rdma_queue_cmd - Create RDMA Queue command
1908  * @opcode:        opcode, 52, 53
1909  * @lif_index      lif index
1910  * @qid_ver:       (qid | (rdma version << 24))
1911  * @cid:           intr, eq_id, or cq_id
1912  * @dbid:          doorbell page id
1913  * @depth_log2:    log base two of queue depth
1914  * @stride_log2:   log base two of queue stride
1915  * @dma_addr:      address of the queue memory
1916  * @xxx_table_index: temporary, but should not need pgtbl for contig. queues.
1917  *
1918  * The same command struct is used to create an rdma event queue, completion
1919  * queue, or rdma admin queue.  The cid is an interrupt number for an event
1920  * queue, an event queue id for a completion queue, or a completion queue id
1921  * for an rdma admin queue.
1922  *
1923  * The queue created via a dev command must be contiguous in dma space.
1924  *
1925  * The dev commands are intended only to be used during driver initialization,
1926  * to create queues supporting the rdma admin queue.  Other queues, and other
1927  * types of rdma resources like memory regions, will be created and registered
1928  * via the rdma admin queue, and will support a more complete interface
1929  * providing scatter gather lists for larger, scattered queue buffers and
1930  * memory registration.
1931  *
1932  * There is no rdma specific dev command completion struct.  Completion uses
1933  * the common struct ionic_admin_comp.  Only the status is indicated.
1934  **/
1935 struct ionic_rdma_queue_cmd {
1936         u8     opcode;
1937         u8     rsvd;
1938         __le16 lif_index;
1939         __le32 qid_ver;
1940         __le32 cid;
1941         __le16 dbid;
1942         u8     depth_log2;
1943         u8     stride_log2;
1944         __le64 dma_addr;
1945         u8     rsvd2[36];
1946         __le32 xxx_table_index;
1947 };
1948
1949 /******************************************************************
1950  ******************* Notify Events ********************************
1951  ******************************************************************/
1952
1953 /**
1954  * struct ionic_notifyq_event
1955  * @eid:   event number
1956  * @ecode: event code
1957  * @data:  unspecified data about the event
1958  *
1959  * This is the generic event report struct from which the other
1960  * actual events will be formed.
1961  */
1962 struct ionic_notifyq_event {
1963         __le64 eid;
1964         __le16 ecode;
1965         u8     data[54];
1966 };
1967
1968 /**
1969  * struct ionic_link_change_event
1970  * @eid:                event number
1971  * @ecode:              event code = EVENT_OPCODE_LINK_CHANGE
1972  * @link_status:        link up or down, with error bits (enum port_status)
1973  * @link_speed:         speed of the network link
1974  *
1975  * Sent when the network link state changes between UP and DOWN
1976  */
1977 struct ionic_link_change_event {
1978         __le64 eid;
1979         __le16 ecode;
1980         __le16 link_status;
1981         __le32 link_speed;      /* units of 1Mbps: e.g. 10000 = 10Gbps */
1982         u8     rsvd[48];
1983 };
1984
1985 /**
1986  * struct ionic_reset_event
1987  * @eid:                event number
1988  * @ecode:              event code = EVENT_OPCODE_RESET
1989  * @reset_code:         reset type
1990  * @state:              0=pending, 1=complete, 2=error
1991  *
1992  * Sent when the NIC or some subsystem is going to be or
1993  * has been reset.
1994  */
1995 struct ionic_reset_event {
1996         __le64 eid;
1997         __le16 ecode;
1998         u8     reset_code;
1999         u8     state;
2000         u8     rsvd[52];
2001 };
2002
2003 /**
2004  * struct ionic_heartbeat_event
2005  * @eid:        event number
2006  * @ecode:      event code = EVENT_OPCODE_HEARTBEAT
2007  *
2008  * Sent periodically by the NIC to indicate continued health
2009  */
2010 struct ionic_heartbeat_event {
2011         __le64 eid;
2012         __le16 ecode;
2013         u8     rsvd[54];
2014 };
2015
2016 /**
2017  * struct ionic_log_event
2018  * @eid:        event number
2019  * @ecode:      event code = EVENT_OPCODE_LOG
2020  * @data:       log data
2021  *
2022  * Sent to notify the driver of an internal error.
2023  */
2024 struct ionic_log_event {
2025         __le64 eid;
2026         __le16 ecode;
2027         u8     data[54];
2028 };
2029
2030 /**
2031  * struct ionic_port_stats
2032  */
2033 struct ionic_port_stats {
2034         __le64 frames_rx_ok;
2035         __le64 frames_rx_all;
2036         __le64 frames_rx_bad_fcs;
2037         __le64 frames_rx_bad_all;
2038         __le64 octets_rx_ok;
2039         __le64 octets_rx_all;
2040         __le64 frames_rx_unicast;
2041         __le64 frames_rx_multicast;
2042         __le64 frames_rx_broadcast;
2043         __le64 frames_rx_pause;
2044         __le64 frames_rx_bad_length;
2045         __le64 frames_rx_undersized;
2046         __le64 frames_rx_oversized;
2047         __le64 frames_rx_fragments;
2048         __le64 frames_rx_jabber;
2049         __le64 frames_rx_pripause;
2050         __le64 frames_rx_stomped_crc;
2051         __le64 frames_rx_too_long;
2052         __le64 frames_rx_vlan_good;
2053         __le64 frames_rx_dropped;
2054         __le64 frames_rx_less_than_64b;
2055         __le64 frames_rx_64b;
2056         __le64 frames_rx_65b_127b;
2057         __le64 frames_rx_128b_255b;
2058         __le64 frames_rx_256b_511b;
2059         __le64 frames_rx_512b_1023b;
2060         __le64 frames_rx_1024b_1518b;
2061         __le64 frames_rx_1519b_2047b;
2062         __le64 frames_rx_2048b_4095b;
2063         __le64 frames_rx_4096b_8191b;
2064         __le64 frames_rx_8192b_9215b;
2065         __le64 frames_rx_other;
2066         __le64 frames_tx_ok;
2067         __le64 frames_tx_all;
2068         __le64 frames_tx_bad;
2069         __le64 octets_tx_ok;
2070         __le64 octets_tx_total;
2071         __le64 frames_tx_unicast;
2072         __le64 frames_tx_multicast;
2073         __le64 frames_tx_broadcast;
2074         __le64 frames_tx_pause;
2075         __le64 frames_tx_pripause;
2076         __le64 frames_tx_vlan;
2077         __le64 frames_tx_less_than_64b;
2078         __le64 frames_tx_64b;
2079         __le64 frames_tx_65b_127b;
2080         __le64 frames_tx_128b_255b;
2081         __le64 frames_tx_256b_511b;
2082         __le64 frames_tx_512b_1023b;
2083         __le64 frames_tx_1024b_1518b;
2084         __le64 frames_tx_1519b_2047b;
2085         __le64 frames_tx_2048b_4095b;
2086         __le64 frames_tx_4096b_8191b;
2087         __le64 frames_tx_8192b_9215b;
2088         __le64 frames_tx_other;
2089         __le64 frames_tx_pri_0;
2090         __le64 frames_tx_pri_1;
2091         __le64 frames_tx_pri_2;
2092         __le64 frames_tx_pri_3;
2093         __le64 frames_tx_pri_4;
2094         __le64 frames_tx_pri_5;
2095         __le64 frames_tx_pri_6;
2096         __le64 frames_tx_pri_7;
2097         __le64 frames_rx_pri_0;
2098         __le64 frames_rx_pri_1;
2099         __le64 frames_rx_pri_2;
2100         __le64 frames_rx_pri_3;
2101         __le64 frames_rx_pri_4;
2102         __le64 frames_rx_pri_5;
2103         __le64 frames_rx_pri_6;
2104         __le64 frames_rx_pri_7;
2105         __le64 tx_pripause_0_1us_count;
2106         __le64 tx_pripause_1_1us_count;
2107         __le64 tx_pripause_2_1us_count;
2108         __le64 tx_pripause_3_1us_count;
2109         __le64 tx_pripause_4_1us_count;
2110         __le64 tx_pripause_5_1us_count;
2111         __le64 tx_pripause_6_1us_count;
2112         __le64 tx_pripause_7_1us_count;
2113         __le64 rx_pripause_0_1us_count;
2114         __le64 rx_pripause_1_1us_count;
2115         __le64 rx_pripause_2_1us_count;
2116         __le64 rx_pripause_3_1us_count;
2117         __le64 rx_pripause_4_1us_count;
2118         __le64 rx_pripause_5_1us_count;
2119         __le64 rx_pripause_6_1us_count;
2120         __le64 rx_pripause_7_1us_count;
2121         __le64 rx_pause_1us_count;
2122         __le64 frames_tx_truncated;
2123 };
2124
2125 struct ionic_mgmt_port_stats {
2126         __le64 frames_rx_ok;
2127         __le64 frames_rx_all;
2128         __le64 frames_rx_bad_fcs;
2129         __le64 frames_rx_bad_all;
2130         __le64 octets_rx_ok;
2131         __le64 octets_rx_all;
2132         __le64 frames_rx_unicast;
2133         __le64 frames_rx_multicast;
2134         __le64 frames_rx_broadcast;
2135         __le64 frames_rx_pause;
2136         __le64 frames_rx_bad_length0;
2137         __le64 frames_rx_undersized1;
2138         __le64 frames_rx_oversized2;
2139         __le64 frames_rx_fragments3;
2140         __le64 frames_rx_jabber4;
2141         __le64 frames_rx_64b5;
2142         __le64 frames_rx_65b_127b6;
2143         __le64 frames_rx_128b_255b7;
2144         __le64 frames_rx_256b_511b8;
2145         __le64 frames_rx_512b_1023b9;
2146         __le64 frames_rx_1024b_1518b0;
2147         __le64 frames_rx_gt_1518b1;
2148         __le64 frames_rx_fifo_full2;
2149         __le64 frames_tx_ok3;
2150         __le64 frames_tx_all4;
2151         __le64 frames_tx_bad5;
2152         __le64 octets_tx_ok6;
2153         __le64 octets_tx_total7;
2154         __le64 frames_tx_unicast8;
2155         __le64 frames_tx_multicast9;
2156         __le64 frames_tx_broadcast0;
2157         __le64 frames_tx_pause1;
2158 };
2159
2160 /**
2161  * struct ionic_port_identity - port identity structure
2162  * @version:        identity structure version
2163  * @type:           type of port (enum port_type)
2164  * @num_lanes:      number of lanes for the port
2165  * @autoneg:        autoneg supported
2166  * @min_frame_size: minimum frame size supported
2167  * @max_frame_size: maximum frame size supported
2168  * @fec_type:       supported fec types
2169  * @pause_type:     supported pause types
2170  * @loopback_mode:  supported loopback mode
2171  * @speeds:         supported speeds
2172  * @config:         current port configuration
2173  */
2174 union ionic_port_identity {
2175         struct {
2176                 u8     version;
2177                 u8     type;
2178                 u8     num_lanes;
2179                 u8     autoneg;
2180                 __le32 min_frame_size;
2181                 __le32 max_frame_size;
2182                 u8     fec_type[4];
2183                 u8     pause_type[2];
2184                 u8     loopback_mode[2];
2185                 __le32 speeds[16];
2186                 u8     rsvd2[44];
2187                 union ionic_port_config config;
2188         };
2189         __le32 words[512];
2190 };
2191
2192 /**
2193  * struct ionic_port_info - port info structure
2194  * @port_status:     port status
2195  * @port_stats:      port stats
2196  */
2197 struct ionic_port_info {
2198         union ionic_port_config config;
2199         struct ionic_port_status status;
2200         struct ionic_port_stats stats;
2201 };
2202
2203 /**
2204  * struct ionic_lif_stats
2205  */
2206 struct ionic_lif_stats {
2207         /* RX */
2208         __le64 rx_ucast_bytes;
2209         __le64 rx_ucast_packets;
2210         __le64 rx_mcast_bytes;
2211         __le64 rx_mcast_packets;
2212         __le64 rx_bcast_bytes;
2213         __le64 rx_bcast_packets;
2214         __le64 rsvd0;
2215         __le64 rsvd1;
2216         /* RX drops */
2217         __le64 rx_ucast_drop_bytes;
2218         __le64 rx_ucast_drop_packets;
2219         __le64 rx_mcast_drop_bytes;
2220         __le64 rx_mcast_drop_packets;
2221         __le64 rx_bcast_drop_bytes;
2222         __le64 rx_bcast_drop_packets;
2223         __le64 rx_dma_error;
2224         __le64 rsvd2;
2225         /* TX */
2226         __le64 tx_ucast_bytes;
2227         __le64 tx_ucast_packets;
2228         __le64 tx_mcast_bytes;
2229         __le64 tx_mcast_packets;
2230         __le64 tx_bcast_bytes;
2231         __le64 tx_bcast_packets;
2232         __le64 rsvd3;
2233         __le64 rsvd4;
2234         /* TX drops */
2235         __le64 tx_ucast_drop_bytes;
2236         __le64 tx_ucast_drop_packets;
2237         __le64 tx_mcast_drop_bytes;
2238         __le64 tx_mcast_drop_packets;
2239         __le64 tx_bcast_drop_bytes;
2240         __le64 tx_bcast_drop_packets;
2241         __le64 tx_dma_error;
2242         __le64 rsvd5;
2243         /* Rx Queue/Ring drops */
2244         __le64 rx_queue_disabled;
2245         __le64 rx_queue_empty;
2246         __le64 rx_queue_error;
2247         __le64 rx_desc_fetch_error;
2248         __le64 rx_desc_data_error;
2249         __le64 rsvd6;
2250         __le64 rsvd7;
2251         __le64 rsvd8;
2252         /* Tx Queue/Ring drops */
2253         __le64 tx_queue_disabled;
2254         __le64 tx_queue_error;
2255         __le64 tx_desc_fetch_error;
2256         __le64 tx_desc_data_error;
2257         __le64 rsvd9;
2258         __le64 rsvd10;
2259         __le64 rsvd11;
2260         __le64 rsvd12;
2261
2262         /* RDMA/ROCE TX */
2263         __le64 tx_rdma_ucast_bytes;
2264         __le64 tx_rdma_ucast_packets;
2265         __le64 tx_rdma_mcast_bytes;
2266         __le64 tx_rdma_mcast_packets;
2267         __le64 tx_rdma_cnp_packets;
2268         __le64 rsvd13;
2269         __le64 rsvd14;
2270         __le64 rsvd15;
2271
2272         /* RDMA/ROCE RX */
2273         __le64 rx_rdma_ucast_bytes;
2274         __le64 rx_rdma_ucast_packets;
2275         __le64 rx_rdma_mcast_bytes;
2276         __le64 rx_rdma_mcast_packets;
2277         __le64 rx_rdma_cnp_packets;
2278         __le64 rx_rdma_ecn_packets;
2279         __le64 rsvd16;
2280         __le64 rsvd17;
2281
2282         __le64 rsvd18;
2283         __le64 rsvd19;
2284         __le64 rsvd20;
2285         __le64 rsvd21;
2286         __le64 rsvd22;
2287         __le64 rsvd23;
2288         __le64 rsvd24;
2289         __le64 rsvd25;
2290
2291         __le64 rsvd26;
2292         __le64 rsvd27;
2293         __le64 rsvd28;
2294         __le64 rsvd29;
2295         __le64 rsvd30;
2296         __le64 rsvd31;
2297         __le64 rsvd32;
2298         __le64 rsvd33;
2299
2300         __le64 rsvd34;
2301         __le64 rsvd35;
2302         __le64 rsvd36;
2303         __le64 rsvd37;
2304         __le64 rsvd38;
2305         __le64 rsvd39;
2306         __le64 rsvd40;
2307         __le64 rsvd41;
2308
2309         __le64 rsvd42;
2310         __le64 rsvd43;
2311         __le64 rsvd44;
2312         __le64 rsvd45;
2313         __le64 rsvd46;
2314         __le64 rsvd47;
2315         __le64 rsvd48;
2316         __le64 rsvd49;
2317
2318         /* RDMA/ROCE REQ Error/Debugs (768 - 895) */
2319         __le64 rdma_req_rx_pkt_seq_err;
2320         __le64 rdma_req_rx_rnr_retry_err;
2321         __le64 rdma_req_rx_remote_access_err;
2322         __le64 rdma_req_rx_remote_inv_req_err;
2323         __le64 rdma_req_rx_remote_oper_err;
2324         __le64 rdma_req_rx_implied_nak_seq_err;
2325         __le64 rdma_req_rx_cqe_err;
2326         __le64 rdma_req_rx_cqe_flush_err;
2327
2328         __le64 rdma_req_rx_dup_responses;
2329         __le64 rdma_req_rx_invalid_packets;
2330         __le64 rdma_req_tx_local_access_err;
2331         __le64 rdma_req_tx_local_oper_err;
2332         __le64 rdma_req_tx_memory_mgmt_err;
2333         __le64 rsvd52;
2334         __le64 rsvd53;
2335         __le64 rsvd54;
2336
2337         /* RDMA/ROCE RESP Error/Debugs (896 - 1023) */
2338         __le64 rdma_resp_rx_dup_requests;
2339         __le64 rdma_resp_rx_out_of_buffer;
2340         __le64 rdma_resp_rx_out_of_seq_pkts;
2341         __le64 rdma_resp_rx_cqe_err;
2342         __le64 rdma_resp_rx_cqe_flush_err;
2343         __le64 rdma_resp_rx_local_len_err;
2344         __le64 rdma_resp_rx_inv_request_err;
2345         __le64 rdma_resp_rx_local_qp_oper_err;
2346
2347         __le64 rdma_resp_rx_out_of_atomic_resource;
2348         __le64 rdma_resp_tx_pkt_seq_err;
2349         __le64 rdma_resp_tx_remote_inv_req_err;
2350         __le64 rdma_resp_tx_remote_access_err;
2351         __le64 rdma_resp_tx_remote_oper_err;
2352         __le64 rdma_resp_tx_rnr_retry_err;
2353         __le64 rsvd57;
2354         __le64 rsvd58;
2355 };
2356
2357 /**
2358  * struct ionic_lif_info - lif info structure
2359  */
2360 struct ionic_lif_info {
2361         union ionic_lif_config config;
2362         struct ionic_lif_status status;
2363         struct ionic_lif_stats stats;
2364 };
2365
2366 union ionic_dev_cmd {
2367         u32 words[16];
2368         struct ionic_admin_cmd cmd;
2369         struct ionic_nop_cmd nop;
2370
2371         struct ionic_dev_identify_cmd identify;
2372         struct ionic_dev_init_cmd init;
2373         struct ionic_dev_reset_cmd reset;
2374         struct ionic_dev_getattr_cmd getattr;
2375         struct ionic_dev_setattr_cmd setattr;
2376
2377         struct ionic_port_identify_cmd port_identify;
2378         struct ionic_port_init_cmd port_init;
2379         struct ionic_port_reset_cmd port_reset;
2380         struct ionic_port_getattr_cmd port_getattr;
2381         struct ionic_port_setattr_cmd port_setattr;
2382
2383         struct ionic_vf_setattr_cmd vf_setattr;
2384         struct ionic_vf_getattr_cmd vf_getattr;
2385
2386         struct ionic_lif_identify_cmd lif_identify;
2387         struct ionic_lif_init_cmd lif_init;
2388         struct ionic_lif_reset_cmd lif_reset;
2389
2390         struct ionic_qos_identify_cmd qos_identify;
2391         struct ionic_qos_init_cmd qos_init;
2392         struct ionic_qos_reset_cmd qos_reset;
2393
2394         struct ionic_q_init_cmd q_init;
2395 };
2396
2397 union ionic_dev_cmd_comp {
2398         u32 words[4];
2399         u8 status;
2400         struct ionic_admin_comp comp;
2401         struct ionic_nop_comp nop;
2402
2403         struct ionic_dev_identify_comp identify;
2404         struct ionic_dev_init_comp init;
2405         struct ionic_dev_reset_comp reset;
2406         struct ionic_dev_getattr_comp getattr;
2407         struct ionic_dev_setattr_comp setattr;
2408
2409         struct ionic_port_identify_comp port_identify;
2410         struct ionic_port_init_comp port_init;
2411         struct ionic_port_reset_comp port_reset;
2412         struct ionic_port_getattr_comp port_getattr;
2413         struct ionic_port_setattr_comp port_setattr;
2414
2415         struct ionic_vf_setattr_comp vf_setattr;
2416         struct ionic_vf_getattr_comp vf_getattr;
2417
2418         struct ionic_lif_identify_comp lif_identify;
2419         struct ionic_lif_init_comp lif_init;
2420         ionic_lif_reset_comp lif_reset;
2421
2422         struct ionic_qos_identify_comp qos_identify;
2423         ionic_qos_init_comp qos_init;
2424         ionic_qos_reset_comp qos_reset;
2425
2426         struct ionic_q_init_comp q_init;
2427 };
2428
2429 /**
2430  * union dev_info - Device info register format (read-only)
2431  * @signature:       Signature value of 0x44455649 ('DEVI').
2432  * @version:         Current version of info.
2433  * @asic_type:       Asic type.
2434  * @asic_rev:        Asic revision.
2435  * @fw_status:       Firmware status.
2436  * @fw_heartbeat:    Firmware heartbeat counter.
2437  * @serial_num:      Serial number.
2438  * @fw_version:      Firmware version.
2439  */
2440 union ionic_dev_info_regs {
2441 #define IONIC_DEVINFO_FWVERS_BUFLEN 32
2442 #define IONIC_DEVINFO_SERIAL_BUFLEN 32
2443         struct {
2444                 u32    signature;
2445                 u8     version;
2446                 u8     asic_type;
2447                 u8     asic_rev;
2448 #define IONIC_FW_STS_F_RUNNING  0x1
2449                 u8     fw_status;
2450                 u32    fw_heartbeat;
2451                 char   fw_version[IONIC_DEVINFO_FWVERS_BUFLEN];
2452                 char   serial_num[IONIC_DEVINFO_SERIAL_BUFLEN];
2453         };
2454         u32 words[512];
2455 };
2456
2457 /**
2458  * union ionic_dev_cmd_regs - Device command register format (read-write)
2459  * @doorbell:        Device Cmd Doorbell, write-only.
2460  *                   Write a 1 to signal device to process cmd,
2461  *                   poll done for completion.
2462  * @done:            Done indicator, bit 0 == 1 when command is complete.
2463  * @cmd:             Opcode-specific command bytes
2464  * @comp:            Opcode-specific response bytes
2465  * @data:            Opcode-specific side-data
2466  */
2467 union ionic_dev_cmd_regs {
2468         struct {
2469                 u32                   doorbell;
2470                 u32                   done;
2471                 union ionic_dev_cmd         cmd;
2472                 union ionic_dev_cmd_comp    comp;
2473                 u8                    rsvd[48];
2474                 u32                   data[478];
2475         };
2476         u32 words[512];
2477 };
2478
2479 /**
2480  * union ionic_dev_regs - Device register format in for bar 0 page 0
2481  * @info:            Device info registers
2482  * @devcmd:          Device command registers
2483  */
2484 union ionic_dev_regs {
2485         struct {
2486                 union ionic_dev_info_regs info;
2487                 union ionic_dev_cmd_regs  devcmd;
2488         };
2489         __le32 words[1024];
2490 };
2491
2492 union ionic_adminq_cmd {
2493         struct ionic_admin_cmd cmd;
2494         struct ionic_nop_cmd nop;
2495         struct ionic_q_init_cmd q_init;
2496         struct ionic_q_control_cmd q_control;
2497         struct ionic_lif_setattr_cmd lif_setattr;
2498         struct ionic_lif_getattr_cmd lif_getattr;
2499         struct ionic_rx_mode_set_cmd rx_mode_set;
2500         struct ionic_rx_filter_add_cmd rx_filter_add;
2501         struct ionic_rx_filter_del_cmd rx_filter_del;
2502         struct ionic_rdma_reset_cmd rdma_reset;
2503         struct ionic_rdma_queue_cmd rdma_queue;
2504         struct ionic_fw_download_cmd fw_download;
2505         struct ionic_fw_control_cmd fw_control;
2506 };
2507
2508 union ionic_adminq_comp {
2509         struct ionic_admin_comp comp;
2510         struct ionic_nop_comp nop;
2511         struct ionic_q_init_comp q_init;
2512         struct ionic_lif_setattr_comp lif_setattr;
2513         struct ionic_lif_getattr_comp lif_getattr;
2514         struct ionic_rx_filter_add_comp rx_filter_add;
2515         struct ionic_fw_control_comp fw_control;
2516 };
2517
2518 #define IONIC_BARS_MAX                  6
2519 #define IONIC_PCI_BAR_DBELL             1
2520
2521 /* BAR0 */
2522 #define IONIC_BAR0_SIZE                         0x8000
2523
2524 #define IONIC_BAR0_DEV_INFO_REGS_OFFSET         0x0000
2525 #define IONIC_BAR0_DEV_CMD_REGS_OFFSET          0x0800
2526 #define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET     0x0c00
2527 #define IONIC_BAR0_INTR_STATUS_OFFSET           0x1000
2528 #define IONIC_BAR0_INTR_CTRL_OFFSET             0x2000
2529 #define IONIC_DEV_CMD_DONE                      0x00000001
2530
2531 #define IONIC_ASIC_TYPE_CAPRI                   0
2532
2533 /**
2534  * struct ionic_doorbell - Doorbell register layout
2535  * @p_index: Producer index
2536  * @ring:    Selects the specific ring of the queue to update.
2537  *           Type-specific meaning:
2538  *              ring=0: Default producer/consumer queue.
2539  *              ring=1: (CQ, EQ) Re-Arm queue.  RDMA CQs
2540  *              send events to EQs when armed.  EQs send
2541  *              interrupts when armed.
2542  * @qid:     The queue id selects the queue destination for the
2543  *           producer index and flags.
2544  */
2545 struct ionic_doorbell {
2546         __le16 p_index;
2547         u8     ring;
2548         u8     qid_lo;
2549         __le16 qid_hi;
2550         u16    rsvd2;
2551 };
2552
2553 struct ionic_intr_status {
2554         u32 status[2];
2555 };
2556
2557 struct ionic_notifyq_cmd {
2558         __le32 data;    /* Not used but needed for qcq structure */
2559 };
2560
2561 union ionic_notifyq_comp {
2562         struct ionic_notifyq_event event;
2563         struct ionic_link_change_event link_change;
2564         struct ionic_reset_event reset;
2565         struct ionic_heartbeat_event heartbeat;
2566         struct ionic_log_event log;
2567 };
2568
2569 /* Deprecate */
2570 struct ionic_identity {
2571         union ionic_drv_identity drv;
2572         union ionic_dev_identity dev;
2573         union ionic_lif_identity lif;
2574         union ionic_port_identity port;
2575         union ionic_qos_identity qos;
2576 };
2577
2578 #pragma pack(pop)
2579
2580 #endif /* _IONIC_IF_H_ */