drivers/net/ethernet/qlogic/qed/qed.h

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef _QED_H
  34 #define _QED_H
  35
  36 #include <linux/types.h>
  37 #include <linux/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/firmware.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/list.h>
  42 #include <linux/mutex.h>
  43 #include <linux/pci.h>
  44 #include <linux/slab.h>
  45 #include <linux/string.h>
  46 #include <linux/workqueue.h>
  47 #include <linux/zlib.h>
  48 #include <linux/hashtable.h>
  49 #include <linux/qed/qed_if.h>
  50 #include "qed_debug.h"
  51 #include "qed_hsi.h"
  52
  53 extern const struct qed_common_ops qed_common_ops_pass;
  54
  55 #define QED_MAJOR_VERSION               8
  56 #define QED_MINOR_VERSION               33
  57 #define QED_REVISION_VERSION            0
  58 #define QED_ENGINEERING_VERSION         20
  59
  60 #define QED_VERSION                                              \
  61         ((QED_MAJOR_VERSION << 24) | (QED_MINOR_VERSION << 16) | \
  62          (QED_REVISION_VERSION << 8) | QED_ENGINEERING_VERSION)
  63
  64 #define STORM_FW_VERSION                                       \
  65         ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \
  66          (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
  67
  68 #define MAX_HWFNS_PER_DEVICE    (4)
  69 #define NAME_SIZE 16
  70 #define VER_SIZE 16
  71
  72 #define QED_WFQ_UNIT    100
  73
  74 #define QED_WID_SIZE            (1024)
  75 #define QED_MIN_WIDS            (4)
  76 #define QED_PF_DEMS_SIZE        (4)
  77
  78 /* cau states */
  79 enum qed_coalescing_mode {
  80         QED_COAL_MODE_DISABLE,
  81         QED_COAL_MODE_ENABLE
  82 };
  83
  84 enum qed_nvm_cmd {
  85         QED_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
  86         QED_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
  87         QED_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
  88         QED_GET_MCP_NVM_RESP = 0xFFFFFF00
  89 };
  90
  91 struct qed_eth_cb_ops;
  92 struct qed_dev_info;
  93 union qed_mcp_protocol_stats;
  94 enum qed_mcp_protocol_type;
  95
  96 /* helpers */
  97 #define QED_MFW_GET_FIELD(name, field) \
  98         (((name) & (field ## _MASK)) >> (field ## _SHIFT))
  99
 100 #define QED_MFW_SET_FIELD(name, field, value)                                  \
 101         do {                                                                   \
 102                 (name)  &= ~(field ## _MASK);          \
 103                 (name)  |= (((value) << (field ## _SHIFT)) & (field ## _MASK));\
 104         } while (0)
 105
 106 static inline u32 qed_db_addr(u32 cid, u32 DEMS)
 107 {
 108         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 109                       (cid * QED_PF_DEMS_SIZE);
 110
 111         return db_addr;
 112 }
 113
 114 static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS)
 115 {
 116         u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
 117                       FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
 118
 119         return db_addr;
 120 }
 121
 122 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn)                                 \
 123         ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
 124          ~((1 << (p_hwfn->cdev->cache_shift)) - 1))
 125
 126 #define for_each_hwfn(cdev, i)  for (i = 0; i < cdev->num_hwfns; i++)
 127
 128 #define D_TRINE(val, cond1, cond2, true1, true2, def) \
 129         (val == (cond1) ? true1 :                     \
 130          (val == (cond2) ? true2 : def))
 131
 132 /* forward */
 133 struct qed_ptt_pool;
 134 struct qed_spq;
 135 struct qed_sb_info;
 136 struct qed_sb_attn_info;
 137 struct qed_cxt_mngr;
 138 struct qed_sb_sp_info;
 139 struct qed_ll2_info;
 140 struct qed_mcp_info;
 141
 142 struct qed_rt_data {
 143         u32     *init_val;
 144         bool    *b_valid;
 145 };
 146
 147 enum qed_tunn_mode {
 148         QED_MODE_L2GENEVE_TUNN,
 149         QED_MODE_IPGENEVE_TUNN,
 150         QED_MODE_L2GRE_TUNN,
 151         QED_MODE_IPGRE_TUNN,
 152         QED_MODE_VXLAN_TUNN,
 153 };
 154
 155 enum qed_tunn_clss {
 156         QED_TUNN_CLSS_MAC_VLAN,
 157         QED_TUNN_CLSS_MAC_VNI,
 158         QED_TUNN_CLSS_INNER_MAC_VLAN,
 159         QED_TUNN_CLSS_INNER_MAC_VNI,
 160         QED_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
 161         MAX_QED_TUNN_CLSS,
 162 };
 163
 164 struct qed_tunn_update_type {
 165         bool b_update_mode;
 166         bool b_mode_enabled;
 167         enum qed_tunn_clss tun_cls;
 168 };
 169
 170 struct qed_tunn_update_udp_port {
 171         bool b_update_port;
 172         u16 port;
 173 };
 174
 175 struct qed_tunnel_info {
 176         struct qed_tunn_update_type vxlan;
 177         struct qed_tunn_update_type l2_geneve;
 178         struct qed_tunn_update_type ip_geneve;
 179         struct qed_tunn_update_type l2_gre;
 180         struct qed_tunn_update_type ip_gre;
 181
 182         struct qed_tunn_update_udp_port vxlan_port;
 183         struct qed_tunn_update_udp_port geneve_port;
 184
 185         bool b_update_rx_cls;
 186         bool b_update_tx_cls;
 187 };
 188
 189 struct qed_tunn_start_params {
 190         unsigned long   tunn_mode;
 191         u16             vxlan_udp_port;
 192         u16             geneve_udp_port;
 193         u8              update_vxlan_udp_port;
 194         u8              update_geneve_udp_port;
 195         u8              tunn_clss_vxlan;
 196         u8              tunn_clss_l2geneve;
 197         u8              tunn_clss_ipgeneve;
 198         u8              tunn_clss_l2gre;
 199         u8              tunn_clss_ipgre;
 200 };
 201
 202 struct qed_tunn_update_params {
 203         unsigned long   tunn_mode_update_mask;
 204         unsigned long   tunn_mode;
 205         u16             vxlan_udp_port;
 206         u16             geneve_udp_port;
 207         u8              update_rx_pf_clss;
 208         u8              update_tx_pf_clss;
 209         u8              update_vxlan_udp_port;
 210         u8              update_geneve_udp_port;
 211         u8              tunn_clss_vxlan;
 212         u8              tunn_clss_l2geneve;
 213         u8              tunn_clss_ipgeneve;
 214         u8              tunn_clss_l2gre;
 215         u8              tunn_clss_ipgre;
 216 };
 217
 218 /* The PCI personality is not quite synonymous to protocol ID:
 219  * 1. All personalities need CORE connections
 220  * 2. The Ethernet personality may support also the RoCE/iWARP protocol
 221  */
 222 enum qed_pci_personality {
 223         QED_PCI_ETH,
 224         QED_PCI_FCOE,
 225         QED_PCI_ISCSI,
 226         QED_PCI_ETH_ROCE,
 227         QED_PCI_ETH_IWARP,
 228         QED_PCI_ETH_RDMA,
 229         QED_PCI_DEFAULT, /* default in shmem */
 230 };
 231
 232 /* All VFs are symmetric, all counters are PF + all VFs */
 233 struct qed_qm_iids {
 234         u32 cids;
 235         u32 vf_cids;
 236         u32 tids;
 237 };
 238
 239 /* HW / FW resources, output of features supported below, most information
 240  * is received from MFW.
 241  */
 242 enum qed_resources {
 243         QED_SB,
 244         QED_L2_QUEUE,
 245         QED_VPORT,
 246         QED_RSS_ENG,
 247         QED_PQ,
 248         QED_RL,
 249         QED_MAC,
 250         QED_VLAN,
 251         QED_RDMA_CNQ_RAM,
 252         QED_ILT,
 253         QED_LL2_QUEUE,
 254         QED_CMDQS_CQS,
 255         QED_RDMA_STATS_QUEUE,
 256         QED_BDQ,
 257         QED_MAX_RESC,
 258 };
 259
 260 enum QED_FEATURE {
 261         QED_PF_L2_QUE,
 262         QED_VF,
 263         QED_RDMA_CNQ,
 264         QED_ISCSI_CQ,
 265         QED_FCOE_CQ,
 266         QED_VF_L2_QUE,
 267         QED_MAX_FEATURES,
 268 };
 269
 270 enum QED_PORT_MODE {
 271         QED_PORT_MODE_DE_2X40G,
 272         QED_PORT_MODE_DE_2X50G,
 273         QED_PORT_MODE_DE_1X100G,
 274         QED_PORT_MODE_DE_4X10G_F,
 275         QED_PORT_MODE_DE_4X10G_E,
 276         QED_PORT_MODE_DE_4X20G,
 277         QED_PORT_MODE_DE_1X40G,
 278         QED_PORT_MODE_DE_2X25G,
 279         QED_PORT_MODE_DE_1X25G,
 280         QED_PORT_MODE_DE_4X25G,
 281         QED_PORT_MODE_DE_2X10G,
 282 };
 283
 284 enum qed_dev_cap {
 285         QED_DEV_CAP_ETH,
 286         QED_DEV_CAP_FCOE,
 287         QED_DEV_CAP_ISCSI,
 288         QED_DEV_CAP_ROCE,
 289         QED_DEV_CAP_IWARP,
 290 };
 291
 292 enum qed_wol_support {
 293         QED_WOL_SUPPORT_NONE,
 294         QED_WOL_SUPPORT_PME,
 295 };
 296
 297 struct qed_hw_info {
 298         /* PCI personality */
 299         enum qed_pci_personality personality;
 300 #define QED_IS_RDMA_PERSONALITY(dev)                        \
 301         ((dev)->hw_info.personality == QED_PCI_ETH_ROCE ||  \
 302          (dev)->hw_info.personality == QED_PCI_ETH_IWARP || \
 303          (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
 304 #define QED_IS_ROCE_PERSONALITY(dev)                       \
 305         ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \
 306          (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
 307 #define QED_IS_IWARP_PERSONALITY(dev)                       \
 308         ((dev)->hw_info.personality == QED_PCI_ETH_IWARP || \
 309          (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
 310 #define QED_IS_L2_PERSONALITY(dev)                    \
 311         ((dev)->hw_info.personality == QED_PCI_ETH || \
 312          QED_IS_RDMA_PERSONALITY(dev))
 313 #define QED_IS_FCOE_PERSONALITY(dev) \
 314         ((dev)->hw_info.personality == QED_PCI_FCOE)
 315 #define QED_IS_ISCSI_PERSONALITY(dev) \
 316         ((dev)->hw_info.personality == QED_PCI_ISCSI)
 317
 318         /* Resource Allocation scheme results */
 319         u32                             resc_start[QED_MAX_RESC];
 320         u32                             resc_num[QED_MAX_RESC];
 321         u32                             feat_num[QED_MAX_FEATURES];
 322
 323 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
 324 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
 325 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
 326                                  RESC_NUM(_p_hwfn, resc))
 327 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
 328
 329         /* Amount of traffic classes HW supports */
 330         u8 num_hw_tc;
 331
 332         /* Amount of TCs which should be active according to DCBx or upper
 333          * layer driver configuration.
 334          */
 335         u8 num_active_tc;
 336         u8                              offload_tc;
 337
 338         u32                             concrete_fid;
 339         u16                             opaque_fid;
 340         u16                             ovlan;
 341         u32                             part_num[4];
 342
 343         unsigned char                   hw_mac_addr[ETH_ALEN];
 344         u64                             node_wwn;
 345         u64                             port_wwn;
 346
 347         u16                             num_fcoe_conns;
 348
 349         struct qed_igu_info             *p_igu_info;
 350
 351         u32                             port_mode;
 352         u32                             hw_mode;
 353         unsigned long           device_capabilities;
 354         u16                             mtu;
 355
 356         enum qed_wol_support b_wol_support;
 357 };
 358
 359 /* maximun size of read/write commands (HW limit) */
 360 #define DMAE_MAX_RW_SIZE        0x2000
 361
 362 struct qed_dmae_info {
 363         /* Mutex for synchronizing access to functions */
 364         struct mutex    mutex;
 365
 366         u8              channel;
 367
 368         dma_addr_t      completion_word_phys_addr;
 369
 370         /* The memory location where the DMAE writes the completion
 371          * value when an operation is finished on this context.
 372          */
 373         u32             *p_completion_word;
 374
 375         dma_addr_t      intermediate_buffer_phys_addr;
 376
 377         /* An intermediate buffer for DMAE operations that use virtual
 378          * addresses - data is DMA'd to/from this buffer and then
 379          * memcpy'd to/from the virtual address
 380          */
 381         u32             *p_intermediate_buffer;
 382
 383         dma_addr_t      dmae_cmd_phys_addr;
 384         struct dmae_cmd *p_dmae_cmd;
 385 };
 386
 387 struct qed_wfq_data {
 388         /* when feature is configured for at least 1 vport */
 389         u32     min_speed;
 390         bool    configured;
 391 };
 392
 393 struct qed_qm_info {
 394         struct init_qm_pq_params        *qm_pq_params;
 395         struct init_qm_vport_params     *qm_vport_params;
 396         struct init_qm_port_params      *qm_port_params;
 397         u16                             start_pq;
 398         u8                              start_vport;
 399         u16                              pure_lb_pq;
 400         u16                             offload_pq;
 401         u16                             low_latency_pq;
 402         u16                             pure_ack_pq;
 403         u16                             ooo_pq;
 404         u16                             first_vf_pq;
 405         u16                             first_mcos_pq;
 406         u16                             first_rl_pq;
 407         u16                             num_pqs;
 408         u16                             num_vf_pqs;
 409         u8                              num_vports;
 410         u8                              max_phys_tcs_per_port;
 411         u8                              ooo_tc;
 412         bool                            pf_rl_en;
 413         bool                            pf_wfq_en;
 414         bool                            vport_rl_en;
 415         bool                            vport_wfq_en;
 416         u8                              pf_wfq;
 417         u32                             pf_rl;
 418         struct qed_wfq_data             *wfq_data;
 419         u8 num_pf_rls;
 420 };
 421
 422 struct storm_stats {
 423         u32     address;
 424         u32     len;
 425 };
 426
 427 struct qed_storm_stats {
 428         struct storm_stats mstats;
 429         struct storm_stats pstats;
 430         struct storm_stats tstats;
 431         struct storm_stats ustats;
 432 };
 433
 434 struct qed_fw_data {
 435         struct fw_ver_info      *fw_ver_info;
 436         const u8                *modes_tree_buf;
 437         union init_op           *init_ops;
 438         const u32               *arr_data;
 439         u32                     init_ops_size;
 440 };
 441
 442 enum qed_mf_mode_bit {
 443         /* Supports PF-classification based on tag */
 444         QED_MF_OVLAN_CLSS,
 445
 446         /* Supports PF-classification based on MAC */
 447         QED_MF_LLH_MAC_CLSS,
 448
 449         /* Supports PF-classification based on protocol type */
 450         QED_MF_LLH_PROTO_CLSS,
 451
 452         /* Requires a default PF to be set */
 453         QED_MF_NEED_DEF_PF,
 454
 455         /* Allow LL2 to multicast/broadcast */
 456         QED_MF_LL2_NON_UNICAST,
 457
 458         /* Allow Cross-PF [& child VFs] Tx-switching */
 459         QED_MF_INTER_PF_SWITCH,
 460
 461         /* Unified Fabtic Port support enabled */
 462         QED_MF_UFP_SPECIFIC,
 463
 464         /* Disable Accelerated Receive Flow Steering (aRFS) */
 465         QED_MF_DISABLE_ARFS,
 466
 467         /* Use vlan for steering */
 468         QED_MF_8021Q_TAGGING,
 469
 470         /* Use stag for steering */
 471         QED_MF_8021AD_TAGGING,
 472
 473         /* Allow DSCP to TC mapping */
 474         QED_MF_DSCP_TO_TC_MAP,
 475 };
 476
 477 enum BAR_ID {
 478         BAR_ID_0,               /* used for GRC */
 479         BAR_ID_1                /* Used for doorbells */
 480 };
 481
 482 struct qed_nvm_image_info {
 483         u32 num_images;
 484         struct bist_nvm_image_att *image_att;
 485 };
 486
 487 #define DRV_MODULE_VERSION                    \
 488         __stringify(QED_MAJOR_VERSION) "."    \
 489         __stringify(QED_MINOR_VERSION) "."    \
 490         __stringify(QED_REVISION_VERSION) "." \
 491         __stringify(QED_ENGINEERING_VERSION)
 492
 493 struct qed_simd_fp_handler {
 494         void    *token;
 495         void    (*func)(void *);
 496 };
 497
 498 struct qed_hwfn {
 499         struct qed_dev                  *cdev;
 500         u8                              my_id;          /* ID inside the PF */
 501 #define IS_LEAD_HWFN(edev)              (!((edev)->my_id))
 502         u8                              rel_pf_id;      /* Relative to engine*/
 503         u8                              abs_pf_id;
 504 #define QED_PATH_ID(_p_hwfn) \
 505         (QED_IS_K2((_p_hwfn)->cdev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
 506         u8                              port_id;
 507         bool                            b_active;
 508
 509         u32                             dp_module;
 510         u8                              dp_level;
 511         char                            name[NAME_SIZE];
 512
 513         bool                            first_on_engine;
 514         bool                            hw_init_done;
 515
 516         u8                              num_funcs_on_engine;
 517         u8 enabled_func_idx;
 518
 519         /* BAR access */
 520         void __iomem                    *regview;
 521         void __iomem                    *doorbells;
 522         u64                             db_phys_addr;
 523         unsigned long                   db_size;
 524
 525         /* PTT pool */
 526         struct qed_ptt_pool             *p_ptt_pool;
 527
 528         /* HW info */
 529         struct qed_hw_info              hw_info;
 530
 531         /* rt_array (for init-tool) */
 532         struct qed_rt_data              rt_data;
 533
 534         /* SPQ */
 535         struct qed_spq                  *p_spq;
 536
 537         /* EQ */
 538         struct qed_eq                   *p_eq;
 539
 540         /* Consolidate Q*/
 541         struct qed_consq                *p_consq;
 542
 543         /* Slow-Path definitions */
 544         struct tasklet_struct           *sp_dpc;
 545         bool                            b_sp_dpc_enabled;
 546
 547         struct qed_ptt                  *p_main_ptt;
 548         struct qed_ptt                  *p_dpc_ptt;
 549
 550         /* PTP will be used only by the leading function.
 551          * Usage of all PTP-apis should be synchronized as result.
 552          */
 553         struct qed_ptt *p_ptp_ptt;
 554
 555         struct qed_sb_sp_info           *p_sp_sb;
 556         struct qed_sb_attn_info         *p_sb_attn;
 557
 558         /* Protocol related */
 559         bool                            using_ll2;
 560         struct qed_ll2_info             *p_ll2_info;
 561         struct qed_ooo_info             *p_ooo_info;
 562         struct qed_rdma_info            *p_rdma_info;
 563         struct qed_iscsi_info           *p_iscsi_info;
 564         struct qed_fcoe_info            *p_fcoe_info;
 565         struct qed_pf_params            pf_params;
 566
 567         bool b_rdma_enabled_in_prs;
 568         u32 rdma_prs_search_reg;
 569
 570         struct qed_cxt_mngr             *p_cxt_mngr;
 571
 572         /* Flag indicating whether interrupts are enabled or not*/
 573         bool                            b_int_enabled;
 574         bool                            b_int_requested;
 575
 576         /* True if the driver requests for the link */
 577         bool                            b_drv_link_init;
 578
 579         struct qed_vf_iov               *vf_iov_info;
 580         struct qed_pf_iov               *pf_iov_info;
 581         struct qed_mcp_info             *mcp_info;
 582
 583         struct qed_dcbx_info            *p_dcbx_info;
 584
 585         struct qed_dmae_info            dmae_info;
 586
 587         /* QM init */
 588         struct qed_qm_info              qm_info;
 589         struct qed_storm_stats          storm_stats;
 590
 591         /* Buffer for unzipping firmware data */
 592         void                            *unzip_buf;
 593
 594         struct dbg_tools_data           dbg_info;
 595
 596         /* PWM region specific data */
 597         u16                             wid_count;
 598         u32                             dpi_size;
 599         u32                             dpi_count;
 600
 601         /* This is used to calculate the doorbell address */
 602         u32 dpi_start_offset;
 603
 604         /* If one of the following is set then EDPM shouldn't be used */
 605         u8 dcbx_no_edpm;
 606         u8 db_bar_no_edpm;
 607
 608         /* L2-related */
 609         struct qed_l2_info *p_l2_info;
 610
 611         /* Nvm images number and attributes */
 612         struct qed_nvm_image_info nvm_info;
 613
 614         struct qed_ptt *p_arfs_ptt;
 615
 616         struct qed_simd_fp_handler      simd_proto_handler[64];
 617
 618 #ifdef CONFIG_QED_SRIOV
 619         struct workqueue_struct *iov_wq;
 620         struct delayed_work iov_task;
 621         unsigned long iov_task_flags;
 622 #endif
 623
 624         struct z_stream_s               *stream;
 625 };
 626
 627 struct pci_params {
 628         int             pm_cap;
 629
 630         unsigned long   mem_start;
 631         unsigned long   mem_end;
 632         unsigned int    irq;
 633         u8              pf_num;
 634 };
 635
 636 struct qed_int_param {
 637         u32     int_mode;
 638         u8      num_vectors;
 639         u8      min_msix_cnt; /* for minimal functionality */
 640 };
 641
 642 struct qed_int_params {
 643         struct qed_int_param    in;
 644         struct qed_int_param    out;
 645         struct msix_entry       *msix_table;
 646         bool                    fp_initialized;
 647         u8                      fp_msix_base;
 648         u8                      fp_msix_cnt;
 649         u8                      rdma_msix_base;
 650         u8                      rdma_msix_cnt;
 651 };
 652
 653 struct qed_dbg_feature {
 654         struct dentry *dentry;
 655         u8 *dump_buf;
 656         u32 buf_size;
 657         u32 dumped_dwords;
 658 };
 659
 660 struct qed_dbg_params {
 661         struct qed_dbg_feature features[DBG_FEATURE_NUM];
 662         u8 engine_for_debug;
 663         bool print_data;
 664 };
 665
 666 struct qed_dev {
 667         u32     dp_module;
 668         u8      dp_level;
 669         char    name[NAME_SIZE];
 670
 671         enum    qed_dev_type type;
 672 /* Translate type/revision combo into the proper conditions */
 673 #define QED_IS_BB(dev)  ((dev)->type == QED_DEV_TYPE_BB)
 674 #define QED_IS_BB_B0(dev)       (QED_IS_BB(dev) && \
 675                                  CHIP_REV_IS_B0(dev))
 676 #define QED_IS_AH(dev)  ((dev)->type == QED_DEV_TYPE_AH)
 677 #define QED_IS_K2(dev)  QED_IS_AH(dev)
 678
 679         u16     vendor_id;
 680         u16     device_id;
 681 #define QED_DEV_ID_MASK         0xff00
 682 #define QED_DEV_ID_MASK_BB      0x1600
 683 #define QED_DEV_ID_MASK_AH      0x8000
 684
 685         u16     chip_num;
 686 #define CHIP_NUM_MASK                   0xffff
 687 #define CHIP_NUM_SHIFT                  16
 688
 689         u16     chip_rev;
 690 #define CHIP_REV_MASK                   0xf
 691 #define CHIP_REV_SHIFT                  12
 692 #define CHIP_REV_IS_B0(_cdev)   ((_cdev)->chip_rev == 1)
 693
 694         u16                             chip_metal;
 695 #define CHIP_METAL_MASK                 0xff
 696 #define CHIP_METAL_SHIFT                4
 697
 698         u16                             chip_bond_id;
 699 #define CHIP_BOND_ID_MASK               0xf
 700 #define CHIP_BOND_ID_SHIFT              0
 701
 702         u8                              num_engines;
 703         u8                              num_ports_in_engine;
 704         u8                              num_funcs_in_port;
 705
 706         u8                              path_id;
 707
 708         unsigned long                   mf_bits;
 709
 710         int                             pcie_width;
 711         int                             pcie_speed;
 712
 713         /* Add MF related configuration */
 714         u8                              mcp_rev;
 715         u8                              boot_mode;
 716
 717         /* WoL related configurations */
 718         u8 wol_config;
 719         u8 wol_mac[ETH_ALEN];
 720
 721         u32                             int_mode;
 722         enum qed_coalescing_mode        int_coalescing_mode;
 723         u16                             rx_coalesce_usecs;
 724         u16                             tx_coalesce_usecs;
 725
 726         /* Start Bar offset of first hwfn */
 727         void __iomem                    *regview;
 728         void __iomem                    *doorbells;
 729         u64                             db_phys_addr;
 730         unsigned long                   db_size;
 731
 732         /* PCI */
 733         u8                              cache_shift;
 734
 735         /* Init */
 736         const struct iro                *iro_arr;
 737 #define IRO (p_hwfn->cdev->iro_arr)
 738
 739         /* HW functions */
 740         u8                              num_hwfns;
 741         struct qed_hwfn                 hwfns[MAX_HWFNS_PER_DEVICE];
 742
 743         /* SRIOV */
 744         struct qed_hw_sriov_info *p_iov_info;
 745 #define IS_QED_SRIOV(cdev)              (!!(cdev)->p_iov_info)
 746         struct qed_tunnel_info          tunnel;
 747         bool                            b_is_vf;
 748         u32                             drv_type;
 749         struct qed_eth_stats            *reset_stats;
 750         struct qed_fw_data              *fw_data;
 751
 752         u32                             mcp_nvm_resp;
 753
 754         /* Linux specific here */
 755         struct  qede_dev                *edev;
 756         struct  pci_dev                 *pdev;
 757         u32 flags;
 758 #define QED_FLAG_STORAGE_STARTED        (BIT(0))
 759         int                             msg_enable;
 760
 761         struct pci_params               pci_params;
 762
 763         struct qed_int_params           int_params;
 764
 765         u8                              protocol;
 766 #define IS_QED_ETH_IF(cdev)     ((cdev)->protocol == QED_PROTOCOL_ETH)
 767 #define IS_QED_FCOE_IF(cdev)    ((cdev)->protocol == QED_PROTOCOL_FCOE)
 768
 769         /* Callbacks to protocol driver */
 770         union {
 771                 struct qed_common_cb_ops        *common;
 772                 struct qed_eth_cb_ops           *eth;
 773                 struct qed_fcoe_cb_ops          *fcoe;
 774                 struct qed_iscsi_cb_ops         *iscsi;
 775         } protocol_ops;
 776         void                            *ops_cookie;
 777
 778         struct qed_dbg_params           dbg_params;
 779
 780 #ifdef CONFIG_QED_LL2
 781         struct qed_cb_ll2_info          *ll2;
 782         u8                              ll2_mac_address[ETH_ALEN];
 783 #endif
 784         DECLARE_HASHTABLE(connections, 10);
 785         const struct firmware           *firmware;
 786
 787         u32 rdma_max_sge;
 788         u32 rdma_max_inline;
 789         u32 rdma_max_srq_sge;
 790         u16 tunn_feature_mask;
 791 };
 792
 793 #define NUM_OF_VFS(dev)         (QED_IS_BB(dev) ? MAX_NUM_VFS_BB \
 794                                                 : MAX_NUM_VFS_K2)
 795 #define NUM_OF_L2_QUEUES(dev)   (QED_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
 796                                                 : MAX_NUM_L2_QUEUES_K2)
 797 #define NUM_OF_PORTS(dev)       (QED_IS_BB(dev) ? MAX_NUM_PORTS_BB \
 798                                                 : MAX_NUM_PORTS_K2)
 799 #define NUM_OF_SBS(dev)         (QED_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
 800                                                 : MAX_SB_PER_PATH_K2)
 801 #define NUM_OF_ENG_PFS(dev)     (QED_IS_BB(dev) ? MAX_NUM_PFS_BB \
 802                                                 : MAX_NUM_PFS_K2)
 803
 804 /**
 805  * @brief qed_concrete_to_sw_fid - get the sw function id from
 806  *        the concrete value.
 807  *
 808  * @param concrete_fid
 809  *
 810  * @return inline u8
 811  */
 812 static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
 813                                         u32 concrete_fid)
 814 {
 815         u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
 816         u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
 817         u8 vf_valid = GET_FIELD(concrete_fid,
 818                                 PXP_CONCRETE_FID_VFVALID);
 819         u8 sw_fid;
 820
 821         if (vf_valid)
 822                 sw_fid = vfid + MAX_NUM_PFS;
 823         else
 824                 sw_fid = pfid;
 825
 826         return sw_fid;
 827 }
 828
 829 #define PKT_LB_TC       9
 830 #define MAX_NUM_VOQS_E4 20
 831
 832 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate);
 833 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
 834                                          struct qed_ptt *p_ptt,
 835                                          u32 min_pf_rate);
 836
 837 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
 838 int qed_device_num_engines(struct qed_dev *cdev);
 839 int qed_device_get_port_id(struct qed_dev *cdev);
 840 void qed_set_fw_mac_addr(__le16 *fw_msb,
 841                          __le16 *fw_mid, __le16 *fw_lsb, u8 *mac);
 842
 843 #define QED_LEADING_HWFN(dev)   (&dev->hwfns[0])
 844
 845 /* Flags for indication of required queues */
 846 #define PQ_FLAGS_RLS    (BIT(0))
 847 #define PQ_FLAGS_MCOS   (BIT(1))
 848 #define PQ_FLAGS_LB     (BIT(2))
 849 #define PQ_FLAGS_OOO    (BIT(3))
 850 #define PQ_FLAGS_ACK    (BIT(4))
 851 #define PQ_FLAGS_OFLD   (BIT(5))
 852 #define PQ_FLAGS_VFS    (BIT(6))
 853 #define PQ_FLAGS_LLT    (BIT(7))
 854
 855 /* physical queue index for cm context intialization */
 856 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags);
 857 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc);
 858 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf);
 859
 860 #define QED_LEADING_HWFN(dev)   (&dev->hwfns[0])
 861
 862 /* Other Linux specific common definitions */
 863 #define DP_NAME(cdev) ((cdev)->name)
 864
 865 #define REG_ADDR(cdev, offset)          (void __iomem *)((u8 __iomem *)\
 866                                                 (cdev->regview) + \
 867                                                          (offset))
 868
 869 #define REG_RD(cdev, offset)            readl(REG_ADDR(cdev, offset))
 870 #define REG_WR(cdev, offset, val)       writel((u32)val, REG_ADDR(cdev, offset))
 871 #define REG_WR16(cdev, offset, val)     writew((u16)val, REG_ADDR(cdev, offset))
 872
 873 #define DOORBELL(cdev, db_addr, val)                     \
 874         writel((u32)val, (void __iomem *)((u8 __iomem *)\
 875                                           (cdev->doorbells) + (db_addr)))
 876
 877 /* Prototypes */
 878 int qed_fill_dev_info(struct qed_dev *cdev,
 879                       struct qed_dev_info *dev_info);
 880 void qed_link_update(struct qed_hwfn *hwfn);
 881 u32 qed_unzip_data(struct qed_hwfn *p_hwfn,
 882                    u32 input_len, u8 *input_buf,
 883                    u32 max_size, u8 *unzip_buf);
 884 void qed_get_protocol_stats(struct qed_dev *cdev,
 885                             enum qed_mcp_protocol_type type,
 886                             union qed_mcp_protocol_stats *stats);
 887 int qed_slowpath_irq_req(struct qed_hwfn *hwfn);
 888 void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn);
 889
 890 #endif /* _QED_H */