drivers/net/ethernet/qlogic/qed/qed_dev.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/types.h>
  34 #include <asm/byteorder.h>
  35 #include <linux/io.h>
  36 #include <linux/delay.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/errno.h>
  39 #include <linux/kernel.h>
  40 #include <linux/mutex.h>
  41 #include <linux/pci.h>
  42 #include <linux/slab.h>
  43 #include <linux/string.h>
  44 #include <linux/vmalloc.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/qed/qed_chain.h>
  47 #include <linux/qed/qed_if.h>
  48 #include "qed.h"
  49 #include "qed_cxt.h"
  50 #include "qed_dcbx.h"
  51 #include "qed_dev_api.h"
  52 #include "qed_fcoe.h"
  53 #include "qed_hsi.h"
  54 #include "qed_hw.h"
  55 #include "qed_init_ops.h"
  56 #include "qed_int.h"
  57 #include "qed_iscsi.h"
  58 #include "qed_ll2.h"
  59 #include "qed_mcp.h"
  60 #include "qed_ooo.h"
  61 #include "qed_reg_addr.h"
  62 #include "qed_sp.h"
  63 #include "qed_sriov.h"
  64 #include "qed_vf.h"
  65 #include "qed_rdma.h"
  66
  67 static DEFINE_SPINLOCK(qm_lock);
  68
  69 #define QED_MIN_DPIS            (4)
  70 #define QED_MIN_PWM_REGION      (QED_WID_SIZE * QED_MIN_DPIS)
  71
  72 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn,
  73                            struct qed_ptt *p_ptt, enum BAR_ID bar_id)
  74 {
  75         u32 bar_reg = (bar_id == BAR_ID_0 ?
  76                        PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);
  77         u32 val;
  78
  79         if (IS_VF(p_hwfn->cdev))
  80                 return qed_vf_hw_bar_size(p_hwfn, bar_id);
  81
  82         val = qed_rd(p_hwfn, p_ptt, bar_reg);
  83         if (val)
  84                 return 1 << (val + 15);
  85
  86         /* Old MFW initialized above registered only conditionally */
  87         if (p_hwfn->cdev->num_hwfns > 1) {
  88                 DP_INFO(p_hwfn,
  89                         "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
  90                         return BAR_ID_0 ? 256 * 1024 : 512 * 1024;
  91         } else {
  92                 DP_INFO(p_hwfn,
  93                         "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
  94                         return 512 * 1024;
  95         }
  96 }
  97
  98 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level)
  99 {
 100         u32 i;
 101
 102         cdev->dp_level = dp_level;
 103         cdev->dp_module = dp_module;
 104         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 105                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 106
 107                 p_hwfn->dp_level = dp_level;
 108                 p_hwfn->dp_module = dp_module;
 109         }
 110 }
 111
 112 void qed_init_struct(struct qed_dev *cdev)
 113 {
 114         u8 i;
 115
 116         for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) {
 117                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 118
 119                 p_hwfn->cdev = cdev;
 120                 p_hwfn->my_id = i;
 121                 p_hwfn->b_active = false;
 122
 123                 mutex_init(&p_hwfn->dmae_info.mutex);
 124         }
 125
 126         /* hwfn 0 is always active */
 127         cdev->hwfns[0].b_active = true;
 128
 129         /* set the default cache alignment to 128 */
 130         cdev->cache_shift = 7;
 131 }
 132
 133 static void qed_qm_info_free(struct qed_hwfn *p_hwfn)
 134 {
 135         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 136
 137         kfree(qm_info->qm_pq_params);
 138         qm_info->qm_pq_params = NULL;
 139         kfree(qm_info->qm_vport_params);
 140         qm_info->qm_vport_params = NULL;
 141         kfree(qm_info->qm_port_params);
 142         qm_info->qm_port_params = NULL;
 143         kfree(qm_info->wfq_data);
 144         qm_info->wfq_data = NULL;
 145 }
 146
 147 void qed_resc_free(struct qed_dev *cdev)
 148 {
 149         int i;
 150
 151         if (IS_VF(cdev)) {
 152                 for_each_hwfn(cdev, i)
 153                         qed_l2_free(&cdev->hwfns[i]);
 154                 return;
 155         }
 156
 157         kfree(cdev->fw_data);
 158         cdev->fw_data = NULL;
 159
 160         kfree(cdev->reset_stats);
 161         cdev->reset_stats = NULL;
 162
 163         for_each_hwfn(cdev, i) {
 164                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 165
 166                 qed_cxt_mngr_free(p_hwfn);
 167                 qed_qm_info_free(p_hwfn);
 168                 qed_spq_free(p_hwfn);
 169                 qed_eq_free(p_hwfn);
 170                 qed_consq_free(p_hwfn);
 171                 qed_int_free(p_hwfn);
 172 #ifdef CONFIG_QED_LL2
 173                 qed_ll2_free(p_hwfn);
 174 #endif
 175                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
 176                         qed_fcoe_free(p_hwfn);
 177
 178                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 179                         qed_iscsi_free(p_hwfn);
 180                         qed_ooo_free(p_hwfn);
 181                 }
 182                 qed_iov_free(p_hwfn);
 183                 qed_l2_free(p_hwfn);
 184                 qed_dmae_info_free(p_hwfn);
 185                 qed_dcbx_info_free(p_hwfn);
 186         }
 187 }
 188
 189 /******************** QM initialization *******************/
 190 #define ACTIVE_TCS_BMAP 0x9f
 191 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf
 192
 193 /* determines the physical queue flags for a given PF. */
 194 static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn)
 195 {
 196         u32 flags;
 197
 198         /* common flags */
 199         flags = PQ_FLAGS_LB;
 200
 201         /* feature flags */
 202         if (IS_QED_SRIOV(p_hwfn->cdev))
 203                 flags |= PQ_FLAGS_VFS;
 204
 205         /* protocol flags */
 206         switch (p_hwfn->hw_info.personality) {
 207         case QED_PCI_ETH:
 208                 flags |= PQ_FLAGS_MCOS;
 209                 break;
 210         case QED_PCI_FCOE:
 211                 flags |= PQ_FLAGS_OFLD;
 212                 break;
 213         case QED_PCI_ISCSI:
 214                 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD;
 215                 break;
 216         case QED_PCI_ETH_ROCE:
 217                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT;
 218                 break;
 219         case QED_PCI_ETH_IWARP:
 220                 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO |
 221                     PQ_FLAGS_OFLD;
 222                 break;
 223         default:
 224                 DP_ERR(p_hwfn,
 225                        "unknown personality %d\n", p_hwfn->hw_info.personality);
 226                 return 0;
 227         }
 228
 229         return flags;
 230 }
 231
 232 /* Getters for resource amounts necessary for qm initialization */
 233 u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn)
 234 {
 235         return p_hwfn->hw_info.num_hw_tc;
 236 }
 237
 238 u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn)
 239 {
 240         return IS_QED_SRIOV(p_hwfn->cdev) ?
 241                p_hwfn->cdev->p_iov_info->total_vfs : 0;
 242 }
 243
 244 #define NUM_DEFAULT_RLS 1
 245
 246 u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn)
 247 {
 248         u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
 249
 250         /* num RLs can't exceed resource amount of rls or vports */
 251         num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL),
 252                                  RESC_NUM(p_hwfn, QED_VPORT));
 253
 254         /* Make sure after we reserve there's something left */
 255         if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS)
 256                 return 0;
 257
 258         /* subtract rls necessary for VFs and one default one for the PF */
 259         num_pf_rls -= num_vfs + NUM_DEFAULT_RLS;
 260
 261         return num_pf_rls;
 262 }
 263
 264 u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn)
 265 {
 266         u32 pq_flags = qed_get_pq_flags(p_hwfn);
 267
 268         /* all pqs share the same vport, except for vfs and pf_rl pqs */
 269         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 270                qed_init_qm_get_num_pf_rls(p_hwfn) +
 271                (!!(PQ_FLAGS_VFS & pq_flags)) *
 272                qed_init_qm_get_num_vfs(p_hwfn) + 1;
 273 }
 274
 275 /* calc amount of PQs according to the requested flags */
 276 u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn)
 277 {
 278         u32 pq_flags = qed_get_pq_flags(p_hwfn);
 279
 280         return (!!(PQ_FLAGS_RLS & pq_flags)) *
 281                qed_init_qm_get_num_pf_rls(p_hwfn) +
 282                (!!(PQ_FLAGS_MCOS & pq_flags)) *
 283                qed_init_qm_get_num_tcs(p_hwfn) +
 284                (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) +
 285                (!!(PQ_FLAGS_ACK & pq_flags)) + (!!(PQ_FLAGS_OFLD & pq_flags)) +
 286                (!!(PQ_FLAGS_LLT & pq_flags)) +
 287                (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn);
 288 }
 289
 290 /* initialize the top level QM params */
 291 static void qed_init_qm_params(struct qed_hwfn *p_hwfn)
 292 {
 293         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 294         bool four_port;
 295
 296         /* pq and vport bases for this PF */
 297         qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ);
 298         qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);
 299
 300         /* rate limiting and weighted fair queueing are always enabled */
 301         qm_info->vport_rl_en = true;
 302         qm_info->vport_wfq_en = true;
 303
 304         /* TC config is different for AH 4 port */
 305         four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2;
 306
 307         /* in AH 4 port we have fewer TCs per port */
 308         qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 :
 309                                                      NUM_OF_PHYS_TCS;
 310
 311         /* unless MFW indicated otherwise, ooo_tc == 3 for
 312          * AH 4-port and 4 otherwise.
 313          */
 314         if (!qm_info->ooo_tc)
 315                 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC :
 316                                               DCBX_TCP_OOO_TC;
 317 }
 318
 319 /* initialize qm vport params */
 320 static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn)
 321 {
 322         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 323         u8 i;
 324
 325         /* all vports participate in weighted fair queueing */
 326         for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++)
 327                 qm_info->qm_vport_params[i].vport_wfq = 1;
 328 }
 329
 330 /* initialize qm port params */
 331 static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn)
 332 {
 333         /* Initialize qm port parameters */
 334         u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine;
 335
 336         /* indicate how ooo and high pri traffic is dealt with */
 337         active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
 338                           ACTIVE_TCS_BMAP_4PORT_K2 :
 339                           ACTIVE_TCS_BMAP;
 340
 341         for (i = 0; i < num_ports; i++) {
 342                 struct init_qm_port_params *p_qm_port =
 343                     &p_hwfn->qm_info.qm_port_params[i];
 344
 345                 p_qm_port->active = 1;
 346                 p_qm_port->active_phys_tcs = active_phys_tcs;
 347                 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
 348                 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
 349         }
 350 }
 351
 352 /* Reset the params which must be reset for qm init. QM init may be called as
 353  * a result of flows other than driver load (e.g. dcbx renegotiation). Other
 354  * params may be affected by the init but would simply recalculate to the same
 355  * values. The allocations made for QM init, ports, vports, pqs and vfqs are not
 356  * affected as these amounts stay the same.
 357  */
 358 static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn)
 359 {
 360         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 361
 362         qm_info->num_pqs = 0;
 363         qm_info->num_vports = 0;
 364         qm_info->num_pf_rls = 0;
 365         qm_info->num_vf_pqs = 0;
 366         qm_info->first_vf_pq = 0;
 367         qm_info->first_mcos_pq = 0;
 368         qm_info->first_rl_pq = 0;
 369 }
 370
 371 static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn)
 372 {
 373         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 374
 375         qm_info->num_vports++;
 376
 377         if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
 378                 DP_ERR(p_hwfn,
 379                        "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
 380                        qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
 381 }
 382
 383 /* initialize a single pq and manage qm_info resources accounting.
 384  * The pq_init_flags param determines whether the PQ is rate limited
 385  * (for VF or PF) and whether a new vport is allocated to the pq or not
 386  * (i.e. vport will be shared).
 387  */
 388
 389 /* flags for pq init */
 390 #define PQ_INIT_SHARE_VPORT     (1 << 0)
 391 #define PQ_INIT_PF_RL           (1 << 1)
 392 #define PQ_INIT_VF_RL           (1 << 2)
 393
 394 /* defines for pq init */
 395 #define PQ_INIT_DEFAULT_WRR_GROUP       1
 396 #define PQ_INIT_DEFAULT_TC              0
 397 #define PQ_INIT_OFLD_TC                 (p_hwfn->hw_info.offload_tc)
 398
 399 static void qed_init_qm_pq(struct qed_hwfn *p_hwfn,
 400                            struct qed_qm_info *qm_info,
 401                            u8 tc, u32 pq_init_flags)
 402 {
 403         u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn);
 404
 405         if (pq_idx > max_pq)
 406                 DP_ERR(p_hwfn,
 407                        "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq);
 408
 409         /* init pq params */
 410         qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id;
 411         qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport +
 412             qm_info->num_vports;
 413         qm_info->qm_pq_params[pq_idx].tc_id = tc;
 414         qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP;
 415         qm_info->qm_pq_params[pq_idx].rl_valid =
 416             (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL);
 417
 418         /* qm params accounting */
 419         qm_info->num_pqs++;
 420         if (!(pq_init_flags & PQ_INIT_SHARE_VPORT))
 421                 qm_info->num_vports++;
 422
 423         if (pq_init_flags & PQ_INIT_PF_RL)
 424                 qm_info->num_pf_rls++;
 425
 426         if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn))
 427                 DP_ERR(p_hwfn,
 428                        "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n",
 429                        qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn));
 430
 431         if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn))
 432                 DP_ERR(p_hwfn,
 433                        "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n",
 434                        qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn));
 435 }
 436
 437 /* get pq index according to PQ_FLAGS */
 438 static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn,
 439                                            u32 pq_flags)
 440 {
 441         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 442
 443         /* Can't have multiple flags set here */
 444         if (bitmap_weight((unsigned long *)&pq_flags, sizeof(pq_flags)) > 1)
 445                 goto err;
 446
 447         switch (pq_flags) {
 448         case PQ_FLAGS_RLS:
 449                 return &qm_info->first_rl_pq;
 450         case PQ_FLAGS_MCOS:
 451                 return &qm_info->first_mcos_pq;
 452         case PQ_FLAGS_LB:
 453                 return &qm_info->pure_lb_pq;
 454         case PQ_FLAGS_OOO:
 455                 return &qm_info->ooo_pq;
 456         case PQ_FLAGS_ACK:
 457                 return &qm_info->pure_ack_pq;
 458         case PQ_FLAGS_OFLD:
 459                 return &qm_info->offload_pq;
 460         case PQ_FLAGS_LLT:
 461                 return &qm_info->low_latency_pq;
 462         case PQ_FLAGS_VFS:
 463                 return &qm_info->first_vf_pq;
 464         default:
 465                 goto err;
 466         }
 467
 468 err:
 469         DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags);
 470         return NULL;
 471 }
 472
 473 /* save pq index in qm info */
 474 static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn,
 475                                 u32 pq_flags, u16 pq_val)
 476 {
 477         u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 478
 479         *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val;
 480 }
 481
 482 /* get tx pq index, with the PQ TX base already set (ready for context init) */
 483 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags)
 484 {
 485         u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags);
 486
 487         return *base_pq_idx + CM_TX_PQ_BASE;
 488 }
 489
 490 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc)
 491 {
 492         u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn);
 493
 494         if (tc > max_tc)
 495                 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 496
 497         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
 498 }
 499
 500 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf)
 501 {
 502         u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn);
 503
 504         if (vf > max_vf)
 505                 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 506
 507         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
 508 }
 509
 510 u16 qed_get_cm_pq_idx_rl(struct qed_hwfn *p_hwfn, u8 rl)
 511 {
 512         u16 max_rl = qed_init_qm_get_num_pf_rls(p_hwfn);
 513
 514         if (rl > max_rl)
 515                 DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
 516
 517         return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
 518 }
 519
 520 /* Functions for creating specific types of pqs */
 521 static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn)
 522 {
 523         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 524
 525         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB))
 526                 return;
 527
 528         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs);
 529         qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT);
 530 }
 531
 532 static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn)
 533 {
 534         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 535
 536         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO))
 537                 return;
 538
 539         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs);
 540         qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT);
 541 }
 542
 543 static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn)
 544 {
 545         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 546
 547         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK))
 548                 return;
 549
 550         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs);
 551         qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 552 }
 553
 554 static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn)
 555 {
 556         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 557
 558         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD))
 559                 return;
 560
 561         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs);
 562         qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 563 }
 564
 565 static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn)
 566 {
 567         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 568
 569         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT))
 570                 return;
 571
 572         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs);
 573         qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT);
 574 }
 575
 576 static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn)
 577 {
 578         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 579         u8 tc_idx;
 580
 581         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS))
 582                 return;
 583
 584         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs);
 585         for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++)
 586                 qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT);
 587 }
 588
 589 static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn)
 590 {
 591         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 592         u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn);
 593
 594         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS))
 595                 return;
 596
 597         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs);
 598         qm_info->num_vf_pqs = num_vfs;
 599         for (vf_idx = 0; vf_idx < num_vfs; vf_idx++)
 600                 qed_init_qm_pq(p_hwfn,
 601                                qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL);
 602 }
 603
 604 static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn)
 605 {
 606         u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn);
 607         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 608
 609         if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS))
 610                 return;
 611
 612         qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs);
 613         for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++)
 614                 qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_PF_RL);
 615 }
 616
 617 static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn)
 618 {
 619         /* rate limited pqs, must come first (FW assumption) */
 620         qed_init_qm_rl_pqs(p_hwfn);
 621
 622         /* pqs for multi cos */
 623         qed_init_qm_mcos_pqs(p_hwfn);
 624
 625         /* pure loopback pq */
 626         qed_init_qm_lb_pq(p_hwfn);
 627
 628         /* out of order pq */
 629         qed_init_qm_ooo_pq(p_hwfn);
 630
 631         /* pure ack pq */
 632         qed_init_qm_pure_ack_pq(p_hwfn);
 633
 634         /* pq for offloaded protocol */
 635         qed_init_qm_offload_pq(p_hwfn);
 636
 637         /* low latency pq */
 638         qed_init_qm_low_latency_pq(p_hwfn);
 639
 640         /* done sharing vports */
 641         qed_init_qm_advance_vport(p_hwfn);
 642
 643         /* pqs for vfs */
 644         qed_init_qm_vf_pqs(p_hwfn);
 645 }
 646
 647 /* compare values of getters against resources amounts */
 648 static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn)
 649 {
 650         if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) {
 651                 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n");
 652                 return -EINVAL;
 653         }
 654
 655         if (qed_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, QED_PQ)) {
 656                 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n");
 657                 return -EINVAL;
 658         }
 659
 660         return 0;
 661 }
 662
 663 static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn)
 664 {
 665         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 666         struct init_qm_vport_params *vport;
 667         struct init_qm_port_params *port;
 668         struct init_qm_pq_params *pq;
 669         int i, tc;
 670
 671         /* top level params */
 672         DP_VERBOSE(p_hwfn,
 673                    NETIF_MSG_HW,
 674                    "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n",
 675                    qm_info->start_pq,
 676                    qm_info->start_vport,
 677                    qm_info->pure_lb_pq,
 678                    qm_info->offload_pq, qm_info->pure_ack_pq);
 679         DP_VERBOSE(p_hwfn,
 680                    NETIF_MSG_HW,
 681                    "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n",
 682                    qm_info->ooo_pq,
 683                    qm_info->first_vf_pq,
 684                    qm_info->num_pqs,
 685                    qm_info->num_vf_pqs,
 686                    qm_info->num_vports, qm_info->max_phys_tcs_per_port);
 687         DP_VERBOSE(p_hwfn,
 688                    NETIF_MSG_HW,
 689                    "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n",
 690                    qm_info->pf_rl_en,
 691                    qm_info->pf_wfq_en,
 692                    qm_info->vport_rl_en,
 693                    qm_info->vport_wfq_en,
 694                    qm_info->pf_wfq,
 695                    qm_info->pf_rl,
 696                    qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn));
 697
 698         /* port table */
 699         for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) {
 700                 port = &(qm_info->qm_port_params[i]);
 701                 DP_VERBOSE(p_hwfn,
 702                            NETIF_MSG_HW,
 703                            "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n",
 704                            i,
 705                            port->active,
 706                            port->active_phys_tcs,
 707                            port->num_pbf_cmd_lines,
 708                            port->num_btb_blocks, port->reserved);
 709         }
 710
 711         /* vport table */
 712         for (i = 0; i < qm_info->num_vports; i++) {
 713                 vport = &(qm_info->qm_vport_params[i]);
 714                 DP_VERBOSE(p_hwfn,
 715                            NETIF_MSG_HW,
 716                            "vport idx %d, vport_rl %d, wfq %d, first_tx_pq_id [ ",
 717                            qm_info->start_vport + i,
 718                            vport->vport_rl, vport->vport_wfq);
 719                 for (tc = 0; tc < NUM_OF_TCS; tc++)
 720                         DP_VERBOSE(p_hwfn,
 721                                    NETIF_MSG_HW,
 722                                    "%d ", vport->first_tx_pq_id[tc]);
 723                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n");
 724         }
 725
 726         /* pq table */
 727         for (i = 0; i < qm_info->num_pqs; i++) {
 728                 pq = &(qm_info->qm_pq_params[i]);
 729                 DP_VERBOSE(p_hwfn,
 730                            NETIF_MSG_HW,
 731                            "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n",
 732                            qm_info->start_pq + i,
 733                            pq->port_id,
 734                            pq->vport_id,
 735                            pq->tc_id, pq->wrr_group, pq->rl_valid);
 736         }
 737 }
 738
 739 static void qed_init_qm_info(struct qed_hwfn *p_hwfn)
 740 {
 741         /* reset params required for init run */
 742         qed_init_qm_reset_params(p_hwfn);
 743
 744         /* init QM top level params */
 745         qed_init_qm_params(p_hwfn);
 746
 747         /* init QM port params */
 748         qed_init_qm_port_params(p_hwfn);
 749
 750         /* init QM vport params */
 751         qed_init_qm_vport_params(p_hwfn);
 752
 753         /* init QM physical queue params */
 754         qed_init_qm_pq_params(p_hwfn);
 755
 756         /* display all that init */
 757         qed_dp_init_qm_params(p_hwfn);
 758 }
 759
 760 /* This function reconfigures the QM pf on the fly.
 761  * For this purpose we:
 762  * 1. reconfigure the QM database
 763  * 2. set new values to runtime array
 764  * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
 765  * 4. activate init tool in QM_PF stage
 766  * 5. send an sdm_qm_cmd through rbc interface to release the QM
 767  */
 768 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
 769 {
 770         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 771         bool b_rc;
 772         int rc;
 773
 774         /* initialize qed's qm data structure */
 775         qed_init_qm_info(p_hwfn);
 776
 777         /* stop PF's qm queues */
 778         spin_lock_bh(&qm_lock);
 779         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true,
 780                                     qm_info->start_pq, qm_info->num_pqs);
 781         spin_unlock_bh(&qm_lock);
 782         if (!b_rc)
 783                 return -EINVAL;
 784
 785         /* clear the QM_PF runtime phase leftovers from previous init */
 786         qed_init_clear_rt_data(p_hwfn);
 787
 788         /* prepare QM portion of runtime array */
 789         qed_qm_init_pf(p_hwfn, p_ptt, false);
 790
 791         /* activate init tool on runtime array */
 792         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id,
 793                           p_hwfn->hw_info.hw_mode);
 794         if (rc)
 795                 return rc;
 796
 797         /* start PF's qm queues */
 798         spin_lock_bh(&qm_lock);
 799         b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true,
 800                                     qm_info->start_pq, qm_info->num_pqs);
 801         spin_unlock_bh(&qm_lock);
 802         if (!b_rc)
 803                 return -EINVAL;
 804
 805         return 0;
 806 }
 807
 808 static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn)
 809 {
 810         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
 811         int rc;
 812
 813         rc = qed_init_qm_sanity(p_hwfn);
 814         if (rc)
 815                 goto alloc_err;
 816
 817         qm_info->qm_pq_params = kzalloc(sizeof(*qm_info->qm_pq_params) *
 818                                         qed_init_qm_get_num_pqs(p_hwfn),
 819                                         GFP_KERNEL);
 820         if (!qm_info->qm_pq_params)
 821                 goto alloc_err;
 822
 823         qm_info->qm_vport_params = kzalloc(sizeof(*qm_info->qm_vport_params) *
 824                                            qed_init_qm_get_num_vports(p_hwfn),
 825                                            GFP_KERNEL);
 826         if (!qm_info->qm_vport_params)
 827                 goto alloc_err;
 828
 829         qm_info->qm_port_params = kzalloc(sizeof(*qm_info->qm_port_params) *
 830                                           p_hwfn->cdev->num_ports_in_engine,
 831                                           GFP_KERNEL);
 832         if (!qm_info->qm_port_params)
 833                 goto alloc_err;
 834
 835         qm_info->wfq_data = kzalloc(sizeof(*qm_info->wfq_data) *
 836                                     qed_init_qm_get_num_vports(p_hwfn),
 837                                     GFP_KERNEL);
 838         if (!qm_info->wfq_data)
 839                 goto alloc_err;
 840
 841         return 0;
 842
 843 alloc_err:
 844         DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n");
 845         qed_qm_info_free(p_hwfn);
 846         return -ENOMEM;
 847 }
 848
 849 int qed_resc_alloc(struct qed_dev *cdev)
 850 {
 851         u32 rdma_tasks, excess_tasks;
 852         u32 line_count;
 853         int i, rc = 0;
 854
 855         if (IS_VF(cdev)) {
 856                 for_each_hwfn(cdev, i) {
 857                         rc = qed_l2_alloc(&cdev->hwfns[i]);
 858                         if (rc)
 859                                 return rc;
 860                 }
 861                 return rc;
 862         }
 863
 864         cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);
 865         if (!cdev->fw_data)
 866                 return -ENOMEM;
 867
 868         for_each_hwfn(cdev, i) {
 869                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
 870                 u32 n_eqes, num_cons;
 871
 872                 /* First allocate the context manager structure */
 873                 rc = qed_cxt_mngr_alloc(p_hwfn);
 874                 if (rc)
 875                         goto alloc_err;
 876
 877                 /* Set the HW cid/tid numbers (in the contest manager)
 878                  * Must be done prior to any further computations.
 879                  */
 880                 rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS);
 881                 if (rc)
 882                         goto alloc_err;
 883
 884                 rc = qed_alloc_qm_data(p_hwfn);
 885                 if (rc)
 886                         goto alloc_err;
 887
 888                 /* init qm info */
 889                 qed_init_qm_info(p_hwfn);
 890
 891                 /* Compute the ILT client partition */
 892                 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
 893                 if (rc) {
 894                         DP_NOTICE(p_hwfn,
 895                                   "too many ILT lines; re-computing with less lines\n");
 896                         /* In case there are not enough ILT lines we reduce the
 897                          * number of RDMA tasks and re-compute.
 898                          */
 899                         excess_tasks =
 900                             qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count);
 901                         if (!excess_tasks)
 902                                 goto alloc_err;
 903
 904                         rdma_tasks = RDMA_MAX_TIDS - excess_tasks;
 905                         rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks);
 906                         if (rc)
 907                                 goto alloc_err;
 908
 909                         rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count);
 910                         if (rc) {
 911                                 DP_ERR(p_hwfn,
 912                                        "failed ILT compute. Requested too many lines: %u\n",
 913                                        line_count);
 914
 915                                 goto alloc_err;
 916                         }
 917                 }
 918
 919                 /* CID map / ILT shadow table / T2
 920                  * The talbes sizes are determined by the computations above
 921                  */
 922                 rc = qed_cxt_tables_alloc(p_hwfn);
 923                 if (rc)
 924                         goto alloc_err;
 925
 926                 /* SPQ, must follow ILT because initializes SPQ context */
 927                 rc = qed_spq_alloc(p_hwfn);
 928                 if (rc)
 929                         goto alloc_err;
 930
 931                 /* SP status block allocation */
 932                 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn,
 933                                                          RESERVED_PTT_DPC);
 934
 935                 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt);
 936                 if (rc)
 937                         goto alloc_err;
 938
 939                 rc = qed_iov_alloc(p_hwfn);
 940                 if (rc)
 941                         goto alloc_err;
 942
 943                 /* EQ */
 944                 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain);
 945                 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) {
 946                         enum protocol_type rdma_proto;
 947
 948                         if (QED_IS_ROCE_PERSONALITY(p_hwfn))
 949                                 rdma_proto = PROTOCOLID_ROCE;
 950                         else
 951                                 rdma_proto = PROTOCOLID_IWARP;
 952
 953                         num_cons = qed_cxt_get_proto_cid_count(p_hwfn,
 954                                                                rdma_proto,
 955                                                                NULL) * 2;
 956                         n_eqes += num_cons + 2 * MAX_NUM_VFS_BB;
 957                 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 958                         num_cons =
 959                             qed_cxt_get_proto_cid_count(p_hwfn,
 960                                                         PROTOCOLID_ISCSI,
 961                                                         NULL);
 962                         n_eqes += 2 * num_cons;
 963                 }
 964
 965                 if (n_eqes > 0xFFFF) {
 966                         DP_ERR(p_hwfn,
 967                                "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
 968                                n_eqes, 0xFFFF);
 969                         goto alloc_no_mem;
 970                 }
 971
 972                 rc = qed_eq_alloc(p_hwfn, (u16) n_eqes);
 973                 if (rc)
 974                         goto alloc_err;
 975
 976                 rc = qed_consq_alloc(p_hwfn);
 977                 if (rc)
 978                         goto alloc_err;
 979
 980                 rc = qed_l2_alloc(p_hwfn);
 981                 if (rc)
 982                         goto alloc_err;
 983
 984 #ifdef CONFIG_QED_LL2
 985                 if (p_hwfn->using_ll2) {
 986                         rc = qed_ll2_alloc(p_hwfn);
 987                         if (rc)
 988                                 goto alloc_err;
 989                 }
 990 #endif
 991
 992                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
 993                         rc = qed_fcoe_alloc(p_hwfn);
 994                         if (rc)
 995                                 goto alloc_err;
 996                 }
 997
 998                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
 999                         rc = qed_iscsi_alloc(p_hwfn);
1000                         if (rc)
1001                                 goto alloc_err;
1002                         rc = qed_ooo_alloc(p_hwfn);
1003                         if (rc)
1004                                 goto alloc_err;
1005                 }
1006
1007                 /* DMA info initialization */
1008                 rc = qed_dmae_info_alloc(p_hwfn);
1009                 if (rc)
1010                         goto alloc_err;
1011
1012                 /* DCBX initialization */
1013                 rc = qed_dcbx_info_alloc(p_hwfn);
1014                 if (rc)
1015                         goto alloc_err;
1016         }
1017
1018         cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL);
1019         if (!cdev->reset_stats)
1020                 goto alloc_no_mem;
1021
1022         return 0;
1023
1024 alloc_no_mem:
1025         rc = -ENOMEM;
1026 alloc_err:
1027         qed_resc_free(cdev);
1028         return rc;
1029 }
1030
1031 void qed_resc_setup(struct qed_dev *cdev)
1032 {
1033         int i;
1034
1035         if (IS_VF(cdev)) {
1036                 for_each_hwfn(cdev, i)
1037                         qed_l2_setup(&cdev->hwfns[i]);
1038                 return;
1039         }
1040
1041         for_each_hwfn(cdev, i) {
1042                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1043
1044                 qed_cxt_mngr_setup(p_hwfn);
1045                 qed_spq_setup(p_hwfn);
1046                 qed_eq_setup(p_hwfn);
1047                 qed_consq_setup(p_hwfn);
1048
1049                 /* Read shadow of current MFW mailbox */
1050                 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt);
1051                 memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1052                        p_hwfn->mcp_info->mfw_mb_cur,
1053                        p_hwfn->mcp_info->mfw_mb_length);
1054
1055                 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt);
1056
1057                 qed_l2_setup(p_hwfn);
1058                 qed_iov_setup(p_hwfn);
1059 #ifdef CONFIG_QED_LL2
1060                 if (p_hwfn->using_ll2)
1061                         qed_ll2_setup(p_hwfn);
1062 #endif
1063                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
1064                         qed_fcoe_setup(p_hwfn);
1065
1066                 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) {
1067                         qed_iscsi_setup(p_hwfn);
1068                         qed_ooo_setup(p_hwfn);
1069                 }
1070         }
1071 }
1072
1073 #define FINAL_CLEANUP_POLL_CNT          (100)
1074 #define FINAL_CLEANUP_POLL_TIME         (10)
1075 int qed_final_cleanup(struct qed_hwfn *p_hwfn,
1076                       struct qed_ptt *p_ptt, u16 id, bool is_vf)
1077 {
1078         u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT;
1079         int rc = -EBUSY;
1080
1081         addr = GTT_BAR0_MAP_REG_USDM_RAM +
1082                 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id);
1083
1084         if (is_vf)
1085                 id += 0x10;
1086
1087         command |= X_FINAL_CLEANUP_AGG_INT <<
1088                 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT;
1089         command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT;
1090         command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT;
1091         command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT;
1092
1093         /* Make sure notification is not set before initiating final cleanup */
1094         if (REG_RD(p_hwfn, addr)) {
1095                 DP_NOTICE(p_hwfn,
1096                           "Unexpected; Found final cleanup notification before initiating final cleanup\n");
1097                 REG_WR(p_hwfn, addr, 0);
1098         }
1099
1100         DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1101                    "Sending final cleanup for PFVF[%d] [Command %08x\n]",
1102                    id, command);
1103
1104         qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command);
1105
1106         /* Poll until completion */
1107         while (!REG_RD(p_hwfn, addr) && count--)
1108                 msleep(FINAL_CLEANUP_POLL_TIME);
1109
1110         if (REG_RD(p_hwfn, addr))
1111                 rc = 0;
1112         else
1113                 DP_NOTICE(p_hwfn,
1114                           "Failed to receive FW final cleanup notification\n");
1115
1116         /* Cleanup afterwards */
1117         REG_WR(p_hwfn, addr, 0);
1118
1119         return rc;
1120 }
1121
1122 static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
1123 {
1124         int hw_mode = 0;
1125
1126         if (QED_IS_BB_B0(p_hwfn->cdev)) {
1127                 hw_mode |= 1 << MODE_BB;
1128         } else if (QED_IS_AH(p_hwfn->cdev)) {
1129                 hw_mode |= 1 << MODE_K2;
1130         } else {
1131                 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n",
1132                           p_hwfn->cdev->type);
1133                 return -EINVAL;
1134         }
1135
1136         switch (p_hwfn->cdev->num_ports_in_engine) {
1137         case 1:
1138                 hw_mode |= 1 << MODE_PORTS_PER_ENG_1;
1139                 break;
1140         case 2:
1141                 hw_mode |= 1 << MODE_PORTS_PER_ENG_2;
1142                 break;
1143         case 4:
1144                 hw_mode |= 1 << MODE_PORTS_PER_ENG_4;
1145                 break;
1146         default:
1147                 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n",
1148                           p_hwfn->cdev->num_ports_in_engine);
1149                 return -EINVAL;
1150         }
1151
1152         switch (p_hwfn->cdev->mf_mode) {
1153         case QED_MF_DEFAULT:
1154         case QED_MF_NPAR:
1155                 hw_mode |= 1 << MODE_MF_SI;
1156                 break;
1157         case QED_MF_OVLAN:
1158                 hw_mode |= 1 << MODE_MF_SD;
1159                 break;
1160         default:
1161                 DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
1162                 hw_mode |= 1 << MODE_MF_SI;
1163         }
1164
1165         hw_mode |= 1 << MODE_ASIC;
1166
1167         if (p_hwfn->cdev->num_hwfns > 1)
1168                 hw_mode |= 1 << MODE_100G;
1169
1170         p_hwfn->hw_info.hw_mode = hw_mode;
1171
1172         DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP),
1173                    "Configuring function for hw_mode: 0x%08x\n",
1174                    p_hwfn->hw_info.hw_mode);
1175
1176         return 0;
1177 }
1178
1179 /* Init run time data for all PFs on an engine. */
1180 static void qed_init_cau_rt_data(struct qed_dev *cdev)
1181 {
1182         u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET;
1183         int i, igu_sb_id;
1184
1185         for_each_hwfn(cdev, i) {
1186                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1187                 struct qed_igu_info *p_igu_info;
1188                 struct qed_igu_block *p_block;
1189                 struct cau_sb_entry sb_entry;
1190
1191                 p_igu_info = p_hwfn->hw_info.p_igu_info;
1192
1193                 for (igu_sb_id = 0;
1194                      igu_sb_id < QED_MAPPING_MEMORY_SIZE(cdev); igu_sb_id++) {
1195                         p_block = &p_igu_info->entry[igu_sb_id];
1196
1197                         if (!p_block->is_pf)
1198                                 continue;
1199
1200                         qed_init_cau_sb_entry(p_hwfn, &sb_entry,
1201                                               p_block->function_id, 0, 0);
1202                         STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2,
1203                                          sb_entry);
1204                 }
1205         }
1206 }
1207
1208 static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn,
1209                                      struct qed_ptt *p_ptt)
1210 {
1211         u32 val, wr_mbs, cache_line_size;
1212
1213         val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
1214         switch (val) {
1215         case 0:
1216                 wr_mbs = 128;
1217                 break;
1218         case 1:
1219                 wr_mbs = 256;
1220                 break;
1221         case 2:
1222                 wr_mbs = 512;
1223                 break;
1224         default:
1225                 DP_INFO(p_hwfn,
1226                         "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1227                         val);
1228                 return;
1229         }
1230
1231         cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs);
1232         switch (cache_line_size) {
1233         case 32:
1234                 val = 0;
1235                 break;
1236         case 64:
1237                 val = 1;
1238                 break;
1239         case 128:
1240                 val = 2;
1241                 break;
1242         case 256:
1243                 val = 3;
1244                 break;
1245         default:
1246                 DP_INFO(p_hwfn,
1247                         "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n",
1248                         cache_line_size);
1249         }
1250
1251         if (L1_CACHE_BYTES > wr_mbs)
1252                 DP_INFO(p_hwfn,
1253                         "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n",
1254                         L1_CACHE_BYTES, wr_mbs);
1255
1256         STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);
1257         if (val > 0) {
1258                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);
1259                 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);
1260         }
1261 }
1262
1263 static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
1264                               struct qed_ptt *p_ptt, int hw_mode)
1265 {
1266         struct qed_qm_info *qm_info = &p_hwfn->qm_info;
1267         struct qed_qm_common_rt_init_params params;
1268         struct qed_dev *cdev = p_hwfn->cdev;
1269         u8 vf_id, max_num_vfs;
1270         u16 num_pfs, pf_id;
1271         u32 concrete_fid;
1272         int rc = 0;
1273
1274         qed_init_cau_rt_data(cdev);
1275
1276         /* Program GTT windows */
1277         qed_gtt_init(p_hwfn);
1278
1279         if (p_hwfn->mcp_info) {
1280                 if (p_hwfn->mcp_info->func_info.bandwidth_max)
1281                         qm_info->pf_rl_en = true;
1282                 if (p_hwfn->mcp_info->func_info.bandwidth_min)
1283                         qm_info->pf_wfq_en = true;
1284         }
1285
1286         memset(&params, 0, sizeof(params));
1287         params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine;
1288         params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;
1289         params.pf_rl_en = qm_info->pf_rl_en;
1290         params.pf_wfq_en = qm_info->pf_wfq_en;
1291         params.vport_rl_en = qm_info->vport_rl_en;
1292         params.vport_wfq_en = qm_info->vport_wfq_en;
1293         params.port_params = qm_info->qm_port_params;
1294
1295         qed_qm_common_rt_init(p_hwfn, &params);
1296
1297         qed_cxt_hw_init_common(p_hwfn);
1298
1299         qed_init_cache_line_size(p_hwfn, p_ptt);
1300
1301         rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode);
1302         if (rc)
1303                 return rc;
1304
1305         qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0);
1306         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1);
1307
1308         if (QED_IS_BB(p_hwfn->cdev)) {
1309                 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev);
1310                 for (pf_id = 0; pf_id < num_pfs; pf_id++) {
1311                         qed_fid_pretend(p_hwfn, p_ptt, pf_id);
1312                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1313                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1314                 }
1315                 /* pretend to original PF */
1316                 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1317         }
1318
1319         max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB;
1320         for (vf_id = 0; vf_id < max_num_vfs; vf_id++) {
1321                 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
1322                 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
1323                 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
1324                 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
1325                 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
1326                 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
1327         }
1328         /* pretend to original PF */
1329         qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
1330
1331         return rc;
1332 }
1333
1334 static int
1335 qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn,
1336                      struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus)
1337 {
1338         u32 dpi_bit_shift, dpi_count, dpi_page_size;
1339         u32 min_dpis;
1340         u32 n_wids;
1341
1342         /* Calculate DPI size */
1343         n_wids = max_t(u32, QED_MIN_WIDS, n_cpus);
1344         dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids);
1345         dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
1346         dpi_bit_shift = ilog2(dpi_page_size / 4096);
1347         dpi_count = pwm_region_size / dpi_page_size;
1348
1349         min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis;
1350         min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis);
1351
1352         p_hwfn->dpi_size = dpi_page_size;
1353         p_hwfn->dpi_count = dpi_count;
1354
1355         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift);
1356
1357         if (dpi_count < min_dpis)
1358                 return -EINVAL;
1359
1360         return 0;
1361 }
1362
1363 enum QED_ROCE_EDPM_MODE {
1364         QED_ROCE_EDPM_MODE_ENABLE = 0,
1365         QED_ROCE_EDPM_MODE_FORCE_ON = 1,
1366         QED_ROCE_EDPM_MODE_DISABLE = 2,
1367 };
1368
1369 static int
1370 qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1371 {
1372         u32 pwm_regsize, norm_regsize;
1373         u32 non_pwm_conn, min_addr_reg1;
1374         u32 db_bar_size, n_cpus = 1;
1375         u32 roce_edpm_mode;
1376         u32 pf_dems_shift;
1377         int rc = 0;
1378         u8 cond;
1379
1380         db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1);
1381         if (p_hwfn->cdev->num_hwfns > 1)
1382                 db_bar_size /= 2;
1383
1384         /* Calculate doorbell regions */
1385         non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) +
1386                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE,
1387                                                    NULL) +
1388                        qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
1389                                                    NULL);
1390         norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE);
1391         min_addr_reg1 = norm_regsize / 4096;
1392         pwm_regsize = db_bar_size - norm_regsize;
1393
1394         /* Check that the normal and PWM sizes are valid */
1395         if (db_bar_size < norm_regsize) {
1396                 DP_ERR(p_hwfn->cdev,
1397                        "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n",
1398                        db_bar_size, norm_regsize);
1399                 return -EINVAL;
1400         }
1401
1402         if (pwm_regsize < QED_MIN_PWM_REGION) {
1403                 DP_ERR(p_hwfn->cdev,
1404                        "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n",
1405                        pwm_regsize,
1406                        QED_MIN_PWM_REGION, db_bar_size, norm_regsize);
1407                 return -EINVAL;
1408         }
1409
1410         /* Calculate number of DPIs */
1411         roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode;
1412         if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) ||
1413             ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) {
1414                 /* Either EDPM is mandatory, or we are attempting to allocate a
1415                  * WID per CPU.
1416                  */
1417                 n_cpus = num_present_cpus();
1418                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1419         }
1420
1421         cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) ||
1422                (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE);
1423         if (cond || p_hwfn->dcbx_no_edpm) {
1424                 /* Either EDPM is disabled from user configuration, or it is
1425                  * disabled via DCBx, or it is not mandatory and we failed to
1426                  * allocated a WID per CPU.
1427                  */
1428                 n_cpus = 1;
1429                 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus);
1430
1431                 if (cond)
1432                         qed_rdma_dpm_bar(p_hwfn, p_ptt);
1433         }
1434
1435         p_hwfn->wid_count = (u16) n_cpus;
1436
1437         DP_INFO(p_hwfn,
1438                 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n",
1439                 norm_regsize,
1440                 pwm_regsize,
1441                 p_hwfn->dpi_size,
1442                 p_hwfn->dpi_count,
1443                 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ?
1444                 "disabled" : "enabled");
1445
1446         if (rc) {
1447                 DP_ERR(p_hwfn,
1448                        "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n",
1449                        p_hwfn->dpi_count,
1450                        p_hwfn->pf_params.rdma_pf_params.min_dpis);
1451                 return -EINVAL;
1452         }
1453
1454         p_hwfn->dpi_start_offset = norm_regsize;
1455
1456         /* DEMS size is configured log2 of DWORDs, hence the division by 4 */
1457         pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4);
1458         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift);
1459         qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1);
1460
1461         return 0;
1462 }
1463
1464 static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
1465                             struct qed_ptt *p_ptt, int hw_mode)
1466 {
1467         int rc = 0;
1468
1469         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode);
1470         if (rc)
1471                 return rc;
1472
1473         qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0);
1474
1475         return 0;
1476 }
1477
1478 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
1479                           struct qed_ptt *p_ptt,
1480                           struct qed_tunnel_info *p_tunn,
1481                           int hw_mode,
1482                           bool b_hw_start,
1483                           enum qed_int_mode int_mode,
1484                           bool allow_npar_tx_switch)
1485 {
1486         u8 rel_pf_id = p_hwfn->rel_pf_id;
1487         int rc = 0;
1488
1489         if (p_hwfn->mcp_info) {
1490                 struct qed_mcp_function_info *p_info;
1491
1492                 p_info = &p_hwfn->mcp_info->func_info;
1493                 if (p_info->bandwidth_min)
1494                         p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min;
1495
1496                 /* Update rate limit once we'll actually have a link */
1497                 p_hwfn->qm_info.pf_rl = 100000;
1498         }
1499
1500         qed_cxt_hw_init_pf(p_hwfn, p_ptt);
1501
1502         qed_int_igu_init_rt(p_hwfn);
1503
1504         /* Set VLAN in NIG if needed */
1505         if (hw_mode & BIT(MODE_MF_SD)) {
1506                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n");
1507                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
1508                 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
1509                              p_hwfn->hw_info.ovlan);
1510         }
1511
1512         /* Enable classification by MAC if needed */
1513         if (hw_mode & BIT(MODE_MF_SI)) {
1514                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
1515                            "Configuring TAGMAC_CLS_TYPE\n");
1516                 STORE_RT_REG(p_hwfn,
1517                              NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1);
1518         }
1519
1520         /* Protocol Configuration */
1521         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,
1522                      (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0);
1523         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,
1524                      (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0);
1525         STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);
1526
1527         /* Cleanup chip from previous driver if such remains exist */
1528         rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false);
1529         if (rc)
1530                 return rc;
1531
1532         /* Sanity check before the PF init sequence that uses DMAE */
1533         rc = qed_dmae_sanity(p_hwfn, p_ptt, "pf_phase");
1534         if (rc)
1535                 return rc;
1536
1537         /* PF Init sequence */
1538         rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode);
1539         if (rc)
1540                 return rc;
1541
1542         /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
1543         rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode);
1544         if (rc)
1545                 return rc;
1546
1547         /* Pure runtime initializations - directly to the HW  */
1548         qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
1549
1550         rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
1551         if (rc)
1552                 return rc;
1553
1554         if (b_hw_start) {
1555                 /* enable interrupts */
1556                 qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
1557
1558                 /* send function start command */
1559                 rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn,
1560                                      p_hwfn->cdev->mf_mode,
1561                                      allow_npar_tx_switch);
1562                 if (rc) {
1563                         DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
1564                         return rc;
1565                 }
1566                 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) {
1567                         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2));
1568                         qed_wr(p_hwfn, p_ptt,
1569                                PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST,
1570                                0x100);
1571                 }
1572         }
1573         return rc;
1574 }
1575
1576 static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn,
1577                                struct qed_ptt *p_ptt,
1578                                u8 enable)
1579 {
1580         u32 delay_idx = 0, val, set_val = enable ? 1 : 0;
1581
1582         /* Change PF in PXP */
1583         qed_wr(p_hwfn, p_ptt,
1584                PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val);
1585
1586         /* wait until value is set - try for 1 second every 50us */
1587         for (delay_idx = 0; delay_idx < 20000; delay_idx++) {
1588                 val = qed_rd(p_hwfn, p_ptt,
1589                              PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1590                 if (val == set_val)
1591                         break;
1592
1593                 usleep_range(50, 60);
1594         }
1595
1596         if (val != set_val) {
1597                 DP_NOTICE(p_hwfn,
1598                           "PFID_ENABLE_MASTER wasn't changed after a second\n");
1599                 return -EAGAIN;
1600         }
1601
1602         return 0;
1603 }
1604
1605 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn,
1606                                 struct qed_ptt *p_main_ptt)
1607 {
1608         /* Read shadow of current MFW mailbox */
1609         qed_mcp_read_mb(p_hwfn, p_main_ptt);
1610         memcpy(p_hwfn->mcp_info->mfw_mb_shadow,
1611                p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length);
1612 }
1613
1614 static void
1615 qed_fill_load_req_params(struct qed_load_req_params *p_load_req,
1616                          struct qed_drv_load_params *p_drv_load)
1617 {
1618         memset(p_load_req, 0, sizeof(*p_load_req));
1619
1620         p_load_req->drv_role = p_drv_load->is_crash_kernel ?
1621                                QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS;
1622         p_load_req->timeout_val = p_drv_load->mfw_timeout_val;
1623         p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset;
1624         p_load_req->override_force_load = p_drv_load->override_force_load;
1625 }
1626
1627 static int qed_vf_start(struct qed_hwfn *p_hwfn,
1628                         struct qed_hw_init_params *p_params)
1629 {
1630         if (p_params->p_tunn) {
1631                 qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn);
1632                 qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn);
1633         }
1634
1635         p_hwfn->b_int_enabled = true;
1636
1637         return 0;
1638 }
1639
1640 int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
1641 {
1642         struct qed_load_req_params load_req_params;
1643         u32 load_code, param, drv_mb_param;
1644         bool b_default_mtu = true;
1645         struct qed_hwfn *p_hwfn;
1646         int rc = 0, mfw_rc, i;
1647
1648         if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
1649                 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
1650                 return -EINVAL;
1651         }
1652
1653         if (IS_PF(cdev)) {
1654                 rc = qed_init_fw_data(cdev, p_params->bin_fw_data);
1655                 if (rc)
1656                         return rc;
1657         }
1658
1659         for_each_hwfn(cdev, i) {
1660                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
1661
1662                 /* If management didn't provide a default, set one of our own */
1663                 if (!p_hwfn->hw_info.mtu) {
1664                         p_hwfn->hw_info.mtu = 1500;
1665                         b_default_mtu = false;
1666                 }
1667
1668                 if (IS_VF(cdev)) {
1669                         qed_vf_start(p_hwfn, p_params);
1670                         continue;
1671                 }
1672
1673                 /* Enable DMAE in PXP */
1674                 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
1675
1676                 rc = qed_calc_hw_mode(p_hwfn);
1677                 if (rc)
1678                         return rc;
1679
1680                 qed_fill_load_req_params(&load_req_params,
1681                                          p_params->p_drv_load_params);
1682                 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
1683                                       &load_req_params);
1684                 if (rc) {
1685                         DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n");
1686                         return rc;
1687                 }
1688
1689                 load_code = load_req_params.load_code;
1690                 DP_VERBOSE(p_hwfn, QED_MSG_SP,
1691                            "Load request was sent. Load code: 0x%x\n",
1692                            load_code);
1693
1694                 qed_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt);
1695
1696                 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt);
1697
1698                 p_hwfn->first_on_engine = (load_code ==
1699                                            FW_MSG_CODE_DRV_LOAD_ENGINE);
1700
1701                 switch (load_code) {
1702                 case FW_MSG_CODE_DRV_LOAD_ENGINE:
1703                         rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
1704                                                 p_hwfn->hw_info.hw_mode);
1705                         if (rc)
1706                                 break;
1707                 /* Fall into */
1708                 case FW_MSG_CODE_DRV_LOAD_PORT:
1709                         rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt,
1710                                               p_hwfn->hw_info.hw_mode);
1711                         if (rc)
1712                                 break;
1713
1714                 /* Fall into */
1715                 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1716                         rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
1717                                             p_params->p_tunn,
1718                                             p_hwfn->hw_info.hw_mode,
1719                                             p_params->b_hw_start,
1720                                             p_params->int_mode,
1721                                             p_params->allow_npar_tx_switch);
1722                         break;
1723                 default:
1724                         DP_NOTICE(p_hwfn,
1725                                   "Unexpected load code [0x%08x]", load_code);
1726                         rc = -EINVAL;
1727                         break;
1728                 }
1729
1730                 if (rc)
1731                         DP_NOTICE(p_hwfn,
1732                                   "init phase failed for loadcode 0x%x (rc %d)\n",
1733                                    load_code, rc);
1734
1735                 /* ACK mfw regardless of success or failure of initialization */
1736                 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1737                                      DRV_MSG_CODE_LOAD_DONE,
1738                                      0, &load_code, &param);
1739                 if (rc)
1740                         return rc;
1741                 if (mfw_rc) {
1742                         DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n");
1743                         return mfw_rc;
1744                 }
1745
1746                 /* Check if there is a DID mismatch between nvm-cfg/efuse */
1747                 if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
1748                         DP_NOTICE(p_hwfn,
1749                                   "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
1750
1751                 /* send DCBX attention request command */
1752                 DP_VERBOSE(p_hwfn,
1753                            QED_MSG_DCB,
1754                            "sending phony dcbx set command to trigger DCBx attention handling\n");
1755                 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1756                                      DRV_MSG_CODE_SET_DCBX,
1757                                      1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT,
1758                                      &load_code, &param);
1759                 if (mfw_rc) {
1760                         DP_NOTICE(p_hwfn,
1761                                   "Failed to send DCBX attention request\n");
1762                         return mfw_rc;
1763                 }
1764
1765                 p_hwfn->hw_init_done = true;
1766         }
1767
1768         if (IS_PF(cdev)) {
1769                 p_hwfn = QED_LEADING_HWFN(cdev);
1770                 drv_mb_param = STORM_FW_VERSION;
1771                 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
1772                                  DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER,
1773                                  drv_mb_param, &load_code, &param);
1774                 if (rc)
1775                         DP_INFO(p_hwfn, "Failed to update firmware version\n");
1776
1777                 if (!b_default_mtu) {
1778                         rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt,
1779                                                    p_hwfn->hw_info.mtu);
1780                         if (rc)
1781                                 DP_INFO(p_hwfn,
1782                                         "Failed to update default mtu\n");
1783                 }
1784
1785                 rc = qed_mcp_ov_update_driver_state(p_hwfn,
1786                                                     p_hwfn->p_main_ptt,
1787                                                   QED_OV_DRIVER_STATE_DISABLED);
1788                 if (rc)
1789                         DP_INFO(p_hwfn, "Failed to update driver state\n");
1790
1791                 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt,
1792                                                QED_OV_ESWITCH_VEB);
1793                 if (rc)
1794                         DP_INFO(p_hwfn, "Failed to update eswitch mode\n");
1795         }
1796
1797         return 0;
1798 }
1799
1800 #define QED_HW_STOP_RETRY_LIMIT (10)
1801 static void qed_hw_timers_stop(struct qed_dev *cdev,
1802                                struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1803 {
1804         int i;
1805
1806         /* close timers */
1807         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0);
1808         qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0);
1809
1810         for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) {
1811                 if ((!qed_rd(p_hwfn, p_ptt,
1812                              TM_REG_PF_SCAN_ACTIVE_CONN)) &&
1813                     (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
1814                         break;
1815
1816                 /* Dependent on number of connection/tasks, possibly
1817                  * 1ms sleep is required between polls
1818                  */
1819                 usleep_range(1000, 2000);
1820         }
1821
1822         if (i < QED_HW_STOP_RETRY_LIMIT)
1823                 return;
1824
1825         DP_NOTICE(p_hwfn,
1826                   "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1827                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
1828                   (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
1829 }
1830
1831 void qed_hw_timers_stop_all(struct qed_dev *cdev)
1832 {
1833         int j;
1834
1835         for_each_hwfn(cdev, j) {
1836                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1837                 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt;
1838
1839                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1840         }
1841 }
1842
1843 int qed_hw_stop(struct qed_dev *cdev)
1844 {
1845         struct qed_hwfn *p_hwfn;
1846         struct qed_ptt *p_ptt;
1847         int rc, rc2 = 0;
1848         int j;
1849
1850         for_each_hwfn(cdev, j) {
1851                 p_hwfn = &cdev->hwfns[j];
1852                 p_ptt = p_hwfn->p_main_ptt;
1853
1854                 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");
1855
1856                 if (IS_VF(cdev)) {
1857                         qed_vf_pf_int_cleanup(p_hwfn);
1858                         rc = qed_vf_pf_reset(p_hwfn);
1859                         if (rc) {
1860                                 DP_NOTICE(p_hwfn,
1861                                           "qed_vf_pf_reset failed. rc = %d.\n",
1862                                           rc);
1863                                 rc2 = -EINVAL;
1864                         }
1865                         continue;
1866                 }
1867
1868                 /* mark the hw as uninitialized... */
1869                 p_hwfn->hw_init_done = false;
1870
1871                 /* Send unload command to MCP */
1872                 rc = qed_mcp_unload_req(p_hwfn, p_ptt);
1873                 if (rc) {
1874                         DP_NOTICE(p_hwfn,
1875                                   "Failed sending a UNLOAD_REQ command. rc = %d.\n",
1876                                   rc);
1877                         rc2 = -EINVAL;
1878                 }
1879
1880                 qed_slowpath_irq_sync(p_hwfn);
1881
1882                 /* After this point no MFW attentions are expected, e.g. prevent
1883                  * race between pf stop and dcbx pf update.
1884                  */
1885                 rc = qed_sp_pf_stop(p_hwfn);
1886                 if (rc) {
1887                         DP_NOTICE(p_hwfn,
1888                                   "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n",
1889                                   rc);
1890                         rc2 = -EINVAL;
1891                 }
1892
1893                 qed_wr(p_hwfn, p_ptt,
1894                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1895
1896                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1897                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1898                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1899                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1900                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1901
1902                 qed_hw_timers_stop(cdev, p_hwfn, p_ptt);
1903
1904                 /* Disable Attention Generation */
1905                 qed_int_igu_disable_int(p_hwfn, p_ptt);
1906
1907                 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0);
1908                 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0);
1909
1910                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true);
1911
1912                 /* Need to wait 1ms to guarantee SBs are cleared */
1913                 usleep_range(1000, 2000);
1914
1915                 /* Disable PF in HW blocks */
1916                 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0);
1917                 qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0);
1918
1919                 qed_mcp_unload_done(p_hwfn, p_ptt);
1920                 if (rc) {
1921                         DP_NOTICE(p_hwfn,
1922                                   "Failed sending a UNLOAD_DONE command. rc = %d.\n",
1923                                   rc);
1924                         rc2 = -EINVAL;
1925                 }
1926         }
1927
1928         if (IS_PF(cdev)) {
1929                 p_hwfn = QED_LEADING_HWFN(cdev);
1930                 p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt;
1931
1932                 /* Disable DMAE in PXP - in CMT, this should only be done for
1933                  * first hw-function, and only after all transactions have
1934                  * stopped for all active hw-functions.
1935                  */
1936                 rc = qed_change_pci_hwfn(p_hwfn, p_ptt, false);
1937                 if (rc) {
1938                         DP_NOTICE(p_hwfn,
1939                                   "qed_change_pci_hwfn failed. rc = %d.\n", rc);
1940                         rc2 = -EINVAL;
1941                 }
1942         }
1943
1944         return rc2;
1945 }
1946
1947 int qed_hw_stop_fastpath(struct qed_dev *cdev)
1948 {
1949         int j;
1950
1951         for_each_hwfn(cdev, j) {
1952                 struct qed_hwfn *p_hwfn = &cdev->hwfns[j];
1953                 struct qed_ptt *p_ptt;
1954
1955                 if (IS_VF(cdev)) {
1956                         qed_vf_pf_int_cleanup(p_hwfn);
1957                         continue;
1958                 }
1959                 p_ptt = qed_ptt_acquire(p_hwfn);
1960                 if (!p_ptt)
1961                         return -EAGAIN;
1962
1963                 DP_VERBOSE(p_hwfn,
1964                            NETIF_MSG_IFDOWN, "Shutting down the fastpath\n");
1965
1966                 qed_wr(p_hwfn, p_ptt,
1967                        NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1);
1968
1969                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0);
1970                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0);
1971                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0);
1972                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0);
1973                 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0);
1974
1975                 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false);
1976
1977                 /* Need to wait 1ms to guarantee SBs are cleared */
1978                 usleep_range(1000, 2000);
1979                 qed_ptt_release(p_hwfn, p_ptt);
1980         }
1981
1982         return 0;
1983 }
1984
1985 int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn)
1986 {
1987         struct qed_ptt *p_ptt;
1988
1989         if (IS_VF(p_hwfn->cdev))
1990                 return 0;
1991
1992         p_ptt = qed_ptt_acquire(p_hwfn);
1993         if (!p_ptt)
1994                 return -EAGAIN;
1995
1996         /* If roce info is allocated it means roce is initialized and should
1997          * be enabled in searcher.
1998          */
1999         if (p_hwfn->p_rdma_info &&
2000             p_hwfn->b_rdma_enabled_in_prs)
2001                 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1);
2002
2003         /* Re-open incoming traffic */
2004         qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0);
2005         qed_ptt_release(p_hwfn, p_ptt);
2006
2007         return 0;
2008 }
2009
2010 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
2011 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn)
2012 {
2013         qed_ptt_pool_free(p_hwfn);
2014         kfree(p_hwfn->hw_info.p_igu_info);
2015         p_hwfn->hw_info.p_igu_info = NULL;
2016 }
2017
2018 /* Setup bar access */
2019 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn)
2020 {
2021         /* clear indirect access */
2022         if (QED_IS_AH(p_hwfn->cdev)) {
2023                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2024                        PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0);
2025                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2026                        PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0);
2027                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2028                        PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0);
2029                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2030                        PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0);
2031         } else {
2032                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2033                        PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0);
2034                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2035                        PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0);
2036                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2037                        PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0);
2038                 qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2039                        PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0);
2040         }
2041
2042         /* Clean Previous errors if such exist */
2043         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2044                PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id);
2045
2046         /* enable internal target-read */
2047         qed_wr(p_hwfn, p_hwfn->p_main_ptt,
2048                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
2049 }
2050
2051 static void get_function_id(struct qed_hwfn *p_hwfn)
2052 {
2053         /* ME Register */
2054         p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,
2055                                                   PXP_PF_ME_OPAQUE_ADDR);
2056
2057         p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);
2058
2059         p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf;
2060         p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2061                                       PXP_CONCRETE_FID_PFID);
2062         p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid,
2063                                     PXP_CONCRETE_FID_PORT);
2064
2065         DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
2066                    "Read ME register: Concrete 0x%08x Opaque 0x%04x\n",
2067                    p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid);
2068 }
2069
2070 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
2071 {
2072         u32 *feat_num = p_hwfn->hw_info.feat_num;
2073         struct qed_sb_cnt_info sb_cnt;
2074         u32 non_l2_sbs = 0;
2075
2076         memset(&sb_cnt, 0, sizeof(sb_cnt));
2077         qed_int_get_num_sbs(p_hwfn, &sb_cnt);
2078
2079         if (IS_ENABLED(CONFIG_QED_RDMA) &&
2080             QED_IS_RDMA_PERSONALITY(p_hwfn)) {
2081                 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide
2082                  * the status blocks equally between L2 / RoCE but with
2083                  * consideration as to how many l2 queues / cnqs we have.
2084                  */
2085                 feat_num[QED_RDMA_CNQ] =
2086                         min_t(u32, sb_cnt.cnt / 2,
2087                               RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM));
2088
2089                 non_l2_sbs = feat_num[QED_RDMA_CNQ];
2090         }
2091         if (QED_IS_L2_PERSONALITY(p_hwfn)) {
2092                 /* Start by allocating VF queues, then PF's */
2093                 feat_num[QED_VF_L2_QUE] = min_t(u32,
2094                                                 RESC_NUM(p_hwfn, QED_L2_QUEUE),
2095                                                 sb_cnt.iov_cnt);
2096                 feat_num[QED_PF_L2_QUE] = min_t(u32,
2097                                                 sb_cnt.cnt - non_l2_sbs,
2098                                                 RESC_NUM(p_hwfn,
2099                                                          QED_L2_QUEUE) -
2100                                                 FEAT_NUM(p_hwfn,
2101                                                          QED_VF_L2_QUE));
2102         }
2103
2104         if (QED_IS_FCOE_PERSONALITY(p_hwfn))
2105                 feat_num[QED_FCOE_CQ] =  min_t(u32, sb_cnt.cnt,
2106                                                RESC_NUM(p_hwfn,
2107                                                         QED_CMDQS_CQS));
2108
2109         if (QED_IS_ISCSI_PERSONALITY(p_hwfn))
2110                 feat_num[QED_ISCSI_CQ] = min_t(u32, sb_cnt.cnt,
2111                                                RESC_NUM(p_hwfn,
2112                                                         QED_CMDQS_CQS));
2113         DP_VERBOSE(p_hwfn,
2114                    NETIF_MSG_PROBE,
2115                    "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d FCOE_CQ=%d ISCSI_CQ=%d #SBS=%d\n",
2116                    (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE),
2117                    (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE),
2118                    (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ),
2119                    (int)FEAT_NUM(p_hwfn, QED_FCOE_CQ),
2120                    (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ),
2121                    (int)sb_cnt.cnt);
2122 }
2123
2124 const char *qed_hw_get_resc_name(enum qed_resources res_id)
2125 {
2126         switch (res_id) {
2127         case QED_L2_QUEUE:
2128                 return "L2_QUEUE";
2129         case QED_VPORT:
2130                 return "VPORT";
2131         case QED_RSS_ENG:
2132                 return "RSS_ENG";
2133         case QED_PQ:
2134                 return "PQ";
2135         case QED_RL:
2136                 return "RL";
2137         case QED_MAC:
2138                 return "MAC";
2139         case QED_VLAN:
2140                 return "VLAN";
2141         case QED_RDMA_CNQ_RAM:
2142                 return "RDMA_CNQ_RAM";
2143         case QED_ILT:
2144                 return "ILT";
2145         case QED_LL2_QUEUE:
2146                 return "LL2_QUEUE";
2147         case QED_CMDQS_CQS:
2148                 return "CMDQS_CQS";
2149         case QED_RDMA_STATS_QUEUE:
2150                 return "RDMA_STATS_QUEUE";
2151         case QED_BDQ:
2152                 return "BDQ";
2153         case QED_SB:
2154                 return "SB";
2155         default:
2156                 return "UNKNOWN_RESOURCE";
2157         }
2158 }
2159
2160 static int
2161 __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn,
2162                             struct qed_ptt *p_ptt,
2163                             enum qed_resources res_id,
2164                             u32 resc_max_val, u32 *p_mcp_resp)
2165 {
2166         int rc;
2167
2168         rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id,
2169                                       resc_max_val, p_mcp_resp);
2170         if (rc) {
2171                 DP_NOTICE(p_hwfn,
2172                           "MFW response failure for a max value setting of resource %d [%s]\n",
2173                           res_id, qed_hw_get_resc_name(res_id));
2174                 return rc;
2175         }
2176
2177         if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK)
2178                 DP_INFO(p_hwfn,
2179                         "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n",
2180                         res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp);
2181
2182         return 0;
2183 }
2184
2185 static int
2186 qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2187 {
2188         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2189         u32 resc_max_val, mcp_resp;
2190         u8 res_id;
2191         int rc;
2192
2193         for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2194                 switch (res_id) {
2195                 case QED_LL2_QUEUE:
2196                         resc_max_val = MAX_NUM_LL2_RX_QUEUES;
2197                         break;
2198                 case QED_RDMA_CNQ_RAM:
2199                         /* No need for a case for QED_CMDQS_CQS since
2200                          * CNQ/CMDQS are the same resource.
2201                          */
2202                         resc_max_val = NUM_OF_GLOBAL_QUEUES;
2203                         break;
2204                 case QED_RDMA_STATS_QUEUE:
2205                         resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2
2206                             : RDMA_NUM_STATISTIC_COUNTERS_BB;
2207                         break;
2208                 case QED_BDQ:
2209                         resc_max_val = BDQ_NUM_RESOURCES;
2210                         break;
2211                 default:
2212                         continue;
2213                 }
2214
2215                 rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id,
2216                                                  resc_max_val, &mcp_resp);
2217                 if (rc)
2218                         return rc;
2219
2220                 /* There's no point to continue to the next resource if the
2221                  * command is not supported by the MFW.
2222                  * We do continue if the command is supported but the resource
2223                  * is unknown to the MFW. Such a resource will be later
2224                  * configured with the default allocation values.
2225                  */
2226                 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED)
2227                         return -EINVAL;
2228         }
2229
2230         return 0;
2231 }
2232
2233 static
2234 int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn,
2235                          enum qed_resources res_id,
2236                          u32 *p_resc_num, u32 *p_resc_start)
2237 {
2238         u8 num_funcs = p_hwfn->num_funcs_on_engine;
2239         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2240
2241         switch (res_id) {
2242         case QED_L2_QUEUE:
2243                 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
2244                                MAX_NUM_L2_QUEUES_BB) / num_funcs;
2245                 break;
2246         case QED_VPORT:
2247                 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
2248                                MAX_NUM_VPORTS_BB) / num_funcs;
2249                 break;
2250         case QED_RSS_ENG:
2251                 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
2252                                ETH_RSS_ENGINE_NUM_BB) / num_funcs;
2253                 break;
2254         case QED_PQ:
2255                 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
2256                                MAX_QM_TX_QUEUES_BB) / num_funcs;
2257                 *p_resc_num &= ~0x7;    /* The granularity of the PQs is 8 */
2258                 break;
2259         case QED_RL:
2260                 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
2261                 break;
2262         case QED_MAC:
2263         case QED_VLAN:
2264                 /* Each VFC resource can accommodate both a MAC and a VLAN */
2265                 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
2266                 break;
2267         case QED_ILT:
2268                 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
2269                                PXP_NUM_ILT_RECORDS_BB) / num_funcs;
2270                 break;
2271         case QED_LL2_QUEUE:
2272                 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs;
2273                 break;
2274         case QED_RDMA_CNQ_RAM:
2275         case QED_CMDQS_CQS:
2276                 /* CNQ/CMDQS are the same resource */
2277                 *p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs;
2278                 break;
2279         case QED_RDMA_STATS_QUEUE:
2280                 *p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 :
2281                                RDMA_NUM_STATISTIC_COUNTERS_BB) / num_funcs;
2282                 break;
2283         case QED_BDQ:
2284                 if (p_hwfn->hw_info.personality != QED_PCI_ISCSI &&
2285                     p_hwfn->hw_info.personality != QED_PCI_FCOE)
2286                         *p_resc_num = 0;
2287                 else
2288                         *p_resc_num = 1;
2289                 break;
2290         case QED_SB:
2291                 /* Since we want its value to reflect whether MFW supports
2292                  * the new scheme, have a default of 0.
2293                  */
2294                 *p_resc_num = 0;
2295                 break;
2296         default:
2297                 return -EINVAL;
2298         }
2299
2300         switch (res_id) {
2301         case QED_BDQ:
2302                 if (!*p_resc_num)
2303                         *p_resc_start = 0;
2304                 else if (p_hwfn->cdev->num_ports_in_engine == 4)
2305                         *p_resc_start = p_hwfn->port_id;
2306                 else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI)
2307                         *p_resc_start = p_hwfn->port_id;
2308                 else if (p_hwfn->hw_info.personality == QED_PCI_FCOE)
2309                         *p_resc_start = p_hwfn->port_id + 2;
2310                 break;
2311         default:
2312                 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx;
2313                 break;
2314         }
2315
2316         return 0;
2317 }
2318
2319 static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn,
2320                                   enum qed_resources res_id)
2321 {
2322         u32 dflt_resc_num = 0, dflt_resc_start = 0;
2323         u32 mcp_resp, *p_resc_num, *p_resc_start;
2324         int rc;
2325
2326         p_resc_num = &RESC_NUM(p_hwfn, res_id);
2327         p_resc_start = &RESC_START(p_hwfn, res_id);
2328
2329         rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num,
2330                                   &dflt_resc_start);
2331         if (rc) {
2332                 DP_ERR(p_hwfn,
2333                        "Failed to get default amount for resource %d [%s]\n",
2334                        res_id, qed_hw_get_resc_name(res_id));
2335                 return rc;
2336         }
2337
2338         rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id,
2339                                    &mcp_resp, p_resc_num, p_resc_start);
2340         if (rc) {
2341                 DP_NOTICE(p_hwfn,
2342                           "MFW response failure for an allocation request for resource %d [%s]\n",
2343                           res_id, qed_hw_get_resc_name(res_id));
2344                 return rc;
2345         }
2346
2347         /* Default driver values are applied in the following cases:
2348          * - The resource allocation MB command is not supported by the MFW
2349          * - There is an internal error in the MFW while processing the request
2350          * - The resource ID is unknown to the MFW
2351          */
2352         if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2353                 DP_INFO(p_hwfn,
2354                         "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n",
2355                         res_id,
2356                         qed_hw_get_resc_name(res_id),
2357                         mcp_resp, dflt_resc_num, dflt_resc_start);
2358                 *p_resc_num = dflt_resc_num;
2359                 *p_resc_start = dflt_resc_start;
2360                 goto out;
2361         }
2362
2363 out:
2364         /* PQs have to divide by 8 [that's the HW granularity].
2365          * Reduce number so it would fit.
2366          */
2367         if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) {
2368                 DP_INFO(p_hwfn,
2369                         "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n",
2370                         *p_resc_num,
2371                         (*p_resc_num) & ~0x7,
2372                         *p_resc_start, (*p_resc_start) & ~0x7);
2373                 *p_resc_num &= ~0x7;
2374                 *p_resc_start &= ~0x7;
2375         }
2376
2377         return 0;
2378 }
2379
2380 static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn)
2381 {
2382         int rc;
2383         u8 res_id;
2384
2385         for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
2386                 rc = __qed_hw_set_resc_info(p_hwfn, res_id);
2387                 if (rc)
2388                         return rc;
2389         }
2390
2391         return 0;
2392 }
2393
2394 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2395 {
2396         struct qed_resc_unlock_params resc_unlock_params;
2397         struct qed_resc_lock_params resc_lock_params;
2398         bool b_ah = QED_IS_AH(p_hwfn->cdev);
2399         u8 res_id;
2400         int rc;
2401
2402         /* Setting the max values of the soft resources and the following
2403          * resources allocation queries should be atomic. Since several PFs can
2404          * run in parallel - a resource lock is needed.
2405          * If either the resource lock or resource set value commands are not
2406          * supported - skip the the max values setting, release the lock if
2407          * needed, and proceed to the queries. Other failures, including a
2408          * failure to acquire the lock, will cause this function to fail.
2409          */
2410         qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params,
2411                                        QED_RESC_LOCK_RESC_ALLOC, false);
2412
2413         rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params);
2414         if (rc && rc != -EINVAL) {
2415                 return rc;
2416         } else if (rc == -EINVAL) {
2417                 DP_INFO(p_hwfn,
2418                         "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n");
2419         } else if (!rc && !resc_lock_params.b_granted) {
2420                 DP_NOTICE(p_hwfn,
2421                           "Failed to acquire the resource lock for the resource allocation commands\n");
2422                 return -EBUSY;
2423         } else {
2424                 rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt);
2425                 if (rc && rc != -EINVAL) {
2426                         DP_NOTICE(p_hwfn,
2427                                   "Failed to set the max values of the soft resources\n");
2428                         goto unlock_and_exit;
2429                 } else if (rc == -EINVAL) {
2430                         DP_INFO(p_hwfn,
2431                                 "Skip the max values setting of the soft resources since it is not supported by the MFW\n");
2432                         rc = qed_mcp_resc_unlock(p_hwfn, p_ptt,
2433                                                  &resc_unlock_params);
2434                         if (rc)
2435                                 DP_INFO(p_hwfn,
2436                                         "Failed to release the resource lock for the resource allocation commands\n");
2437                 }
2438         }
2439
2440         rc = qed_hw_set_resc_info(p_hwfn);
2441         if (rc)
2442                 goto unlock_and_exit;
2443
2444         if (resc_lock_params.b_granted && !resc_unlock_params.b_released) {
2445                 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2446                 if (rc)
2447                         DP_INFO(p_hwfn,
2448                                 "Failed to release the resource lock for the resource allocation commands\n");
2449         }
2450
2451         /* Sanity for ILT */
2452         if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) ||
2453             (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) {
2454                 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n",
2455                           RESC_START(p_hwfn, QED_ILT),
2456                           RESC_END(p_hwfn, QED_ILT) - 1);
2457                 return -EINVAL;
2458         }
2459
2460         /* This will also learn the number of SBs from MFW */
2461         if (qed_int_igu_reset_cam(p_hwfn, p_ptt))
2462                 return -EINVAL;
2463
2464         qed_hw_set_feat(p_hwfn);
2465
2466         for (res_id = 0; res_id < QED_MAX_RESC; res_id++)
2467                 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n",
2468                            qed_hw_get_resc_name(res_id),
2469                            RESC_NUM(p_hwfn, res_id),
2470                            RESC_START(p_hwfn, res_id));
2471
2472         return 0;
2473
2474 unlock_and_exit:
2475         if (resc_lock_params.b_granted && !resc_unlock_params.b_released)
2476                 qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params);
2477         return rc;
2478 }
2479
2480 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2481 {
2482         u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities;
2483         u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg;
2484         struct qed_mcp_link_capabilities *p_caps;
2485         struct qed_mcp_link_params *link;
2486
2487         /* Read global nvm_cfg address */
2488         nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
2489
2490         /* Verify MCP has initialized it */
2491         if (!nvm_cfg_addr) {
2492                 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
2493                 return -EINVAL;
2494         }
2495
2496         /* Read nvm_cfg1  (Notice this is just offset, and not offsize (TBD) */
2497         nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
2498
2499         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2500                offsetof(struct nvm_cfg1, glob) +
2501                offsetof(struct nvm_cfg1_glob, core_cfg);
2502
2503         core_cfg = qed_rd(p_hwfn, p_ptt, addr);
2504
2505         switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >>
2506                 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) {
2507         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G:
2508                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G;
2509                 break;
2510         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G:
2511                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G;
2512                 break;
2513         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G:
2514                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G;
2515                 break;
2516         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F:
2517                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F;
2518                 break;
2519         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E:
2520                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E;
2521                 break;
2522         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G:
2523                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G;
2524                 break;
2525         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G:
2526                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G;
2527                 break;
2528         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G:
2529                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G;
2530                 break;
2531         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G:
2532                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G;
2533                 break;
2534         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G:
2535                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G;
2536                 break;
2537         case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G:
2538                 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G;
2539                 break;
2540         default:
2541                 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg);
2542                 break;
2543         }
2544
2545         /* Read default link configuration */
2546         link = &p_hwfn->mcp_info->link_input;
2547         p_caps = &p_hwfn->mcp_info->link_capabilities;
2548         port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2549                         offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]);
2550         link_temp = qed_rd(p_hwfn, p_ptt,
2551                            port_cfg_addr +
2552                            offsetof(struct nvm_cfg1_port, speed_cap_mask));
2553         link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK;
2554         link->speed.advertised_speeds = link_temp;
2555
2556         link_temp = link->speed.advertised_speeds;
2557         p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp;
2558
2559         link_temp = qed_rd(p_hwfn, p_ptt,
2560                            port_cfg_addr +
2561                            offsetof(struct nvm_cfg1_port, link_settings));
2562         switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >>
2563                 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) {
2564         case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG:
2565                 link->speed.autoneg = true;
2566                 break;
2567         case NVM_CFG1_PORT_DRV_LINK_SPEED_1G:
2568                 link->speed.forced_speed = 1000;
2569                 break;
2570         case NVM_CFG1_PORT_DRV_LINK_SPEED_10G:
2571                 link->speed.forced_speed = 10000;
2572                 break;
2573         case NVM_CFG1_PORT_DRV_LINK_SPEED_25G:
2574                 link->speed.forced_speed = 25000;
2575                 break;
2576         case NVM_CFG1_PORT_DRV_LINK_SPEED_40G:
2577                 link->speed.forced_speed = 40000;
2578                 break;
2579         case NVM_CFG1_PORT_DRV_LINK_SPEED_50G:
2580                 link->speed.forced_speed = 50000;
2581                 break;
2582         case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G:
2583                 link->speed.forced_speed = 100000;
2584                 break;
2585         default:
2586                 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp);
2587         }
2588
2589         p_hwfn->mcp_info->link_capabilities.default_speed_autoneg =
2590                 link->speed.autoneg;
2591
2592         link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK;
2593         link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET;
2594         link->pause.autoneg = !!(link_temp &
2595                                  NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG);
2596         link->pause.forced_rx = !!(link_temp &
2597                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX);
2598         link->pause.forced_tx = !!(link_temp &
2599                                    NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX);
2600         link->loopback_mode = 0;
2601
2602         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
2603                 link_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr +
2604                                    offsetof(struct nvm_cfg1_port, ext_phy));
2605                 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK;
2606                 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET;
2607                 p_caps->default_eee = QED_MCP_EEE_ENABLED;
2608                 link->eee.enable = true;
2609                 switch (link_temp) {
2610                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED:
2611                         p_caps->default_eee = QED_MCP_EEE_DISABLED;
2612                         link->eee.enable = false;
2613                         break;
2614                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED:
2615                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME;
2616                         break;
2617                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE:
2618                         p_caps->eee_lpi_timer =
2619                             EEE_TX_TIMER_USEC_AGGRESSIVE_TIME;
2620                         break;
2621                 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY:
2622                         p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME;
2623                         break;
2624                 }
2625
2626                 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer;
2627                 link->eee.tx_lpi_enable = link->eee.enable;
2628                 link->eee.adv_caps = QED_EEE_1G_ADV | QED_EEE_10G_ADV;
2629         } else {
2630                 p_caps->default_eee = QED_MCP_EEE_UNSUPPORTED;
2631         }
2632
2633         DP_VERBOSE(p_hwfn,
2634                    NETIF_MSG_LINK,
2635                    "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x EEE: %02x [%08x usec]\n",
2636                    link->speed.forced_speed,
2637                    link->speed.advertised_speeds,
2638                    link->speed.autoneg,
2639                    link->pause.autoneg,
2640                    p_caps->default_eee, p_caps->eee_lpi_timer);
2641
2642         /* Read Multi-function information from shmem */
2643         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2644                offsetof(struct nvm_cfg1, glob) +
2645                offsetof(struct nvm_cfg1_glob, generic_cont0);
2646
2647         generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
2648
2649         mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2650                   NVM_CFG1_GLOB_MF_MODE_OFFSET;
2651
2652         switch (mf_mode) {
2653         case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2654                 p_hwfn->cdev->mf_mode = QED_MF_OVLAN;
2655                 break;
2656         case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2657                 p_hwfn->cdev->mf_mode = QED_MF_NPAR;
2658                 break;
2659         case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2660                 p_hwfn->cdev->mf_mode = QED_MF_DEFAULT;
2661                 break;
2662         }
2663         DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2664                 p_hwfn->cdev->mf_mode);
2665
2666         /* Read Multi-function information from shmem */
2667         addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2668                 offsetof(struct nvm_cfg1, glob) +
2669                 offsetof(struct nvm_cfg1_glob, device_capabilities);
2670
2671         device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
2672         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET)
2673                 __set_bit(QED_DEV_CAP_ETH,
2674                           &p_hwfn->hw_info.device_capabilities);
2675         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE)
2676                 __set_bit(QED_DEV_CAP_FCOE,
2677                           &p_hwfn->hw_info.device_capabilities);
2678         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI)
2679                 __set_bit(QED_DEV_CAP_ISCSI,
2680                           &p_hwfn->hw_info.device_capabilities);
2681         if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE)
2682                 __set_bit(QED_DEV_CAP_ROCE,
2683                           &p_hwfn->hw_info.device_capabilities);
2684
2685         return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);
2686 }
2687
2688 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2689 {
2690         u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id;
2691         u32 reg_function_hide, tmp, eng_mask, low_pfs_mask;
2692         struct qed_dev *cdev = p_hwfn->cdev;
2693
2694         num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB;
2695
2696         /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
2697          * in the other bits are selected.
2698          * Bits 1-15 are for functions 1-15, respectively, and their value is
2699          * '0' only for enabled functions (function 0 always exists and
2700          * enabled).
2701          * In case of CMT, only the "even" functions are enabled, and thus the
2702          * number of functions for both hwfns is learnt from the same bits.
2703          */
2704         reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
2705
2706         if (reg_function_hide & 0x1) {
2707                 if (QED_IS_BB(cdev)) {
2708                         if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) {
2709                                 num_funcs = 0;
2710                                 eng_mask = 0xaaaa;
2711                         } else {
2712                                 num_funcs = 1;
2713                                 eng_mask = 0x5554;
2714                         }
2715                 } else {
2716                         num_funcs = 1;
2717                         eng_mask = 0xfffe;
2718                 }
2719
2720                 /* Get the number of the enabled functions on the engine */
2721                 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;
2722                 while (tmp) {
2723                         if (tmp & 0x1)
2724                                 num_funcs++;
2725                         tmp >>= 0x1;
2726                 }
2727
2728                 /* Get the PF index within the enabled functions */
2729                 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1;
2730                 tmp = reg_function_hide & eng_mask & low_pfs_mask;
2731                 while (tmp) {
2732                         if (tmp & 0x1)
2733                                 enabled_func_idx--;
2734                         tmp >>= 0x1;
2735                 }
2736         }
2737
2738         p_hwfn->num_funcs_on_engine = num_funcs;
2739         p_hwfn->enabled_func_idx = enabled_func_idx;
2740
2741         DP_VERBOSE(p_hwfn,
2742                    NETIF_MSG_PROBE,
2743                    "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n",
2744                    p_hwfn->rel_pf_id,
2745                    p_hwfn->abs_pf_id,
2746                    p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine);
2747 }
2748
2749 static void qed_hw_info_port_num_bb(struct qed_hwfn *p_hwfn,
2750                                     struct qed_ptt *p_ptt)
2751 {
2752         u32 port_mode;
2753
2754         port_mode = qed_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0);
2755
2756         if (port_mode < 3) {
2757                 p_hwfn->cdev->num_ports_in_engine = 1;
2758         } else if (port_mode <= 5) {
2759                 p_hwfn->cdev->num_ports_in_engine = 2;
2760         } else {
2761                 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n",
2762                           p_hwfn->cdev->num_ports_in_engine);
2763
2764                 /* Default num_ports_in_engine to something */
2765                 p_hwfn->cdev->num_ports_in_engine = 1;
2766         }
2767 }
2768
2769 static void qed_hw_info_port_num_ah(struct qed_hwfn *p_hwfn,
2770                                     struct qed_ptt *p_ptt)
2771 {
2772         u32 port;
2773         int i;
2774
2775         p_hwfn->cdev->num_ports_in_engine = 0;
2776
2777         for (i = 0; i < MAX_NUM_PORTS_K2; i++) {
2778                 port = qed_rd(p_hwfn, p_ptt,
2779                               CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4));
2780                 if (port & 1)
2781                         p_hwfn->cdev->num_ports_in_engine++;
2782         }
2783
2784         if (!p_hwfn->cdev->num_ports_in_engine) {
2785                 DP_NOTICE(p_hwfn, "All NIG ports are inactive\n");
2786
2787                 /* Default num_ports_in_engine to something */
2788                 p_hwfn->cdev->num_ports_in_engine = 1;
2789         }
2790 }
2791
2792 static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2793 {
2794         if (QED_IS_BB(p_hwfn->cdev))
2795                 qed_hw_info_port_num_bb(p_hwfn, p_ptt);
2796         else
2797                 qed_hw_info_port_num_ah(p_hwfn, p_ptt);
2798 }
2799
2800 static void qed_get_eee_caps(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2801 {
2802         struct qed_mcp_link_capabilities *p_caps;
2803         u32 eee_status;
2804
2805         p_caps = &p_hwfn->mcp_info->link_capabilities;
2806         if (p_caps->default_eee == QED_MCP_EEE_UNSUPPORTED)
2807                 return;
2808
2809         p_caps->eee_speed_caps = 0;
2810         eee_status = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
2811                             offsetof(struct public_port, eee_status));
2812         eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >>
2813                         EEE_SUPPORTED_SPEED_OFFSET;
2814
2815         if (eee_status & EEE_1G_SUPPORTED)
2816                 p_caps->eee_speed_caps |= QED_EEE_1G_ADV;
2817         if (eee_status & EEE_10G_ADV)
2818                 p_caps->eee_speed_caps |= QED_EEE_10G_ADV;
2819 }
2820
2821 static int
2822 qed_get_hw_info(struct qed_hwfn *p_hwfn,
2823                 struct qed_ptt *p_ptt,
2824                 enum qed_pci_personality personality)
2825 {
2826         int rc;
2827
2828         /* Since all information is common, only first hwfns should do this */
2829         if (IS_LEAD_HWFN(p_hwfn)) {
2830                 rc = qed_iov_hw_info(p_hwfn);
2831                 if (rc)
2832                         return rc;
2833         }
2834
2835         qed_hw_info_port_num(p_hwfn, p_ptt);
2836
2837         qed_mcp_get_capabilities(p_hwfn, p_ptt);
2838
2839         qed_hw_get_nvm_info(p_hwfn, p_ptt);
2840
2841         rc = qed_int_igu_read_cam(p_hwfn, p_ptt);
2842         if (rc)
2843                 return rc;
2844
2845         if (qed_mcp_is_init(p_hwfn))
2846                 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr,
2847                                 p_hwfn->mcp_info->func_info.mac);
2848         else
2849                 eth_random_addr(p_hwfn->hw_info.hw_mac_addr);
2850
2851         if (qed_mcp_is_init(p_hwfn)) {
2852                 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET)
2853                         p_hwfn->hw_info.ovlan =
2854                                 p_hwfn->mcp_info->func_info.ovlan;
2855
2856                 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
2857
2858                 qed_get_eee_caps(p_hwfn, p_ptt);
2859         }
2860
2861         if (qed_mcp_is_init(p_hwfn)) {
2862                 enum qed_pci_personality protocol;
2863
2864                 protocol = p_hwfn->mcp_info->func_info.protocol;
2865                 p_hwfn->hw_info.personality = protocol;
2866         }
2867
2868         p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2;
2869         p_hwfn->hw_info.num_active_tc = 1;
2870
2871         qed_get_num_funcs(p_hwfn, p_ptt);
2872
2873         if (qed_mcp_is_init(p_hwfn))
2874                 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu;
2875
2876         return qed_hw_get_resc(p_hwfn, p_ptt);
2877 }
2878
2879 static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2880 {
2881         struct qed_dev *cdev = p_hwfn->cdev;
2882         u16 device_id_mask;
2883         u32 tmp;
2884
2885         /* Read Vendor Id / Device Id */
2886         pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id);
2887         pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id);
2888
2889         /* Determine type */
2890         device_id_mask = cdev->device_id & QED_DEV_ID_MASK;
2891         switch (device_id_mask) {
2892         case QED_DEV_ID_MASK_BB:
2893                 cdev->type = QED_DEV_TYPE_BB;
2894                 break;
2895         case QED_DEV_ID_MASK_AH:
2896                 cdev->type = QED_DEV_TYPE_AH;
2897                 break;
2898         default:
2899                 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id);
2900                 return -EBUSY;
2901         }
2902
2903         cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
2904         cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
2905
2906         MASK_FIELD(CHIP_REV, cdev->chip_rev);
2907
2908         /* Learn number of HW-functions */
2909         tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
2910
2911         if (tmp & (1 << p_hwfn->rel_pf_id)) {
2912                 DP_NOTICE(cdev->hwfns, "device in CMT mode\n");
2913                 cdev->num_hwfns = 2;
2914         } else {
2915                 cdev->num_hwfns = 1;
2916         }
2917
2918         cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt,
2919                                     MISCS_REG_CHIP_TEST_REG) >> 4;
2920         MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id);
2921         cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
2922         MASK_FIELD(CHIP_METAL, cdev->chip_metal);
2923
2924         DP_INFO(cdev->hwfns,
2925                 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
2926                 QED_IS_BB(cdev) ? "BB" : "AH",
2927                 'A' + cdev->chip_rev,
2928                 (int)cdev->chip_metal,
2929                 cdev->chip_num, cdev->chip_rev,
2930                 cdev->chip_bond_id, cdev->chip_metal);
2931
2932         return 0;
2933 }
2934
2935 static void qed_nvm_info_free(struct qed_hwfn *p_hwfn)
2936 {
2937         kfree(p_hwfn->nvm_info.image_att);
2938         p_hwfn->nvm_info.image_att = NULL;
2939 }
2940
2941 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
2942                                  void __iomem *p_regview,
2943                                  void __iomem *p_doorbells,
2944                                  enum qed_pci_personality personality)
2945 {
2946         int rc = 0;
2947
2948         /* Split PCI bars evenly between hwfns */
2949         p_hwfn->regview = p_regview;
2950         p_hwfn->doorbells = p_doorbells;
2951
2952         if (IS_VF(p_hwfn->cdev))
2953                 return qed_vf_hw_prepare(p_hwfn);
2954
2955         /* Validate that chip access is feasible */
2956         if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
2957                 DP_ERR(p_hwfn,
2958                        "Reading the ME register returns all Fs; Preventing further chip access\n");
2959                 return -EINVAL;
2960         }
2961
2962         get_function_id(p_hwfn);
2963
2964         /* Allocate PTT pool */
2965         rc = qed_ptt_pool_alloc(p_hwfn);
2966         if (rc)
2967                 goto err0;
2968
2969         /* Allocate the main PTT */
2970         p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN);
2971
2972         /* First hwfn learns basic information, e.g., number of hwfns */
2973         if (!p_hwfn->my_id) {
2974                 rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt);
2975                 if (rc)
2976                         goto err1;
2977         }
2978
2979         qed_hw_hwfn_prepare(p_hwfn);
2980
2981         /* Initialize MCP structure */
2982         rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt);
2983         if (rc) {
2984                 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n");
2985                 goto err1;
2986         }
2987
2988         /* Read the device configuration information from the HW and SHMEM */
2989         rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality);
2990         if (rc) {
2991                 DP_NOTICE(p_hwfn, "Failed to get HW information\n");
2992                 goto err2;
2993         }
2994
2995         /* Sending a mailbox to the MFW should be done after qed_get_hw_info()
2996          * is called as it sets the ports number in an engine.
2997          */
2998         if (IS_LEAD_HWFN(p_hwfn)) {
2999                 rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
3000                 if (rc)
3001                         DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n");
3002         }
3003
3004         /* NVRAM info initialization and population */
3005         if (IS_LEAD_HWFN(p_hwfn)) {
3006                 rc = qed_mcp_nvm_info_populate(p_hwfn);
3007                 if (rc) {
3008                         DP_NOTICE(p_hwfn,
3009                                   "Failed to populate nvm info shadow\n");
3010                         goto err2;
3011                 }
3012         }
3013
3014         /* Allocate the init RT array and initialize the init-ops engine */
3015         rc = qed_init_alloc(p_hwfn);
3016         if (rc)
3017                 goto err3;
3018
3019         return rc;
3020 err3:
3021         if (IS_LEAD_HWFN(p_hwfn))
3022                 qed_nvm_info_free(p_hwfn);
3023 err2:
3024         if (IS_LEAD_HWFN(p_hwfn))
3025                 qed_iov_free_hw_info(p_hwfn->cdev);
3026         qed_mcp_free(p_hwfn);
3027 err1:
3028         qed_hw_hwfn_free(p_hwfn);
3029 err0:
3030         return rc;
3031 }
3032
3033 int qed_hw_prepare(struct qed_dev *cdev,
3034                    int personality)
3035 {
3036         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
3037         int rc;
3038
3039         /* Store the precompiled init data ptrs */
3040         if (IS_PF(cdev))
3041                 qed_init_iro_array(cdev);
3042
3043         /* Initialize the first hwfn - will learn number of hwfns */
3044         rc = qed_hw_prepare_single(p_hwfn,
3045                                    cdev->regview,
3046                                    cdev->doorbells, personality);
3047         if (rc)
3048                 return rc;
3049
3050         personality = p_hwfn->hw_info.personality;
3051
3052         /* Initialize the rest of the hwfns */
3053         if (cdev->num_hwfns > 1) {
3054                 void __iomem *p_regview, *p_doorbell;
3055                 u8 __iomem *addr;
3056
3057                 /* adjust bar offset for second engine */
3058                 addr = cdev->regview +
3059                        qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
3060                                        BAR_ID_0) / 2;
3061                 p_regview = addr;
3062
3063                 addr = cdev->doorbells +
3064                        qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,
3065                                        BAR_ID_1) / 2;
3066                 p_doorbell = addr;
3067
3068                 /* prepare second hw function */
3069                 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview,
3070                                            p_doorbell, personality);
3071
3072                 /* in case of error, need to free the previously
3073                  * initiliazed hwfn 0.
3074                  */
3075                 if (rc) {
3076                         if (IS_PF(cdev)) {
3077                                 qed_init_free(p_hwfn);
3078                                 qed_nvm_info_free(p_hwfn);
3079                                 qed_mcp_free(p_hwfn);
3080                                 qed_hw_hwfn_free(p_hwfn);
3081                         }
3082                 }
3083         }
3084
3085         return rc;
3086 }
3087
3088 void qed_hw_remove(struct qed_dev *cdev)
3089 {
3090         struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
3091         int i;
3092
3093         if (IS_PF(cdev))
3094                 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt,
3095                                                QED_OV_DRIVER_STATE_NOT_LOADED);
3096
3097         for_each_hwfn(cdev, i) {
3098                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
3099
3100                 if (IS_VF(cdev)) {
3101                         qed_vf_pf_release(p_hwfn);
3102                         continue;
3103                 }
3104
3105                 qed_init_free(p_hwfn);
3106                 qed_hw_hwfn_free(p_hwfn);
3107                 qed_mcp_free(p_hwfn);
3108         }
3109
3110         qed_iov_free_hw_info(cdev);
3111
3112         qed_nvm_info_free(p_hwfn);
3113 }
3114
3115 static void qed_chain_free_next_ptr(struct qed_dev *cdev,
3116                                     struct qed_chain *p_chain)
3117 {
3118         void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL;
3119         dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0;
3120         struct qed_chain_next *p_next;
3121         u32 size, i;
3122
3123         if (!p_virt)
3124                 return;
3125
3126         size = p_chain->elem_size * p_chain->usable_per_page;
3127
3128         for (i = 0; i < p_chain->page_cnt; i++) {
3129                 if (!p_virt)
3130                         break;
3131
3132                 p_next = (struct qed_chain_next *)((u8 *)p_virt + size);
3133                 p_virt_next = p_next->next_virt;
3134                 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys);
3135
3136                 dma_free_coherent(&cdev->pdev->dev,
3137                                   QED_CHAIN_PAGE_SIZE, p_virt, p_phys);
3138
3139                 p_virt = p_virt_next;
3140                 p_phys = p_phys_next;
3141         }
3142 }
3143
3144 static void qed_chain_free_single(struct qed_dev *cdev,
3145                                   struct qed_chain *p_chain)
3146 {
3147         if (!p_chain->p_virt_addr)
3148                 return;
3149
3150         dma_free_coherent(&cdev->pdev->dev,
3151                           QED_CHAIN_PAGE_SIZE,
3152                           p_chain->p_virt_addr, p_chain->p_phys_addr);
3153 }
3154
3155 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain)
3156 {
3157         void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl;
3158         u32 page_cnt = p_chain->page_cnt, i, pbl_size;
3159         u8 *p_pbl_virt = p_chain->pbl_sp.p_virt_table;
3160
3161         if (!pp_virt_addr_tbl)
3162                 return;
3163
3164         if (!p_pbl_virt)
3165                 goto out;
3166
3167         for (i = 0; i < page_cnt; i++) {
3168                 if (!pp_virt_addr_tbl[i])
3169                         break;
3170
3171                 dma_free_coherent(&cdev->pdev->dev,
3172                                   QED_CHAIN_PAGE_SIZE,
3173                                   pp_virt_addr_tbl[i],
3174                                   *(dma_addr_t *)p_pbl_virt);
3175
3176                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3177         }
3178
3179         pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3180
3181         if (!p_chain->b_external_pbl)
3182                 dma_free_coherent(&cdev->pdev->dev,
3183                                   pbl_size,
3184                                   p_chain->pbl_sp.p_virt_table,
3185                                   p_chain->pbl_sp.p_phys_table);
3186 out:
3187         vfree(p_chain->pbl.pp_virt_addr_tbl);
3188         p_chain->pbl.pp_virt_addr_tbl = NULL;
3189 }
3190
3191 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain)
3192 {
3193         switch (p_chain->mode) {
3194         case QED_CHAIN_MODE_NEXT_PTR:
3195                 qed_chain_free_next_ptr(cdev, p_chain);
3196                 break;
3197         case QED_CHAIN_MODE_SINGLE:
3198                 qed_chain_free_single(cdev, p_chain);
3199                 break;
3200         case QED_CHAIN_MODE_PBL:
3201                 qed_chain_free_pbl(cdev, p_chain);
3202                 break;
3203         }
3204 }
3205
3206 static int
3207 qed_chain_alloc_sanity_check(struct qed_dev *cdev,
3208                              enum qed_chain_cnt_type cnt_type,
3209                              size_t elem_size, u32 page_cnt)
3210 {
3211         u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt;
3212
3213         /* The actual chain size can be larger than the maximal possible value
3214          * after rounding up the requested elements number to pages, and after
3215          * taking into acount the unusuable elements (next-ptr elements).
3216          * The size of a "u16" chain can be (U16_MAX + 1) since the chain
3217          * size/capacity fields are of a u32 type.
3218          */
3219         if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 &&
3220              chain_size > ((u32)U16_MAX + 1)) ||
3221             (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) {
3222                 DP_NOTICE(cdev,
3223                           "The actual chain size (0x%llx) is larger than the maximal possible value\n",
3224                           chain_size);
3225                 return -EINVAL;
3226         }
3227
3228         return 0;
3229 }
3230
3231 static int
3232 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain)
3233 {
3234         void *p_virt = NULL, *p_virt_prev = NULL;
3235         dma_addr_t p_phys = 0;
3236         u32 i;
3237
3238         for (i = 0; i < p_chain->page_cnt; i++) {
3239                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3240                                             QED_CHAIN_PAGE_SIZE,
3241                                             &p_phys, GFP_KERNEL);
3242                 if (!p_virt)
3243                         return -ENOMEM;
3244
3245                 if (i == 0) {
3246                         qed_chain_init_mem(p_chain, p_virt, p_phys);
3247                         qed_chain_reset(p_chain);
3248                 } else {
3249                         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3250                                                      p_virt, p_phys);
3251                 }
3252
3253                 p_virt_prev = p_virt;
3254         }
3255         /* Last page's next element should point to the beginning of the
3256          * chain.
3257          */
3258         qed_chain_init_next_ptr_elem(p_chain, p_virt_prev,
3259                                      p_chain->p_virt_addr,
3260                                      p_chain->p_phys_addr);
3261
3262         return 0;
3263 }
3264
3265 static int
3266 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain)
3267 {
3268         dma_addr_t p_phys = 0;
3269         void *p_virt = NULL;
3270
3271         p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3272                                     QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL);
3273         if (!p_virt)
3274                 return -ENOMEM;
3275
3276         qed_chain_init_mem(p_chain, p_virt, p_phys);
3277         qed_chain_reset(p_chain);
3278
3279         return 0;
3280 }
3281
3282 static int
3283 qed_chain_alloc_pbl(struct qed_dev *cdev,
3284                     struct qed_chain *p_chain,
3285                     struct qed_chain_ext_pbl *ext_pbl)
3286 {
3287         u32 page_cnt = p_chain->page_cnt, size, i;
3288         dma_addr_t p_phys = 0, p_pbl_phys = 0;
3289         void **pp_virt_addr_tbl = NULL;
3290         u8 *p_pbl_virt = NULL;
3291         void *p_virt = NULL;
3292
3293         size = page_cnt * sizeof(*pp_virt_addr_tbl);
3294         pp_virt_addr_tbl = vzalloc(size);
3295         if (!pp_virt_addr_tbl)
3296                 return -ENOMEM;
3297
3298         /* The allocation of the PBL table is done with its full size, since it
3299          * is expected to be successive.
3300          * qed_chain_init_pbl_mem() is called even in a case of an allocation
3301          * failure, since pp_virt_addr_tbl was previously allocated, and it
3302          * should be saved to allow its freeing during the error flow.
3303          */
3304         size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE;
3305
3306         if (!ext_pbl) {
3307                 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev,
3308                                                 size, &p_pbl_phys, GFP_KERNEL);
3309         } else {
3310                 p_pbl_virt = ext_pbl->p_pbl_virt;
3311                 p_pbl_phys = ext_pbl->p_pbl_phys;
3312                 p_chain->b_external_pbl = true;
3313         }
3314
3315         qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys,
3316                                pp_virt_addr_tbl);
3317         if (!p_pbl_virt)
3318                 return -ENOMEM;
3319
3320         for (i = 0; i < page_cnt; i++) {
3321                 p_virt = dma_alloc_coherent(&cdev->pdev->dev,
3322                                             QED_CHAIN_PAGE_SIZE,
3323                                             &p_phys, GFP_KERNEL);
3324                 if (!p_virt)
3325                         return -ENOMEM;
3326
3327                 if (i == 0) {
3328                         qed_chain_init_mem(p_chain, p_virt, p_phys);
3329                         qed_chain_reset(p_chain);
3330                 }
3331
3332                 /* Fill the PBL table with the physical address of the page */
3333                 *(dma_addr_t *)p_pbl_virt = p_phys;
3334                 /* Keep the virtual address of the page */
3335                 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt;
3336
3337                 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE;
3338         }
3339
3340         return 0;
3341 }
3342
3343 int qed_chain_alloc(struct qed_dev *cdev,
3344                     enum qed_chain_use_mode intended_use,
3345                     enum qed_chain_mode mode,
3346                     enum qed_chain_cnt_type cnt_type,
3347                     u32 num_elems,
3348                     size_t elem_size,
3349                     struct qed_chain *p_chain,
3350                     struct qed_chain_ext_pbl *ext_pbl)
3351 {
3352         u32 page_cnt;
3353         int rc = 0;
3354
3355         if (mode == QED_CHAIN_MODE_SINGLE)
3356                 page_cnt = 1;
3357         else
3358                 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode);
3359
3360         rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt);
3361         if (rc) {
3362                 DP_NOTICE(cdev,
3363                           "Cannot allocate a chain with the given arguments:\n");
3364                 DP_NOTICE(cdev,
3365                           "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
3366                           intended_use, mode, cnt_type, num_elems, elem_size);
3367                 return rc;
3368         }
3369
3370         qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use,
3371                               mode, cnt_type);
3372
3373         switch (mode) {
3374         case QED_CHAIN_MODE_NEXT_PTR:
3375                 rc = qed_chain_alloc_next_ptr(cdev, p_chain);
3376                 break;
3377         case QED_CHAIN_MODE_SINGLE:
3378                 rc = qed_chain_alloc_single(cdev, p_chain);
3379                 break;
3380         case QED_CHAIN_MODE_PBL:
3381                 rc = qed_chain_alloc_pbl(cdev, p_chain, ext_pbl);
3382                 break;
3383         }
3384         if (rc)
3385                 goto nomem;
3386
3387         return 0;
3388
3389 nomem:
3390         qed_chain_free(cdev, p_chain);
3391         return rc;
3392 }
3393
3394 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id)
3395 {
3396         if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) {
3397                 u16 min, max;
3398
3399                 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE);
3400                 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE);
3401                 DP_NOTICE(p_hwfn,
3402                           "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
3403                           src_id, min, max);
3404
3405                 return -EINVAL;
3406         }
3407
3408         *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id;
3409
3410         return 0;
3411 }
3412
3413 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3414 {
3415         if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) {
3416                 u8 min, max;
3417
3418                 min = (u8)RESC_START(p_hwfn, QED_VPORT);
3419                 max = min + RESC_NUM(p_hwfn, QED_VPORT);
3420                 DP_NOTICE(p_hwfn,
3421                           "vport id [%d] is not valid, available indices [%d - %d]\n",
3422                           src_id, min, max);
3423
3424                 return -EINVAL;
3425         }
3426
3427         *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id;
3428
3429         return 0;
3430 }
3431
3432 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id)
3433 {
3434         if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) {
3435                 u8 min, max;
3436
3437                 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG);
3438                 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG);
3439                 DP_NOTICE(p_hwfn,
3440                           "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
3441                           src_id, min, max);
3442
3443                 return -EINVAL;
3444         }
3445
3446         *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id;
3447
3448         return 0;
3449 }
3450
3451 static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low,
3452                                   u8 *p_filter)
3453 {
3454         *p_high = p_filter[1] | (p_filter[0] << 8);
3455         *p_low = p_filter[5] | (p_filter[4] << 8) |
3456                  (p_filter[3] << 16) | (p_filter[2] << 24);
3457 }
3458
3459 int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
3460                            struct qed_ptt *p_ptt, u8 *p_filter)
3461 {
3462         u32 high = 0, low = 0, en;
3463         int i;
3464
3465         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3466                 return 0;
3467
3468         qed_llh_mac_to_filter(&high, &low, p_filter);
3469
3470         /* Find a free entry and utilize it */
3471         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3472                 en = qed_rd(p_hwfn, p_ptt,
3473                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3474                 if (en)
3475                         continue;
3476                 qed_wr(p_hwfn, p_ptt,
3477                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3478                        2 * i * sizeof(u32), low);
3479                 qed_wr(p_hwfn, p_ptt,
3480                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3481                        (2 * i + 1) * sizeof(u32), high);
3482                 qed_wr(p_hwfn, p_ptt,
3483                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3484                 qed_wr(p_hwfn, p_ptt,
3485                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3486                        i * sizeof(u32), 0);
3487                 qed_wr(p_hwfn, p_ptt,
3488                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3489                 break;
3490         }
3491         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3492                 DP_NOTICE(p_hwfn,
3493                           "Failed to find an empty LLH filter to utilize\n");
3494                 return -EINVAL;
3495         }
3496
3497         DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3498                    "mac: %pM is added at %d\n",
3499                    p_filter, i);
3500
3501         return 0;
3502 }
3503
3504 void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
3505                                struct qed_ptt *p_ptt, u8 *p_filter)
3506 {
3507         u32 high = 0, low = 0;
3508         int i;
3509
3510         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3511                 return;
3512
3513         qed_llh_mac_to_filter(&high, &low, p_filter);
3514
3515         /* Find the entry and clean it */
3516         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3517                 if (qed_rd(p_hwfn, p_ptt,
3518                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3519                            2 * i * sizeof(u32)) != low)
3520                         continue;
3521                 if (qed_rd(p_hwfn, p_ptt,
3522                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3523                            (2 * i + 1) * sizeof(u32)) != high)
3524                         continue;
3525
3526                 qed_wr(p_hwfn, p_ptt,
3527                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3528                 qed_wr(p_hwfn, p_ptt,
3529                        NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3530                 qed_wr(p_hwfn, p_ptt,
3531                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3532                        (2 * i + 1) * sizeof(u32), 0);
3533
3534                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3535                            "mac: %pM is removed from %d\n",
3536                            p_filter, i);
3537                 break;
3538         }
3539         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3540                 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3541 }
3542
3543 int
3544 qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn,
3545                             struct qed_ptt *p_ptt,
3546                             u16 source_port_or_eth_type,
3547                             u16 dest_port, enum qed_llh_port_filter_type_t type)
3548 {
3549         u32 high = 0, low = 0, en;
3550         int i;
3551
3552         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3553                 return 0;
3554
3555         switch (type) {
3556         case QED_LLH_FILTER_ETHERTYPE:
3557                 high = source_port_or_eth_type;
3558                 break;
3559         case QED_LLH_FILTER_TCP_SRC_PORT:
3560         case QED_LLH_FILTER_UDP_SRC_PORT:
3561                 low = source_port_or_eth_type << 16;
3562                 break;
3563         case QED_LLH_FILTER_TCP_DEST_PORT:
3564         case QED_LLH_FILTER_UDP_DEST_PORT:
3565                 low = dest_port;
3566                 break;
3567         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3568         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3569                 low = (source_port_or_eth_type << 16) | dest_port;
3570                 break;
3571         default:
3572                 DP_NOTICE(p_hwfn,
3573                           "Non valid LLH protocol filter type %d\n", type);
3574                 return -EINVAL;
3575         }
3576         /* Find a free entry and utilize it */
3577         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3578                 en = qed_rd(p_hwfn, p_ptt,
3579                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32));
3580                 if (en)
3581                         continue;
3582                 qed_wr(p_hwfn, p_ptt,
3583                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3584                        2 * i * sizeof(u32), low);
3585                 qed_wr(p_hwfn, p_ptt,
3586                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3587                        (2 * i + 1) * sizeof(u32), high);
3588                 qed_wr(p_hwfn, p_ptt,
3589                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1);
3590                 qed_wr(p_hwfn, p_ptt,
3591                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3592                        i * sizeof(u32), 1 << type);
3593                 qed_wr(p_hwfn, p_ptt,
3594                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1);
3595                 break;
3596         }
3597         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {
3598                 DP_NOTICE(p_hwfn,
3599                           "Failed to find an empty LLH filter to utilize\n");
3600                 return -EINVAL;
3601         }
3602         switch (type) {
3603         case QED_LLH_FILTER_ETHERTYPE:
3604                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3605                            "ETH type %x is added at %d\n",
3606                            source_port_or_eth_type, i);
3607                 break;
3608         case QED_LLH_FILTER_TCP_SRC_PORT:
3609                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3610                            "TCP src port %x is added at %d\n",
3611                            source_port_or_eth_type, i);
3612                 break;
3613         case QED_LLH_FILTER_UDP_SRC_PORT:
3614                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3615                            "UDP src port %x is added at %d\n",
3616                            source_port_or_eth_type, i);
3617                 break;
3618         case QED_LLH_FILTER_TCP_DEST_PORT:
3619                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3620                            "TCP dst port %x is added at %d\n", dest_port, i);
3621                 break;
3622         case QED_LLH_FILTER_UDP_DEST_PORT:
3623                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3624                            "UDP dst port %x is added at %d\n", dest_port, i);
3625                 break;
3626         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3627                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3628                            "TCP src/dst ports %x/%x are added at %d\n",
3629                            source_port_or_eth_type, dest_port, i);
3630                 break;
3631         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3632                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
3633                            "UDP src/dst ports %x/%x are added at %d\n",
3634                            source_port_or_eth_type, dest_port, i);
3635                 break;
3636         }
3637         return 0;
3638 }
3639
3640 void
3641 qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn,
3642                                struct qed_ptt *p_ptt,
3643                                u16 source_port_or_eth_type,
3644                                u16 dest_port,
3645                                enum qed_llh_port_filter_type_t type)
3646 {
3647         u32 high = 0, low = 0;
3648         int i;
3649
3650         if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3651                 return;
3652
3653         switch (type) {
3654         case QED_LLH_FILTER_ETHERTYPE:
3655                 high = source_port_or_eth_type;
3656                 break;
3657         case QED_LLH_FILTER_TCP_SRC_PORT:
3658         case QED_LLH_FILTER_UDP_SRC_PORT:
3659                 low = source_port_or_eth_type << 16;
3660                 break;
3661         case QED_LLH_FILTER_TCP_DEST_PORT:
3662         case QED_LLH_FILTER_UDP_DEST_PORT:
3663                 low = dest_port;
3664                 break;
3665         case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT:
3666         case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT:
3667                 low = (source_port_or_eth_type << 16) | dest_port;
3668                 break;
3669         default:
3670                 DP_NOTICE(p_hwfn,
3671                           "Non valid LLH protocol filter type %d\n", type);
3672                 return;
3673         }
3674
3675         for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {
3676                 if (!qed_rd(p_hwfn, p_ptt,
3677                             NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)))
3678                         continue;
3679                 if (!qed_rd(p_hwfn, p_ptt,
3680                             NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32)))
3681                         continue;
3682                 if (!(qed_rd(p_hwfn, p_ptt,
3683                              NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3684                              i * sizeof(u32)) & BIT(type)))
3685                         continue;
3686                 if (qed_rd(p_hwfn, p_ptt,
3687                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3688                            2 * i * sizeof(u32)) != low)
3689                         continue;
3690                 if (qed_rd(p_hwfn, p_ptt,
3691                            NIG_REG_LLH_FUNC_FILTER_VALUE +
3692                            (2 * i + 1) * sizeof(u32)) != high)
3693                         continue;
3694
3695                 qed_wr(p_hwfn, p_ptt,
3696                        NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0);
3697                 qed_wr(p_hwfn, p_ptt,
3698                        NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0);
3699                 qed_wr(p_hwfn, p_ptt,
3700                        NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE +
3701                        i * sizeof(u32), 0);
3702                 qed_wr(p_hwfn, p_ptt,
3703                        NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0);
3704                 qed_wr(p_hwfn, p_ptt,
3705                        NIG_REG_LLH_FUNC_FILTER_VALUE +
3706                        (2 * i + 1) * sizeof(u32), 0);
3707                 break;
3708         }
3709
3710         if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)
3711                 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n");
3712 }
3713
3714 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
3715                             u32 hw_addr, void *p_eth_qzone,
3716                             size_t eth_qzone_size, u8 timeset)
3717 {
3718         struct coalescing_timeset *p_coal_timeset;
3719
3720         if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) {
3721                 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n");
3722                 return -EINVAL;
3723         }
3724
3725         p_coal_timeset = p_eth_qzone;
3726         memset(p_eth_qzone, 0, eth_qzone_size);
3727         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset);
3728         SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1);
3729         qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size);
3730
3731         return 0;
3732 }
3733
3734 int qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle)
3735 {
3736         struct qed_queue_cid *p_cid = p_handle;
3737         struct qed_hwfn *p_hwfn;
3738         struct qed_ptt *p_ptt;
3739         int rc = 0;
3740
3741         p_hwfn = p_cid->p_owner;
3742
3743         if (IS_VF(p_hwfn->cdev))
3744                 return qed_vf_pf_set_coalesce(p_hwfn, rx_coal, tx_coal, p_cid);
3745
3746         p_ptt = qed_ptt_acquire(p_hwfn);
3747         if (!p_ptt)
3748                 return -EAGAIN;
3749
3750         if (rx_coal) {
3751                 rc = qed_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid);
3752                 if (rc)
3753                         goto out;
3754                 p_hwfn->cdev->rx_coalesce_usecs = rx_coal;
3755         }
3756
3757         if (tx_coal) {
3758                 rc = qed_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid);
3759                 if (rc)
3760                         goto out;
3761                 p_hwfn->cdev->tx_coalesce_usecs = tx_coal;
3762         }
3763 out:
3764         qed_ptt_release(p_hwfn, p_ptt);
3765         return rc;
3766 }
3767
3768 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn,
3769                          struct qed_ptt *p_ptt,
3770                          u16 coalesce, struct qed_queue_cid *p_cid)
3771 {
3772         struct ustorm_eth_queue_zone eth_qzone;
3773         u8 timeset, timer_res;
3774         u32 address;
3775         int rc;
3776
3777         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3778         if (coalesce <= 0x7F) {
3779                 timer_res = 0;
3780         } else if (coalesce <= 0xFF) {
3781                 timer_res = 1;
3782         } else if (coalesce <= 0x1FF) {
3783                 timer_res = 2;
3784         } else {
3785                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3786                 return -EINVAL;
3787         }
3788         timeset = (u8)(coalesce >> timer_res);
3789
3790         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
3791                                    p_cid->sb_igu_id, false);
3792         if (rc)
3793                 goto out;
3794
3795         address = BAR0_MAP_REG_USDM_RAM +
3796                   USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
3797
3798         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3799                               sizeof(struct ustorm_eth_queue_zone), timeset);
3800         if (rc)
3801                 goto out;
3802
3803 out:
3804         return rc;
3805 }
3806
3807 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn,
3808                          struct qed_ptt *p_ptt,
3809                          u16 coalesce, struct qed_queue_cid *p_cid)
3810 {
3811         struct xstorm_eth_queue_zone eth_qzone;
3812         u8 timeset, timer_res;
3813         u32 address;
3814         int rc;
3815
3816         /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
3817         if (coalesce <= 0x7F) {
3818                 timer_res = 0;
3819         } else if (coalesce <= 0xFF) {
3820                 timer_res = 1;
3821         } else if (coalesce <= 0x1FF) {
3822                 timer_res = 2;
3823         } else {
3824                 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce);
3825                 return -EINVAL;
3826         }
3827         timeset = (u8)(coalesce >> timer_res);
3828
3829         rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res,
3830                                    p_cid->sb_igu_id, true);
3831         if (rc)
3832                 goto out;
3833
3834         address = BAR0_MAP_REG_XSDM_RAM +
3835                   XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id);
3836
3837         rc = qed_set_coalesce(p_hwfn, p_ptt, address, &eth_qzone,
3838                               sizeof(struct xstorm_eth_queue_zone), timeset);
3839 out:
3840         return rc;
3841 }
3842
3843 /* Calculate final WFQ values for all vports and configure them.
3844  * After this configuration each vport will have
3845  * approx min rate =  min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
3846  */
3847 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
3848                                              struct qed_ptt *p_ptt,
3849                                              u32 min_pf_rate)
3850 {
3851         struct init_qm_vport_params *vport_params;
3852         int i;
3853
3854         vport_params = p_hwfn->qm_info.qm_vport_params;
3855
3856         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3857                 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3858
3859                 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) /
3860                                                 min_pf_rate;
3861                 qed_init_vport_wfq(p_hwfn, p_ptt,
3862                                    vport_params[i].first_tx_pq_id,
3863                                    vport_params[i].vport_wfq);
3864         }
3865 }
3866
3867 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn,
3868                                        u32 min_pf_rate)
3869
3870 {
3871         int i;
3872
3873         for (i = 0; i < p_hwfn->qm_info.num_vports; i++)
3874                 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1;
3875 }
3876
3877 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn,
3878                                            struct qed_ptt *p_ptt,
3879                                            u32 min_pf_rate)
3880 {
3881         struct init_qm_vport_params *vport_params;
3882         int i;
3883
3884         vport_params = p_hwfn->qm_info.qm_vport_params;
3885
3886         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
3887                 qed_init_wfq_default_param(p_hwfn, min_pf_rate);
3888                 qed_init_vport_wfq(p_hwfn, p_ptt,
3889                                    vport_params[i].first_tx_pq_id,
3890                                    vport_params[i].vport_wfq);
3891         }
3892 }
3893
3894 /* This function performs several validations for WFQ
3895  * configuration and required min rate for a given vport
3896  * 1. req_rate must be greater than one percent of min_pf_rate.
3897  * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
3898  *    rates to get less than one percent of min_pf_rate.
3899  * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
3900  */
3901 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn,
3902                               u16 vport_id, u32 req_rate, u32 min_pf_rate)
3903 {
3904         u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0;
3905         int non_requested_count = 0, req_count = 0, i, num_vports;
3906
3907         num_vports = p_hwfn->qm_info.num_vports;
3908
3909         /* Accounting for the vports which are configured for WFQ explicitly */
3910         for (i = 0; i < num_vports; i++) {
3911                 u32 tmp_speed;
3912
3913                 if ((i != vport_id) &&
3914                     p_hwfn->qm_info.wfq_data[i].configured) {
3915                         req_count++;
3916                         tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed;
3917                         total_req_min_rate += tmp_speed;
3918                 }
3919         }
3920
3921         /* Include current vport data as well */
3922         req_count++;
3923         total_req_min_rate += req_rate;
3924         non_requested_count = num_vports - req_count;
3925
3926         if (req_rate < min_pf_rate / QED_WFQ_UNIT) {
3927                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3928                            "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3929                            vport_id, req_rate, min_pf_rate);
3930                 return -EINVAL;
3931         }
3932
3933         if (num_vports > QED_WFQ_UNIT) {
3934                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3935                            "Number of vports is greater than %d\n",
3936                            QED_WFQ_UNIT);
3937                 return -EINVAL;
3938         }
3939
3940         if (total_req_min_rate > min_pf_rate) {
3941                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3942                            "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
3943                            total_req_min_rate, min_pf_rate);
3944                 return -EINVAL;
3945         }
3946
3947         total_left_rate = min_pf_rate - total_req_min_rate;
3948
3949         left_rate_per_vp = total_left_rate / non_requested_count;
3950         if (left_rate_per_vp <  min_pf_rate / QED_WFQ_UNIT) {
3951                 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
3952                            "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
3953                            left_rate_per_vp, min_pf_rate);
3954                 return -EINVAL;
3955         }
3956
3957         p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate;
3958         p_hwfn->qm_info.wfq_data[vport_id].configured = true;
3959
3960         for (i = 0; i < num_vports; i++) {
3961                 if (p_hwfn->qm_info.wfq_data[i].configured)
3962                         continue;
3963
3964                 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp;
3965         }
3966
3967         return 0;
3968 }
3969
3970 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn,
3971                                      struct qed_ptt *p_ptt, u16 vp_id, u32 rate)
3972 {
3973         struct qed_mcp_link_state *p_link;
3974         int rc = 0;
3975
3976         p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output;
3977
3978         if (!p_link->min_pf_rate) {
3979                 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate;
3980                 p_hwfn->qm_info.wfq_data[vp_id].configured = true;
3981                 return rc;
3982         }
3983
3984         rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate);
3985
3986         if (!rc)
3987                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt,
3988                                                  p_link->min_pf_rate);
3989         else
3990                 DP_NOTICE(p_hwfn,
3991                           "Validation failed while configuring min rate\n");
3992
3993         return rc;
3994 }
3995
3996 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn,
3997                                                  struct qed_ptt *p_ptt,
3998                                                  u32 min_pf_rate)
3999 {
4000         bool use_wfq = false;
4001         int rc = 0;
4002         u16 i;
4003
4004         /* Validate all pre configured vports for wfq */
4005         for (i = 0; i < p_hwfn->qm_info.num_vports; i++) {
4006                 u32 rate;
4007
4008                 if (!p_hwfn->qm_info.wfq_data[i].configured)
4009                         continue;
4010
4011                 rate = p_hwfn->qm_info.wfq_data[i].min_speed;
4012                 use_wfq = true;
4013
4014                 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate);
4015                 if (rc) {
4016                         DP_NOTICE(p_hwfn,
4017                                   "WFQ validation failed while configuring min rate\n");
4018                         break;
4019                 }
4020         }
4021
4022         if (!rc && use_wfq)
4023                 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4024         else
4025                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate);
4026
4027         return rc;
4028 }
4029
4030 /* Main API for qed clients to configure vport min rate.
4031  * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
4032  * rate - Speed in Mbps needs to be assigned to a given vport.
4033  */
4034 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate)
4035 {
4036         int i, rc = -EINVAL;
4037
4038         /* Currently not supported; Might change in future */
4039         if (cdev->num_hwfns > 1) {
4040                 DP_NOTICE(cdev,
4041                           "WFQ configuration is not supported for this device\n");
4042                 return rc;
4043         }
4044
4045         for_each_hwfn(cdev, i) {
4046                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4047                 struct qed_ptt *p_ptt;
4048
4049                 p_ptt = qed_ptt_acquire(p_hwfn);
4050                 if (!p_ptt)
4051                         return -EBUSY;
4052
4053                 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate);
4054
4055                 if (rc) {
4056                         qed_ptt_release(p_hwfn, p_ptt);
4057                         return rc;
4058                 }
4059
4060                 qed_ptt_release(p_hwfn, p_ptt);
4061         }
4062
4063         return rc;
4064 }
4065
4066 /* API to configure WFQ from mcp link change */
4067 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
4068                                          struct qed_ptt *p_ptt, u32 min_pf_rate)
4069 {
4070         int i;
4071
4072         if (cdev->num_hwfns > 1) {
4073                 DP_VERBOSE(cdev,
4074                            NETIF_MSG_LINK,
4075                            "WFQ configuration is not supported for this device\n");
4076                 return;
4077         }
4078
4079         for_each_hwfn(cdev, i) {
4080                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4081
4082                 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt,
4083                                                       min_pf_rate);
4084         }
4085 }
4086
4087 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn,
4088                                      struct qed_ptt *p_ptt,
4089                                      struct qed_mcp_link_state *p_link,
4090                                      u8 max_bw)
4091 {
4092         int rc = 0;
4093
4094         p_hwfn->mcp_info->func_info.bandwidth_max = max_bw;
4095
4096         if (!p_link->line_speed && (max_bw != 100))
4097                 return rc;
4098
4099         p_link->speed = (p_link->line_speed * max_bw) / 100;
4100         p_hwfn->qm_info.pf_rl = p_link->speed;
4101
4102         /* Since the limiter also affects Tx-switched traffic, we don't want it
4103          * to limit such traffic in case there's no actual limit.
4104          * In that case, set limit to imaginary high boundary.
4105          */
4106         if (max_bw == 100)
4107                 p_hwfn->qm_info.pf_rl = 100000;
4108
4109         rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
4110                             p_hwfn->qm_info.pf_rl);
4111
4112         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4113                    "Configured MAX bandwidth to be %08x Mb/sec\n",
4114                    p_link->speed);
4115
4116         return rc;
4117 }
4118
4119 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
4120 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw)
4121 {
4122         int i, rc = -EINVAL;
4123
4124         if (max_bw < 1 || max_bw > 100) {
4125                 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n");
4126                 return rc;
4127         }
4128
4129         for_each_hwfn(cdev, i) {
4130                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4131                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4132                 struct qed_mcp_link_state *p_link;
4133                 struct qed_ptt *p_ptt;
4134
4135                 p_link = &p_lead->mcp_info->link_output;
4136
4137                 p_ptt = qed_ptt_acquire(p_hwfn);
4138                 if (!p_ptt)
4139                         return -EBUSY;
4140
4141                 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt,
4142                                                       p_link, max_bw);
4143
4144                 qed_ptt_release(p_hwfn, p_ptt);
4145
4146                 if (rc)
4147                         break;
4148         }
4149
4150         return rc;
4151 }
4152
4153 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
4154                                      struct qed_ptt *p_ptt,
4155                                      struct qed_mcp_link_state *p_link,
4156                                      u8 min_bw)
4157 {
4158         int rc = 0;
4159
4160         p_hwfn->mcp_info->func_info.bandwidth_min = min_bw;
4161         p_hwfn->qm_info.pf_wfq = min_bw;
4162
4163         if (!p_link->line_speed)
4164                 return rc;
4165
4166         p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100;
4167
4168         rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw);
4169
4170         DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
4171                    "Configured MIN bandwidth to be %d Mb/sec\n",
4172                    p_link->min_pf_rate);
4173
4174         return rc;
4175 }
4176
4177 /* Main API to configure PF min bandwidth where bw range is [1-100] */
4178 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw)
4179 {
4180         int i, rc = -EINVAL;
4181
4182         if (min_bw < 1 || min_bw > 100) {
4183                 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n");
4184                 return rc;
4185         }
4186
4187         for_each_hwfn(cdev, i) {
4188                 struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
4189                 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev);
4190                 struct qed_mcp_link_state *p_link;
4191                 struct qed_ptt *p_ptt;
4192
4193                 p_link = &p_lead->mcp_info->link_output;
4194
4195                 p_ptt = qed_ptt_acquire(p_hwfn);
4196                 if (!p_ptt)
4197                         return -EBUSY;
4198
4199                 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt,
4200                                                       p_link, min_bw);
4201                 if (rc) {
4202                         qed_ptt_release(p_hwfn, p_ptt);
4203                         return rc;
4204                 }
4205
4206                 if (p_link->min_pf_rate) {
4207                         u32 min_rate = p_link->min_pf_rate;
4208
4209                         rc = __qed_configure_vp_wfq_on_link_change(p_hwfn,
4210                                                                    p_ptt,
4211                                                                    min_rate);
4212                 }
4213
4214                 qed_ptt_release(p_hwfn, p_ptt);
4215         }
4216
4217         return rc;
4218 }
4219
4220 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
4221 {
4222         struct qed_mcp_link_state *p_link;
4223
4224         p_link = &p_hwfn->mcp_info->link_output;
4225
4226         if (p_link->min_pf_rate)
4227                 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt,
4228                                                p_link->min_pf_rate);
4229
4230         memset(p_hwfn->qm_info.wfq_data, 0,
4231                sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports);
4232 }
4233
4234 int qed_device_num_engines(struct qed_dev *cdev)
4235 {
4236         return QED_IS_BB(cdev) ? 2 : 1;
4237 }
4238
4239 static int qed_device_num_ports(struct qed_dev *cdev)
4240 {
4241         /* in CMT always only one port */
4242         if (cdev->num_hwfns > 1)
4243                 return 1;
4244
4245         return cdev->num_ports_in_engine * qed_device_num_engines(cdev);
4246 }
4247
4248 int qed_device_get_port_id(struct qed_dev *cdev)
4249 {
4250         return (QED_LEADING_HWFN(cdev)->abs_pf_id) % qed_device_num_ports(cdev);
4251 }
4252
4253 void qed_set_fw_mac_addr(__le16 *fw_msb,
4254                          __le16 *fw_mid, __le16 *fw_lsb, u8 *mac)
4255 {
4256         ((u8 *)fw_msb)[0] = mac[1];
4257         ((u8 *)fw_msb)[1] = mac[0];
4258         ((u8 *)fw_mid)[0] = mac[3];
4259         ((u8 *)fw_mid)[1] = mac[2];
4260         ((u8 *)fw_lsb)[0] = mac[5];
4261         ((u8 *)fw_lsb)[1] = mac[4];
4262 }