1 /* QLogic qede NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
11 #include <linux/compiler.h>
12 #include <linux/version.h>
13 #include <linux/workqueue.h>
14 #include <linux/netdevice.h>
15 #include <linux/interrupt.h>
16 #include <linux/bitmap.h>
17 #include <linux/kernel.h>
18 #include <linux/mutex.h>
20 #include <linux/qed/common_hsi.h>
21 #include <linux/qed/eth_common.h>
22 #include <linux/qed/qed_if.h>
23 #include <linux/qed/qed_chain.h>
24 #include <linux/qed/qed_eth_if.h>
26 #define QEDE_MAJOR_VERSION 8
27 #define QEDE_MINOR_VERSION 10
28 #define QEDE_REVISION_VERSION 9
29 #define QEDE_ENGINEERING_VERSION 20
30 #define DRV_MODULE_VERSION __stringify(QEDE_MAJOR_VERSION) "." \
31 __stringify(QEDE_MINOR_VERSION) "." \
32 __stringify(QEDE_REVISION_VERSION) "." \
33 __stringify(QEDE_ENGINEERING_VERSION)
35 #define DRV_MODULE_SYM qede
39 u64 packet_too_big_discard;
47 u64 mftag_filter_discards;
48 u64 mac_filter_discards;
58 u64 coalesced_aborts_num;
59 u64 non_coalesced_pkts;
63 u64 rx_64_byte_packets;
64 u64 rx_65_to_127_byte_packets;
65 u64 rx_128_to_255_byte_packets;
66 u64 rx_256_to_511_byte_packets;
67 u64 rx_512_to_1023_byte_packets;
68 u64 rx_1024_to_1518_byte_packets;
69 u64 rx_1519_to_1522_byte_packets;
70 u64 rx_1519_to_2047_byte_packets;
71 u64 rx_2048_to_4095_byte_packets;
72 u64 rx_4096_to_9216_byte_packets;
73 u64 rx_9217_to_16383_byte_packets;
75 u64 rx_mac_crtl_frames;
79 u64 rx_carrier_errors;
80 u64 rx_oversize_packets;
82 u64 rx_undersize_packets;
84 u64 tx_64_byte_packets;
85 u64 tx_65_to_127_byte_packets;
86 u64 tx_128_to_255_byte_packets;
87 u64 tx_256_to_511_byte_packets;
88 u64 tx_512_to_1023_byte_packets;
89 u64 tx_1024_to_1518_byte_packets;
90 u64 tx_1519_to_2047_byte_packets;
91 u64 tx_2048_to_4095_byte_packets;
92 u64 tx_4096_to_9216_byte_packets;
93 u64 tx_9217_to_16383_byte_packets;
96 u64 tx_lpi_entry_count;
97 u64 tx_total_collisions;
100 u64 tx_mac_ctrl_frames;
104 struct list_head list;
109 struct qede_rdma_dev {
110 struct qedr_dev *qedr_dev;
111 struct list_head entry;
112 struct list_head roce_event_list;
113 struct workqueue_struct *roce_wq;
117 struct qed_dev *cdev;
118 struct net_device *ndev;
119 struct pci_dev *pdev;
125 #define QEDE_FLAG_IS_VF BIT(0)
126 #define IS_VF(edev) (!!((edev)->flags & QEDE_FLAG_IS_VF))
128 const struct qed_eth_ops *ops;
130 struct qed_dev_eth_info dev_info;
131 #define QEDE_MAX_RSS_CNT(edev) ((edev)->dev_info.num_queues)
132 #define QEDE_MAX_TSS_CNT(edev) ((edev)->dev_info.num_queues)
134 struct qede_fastpath *fp_array;
141 #define QEDE_QUEUE_CNT(edev) ((edev)->num_queues)
142 #define QEDE_RSS_COUNT(edev) ((edev)->num_queues - (edev)->fp_num_tx)
143 #define QEDE_TSS_COUNT(edev) ((edev)->num_queues - (edev)->fp_num_rx)
145 struct qed_int_info int_info;
146 unsigned char primary_mac[ETH_ALEN];
148 /* Smaller private varaiant of the RTNL lock */
149 struct mutex qede_lock;
150 u32 state; /* Protected by qede_lock */
154 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
155 #define ETH_OVERHEAD (ETH_HLEN + 8 + 8)
156 /* Max supported alignment is 256 (8 shift)
157 * minimal alignment shift 6 is optimal for 57xxx HW performance
159 #define QEDE_RX_ALIGN_SHIFT max(6, min(8, L1_CACHE_SHIFT))
160 /* We assume skb_build() uses sizeof(struct skb_shared_info) bytes
161 * at the end of skb->data, to avoid wasting a full cache line.
162 * This reduces memory use (skb->truesize).
164 #define QEDE_FW_RX_ALIGN_END \
165 max_t(u64, 1UL << QEDE_RX_ALIGN_SHIFT, \
166 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
168 struct qede_stats stats;
169 #define QEDE_RSS_INDIR_INITED BIT(0)
170 #define QEDE_RSS_KEY_INITED BIT(1)
171 #define QEDE_RSS_CAPS_INITED BIT(2)
172 u32 rss_params_inited; /* bit-field to track initialized rss params */
173 struct qed_update_vport_rss_params rss_params;
174 u16 q_num_rx_buffers; /* Must be a power of two */
175 u16 q_num_tx_buffers; /* Must be a power of two */
178 struct list_head vlan_list;
179 u16 configured_vlans;
180 u16 non_configured_vlans;
181 bool accept_any_vlan;
182 struct delayed_work sp_task;
183 unsigned long sp_flags;
189 struct qede_rdma_dev rdma_info;
197 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
200 #define MAX_NUM_PRI 8
202 /* The driver supports the new build_skb() API:
203 * RX ring buffer contains pointer to kmalloc() data only,
204 * skb are built only after the frame was DMA-ed.
209 unsigned int page_offset;
212 enum qede_agg_state {
213 QEDE_AGG_STATE_NONE = 0,
214 QEDE_AGG_STATE_START = 1,
215 QEDE_AGG_STATE_ERROR = 2
218 struct qede_agg_info {
219 /* rx_buf is a data buffer that can be placed / consumed from rx bd
220 * chain. It has two purposes: We will preallocate the data buffer
221 * for each aggregation when we open the interface and will place this
222 * buffer on the rx-bd-ring when we receive TPA_START. We don't want
223 * to be in a state where allocation fails, as we can't reuse the
224 * consumer buffer in the rx-chain since FW may still be writing to it
225 * (since header needs to be modified for TPA).
226 * The second purpose is to keep a pointer to the bd buffer during
229 struct sw_rx_data buffer;
230 dma_addr_t buffer_mapping;
234 /* We need some structs from the start cookie until termination */
236 u16 start_cqe_bd_len;
237 u8 start_cqe_placement_offset;
245 struct qede_rx_queue {
247 struct sw_rx_data *sw_rx_ring;
250 struct qed_chain rx_bd_ring;
251 struct qed_chain rx_comp_ring;
252 void __iomem *hw_rxq_prod_addr;
255 struct qede_agg_info tpa_info[ETH_TPA_MAX_AGGS_NUM];
258 unsigned int rx_buf_seg_size;
270 struct eth_db_data data;
277 /* Set on the first BD descriptor when there is a split BD */
278 #define QEDE_TSO_SPLIT_BD BIT(0)
281 struct qede_tx_queue {
282 int index; /* Queue index */
284 struct sw_tx_bd *sw_tx_ring;
287 struct qed_chain tx_pbl;
288 void __iomem *doorbell_addr;
298 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr.hi), \
299 le32_to_cpu((bd)->addr.lo))
300 #define BD_SET_UNMAP_ADDR_LEN(bd, maddr, len) \
302 (bd)->addr.hi = cpu_to_le32(upper_32_bits(maddr)); \
303 (bd)->addr.lo = cpu_to_le32(lower_32_bits(maddr)); \
304 (bd)->nbytes = cpu_to_le16(len); \
306 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
308 struct qede_fastpath {
309 struct qede_dev *edev;
310 #define QEDE_FASTPATH_TX BIT(0)
311 #define QEDE_FASTPATH_RX BIT(1)
312 #define QEDE_FASTPATH_COMBINED (QEDE_FASTPATH_TX | QEDE_FASTPATH_RX)
315 struct napi_struct napi;
316 struct qed_sb_info *sb_info;
317 struct qede_rx_queue *rxq;
318 struct qede_tx_queue *txq;
320 #define VEC_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
321 char name[VEC_NAME_SIZE];
324 /* Debug print definitions */
325 #define DP_NAME(edev) ((edev)->ndev->name)
328 #define XMIT_L4_CSUM BIT(0)
329 #define XMIT_LSO BIT(1)
330 #define XMIT_ENC BIT(2)
331 #define XMIT_ENC_GSO_L4_CSUM BIT(3)
333 #define QEDE_CSUM_ERROR BIT(0)
334 #define QEDE_CSUM_UNNECESSARY BIT(1)
335 #define QEDE_TUNN_CSUM_UNNECESSARY BIT(2)
337 #define QEDE_SP_RX_MODE 1
338 #define QEDE_SP_VXLAN_PORT_CONFIG 2
339 #define QEDE_SP_GENEVE_PORT_CONFIG 3
341 union qede_reload_args {
346 void qede_set_dcbnl_ops(struct net_device *ndev);
348 void qede_config_debug(uint debug, u32 *p_dp_module, u8 *p_dp_level);
349 void qede_set_ethtool_ops(struct net_device *netdev);
350 void qede_reload(struct qede_dev *edev,
351 void (*func)(struct qede_dev *edev,
352 union qede_reload_args *args),
353 union qede_reload_args *args);
354 int qede_change_mtu(struct net_device *dev, int new_mtu);
355 void qede_fill_by_demand_stats(struct qede_dev *edev);
356 bool qede_has_rx_work(struct qede_rx_queue *rxq);
357 int qede_txq_has_work(struct qede_tx_queue *txq);
358 void qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq, struct qede_dev *edev,
360 void qede_update_rx_prod(struct qede_dev *edev, struct qede_rx_queue *rxq);
362 #define RX_RING_SIZE_POW 13
363 #define RX_RING_SIZE ((u16)BIT(RX_RING_SIZE_POW))
364 #define NUM_RX_BDS_MAX (RX_RING_SIZE - 1)
365 #define NUM_RX_BDS_MIN 128
366 #define NUM_RX_BDS_DEF ((u16)BIT(10) - 1)
368 #define TX_RING_SIZE_POW 13
369 #define TX_RING_SIZE ((u16)BIT(TX_RING_SIZE_POW))
370 #define NUM_TX_BDS_MAX (TX_RING_SIZE - 1)
371 #define NUM_TX_BDS_MIN 128
372 #define NUM_TX_BDS_DEF NUM_TX_BDS_MAX
374 #define QEDE_MIN_PKT_LEN 64
375 #define QEDE_RX_HDR_SIZE 256
376 #define QEDE_MAX_JUMBO_PACKET_SIZE 9600
377 #define for_each_queue(i) for (i = 0; i < edev->num_queues; i++)
379 #endif /* _QEDE_H_ */