drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/phy.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/crc32.h>
  22 #include <linux/in.h>
  23 #include <linux/io.h>
  24 #include <linux/ip.h>
  25 #include <linux/tcp.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/firmware.h>
  30 #include <linux/prefetch.h>
  31 #include <linux/pci-aspm.h>
  32 #include <linux/ipv6.h>
  33 #include <net/ip6_checksum.h>
  34
  35 #define MODULENAME "r8169"
  36
  37 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  38 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  39 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  40 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  41 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  42 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  43 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  44 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  45 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  46 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  47 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  48 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  49 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  50 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  51 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  52 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  53 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  54 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  55 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  56
  57 #define R8169_MSG_DEFAULT \
  58         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  59
  60 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  61    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  62 static const int multicast_filter_limit = 32;
  63
  64 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  65 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  66
  67 #define R8169_REGS_SIZE         256
  68 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  69 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  70 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  71 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  72 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  73
  74 /* write/read MMIO register */
  75 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  76 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  77 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  78 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  79 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  80 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  81
  82 enum mac_version {
  83         RTL_GIGA_MAC_VER_01 = 0,
  84         RTL_GIGA_MAC_VER_02,
  85         RTL_GIGA_MAC_VER_03,
  86         RTL_GIGA_MAC_VER_04,
  87         RTL_GIGA_MAC_VER_05,
  88         RTL_GIGA_MAC_VER_06,
  89         RTL_GIGA_MAC_VER_07,
  90         RTL_GIGA_MAC_VER_08,
  91         RTL_GIGA_MAC_VER_09,
  92         RTL_GIGA_MAC_VER_10,
  93         RTL_GIGA_MAC_VER_11,
  94         RTL_GIGA_MAC_VER_12,
  95         RTL_GIGA_MAC_VER_13,
  96         RTL_GIGA_MAC_VER_14,
  97         RTL_GIGA_MAC_VER_15,
  98         RTL_GIGA_MAC_VER_16,
  99         RTL_GIGA_MAC_VER_17,
 100         RTL_GIGA_MAC_VER_18,
 101         RTL_GIGA_MAC_VER_19,
 102         RTL_GIGA_MAC_VER_20,
 103         RTL_GIGA_MAC_VER_21,
 104         RTL_GIGA_MAC_VER_22,
 105         RTL_GIGA_MAC_VER_23,
 106         RTL_GIGA_MAC_VER_24,
 107         RTL_GIGA_MAC_VER_25,
 108         RTL_GIGA_MAC_VER_26,
 109         RTL_GIGA_MAC_VER_27,
 110         RTL_GIGA_MAC_VER_28,
 111         RTL_GIGA_MAC_VER_29,
 112         RTL_GIGA_MAC_VER_30,
 113         RTL_GIGA_MAC_VER_31,
 114         RTL_GIGA_MAC_VER_32,
 115         RTL_GIGA_MAC_VER_33,
 116         RTL_GIGA_MAC_VER_34,
 117         RTL_GIGA_MAC_VER_35,
 118         RTL_GIGA_MAC_VER_36,
 119         RTL_GIGA_MAC_VER_37,
 120         RTL_GIGA_MAC_VER_38,
 121         RTL_GIGA_MAC_VER_39,
 122         RTL_GIGA_MAC_VER_40,
 123         RTL_GIGA_MAC_VER_41,
 124         RTL_GIGA_MAC_VER_42,
 125         RTL_GIGA_MAC_VER_43,
 126         RTL_GIGA_MAC_VER_44,
 127         RTL_GIGA_MAC_VER_45,
 128         RTL_GIGA_MAC_VER_46,
 129         RTL_GIGA_MAC_VER_47,
 130         RTL_GIGA_MAC_VER_48,
 131         RTL_GIGA_MAC_VER_49,
 132         RTL_GIGA_MAC_VER_50,
 133         RTL_GIGA_MAC_VER_51,
 134         RTL_GIGA_MAC_NONE   = 0xff,
 135 };
 136
 137 #define JUMBO_1K        ETH_DATA_LEN
 138 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 139 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 140 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 141 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 142
 143 static const struct {
 144         const char *name;
 145         const char *fw_name;
 146 } rtl_chip_infos[] = {
 147         /* PCI devices. */
 148         [RTL_GIGA_MAC_VER_01] = {"RTL8169"                              },
 149         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
 150         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
 151         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 152         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 153         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 154         /* PCI-E devices. */
 155         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 156         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 157         [RTL_GIGA_MAC_VER_09] = {"RTL8102e"                             },
 158         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 159         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 160         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 161         [RTL_GIGA_MAC_VER_13] = {"RTL8101e"                             },
 162         [RTL_GIGA_MAC_VER_14] = {"RTL8100e"                             },
 163         [RTL_GIGA_MAC_VER_15] = {"RTL8100e"                             },
 164         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 165         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 166         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 167         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 168         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 169         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 170         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 171         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 172         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 173         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 174         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 175         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 176         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 177         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 178         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 179         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 180         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 181         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 182         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 183         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 184         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 185         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 186         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 187         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 188         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 189         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 190         [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g",      FIRMWARE_8168G_3},
 191         [RTL_GIGA_MAC_VER_43] = {"RTL8106e",            FIRMWARE_8106E_2},
 192         [RTL_GIGA_MAC_VER_44] = {"RTL8411",             FIRMWARE_8411_2 },
 193         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 194         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 195         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 196         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 197         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 198         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 199         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 200 };
 201
 202 enum cfg_version {
 203         RTL_CFG_0 = 0x00,
 204         RTL_CFG_1,
 205         RTL_CFG_2
 206 };
 207
 208 static const struct pci_device_id rtl8169_pci_tbl[] = {
 209         { PCI_VDEVICE(REALTEK,  0x2502), RTL_CFG_1 },
 210         { PCI_VDEVICE(REALTEK,  0x2600), RTL_CFG_1 },
 211         { PCI_VDEVICE(REALTEK,  0x8129), RTL_CFG_0 },
 212         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_2 },
 213         { PCI_VDEVICE(REALTEK,  0x8161), RTL_CFG_1 },
 214         { PCI_VDEVICE(REALTEK,  0x8167), RTL_CFG_0 },
 215         { PCI_VDEVICE(REALTEK,  0x8168), RTL_CFG_1 },
 216         { PCI_VDEVICE(NCUBE,    0x8168), RTL_CFG_1 },
 217         { PCI_VDEVICE(REALTEK,  0x8169), RTL_CFG_0 },
 218         { PCI_VENDOR_ID_DLINK,  0x4300,
 219                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
 220         { PCI_VDEVICE(DLINK,    0x4300), RTL_CFG_0 },
 221         { PCI_VDEVICE(DLINK,    0x4302), RTL_CFG_0 },
 222         { PCI_VDEVICE(AT,       0xc107), RTL_CFG_0 },
 223         { PCI_VDEVICE(USR,      0x0116), RTL_CFG_0 },
 224         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 225                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 226         { 0x0001,                               0x8168,
 227                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 228         {}
 229 };
 230
 231 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 232
 233 static struct {
 234         u32 msg_enable;
 235 } debug = { -1 };
 236
 237 enum rtl_registers {
 238         MAC0            = 0,    /* Ethernet hardware address. */
 239         MAC4            = 4,
 240         MAR0            = 8,    /* Multicast filter. */
 241         CounterAddrLow          = 0x10,
 242         CounterAddrHigh         = 0x14,
 243         TxDescStartAddrLow      = 0x20,
 244         TxDescStartAddrHigh     = 0x24,
 245         TxHDescStartAddrLow     = 0x28,
 246         TxHDescStartAddrHigh    = 0x2c,
 247         FLASH           = 0x30,
 248         ERSR            = 0x36,
 249         ChipCmd         = 0x37,
 250         TxPoll          = 0x38,
 251         IntrMask        = 0x3c,
 252         IntrStatus      = 0x3e,
 253
 254         TxConfig        = 0x40,
 255 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 256 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 257
 258         RxConfig        = 0x44,
 259 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 260 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 261 #define RXCFG_FIFO_SHIFT                13
 262                                         /* No threshold before first PCI xfer */
 263 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 264 #define RX_EARLY_OFF                    (1 << 11)
 265 #define RXCFG_DMA_SHIFT                 8
 266                                         /* Unlimited maximum PCI burst. */
 267 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 268
 269         RxMissed        = 0x4c,
 270         Cfg9346         = 0x50,
 271         Config0         = 0x51,
 272         Config1         = 0x52,
 273         Config2         = 0x53,
 274 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 275
 276         Config3         = 0x54,
 277         Config4         = 0x55,
 278         Config5         = 0x56,
 279         MultiIntr       = 0x5c,
 280         PHYAR           = 0x60,
 281         PHYstatus       = 0x6c,
 282         RxMaxSize       = 0xda,
 283         CPlusCmd        = 0xe0,
 284         IntrMitigate    = 0xe2,
 285
 286 #define RTL_COALESCE_MASK       0x0f
 287 #define RTL_COALESCE_SHIFT      4
 288 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 289 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 290
 291         RxDescAddrLow   = 0xe4,
 292         RxDescAddrHigh  = 0xe8,
 293         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 294
 295 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 296
 297         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 298
 299 #define TxPacketMax     (8064 >> 7)
 300 #define EarlySize       0x27
 301
 302         FuncEvent       = 0xf0,
 303         FuncEventMask   = 0xf4,
 304         FuncPresetState = 0xf8,
 305         IBCR0           = 0xf8,
 306         IBCR2           = 0xf9,
 307         IBIMR0          = 0xfa,
 308         IBISR0          = 0xfb,
 309         FuncForceEvent  = 0xfc,
 310 };
 311
 312 enum rtl8168_8101_registers {
 313         CSIDR                   = 0x64,
 314         CSIAR                   = 0x68,
 315 #define CSIAR_FLAG                      0x80000000
 316 #define CSIAR_WRITE_CMD                 0x80000000
 317 #define CSIAR_BYTE_ENABLE               0x0000f000
 318 #define CSIAR_ADDR_MASK                 0x00000fff
 319         PMCH                    = 0x6f,
 320         EPHYAR                  = 0x80,
 321 #define EPHYAR_FLAG                     0x80000000
 322 #define EPHYAR_WRITE_CMD                0x80000000
 323 #define EPHYAR_REG_MASK                 0x1f
 324 #define EPHYAR_REG_SHIFT                16
 325 #define EPHYAR_DATA_MASK                0xffff
 326         DLLPR                   = 0xd0,
 327 #define PFM_EN                          (1 << 6)
 328 #define TX_10M_PS_EN                    (1 << 7)
 329         DBG_REG                 = 0xd1,
 330 #define FIX_NAK_1                       (1 << 4)
 331 #define FIX_NAK_2                       (1 << 3)
 332         TWSI                    = 0xd2,
 333         MCU                     = 0xd3,
 334 #define NOW_IS_OOB                      (1 << 7)
 335 #define TX_EMPTY                        (1 << 5)
 336 #define RX_EMPTY                        (1 << 4)
 337 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 338 #define EN_NDP                          (1 << 3)
 339 #define EN_OOB_RESET                    (1 << 2)
 340 #define LINK_LIST_RDY                   (1 << 1)
 341         EFUSEAR                 = 0xdc,
 342 #define EFUSEAR_FLAG                    0x80000000
 343 #define EFUSEAR_WRITE_CMD               0x80000000
 344 #define EFUSEAR_READ_CMD                0x00000000
 345 #define EFUSEAR_REG_MASK                0x03ff
 346 #define EFUSEAR_REG_SHIFT               8
 347 #define EFUSEAR_DATA_MASK               0xff
 348         MISC_1                  = 0xf2,
 349 #define PFM_D3COLD_EN                   (1 << 6)
 350 };
 351
 352 enum rtl8168_registers {
 353         LED_FREQ                = 0x1a,
 354         EEE_LED                 = 0x1b,
 355         ERIDR                   = 0x70,
 356         ERIAR                   = 0x74,
 357 #define ERIAR_FLAG                      0x80000000
 358 #define ERIAR_WRITE_CMD                 0x80000000
 359 #define ERIAR_READ_CMD                  0x00000000
 360 #define ERIAR_ADDR_BYTE_ALIGN           4
 361 #define ERIAR_TYPE_SHIFT                16
 362 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 363 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 364 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 365 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 366 #define ERIAR_MASK_SHIFT                12
 367 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 368 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 369 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 370 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 371 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 372         EPHY_RXER_NUM           = 0x7c,
 373         OCPDR                   = 0xb0, /* OCP GPHY access */
 374 #define OCPDR_WRITE_CMD                 0x80000000
 375 #define OCPDR_READ_CMD                  0x00000000
 376 #define OCPDR_REG_MASK                  0x7f
 377 #define OCPDR_GPHY_REG_SHIFT            16
 378 #define OCPDR_DATA_MASK                 0xffff
 379         OCPAR                   = 0xb4,
 380 #define OCPAR_FLAG                      0x80000000
 381 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 382 #define OCPAR_GPHY_READ_CMD             0x0000f060
 383         GPHY_OCP                = 0xb8,
 384         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 385         MISC                    = 0xf0, /* 8168e only. */
 386 #define TXPLA_RST                       (1 << 29)
 387 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 388 #define PWM_EN                          (1 << 22)
 389 #define RXDV_GATED_EN                   (1 << 19)
 390 #define EARLY_TALLY_EN                  (1 << 16)
 391 };
 392
 393 enum rtl_register_content {
 394         /* InterruptStatusBits */
 395         SYSErr          = 0x8000,
 396         PCSTimeout      = 0x4000,
 397         SWInt           = 0x0100,
 398         TxDescUnavail   = 0x0080,
 399         RxFIFOOver      = 0x0040,
 400         LinkChg         = 0x0020,
 401         RxOverflow      = 0x0010,
 402         TxErr           = 0x0008,
 403         TxOK            = 0x0004,
 404         RxErr           = 0x0002,
 405         RxOK            = 0x0001,
 406
 407         /* RxStatusDesc */
 408         RxBOVF  = (1 << 24),
 409         RxFOVF  = (1 << 23),
 410         RxRWT   = (1 << 22),
 411         RxRES   = (1 << 21),
 412         RxRUNT  = (1 << 20),
 413         RxCRC   = (1 << 19),
 414
 415         /* ChipCmdBits */
 416         StopReq         = 0x80,
 417         CmdReset        = 0x10,
 418         CmdRxEnb        = 0x08,
 419         CmdTxEnb        = 0x04,
 420         RxBufEmpty      = 0x01,
 421
 422         /* TXPoll register p.5 */
 423         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 424         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 425         FSWInt          = 0x01,         /* Forced software interrupt */
 426
 427         /* Cfg9346Bits */
 428         Cfg9346_Lock    = 0x00,
 429         Cfg9346_Unlock  = 0xc0,
 430
 431         /* rx_mode_bits */
 432         AcceptErr       = 0x20,
 433         AcceptRunt      = 0x10,
 434         AcceptBroadcast = 0x08,
 435         AcceptMulticast = 0x04,
 436         AcceptMyPhys    = 0x02,
 437         AcceptAllPhys   = 0x01,
 438 #define RX_CONFIG_ACCEPT_MASK           0x3f
 439
 440         /* TxConfigBits */
 441         TxInterFrameGapShift = 24,
 442         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 443
 444         /* Config1 register p.24 */
 445         LEDS1           = (1 << 7),
 446         LEDS0           = (1 << 6),
 447         Speed_down      = (1 << 4),
 448         MEMMAP          = (1 << 3),
 449         IOMAP           = (1 << 2),
 450         VPD             = (1 << 1),
 451         PMEnable        = (1 << 0),     /* Power Management Enable */
 452
 453         /* Config2 register p. 25 */
 454         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 455         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 456         PCI_Clock_66MHz = 0x01,
 457         PCI_Clock_33MHz = 0x00,
 458
 459         /* Config3 register p.25 */
 460         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 461         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 462         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 463         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 464         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 465
 466         /* Config4 register */
 467         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 468
 469         /* Config5 register p.27 */
 470         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 471         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 472         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 473         Spi_en          = (1 << 3),
 474         LanWake         = (1 << 1),     /* LanWake enable/disable */
 475         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 476         ASPM_en         = (1 << 0),     /* ASPM enable */
 477
 478         /* CPlusCmd p.31 */
 479         EnableBist      = (1 << 15),    // 8168 8101
 480         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 481         Normal_mode     = (1 << 13),    // unused
 482         Force_half_dup  = (1 << 12),    // 8168 8101
 483         Force_rxflow_en = (1 << 11),    // 8168 8101
 484         Force_txflow_en = (1 << 10),    // 8168 8101
 485         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 486         ASF             = (1 << 8),     // 8168 8101
 487         PktCntrDisable  = (1 << 7),     // 8168 8101
 488         Mac_dbgo_sel    = 0x001c,       // 8168
 489         RxVlan          = (1 << 6),
 490         RxChkSum        = (1 << 5),
 491         PCIDAC          = (1 << 4),
 492         PCIMulRW        = (1 << 3),
 493 #define INTT_MASK       GENMASK(1, 0)
 494
 495         /* rtl8169_PHYstatus */
 496         TBI_Enable      = 0x80,
 497         TxFlowCtrl      = 0x40,
 498         RxFlowCtrl      = 0x20,
 499         _1000bpsF       = 0x10,
 500         _100bps         = 0x08,
 501         _10bps          = 0x04,
 502         LinkStatus      = 0x02,
 503         FullDup         = 0x01,
 504
 505         /* _TBICSRBit */
 506         TBILinkOK       = 0x02000000,
 507
 508         /* ResetCounterCommand */
 509         CounterReset    = 0x1,
 510
 511         /* DumpCounterCommand */
 512         CounterDump     = 0x8,
 513
 514         /* magic enable v2 */
 515         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 516 };
 517
 518 enum rtl_desc_bit {
 519         /* First doubleword. */
 520         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 521         RingEnd         = (1 << 30), /* End of descriptor ring */
 522         FirstFrag       = (1 << 29), /* First segment of a packet */
 523         LastFrag        = (1 << 28), /* Final segment of a packet */
 524 };
 525
 526 /* Generic case. */
 527 enum rtl_tx_desc_bit {
 528         /* First doubleword. */
 529         TD_LSO          = (1 << 27),            /* Large Send Offload */
 530 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 531
 532         /* Second doubleword. */
 533         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 534 };
 535
 536 /* 8169, 8168b and 810x except 8102e. */
 537 enum rtl_tx_desc_bit_0 {
 538         /* First doubleword. */
 539 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 540         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 541         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 542         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 543 };
 544
 545 /* 8102e, 8168c and beyond. */
 546 enum rtl_tx_desc_bit_1 {
 547         /* First doubleword. */
 548         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 549         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 550 #define GTTCPHO_SHIFT                   18
 551 #define GTTCPHO_MAX                     0x7fU
 552
 553         /* Second doubleword. */
 554 #define TCPHO_SHIFT                     18
 555 #define TCPHO_MAX                       0x3ffU
 556 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 557         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 558         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 559         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 560         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 561 };
 562
 563 enum rtl_rx_desc_bit {
 564         /* Rx private */
 565         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 566         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 567
 568 #define RxProtoUDP      (PID1)
 569 #define RxProtoTCP      (PID0)
 570 #define RxProtoIP       (PID1 | PID0)
 571 #define RxProtoMask     RxProtoIP
 572
 573         IPFail          = (1 << 16), /* IP checksum failed */
 574         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 575         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 576         RxVlanTag       = (1 << 16), /* VLAN tag available */
 577 };
 578
 579 #define RsvdMask        0x3fffc000
 580 #define CPCMD_QUIRK_MASK        (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 581
 582 struct TxDesc {
 583         __le32 opts1;
 584         __le32 opts2;
 585         __le64 addr;
 586 };
 587
 588 struct RxDesc {
 589         __le32 opts1;
 590         __le32 opts2;
 591         __le64 addr;
 592 };
 593
 594 struct ring_info {
 595         struct sk_buff  *skb;
 596         u32             len;
 597 };
 598
 599 struct rtl8169_counters {
 600         __le64  tx_packets;
 601         __le64  rx_packets;
 602         __le64  tx_errors;
 603         __le32  rx_errors;
 604         __le16  rx_missed;
 605         __le16  align_errors;
 606         __le32  tx_one_collision;
 607         __le32  tx_multi_collision;
 608         __le64  rx_unicast;
 609         __le64  rx_broadcast;
 610         __le32  rx_multicast;
 611         __le16  tx_aborted;
 612         __le16  tx_underun;
 613 };
 614
 615 struct rtl8169_tc_offsets {
 616         bool    inited;
 617         __le64  tx_errors;
 618         __le32  tx_multi_collision;
 619         __le16  tx_aborted;
 620 };
 621
 622 enum rtl_flag {
 623         RTL_FLAG_TASK_ENABLED = 0,
 624         RTL_FLAG_TASK_RESET_PENDING,
 625         RTL_FLAG_MAX
 626 };
 627
 628 struct rtl8169_stats {
 629         u64                     packets;
 630         u64                     bytes;
 631         struct u64_stats_sync   syncp;
 632 };
 633
 634 struct rtl8169_private {
 635         void __iomem *mmio_addr;        /* memory map physical address */
 636         struct pci_dev *pci_dev;
 637         struct net_device *dev;
 638         struct phy_device *phydev;
 639         struct napi_struct napi;
 640         u32 msg_enable;
 641         u16 mac_version;
 642         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 643         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 644         u32 dirty_tx;
 645         struct rtl8169_stats rx_stats;
 646         struct rtl8169_stats tx_stats;
 647         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 648         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 649         dma_addr_t TxPhyAddr;
 650         dma_addr_t RxPhyAddr;
 651         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 652         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 653         u16 cp_cmd;
 654
 655         u16 irq_mask;
 656         const struct rtl_coalesce_info *coalesce_info;
 657         struct clk *clk;
 658
 659         struct mdio_ops {
 660                 void (*write)(struct rtl8169_private *, int, int);
 661                 int (*read)(struct rtl8169_private *, int);
 662         } mdio_ops;
 663
 664         struct jumbo_ops {
 665                 void (*enable)(struct rtl8169_private *);
 666                 void (*disable)(struct rtl8169_private *);
 667         } jumbo_ops;
 668
 669         void (*hw_start)(struct rtl8169_private *tp);
 670         bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
 671
 672         struct {
 673                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 674                 struct mutex mutex;
 675                 struct work_struct work;
 676         } wk;
 677
 678         unsigned irq_enabled:1;
 679         unsigned supports_gmii:1;
 680         dma_addr_t counters_phys_addr;
 681         struct rtl8169_counters *counters;
 682         struct rtl8169_tc_offsets tc_offset;
 683         u32 saved_wolopts;
 684
 685         const char *fw_name;
 686         struct rtl_fw {
 687                 const struct firmware *fw;
 688
 689 #define RTL_VER_SIZE            32
 690
 691                 char version[RTL_VER_SIZE];
 692
 693                 struct rtl_fw_phy_action {
 694                         __le32 *code;
 695                         size_t size;
 696                 } phy_action;
 697         } *rtl_fw;
 698
 699         u32 ocp_base;
 700 };
 701
 702 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 703
 704 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 705 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 706 module_param_named(debug, debug.msg_enable, int, 0);
 707 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 708 MODULE_SOFTDEP("pre: realtek");
 709 MODULE_LICENSE("GPL");
 710 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 711 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 712 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 713 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 714 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 715 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 716 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 717 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 718 MODULE_FIRMWARE(FIRMWARE_8402_1);
 719 MODULE_FIRMWARE(FIRMWARE_8411_1);
 720 MODULE_FIRMWARE(FIRMWARE_8411_2);
 721 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 722 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 723 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 724 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 725 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 726 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 727 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 728 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 729
 730 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 731 {
 732         return &tp->pci_dev->dev;
 733 }
 734
 735 static void rtl_lock_work(struct rtl8169_private *tp)
 736 {
 737         mutex_lock(&tp->wk.mutex);
 738 }
 739
 740 static void rtl_unlock_work(struct rtl8169_private *tp)
 741 {
 742         mutex_unlock(&tp->wk.mutex);
 743 }
 744
 745 static void rtl_lock_config_regs(struct rtl8169_private *tp)
 746 {
 747         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 748 }
 749
 750 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 751 {
 752         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 753 }
 754
 755 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 756 {
 757         pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 758                                            PCI_EXP_DEVCTL_READRQ, force);
 759 }
 760
 761 struct rtl_cond {
 762         bool (*check)(struct rtl8169_private *);
 763         const char *msg;
 764 };
 765
 766 static void rtl_udelay(unsigned int d)
 767 {
 768         udelay(d);
 769 }
 770
 771 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 772                           void (*delay)(unsigned int), unsigned int d, int n,
 773                           bool high)
 774 {
 775         int i;
 776
 777         for (i = 0; i < n; i++) {
 778                 if (c->check(tp) == high)
 779                         return true;
 780                 delay(d);
 781         }
 782         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 783                   c->msg, !high, n, d);
 784         return false;
 785 }
 786
 787 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 788                                       const struct rtl_cond *c,
 789                                       unsigned int d, int n)
 790 {
 791         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 792 }
 793
 794 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 795                                      const struct rtl_cond *c,
 796                                      unsigned int d, int n)
 797 {
 798         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 799 }
 800
 801 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 802                                       const struct rtl_cond *c,
 803                                       unsigned int d, int n)
 804 {
 805         return rtl_loop_wait(tp, c, msleep, d, n, true);
 806 }
 807
 808 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 809                                      const struct rtl_cond *c,
 810                                      unsigned int d, int n)
 811 {
 812         return rtl_loop_wait(tp, c, msleep, d, n, false);
 813 }
 814
 815 #define DECLARE_RTL_COND(name)                          \
 816 static bool name ## _check(struct rtl8169_private *);   \
 817                                                         \
 818 static const struct rtl_cond name = {                   \
 819         .check  = name ## _check,                       \
 820         .msg    = #name                                 \
 821 };                                                      \
 822                                                         \
 823 static bool name ## _check(struct rtl8169_private *tp)
 824
 825 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 826 {
 827         if (reg & 0xffff0001) {
 828                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 829                 return true;
 830         }
 831         return false;
 832 }
 833
 834 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 835 {
 836         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 837 }
 838
 839 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 840 {
 841         if (rtl_ocp_reg_failure(tp, reg))
 842                 return;
 843
 844         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 845
 846         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 847 }
 848
 849 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 850 {
 851         if (rtl_ocp_reg_failure(tp, reg))
 852                 return 0;
 853
 854         RTL_W32(tp, GPHY_OCP, reg << 15);
 855
 856         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 857                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
 858 }
 859
 860 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 861 {
 862         if (rtl_ocp_reg_failure(tp, reg))
 863                 return;
 864
 865         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 866 }
 867
 868 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 869 {
 870         if (rtl_ocp_reg_failure(tp, reg))
 871                 return 0;
 872
 873         RTL_W32(tp, OCPDR, reg << 15);
 874
 875         return RTL_R32(tp, OCPDR);
 876 }
 877
 878 #define OCP_STD_PHY_BASE        0xa400
 879
 880 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 881 {
 882         if (reg == 0x1f) {
 883                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 884                 return;
 885         }
 886
 887         if (tp->ocp_base != OCP_STD_PHY_BASE)
 888                 reg -= 0x10;
 889
 890         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 891 }
 892
 893 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 894 {
 895         if (tp->ocp_base != OCP_STD_PHY_BASE)
 896                 reg -= 0x10;
 897
 898         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 899 }
 900
 901 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 902 {
 903         if (reg == 0x1f) {
 904                 tp->ocp_base = value << 4;
 905                 return;
 906         }
 907
 908         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 909 }
 910
 911 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 912 {
 913         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 914 }
 915
 916 DECLARE_RTL_COND(rtl_phyar_cond)
 917 {
 918         return RTL_R32(tp, PHYAR) & 0x80000000;
 919 }
 920
 921 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 922 {
 923         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 924
 925         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 926         /*
 927          * According to hardware specs a 20us delay is required after write
 928          * complete indication, but before sending next command.
 929          */
 930         udelay(20);
 931 }
 932
 933 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 934 {
 935         int value;
 936
 937         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 938
 939         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 940                 RTL_R32(tp, PHYAR) & 0xffff : ~0;
 941
 942         /*
 943          * According to hardware specs a 20us delay is required after read
 944          * complete indication, but before sending next command.
 945          */
 946         udelay(20);
 947
 948         return value;
 949 }
 950
 951 DECLARE_RTL_COND(rtl_ocpar_cond)
 952 {
 953         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 954 }
 955
 956 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 957 {
 958         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 959         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 960         RTL_W32(tp, EPHY_RXER_NUM, 0);
 961
 962         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 963 }
 964
 965 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 966 {
 967         r8168dp_1_mdio_access(tp, reg,
 968                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
 969 }
 970
 971 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
 972 {
 973         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
 974
 975         mdelay(1);
 976         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
 977         RTL_W32(tp, EPHY_RXER_NUM, 0);
 978
 979         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
 980                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
 981 }
 982
 983 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 984
 985 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
 986 {
 987         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 988 }
 989
 990 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
 991 {
 992         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 993 }
 994
 995 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
 996 {
 997         r8168dp_2_mdio_start(tp);
 998
 999         r8169_mdio_write(tp, reg, value);
1000
1001         r8168dp_2_mdio_stop(tp);
1002 }
1003
1004 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1005 {
1006         int value;
1007
1008         r8168dp_2_mdio_start(tp);
1009
1010         value = r8169_mdio_read(tp, reg);
1011
1012         r8168dp_2_mdio_stop(tp);
1013
1014         return value;
1015 }
1016
1017 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1018 {
1019         tp->mdio_ops.write(tp, location, val);
1020 }
1021
1022 static int rtl_readphy(struct rtl8169_private *tp, int location)
1023 {
1024         return tp->mdio_ops.read(tp, location);
1025 }
1026
1027 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1028 {
1029         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1030 }
1031
1032 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1033 {
1034         int val;
1035
1036         val = rtl_readphy(tp, reg_addr);
1037         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1038 }
1039
1040 DECLARE_RTL_COND(rtl_ephyar_cond)
1041 {
1042         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1043 }
1044
1045 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1046 {
1047         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1048                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1049
1050         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1051
1052         udelay(10);
1053 }
1054
1055 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1056 {
1057         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1058
1059         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1060                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1061 }
1062
1063 DECLARE_RTL_COND(rtl_eriar_cond)
1064 {
1065         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1066 }
1067
1068 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1069                            u32 val, int type)
1070 {
1071         BUG_ON((addr & 3) || (mask == 0));
1072         RTL_W32(tp, ERIDR, val);
1073         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1074
1075         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1076 }
1077
1078 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1079                           u32 val)
1080 {
1081         _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1082 }
1083
1084 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1085 {
1086         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1087
1088         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1089                 RTL_R32(tp, ERIDR) : ~0;
1090 }
1091
1092 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1093 {
1094         return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1095 }
1096
1097 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1098                          u32 m)
1099 {
1100         u32 val;
1101
1102         val = rtl_eri_read(tp, addr);
1103         rtl_eri_write(tp, addr, mask, (val & ~m) | p);
1104 }
1105
1106 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1107                              u32 p)
1108 {
1109         rtl_w0w1_eri(tp, addr, mask, p, 0);
1110 }
1111
1112 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1113                                u32 m)
1114 {
1115         rtl_w0w1_eri(tp, addr, mask, 0, m);
1116 }
1117
1118 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1119 {
1120         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1121         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1122                 RTL_R32(tp, OCPDR) : ~0;
1123 }
1124
1125 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1126 {
1127         return _rtl_eri_read(tp, reg, ERIAR_OOB);
1128 }
1129
1130 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1131                               u32 data)
1132 {
1133         RTL_W32(tp, OCPDR, data);
1134         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1135         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1136 }
1137
1138 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1139                               u32 data)
1140 {
1141         _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1142                        data, ERIAR_OOB);
1143 }
1144
1145 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1146 {
1147         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1148
1149         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1150 }
1151
1152 #define OOB_CMD_RESET           0x00
1153 #define OOB_CMD_DRIVER_START    0x05
1154 #define OOB_CMD_DRIVER_STOP     0x06
1155
1156 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1157 {
1158         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1159 }
1160
1161 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1162 {
1163         u16 reg;
1164
1165         reg = rtl8168_get_ocp_reg(tp);
1166
1167         return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1168 }
1169
1170 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1171 {
1172         return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1173 }
1174
1175 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1176 {
1177         return RTL_R8(tp, IBISR0) & 0x20;
1178 }
1179
1180 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1181 {
1182         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1183         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1184         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1185         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1186 }
1187
1188 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1189 {
1190         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1191         rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1192 }
1193
1194 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1195 {
1196         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1197         r8168ep_ocp_write(tp, 0x01, 0x30,
1198                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1199         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1200 }
1201
1202 static void rtl8168_driver_start(struct rtl8169_private *tp)
1203 {
1204         switch (tp->mac_version) {
1205         case RTL_GIGA_MAC_VER_27:
1206         case RTL_GIGA_MAC_VER_28:
1207         case RTL_GIGA_MAC_VER_31:
1208                 rtl8168dp_driver_start(tp);
1209                 break;
1210         case RTL_GIGA_MAC_VER_49:
1211         case RTL_GIGA_MAC_VER_50:
1212         case RTL_GIGA_MAC_VER_51:
1213                 rtl8168ep_driver_start(tp);
1214                 break;
1215         default:
1216                 BUG();
1217                 break;
1218         }
1219 }
1220
1221 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1222 {
1223         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1224         rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1225 }
1226
1227 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1228 {
1229         rtl8168ep_stop_cmac(tp);
1230         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1231         r8168ep_ocp_write(tp, 0x01, 0x30,
1232                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1233         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1234 }
1235
1236 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1237 {
1238         switch (tp->mac_version) {
1239         case RTL_GIGA_MAC_VER_27:
1240         case RTL_GIGA_MAC_VER_28:
1241         case RTL_GIGA_MAC_VER_31:
1242                 rtl8168dp_driver_stop(tp);
1243                 break;
1244         case RTL_GIGA_MAC_VER_49:
1245         case RTL_GIGA_MAC_VER_50:
1246         case RTL_GIGA_MAC_VER_51:
1247                 rtl8168ep_driver_stop(tp);
1248                 break;
1249         default:
1250                 BUG();
1251                 break;
1252         }
1253 }
1254
1255 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1256 {
1257         u16 reg = rtl8168_get_ocp_reg(tp);
1258
1259         return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1260 }
1261
1262 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1263 {
1264         return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1265 }
1266
1267 static bool r8168_check_dash(struct rtl8169_private *tp)
1268 {
1269         switch (tp->mac_version) {
1270         case RTL_GIGA_MAC_VER_27:
1271         case RTL_GIGA_MAC_VER_28:
1272         case RTL_GIGA_MAC_VER_31:
1273                 return r8168dp_check_dash(tp);
1274         case RTL_GIGA_MAC_VER_49:
1275         case RTL_GIGA_MAC_VER_50:
1276         case RTL_GIGA_MAC_VER_51:
1277                 return r8168ep_check_dash(tp);
1278         default:
1279                 return false;
1280         }
1281 }
1282
1283 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1284 {
1285         rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1286         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1287 }
1288
1289 DECLARE_RTL_COND(rtl_efusear_cond)
1290 {
1291         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1292 }
1293
1294 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1295 {
1296         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1297
1298         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1299                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1300 }
1301
1302 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1303 {
1304         RTL_W16(tp, IntrStatus, bits);
1305 }
1306
1307 static void rtl_irq_disable(struct rtl8169_private *tp)
1308 {
1309         RTL_W16(tp, IntrMask, 0);
1310         tp->irq_enabled = 0;
1311 }
1312
1313 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1314 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1315 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1316
1317 static void rtl_irq_enable(struct rtl8169_private *tp)
1318 {
1319         tp->irq_enabled = 1;
1320         RTL_W16(tp, IntrMask, tp->irq_mask);
1321 }
1322
1323 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1324 {
1325         rtl_irq_disable(tp);
1326         rtl_ack_events(tp, 0xffff);
1327         /* PCI commit */
1328         RTL_R8(tp, ChipCmd);
1329 }
1330
1331 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1332 {
1333         struct net_device *dev = tp->dev;
1334         struct phy_device *phydev = tp->phydev;
1335
1336         if (!netif_running(dev))
1337                 return;
1338
1339         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1340             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1341                 if (phydev->speed == SPEED_1000) {
1342                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1343                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1344                 } else if (phydev->speed == SPEED_100) {
1345                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1346                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1347                 } else {
1348                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1349                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1350                 }
1351                 rtl_reset_packet_filter(tp);
1352         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1353                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1354                 if (phydev->speed == SPEED_1000) {
1355                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1356                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1357                 } else {
1358                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1359                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1360                 }
1361         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1362                 if (phydev->speed == SPEED_10) {
1363                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1364                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1365                 } else {
1366                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1367                 }
1368         }
1369 }
1370
1371 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1372
1373 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1374 {
1375         struct rtl8169_private *tp = netdev_priv(dev);
1376
1377         rtl_lock_work(tp);
1378         wol->supported = WAKE_ANY;
1379         wol->wolopts = tp->saved_wolopts;
1380         rtl_unlock_work(tp);
1381 }
1382
1383 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1384 {
1385         unsigned int i, tmp;
1386         static const struct {
1387                 u32 opt;
1388                 u16 reg;
1389                 u8  mask;
1390         } cfg[] = {
1391                 { WAKE_PHY,   Config3, LinkUp },
1392                 { WAKE_UCAST, Config5, UWF },
1393                 { WAKE_BCAST, Config5, BWF },
1394                 { WAKE_MCAST, Config5, MWF },
1395                 { WAKE_ANY,   Config5, LanWake },
1396                 { WAKE_MAGIC, Config3, MagicPacket }
1397         };
1398         u8 options;
1399
1400         rtl_unlock_config_regs(tp);
1401
1402         switch (tp->mac_version) {
1403         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1404         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1405                 tmp = ARRAY_SIZE(cfg) - 1;
1406                 if (wolopts & WAKE_MAGIC)
1407                         rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1408                                          MagicPacket_v2);
1409                 else
1410                         rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1411                                            MagicPacket_v2);
1412                 break;
1413         default:
1414                 tmp = ARRAY_SIZE(cfg);
1415                 break;
1416         }
1417
1418         for (i = 0; i < tmp; i++) {
1419                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1420                 if (wolopts & cfg[i].opt)
1421                         options |= cfg[i].mask;
1422                 RTL_W8(tp, cfg[i].reg, options);
1423         }
1424
1425         switch (tp->mac_version) {
1426         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1427                 options = RTL_R8(tp, Config1) & ~PMEnable;
1428                 if (wolopts)
1429                         options |= PMEnable;
1430                 RTL_W8(tp, Config1, options);
1431                 break;
1432         default:
1433                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1434                 if (wolopts)
1435                         options |= PME_SIGNAL;
1436                 RTL_W8(tp, Config2, options);
1437                 break;
1438         }
1439
1440         rtl_lock_config_regs(tp);
1441
1442         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1443 }
1444
1445 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1446 {
1447         struct rtl8169_private *tp = netdev_priv(dev);
1448         struct device *d = tp_to_dev(tp);
1449
1450         if (wol->wolopts & ~WAKE_ANY)
1451                 return -EINVAL;
1452
1453         pm_runtime_get_noresume(d);
1454
1455         rtl_lock_work(tp);
1456
1457         tp->saved_wolopts = wol->wolopts;
1458
1459         if (pm_runtime_active(d))
1460                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1461
1462         rtl_unlock_work(tp);
1463
1464         pm_runtime_put_noidle(d);
1465
1466         return 0;
1467 }
1468
1469 static void rtl8169_get_drvinfo(struct net_device *dev,
1470                                 struct ethtool_drvinfo *info)
1471 {
1472         struct rtl8169_private *tp = netdev_priv(dev);
1473         struct rtl_fw *rtl_fw = tp->rtl_fw;
1474
1475         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1476         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1477         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1478         if (rtl_fw)
1479                 strlcpy(info->fw_version, rtl_fw->version,
1480                         sizeof(info->fw_version));
1481 }
1482
1483 static int rtl8169_get_regs_len(struct net_device *dev)
1484 {
1485         return R8169_REGS_SIZE;
1486 }
1487
1488 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1489         netdev_features_t features)
1490 {
1491         struct rtl8169_private *tp = netdev_priv(dev);
1492
1493         if (dev->mtu > TD_MSS_MAX)
1494                 features &= ~NETIF_F_ALL_TSO;
1495
1496         if (dev->mtu > JUMBO_1K &&
1497             tp->mac_version > RTL_GIGA_MAC_VER_06)
1498                 features &= ~NETIF_F_IP_CSUM;
1499
1500         return features;
1501 }
1502
1503 static int rtl8169_set_features(struct net_device *dev,
1504                                 netdev_features_t features)
1505 {
1506         struct rtl8169_private *tp = netdev_priv(dev);
1507         u32 rx_config;
1508
1509         rtl_lock_work(tp);
1510
1511         rx_config = RTL_R32(tp, RxConfig);
1512         if (features & NETIF_F_RXALL)
1513                 rx_config |= (AcceptErr | AcceptRunt);
1514         else
1515                 rx_config &= ~(AcceptErr | AcceptRunt);
1516
1517         RTL_W32(tp, RxConfig, rx_config);
1518
1519         if (features & NETIF_F_RXCSUM)
1520                 tp->cp_cmd |= RxChkSum;
1521         else
1522                 tp->cp_cmd &= ~RxChkSum;
1523
1524         if (features & NETIF_F_HW_VLAN_CTAG_RX)
1525                 tp->cp_cmd |= RxVlan;
1526         else
1527                 tp->cp_cmd &= ~RxVlan;
1528
1529         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1530         RTL_R16(tp, CPlusCmd);
1531
1532         rtl_unlock_work(tp);
1533
1534         return 0;
1535 }
1536
1537 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1538 {
1539         return (skb_vlan_tag_present(skb)) ?
1540                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1541 }
1542
1543 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1544 {
1545         u32 opts2 = le32_to_cpu(desc->opts2);
1546
1547         if (opts2 & RxVlanTag)
1548                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1549 }
1550
1551 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1552                              void *p)
1553 {
1554         struct rtl8169_private *tp = netdev_priv(dev);
1555         u32 __iomem *data = tp->mmio_addr;
1556         u32 *dw = p;
1557         int i;
1558
1559         rtl_lock_work(tp);
1560         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1561                 memcpy_fromio(dw++, data++, 4);
1562         rtl_unlock_work(tp);
1563 }
1564
1565 static u32 rtl8169_get_msglevel(struct net_device *dev)
1566 {
1567         struct rtl8169_private *tp = netdev_priv(dev);
1568
1569         return tp->msg_enable;
1570 }
1571
1572 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1573 {
1574         struct rtl8169_private *tp = netdev_priv(dev);
1575
1576         tp->msg_enable = value;
1577 }
1578
1579 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1580         "tx_packets",
1581         "rx_packets",
1582         "tx_errors",
1583         "rx_errors",
1584         "rx_missed",
1585         "align_errors",
1586         "tx_single_collisions",
1587         "tx_multi_collisions",
1588         "unicast",
1589         "broadcast",
1590         "multicast",
1591         "tx_aborted",
1592         "tx_underrun",
1593 };
1594
1595 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1596 {
1597         switch (sset) {
1598         case ETH_SS_STATS:
1599                 return ARRAY_SIZE(rtl8169_gstrings);
1600         default:
1601                 return -EOPNOTSUPP;
1602         }
1603 }
1604
1605 DECLARE_RTL_COND(rtl_counters_cond)
1606 {
1607         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1608 }
1609
1610 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1611 {
1612         dma_addr_t paddr = tp->counters_phys_addr;
1613         u32 cmd;
1614
1615         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1616         RTL_R32(tp, CounterAddrHigh);
1617         cmd = (u64)paddr & DMA_BIT_MASK(32);
1618         RTL_W32(tp, CounterAddrLow, cmd);
1619         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1620
1621         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1622 }
1623
1624 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1625 {
1626         /*
1627          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1628          * tally counters.
1629          */
1630         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1631                 return true;
1632
1633         return rtl8169_do_counters(tp, CounterReset);
1634 }
1635
1636 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1637 {
1638         u8 val = RTL_R8(tp, ChipCmd);
1639
1640         /*
1641          * Some chips are unable to dump tally counters when the receiver
1642          * is disabled. If 0xff chip may be in a PCI power-save state.
1643          */
1644         if (!(val & CmdRxEnb) || val == 0xff)
1645                 return true;
1646
1647         return rtl8169_do_counters(tp, CounterDump);
1648 }
1649
1650 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1651 {
1652         struct rtl8169_counters *counters = tp->counters;
1653         bool ret = false;
1654
1655         /*
1656          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1657          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1658          * reset by a power cycle, while the counter values collected by the
1659          * driver are reset at every driver unload/load cycle.
1660          *
1661          * To make sure the HW values returned by @get_stats64 match the SW
1662          * values, we collect the initial values at first open(*) and use them
1663          * as offsets to normalize the values returned by @get_stats64.
1664          *
1665          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1666          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1667          * set at open time by rtl_hw_start.
1668          */
1669
1670         if (tp->tc_offset.inited)
1671                 return true;
1672
1673         /* If both, reset and update fail, propagate to caller. */
1674         if (rtl8169_reset_counters(tp))
1675                 ret = true;
1676
1677         if (rtl8169_update_counters(tp))
1678                 ret = true;
1679
1680         tp->tc_offset.tx_errors = counters->tx_errors;
1681         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1682         tp->tc_offset.tx_aborted = counters->tx_aborted;
1683         tp->tc_offset.inited = true;
1684
1685         return ret;
1686 }
1687
1688 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1689                                       struct ethtool_stats *stats, u64 *data)
1690 {
1691         struct rtl8169_private *tp = netdev_priv(dev);
1692         struct device *d = tp_to_dev(tp);
1693         struct rtl8169_counters *counters = tp->counters;
1694
1695         ASSERT_RTNL();
1696
1697         pm_runtime_get_noresume(d);
1698
1699         if (pm_runtime_active(d))
1700                 rtl8169_update_counters(tp);
1701
1702         pm_runtime_put_noidle(d);
1703
1704         data[0] = le64_to_cpu(counters->tx_packets);
1705         data[1] = le64_to_cpu(counters->rx_packets);
1706         data[2] = le64_to_cpu(counters->tx_errors);
1707         data[3] = le32_to_cpu(counters->rx_errors);
1708         data[4] = le16_to_cpu(counters->rx_missed);
1709         data[5] = le16_to_cpu(counters->align_errors);
1710         data[6] = le32_to_cpu(counters->tx_one_collision);
1711         data[7] = le32_to_cpu(counters->tx_multi_collision);
1712         data[8] = le64_to_cpu(counters->rx_unicast);
1713         data[9] = le64_to_cpu(counters->rx_broadcast);
1714         data[10] = le32_to_cpu(counters->rx_multicast);
1715         data[11] = le16_to_cpu(counters->tx_aborted);
1716         data[12] = le16_to_cpu(counters->tx_underun);
1717 }
1718
1719 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1720 {
1721         switch(stringset) {
1722         case ETH_SS_STATS:
1723                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1724                 break;
1725         }
1726 }
1727
1728 /*
1729  * Interrupt coalescing
1730  *
1731  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1732  * >     8169, 8168 and 810x line of chipsets
1733  *
1734  * 8169, 8168, and 8136(810x) serial chipsets support it.
1735  *
1736  * > 2 - the Tx timer unit at gigabit speed
1737  *
1738  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1739  * (0xe0) bit 1 and bit 0.
1740  *
1741  * For 8169
1742  * bit[1:0] \ speed        1000M           100M            10M
1743  * 0 0                     320ns           2.56us          40.96us
1744  * 0 1                     2.56us          20.48us         327.7us
1745  * 1 0                     5.12us          40.96us         655.4us
1746  * 1 1                     10.24us         81.92us         1.31ms
1747  *
1748  * For the other
1749  * bit[1:0] \ speed        1000M           100M            10M
1750  * 0 0                     5us             2.56us          40.96us
1751  * 0 1                     40us            20.48us         327.7us
1752  * 1 0                     80us            40.96us         655.4us
1753  * 1 1                     160us           81.92us         1.31ms
1754  */
1755
1756 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1757 struct rtl_coalesce_scale {
1758         /* Rx / Tx */
1759         u32 nsecs[2];
1760 };
1761
1762 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1763 struct rtl_coalesce_info {
1764         u32 speed;
1765         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1766 };
1767
1768 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1769 #define rxtx_x1822(r, t) {              \
1770         {{(r),          (t)}},          \
1771         {{(r)*8,        (t)*8}},        \
1772         {{(r)*8*2,      (t)*8*2}},      \
1773         {{(r)*8*2*2,    (t)*8*2*2}},    \
1774 }
1775 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1776         /* speed        delays:     rx00   tx00 */
1777         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1778         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1779         { SPEED_1000,   rxtx_x1822(  320,   320)        },
1780         { 0 },
1781 };
1782
1783 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1784         /* speed        delays:     rx00   tx00 */
1785         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1786         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1787         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1788         { 0 },
1789 };
1790 #undef rxtx_x1822
1791
1792 /* get rx/tx scale vector corresponding to current speed */
1793 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1794 {
1795         struct rtl8169_private *tp = netdev_priv(dev);
1796         struct ethtool_link_ksettings ecmd;
1797         const struct rtl_coalesce_info *ci;
1798         int rc;
1799
1800         rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1801         if (rc < 0)
1802                 return ERR_PTR(rc);
1803
1804         for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1805                 if (ecmd.base.speed == ci->speed) {
1806                         return ci;
1807                 }
1808         }
1809
1810         return ERR_PTR(-ELNRNG);
1811 }
1812
1813 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1814 {
1815         struct rtl8169_private *tp = netdev_priv(dev);
1816         const struct rtl_coalesce_info *ci;
1817         const struct rtl_coalesce_scale *scale;
1818         struct {
1819                 u32 *max_frames;
1820                 u32 *usecs;
1821         } coal_settings [] = {
1822                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1823                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1824         }, *p = coal_settings;
1825         int i;
1826         u16 w;
1827
1828         memset(ec, 0, sizeof(*ec));
1829
1830         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1831         ci = rtl_coalesce_info(dev);
1832         if (IS_ERR(ci))
1833                 return PTR_ERR(ci);
1834
1835         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1836
1837         /* read IntrMitigate and adjust according to scale */
1838         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1839                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1840                 w >>= RTL_COALESCE_SHIFT;
1841                 *p->usecs = w & RTL_COALESCE_MASK;
1842         }
1843
1844         for (i = 0; i < 2; i++) {
1845                 p = coal_settings + i;
1846                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1847
1848                 /*
1849                  * ethtool_coalesce says it is illegal to set both usecs and
1850                  * max_frames to 0.
1851                  */
1852                 if (!*p->usecs && !*p->max_frames)
1853                         *p->max_frames = 1;
1854         }
1855
1856         return 0;
1857 }
1858
1859 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1860 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1861                         struct net_device *dev, u32 nsec, u16 *cp01)
1862 {
1863         const struct rtl_coalesce_info *ci;
1864         u16 i;
1865
1866         ci = rtl_coalesce_info(dev);
1867         if (IS_ERR(ci))
1868                 return ERR_CAST(ci);
1869
1870         for (i = 0; i < 4; i++) {
1871                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1872                                         ci->scalev[i].nsecs[1]);
1873                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1874                         *cp01 = i;
1875                         return &ci->scalev[i];
1876                 }
1877         }
1878
1879         return ERR_PTR(-EINVAL);
1880 }
1881
1882 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1883 {
1884         struct rtl8169_private *tp = netdev_priv(dev);
1885         const struct rtl_coalesce_scale *scale;
1886         struct {
1887                 u32 frames;
1888                 u32 usecs;
1889         } coal_settings [] = {
1890                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1891                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1892         }, *p = coal_settings;
1893         u16 w = 0, cp01;
1894         int i;
1895
1896         scale = rtl_coalesce_choose_scale(dev,
1897                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1898         if (IS_ERR(scale))
1899                 return PTR_ERR(scale);
1900
1901         for (i = 0; i < 2; i++, p++) {
1902                 u32 units;
1903
1904                 /*
1905                  * accept max_frames=1 we returned in rtl_get_coalesce.
1906                  * accept it not only when usecs=0 because of e.g. the following scenario:
1907                  *
1908                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1909                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1910                  * - then user does `ethtool -C eth0 rx-usecs 100`
1911                  *
1912                  * since ethtool sends to kernel whole ethtool_coalesce
1913                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
1914                  * we'll reject it below in `frames % 4 != 0`.
1915                  */
1916                 if (p->frames == 1) {
1917                         p->frames = 0;
1918                 }
1919
1920                 units = p->usecs * 1000 / scale->nsecs[i];
1921                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1922                         return -EINVAL;
1923
1924                 w <<= RTL_COALESCE_SHIFT;
1925                 w |= units;
1926                 w <<= RTL_COALESCE_SHIFT;
1927                 w |= p->frames >> 2;
1928         }
1929
1930         rtl_lock_work(tp);
1931
1932         RTL_W16(tp, IntrMitigate, swab16(w));
1933
1934         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1935         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1936         RTL_R16(tp, CPlusCmd);
1937
1938         rtl_unlock_work(tp);
1939
1940         return 0;
1941 }
1942
1943 static int rtl_get_eee_supp(struct rtl8169_private *tp)
1944 {
1945         struct phy_device *phydev = tp->phydev;
1946         int ret;
1947
1948         switch (tp->mac_version) {
1949         case RTL_GIGA_MAC_VER_34:
1950         case RTL_GIGA_MAC_VER_35:
1951         case RTL_GIGA_MAC_VER_36:
1952         case RTL_GIGA_MAC_VER_38:
1953                 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1954                 break;
1955         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1956                 phy_write(phydev, 0x1f, 0x0a5c);
1957                 ret = phy_read(phydev, 0x12);
1958                 phy_write(phydev, 0x1f, 0x0000);
1959                 break;
1960         default:
1961                 ret = -EPROTONOSUPPORT;
1962                 break;
1963         }
1964
1965         return ret;
1966 }
1967
1968 static int rtl_get_eee_lpadv(struct rtl8169_private *tp)
1969 {
1970         struct phy_device *phydev = tp->phydev;
1971         int ret;
1972
1973         switch (tp->mac_version) {
1974         case RTL_GIGA_MAC_VER_34:
1975         case RTL_GIGA_MAC_VER_35:
1976         case RTL_GIGA_MAC_VER_36:
1977         case RTL_GIGA_MAC_VER_38:
1978                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
1979                 break;
1980         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1981                 phy_write(phydev, 0x1f, 0x0a5d);
1982                 ret = phy_read(phydev, 0x11);
1983                 phy_write(phydev, 0x1f, 0x0000);
1984                 break;
1985         default:
1986                 ret = -EPROTONOSUPPORT;
1987                 break;
1988         }
1989
1990         return ret;
1991 }
1992
1993 static int rtl_get_eee_adv(struct rtl8169_private *tp)
1994 {
1995         struct phy_device *phydev = tp->phydev;
1996         int ret;
1997
1998         switch (tp->mac_version) {
1999         case RTL_GIGA_MAC_VER_34:
2000         case RTL_GIGA_MAC_VER_35:
2001         case RTL_GIGA_MAC_VER_36:
2002         case RTL_GIGA_MAC_VER_38:
2003                 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
2004                 break;
2005         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2006                 phy_write(phydev, 0x1f, 0x0a5d);
2007                 ret = phy_read(phydev, 0x10);
2008                 phy_write(phydev, 0x1f, 0x0000);
2009                 break;
2010         default:
2011                 ret = -EPROTONOSUPPORT;
2012                 break;
2013         }
2014
2015         return ret;
2016 }
2017
2018 static int rtl_set_eee_adv(struct rtl8169_private *tp, int val)
2019 {
2020         struct phy_device *phydev = tp->phydev;
2021         int ret = 0;
2022
2023         switch (tp->mac_version) {
2024         case RTL_GIGA_MAC_VER_34:
2025         case RTL_GIGA_MAC_VER_35:
2026         case RTL_GIGA_MAC_VER_36:
2027         case RTL_GIGA_MAC_VER_38:
2028                 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
2029                 break;
2030         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
2031                 phy_write(phydev, 0x1f, 0x0a5d);
2032                 phy_write(phydev, 0x10, val);
2033                 phy_write(phydev, 0x1f, 0x0000);
2034                 break;
2035         default:
2036                 ret = -EPROTONOSUPPORT;
2037                 break;
2038         }
2039
2040         return ret;
2041 }
2042
2043 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2044 {
2045         struct rtl8169_private *tp = netdev_priv(dev);
2046         struct device *d = tp_to_dev(tp);
2047         int ret;
2048
2049         pm_runtime_get_noresume(d);
2050
2051         if (!pm_runtime_active(d)) {
2052                 ret = -EOPNOTSUPP;
2053                 goto out;
2054         }
2055
2056         /* Get Supported EEE */
2057         ret = rtl_get_eee_supp(tp);
2058         if (ret < 0)
2059                 goto out;
2060         data->supported = mmd_eee_cap_to_ethtool_sup_t(ret);
2061
2062         /* Get advertisement EEE */
2063         ret = rtl_get_eee_adv(tp);
2064         if (ret < 0)
2065                 goto out;
2066         data->advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2067         data->eee_enabled = !!data->advertised;
2068
2069         /* Get LP advertisement EEE */
2070         ret = rtl_get_eee_lpadv(tp);
2071         if (ret < 0)
2072                 goto out;
2073         data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(ret);
2074         data->eee_active = !!(data->advertised & data->lp_advertised);
2075 out:
2076         pm_runtime_put_noidle(d);
2077         return ret < 0 ? ret : 0;
2078 }
2079
2080 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2081 {
2082         struct rtl8169_private *tp = netdev_priv(dev);
2083         struct device *d = tp_to_dev(tp);
2084         int old_adv, adv = 0, cap, ret;
2085
2086         pm_runtime_get_noresume(d);
2087
2088         if (!dev->phydev || !pm_runtime_active(d)) {
2089                 ret = -EOPNOTSUPP;
2090                 goto out;
2091         }
2092
2093         if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2094             dev->phydev->duplex != DUPLEX_FULL) {
2095                 ret = -EPROTONOSUPPORT;
2096                 goto out;
2097         }
2098
2099         /* Get Supported EEE */
2100         ret = rtl_get_eee_supp(tp);
2101         if (ret < 0)
2102                 goto out;
2103         cap = ret;
2104
2105         ret = rtl_get_eee_adv(tp);
2106         if (ret < 0)
2107                 goto out;
2108         old_adv = ret;
2109
2110         if (data->eee_enabled) {
2111                 adv = !data->advertised ? cap :
2112                       ethtool_adv_to_mmd_eee_adv_t(data->advertised) & cap;
2113                 /* Mask prohibited EEE modes */
2114                 adv &= ~dev->phydev->eee_broken_modes;
2115         }
2116
2117         if (old_adv != adv) {
2118                 ret = rtl_set_eee_adv(tp, adv);
2119                 if (ret < 0)
2120                         goto out;
2121
2122                 /* Restart autonegotiation so the new modes get sent to the
2123                  * link partner.
2124                  */
2125                 ret = phy_restart_aneg(dev->phydev);
2126         }
2127
2128 out:
2129         pm_runtime_put_noidle(d);
2130         return ret < 0 ? ret : 0;
2131 }
2132
2133 static const struct ethtool_ops rtl8169_ethtool_ops = {
2134         .get_drvinfo            = rtl8169_get_drvinfo,
2135         .get_regs_len           = rtl8169_get_regs_len,
2136         .get_link               = ethtool_op_get_link,
2137         .get_coalesce           = rtl_get_coalesce,
2138         .set_coalesce           = rtl_set_coalesce,
2139         .get_msglevel           = rtl8169_get_msglevel,
2140         .set_msglevel           = rtl8169_set_msglevel,
2141         .get_regs               = rtl8169_get_regs,
2142         .get_wol                = rtl8169_get_wol,
2143         .set_wol                = rtl8169_set_wol,
2144         .get_strings            = rtl8169_get_strings,
2145         .get_sset_count         = rtl8169_get_sset_count,
2146         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2147         .get_ts_info            = ethtool_op_get_ts_info,
2148         .nway_reset             = phy_ethtool_nway_reset,
2149         .get_eee                = rtl8169_get_eee,
2150         .set_eee                = rtl8169_set_eee,
2151         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2152         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2153 };
2154
2155 static void rtl_enable_eee(struct rtl8169_private *tp)
2156 {
2157         int supported = rtl_get_eee_supp(tp);
2158
2159         if (supported > 0)
2160                 rtl_set_eee_adv(tp, supported);
2161 }
2162
2163 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2164 {
2165         /*
2166          * The driver currently handles the 8168Bf and the 8168Be identically
2167          * but they can be identified more specifically through the test below
2168          * if needed:
2169          *
2170          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2171          *
2172          * Same thing for the 8101Eb and the 8101Ec:
2173          *
2174          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2175          */
2176         static const struct rtl_mac_info {
2177                 u16 mask;
2178                 u16 val;
2179                 u16 mac_version;
2180         } mac_info[] = {
2181                 /* 8168EP family. */
2182                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2183                 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2184                 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2185
2186                 /* 8168H family. */
2187                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2188                 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2189
2190                 /* 8168G family. */
2191                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2192                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2193                 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2194                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2195
2196                 /* 8168F family. */
2197                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2198                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2199                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2200
2201                 /* 8168E family. */
2202                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2203                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2204                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2205
2206                 /* 8168D family. */
2207                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2208                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2209
2210                 /* 8168DP family. */
2211                 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2212                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2213                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2214
2215                 /* 8168C family. */
2216                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2217                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2218                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2219                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2220                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2221                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2222                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2223
2224                 /* 8168B family. */
2225                 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2226                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2227                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2228
2229                 /* 8101 family. */
2230                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2231                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2232                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2233                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2234                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2235                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2236                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2237                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2238                 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2239                 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2240                 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2241                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2242                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2243                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2244                 /* FIXME: where did these entries come from ? -- FR */
2245                 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2246                 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2247
2248                 /* 8110 family. */
2249                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2250                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2251                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2252                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2253                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2254                 { 0xfc8, 0x000, RTL_GIGA_MAC_VER_01 },
2255
2256                 /* Catch-all */
2257                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2258         };
2259         const struct rtl_mac_info *p = mac_info;
2260         u16 reg = RTL_R32(tp, TxConfig) >> 20;
2261
2262         while ((reg & p->mask) != p->val)
2263                 p++;
2264         tp->mac_version = p->mac_version;
2265
2266         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2267                 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2268         } else if (!tp->supports_gmii) {
2269                 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2270                         tp->mac_version = RTL_GIGA_MAC_VER_43;
2271                 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2272                         tp->mac_version = RTL_GIGA_MAC_VER_47;
2273                 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2274                         tp->mac_version = RTL_GIGA_MAC_VER_48;
2275         }
2276 }
2277
2278 struct phy_reg {
2279         u16 reg;
2280         u16 val;
2281 };
2282
2283 static void __rtl_writephy_batch(struct rtl8169_private *tp,
2284                                  const struct phy_reg *regs, int len)
2285 {
2286         while (len-- > 0) {
2287                 rtl_writephy(tp, regs->reg, regs->val);
2288                 regs++;
2289         }
2290 }
2291
2292 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2293
2294 #define PHY_READ                0x00000000
2295 #define PHY_DATA_OR             0x10000000
2296 #define PHY_DATA_AND            0x20000000
2297 #define PHY_BJMPN               0x30000000
2298 #define PHY_MDIO_CHG            0x40000000
2299 #define PHY_CLEAR_READCOUNT     0x70000000
2300 #define PHY_WRITE               0x80000000
2301 #define PHY_READCOUNT_EQ_SKIP   0x90000000
2302 #define PHY_COMP_EQ_SKIPN       0xa0000000
2303 #define PHY_COMP_NEQ_SKIPN      0xb0000000
2304 #define PHY_WRITE_PREVIOUS      0xc0000000
2305 #define PHY_SKIPN               0xd0000000
2306 #define PHY_DELAY_MS            0xe0000000
2307
2308 struct fw_info {
2309         u32     magic;
2310         char    version[RTL_VER_SIZE];
2311         __le32  fw_start;
2312         __le32  fw_len;
2313         u8      chksum;
2314 } __packed;
2315
2316 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2317
2318 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2319 {
2320         const struct firmware *fw = rtl_fw->fw;
2321         struct fw_info *fw_info = (struct fw_info *)fw->data;
2322         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2323         char *version = rtl_fw->version;
2324         bool rc = false;
2325
2326         if (fw->size < FW_OPCODE_SIZE)
2327                 goto out;
2328
2329         if (!fw_info->magic) {
2330                 size_t i, size, start;
2331                 u8 checksum = 0;
2332
2333                 if (fw->size < sizeof(*fw_info))
2334                         goto out;
2335
2336                 for (i = 0; i < fw->size; i++)
2337                         checksum += fw->data[i];
2338                 if (checksum != 0)
2339                         goto out;
2340
2341                 start = le32_to_cpu(fw_info->fw_start);
2342                 if (start > fw->size)
2343                         goto out;
2344
2345                 size = le32_to_cpu(fw_info->fw_len);
2346                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2347                         goto out;
2348
2349                 memcpy(version, fw_info->version, RTL_VER_SIZE);
2350
2351                 pa->code = (__le32 *)(fw->data + start);
2352                 pa->size = size;
2353         } else {
2354                 if (fw->size % FW_OPCODE_SIZE)
2355                         goto out;
2356
2357                 strlcpy(version, tp->fw_name, RTL_VER_SIZE);
2358
2359                 pa->code = (__le32 *)fw->data;
2360                 pa->size = fw->size / FW_OPCODE_SIZE;
2361         }
2362         version[RTL_VER_SIZE - 1] = 0;
2363
2364         rc = true;
2365 out:
2366         return rc;
2367 }
2368
2369 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2370                            struct rtl_fw_phy_action *pa)
2371 {
2372         bool rc = false;
2373         size_t index;
2374
2375         for (index = 0; index < pa->size; index++) {
2376                 u32 action = le32_to_cpu(pa->code[index]);
2377                 u32 regno = (action & 0x0fff0000) >> 16;
2378
2379                 switch(action & 0xf0000000) {
2380                 case PHY_READ:
2381                 case PHY_DATA_OR:
2382                 case PHY_DATA_AND:
2383                 case PHY_MDIO_CHG:
2384                 case PHY_CLEAR_READCOUNT:
2385                 case PHY_WRITE:
2386                 case PHY_WRITE_PREVIOUS:
2387                 case PHY_DELAY_MS:
2388                         break;
2389
2390                 case PHY_BJMPN:
2391                         if (regno > index) {
2392                                 netif_err(tp, ifup, tp->dev,
2393                                           "Out of range of firmware\n");
2394                                 goto out;
2395                         }
2396                         break;
2397                 case PHY_READCOUNT_EQ_SKIP:
2398                         if (index + 2 >= pa->size) {
2399                                 netif_err(tp, ifup, tp->dev,
2400                                           "Out of range of firmware\n");
2401                                 goto out;
2402                         }
2403                         break;
2404                 case PHY_COMP_EQ_SKIPN:
2405                 case PHY_COMP_NEQ_SKIPN:
2406                 case PHY_SKIPN:
2407                         if (index + 1 + regno >= pa->size) {
2408                                 netif_err(tp, ifup, tp->dev,
2409                                           "Out of range of firmware\n");
2410                                 goto out;
2411                         }
2412                         break;
2413
2414                 default:
2415                         netif_err(tp, ifup, tp->dev,
2416                                   "Invalid action 0x%08x\n", action);
2417                         goto out;
2418                 }
2419         }
2420         rc = true;
2421 out:
2422         return rc;
2423 }
2424
2425 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2426 {
2427         struct net_device *dev = tp->dev;
2428         int rc = -EINVAL;
2429
2430         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2431                 netif_err(tp, ifup, dev, "invalid firmware\n");
2432                 goto out;
2433         }
2434
2435         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2436                 rc = 0;
2437 out:
2438         return rc;
2439 }
2440
2441 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2442 {
2443         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2444         struct mdio_ops org, *ops = &tp->mdio_ops;
2445         u32 predata, count;
2446         size_t index;
2447
2448         predata = count = 0;
2449         org.write = ops->write;
2450         org.read = ops->read;
2451
2452         for (index = 0; index < pa->size; ) {
2453                 u32 action = le32_to_cpu(pa->code[index]);
2454                 u32 data = action & 0x0000ffff;
2455                 u32 regno = (action & 0x0fff0000) >> 16;
2456
2457                 if (!action)
2458                         break;
2459
2460                 switch(action & 0xf0000000) {
2461                 case PHY_READ:
2462                         predata = rtl_readphy(tp, regno);
2463                         count++;
2464                         index++;
2465                         break;
2466                 case PHY_DATA_OR:
2467                         predata |= data;
2468                         index++;
2469                         break;
2470                 case PHY_DATA_AND:
2471                         predata &= data;
2472                         index++;
2473                         break;
2474                 case PHY_BJMPN:
2475                         index -= regno;
2476                         break;
2477                 case PHY_MDIO_CHG:
2478                         if (data == 0) {
2479                                 ops->write = org.write;
2480                                 ops->read = org.read;
2481                         } else if (data == 1) {
2482                                 ops->write = mac_mcu_write;
2483                                 ops->read = mac_mcu_read;
2484                         }
2485
2486                         index++;
2487                         break;
2488                 case PHY_CLEAR_READCOUNT:
2489                         count = 0;
2490                         index++;
2491                         break;
2492                 case PHY_WRITE:
2493                         rtl_writephy(tp, regno, data);
2494                         index++;
2495                         break;
2496                 case PHY_READCOUNT_EQ_SKIP:
2497                         index += (count == data) ? 2 : 1;
2498                         break;
2499                 case PHY_COMP_EQ_SKIPN:
2500                         if (predata == data)
2501                                 index += regno;
2502                         index++;
2503                         break;
2504                 case PHY_COMP_NEQ_SKIPN:
2505                         if (predata != data)
2506                                 index += regno;
2507                         index++;
2508                         break;
2509                 case PHY_WRITE_PREVIOUS:
2510                         rtl_writephy(tp, regno, predata);
2511                         index++;
2512                         break;
2513                 case PHY_SKIPN:
2514                         index += regno + 1;
2515                         break;
2516                 case PHY_DELAY_MS:
2517                         mdelay(data);
2518                         index++;
2519                         break;
2520
2521                 default:
2522                         BUG();
2523                 }
2524         }
2525
2526         ops->write = org.write;
2527         ops->read = org.read;
2528 }
2529
2530 static void rtl_release_firmware(struct rtl8169_private *tp)
2531 {
2532         if (tp->rtl_fw) {
2533                 release_firmware(tp->rtl_fw->fw);
2534                 kfree(tp->rtl_fw);
2535                 tp->rtl_fw = NULL;
2536         }
2537 }
2538
2539 static void rtl_apply_firmware(struct rtl8169_private *tp)
2540 {
2541         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2542         if (tp->rtl_fw)
2543                 rtl_phy_write_fw(tp, tp->rtl_fw);
2544 }
2545
2546 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2547 {
2548         if (rtl_readphy(tp, reg) != val)
2549                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2550         else
2551                 rtl_apply_firmware(tp);
2552 }
2553
2554 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2555 {
2556         /* Adjust EEE LED frequency */
2557         if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2558                 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2559
2560         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
2561 }
2562
2563 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2564 {
2565         struct phy_device *phydev = tp->phydev;
2566
2567         phy_write(phydev, 0x1f, 0x0007);
2568         phy_write(phydev, 0x1e, 0x0020);
2569         phy_set_bits(phydev, 0x15, BIT(8));
2570
2571         phy_write(phydev, 0x1f, 0x0005);
2572         phy_write(phydev, 0x05, 0x8b85);
2573         phy_set_bits(phydev, 0x06, BIT(13));
2574
2575         phy_write(phydev, 0x1f, 0x0000);
2576 }
2577
2578 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2579 {
2580         phy_write(tp->phydev, 0x1f, 0x0a43);
2581         phy_set_bits(tp->phydev, 0x11, BIT(4));
2582         phy_write(tp->phydev, 0x1f, 0x0000);
2583 }
2584
2585 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2586 {
2587         static const struct phy_reg phy_reg_init[] = {
2588                 { 0x1f, 0x0001 },
2589                 { 0x06, 0x006e },
2590                 { 0x08, 0x0708 },
2591                 { 0x15, 0x4000 },
2592                 { 0x18, 0x65c7 },
2593
2594                 { 0x1f, 0x0001 },
2595                 { 0x03, 0x00a1 },
2596                 { 0x02, 0x0008 },
2597                 { 0x01, 0x0120 },
2598                 { 0x00, 0x1000 },
2599                 { 0x04, 0x0800 },
2600                 { 0x04, 0x0000 },
2601
2602                 { 0x03, 0xff41 },
2603                 { 0x02, 0xdf60 },
2604                 { 0x01, 0x0140 },
2605                 { 0x00, 0x0077 },
2606                 { 0x04, 0x7800 },
2607                 { 0x04, 0x7000 },
2608
2609                 { 0x03, 0x802f },
2610                 { 0x02, 0x4f02 },
2611                 { 0x01, 0x0409 },
2612                 { 0x00, 0xf0f9 },
2613                 { 0x04, 0x9800 },
2614                 { 0x04, 0x9000 },
2615
2616                 { 0x03, 0xdf01 },
2617                 { 0x02, 0xdf20 },
2618                 { 0x01, 0xff95 },
2619                 { 0x00, 0xba00 },
2620                 { 0x04, 0xa800 },
2621                 { 0x04, 0xa000 },
2622
2623                 { 0x03, 0xff41 },
2624                 { 0x02, 0xdf20 },
2625                 { 0x01, 0x0140 },
2626                 { 0x00, 0x00bb },
2627                 { 0x04, 0xb800 },
2628                 { 0x04, 0xb000 },
2629
2630                 { 0x03, 0xdf41 },
2631                 { 0x02, 0xdc60 },
2632                 { 0x01, 0x6340 },
2633                 { 0x00, 0x007d },
2634                 { 0x04, 0xd800 },
2635                 { 0x04, 0xd000 },
2636
2637                 { 0x03, 0xdf01 },
2638                 { 0x02, 0xdf20 },
2639                 { 0x01, 0x100a },
2640                 { 0x00, 0xa0ff },
2641                 { 0x04, 0xf800 },
2642                 { 0x04, 0xf000 },
2643
2644                 { 0x1f, 0x0000 },
2645                 { 0x0b, 0x0000 },
2646                 { 0x00, 0x9200 }
2647         };
2648
2649         rtl_writephy_batch(tp, phy_reg_init);
2650 }
2651
2652 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2653 {
2654         static const struct phy_reg phy_reg_init[] = {
2655                 { 0x1f, 0x0002 },
2656                 { 0x01, 0x90d0 },
2657                 { 0x1f, 0x0000 }
2658         };
2659
2660         rtl_writephy_batch(tp, phy_reg_init);
2661 }
2662
2663 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2664 {
2665         struct pci_dev *pdev = tp->pci_dev;
2666
2667         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2668             (pdev->subsystem_device != 0xe000))
2669                 return;
2670
2671         rtl_writephy(tp, 0x1f, 0x0001);
2672         rtl_writephy(tp, 0x10, 0xf01b);
2673         rtl_writephy(tp, 0x1f, 0x0000);
2674 }
2675
2676 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2677 {
2678         static const struct phy_reg phy_reg_init[] = {
2679                 { 0x1f, 0x0001 },
2680                 { 0x04, 0x0000 },
2681                 { 0x03, 0x00a1 },
2682                 { 0x02, 0x0008 },
2683                 { 0x01, 0x0120 },
2684                 { 0x00, 0x1000 },
2685                 { 0x04, 0x0800 },
2686                 { 0x04, 0x9000 },
2687                 { 0x03, 0x802f },
2688                 { 0x02, 0x4f02 },
2689                 { 0x01, 0x0409 },
2690                 { 0x00, 0xf099 },
2691                 { 0x04, 0x9800 },
2692                 { 0x04, 0xa000 },
2693                 { 0x03, 0xdf01 },
2694                 { 0x02, 0xdf20 },
2695                 { 0x01, 0xff95 },
2696                 { 0x00, 0xba00 },
2697                 { 0x04, 0xa800 },
2698                 { 0x04, 0xf000 },
2699                 { 0x03, 0xdf01 },
2700                 { 0x02, 0xdf20 },
2701                 { 0x01, 0x101a },
2702                 { 0x00, 0xa0ff },
2703                 { 0x04, 0xf800 },
2704                 { 0x04, 0x0000 },
2705                 { 0x1f, 0x0000 },
2706
2707                 { 0x1f, 0x0001 },
2708                 { 0x10, 0xf41b },
2709                 { 0x14, 0xfb54 },
2710                 { 0x18, 0xf5c7 },
2711                 { 0x1f, 0x0000 },
2712
2713                 { 0x1f, 0x0001 },
2714                 { 0x17, 0x0cc0 },
2715                 { 0x1f, 0x0000 }
2716         };
2717
2718         rtl_writephy_batch(tp, phy_reg_init);
2719
2720         rtl8169scd_hw_phy_config_quirk(tp);
2721 }
2722
2723 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2724 {
2725         static const struct phy_reg phy_reg_init[] = {
2726                 { 0x1f, 0x0001 },
2727                 { 0x04, 0x0000 },
2728                 { 0x03, 0x00a1 },
2729                 { 0x02, 0x0008 },
2730                 { 0x01, 0x0120 },
2731                 { 0x00, 0x1000 },
2732                 { 0x04, 0x0800 },
2733                 { 0x04, 0x9000 },
2734                 { 0x03, 0x802f },
2735                 { 0x02, 0x4f02 },
2736                 { 0x01, 0x0409 },
2737                 { 0x00, 0xf099 },
2738                 { 0x04, 0x9800 },
2739                 { 0x04, 0xa000 },
2740                 { 0x03, 0xdf01 },
2741                 { 0x02, 0xdf20 },
2742                 { 0x01, 0xff95 },
2743                 { 0x00, 0xba00 },
2744                 { 0x04, 0xa800 },
2745                 { 0x04, 0xf000 },
2746                 { 0x03, 0xdf01 },
2747                 { 0x02, 0xdf20 },
2748                 { 0x01, 0x101a },
2749                 { 0x00, 0xa0ff },
2750                 { 0x04, 0xf800 },
2751                 { 0x04, 0x0000 },
2752                 { 0x1f, 0x0000 },
2753
2754                 { 0x1f, 0x0001 },
2755                 { 0x0b, 0x8480 },
2756                 { 0x1f, 0x0000 },
2757
2758                 { 0x1f, 0x0001 },
2759                 { 0x18, 0x67c7 },
2760                 { 0x04, 0x2000 },
2761                 { 0x03, 0x002f },
2762                 { 0x02, 0x4360 },
2763                 { 0x01, 0x0109 },
2764                 { 0x00, 0x3022 },
2765                 { 0x04, 0x2800 },
2766                 { 0x1f, 0x0000 },
2767
2768                 { 0x1f, 0x0001 },
2769                 { 0x17, 0x0cc0 },
2770                 { 0x1f, 0x0000 }
2771         };
2772
2773         rtl_writephy_batch(tp, phy_reg_init);
2774 }
2775
2776 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2777 {
2778         static const struct phy_reg phy_reg_init[] = {
2779                 { 0x10, 0xf41b },
2780                 { 0x1f, 0x0000 }
2781         };
2782
2783         rtl_writephy(tp, 0x1f, 0x0001);
2784         rtl_patchphy(tp, 0x16, 1 << 0);
2785
2786         rtl_writephy_batch(tp, phy_reg_init);
2787 }
2788
2789 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2790 {
2791         static const struct phy_reg phy_reg_init[] = {
2792                 { 0x1f, 0x0001 },
2793                 { 0x10, 0xf41b },
2794                 { 0x1f, 0x0000 }
2795         };
2796
2797         rtl_writephy_batch(tp, phy_reg_init);
2798 }
2799
2800 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2801 {
2802         static const struct phy_reg phy_reg_init[] = {
2803                 { 0x1f, 0x0000 },
2804                 { 0x1d, 0x0f00 },
2805                 { 0x1f, 0x0002 },
2806                 { 0x0c, 0x1ec8 },
2807                 { 0x1f, 0x0000 }
2808         };
2809
2810         rtl_writephy_batch(tp, phy_reg_init);
2811 }
2812
2813 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2814 {
2815         static const struct phy_reg phy_reg_init[] = {
2816                 { 0x1f, 0x0001 },
2817                 { 0x1d, 0x3d98 },
2818                 { 0x1f, 0x0000 }
2819         };
2820
2821         rtl_writephy(tp, 0x1f, 0x0000);
2822         rtl_patchphy(tp, 0x14, 1 << 5);
2823         rtl_patchphy(tp, 0x0d, 1 << 5);
2824
2825         rtl_writephy_batch(tp, phy_reg_init);
2826 }
2827
2828 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2829 {
2830         static const struct phy_reg phy_reg_init[] = {
2831                 { 0x1f, 0x0001 },
2832                 { 0x12, 0x2300 },
2833                 { 0x1f, 0x0002 },
2834                 { 0x00, 0x88d4 },
2835                 { 0x01, 0x82b1 },
2836                 { 0x03, 0x7002 },
2837                 { 0x08, 0x9e30 },
2838                 { 0x09, 0x01f0 },
2839                 { 0x0a, 0x5500 },
2840                 { 0x0c, 0x00c8 },
2841                 { 0x1f, 0x0003 },
2842                 { 0x12, 0xc096 },
2843                 { 0x16, 0x000a },
2844                 { 0x1f, 0x0000 },
2845                 { 0x1f, 0x0000 },
2846                 { 0x09, 0x2000 },
2847                 { 0x09, 0x0000 }
2848         };
2849
2850         rtl_writephy_batch(tp, phy_reg_init);
2851
2852         rtl_patchphy(tp, 0x14, 1 << 5);
2853         rtl_patchphy(tp, 0x0d, 1 << 5);
2854         rtl_writephy(tp, 0x1f, 0x0000);
2855 }
2856
2857 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2858 {
2859         static const struct phy_reg phy_reg_init[] = {
2860                 { 0x1f, 0x0001 },
2861                 { 0x12, 0x2300 },
2862                 { 0x03, 0x802f },
2863                 { 0x02, 0x4f02 },
2864                 { 0x01, 0x0409 },
2865                 { 0x00, 0xf099 },
2866                 { 0x04, 0x9800 },
2867                 { 0x04, 0x9000 },
2868                 { 0x1d, 0x3d98 },
2869                 { 0x1f, 0x0002 },
2870                 { 0x0c, 0x7eb8 },
2871                 { 0x06, 0x0761 },
2872                 { 0x1f, 0x0003 },
2873                 { 0x16, 0x0f0a },
2874                 { 0x1f, 0x0000 }
2875         };
2876
2877         rtl_writephy_batch(tp, phy_reg_init);
2878
2879         rtl_patchphy(tp, 0x16, 1 << 0);
2880         rtl_patchphy(tp, 0x14, 1 << 5);
2881         rtl_patchphy(tp, 0x0d, 1 << 5);
2882         rtl_writephy(tp, 0x1f, 0x0000);
2883 }
2884
2885 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2886 {
2887         static const struct phy_reg phy_reg_init[] = {
2888                 { 0x1f, 0x0001 },
2889                 { 0x12, 0x2300 },
2890                 { 0x1d, 0x3d98 },
2891                 { 0x1f, 0x0002 },
2892                 { 0x0c, 0x7eb8 },
2893                 { 0x06, 0x5461 },
2894                 { 0x1f, 0x0003 },
2895                 { 0x16, 0x0f0a },
2896                 { 0x1f, 0x0000 }
2897         };
2898
2899         rtl_writephy_batch(tp, phy_reg_init);
2900
2901         rtl_patchphy(tp, 0x16, 1 << 0);
2902         rtl_patchphy(tp, 0x14, 1 << 5);
2903         rtl_patchphy(tp, 0x0d, 1 << 5);
2904         rtl_writephy(tp, 0x1f, 0x0000);
2905 }
2906
2907 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2908 {
2909         rtl8168c_3_hw_phy_config(tp);
2910 }
2911
2912 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2913 {
2914         static const struct phy_reg phy_reg_init_0[] = {
2915                 /* Channel Estimation */
2916                 { 0x1f, 0x0001 },
2917                 { 0x06, 0x4064 },
2918                 { 0x07, 0x2863 },
2919                 { 0x08, 0x059c },
2920                 { 0x09, 0x26b4 },
2921                 { 0x0a, 0x6a19 },
2922                 { 0x0b, 0xdcc8 },
2923                 { 0x10, 0xf06d },
2924                 { 0x14, 0x7f68 },
2925                 { 0x18, 0x7fd9 },
2926                 { 0x1c, 0xf0ff },
2927                 { 0x1d, 0x3d9c },
2928                 { 0x1f, 0x0003 },
2929                 { 0x12, 0xf49f },
2930                 { 0x13, 0x070b },
2931                 { 0x1a, 0x05ad },
2932                 { 0x14, 0x94c0 },
2933
2934                 /*
2935                  * Tx Error Issue
2936                  * Enhance line driver power
2937                  */
2938                 { 0x1f, 0x0002 },
2939                 { 0x06, 0x5561 },
2940                 { 0x1f, 0x0005 },
2941                 { 0x05, 0x8332 },
2942                 { 0x06, 0x5561 },
2943
2944                 /*
2945                  * Can not link to 1Gbps with bad cable
2946                  * Decrease SNR threshold form 21.07dB to 19.04dB
2947                  */
2948                 { 0x1f, 0x0001 },
2949                 { 0x17, 0x0cc0 },
2950
2951                 { 0x1f, 0x0000 },
2952                 { 0x0d, 0xf880 }
2953         };
2954
2955         rtl_writephy_batch(tp, phy_reg_init_0);
2956
2957         /*
2958          * Rx Error Issue
2959          * Fine Tune Switching regulator parameter
2960          */
2961         rtl_writephy(tp, 0x1f, 0x0002);
2962         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2963         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2964
2965         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2966                 static const struct phy_reg phy_reg_init[] = {
2967                         { 0x1f, 0x0002 },
2968                         { 0x05, 0x669a },
2969                         { 0x1f, 0x0005 },
2970                         { 0x05, 0x8330 },
2971                         { 0x06, 0x669a },
2972                         { 0x1f, 0x0002 }
2973                 };
2974                 int val;
2975
2976                 rtl_writephy_batch(tp, phy_reg_init);
2977
2978                 val = rtl_readphy(tp, 0x0d);
2979
2980                 if ((val & 0x00ff) != 0x006c) {
2981                         static const u32 set[] = {
2982                                 0x0065, 0x0066, 0x0067, 0x0068,
2983                                 0x0069, 0x006a, 0x006b, 0x006c
2984                         };
2985                         int i;
2986
2987                         rtl_writephy(tp, 0x1f, 0x0002);
2988
2989                         val &= 0xff00;
2990                         for (i = 0; i < ARRAY_SIZE(set); i++)
2991                                 rtl_writephy(tp, 0x0d, val | set[i]);
2992                 }
2993         } else {
2994                 static const struct phy_reg phy_reg_init[] = {
2995                         { 0x1f, 0x0002 },
2996                         { 0x05, 0x6662 },
2997                         { 0x1f, 0x0005 },
2998                         { 0x05, 0x8330 },
2999                         { 0x06, 0x6662 }
3000                 };
3001
3002                 rtl_writephy_batch(tp, phy_reg_init);
3003         }
3004
3005         /* RSET couple improve */
3006         rtl_writephy(tp, 0x1f, 0x0002);
3007         rtl_patchphy(tp, 0x0d, 0x0300);
3008         rtl_patchphy(tp, 0x0f, 0x0010);
3009
3010         /* Fine tune PLL performance */
3011         rtl_writephy(tp, 0x1f, 0x0002);
3012         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3013         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3014
3015         rtl_writephy(tp, 0x1f, 0x0005);
3016         rtl_writephy(tp, 0x05, 0x001b);
3017
3018         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3019
3020         rtl_writephy(tp, 0x1f, 0x0000);
3021 }
3022
3023 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3024 {
3025         static const struct phy_reg phy_reg_init_0[] = {
3026                 /* Channel Estimation */
3027                 { 0x1f, 0x0001 },
3028                 { 0x06, 0x4064 },
3029                 { 0x07, 0x2863 },
3030                 { 0x08, 0x059c },
3031                 { 0x09, 0x26b4 },
3032                 { 0x0a, 0x6a19 },
3033                 { 0x0b, 0xdcc8 },
3034                 { 0x10, 0xf06d },
3035                 { 0x14, 0x7f68 },
3036                 { 0x18, 0x7fd9 },
3037                 { 0x1c, 0xf0ff },
3038                 { 0x1d, 0x3d9c },
3039                 { 0x1f, 0x0003 },
3040                 { 0x12, 0xf49f },
3041                 { 0x13, 0x070b },
3042                 { 0x1a, 0x05ad },
3043                 { 0x14, 0x94c0 },
3044
3045                 /*
3046                  * Tx Error Issue
3047                  * Enhance line driver power
3048                  */
3049                 { 0x1f, 0x0002 },
3050                 { 0x06, 0x5561 },
3051                 { 0x1f, 0x0005 },
3052                 { 0x05, 0x8332 },
3053                 { 0x06, 0x5561 },
3054
3055                 /*
3056                  * Can not link to 1Gbps with bad cable
3057                  * Decrease SNR threshold form 21.07dB to 19.04dB
3058                  */
3059                 { 0x1f, 0x0001 },
3060                 { 0x17, 0x0cc0 },
3061
3062                 { 0x1f, 0x0000 },
3063                 { 0x0d, 0xf880 }
3064         };
3065
3066         rtl_writephy_batch(tp, phy_reg_init_0);
3067
3068         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3069                 static const struct phy_reg phy_reg_init[] = {
3070                         { 0x1f, 0x0002 },
3071                         { 0x05, 0x669a },
3072                         { 0x1f, 0x0005 },
3073                         { 0x05, 0x8330 },
3074                         { 0x06, 0x669a },
3075
3076                         { 0x1f, 0x0002 }
3077                 };
3078                 int val;
3079
3080                 rtl_writephy_batch(tp, phy_reg_init);
3081
3082                 val = rtl_readphy(tp, 0x0d);
3083                 if ((val & 0x00ff) != 0x006c) {
3084                         static const u32 set[] = {
3085                                 0x0065, 0x0066, 0x0067, 0x0068,
3086                                 0x0069, 0x006a, 0x006b, 0x006c
3087                         };
3088                         int i;
3089
3090                         rtl_writephy(tp, 0x1f, 0x0002);
3091
3092                         val &= 0xff00;
3093                         for (i = 0; i < ARRAY_SIZE(set); i++)
3094                                 rtl_writephy(tp, 0x0d, val | set[i]);
3095                 }
3096         } else {
3097                 static const struct phy_reg phy_reg_init[] = {
3098                         { 0x1f, 0x0002 },
3099                         { 0x05, 0x2642 },
3100                         { 0x1f, 0x0005 },
3101                         { 0x05, 0x8330 },
3102                         { 0x06, 0x2642 }
3103                 };
3104
3105                 rtl_writephy_batch(tp, phy_reg_init);
3106         }
3107
3108         /* Fine tune PLL performance */
3109         rtl_writephy(tp, 0x1f, 0x0002);
3110         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3111         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3112
3113         /* Switching regulator Slew rate */
3114         rtl_writephy(tp, 0x1f, 0x0002);
3115         rtl_patchphy(tp, 0x0f, 0x0017);
3116
3117         rtl_writephy(tp, 0x1f, 0x0005);
3118         rtl_writephy(tp, 0x05, 0x001b);
3119
3120         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3121
3122         rtl_writephy(tp, 0x1f, 0x0000);
3123 }
3124
3125 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3126 {
3127         static const struct phy_reg phy_reg_init[] = {
3128                 { 0x1f, 0x0002 },
3129                 { 0x10, 0x0008 },
3130                 { 0x0d, 0x006c },
3131
3132                 { 0x1f, 0x0000 },
3133                 { 0x0d, 0xf880 },
3134
3135                 { 0x1f, 0x0001 },
3136                 { 0x17, 0x0cc0 },
3137
3138                 { 0x1f, 0x0001 },
3139                 { 0x0b, 0xa4d8 },
3140                 { 0x09, 0x281c },
3141                 { 0x07, 0x2883 },
3142                 { 0x0a, 0x6b35 },
3143                 { 0x1d, 0x3da4 },
3144                 { 0x1c, 0xeffd },
3145                 { 0x14, 0x7f52 },
3146                 { 0x18, 0x7fc6 },
3147                 { 0x08, 0x0601 },
3148                 { 0x06, 0x4063 },
3149                 { 0x10, 0xf074 },
3150                 { 0x1f, 0x0003 },
3151                 { 0x13, 0x0789 },
3152                 { 0x12, 0xf4bd },
3153                 { 0x1a, 0x04fd },
3154                 { 0x14, 0x84b0 },
3155                 { 0x1f, 0x0000 },
3156                 { 0x00, 0x9200 },
3157
3158                 { 0x1f, 0x0005 },
3159                 { 0x01, 0x0340 },
3160                 { 0x1f, 0x0001 },
3161                 { 0x04, 0x4000 },
3162                 { 0x03, 0x1d21 },
3163                 { 0x02, 0x0c32 },
3164                 { 0x01, 0x0200 },
3165                 { 0x00, 0x5554 },
3166                 { 0x04, 0x4800 },
3167                 { 0x04, 0x4000 },
3168                 { 0x04, 0xf000 },
3169                 { 0x03, 0xdf01 },
3170                 { 0x02, 0xdf20 },
3171                 { 0x01, 0x101a },
3172                 { 0x00, 0xa0ff },
3173                 { 0x04, 0xf800 },
3174                 { 0x04, 0xf000 },
3175                 { 0x1f, 0x0000 },
3176
3177                 { 0x1f, 0x0007 },
3178                 { 0x1e, 0x0023 },
3179                 { 0x16, 0x0000 },
3180                 { 0x1f, 0x0000 }
3181         };
3182
3183         rtl_writephy_batch(tp, phy_reg_init);
3184 }
3185
3186 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3187 {
3188         static const struct phy_reg phy_reg_init[] = {
3189                 { 0x1f, 0x0001 },
3190                 { 0x17, 0x0cc0 },
3191
3192                 { 0x1f, 0x0007 },
3193                 { 0x1e, 0x002d },
3194                 { 0x18, 0x0040 },
3195                 { 0x1f, 0x0000 }
3196         };
3197
3198         rtl_writephy_batch(tp, phy_reg_init);
3199         rtl_patchphy(tp, 0x0d, 1 << 5);
3200 }
3201
3202 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3203 {
3204         static const struct phy_reg phy_reg_init[] = {
3205                 /* Enable Delay cap */
3206                 { 0x1f, 0x0005 },
3207                 { 0x05, 0x8b80 },
3208                 { 0x06, 0xc896 },
3209                 { 0x1f, 0x0000 },
3210
3211                 /* Channel estimation fine tune */
3212                 { 0x1f, 0x0001 },
3213                 { 0x0b, 0x6c20 },
3214                 { 0x07, 0x2872 },
3215                 { 0x1c, 0xefff },
3216                 { 0x1f, 0x0003 },
3217                 { 0x14, 0x6420 },
3218                 { 0x1f, 0x0000 },
3219
3220                 /* Update PFM & 10M TX idle timer */
3221                 { 0x1f, 0x0007 },
3222                 { 0x1e, 0x002f },
3223                 { 0x15, 0x1919 },
3224                 { 0x1f, 0x0000 },
3225
3226                 { 0x1f, 0x0007 },
3227                 { 0x1e, 0x00ac },
3228                 { 0x18, 0x0006 },
3229                 { 0x1f, 0x0000 }
3230         };
3231
3232         rtl_apply_firmware(tp);
3233
3234         rtl_writephy_batch(tp, phy_reg_init);
3235
3236         /* DCO enable for 10M IDLE Power */
3237         rtl_writephy(tp, 0x1f, 0x0007);
3238         rtl_writephy(tp, 0x1e, 0x0023);
3239         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3240         rtl_writephy(tp, 0x1f, 0x0000);
3241
3242         /* For impedance matching */
3243         rtl_writephy(tp, 0x1f, 0x0002);
3244         rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3245         rtl_writephy(tp, 0x1f, 0x0000);
3246
3247         /* PHY auto speed down */
3248         rtl_writephy(tp, 0x1f, 0x0007);
3249         rtl_writephy(tp, 0x1e, 0x002d);
3250         rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3251         rtl_writephy(tp, 0x1f, 0x0000);
3252         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3253
3254         rtl_writephy(tp, 0x1f, 0x0005);
3255         rtl_writephy(tp, 0x05, 0x8b86);
3256         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3257         rtl_writephy(tp, 0x1f, 0x0000);
3258
3259         rtl_writephy(tp, 0x1f, 0x0005);
3260         rtl_writephy(tp, 0x05, 0x8b85);
3261         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3262         rtl_writephy(tp, 0x1f, 0x0007);
3263         rtl_writephy(tp, 0x1e, 0x0020);
3264         rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3265         rtl_writephy(tp, 0x1f, 0x0006);
3266         rtl_writephy(tp, 0x00, 0x5a00);
3267         rtl_writephy(tp, 0x1f, 0x0000);
3268         rtl_writephy(tp, 0x0d, 0x0007);
3269         rtl_writephy(tp, 0x0e, 0x003c);
3270         rtl_writephy(tp, 0x0d, 0x4007);
3271         rtl_writephy(tp, 0x0e, 0x0000);
3272         rtl_writephy(tp, 0x0d, 0x0000);
3273 }
3274
3275 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3276 {
3277         const u16 w[] = {
3278                 addr[0] | (addr[1] << 8),
3279                 addr[2] | (addr[3] << 8),
3280                 addr[4] | (addr[5] << 8)
3281         };
3282
3283         rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
3284         rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
3285         rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
3286         rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
3287 }
3288
3289 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3290 {
3291         static const struct phy_reg phy_reg_init[] = {
3292                 /* Enable Delay cap */
3293                 { 0x1f, 0x0004 },
3294                 { 0x1f, 0x0007 },
3295                 { 0x1e, 0x00ac },
3296                 { 0x18, 0x0006 },
3297                 { 0x1f, 0x0002 },
3298                 { 0x1f, 0x0000 },
3299                 { 0x1f, 0x0000 },
3300
3301                 /* Channel estimation fine tune */
3302                 { 0x1f, 0x0003 },
3303                 { 0x09, 0xa20f },
3304                 { 0x1f, 0x0000 },
3305                 { 0x1f, 0x0000 },
3306
3307                 /* Green Setting */
3308                 { 0x1f, 0x0005 },
3309                 { 0x05, 0x8b5b },
3310                 { 0x06, 0x9222 },
3311                 { 0x05, 0x8b6d },
3312                 { 0x06, 0x8000 },
3313                 { 0x05, 0x8b76 },
3314                 { 0x06, 0x8000 },
3315                 { 0x1f, 0x0000 }
3316         };
3317
3318         rtl_apply_firmware(tp);
3319
3320         rtl_writephy_batch(tp, phy_reg_init);
3321
3322         /* For 4-corner performance improve */
3323         rtl_writephy(tp, 0x1f, 0x0005);
3324         rtl_writephy(tp, 0x05, 0x8b80);
3325         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3326         rtl_writephy(tp, 0x1f, 0x0000);
3327
3328         /* PHY auto speed down */
3329         rtl_writephy(tp, 0x1f, 0x0004);
3330         rtl_writephy(tp, 0x1f, 0x0007);
3331         rtl_writephy(tp, 0x1e, 0x002d);
3332         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3333         rtl_writephy(tp, 0x1f, 0x0002);
3334         rtl_writephy(tp, 0x1f, 0x0000);
3335         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3336
3337         /* improve 10M EEE waveform */
3338         rtl_writephy(tp, 0x1f, 0x0005);
3339         rtl_writephy(tp, 0x05, 0x8b86);
3340         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3341         rtl_writephy(tp, 0x1f, 0x0000);
3342
3343         /* Improve 2-pair detection performance */
3344         rtl_writephy(tp, 0x1f, 0x0005);
3345         rtl_writephy(tp, 0x05, 0x8b85);
3346         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3347         rtl_writephy(tp, 0x1f, 0x0000);
3348
3349         rtl8168f_config_eee_phy(tp);
3350         rtl_enable_eee(tp);
3351
3352         /* Green feature */
3353         rtl_writephy(tp, 0x1f, 0x0003);
3354         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3355         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3356         rtl_writephy(tp, 0x1f, 0x0000);
3357         rtl_writephy(tp, 0x1f, 0x0005);
3358         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3359         rtl_writephy(tp, 0x1f, 0x0000);
3360
3361         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3362         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3363 }
3364
3365 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3366 {
3367         /* For 4-corner performance improve */
3368         rtl_writephy(tp, 0x1f, 0x0005);
3369         rtl_writephy(tp, 0x05, 0x8b80);
3370         rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3371         rtl_writephy(tp, 0x1f, 0x0000);
3372
3373         /* PHY auto speed down */
3374         rtl_writephy(tp, 0x1f, 0x0007);
3375         rtl_writephy(tp, 0x1e, 0x002d);
3376         rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3377         rtl_writephy(tp, 0x1f, 0x0000);
3378         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3379
3380         /* Improve 10M EEE waveform */
3381         rtl_writephy(tp, 0x1f, 0x0005);
3382         rtl_writephy(tp, 0x05, 0x8b86);
3383         rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3384         rtl_writephy(tp, 0x1f, 0x0000);
3385
3386         rtl8168f_config_eee_phy(tp);
3387         rtl_enable_eee(tp);
3388 }
3389
3390 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3391 {
3392         static const struct phy_reg phy_reg_init[] = {
3393                 /* Channel estimation fine tune */
3394                 { 0x1f, 0x0003 },
3395                 { 0x09, 0xa20f },
3396                 { 0x1f, 0x0000 },
3397
3398                 /* Modify green table for giga & fnet */
3399                 { 0x1f, 0x0005 },
3400                 { 0x05, 0x8b55 },
3401                 { 0x06, 0x0000 },
3402                 { 0x05, 0x8b5e },
3403                 { 0x06, 0x0000 },
3404                 { 0x05, 0x8b67 },
3405                 { 0x06, 0x0000 },
3406                 { 0x05, 0x8b70 },
3407                 { 0x06, 0x0000 },
3408                 { 0x1f, 0x0000 },
3409                 { 0x1f, 0x0007 },
3410                 { 0x1e, 0x0078 },
3411                 { 0x17, 0x0000 },
3412                 { 0x19, 0x00fb },
3413                 { 0x1f, 0x0000 },
3414
3415                 /* Modify green table for 10M */
3416                 { 0x1f, 0x0005 },
3417                 { 0x05, 0x8b79 },
3418                 { 0x06, 0xaa00 },
3419                 { 0x1f, 0x0000 },
3420
3421                 /* Disable hiimpedance detection (RTCT) */
3422                 { 0x1f, 0x0003 },
3423                 { 0x01, 0x328a },
3424                 { 0x1f, 0x0000 }
3425         };
3426
3427         rtl_apply_firmware(tp);
3428
3429         rtl_writephy_batch(tp, phy_reg_init);
3430
3431         rtl8168f_hw_phy_config(tp);
3432
3433         /* Improve 2-pair detection performance */
3434         rtl_writephy(tp, 0x1f, 0x0005);
3435         rtl_writephy(tp, 0x05, 0x8b85);
3436         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3437         rtl_writephy(tp, 0x1f, 0x0000);
3438 }
3439
3440 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3441 {
3442         rtl_apply_firmware(tp);
3443
3444         rtl8168f_hw_phy_config(tp);
3445 }
3446
3447 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3448 {
3449         static const struct phy_reg phy_reg_init[] = {
3450                 /* Channel estimation fine tune */
3451                 { 0x1f, 0x0003 },
3452                 { 0x09, 0xa20f },
3453                 { 0x1f, 0x0000 },
3454
3455                 /* Modify green table for giga & fnet */
3456                 { 0x1f, 0x0005 },
3457                 { 0x05, 0x8b55 },
3458                 { 0x06, 0x0000 },
3459                 { 0x05, 0x8b5e },
3460                 { 0x06, 0x0000 },
3461                 { 0x05, 0x8b67 },
3462                 { 0x06, 0x0000 },
3463                 { 0x05, 0x8b70 },
3464                 { 0x06, 0x0000 },
3465                 { 0x1f, 0x0000 },
3466                 { 0x1f, 0x0007 },
3467                 { 0x1e, 0x0078 },
3468                 { 0x17, 0x0000 },
3469                 { 0x19, 0x00aa },
3470                 { 0x1f, 0x0000 },
3471
3472                 /* Modify green table for 10M */
3473                 { 0x1f, 0x0005 },
3474                 { 0x05, 0x8b79 },
3475                 { 0x06, 0xaa00 },
3476                 { 0x1f, 0x0000 },
3477
3478                 /* Disable hiimpedance detection (RTCT) */
3479                 { 0x1f, 0x0003 },
3480                 { 0x01, 0x328a },
3481                 { 0x1f, 0x0000 }
3482         };
3483
3484
3485         rtl_apply_firmware(tp);
3486
3487         rtl8168f_hw_phy_config(tp);
3488
3489         /* Improve 2-pair detection performance */
3490         rtl_writephy(tp, 0x1f, 0x0005);
3491         rtl_writephy(tp, 0x05, 0x8b85);
3492         rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3493         rtl_writephy(tp, 0x1f, 0x0000);
3494
3495         rtl_writephy_batch(tp, phy_reg_init);
3496
3497         /* Modify green table for giga */
3498         rtl_writephy(tp, 0x1f, 0x0005);
3499         rtl_writephy(tp, 0x05, 0x8b54);
3500         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3501         rtl_writephy(tp, 0x05, 0x8b5d);
3502         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3503         rtl_writephy(tp, 0x05, 0x8a7c);
3504         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3505         rtl_writephy(tp, 0x05, 0x8a7f);
3506         rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3507         rtl_writephy(tp, 0x05, 0x8a82);
3508         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3509         rtl_writephy(tp, 0x05, 0x8a85);
3510         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3511         rtl_writephy(tp, 0x05, 0x8a88);
3512         rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3513         rtl_writephy(tp, 0x1f, 0x0000);
3514
3515         /* uc same-seed solution */
3516         rtl_writephy(tp, 0x1f, 0x0005);
3517         rtl_writephy(tp, 0x05, 0x8b85);
3518         rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3519         rtl_writephy(tp, 0x1f, 0x0000);
3520
3521         /* Green feature */
3522         rtl_writephy(tp, 0x1f, 0x0003);
3523         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3524         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3525         rtl_writephy(tp, 0x1f, 0x0000);
3526 }
3527
3528 static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3529 {
3530         phy_write(tp->phydev, 0x1f, 0x0a43);
3531         phy_clear_bits(tp->phydev, 0x10, BIT(2));
3532 }
3533
3534 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3535 {
3536         struct phy_device *phydev = tp->phydev;
3537
3538         phy_write(phydev, 0x1f, 0x0bcc);
3539         phy_clear_bits(phydev, 0x14, BIT(8));
3540
3541         phy_write(phydev, 0x1f, 0x0a44);
3542         phy_set_bits(phydev, 0x11, BIT(7) | BIT(6));
3543
3544         phy_write(phydev, 0x1f, 0x0a43);
3545         phy_write(phydev, 0x13, 0x8084);
3546         phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3547         phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3548
3549         phy_write(phydev, 0x1f, 0x0000);
3550 }
3551
3552 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3553 {
3554         rtl_apply_firmware(tp);
3555
3556         rtl_writephy(tp, 0x1f, 0x0a46);
3557         if (rtl_readphy(tp, 0x10) & 0x0100) {
3558                 rtl_writephy(tp, 0x1f, 0x0bcc);
3559                 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3560         } else {
3561                 rtl_writephy(tp, 0x1f, 0x0bcc);
3562                 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3563         }
3564
3565         rtl_writephy(tp, 0x1f, 0x0a46);
3566         if (rtl_readphy(tp, 0x13) & 0x0100) {
3567                 rtl_writephy(tp, 0x1f, 0x0c41);
3568                 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3569         } else {
3570                 rtl_writephy(tp, 0x1f, 0x0c41);
3571                 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3572         }
3573
3574         /* Enable PHY auto speed down */
3575         rtl_writephy(tp, 0x1f, 0x0a44);
3576         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3577
3578         rtl8168g_phy_adjust_10m_aldps(tp);
3579
3580         /* EEE auto-fallback function */
3581         rtl_writephy(tp, 0x1f, 0x0a4b);
3582         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3583
3584         /* Enable UC LPF tune function */
3585         rtl_writephy(tp, 0x1f, 0x0a43);
3586         rtl_writephy(tp, 0x13, 0x8012);
3587         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3588
3589         rtl_writephy(tp, 0x1f, 0x0c42);
3590         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3591
3592         /* Improve SWR Efficiency */
3593         rtl_writephy(tp, 0x1f, 0x0bcd);
3594         rtl_writephy(tp, 0x14, 0x5065);
3595         rtl_writephy(tp, 0x14, 0xd065);
3596         rtl_writephy(tp, 0x1f, 0x0bc8);
3597         rtl_writephy(tp, 0x11, 0x5655);
3598         rtl_writephy(tp, 0x1f, 0x0bcd);
3599         rtl_writephy(tp, 0x14, 0x1065);
3600         rtl_writephy(tp, 0x14, 0x9065);
3601         rtl_writephy(tp, 0x14, 0x1065);
3602
3603         rtl8168g_disable_aldps(tp);
3604         rtl8168g_config_eee_phy(tp);
3605         rtl_enable_eee(tp);
3606 }
3607
3608 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3609 {
3610         rtl_apply_firmware(tp);
3611         rtl8168g_config_eee_phy(tp);
3612         rtl_enable_eee(tp);
3613 }
3614
3615 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3616 {
3617         u16 dout_tapbin;
3618         u32 data;
3619
3620         rtl_apply_firmware(tp);
3621
3622         /* CHN EST parameters adjust - giga master */
3623         rtl_writephy(tp, 0x1f, 0x0a43);
3624         rtl_writephy(tp, 0x13, 0x809b);
3625         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3626         rtl_writephy(tp, 0x13, 0x80a2);
3627         rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3628         rtl_writephy(tp, 0x13, 0x80a4);
3629         rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3630         rtl_writephy(tp, 0x13, 0x809c);
3631         rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3632         rtl_writephy(tp, 0x1f, 0x0000);
3633
3634         /* CHN EST parameters adjust - giga slave */
3635         rtl_writephy(tp, 0x1f, 0x0a43);
3636         rtl_writephy(tp, 0x13, 0x80ad);
3637         rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3638         rtl_writephy(tp, 0x13, 0x80b4);
3639         rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3640         rtl_writephy(tp, 0x13, 0x80ac);
3641         rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3642         rtl_writephy(tp, 0x1f, 0x0000);
3643
3644         /* CHN EST parameters adjust - fnet */
3645         rtl_writephy(tp, 0x1f, 0x0a43);
3646         rtl_writephy(tp, 0x13, 0x808e);
3647         rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3648         rtl_writephy(tp, 0x13, 0x8090);
3649         rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3650         rtl_writephy(tp, 0x13, 0x8092);
3651         rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3652         rtl_writephy(tp, 0x1f, 0x0000);
3653
3654         /* enable R-tune & PGA-retune function */
3655         dout_tapbin = 0;
3656         rtl_writephy(tp, 0x1f, 0x0a46);
3657         data = rtl_readphy(tp, 0x13);
3658         data &= 3;
3659         data <<= 2;
3660         dout_tapbin |= data;
3661         data = rtl_readphy(tp, 0x12);
3662         data &= 0xc000;
3663         data >>= 14;
3664         dout_tapbin |= data;
3665         dout_tapbin = ~(dout_tapbin^0x08);
3666         dout_tapbin <<= 12;
3667         dout_tapbin &= 0xf000;
3668         rtl_writephy(tp, 0x1f, 0x0a43);
3669         rtl_writephy(tp, 0x13, 0x827a);
3670         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3671         rtl_writephy(tp, 0x13, 0x827b);
3672         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3673         rtl_writephy(tp, 0x13, 0x827c);
3674         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3675         rtl_writephy(tp, 0x13, 0x827d);
3676         rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3677
3678         rtl_writephy(tp, 0x1f, 0x0a43);
3679         rtl_writephy(tp, 0x13, 0x0811);
3680         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3681         rtl_writephy(tp, 0x1f, 0x0a42);
3682         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3683         rtl_writephy(tp, 0x1f, 0x0000);
3684
3685         /* enable GPHY 10M */
3686         rtl_writephy(tp, 0x1f, 0x0a44);
3687         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3688         rtl_writephy(tp, 0x1f, 0x0000);
3689
3690         /* SAR ADC performance */
3691         rtl_writephy(tp, 0x1f, 0x0bca);
3692         rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3693         rtl_writephy(tp, 0x1f, 0x0000);
3694
3695         rtl_writephy(tp, 0x1f, 0x0a43);
3696         rtl_writephy(tp, 0x13, 0x803f);
3697         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3698         rtl_writephy(tp, 0x13, 0x8047);
3699         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3700         rtl_writephy(tp, 0x13, 0x804f);
3701         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3702         rtl_writephy(tp, 0x13, 0x8057);
3703         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3704         rtl_writephy(tp, 0x13, 0x805f);
3705         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3706         rtl_writephy(tp, 0x13, 0x8067);
3707         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3708         rtl_writephy(tp, 0x13, 0x806f);
3709         rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3710         rtl_writephy(tp, 0x1f, 0x0000);
3711
3712         /* disable phy pfm mode */
3713         rtl_writephy(tp, 0x1f, 0x0a44);
3714         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3715         rtl_writephy(tp, 0x1f, 0x0000);
3716
3717         rtl8168g_disable_aldps(tp);
3718         rtl8168g_config_eee_phy(tp);
3719         rtl_enable_eee(tp);
3720 }
3721
3722 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3723 {
3724         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3725         u16 rlen;
3726         u32 data;
3727
3728         rtl_apply_firmware(tp);
3729
3730         /* CHIN EST parameter update */
3731         rtl_writephy(tp, 0x1f, 0x0a43);
3732         rtl_writephy(tp, 0x13, 0x808a);
3733         rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3734         rtl_writephy(tp, 0x1f, 0x0000);
3735
3736         /* enable R-tune & PGA-retune function */
3737         rtl_writephy(tp, 0x1f, 0x0a43);
3738         rtl_writephy(tp, 0x13, 0x0811);
3739         rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3740         rtl_writephy(tp, 0x1f, 0x0a42);
3741         rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3742         rtl_writephy(tp, 0x1f, 0x0000);
3743
3744         /* enable GPHY 10M */
3745         rtl_writephy(tp, 0x1f, 0x0a44);
3746         rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3747         rtl_writephy(tp, 0x1f, 0x0000);
3748
3749         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3750         data = r8168_mac_ocp_read(tp, 0xdd02);
3751         ioffset_p3 = ((data & 0x80)>>7);
3752         ioffset_p3 <<= 3;
3753
3754         data = r8168_mac_ocp_read(tp, 0xdd00);
3755         ioffset_p3 |= ((data & (0xe000))>>13);
3756         ioffset_p2 = ((data & (0x1e00))>>9);
3757         ioffset_p1 = ((data & (0x01e0))>>5);
3758         ioffset_p0 = ((data & 0x0010)>>4);
3759         ioffset_p0 <<= 3;
3760         ioffset_p0 |= (data & (0x07));
3761         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3762
3763         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3764             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3765                 rtl_writephy(tp, 0x1f, 0x0bcf);
3766                 rtl_writephy(tp, 0x16, data);
3767                 rtl_writephy(tp, 0x1f, 0x0000);
3768         }
3769
3770         /* Modify rlen (TX LPF corner frequency) level */
3771         rtl_writephy(tp, 0x1f, 0x0bcd);
3772         data = rtl_readphy(tp, 0x16);
3773         data &= 0x000f;
3774         rlen = 0;
3775         if (data > 3)
3776                 rlen = data - 3;
3777         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3778         rtl_writephy(tp, 0x17, data);
3779         rtl_writephy(tp, 0x1f, 0x0bcd);
3780         rtl_writephy(tp, 0x1f, 0x0000);
3781
3782         /* disable phy pfm mode */
3783         rtl_writephy(tp, 0x1f, 0x0a44);
3784         rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3785         rtl_writephy(tp, 0x1f, 0x0000);
3786
3787         rtl8168g_disable_aldps(tp);
3788         rtl8168g_config_eee_phy(tp);
3789         rtl_enable_eee(tp);
3790 }
3791
3792 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3793 {
3794         /* Enable PHY auto speed down */
3795         rtl_writephy(tp, 0x1f, 0x0a44);
3796         rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3797         rtl_writephy(tp, 0x1f, 0x0000);
3798
3799         rtl8168g_phy_adjust_10m_aldps(tp);
3800
3801         /* Enable EEE auto-fallback function */
3802         rtl_writephy(tp, 0x1f, 0x0a4b);
3803         rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3804         rtl_writephy(tp, 0x1f, 0x0000);
3805
3806         /* Enable UC LPF tune function */
3807         rtl_writephy(tp, 0x1f, 0x0a43);
3808         rtl_writephy(tp, 0x13, 0x8012);
3809         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3810         rtl_writephy(tp, 0x1f, 0x0000);
3811
3812         /* set rg_sel_sdm_rate */
3813         rtl_writephy(tp, 0x1f, 0x0c42);
3814         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3815         rtl_writephy(tp, 0x1f, 0x0000);
3816
3817         rtl8168g_disable_aldps(tp);
3818         rtl8168g_config_eee_phy(tp);
3819         rtl_enable_eee(tp);
3820 }
3821
3822 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3823 {
3824         rtl8168g_phy_adjust_10m_aldps(tp);
3825
3826         /* Enable UC LPF tune function */
3827         rtl_writephy(tp, 0x1f, 0x0a43);
3828         rtl_writephy(tp, 0x13, 0x8012);
3829         rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3830         rtl_writephy(tp, 0x1f, 0x0000);
3831
3832         /* Set rg_sel_sdm_rate */
3833         rtl_writephy(tp, 0x1f, 0x0c42);
3834         rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3835         rtl_writephy(tp, 0x1f, 0x0000);
3836
3837         /* Channel estimation parameters */
3838         rtl_writephy(tp, 0x1f, 0x0a43);
3839         rtl_writephy(tp, 0x13, 0x80f3);
3840         rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3841         rtl_writephy(tp, 0x13, 0x80f0);
3842         rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3843         rtl_writephy(tp, 0x13, 0x80ef);
3844         rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3845         rtl_writephy(tp, 0x13, 0x80f6);
3846         rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3847         rtl_writephy(tp, 0x13, 0x80ec);
3848         rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3849         rtl_writephy(tp, 0x13, 0x80ed);
3850         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3851         rtl_writephy(tp, 0x13, 0x80f2);
3852         rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3853         rtl_writephy(tp, 0x13, 0x80f4);
3854         rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3855         rtl_writephy(tp, 0x1f, 0x0a43);
3856         rtl_writephy(tp, 0x13, 0x8110);
3857         rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3858         rtl_writephy(tp, 0x13, 0x810f);
3859         rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3860         rtl_writephy(tp, 0x13, 0x8111);
3861         rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3862         rtl_writephy(tp, 0x13, 0x8113);
3863         rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3864         rtl_writephy(tp, 0x13, 0x8115);
3865         rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3866         rtl_writephy(tp, 0x13, 0x810e);
3867         rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3868         rtl_writephy(tp, 0x13, 0x810c);
3869         rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3870         rtl_writephy(tp, 0x13, 0x810b);
3871         rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3872         rtl_writephy(tp, 0x1f, 0x0a43);
3873         rtl_writephy(tp, 0x13, 0x80d1);
3874         rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3875         rtl_writephy(tp, 0x13, 0x80cd);
3876         rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3877         rtl_writephy(tp, 0x13, 0x80d3);
3878         rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3879         rtl_writephy(tp, 0x13, 0x80d5);
3880         rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3881         rtl_writephy(tp, 0x13, 0x80d7);
3882         rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3883
3884         /* Force PWM-mode */
3885         rtl_writephy(tp, 0x1f, 0x0bcd);
3886         rtl_writephy(tp, 0x14, 0x5065);
3887         rtl_writephy(tp, 0x14, 0xd065);
3888         rtl_writephy(tp, 0x1f, 0x0bc8);
3889         rtl_writephy(tp, 0x12, 0x00ed);
3890         rtl_writephy(tp, 0x1f, 0x0bcd);
3891         rtl_writephy(tp, 0x14, 0x1065);
3892         rtl_writephy(tp, 0x14, 0x9065);
3893         rtl_writephy(tp, 0x14, 0x1065);
3894         rtl_writephy(tp, 0x1f, 0x0000);
3895
3896         rtl8168g_disable_aldps(tp);
3897         rtl8168g_config_eee_phy(tp);
3898         rtl_enable_eee(tp);
3899 }
3900
3901 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3902 {
3903         static const struct phy_reg phy_reg_init[] = {
3904                 { 0x1f, 0x0003 },
3905                 { 0x08, 0x441d },
3906                 { 0x01, 0x9100 },
3907                 { 0x1f, 0x0000 }
3908         };
3909
3910         rtl_writephy(tp, 0x1f, 0x0000);
3911         rtl_patchphy(tp, 0x11, 1 << 12);
3912         rtl_patchphy(tp, 0x19, 1 << 13);
3913         rtl_patchphy(tp, 0x10, 1 << 15);
3914
3915         rtl_writephy_batch(tp, phy_reg_init);
3916 }
3917
3918 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3919 {
3920         static const struct phy_reg phy_reg_init[] = {
3921                 { 0x1f, 0x0005 },
3922                 { 0x1a, 0x0000 },
3923                 { 0x1f, 0x0000 },
3924
3925                 { 0x1f, 0x0004 },
3926                 { 0x1c, 0x0000 },
3927                 { 0x1f, 0x0000 },
3928
3929                 { 0x1f, 0x0001 },
3930                 { 0x15, 0x7701 },
3931                 { 0x1f, 0x0000 }
3932         };
3933
3934         /* Disable ALDPS before ram code */
3935         rtl_writephy(tp, 0x1f, 0x0000);
3936         rtl_writephy(tp, 0x18, 0x0310);
3937         msleep(100);
3938
3939         rtl_apply_firmware(tp);
3940
3941         rtl_writephy_batch(tp, phy_reg_init);
3942 }
3943
3944 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3945 {
3946         /* Disable ALDPS before setting firmware */
3947         rtl_writephy(tp, 0x1f, 0x0000);
3948         rtl_writephy(tp, 0x18, 0x0310);
3949         msleep(20);
3950
3951         rtl_apply_firmware(tp);
3952
3953         /* EEE setting */
3954         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3955         rtl_writephy(tp, 0x1f, 0x0004);
3956         rtl_writephy(tp, 0x10, 0x401f);
3957         rtl_writephy(tp, 0x19, 0x7030);
3958         rtl_writephy(tp, 0x1f, 0x0000);
3959 }
3960
3961 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3962 {
3963         static const struct phy_reg phy_reg_init[] = {
3964                 { 0x1f, 0x0004 },
3965                 { 0x10, 0xc07f },
3966                 { 0x19, 0x7030 },
3967                 { 0x1f, 0x0000 }
3968         };
3969
3970         /* Disable ALDPS before ram code */
3971         rtl_writephy(tp, 0x1f, 0x0000);
3972         rtl_writephy(tp, 0x18, 0x0310);
3973         msleep(100);
3974
3975         rtl_apply_firmware(tp);
3976
3977         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3978         rtl_writephy_batch(tp, phy_reg_init);
3979
3980         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3981 }
3982
3983 static void rtl_hw_phy_config(struct net_device *dev)
3984 {
3985         static const rtl_generic_fct phy_configs[] = {
3986                 /* PCI devices. */
3987                 [RTL_GIGA_MAC_VER_01] = NULL,
3988                 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
3989                 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
3990                 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
3991                 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
3992                 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
3993                 /* PCI-E devices. */
3994                 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
3995                 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
3996                 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
3997                 [RTL_GIGA_MAC_VER_10] = NULL,
3998                 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
3999                 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
4000                 [RTL_GIGA_MAC_VER_13] = NULL,
4001                 [RTL_GIGA_MAC_VER_14] = NULL,
4002                 [RTL_GIGA_MAC_VER_15] = NULL,
4003                 [RTL_GIGA_MAC_VER_16] = NULL,
4004                 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
4005                 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
4006                 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
4007                 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
4008                 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
4009                 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config,
4010                 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
4011                 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
4012                 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
4013                 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
4014                 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
4015                 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
4016                 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
4017                 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
4018                 [RTL_GIGA_MAC_VER_31] = NULL,
4019                 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
4020                 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
4021                 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
4022                 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
4023                 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
4024                 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
4025                 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
4026                 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
4027                 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
4028                 [RTL_GIGA_MAC_VER_41] = NULL,
4029                 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
4030                 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
4031                 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
4032                 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
4033                 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
4034                 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
4035                 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
4036                 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
4037                 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
4038                 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
4039         };
4040         struct rtl8169_private *tp = netdev_priv(dev);
4041
4042         if (phy_configs[tp->mac_version])
4043                 phy_configs[tp->mac_version](tp);
4044 }
4045
4046 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4047 {
4048         if (!test_and_set_bit(flag, tp->wk.flags))
4049                 schedule_work(&tp->wk.work);
4050 }
4051
4052 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4053 {
4054         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4055                (RTL_R8(tp, PHYstatus) & TBI_Enable);
4056 }
4057
4058 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4059 {
4060         rtl_hw_phy_config(dev);
4061
4062         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4063                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4064                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4065                 netif_dbg(tp, drv, dev,
4066                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4067                 RTL_W8(tp, 0x82, 0x01);
4068         }
4069
4070         /* We may have called phy_speed_down before */
4071         phy_speed_up(tp->phydev);
4072
4073         genphy_soft_reset(tp->phydev);
4074 }
4075
4076 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4077 {
4078         rtl_lock_work(tp);
4079
4080         rtl_unlock_config_regs(tp);
4081
4082         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4083         RTL_R32(tp, MAC4);
4084
4085         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4086         RTL_R32(tp, MAC0);
4087
4088         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4089                 rtl_rar_exgmac_set(tp, addr);
4090
4091         rtl_lock_config_regs(tp);
4092
4093         rtl_unlock_work(tp);
4094 }
4095
4096 static int rtl_set_mac_address(struct net_device *dev, void *p)
4097 {
4098         struct rtl8169_private *tp = netdev_priv(dev);
4099         struct device *d = tp_to_dev(tp);
4100         int ret;
4101
4102         ret = eth_mac_addr(dev, p);
4103         if (ret)
4104                 return ret;
4105
4106         pm_runtime_get_noresume(d);
4107
4108         if (pm_runtime_active(d))
4109                 rtl_rar_set(tp, dev->dev_addr);
4110
4111         pm_runtime_put_noidle(d);
4112
4113         return 0;
4114 }
4115
4116 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4117 {
4118         struct rtl8169_private *tp = netdev_priv(dev);
4119
4120         if (!netif_running(dev))
4121                 return -ENODEV;
4122
4123         return phy_mii_ioctl(tp->phydev, ifr, cmd);
4124 }
4125
4126 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4127 {
4128         struct mdio_ops *ops = &tp->mdio_ops;
4129
4130         switch (tp->mac_version) {
4131         case RTL_GIGA_MAC_VER_27:
4132                 ops->write      = r8168dp_1_mdio_write;
4133                 ops->read       = r8168dp_1_mdio_read;
4134                 break;
4135         case RTL_GIGA_MAC_VER_28:
4136         case RTL_GIGA_MAC_VER_31:
4137                 ops->write      = r8168dp_2_mdio_write;
4138                 ops->read       = r8168dp_2_mdio_read;
4139                 break;
4140         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4141                 ops->write      = r8168g_mdio_write;
4142                 ops->read       = r8168g_mdio_read;
4143                 break;
4144         default:
4145                 ops->write      = r8169_mdio_write;
4146                 ops->read       = r8169_mdio_read;
4147                 break;
4148         }
4149 }
4150
4151 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4152 {
4153         switch (tp->mac_version) {
4154         case RTL_GIGA_MAC_VER_25:
4155         case RTL_GIGA_MAC_VER_26:
4156         case RTL_GIGA_MAC_VER_29:
4157         case RTL_GIGA_MAC_VER_30:
4158         case RTL_GIGA_MAC_VER_32:
4159         case RTL_GIGA_MAC_VER_33:
4160         case RTL_GIGA_MAC_VER_34:
4161         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4162                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4163                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4164                 break;
4165         default:
4166                 break;
4167         }
4168 }
4169
4170 static void r8168_pll_power_down(struct rtl8169_private *tp)
4171 {
4172         if (r8168_check_dash(tp))
4173                 return;
4174
4175         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4176             tp->mac_version == RTL_GIGA_MAC_VER_33)
4177                 rtl_ephy_write(tp, 0x19, 0xff64);
4178
4179         if (device_may_wakeup(tp_to_dev(tp))) {
4180                 phy_speed_down(tp->phydev, false);
4181                 rtl_wol_suspend_quirk(tp);
4182                 return;
4183         }
4184
4185         switch (tp->mac_version) {
4186         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4187         case RTL_GIGA_MAC_VER_37:
4188         case RTL_GIGA_MAC_VER_39:
4189         case RTL_GIGA_MAC_VER_43:
4190         case RTL_GIGA_MAC_VER_44:
4191         case RTL_GIGA_MAC_VER_45:
4192         case RTL_GIGA_MAC_VER_46:
4193         case RTL_GIGA_MAC_VER_47:
4194         case RTL_GIGA_MAC_VER_48:
4195         case RTL_GIGA_MAC_VER_50:
4196         case RTL_GIGA_MAC_VER_51:
4197                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4198                 break;
4199         case RTL_GIGA_MAC_VER_40:
4200         case RTL_GIGA_MAC_VER_41:
4201         case RTL_GIGA_MAC_VER_49:
4202                 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
4203                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4204                 break;
4205         }
4206 }
4207
4208 static void r8168_pll_power_up(struct rtl8169_private *tp)
4209 {
4210         switch (tp->mac_version) {
4211         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4212         case RTL_GIGA_MAC_VER_37:
4213         case RTL_GIGA_MAC_VER_39:
4214         case RTL_GIGA_MAC_VER_43:
4215                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4216                 break;
4217         case RTL_GIGA_MAC_VER_44:
4218         case RTL_GIGA_MAC_VER_45:
4219         case RTL_GIGA_MAC_VER_46:
4220         case RTL_GIGA_MAC_VER_47:
4221         case RTL_GIGA_MAC_VER_48:
4222         case RTL_GIGA_MAC_VER_50:
4223         case RTL_GIGA_MAC_VER_51:
4224                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4225                 break;
4226         case RTL_GIGA_MAC_VER_40:
4227         case RTL_GIGA_MAC_VER_41:
4228         case RTL_GIGA_MAC_VER_49:
4229                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4230                 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
4231                 break;
4232         }
4233
4234         phy_resume(tp->phydev);
4235         /* give MAC/PHY some time to resume */
4236         msleep(20);
4237 }
4238
4239 static void rtl_pll_power_down(struct rtl8169_private *tp)
4240 {
4241         switch (tp->mac_version) {
4242         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4243         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4244                 break;
4245         default:
4246                 r8168_pll_power_down(tp);
4247         }
4248 }
4249
4250 static void rtl_pll_power_up(struct rtl8169_private *tp)
4251 {
4252         switch (tp->mac_version) {
4253         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4254         case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4255                 break;
4256         default:
4257                 r8168_pll_power_up(tp);
4258         }
4259 }
4260
4261 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4262 {
4263         switch (tp->mac_version) {
4264         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4265         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4266                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4267                 break;
4268         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4269         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4270         case RTL_GIGA_MAC_VER_38:
4271                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4272                 break;
4273         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4274                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4275                 break;
4276         default:
4277                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4278                 break;
4279         }
4280 }
4281
4282 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4283 {
4284         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4285 }
4286
4287 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4288 {
4289         if (tp->jumbo_ops.enable) {
4290                 rtl_unlock_config_regs(tp);
4291                 tp->jumbo_ops.enable(tp);
4292                 rtl_lock_config_regs(tp);
4293         }
4294 }
4295
4296 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4297 {
4298         if (tp->jumbo_ops.disable) {
4299                 rtl_unlock_config_regs(tp);
4300                 tp->jumbo_ops.disable(tp);
4301                 rtl_lock_config_regs(tp);
4302         }
4303 }
4304
4305 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4306 {
4307         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4308         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4309         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4310 }
4311
4312 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4313 {
4314         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4315         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4316         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4317 }
4318
4319 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4320 {
4321         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4322 }
4323
4324 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4325 {
4326         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4327 }
4328
4329 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4330 {
4331         RTL_W8(tp, MaxTxPacketSize, 0x3f);
4332         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4333         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4334         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4335 }
4336
4337 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4338 {
4339         RTL_W8(tp, MaxTxPacketSize, 0x0c);
4340         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4341         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4342         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4343 }
4344
4345 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4346 {
4347         rtl_tx_performance_tweak(tp,
4348                 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4349 }
4350
4351 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4352 {
4353         rtl_tx_performance_tweak(tp,
4354                 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4355 }
4356
4357 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4358 {
4359         r8168b_0_hw_jumbo_enable(tp);
4360
4361         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4362 }
4363
4364 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4365 {
4366         r8168b_0_hw_jumbo_disable(tp);
4367
4368         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4369 }
4370
4371 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4372 {
4373         struct jumbo_ops *ops = &tp->jumbo_ops;
4374
4375         switch (tp->mac_version) {
4376         case RTL_GIGA_MAC_VER_11:
4377                 ops->disable    = r8168b_0_hw_jumbo_disable;
4378                 ops->enable     = r8168b_0_hw_jumbo_enable;
4379                 break;
4380         case RTL_GIGA_MAC_VER_12:
4381         case RTL_GIGA_MAC_VER_17:
4382                 ops->disable    = r8168b_1_hw_jumbo_disable;
4383                 ops->enable     = r8168b_1_hw_jumbo_enable;
4384                 break;
4385         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4386         case RTL_GIGA_MAC_VER_19:
4387         case RTL_GIGA_MAC_VER_20:
4388         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4389         case RTL_GIGA_MAC_VER_22:
4390         case RTL_GIGA_MAC_VER_23:
4391         case RTL_GIGA_MAC_VER_24:
4392         case RTL_GIGA_MAC_VER_25:
4393         case RTL_GIGA_MAC_VER_26:
4394                 ops->disable    = r8168c_hw_jumbo_disable;
4395                 ops->enable     = r8168c_hw_jumbo_enable;
4396                 break;
4397         case RTL_GIGA_MAC_VER_27:
4398         case RTL_GIGA_MAC_VER_28:
4399                 ops->disable    = r8168dp_hw_jumbo_disable;
4400                 ops->enable     = r8168dp_hw_jumbo_enable;
4401                 break;
4402         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4403         case RTL_GIGA_MAC_VER_32:
4404         case RTL_GIGA_MAC_VER_33:
4405         case RTL_GIGA_MAC_VER_34:
4406                 ops->disable    = r8168e_hw_jumbo_disable;
4407                 ops->enable     = r8168e_hw_jumbo_enable;
4408                 break;
4409
4410         /*
4411          * No action needed for jumbo frames with 8169.
4412          * No jumbo for 810x at all.
4413          */
4414         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4415         default:
4416                 ops->disable    = NULL;
4417                 ops->enable     = NULL;
4418                 break;
4419         }
4420 }
4421
4422 DECLARE_RTL_COND(rtl_chipcmd_cond)
4423 {
4424         return RTL_R8(tp, ChipCmd) & CmdReset;
4425 }
4426
4427 static void rtl_hw_reset(struct rtl8169_private *tp)
4428 {
4429         RTL_W8(tp, ChipCmd, CmdReset);
4430
4431         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4432 }
4433
4434 static void rtl_request_firmware(struct rtl8169_private *tp)
4435 {
4436         struct rtl_fw *rtl_fw;
4437         int rc = -ENOMEM;
4438
4439         /* firmware loaded already or no firmware available */
4440         if (tp->rtl_fw || !tp->fw_name)
4441                 return;
4442
4443         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4444         if (!rtl_fw)
4445                 goto err_warn;
4446
4447         rc = request_firmware(&rtl_fw->fw, tp->fw_name, tp_to_dev(tp));
4448         if (rc < 0)
4449                 goto err_free;
4450
4451         rc = rtl_check_firmware(tp, rtl_fw);
4452         if (rc < 0)
4453                 goto err_release_firmware;
4454
4455         tp->rtl_fw = rtl_fw;
4456
4457         return;
4458
4459 err_release_firmware:
4460         release_firmware(rtl_fw->fw);
4461 err_free:
4462         kfree(rtl_fw);
4463 err_warn:
4464         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4465                    tp->fw_name, rc);
4466 }
4467
4468 static void rtl_rx_close(struct rtl8169_private *tp)
4469 {
4470         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4471 }
4472
4473 DECLARE_RTL_COND(rtl_npq_cond)
4474 {
4475         return RTL_R8(tp, TxPoll) & NPQ;
4476 }
4477
4478 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4479 {
4480         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4481 }
4482
4483 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4484 {
4485         /* Disable interrupts */
4486         rtl8169_irq_mask_and_ack(tp);
4487
4488         rtl_rx_close(tp);
4489
4490         switch (tp->mac_version) {
4491         case RTL_GIGA_MAC_VER_27:
4492         case RTL_GIGA_MAC_VER_28:
4493         case RTL_GIGA_MAC_VER_31:
4494                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4495                 break;
4496         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4497         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4498                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4499                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4500                 break;
4501         default:
4502                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4503                 udelay(100);
4504                 break;
4505         }
4506
4507         rtl_hw_reset(tp);
4508 }
4509
4510 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4511 {
4512         u32 val = TX_DMA_BURST << TxDMAShift |
4513                   InterFrameGap << TxInterFrameGapShift;
4514
4515         if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4516             tp->mac_version != RTL_GIGA_MAC_VER_39)
4517                 val |= TXCFG_AUTO_FIFO;
4518
4519         RTL_W32(tp, TxConfig, val);
4520 }
4521
4522 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4523 {
4524         /* Low hurts. Let's disable the filtering. */
4525         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4526 }
4527
4528 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4529 {
4530         /*
4531          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4532          * register to be written before TxDescAddrLow to work.
4533          * Switching from MMIO to I/O access fixes the issue as well.
4534          */
4535         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4536         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4537         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4538         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4539 }
4540
4541 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4542 {
4543         u32 val;
4544
4545         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4546                 val = 0x000fff00;
4547         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4548                 val = 0x00ffff00;
4549         else
4550                 return;
4551
4552         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4553                 val |= 0xff;
4554
4555         RTL_W32(tp, 0x7c, val);
4556 }
4557
4558 static void rtl_set_rx_mode(struct net_device *dev)
4559 {
4560         struct rtl8169_private *tp = netdev_priv(dev);
4561         u32 mc_filter[2];       /* Multicast hash filter */
4562         int rx_mode;
4563         u32 tmp = 0;
4564
4565         if (dev->flags & IFF_PROMISC) {
4566                 /* Unconditionally log net taps. */
4567                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4568                 rx_mode =
4569                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4570                     AcceptAllPhys;
4571                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4572         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4573                    (dev->flags & IFF_ALLMULTI)) {
4574                 /* Too many to filter perfectly -- accept all multicasts. */
4575                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4576                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4577         } else {
4578                 struct netdev_hw_addr *ha;
4579
4580                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4581                 mc_filter[1] = mc_filter[0] = 0;
4582                 netdev_for_each_mc_addr(ha, dev) {
4583                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4584                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4585                         rx_mode |= AcceptMulticast;
4586                 }
4587         }
4588
4589         if (dev->features & NETIF_F_RXALL)
4590                 rx_mode |= (AcceptErr | AcceptRunt);
4591
4592         tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4593
4594         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4595                 u32 data = mc_filter[0];
4596
4597                 mc_filter[0] = swab32(mc_filter[1]);
4598                 mc_filter[1] = swab32(data);
4599         }
4600
4601         if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4602                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4603
4604         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4605         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4606
4607         RTL_W32(tp, RxConfig, tmp);
4608 }
4609
4610 static void rtl_hw_start(struct  rtl8169_private *tp)
4611 {
4612         rtl_unlock_config_regs(tp);
4613
4614         tp->hw_start(tp);
4615
4616         rtl_set_rx_max_size(tp);
4617         rtl_set_rx_tx_desc_registers(tp);
4618         rtl_lock_config_regs(tp);
4619
4620         /* disable interrupt coalescing */
4621         RTL_W16(tp, IntrMitigate, 0x0000);
4622         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4623         RTL_R8(tp, IntrMask);
4624         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4625         rtl_init_rxcfg(tp);
4626         rtl_set_tx_config_registers(tp);
4627
4628         rtl_set_rx_mode(tp->dev);
4629         /* no early-rx interrupts */
4630         RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4631         rtl_irq_enable(tp);
4632 }
4633
4634 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4635 {
4636         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4637                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4638
4639         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4640
4641         tp->cp_cmd |= PCIMulRW;
4642
4643         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4644             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4645                 netif_dbg(tp, drv, tp->dev,
4646                           "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4647                 tp->cp_cmd |= (1 << 14);
4648         }
4649
4650         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4651
4652         rtl8169_set_magic_reg(tp, tp->mac_version);
4653
4654         RTL_W32(tp, RxMissed, 0);
4655 }
4656
4657 DECLARE_RTL_COND(rtl_csiar_cond)
4658 {
4659         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4660 }
4661
4662 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4663 {
4664         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4665
4666         RTL_W32(tp, CSIDR, value);
4667         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4668                 CSIAR_BYTE_ENABLE | func << 16);
4669
4670         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4671 }
4672
4673 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4674 {
4675         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4676
4677         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4678                 CSIAR_BYTE_ENABLE);
4679
4680         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4681                 RTL_R32(tp, CSIDR) : ~0;
4682 }
4683
4684 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4685 {
4686         struct pci_dev *pdev = tp->pci_dev;
4687         u32 csi;
4688
4689         /* According to Realtek the value at config space address 0x070f
4690          * controls the L0s/L1 entrance latency. We try standard ECAM access
4691          * first and if it fails fall back to CSI.
4692          */
4693         if (pdev->cfg_size > 0x070f &&
4694             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4695                 return;
4696
4697         netdev_notice_once(tp->dev,
4698                 "No native access to PCI extended config space, falling back to CSI\n");
4699         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4700         rtl_csi_write(tp, 0x070c, csi | val << 24);
4701 }
4702
4703 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4704 {
4705         rtl_csi_access_enable(tp, 0x27);
4706 }
4707
4708 struct ephy_info {
4709         unsigned int offset;
4710         u16 mask;
4711         u16 bits;
4712 };
4713
4714 static void __rtl_ephy_init(struct rtl8169_private *tp,
4715                             const struct ephy_info *e, int len)
4716 {
4717         u16 w;
4718
4719         while (len-- > 0) {
4720                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4721                 rtl_ephy_write(tp, e->offset, w);
4722                 e++;
4723         }
4724 }
4725
4726 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4727
4728 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4729 {
4730         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4731                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4732 }
4733
4734 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4735 {
4736         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4737                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4738 }
4739
4740 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4741 {
4742         /* work around an issue when PCI reset occurs during L2/L3 state */
4743         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4744 }
4745
4746 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4747 {
4748         if (enable) {
4749                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4750                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4751         } else {
4752                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4753                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4754         }
4755
4756         udelay(10);
4757 }
4758
4759 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
4760                               u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
4761 {
4762         /* Usage of dynamic vs. static FIFO is controlled by bit
4763          * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4764          */
4765         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
4766         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
4767 }
4768
4769 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
4770                                           u8 low, u8 high)
4771 {
4772         /* FIFO thresholds for pause flow control */
4773         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
4774         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
4775 }
4776
4777 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4778 {
4779         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4780
4781         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4782         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4783
4784         if (tp->dev->mtu <= ETH_DATA_LEN) {
4785                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4786                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
4787         }
4788 }
4789
4790 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4791 {
4792         rtl_hw_start_8168bb(tp);
4793
4794         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4795
4796         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4797 }
4798
4799 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4800 {
4801         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4802
4803         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4804
4805         if (tp->dev->mtu <= ETH_DATA_LEN)
4806                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4807
4808         rtl_disable_clock_request(tp);
4809
4810         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4811         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4812 }
4813
4814 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4815 {
4816         static const struct ephy_info e_info_8168cp[] = {
4817                 { 0x01, 0,      0x0001 },
4818                 { 0x02, 0x0800, 0x1000 },
4819                 { 0x03, 0,      0x0042 },
4820                 { 0x06, 0x0080, 0x0000 },
4821                 { 0x07, 0,      0x2000 }
4822         };
4823
4824         rtl_set_def_aspm_entry_latency(tp);
4825
4826         rtl_ephy_init(tp, e_info_8168cp);
4827
4828         __rtl_hw_start_8168cp(tp);
4829 }
4830
4831 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4832 {
4833         rtl_set_def_aspm_entry_latency(tp);
4834
4835         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4836
4837         if (tp->dev->mtu <= ETH_DATA_LEN)
4838                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4839
4840         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4841         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4842 }
4843
4844 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4845 {
4846         rtl_set_def_aspm_entry_latency(tp);
4847
4848         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4849
4850         /* Magic. */
4851         RTL_W8(tp, DBG_REG, 0x20);
4852
4853         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4854
4855         if (tp->dev->mtu <= ETH_DATA_LEN)
4856                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4857
4858         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4859         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4860 }
4861
4862 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4863 {
4864         static const struct ephy_info e_info_8168c_1[] = {
4865                 { 0x02, 0x0800, 0x1000 },
4866                 { 0x03, 0,      0x0002 },
4867                 { 0x06, 0x0080, 0x0000 }
4868         };
4869
4870         rtl_set_def_aspm_entry_latency(tp);
4871
4872         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4873
4874         rtl_ephy_init(tp, e_info_8168c_1);
4875
4876         __rtl_hw_start_8168cp(tp);
4877 }
4878
4879 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4880 {
4881         static const struct ephy_info e_info_8168c_2[] = {
4882                 { 0x01, 0,      0x0001 },
4883                 { 0x03, 0x0400, 0x0220 }
4884         };
4885
4886         rtl_set_def_aspm_entry_latency(tp);
4887
4888         rtl_ephy_init(tp, e_info_8168c_2);
4889
4890         __rtl_hw_start_8168cp(tp);
4891 }
4892
4893 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4894 {
4895         rtl_hw_start_8168c_2(tp);
4896 }
4897
4898 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4899 {
4900         rtl_set_def_aspm_entry_latency(tp);
4901
4902         __rtl_hw_start_8168cp(tp);
4903 }
4904
4905 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4906 {
4907         rtl_set_def_aspm_entry_latency(tp);
4908
4909         rtl_disable_clock_request(tp);
4910
4911         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4912
4913         if (tp->dev->mtu <= ETH_DATA_LEN)
4914                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4915
4916         tp->cp_cmd &= CPCMD_QUIRK_MASK;
4917         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4918 }
4919
4920 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4921 {
4922         rtl_set_def_aspm_entry_latency(tp);
4923
4924         if (tp->dev->mtu <= ETH_DATA_LEN)
4925                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4926
4927         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4928
4929         rtl_disable_clock_request(tp);
4930 }
4931
4932 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4933 {
4934         static const struct ephy_info e_info_8168d_4[] = {
4935                 { 0x0b, 0x0000, 0x0048 },
4936                 { 0x19, 0x0020, 0x0050 },
4937                 { 0x0c, 0x0100, 0x0020 }
4938         };
4939
4940         rtl_set_def_aspm_entry_latency(tp);
4941
4942         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4943
4944         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4945
4946         rtl_ephy_init(tp, e_info_8168d_4);
4947
4948         rtl_enable_clock_request(tp);
4949 }
4950
4951 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4952 {
4953         static const struct ephy_info e_info_8168e_1[] = {
4954                 { 0x00, 0x0200, 0x0100 },
4955                 { 0x00, 0x0000, 0x0004 },
4956                 { 0x06, 0x0002, 0x0001 },
4957                 { 0x06, 0x0000, 0x0030 },
4958                 { 0x07, 0x0000, 0x2000 },
4959                 { 0x00, 0x0000, 0x0020 },
4960                 { 0x03, 0x5800, 0x2000 },
4961                 { 0x03, 0x0000, 0x0001 },
4962                 { 0x01, 0x0800, 0x1000 },
4963                 { 0x07, 0x0000, 0x4000 },
4964                 { 0x1e, 0x0000, 0x2000 },
4965                 { 0x19, 0xffff, 0xfe6c },
4966                 { 0x0a, 0x0000, 0x0040 }
4967         };
4968
4969         rtl_set_def_aspm_entry_latency(tp);
4970
4971         rtl_ephy_init(tp, e_info_8168e_1);
4972
4973         if (tp->dev->mtu <= ETH_DATA_LEN)
4974                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4975
4976         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4977
4978         rtl_disable_clock_request(tp);
4979
4980         /* Reset tx FIFO pointer */
4981         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4982         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4983
4984         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4985 }
4986
4987 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4988 {
4989         static const struct ephy_info e_info_8168e_2[] = {
4990                 { 0x09, 0x0000, 0x0080 },
4991                 { 0x19, 0x0000, 0x0224 }
4992         };
4993
4994         rtl_set_def_aspm_entry_latency(tp);
4995
4996         rtl_ephy_init(tp, e_info_8168e_2);
4997
4998         if (tp->dev->mtu <= ETH_DATA_LEN)
4999                 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5000
5001         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5002         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5003         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
5004         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
5005         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
5006         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
5007         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
5008
5009         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5010
5011         rtl_disable_clock_request(tp);
5012
5013         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5014
5015         rtl8168_config_eee_mac(tp);
5016
5017         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5018         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5019         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5020
5021         rtl_hw_aspm_clkreq_enable(tp, true);
5022 }
5023
5024 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5025 {
5026         rtl_set_def_aspm_entry_latency(tp);
5027
5028         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5029
5030         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5031         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5032         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
5033         rtl_reset_packet_filter(tp);
5034         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
5035         rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
5036         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
5037         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
5038
5039         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5040
5041         rtl_disable_clock_request(tp);
5042
5043         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5044         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5045         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5046         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5047
5048         rtl8168_config_eee_mac(tp);
5049 }
5050
5051 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5052 {
5053         static const struct ephy_info e_info_8168f_1[] = {
5054                 { 0x06, 0x00c0, 0x0020 },
5055                 { 0x08, 0x0001, 0x0002 },
5056                 { 0x09, 0x0000, 0x0080 },
5057                 { 0x19, 0x0000, 0x0224 }
5058         };
5059
5060         rtl_hw_start_8168f(tp);
5061
5062         rtl_ephy_init(tp, e_info_8168f_1);
5063
5064         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
5065 }
5066
5067 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5068 {
5069         static const struct ephy_info e_info_8168f_1[] = {
5070                 { 0x06, 0x00c0, 0x0020 },
5071                 { 0x0f, 0xffff, 0x5200 },
5072                 { 0x1e, 0x0000, 0x4000 },
5073                 { 0x19, 0x0000, 0x0224 }
5074         };
5075
5076         rtl_hw_start_8168f(tp);
5077         rtl_pcie_state_l2l3_disable(tp);
5078
5079         rtl_ephy_init(tp, e_info_8168f_1);
5080
5081         rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
5082 }
5083
5084 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5085 {
5086         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5087         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
5088
5089         rtl_set_def_aspm_entry_latency(tp);
5090
5091         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5092
5093         rtl_reset_packet_filter(tp);
5094         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
5095
5096         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5097         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5098
5099         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5100         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5101
5102         rtl8168_config_eee_mac(tp);
5103
5104         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
5105         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
5106
5107         rtl_pcie_state_l2l3_disable(tp);
5108 }
5109
5110 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5111 {
5112         static const struct ephy_info e_info_8168g_1[] = {
5113                 { 0x00, 0x0000, 0x0008 },
5114                 { 0x0c, 0x37d0, 0x0820 },
5115                 { 0x1e, 0x0000, 0x0001 },
5116                 { 0x19, 0x8000, 0x0000 }
5117         };
5118
5119         rtl_hw_start_8168g(tp);
5120
5121         /* disable aspm and clock request before access ephy */
5122         rtl_hw_aspm_clkreq_enable(tp, false);
5123         rtl_ephy_init(tp, e_info_8168g_1);
5124         rtl_hw_aspm_clkreq_enable(tp, true);
5125 }
5126
5127 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5128 {
5129         static const struct ephy_info e_info_8168g_2[] = {
5130                 { 0x00, 0x0000, 0x0008 },
5131                 { 0x0c, 0x3df0, 0x0200 },
5132                 { 0x19, 0xffff, 0xfc00 },
5133                 { 0x1e, 0xffff, 0x20eb }
5134         };
5135
5136         rtl_hw_start_8168g(tp);
5137
5138         /* disable aspm and clock request before access ephy */
5139         RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5140         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5141         rtl_ephy_init(tp, e_info_8168g_2);
5142 }
5143
5144 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5145 {
5146         static const struct ephy_info e_info_8411_2[] = {
5147                 { 0x00, 0x0000, 0x0008 },
5148                 { 0x0c, 0x3df0, 0x0200 },
5149                 { 0x0f, 0xffff, 0x5200 },
5150                 { 0x19, 0x0020, 0x0000 },
5151                 { 0x1e, 0x0000, 0x2000 }
5152         };
5153
5154         rtl_hw_start_8168g(tp);
5155
5156         /* disable aspm and clock request before access ephy */
5157         rtl_hw_aspm_clkreq_enable(tp, false);
5158         rtl_ephy_init(tp, e_info_8411_2);
5159         rtl_hw_aspm_clkreq_enable(tp, true);
5160 }
5161
5162 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5163 {
5164         int rg_saw_cnt;
5165         u32 data;
5166         static const struct ephy_info e_info_8168h_1[] = {
5167                 { 0x1e, 0x0800, 0x0001 },
5168                 { 0x1d, 0x0000, 0x0800 },
5169                 { 0x05, 0xffff, 0x2089 },
5170                 { 0x06, 0xffff, 0x5881 },
5171                 { 0x04, 0xffff, 0x154a },
5172                 { 0x01, 0xffff, 0x068b }
5173         };
5174
5175         /* disable aspm and clock request before access ephy */
5176         rtl_hw_aspm_clkreq_enable(tp, false);
5177         rtl_ephy_init(tp, e_info_8168h_1);
5178
5179         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5180         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
5181
5182         rtl_set_def_aspm_entry_latency(tp);
5183
5184         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5185
5186         rtl_reset_packet_filter(tp);
5187
5188         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
5189
5190         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
5191
5192         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5193
5194         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5195         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5196
5197         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5198         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5199
5200         rtl8168_config_eee_mac(tp);
5201
5202         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5203         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5204
5205         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5206
5207         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
5208
5209         rtl_pcie_state_l2l3_disable(tp);
5210
5211         rtl_writephy(tp, 0x1f, 0x0c42);
5212         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5213         rtl_writephy(tp, 0x1f, 0x0000);
5214         if (rg_saw_cnt > 0) {
5215                 u16 sw_cnt_1ms_ini;
5216
5217                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5218                 sw_cnt_1ms_ini &= 0x0fff;
5219                 data = r8168_mac_ocp_read(tp, 0xd412);
5220                 data &= ~0x0fff;
5221                 data |= sw_cnt_1ms_ini;
5222                 r8168_mac_ocp_write(tp, 0xd412, data);
5223         }
5224
5225         data = r8168_mac_ocp_read(tp, 0xe056);
5226         data &= ~0xf0;
5227         data |= 0x70;
5228         r8168_mac_ocp_write(tp, 0xe056, data);
5229
5230         data = r8168_mac_ocp_read(tp, 0xe052);
5231         data &= ~0x6000;
5232         data |= 0x8008;
5233         r8168_mac_ocp_write(tp, 0xe052, data);
5234
5235         data = r8168_mac_ocp_read(tp, 0xe0d6);
5236         data &= ~0x01ff;
5237         data |= 0x017f;
5238         r8168_mac_ocp_write(tp, 0xe0d6, data);
5239
5240         data = r8168_mac_ocp_read(tp, 0xd420);
5241         data &= ~0x0fff;
5242         data |= 0x047f;
5243         r8168_mac_ocp_write(tp, 0xd420, data);
5244
5245         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5246         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5247         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5248         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5249
5250         rtl_hw_aspm_clkreq_enable(tp, true);
5251 }
5252
5253 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5254 {
5255         rtl8168ep_stop_cmac(tp);
5256
5257         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5258         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
5259
5260         rtl_set_def_aspm_entry_latency(tp);
5261
5262         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5263
5264         rtl_reset_packet_filter(tp);
5265
5266         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
5267
5268         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5269
5270         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5271         RTL_W8(tp, MaxTxPacketSize, EarlySize);
5272
5273         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5274         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5275
5276         rtl8168_config_eee_mac(tp);
5277
5278         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
5279
5280         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5281
5282         rtl_pcie_state_l2l3_disable(tp);
5283 }
5284
5285 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5286 {
5287         static const struct ephy_info e_info_8168ep_1[] = {
5288                 { 0x00, 0xffff, 0x10ab },
5289                 { 0x06, 0xffff, 0xf030 },
5290                 { 0x08, 0xffff, 0x2006 },
5291                 { 0x0d, 0xffff, 0x1666 },
5292                 { 0x0c, 0x3ff0, 0x0000 }
5293         };
5294
5295         /* disable aspm and clock request before access ephy */
5296         rtl_hw_aspm_clkreq_enable(tp, false);
5297         rtl_ephy_init(tp, e_info_8168ep_1);
5298
5299         rtl_hw_start_8168ep(tp);
5300
5301         rtl_hw_aspm_clkreq_enable(tp, true);
5302 }
5303
5304 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5305 {
5306         static const struct ephy_info e_info_8168ep_2[] = {
5307                 { 0x00, 0xffff, 0x10a3 },
5308                 { 0x19, 0xffff, 0xfc00 },
5309                 { 0x1e, 0xffff, 0x20ea }
5310         };
5311
5312         /* disable aspm and clock request before access ephy */
5313         rtl_hw_aspm_clkreq_enable(tp, false);
5314         rtl_ephy_init(tp, e_info_8168ep_2);
5315
5316         rtl_hw_start_8168ep(tp);
5317
5318         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5319         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5320
5321         rtl_hw_aspm_clkreq_enable(tp, true);
5322 }
5323
5324 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5325 {
5326         u32 data;
5327         static const struct ephy_info e_info_8168ep_3[] = {
5328                 { 0x00, 0xffff, 0x10a3 },
5329                 { 0x19, 0xffff, 0x7c00 },
5330                 { 0x1e, 0xffff, 0x20eb },
5331                 { 0x0d, 0xffff, 0x1666 }
5332         };
5333
5334         /* disable aspm and clock request before access ephy */
5335         rtl_hw_aspm_clkreq_enable(tp, false);
5336         rtl_ephy_init(tp, e_info_8168ep_3);
5337
5338         rtl_hw_start_8168ep(tp);
5339
5340         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5341         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5342
5343         data = r8168_mac_ocp_read(tp, 0xd3e2);
5344         data &= 0xf000;
5345         data |= 0x0271;
5346         r8168_mac_ocp_write(tp, 0xd3e2, data);
5347
5348         data = r8168_mac_ocp_read(tp, 0xd3e4);
5349         data &= 0xff00;
5350         r8168_mac_ocp_write(tp, 0xd3e4, data);
5351
5352         data = r8168_mac_ocp_read(tp, 0xe860);
5353         data |= 0x0080;
5354         r8168_mac_ocp_write(tp, 0xe860, data);
5355
5356         rtl_hw_aspm_clkreq_enable(tp, true);
5357 }
5358
5359 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5360 {
5361         static const struct ephy_info e_info_8102e_1[] = {
5362                 { 0x01, 0, 0x6e65 },
5363                 { 0x02, 0, 0x091f },
5364                 { 0x03, 0, 0xc2f9 },
5365                 { 0x06, 0, 0xafb5 },
5366                 { 0x07, 0, 0x0e00 },
5367                 { 0x19, 0, 0xec80 },
5368                 { 0x01, 0, 0x2e65 },
5369                 { 0x01, 0, 0x6e65 }
5370         };
5371         u8 cfg1;
5372
5373         rtl_set_def_aspm_entry_latency(tp);
5374
5375         RTL_W8(tp, DBG_REG, FIX_NAK_1);
5376
5377         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5378
5379         RTL_W8(tp, Config1,
5380                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5381         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5382
5383         cfg1 = RTL_R8(tp, Config1);
5384         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5385                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5386
5387         rtl_ephy_init(tp, e_info_8102e_1);
5388 }
5389
5390 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5391 {
5392         rtl_set_def_aspm_entry_latency(tp);
5393
5394         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5395
5396         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5397         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5398 }
5399
5400 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5401 {
5402         rtl_hw_start_8102e_2(tp);
5403
5404         rtl_ephy_write(tp, 0x03, 0xc2f9);
5405 }
5406
5407 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5408 {
5409         static const struct ephy_info e_info_8105e_1[] = {
5410                 { 0x07, 0, 0x4000 },
5411                 { 0x19, 0, 0x0200 },
5412                 { 0x19, 0, 0x0020 },
5413                 { 0x1e, 0, 0x2000 },
5414                 { 0x03, 0, 0x0001 },
5415                 { 0x19, 0, 0x0100 },
5416                 { 0x19, 0, 0x0004 },
5417                 { 0x0a, 0, 0x0020 }
5418         };
5419
5420         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5421         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5422
5423         /* Disable Early Tally Counter */
5424         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5425
5426         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5427         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5428
5429         rtl_ephy_init(tp, e_info_8105e_1);
5430
5431         rtl_pcie_state_l2l3_disable(tp);
5432 }
5433
5434 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5435 {
5436         rtl_hw_start_8105e_1(tp);
5437         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5438 }
5439
5440 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5441 {
5442         static const struct ephy_info e_info_8402[] = {
5443                 { 0x19, 0xffff, 0xff64 },
5444                 { 0x1e, 0, 0x4000 }
5445         };
5446
5447         rtl_set_def_aspm_entry_latency(tp);
5448
5449         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5450         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5451
5452         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5453
5454         rtl_ephy_init(tp, e_info_8402);
5455
5456         rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5457
5458         rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
5459         rtl_reset_packet_filter(tp);
5460         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5461         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5462         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
5463
5464         rtl_pcie_state_l2l3_disable(tp);
5465 }
5466
5467 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5468 {
5469         rtl_hw_aspm_clkreq_enable(tp, false);
5470
5471         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5472         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5473
5474         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5475         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5476         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5477
5478         rtl_pcie_state_l2l3_disable(tp);
5479         rtl_hw_aspm_clkreq_enable(tp, true);
5480 }
5481
5482 static void rtl_hw_config(struct rtl8169_private *tp)
5483 {
5484         static const rtl_generic_fct hw_configs[] = {
5485                 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
5486                 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
5487                 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
5488                 [RTL_GIGA_MAC_VER_10] = NULL,
5489                 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb,
5490                 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef,
5491                 [RTL_GIGA_MAC_VER_13] = NULL,
5492                 [RTL_GIGA_MAC_VER_14] = NULL,
5493                 [RTL_GIGA_MAC_VER_15] = NULL,
5494                 [RTL_GIGA_MAC_VER_16] = NULL,
5495                 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef,
5496                 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
5497                 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
5498                 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
5499                 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
5500                 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
5501                 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
5502                 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
5503                 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
5504                 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
5505                 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
5506                 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
5507                 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
5508                 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
5509                 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp,
5510                 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
5511                 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
5512                 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
5513                 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
5514                 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
5515                 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
5516                 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
5517                 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
5518                 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
5519                 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
5520                 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
5521                 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
5522                 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
5523                 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
5524                 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
5525                 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
5526                 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
5527                 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
5528                 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
5529                 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
5530         };
5531
5532         if (hw_configs[tp->mac_version])
5533                 hw_configs[tp->mac_version](tp);
5534 }
5535
5536 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5537 {
5538         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5539
5540         /* Workaround for RxFIFO overflow. */
5541         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5542                 tp->irq_mask |= RxFIFOOver;
5543                 tp->irq_mask &= ~RxOverflow;
5544         }
5545
5546         rtl_hw_config(tp);
5547 }
5548
5549 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5550 {
5551         if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5552                 tp->irq_mask &= ~RxFIFOOver;
5553
5554         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5555             tp->mac_version == RTL_GIGA_MAC_VER_16)
5556                 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5557                                          PCI_EXP_DEVCTL_NOSNOOP_EN);
5558
5559         RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5560
5561         tp->cp_cmd &= CPCMD_QUIRK_MASK;
5562         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5563
5564         rtl_hw_config(tp);
5565 }
5566
5567 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5568 {
5569         struct rtl8169_private *tp = netdev_priv(dev);
5570
5571         if (new_mtu > ETH_DATA_LEN)
5572                 rtl_hw_jumbo_enable(tp);
5573         else
5574                 rtl_hw_jumbo_disable(tp);
5575
5576         dev->mtu = new_mtu;
5577         netdev_update_features(dev);
5578
5579         return 0;
5580 }
5581
5582 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5583 {
5584         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5585         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5586 }
5587
5588 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5589                                      void **data_buff, struct RxDesc *desc)
5590 {
5591         dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5592                          R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5593
5594         kfree(*data_buff);
5595         *data_buff = NULL;
5596         rtl8169_make_unusable_by_asic(desc);
5597 }
5598
5599 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5600 {
5601         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5602
5603         /* Force memory writes to complete before releasing descriptor */
5604         dma_wmb();
5605
5606         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5607 }
5608
5609 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5610                                              struct RxDesc *desc)
5611 {
5612         void *data;
5613         dma_addr_t mapping;
5614         struct device *d = tp_to_dev(tp);
5615         int node = dev_to_node(d);
5616
5617         data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5618         if (!data)
5619                 return NULL;
5620
5621         /* Memory should be properly aligned, but better check. */
5622         if (!IS_ALIGNED((unsigned long)data, 8)) {
5623                 netdev_err_once(tp->dev, "RX buffer not 8-byte-aligned\n");
5624                 goto err_out;
5625         }
5626
5627         mapping = dma_map_single(d, data, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5628         if (unlikely(dma_mapping_error(d, mapping))) {
5629                 if (net_ratelimit())
5630                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5631                 goto err_out;
5632         }
5633
5634         desc->addr = cpu_to_le64(mapping);
5635         rtl8169_mark_to_asic(desc);
5636         return data;
5637
5638 err_out:
5639         kfree(data);
5640         return NULL;
5641 }
5642
5643 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5644 {
5645         unsigned int i;
5646
5647         for (i = 0; i < NUM_RX_DESC; i++) {
5648                 if (tp->Rx_databuff[i]) {
5649                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5650                                             tp->RxDescArray + i);
5651                 }
5652         }
5653 }
5654
5655 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5656 {
5657         desc->opts1 |= cpu_to_le32(RingEnd);
5658 }
5659
5660 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5661 {
5662         unsigned int i;
5663
5664         for (i = 0; i < NUM_RX_DESC; i++) {
5665                 void *data;
5666
5667                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5668                 if (!data) {
5669                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5670                         goto err_out;
5671                 }
5672                 tp->Rx_databuff[i] = data;
5673         }
5674
5675         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5676         return 0;
5677
5678 err_out:
5679         rtl8169_rx_clear(tp);
5680         return -ENOMEM;
5681 }
5682
5683 static int rtl8169_init_ring(struct rtl8169_private *tp)
5684 {
5685         rtl8169_init_ring_indexes(tp);
5686
5687         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5688         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5689
5690         return rtl8169_rx_fill(tp);
5691 }
5692
5693 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5694                                  struct TxDesc *desc)
5695 {
5696         unsigned int len = tx_skb->len;
5697
5698         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5699
5700         desc->opts1 = 0x00;
5701         desc->opts2 = 0x00;
5702         desc->addr = 0x00;
5703         tx_skb->len = 0;
5704 }
5705
5706 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5707                                    unsigned int n)
5708 {
5709         unsigned int i;
5710
5711         for (i = 0; i < n; i++) {
5712                 unsigned int entry = (start + i) % NUM_TX_DESC;
5713                 struct ring_info *tx_skb = tp->tx_skb + entry;
5714                 unsigned int len = tx_skb->len;
5715
5716                 if (len) {
5717                         struct sk_buff *skb = tx_skb->skb;
5718
5719                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5720                                              tp->TxDescArray + entry);
5721                         if (skb) {
5722                                 dev_consume_skb_any(skb);
5723                                 tx_skb->skb = NULL;
5724                         }
5725                 }
5726         }
5727 }
5728
5729 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5730 {
5731         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5732         tp->cur_tx = tp->dirty_tx = 0;
5733         netdev_reset_queue(tp->dev);
5734 }
5735
5736 static void rtl_reset_work(struct rtl8169_private *tp)
5737 {
5738         struct net_device *dev = tp->dev;
5739         int i;
5740
5741         napi_disable(&tp->napi);
5742         netif_stop_queue(dev);
5743         synchronize_rcu();
5744
5745         rtl8169_hw_reset(tp);
5746
5747         for (i = 0; i < NUM_RX_DESC; i++)
5748                 rtl8169_mark_to_asic(tp->RxDescArray + i);
5749
5750         rtl8169_tx_clear(tp);
5751         rtl8169_init_ring_indexes(tp);
5752
5753         napi_enable(&tp->napi);
5754         rtl_hw_start(tp);
5755         netif_wake_queue(dev);
5756 }
5757
5758 static void rtl8169_tx_timeout(struct net_device *dev)
5759 {
5760         struct rtl8169_private *tp = netdev_priv(dev);
5761
5762         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5763 }
5764
5765 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5766 {
5767         u32 status = opts0 | len;
5768
5769         if (entry == NUM_TX_DESC - 1)
5770                 status |= RingEnd;
5771
5772         return cpu_to_le32(status);
5773 }
5774
5775 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5776                               u32 *opts)
5777 {
5778         struct skb_shared_info *info = skb_shinfo(skb);
5779         unsigned int cur_frag, entry;
5780         struct TxDesc *uninitialized_var(txd);
5781         struct device *d = tp_to_dev(tp);
5782
5783         entry = tp->cur_tx;
5784         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5785                 const skb_frag_t *frag = info->frags + cur_frag;
5786                 dma_addr_t mapping;
5787                 u32 len;
5788                 void *addr;
5789
5790                 entry = (entry + 1) % NUM_TX_DESC;
5791
5792                 txd = tp->TxDescArray + entry;
5793                 len = skb_frag_size(frag);
5794                 addr = skb_frag_address(frag);
5795                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5796                 if (unlikely(dma_mapping_error(d, mapping))) {
5797                         if (net_ratelimit())
5798                                 netif_err(tp, drv, tp->dev,
5799                                           "Failed to map TX fragments DMA!\n");
5800                         goto err_out;
5801                 }
5802
5803                 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5804                 txd->opts2 = cpu_to_le32(opts[1]);
5805                 txd->addr = cpu_to_le64(mapping);
5806
5807                 tp->tx_skb[entry].len = len;
5808         }
5809
5810         if (cur_frag) {
5811                 tp->tx_skb[entry].skb = skb;
5812                 txd->opts1 |= cpu_to_le32(LastFrag);
5813         }
5814
5815         return cur_frag;
5816
5817 err_out:
5818         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5819         return -EIO;
5820 }
5821
5822 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5823 {
5824         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5825 }
5826
5827 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5828                                       struct net_device *dev);
5829 /* r8169_csum_workaround()
5830  * The hw limites the value the transport offset. When the offset is out of the
5831  * range, calculate the checksum by sw.
5832  */
5833 static void r8169_csum_workaround(struct rtl8169_private *tp,
5834                                   struct sk_buff *skb)
5835 {
5836         if (skb_shinfo(skb)->gso_size) {
5837                 netdev_features_t features = tp->dev->features;
5838                 struct sk_buff *segs, *nskb;
5839
5840                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5841                 segs = skb_gso_segment(skb, features);
5842                 if (IS_ERR(segs) || !segs)
5843                         goto drop;
5844
5845                 do {
5846                         nskb = segs;
5847                         segs = segs->next;
5848                         nskb->next = NULL;
5849                         rtl8169_start_xmit(nskb, tp->dev);
5850                 } while (segs);
5851
5852                 dev_consume_skb_any(skb);
5853         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5854                 if (skb_checksum_help(skb) < 0)
5855                         goto drop;
5856
5857                 rtl8169_start_xmit(skb, tp->dev);
5858         } else {
5859                 struct net_device_stats *stats;
5860
5861 drop:
5862                 stats = &tp->dev->stats;
5863                 stats->tx_dropped++;
5864                 dev_kfree_skb_any(skb);
5865         }
5866 }
5867
5868 /* msdn_giant_send_check()
5869  * According to the document of microsoft, the TCP Pseudo Header excludes the
5870  * packet length for IPv6 TCP large packets.
5871  */
5872 static int msdn_giant_send_check(struct sk_buff *skb)
5873 {
5874         const struct ipv6hdr *ipv6h;
5875         struct tcphdr *th;
5876         int ret;
5877
5878         ret = skb_cow_head(skb, 0);
5879         if (ret)
5880                 return ret;
5881
5882         ipv6h = ipv6_hdr(skb);
5883         th = tcp_hdr(skb);
5884
5885         th->check = 0;
5886         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5887
5888         return ret;
5889 }
5890
5891 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
5892                                 struct sk_buff *skb, u32 *opts)
5893 {
5894         u32 mss = skb_shinfo(skb)->gso_size;
5895
5896         if (mss) {
5897                 opts[0] |= TD_LSO;
5898                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5899         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5900                 const struct iphdr *ip = ip_hdr(skb);
5901
5902                 if (ip->protocol == IPPROTO_TCP)
5903                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5904                 else if (ip->protocol == IPPROTO_UDP)
5905                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5906                 else
5907                         WARN_ON_ONCE(1);
5908         }
5909
5910         return true;
5911 }
5912
5913 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5914                                 struct sk_buff *skb, u32 *opts)
5915 {
5916         u32 transport_offset = (u32)skb_transport_offset(skb);
5917         u32 mss = skb_shinfo(skb)->gso_size;
5918
5919         if (mss) {
5920                 if (transport_offset > GTTCPHO_MAX) {
5921                         netif_warn(tp, tx_err, tp->dev,
5922                                    "Invalid transport offset 0x%x for TSO\n",
5923                                    transport_offset);
5924                         return false;
5925                 }
5926
5927                 switch (vlan_get_protocol(skb)) {
5928                 case htons(ETH_P_IP):
5929                         opts[0] |= TD1_GTSENV4;
5930                         break;
5931
5932                 case htons(ETH_P_IPV6):
5933                         if (msdn_giant_send_check(skb))
5934                                 return false;
5935
5936                         opts[0] |= TD1_GTSENV6;
5937                         break;
5938
5939                 default:
5940                         WARN_ON_ONCE(1);
5941                         break;
5942                 }
5943
5944                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5945                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
5946         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5947                 u8 ip_protocol;
5948
5949                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5950                         return !(skb_checksum_help(skb) || eth_skb_pad(skb));
5951
5952                 if (transport_offset > TCPHO_MAX) {
5953                         netif_warn(tp, tx_err, tp->dev,
5954                                    "Invalid transport offset 0x%x\n",
5955                                    transport_offset);
5956                         return false;
5957                 }
5958
5959                 switch (vlan_get_protocol(skb)) {
5960                 case htons(ETH_P_IP):
5961                         opts[1] |= TD1_IPv4_CS;
5962                         ip_protocol = ip_hdr(skb)->protocol;
5963                         break;
5964
5965                 case htons(ETH_P_IPV6):
5966                         opts[1] |= TD1_IPv6_CS;
5967                         ip_protocol = ipv6_hdr(skb)->nexthdr;
5968                         break;
5969
5970                 default:
5971                         ip_protocol = IPPROTO_RAW;
5972                         break;
5973                 }
5974
5975                 if (ip_protocol == IPPROTO_TCP)
5976                         opts[1] |= TD1_TCP_CS;
5977                 else if (ip_protocol == IPPROTO_UDP)
5978                         opts[1] |= TD1_UDP_CS;
5979                 else
5980                         WARN_ON_ONCE(1);
5981
5982                 opts[1] |= transport_offset << TCPHO_SHIFT;
5983         } else {
5984                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5985                         return !eth_skb_pad(skb);
5986         }
5987
5988         return true;
5989 }
5990
5991 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
5992                                unsigned int nr_frags)
5993 {
5994         unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
5995
5996         /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
5997         return slots_avail > nr_frags;
5998 }
5999
6000 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6001                                       struct net_device *dev)
6002 {
6003         struct rtl8169_private *tp = netdev_priv(dev);
6004         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
6005         struct TxDesc *txd = tp->TxDescArray + entry;
6006         struct device *d = tp_to_dev(tp);
6007         dma_addr_t mapping;
6008         u32 opts[2], len;
6009         int frags;
6010
6011         if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
6012                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6013                 goto err_stop_0;
6014         }
6015
6016         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6017                 goto err_stop_0;
6018
6019         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6020         opts[0] = DescOwn;
6021
6022         if (!tp->tso_csum(tp, skb, opts)) {
6023                 r8169_csum_workaround(tp, skb);
6024                 return NETDEV_TX_OK;
6025         }
6026
6027         len = skb_headlen(skb);
6028         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6029         if (unlikely(dma_mapping_error(d, mapping))) {
6030                 if (net_ratelimit())
6031                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6032                 goto err_dma_0;
6033         }
6034
6035         tp->tx_skb[entry].len = len;
6036         txd->addr = cpu_to_le64(mapping);
6037
6038         frags = rtl8169_xmit_frags(tp, skb, opts);
6039         if (frags < 0)
6040                 goto err_dma_1;
6041         else if (frags)
6042                 opts[0] |= FirstFrag;
6043         else {
6044                 opts[0] |= FirstFrag | LastFrag;
6045                 tp->tx_skb[entry].skb = skb;
6046         }
6047
6048         txd->opts2 = cpu_to_le32(opts[1]);
6049
6050         netdev_sent_queue(dev, skb->len);
6051
6052         skb_tx_timestamp(skb);
6053
6054         /* Force memory writes to complete before releasing descriptor */
6055         dma_wmb();
6056
6057         txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
6058
6059         /* Force all memory writes to complete before notifying device */
6060         wmb();
6061
6062         tp->cur_tx += frags + 1;
6063
6064         RTL_W8(tp, TxPoll, NPQ);
6065
6066         if (!rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6067                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6068                  * not miss a ring update when it notices a stopped queue.
6069                  */
6070                 smp_wmb();
6071                 netif_stop_queue(dev);
6072                 /* Sync with rtl_tx:
6073                  * - publish queue status and cur_tx ring index (write barrier)
6074                  * - refresh dirty_tx ring index (read barrier).
6075                  * May the current thread have a pessimistic view of the ring
6076                  * status and forget to wake up queue, a racing rtl_tx thread
6077                  * can't.
6078                  */
6079                 smp_mb();
6080                 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
6081                         netif_start_queue(dev);
6082         }
6083
6084         return NETDEV_TX_OK;
6085
6086 err_dma_1:
6087         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6088 err_dma_0:
6089         dev_kfree_skb_any(skb);
6090         dev->stats.tx_dropped++;
6091         return NETDEV_TX_OK;
6092
6093 err_stop_0:
6094         netif_stop_queue(dev);
6095         dev->stats.tx_dropped++;
6096         return NETDEV_TX_BUSY;
6097 }
6098
6099 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6100 {
6101         struct rtl8169_private *tp = netdev_priv(dev);
6102         struct pci_dev *pdev = tp->pci_dev;
6103         u16 pci_status, pci_cmd;
6104
6105         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6106         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6107
6108         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6109                   pci_cmd, pci_status);
6110
6111         /*
6112          * The recovery sequence below admits a very elaborated explanation:
6113          * - it seems to work;
6114          * - I did not see what else could be done;
6115          * - it makes iop3xx happy.
6116          *
6117          * Feel free to adjust to your needs.
6118          */
6119         if (pdev->broken_parity_status)
6120                 pci_cmd &= ~PCI_COMMAND_PARITY;
6121         else
6122                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6123
6124         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6125
6126         pci_write_config_word(pdev, PCI_STATUS,
6127                 pci_status & (PCI_STATUS_DETECTED_PARITY |
6128                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6129                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6130
6131         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6132 }
6133
6134 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
6135                    int budget)
6136 {
6137         unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
6138
6139         dirty_tx = tp->dirty_tx;
6140         smp_rmb();
6141         tx_left = tp->cur_tx - dirty_tx;
6142
6143         while (tx_left > 0) {
6144                 unsigned int entry = dirty_tx % NUM_TX_DESC;
6145                 struct ring_info *tx_skb = tp->tx_skb + entry;
6146                 u32 status;
6147
6148                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6149                 if (status & DescOwn)
6150                         break;
6151
6152                 /* This barrier is needed to keep us from reading
6153                  * any other fields out of the Tx descriptor until
6154                  * we know the status of DescOwn
6155                  */
6156                 dma_rmb();
6157
6158                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6159                                      tp->TxDescArray + entry);
6160                 if (status & LastFrag) {
6161                         pkts_compl++;
6162                         bytes_compl += tx_skb->skb->len;
6163                         napi_consume_skb(tx_skb->skb, budget);
6164                         tx_skb->skb = NULL;
6165                 }
6166                 dirty_tx++;
6167                 tx_left--;
6168         }
6169
6170         if (tp->dirty_tx != dirty_tx) {
6171                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
6172
6173                 u64_stats_update_begin(&tp->tx_stats.syncp);
6174                 tp->tx_stats.packets += pkts_compl;
6175                 tp->tx_stats.bytes += bytes_compl;
6176                 u64_stats_update_end(&tp->tx_stats.syncp);
6177
6178                 tp->dirty_tx = dirty_tx;
6179                 /* Sync with rtl8169_start_xmit:
6180                  * - publish dirty_tx ring index (write barrier)
6181                  * - refresh cur_tx ring index and queue status (read barrier)
6182                  * May the current thread miss the stopped queue condition,
6183                  * a racing xmit thread can only have a right view of the
6184                  * ring status.
6185                  */
6186                 smp_mb();
6187                 if (netif_queue_stopped(dev) &&
6188                     rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
6189                         netif_wake_queue(dev);
6190                 }
6191                 /*
6192                  * 8168 hack: TxPoll requests are lost when the Tx packets are
6193                  * too close. Let's kick an extra TxPoll request when a burst
6194                  * of start_xmit activity is detected (if it is not detected,
6195                  * it is slow enough). -- FR
6196                  */
6197                 if (tp->cur_tx != dirty_tx)
6198                         RTL_W8(tp, TxPoll, NPQ);
6199         }
6200 }
6201
6202 static inline int rtl8169_fragmented_frame(u32 status)
6203 {
6204         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6205 }
6206
6207 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6208 {
6209         u32 status = opts1 & RxProtoMask;
6210
6211         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6212             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6213                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6214         else
6215                 skb_checksum_none_assert(skb);
6216 }
6217
6218 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6219                                            struct rtl8169_private *tp,
6220                                            int pkt_size,
6221                                            dma_addr_t addr)
6222 {
6223         struct sk_buff *skb;
6224         struct device *d = tp_to_dev(tp);
6225
6226         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6227         prefetch(data);
6228         skb = napi_alloc_skb(&tp->napi, pkt_size);
6229         if (skb)
6230                 skb_copy_to_linear_data(skb, data, pkt_size);
6231         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6232
6233         return skb;
6234 }
6235
6236 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6237 {
6238         unsigned int cur_rx, rx_left;
6239         unsigned int count;
6240
6241         cur_rx = tp->cur_rx;
6242
6243         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6244                 unsigned int entry = cur_rx % NUM_RX_DESC;
6245                 struct RxDesc *desc = tp->RxDescArray + entry;
6246                 u32 status;
6247
6248                 status = le32_to_cpu(desc->opts1);
6249                 if (status & DescOwn)
6250                         break;
6251
6252                 /* This barrier is needed to keep us from reading
6253                  * any other fields out of the Rx descriptor until
6254                  * we know the status of DescOwn
6255                  */
6256                 dma_rmb();
6257
6258                 if (unlikely(status & RxRES)) {
6259                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6260                                    status);
6261                         dev->stats.rx_errors++;
6262                         if (status & (RxRWT | RxRUNT))
6263                                 dev->stats.rx_length_errors++;
6264                         if (status & RxCRC)
6265                                 dev->stats.rx_crc_errors++;
6266                         /* RxFOVF is a reserved bit on later chip versions */
6267                         if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6268                             status & RxFOVF) {
6269                                 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6270                                 dev->stats.rx_fifo_errors++;
6271                         } else if (status & (RxRUNT | RxCRC) &&
6272                                    !(status & RxRWT) &&
6273                                    dev->features & NETIF_F_RXALL) {
6274                                 goto process_pkt;
6275                         }
6276                 } else {
6277                         struct sk_buff *skb;
6278                         dma_addr_t addr;
6279                         int pkt_size;
6280
6281 process_pkt:
6282                         addr = le64_to_cpu(desc->addr);
6283                         if (likely(!(dev->features & NETIF_F_RXFCS)))
6284                                 pkt_size = (status & 0x00003fff) - 4;
6285                         else
6286                                 pkt_size = status & 0x00003fff;
6287
6288                         /*
6289                          * The driver does not support incoming fragmented
6290                          * frames. They are seen as a symptom of over-mtu
6291                          * sized frames.
6292                          */
6293                         if (unlikely(rtl8169_fragmented_frame(status))) {
6294                                 dev->stats.rx_dropped++;
6295                                 dev->stats.rx_length_errors++;
6296                                 goto release_descriptor;
6297                         }
6298
6299                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6300                                                   tp, pkt_size, addr);
6301                         if (!skb) {
6302                                 dev->stats.rx_dropped++;
6303                                 goto release_descriptor;
6304                         }
6305
6306                         rtl8169_rx_csum(skb, status);
6307                         skb_put(skb, pkt_size);
6308                         skb->protocol = eth_type_trans(skb, dev);
6309
6310                         rtl8169_rx_vlan_tag(desc, skb);
6311
6312                         if (skb->pkt_type == PACKET_MULTICAST)
6313                                 dev->stats.multicast++;
6314
6315                         napi_gro_receive(&tp->napi, skb);
6316
6317                         u64_stats_update_begin(&tp->rx_stats.syncp);
6318                         tp->rx_stats.packets++;
6319                         tp->rx_stats.bytes += pkt_size;
6320                         u64_stats_update_end(&tp->rx_stats.syncp);
6321                 }
6322 release_descriptor:
6323                 desc->opts2 = 0;
6324                 rtl8169_mark_to_asic(desc);
6325         }
6326
6327         count = cur_rx - tp->cur_rx;
6328         tp->cur_rx = cur_rx;
6329
6330         return count;
6331 }
6332
6333 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6334 {
6335         struct rtl8169_private *tp = dev_instance;
6336         u16 status = RTL_R16(tp, IntrStatus);
6337
6338         if (!tp->irq_enabled || status == 0xffff || !(status & tp->irq_mask))
6339                 return IRQ_NONE;
6340
6341         if (unlikely(status & SYSErr)) {
6342                 rtl8169_pcierr_interrupt(tp->dev);
6343                 goto out;
6344         }
6345
6346         if (status & LinkChg)
6347                 phy_mac_interrupt(tp->phydev);
6348
6349         if (unlikely(status & RxFIFOOver &&
6350             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6351                 netif_stop_queue(tp->dev);
6352                 /* XXX - Hack alert. See rtl_task(). */
6353                 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6354         }
6355
6356         rtl_irq_disable(tp);
6357         napi_schedule_irqoff(&tp->napi);
6358 out:
6359         rtl_ack_events(tp, status);
6360
6361         return IRQ_HANDLED;
6362 }
6363
6364 static void rtl_task(struct work_struct *work)
6365 {
6366         static const struct {
6367                 int bitnr;
6368                 void (*action)(struct rtl8169_private *);
6369         } rtl_work[] = {
6370                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6371         };
6372         struct rtl8169_private *tp =
6373                 container_of(work, struct rtl8169_private, wk.work);
6374         struct net_device *dev = tp->dev;
6375         int i;
6376
6377         rtl_lock_work(tp);
6378
6379         if (!netif_running(dev) ||
6380             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6381                 goto out_unlock;
6382
6383         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6384                 bool pending;
6385
6386                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6387                 if (pending)
6388                         rtl_work[i].action(tp);
6389         }
6390
6391 out_unlock:
6392         rtl_unlock_work(tp);
6393 }
6394
6395 static int rtl8169_poll(struct napi_struct *napi, int budget)
6396 {
6397         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6398         struct net_device *dev = tp->dev;
6399         int work_done;
6400
6401         work_done = rtl_rx(dev, tp, (u32) budget);
6402
6403         rtl_tx(dev, tp, budget);
6404
6405         if (work_done < budget) {
6406                 napi_complete_done(napi, work_done);
6407                 rtl_irq_enable(tp);
6408         }
6409
6410         return work_done;
6411 }
6412
6413 static void rtl8169_rx_missed(struct net_device *dev)
6414 {
6415         struct rtl8169_private *tp = netdev_priv(dev);
6416
6417         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6418                 return;
6419
6420         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6421         RTL_W32(tp, RxMissed, 0);
6422 }
6423
6424 static void r8169_phylink_handler(struct net_device *ndev)
6425 {
6426         struct rtl8169_private *tp = netdev_priv(ndev);
6427
6428         if (netif_carrier_ok(ndev)) {
6429                 rtl_link_chg_patch(tp);
6430                 pm_request_resume(&tp->pci_dev->dev);
6431         } else {
6432                 pm_runtime_idle(&tp->pci_dev->dev);
6433         }
6434
6435         if (net_ratelimit())
6436                 phy_print_status(tp->phydev);
6437 }
6438
6439 static int r8169_phy_connect(struct rtl8169_private *tp)
6440 {
6441         struct phy_device *phydev = tp->phydev;
6442         phy_interface_t phy_mode;
6443         int ret;
6444
6445         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6446                    PHY_INTERFACE_MODE_MII;
6447
6448         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6449                                  phy_mode);
6450         if (ret)
6451                 return ret;
6452
6453         if (!tp->supports_gmii)
6454                 phy_set_max_speed(phydev, SPEED_100);
6455
6456         phy_support_asym_pause(phydev);
6457
6458         phy_attached_info(phydev);
6459
6460         return 0;
6461 }
6462
6463 static void rtl8169_down(struct net_device *dev)
6464 {
6465         struct rtl8169_private *tp = netdev_priv(dev);
6466
6467         phy_stop(tp->phydev);
6468
6469         napi_disable(&tp->napi);
6470         netif_stop_queue(dev);
6471
6472         rtl8169_hw_reset(tp);
6473         /*
6474          * At this point device interrupts can not be enabled in any function,
6475          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6476          * and napi is disabled (rtl8169_poll).
6477          */
6478         rtl8169_rx_missed(dev);
6479
6480         /* Give a racing hard_start_xmit a few cycles to complete. */
6481         synchronize_rcu();
6482
6483         rtl8169_tx_clear(tp);
6484
6485         rtl8169_rx_clear(tp);
6486
6487         rtl_pll_power_down(tp);
6488 }
6489
6490 static int rtl8169_close(struct net_device *dev)
6491 {
6492         struct rtl8169_private *tp = netdev_priv(dev);
6493         struct pci_dev *pdev = tp->pci_dev;
6494
6495         pm_runtime_get_sync(&pdev->dev);
6496
6497         /* Update counters before going down */
6498         rtl8169_update_counters(tp);
6499
6500         rtl_lock_work(tp);
6501         /* Clear all task flags */
6502         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6503
6504         rtl8169_down(dev);
6505         rtl_unlock_work(tp);
6506
6507         cancel_work_sync(&tp->wk.work);
6508
6509         phy_disconnect(tp->phydev);
6510
6511         pci_free_irq(pdev, 0, tp);
6512
6513         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6514                           tp->RxPhyAddr);
6515         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6516                           tp->TxPhyAddr);
6517         tp->TxDescArray = NULL;
6518         tp->RxDescArray = NULL;
6519
6520         pm_runtime_put_sync(&pdev->dev);
6521
6522         return 0;
6523 }
6524
6525 #ifdef CONFIG_NET_POLL_CONTROLLER
6526 static void rtl8169_netpoll(struct net_device *dev)
6527 {
6528         struct rtl8169_private *tp = netdev_priv(dev);
6529
6530         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6531 }
6532 #endif
6533
6534 static int rtl_open(struct net_device *dev)
6535 {
6536         struct rtl8169_private *tp = netdev_priv(dev);
6537         struct pci_dev *pdev = tp->pci_dev;
6538         int retval = -ENOMEM;
6539
6540         pm_runtime_get_sync(&pdev->dev);
6541
6542         /*
6543          * Rx and Tx descriptors needs 256 bytes alignment.
6544          * dma_alloc_coherent provides more.
6545          */
6546         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6547                                              &tp->TxPhyAddr, GFP_KERNEL);
6548         if (!tp->TxDescArray)
6549                 goto err_pm_runtime_put;
6550
6551         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6552                                              &tp->RxPhyAddr, GFP_KERNEL);
6553         if (!tp->RxDescArray)
6554                 goto err_free_tx_0;
6555
6556         retval = rtl8169_init_ring(tp);
6557         if (retval < 0)
6558                 goto err_free_rx_1;
6559
6560         rtl_request_firmware(tp);
6561
6562         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6563                                  dev->name);
6564         if (retval < 0)
6565                 goto err_release_fw_2;
6566
6567         retval = r8169_phy_connect(tp);
6568         if (retval)
6569                 goto err_free_irq;
6570
6571         rtl_lock_work(tp);
6572
6573         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6574
6575         napi_enable(&tp->napi);
6576
6577         rtl8169_init_phy(dev, tp);
6578
6579         rtl_pll_power_up(tp);
6580
6581         rtl_hw_start(tp);
6582
6583         if (!rtl8169_init_counter_offsets(tp))
6584                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6585
6586         phy_start(tp->phydev);
6587         netif_start_queue(dev);
6588
6589         rtl_unlock_work(tp);
6590
6591         pm_runtime_put_sync(&pdev->dev);
6592 out:
6593         return retval;
6594
6595 err_free_irq:
6596         pci_free_irq(pdev, 0, tp);
6597 err_release_fw_2:
6598         rtl_release_firmware(tp);
6599         rtl8169_rx_clear(tp);
6600 err_free_rx_1:
6601         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6602                           tp->RxPhyAddr);
6603         tp->RxDescArray = NULL;
6604 err_free_tx_0:
6605         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6606                           tp->TxPhyAddr);
6607         tp->TxDescArray = NULL;
6608 err_pm_runtime_put:
6609         pm_runtime_put_noidle(&pdev->dev);
6610         goto out;
6611 }
6612
6613 static void
6614 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6615 {
6616         struct rtl8169_private *tp = netdev_priv(dev);
6617         struct pci_dev *pdev = tp->pci_dev;
6618         struct rtl8169_counters *counters = tp->counters;
6619         unsigned int start;
6620
6621         pm_runtime_get_noresume(&pdev->dev);
6622
6623         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6624                 rtl8169_rx_missed(dev);
6625
6626         do {
6627                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6628                 stats->rx_packets = tp->rx_stats.packets;
6629                 stats->rx_bytes = tp->rx_stats.bytes;
6630         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6631
6632         do {
6633                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6634                 stats->tx_packets = tp->tx_stats.packets;
6635                 stats->tx_bytes = tp->tx_stats.bytes;
6636         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6637
6638         stats->rx_dropped       = dev->stats.rx_dropped;
6639         stats->tx_dropped       = dev->stats.tx_dropped;
6640         stats->rx_length_errors = dev->stats.rx_length_errors;
6641         stats->rx_errors        = dev->stats.rx_errors;
6642         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6643         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6644         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6645         stats->multicast        = dev->stats.multicast;
6646
6647         /*
6648          * Fetch additonal counter values missing in stats collected by driver
6649          * from tally counters.
6650          */
6651         if (pm_runtime_active(&pdev->dev))
6652                 rtl8169_update_counters(tp);
6653
6654         /*
6655          * Subtract values fetched during initalization.
6656          * See rtl8169_init_counter_offsets for a description why we do that.
6657          */
6658         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6659                 le64_to_cpu(tp->tc_offset.tx_errors);
6660         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6661                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6662         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6663                 le16_to_cpu(tp->tc_offset.tx_aborted);
6664
6665         pm_runtime_put_noidle(&pdev->dev);
6666 }
6667
6668 static void rtl8169_net_suspend(struct net_device *dev)
6669 {
6670         struct rtl8169_private *tp = netdev_priv(dev);
6671
6672         if (!netif_running(dev))
6673                 return;
6674
6675         phy_stop(tp->phydev);
6676         netif_device_detach(dev);
6677
6678         rtl_lock_work(tp);
6679         napi_disable(&tp->napi);
6680         /* Clear all task flags */
6681         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6682
6683         rtl_unlock_work(tp);
6684
6685         rtl_pll_power_down(tp);
6686 }
6687
6688 #ifdef CONFIG_PM
6689
6690 static int rtl8169_suspend(struct device *device)
6691 {
6692         struct net_device *dev = dev_get_drvdata(device);
6693         struct rtl8169_private *tp = netdev_priv(dev);
6694
6695         rtl8169_net_suspend(dev);
6696         clk_disable_unprepare(tp->clk);
6697
6698         return 0;
6699 }
6700
6701 static void __rtl8169_resume(struct net_device *dev)
6702 {
6703         struct rtl8169_private *tp = netdev_priv(dev);
6704
6705         netif_device_attach(dev);
6706
6707         rtl_pll_power_up(tp);
6708         rtl8169_init_phy(dev, tp);
6709
6710         phy_start(tp->phydev);
6711
6712         rtl_lock_work(tp);
6713         napi_enable(&tp->napi);
6714         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6715         rtl_reset_work(tp);
6716         rtl_unlock_work(tp);
6717 }
6718
6719 static int rtl8169_resume(struct device *device)
6720 {
6721         struct net_device *dev = dev_get_drvdata(device);
6722         struct rtl8169_private *tp = netdev_priv(dev);
6723
6724         clk_prepare_enable(tp->clk);
6725
6726         if (netif_running(dev))
6727                 __rtl8169_resume(dev);
6728
6729         return 0;
6730 }
6731
6732 static int rtl8169_runtime_suspend(struct device *device)
6733 {
6734         struct net_device *dev = dev_get_drvdata(device);
6735         struct rtl8169_private *tp = netdev_priv(dev);
6736
6737         if (!tp->TxDescArray)
6738                 return 0;
6739
6740         rtl_lock_work(tp);
6741         __rtl8169_set_wol(tp, WAKE_ANY);
6742         rtl_unlock_work(tp);
6743
6744         rtl8169_net_suspend(dev);
6745
6746         /* Update counters before going runtime suspend */
6747         rtl8169_rx_missed(dev);
6748         rtl8169_update_counters(tp);
6749
6750         return 0;
6751 }
6752
6753 static int rtl8169_runtime_resume(struct device *device)
6754 {
6755         struct net_device *dev = dev_get_drvdata(device);
6756         struct rtl8169_private *tp = netdev_priv(dev);
6757         rtl_rar_set(tp, dev->dev_addr);
6758
6759         if (!tp->TxDescArray)
6760                 return 0;
6761
6762         rtl_lock_work(tp);
6763         __rtl8169_set_wol(tp, tp->saved_wolopts);
6764         rtl_unlock_work(tp);
6765
6766         __rtl8169_resume(dev);
6767
6768         return 0;
6769 }
6770
6771 static int rtl8169_runtime_idle(struct device *device)
6772 {
6773         struct net_device *dev = dev_get_drvdata(device);
6774
6775         if (!netif_running(dev) || !netif_carrier_ok(dev))
6776                 pm_schedule_suspend(device, 10000);
6777
6778         return -EBUSY;
6779 }
6780
6781 static const struct dev_pm_ops rtl8169_pm_ops = {
6782         .suspend                = rtl8169_suspend,
6783         .resume                 = rtl8169_resume,
6784         .freeze                 = rtl8169_suspend,
6785         .thaw                   = rtl8169_resume,
6786         .poweroff               = rtl8169_suspend,
6787         .restore                = rtl8169_resume,
6788         .runtime_suspend        = rtl8169_runtime_suspend,
6789         .runtime_resume         = rtl8169_runtime_resume,
6790         .runtime_idle           = rtl8169_runtime_idle,
6791 };
6792
6793 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6794
6795 #else /* !CONFIG_PM */
6796
6797 #define RTL8169_PM_OPS  NULL
6798
6799 #endif /* !CONFIG_PM */
6800
6801 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6802 {
6803         /* WoL fails with 8168b when the receiver is disabled. */
6804         switch (tp->mac_version) {
6805         case RTL_GIGA_MAC_VER_11:
6806         case RTL_GIGA_MAC_VER_12:
6807         case RTL_GIGA_MAC_VER_17:
6808                 pci_clear_master(tp->pci_dev);
6809
6810                 RTL_W8(tp, ChipCmd, CmdRxEnb);
6811                 /* PCI commit */
6812                 RTL_R8(tp, ChipCmd);
6813                 break;
6814         default:
6815                 break;
6816         }
6817 }
6818
6819 static void rtl_shutdown(struct pci_dev *pdev)
6820 {
6821         struct net_device *dev = pci_get_drvdata(pdev);
6822         struct rtl8169_private *tp = netdev_priv(dev);
6823
6824         rtl8169_net_suspend(dev);
6825
6826         /* Restore original MAC address */
6827         rtl_rar_set(tp, dev->perm_addr);
6828
6829         rtl8169_hw_reset(tp);
6830
6831         if (system_state == SYSTEM_POWER_OFF) {
6832                 if (tp->saved_wolopts) {
6833                         rtl_wol_suspend_quirk(tp);
6834                         rtl_wol_shutdown_quirk(tp);
6835                 }
6836
6837                 pci_wake_from_d3(pdev, true);
6838                 pci_set_power_state(pdev, PCI_D3hot);
6839         }
6840 }
6841
6842 static void rtl_remove_one(struct pci_dev *pdev)
6843 {
6844         struct net_device *dev = pci_get_drvdata(pdev);
6845         struct rtl8169_private *tp = netdev_priv(dev);
6846
6847         if (r8168_check_dash(tp))
6848                 rtl8168_driver_stop(tp);
6849
6850         netif_napi_del(&tp->napi);
6851
6852         unregister_netdev(dev);
6853         mdiobus_unregister(tp->phydev->mdio.bus);
6854
6855         rtl_release_firmware(tp);
6856
6857         if (pci_dev_run_wake(pdev))
6858                 pm_runtime_get_noresume(&pdev->dev);
6859
6860         /* restore original MAC address */
6861         rtl_rar_set(tp, dev->perm_addr);
6862 }
6863
6864 static const struct net_device_ops rtl_netdev_ops = {
6865         .ndo_open               = rtl_open,
6866         .ndo_stop               = rtl8169_close,
6867         .ndo_get_stats64        = rtl8169_get_stats64,
6868         .ndo_start_xmit         = rtl8169_start_xmit,
6869         .ndo_tx_timeout         = rtl8169_tx_timeout,
6870         .ndo_validate_addr      = eth_validate_addr,
6871         .ndo_change_mtu         = rtl8169_change_mtu,
6872         .ndo_fix_features       = rtl8169_fix_features,
6873         .ndo_set_features       = rtl8169_set_features,
6874         .ndo_set_mac_address    = rtl_set_mac_address,
6875         .ndo_do_ioctl           = rtl8169_ioctl,
6876         .ndo_set_rx_mode        = rtl_set_rx_mode,
6877 #ifdef CONFIG_NET_POLL_CONTROLLER
6878         .ndo_poll_controller    = rtl8169_netpoll,
6879 #endif
6880
6881 };
6882
6883 static const struct rtl_cfg_info {
6884         void (*hw_start)(struct rtl8169_private *tp);
6885         u16 irq_mask;
6886         unsigned int has_gmii:1;
6887         const struct rtl_coalesce_info *coalesce_info;
6888 } rtl_cfg_infos [] = {
6889         [RTL_CFG_0] = {
6890                 .hw_start       = rtl_hw_start_8169,
6891                 .irq_mask       = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
6892                 .has_gmii       = 1,
6893                 .coalesce_info  = rtl_coalesce_info_8169,
6894         },
6895         [RTL_CFG_1] = {
6896                 .hw_start       = rtl_hw_start_8168,
6897                 .irq_mask       = LinkChg | RxOverflow,
6898                 .has_gmii       = 1,
6899                 .coalesce_info  = rtl_coalesce_info_8168_8136,
6900         },
6901         [RTL_CFG_2] = {
6902                 .hw_start       = rtl_hw_start_8101,
6903                 .irq_mask       = LinkChg | RxOverflow | RxFIFOOver,
6904                 .coalesce_info  = rtl_coalesce_info_8168_8136,
6905         }
6906 };
6907
6908 static int rtl_alloc_irq(struct rtl8169_private *tp)
6909 {
6910         unsigned int flags;
6911
6912         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
6913                 rtl_unlock_config_regs(tp);
6914                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
6915                 rtl_lock_config_regs(tp);
6916                 flags = PCI_IRQ_LEGACY;
6917         } else {
6918                 flags = PCI_IRQ_ALL_TYPES;
6919         }
6920
6921         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
6922 }
6923
6924 static void rtl_read_mac_address(struct rtl8169_private *tp,
6925                                  u8 mac_addr[ETH_ALEN])
6926 {
6927         u32 value;
6928
6929         /* Get MAC address */
6930         switch (tp->mac_version) {
6931         case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
6932         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6933                 value = rtl_eri_read(tp, 0xe0);
6934                 mac_addr[0] = (value >>  0) & 0xff;
6935                 mac_addr[1] = (value >>  8) & 0xff;
6936                 mac_addr[2] = (value >> 16) & 0xff;
6937                 mac_addr[3] = (value >> 24) & 0xff;
6938
6939                 value = rtl_eri_read(tp, 0xe4);
6940                 mac_addr[4] = (value >>  0) & 0xff;
6941                 mac_addr[5] = (value >>  8) & 0xff;
6942                 break;
6943         default:
6944                 break;
6945         }
6946 }
6947
6948 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6949 {
6950         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
6951 }
6952
6953 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6954 {
6955         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6956 }
6957
6958 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
6959 {
6960         struct rtl8169_private *tp = mii_bus->priv;
6961
6962         if (phyaddr > 0)
6963                 return -ENODEV;
6964
6965         return rtl_readphy(tp, phyreg);
6966 }
6967
6968 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
6969                                 int phyreg, u16 val)
6970 {
6971         struct rtl8169_private *tp = mii_bus->priv;
6972
6973         if (phyaddr > 0)
6974                 return -ENODEV;
6975
6976         rtl_writephy(tp, phyreg, val);
6977
6978         return 0;
6979 }
6980
6981 static int r8169_mdio_register(struct rtl8169_private *tp)
6982 {
6983         struct pci_dev *pdev = tp->pci_dev;
6984         struct mii_bus *new_bus;
6985         int ret;
6986
6987         new_bus = devm_mdiobus_alloc(&pdev->dev);
6988         if (!new_bus)
6989                 return -ENOMEM;
6990
6991         new_bus->name = "r8169";
6992         new_bus->priv = tp;
6993         new_bus->parent = &pdev->dev;
6994         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
6995         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
6996
6997         new_bus->read = r8169_mdio_read_reg;
6998         new_bus->write = r8169_mdio_write_reg;
6999
7000         ret = mdiobus_register(new_bus);
7001         if (ret)
7002                 return ret;
7003
7004         tp->phydev = mdiobus_get_phy(new_bus, 0);
7005         if (!tp->phydev) {
7006                 mdiobus_unregister(new_bus);
7007                 return -ENODEV;
7008         }
7009
7010         /* PHY will be woken up in rtl_open() */
7011         phy_suspend(tp->phydev);
7012
7013         return 0;
7014 }
7015
7016 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7017 {
7018         u32 data;
7019
7020         tp->ocp_base = OCP_STD_PHY_BASE;
7021
7022         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
7023
7024         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7025                 return;
7026
7027         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7028                 return;
7029
7030         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7031         msleep(1);
7032         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7033
7034         data = r8168_mac_ocp_read(tp, 0xe8de);
7035         data &= ~(1 << 14);
7036         r8168_mac_ocp_write(tp, 0xe8de, data);
7037
7038         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7039                 return;
7040
7041         data = r8168_mac_ocp_read(tp, 0xe8de);
7042         data |= (1 << 15);
7043         r8168_mac_ocp_write(tp, 0xe8de, data);
7044
7045         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7046                 return;
7047 }
7048
7049 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7050 {
7051         rtl8168ep_stop_cmac(tp);
7052         rtl_hw_init_8168g(tp);
7053 }
7054
7055 static void rtl_hw_initialize(struct rtl8169_private *tp)
7056 {
7057         switch (tp->mac_version) {
7058         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
7059                 rtl_hw_init_8168g(tp);
7060                 break;
7061         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
7062                 rtl_hw_init_8168ep(tp);
7063                 break;
7064         default:
7065                 break;
7066         }
7067 }
7068
7069 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
7070 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
7071 {
7072         switch (tp->mac_version) {
7073         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7074         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
7075                 return false;
7076         default:
7077                 return true;
7078         }
7079 }
7080
7081 static int rtl_jumbo_max(struct rtl8169_private *tp)
7082 {
7083         /* Non-GBit versions don't support jumbo frames */
7084         if (!tp->supports_gmii)
7085                 return JUMBO_1K;
7086
7087         switch (tp->mac_version) {
7088         /* RTL8169 */
7089         case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7090                 return JUMBO_7K;
7091         /* RTL8168b */
7092         case RTL_GIGA_MAC_VER_11:
7093         case RTL_GIGA_MAC_VER_12:
7094         case RTL_GIGA_MAC_VER_17:
7095                 return JUMBO_4K;
7096         /* RTL8168c */
7097         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7098                 return JUMBO_6K;
7099         default:
7100                 return JUMBO_9K;
7101         }
7102 }
7103
7104 static void rtl_disable_clk(void *data)
7105 {
7106         clk_disable_unprepare(data);
7107 }
7108
7109 static int rtl_get_ether_clk(struct rtl8169_private *tp)
7110 {
7111         struct device *d = tp_to_dev(tp);
7112         struct clk *clk;
7113         int rc;
7114
7115         clk = devm_clk_get(d, "ether_clk");
7116         if (IS_ERR(clk)) {
7117                 rc = PTR_ERR(clk);
7118                 if (rc == -ENOENT)
7119                         /* clk-core allows NULL (for suspend / resume) */
7120                         rc = 0;
7121                 else if (rc != -EPROBE_DEFER)
7122                         dev_err(d, "failed to get clk: %d\n", rc);
7123         } else {
7124                 tp->clk = clk;
7125                 rc = clk_prepare_enable(clk);
7126                 if (rc)
7127                         dev_err(d, "failed to enable clk: %d\n", rc);
7128                 else
7129                         rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
7130         }
7131
7132         return rc;
7133 }
7134
7135 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7136 {
7137         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7138         /* align to u16 for is_valid_ether_addr() */
7139         u8 mac_addr[ETH_ALEN] __aligned(2) = {};
7140         struct rtl8169_private *tp;
7141         struct net_device *dev;
7142         int chipset, region, i;
7143         int jumbo_max, rc;
7144
7145         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7146         if (!dev)
7147                 return -ENOMEM;
7148
7149         SET_NETDEV_DEV(dev, &pdev->dev);
7150         dev->netdev_ops = &rtl_netdev_ops;
7151         tp = netdev_priv(dev);
7152         tp->dev = dev;
7153         tp->pci_dev = pdev;
7154         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7155         tp->supports_gmii = cfg->has_gmii;
7156
7157         /* Get the *optional* external "ether_clk" used on some boards */
7158         rc = rtl_get_ether_clk(tp);
7159         if (rc)
7160                 return rc;
7161
7162         /* Disable ASPM completely as that cause random device stop working
7163          * problems as well as full system hangs for some PCIe devices users.
7164          */
7165         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
7166
7167         /* enable device (incl. PCI PM wakeup and hotplug setup) */
7168         rc = pcim_enable_device(pdev);
7169         if (rc < 0) {
7170                 dev_err(&pdev->dev, "enable failure\n");
7171                 return rc;
7172         }
7173
7174         if (pcim_set_mwi(pdev) < 0)
7175                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7176
7177         /* use first MMIO region */
7178         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7179         if (region < 0) {
7180                 dev_err(&pdev->dev, "no MMIO resource found\n");
7181                 return -ENODEV;
7182         }
7183
7184         /* check for weird/broken PCI region reporting */
7185         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7186                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7187                 return -ENODEV;
7188         }
7189
7190         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7191         if (rc < 0) {
7192                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7193                 return rc;
7194         }
7195
7196         tp->mmio_addr = pcim_iomap_table(pdev)[region];
7197
7198         /* Identify chip attached to board */
7199         rtl8169_get_mac_version(tp);
7200         if (tp->mac_version == RTL_GIGA_MAC_NONE)
7201                 return -ENODEV;
7202
7203         if (rtl_tbi_enabled(tp)) {
7204                 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7205                 return -ENODEV;
7206         }
7207
7208         tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7209
7210         if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
7211             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
7212                 dev->features |= NETIF_F_HIGHDMA;
7213         } else {
7214                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7215                 if (rc < 0) {
7216                         dev_err(&pdev->dev, "DMA configuration failed\n");
7217                         return rc;
7218                 }
7219         }
7220
7221         rtl_init_rxcfg(tp);
7222
7223         rtl8169_irq_mask_and_ack(tp);
7224
7225         rtl_hw_initialize(tp);
7226
7227         rtl_hw_reset(tp);
7228
7229         pci_set_master(pdev);
7230
7231         rtl_init_mdio_ops(tp);
7232         rtl_init_jumbo_ops(tp);
7233
7234         chipset = tp->mac_version;
7235
7236         rc = rtl_alloc_irq(tp);
7237         if (rc < 0) {
7238                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7239                 return rc;
7240         }
7241
7242         mutex_init(&tp->wk.mutex);
7243         INIT_WORK(&tp->wk.work, rtl_task);
7244         u64_stats_init(&tp->rx_stats.syncp);
7245         u64_stats_init(&tp->tx_stats.syncp);
7246
7247         /* get MAC address */
7248         rc = eth_platform_get_mac_address(&pdev->dev, mac_addr);
7249         if (rc)
7250                 rtl_read_mac_address(tp, mac_addr);
7251
7252         if (is_valid_ether_addr(mac_addr))
7253                 rtl_rar_set(tp, mac_addr);
7254
7255         for (i = 0; i < ETH_ALEN; i++)
7256                 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7257
7258         dev->ethtool_ops = &rtl8169_ethtool_ops;
7259
7260         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7261
7262         /* don't enable SG, IP_CSUM and TSO by default - it might not work
7263          * properly for all devices */
7264         dev->features |= NETIF_F_RXCSUM |
7265                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7266
7267         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7268                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7269                 NETIF_F_HW_VLAN_CTAG_RX;
7270         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7271                 NETIF_F_HIGHDMA;
7272         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7273
7274         tp->cp_cmd |= RxChkSum | RxVlan;
7275
7276         /*
7277          * Pretend we are using VLANs; This bypasses a nasty bug where
7278          * Interrupts stop flowing on high load on 8110SCd controllers.
7279          */
7280         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7281                 /* Disallow toggling */
7282                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7283
7284         if (rtl_chip_supports_csum_v2(tp)) {
7285                 tp->tso_csum = rtl8169_tso_csum_v2;
7286                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7287         } else {
7288                 tp->tso_csum = rtl8169_tso_csum_v1;
7289         }
7290
7291         dev->hw_features |= NETIF_F_RXALL;
7292         dev->hw_features |= NETIF_F_RXFCS;
7293
7294         /* MTU range: 60 - hw-specific max */
7295         dev->min_mtu = ETH_ZLEN;
7296         jumbo_max = rtl_jumbo_max(tp);
7297         dev->max_mtu = jumbo_max;
7298
7299         tp->hw_start = cfg->hw_start;
7300         tp->irq_mask = RTL_EVENT_NAPI | cfg->irq_mask;
7301         tp->coalesce_info = cfg->coalesce_info;
7302
7303         tp->fw_name = rtl_chip_infos[chipset].fw_name;
7304
7305         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7306                                             &tp->counters_phys_addr,
7307                                             GFP_KERNEL);
7308         if (!tp->counters)
7309                 return -ENOMEM;
7310
7311         pci_set_drvdata(pdev, dev);
7312
7313         rc = r8169_mdio_register(tp);
7314         if (rc)
7315                 return rc;
7316
7317         /* chip gets powered up in rtl_open() */
7318         rtl_pll_power_down(tp);
7319
7320         rc = register_netdev(dev);
7321         if (rc)
7322                 goto err_mdio_unregister;
7323
7324         netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
7325                    rtl_chip_infos[chipset].name, dev->dev_addr,
7326                    (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
7327                    pci_irq_vector(pdev, 0));
7328
7329         if (jumbo_max > JUMBO_1K)
7330                 netif_info(tp, probe, dev,
7331                            "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7332                            jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7333                            "ok" : "ko");
7334
7335         if (r8168_check_dash(tp))
7336                 rtl8168_driver_start(tp);
7337
7338         if (pci_dev_run_wake(pdev))
7339                 pm_runtime_put_sync(&pdev->dev);
7340
7341         return 0;
7342
7343 err_mdio_unregister:
7344         mdiobus_unregister(tp->phydev->mdio.bus);
7345         return rc;
7346 }
7347
7348 static struct pci_driver rtl8169_pci_driver = {
7349         .name           = MODULENAME,
7350         .id_table       = rtl8169_pci_tbl,
7351         .probe          = rtl_init_one,
7352         .remove         = rtl_remove_one,
7353         .shutdown       = rtl_shutdown,
7354         .driver.pm      = RTL8169_PM_OPS,
7355 };
7356
7357 module_pci_driver(rtl8169_pci_driver);