drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* 10G controller driver for Samsung SoCs
   3  *
   4  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * Author: Siva Reddy Kallam <siva.kallam@samsung.com>
   8  */
   9
  10 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  11
  12 #include <linux/clk.h>
  13 #include <linux/crc32.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/ethtool.h>
  17 #include <linux/if.h>
  18 #include <linux/if_ether.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/ip.h>
  23 #include <linux/kernel.h>
  24 #include <linux/mii.h>
  25 #include <linux/module.h>
  26 #include <linux/net_tstamp.h>
  27 #include <linux/netdevice.h>
  28 #include <linux/phy.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/prefetch.h>
  31 #include <linux/skbuff.h>
  32 #include <linux/slab.h>
  33 #include <linux/tcp.h>
  34 #include <linux/sxgbe_platform.h>
  35
  36 #include "sxgbe_common.h"
  37 #include "sxgbe_desc.h"
  38 #include "sxgbe_dma.h"
  39 #include "sxgbe_mtl.h"
  40 #include "sxgbe_reg.h"
  41
  42 #define SXGBE_ALIGN(x)  L1_CACHE_ALIGN(x)
  43 #define JUMBO_LEN       9000
  44
  45 /* Module parameters */
  46 #define TX_TIMEO        5000
  47 #define DMA_TX_SIZE     512
  48 #define DMA_RX_SIZE     1024
  49 #define TC_DEFAULT      64
  50 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
  51 /* The default timer value as per the sxgbe specification 1 sec(1000 ms) */
  52 #define SXGBE_DEFAULT_LPI_TIMER 1000
  53
  54 static int debug = -1;
  55 static int eee_timer = SXGBE_DEFAULT_LPI_TIMER;
  56
  57 module_param(eee_timer, int, 0644);
  58
  59 module_param(debug, int, 0644);
  60 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
  61                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
  62                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
  63
  64 static irqreturn_t sxgbe_common_interrupt(int irq, void *dev_id);
  65 static irqreturn_t sxgbe_tx_interrupt(int irq, void *dev_id);
  66 static irqreturn_t sxgbe_rx_interrupt(int irq, void *dev_id);
  67
  68 #define SXGBE_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
  69
  70 #define SXGBE_LPI_TIMER(x) (jiffies + msecs_to_jiffies(x))
  71
  72 /**
  73  * sxgbe_verify_args - verify the driver parameters.
  74  * Description: it verifies if some wrong parameter is passed to the driver.
  75  * Note that wrong parameters are replaced with the default values.
  76  */
  77 static void sxgbe_verify_args(void)
  78 {
  79         if (unlikely(eee_timer < 0))
  80                 eee_timer = SXGBE_DEFAULT_LPI_TIMER;
  81 }
  82
  83 static void sxgbe_enable_eee_mode(const struct sxgbe_priv_data *priv)
  84 {
  85         /* Check and enter in LPI mode */
  86         if (!priv->tx_path_in_lpi_mode)
  87                 priv->hw->mac->set_eee_mode(priv->ioaddr);
  88 }
  89
  90 void sxgbe_disable_eee_mode(struct sxgbe_priv_data * const priv)
  91 {
  92         /* Exit and disable EEE in case of we are are in LPI state. */
  93         priv->hw->mac->reset_eee_mode(priv->ioaddr);
  94         del_timer_sync(&priv->eee_ctrl_timer);
  95         priv->tx_path_in_lpi_mode = false;
  96 }
  97
  98 /**
  99  * sxgbe_eee_ctrl_timer
 100  * @arg : data hook
 101  * Description:
 102  *  If there is no data transfer and if we are not in LPI state,
 103  *  then MAC Transmitter can be moved to LPI state.
 104  */
 105 static void sxgbe_eee_ctrl_timer(struct timer_list *t)
 106 {
 107         struct sxgbe_priv_data *priv = from_timer(priv, t, eee_ctrl_timer);
 108
 109         sxgbe_enable_eee_mode(priv);
 110         mod_timer(&priv->eee_ctrl_timer, SXGBE_LPI_TIMER(eee_timer));
 111 }
 112
 113 /**
 114  * sxgbe_eee_init
 115  * @priv: private device pointer
 116  * Description:
 117  *  If the EEE support has been enabled while configuring the driver,
 118  *  if the GMAC actually supports the EEE (from the HW cap reg) and the
 119  *  phy can also manage EEE, so enable the LPI state and start the timer
 120  *  to verify if the tx path can enter in LPI state.
 121  */
 122 bool sxgbe_eee_init(struct sxgbe_priv_data * const priv)
 123 {
 124         struct net_device *ndev = priv->dev;
 125         bool ret = false;
 126
 127         /* MAC core supports the EEE feature. */
 128         if (priv->hw_cap.eee) {
 129                 /* Check if the PHY supports EEE */
 130                 if (phy_init_eee(ndev->phydev, 1))
 131                         return false;
 132
 133                 priv->eee_active = 1;
 134                 timer_setup(&priv->eee_ctrl_timer, sxgbe_eee_ctrl_timer, 0);
 135                 priv->eee_ctrl_timer.expires = SXGBE_LPI_TIMER(eee_timer);
 136                 add_timer(&priv->eee_ctrl_timer);
 137
 138                 priv->hw->mac->set_eee_timer(priv->ioaddr,
 139                                              SXGBE_DEFAULT_LPI_TIMER,
 140                                              priv->tx_lpi_timer);
 141
 142                 pr_info("Energy-Efficient Ethernet initialized\n");
 143
 144                 ret = true;
 145         }
 146
 147         return ret;
 148 }
 149
 150 static void sxgbe_eee_adjust(const struct sxgbe_priv_data *priv)
 151 {
 152         struct net_device *ndev = priv->dev;
 153
 154         /* When the EEE has been already initialised we have to
 155          * modify the PLS bit in the LPI ctrl & status reg according
 156          * to the PHY link status. For this reason.
 157          */
 158         if (priv->eee_enabled)
 159                 priv->hw->mac->set_eee_pls(priv->ioaddr, ndev->phydev->link);
 160 }
 161
 162 /**
 163  * sxgbe_clk_csr_set - dynamically set the MDC clock
 164  * @priv: driver private structure
 165  * Description: this is to dynamically set the MDC clock according to the csr
 166  * clock input.
 167  */
 168 static void sxgbe_clk_csr_set(struct sxgbe_priv_data *priv)
 169 {
 170         u32 clk_rate = clk_get_rate(priv->sxgbe_clk);
 171
 172         /* assign the proper divider, this will be used during
 173          * mdio communication
 174          */
 175         if (clk_rate < SXGBE_CSR_F_150M)
 176                 priv->clk_csr = SXGBE_CSR_100_150M;
 177         else if (clk_rate <= SXGBE_CSR_F_250M)
 178                 priv->clk_csr = SXGBE_CSR_150_250M;
 179         else if (clk_rate <= SXGBE_CSR_F_300M)
 180                 priv->clk_csr = SXGBE_CSR_250_300M;
 181         else if (clk_rate <= SXGBE_CSR_F_350M)
 182                 priv->clk_csr = SXGBE_CSR_300_350M;
 183         else if (clk_rate <= SXGBE_CSR_F_400M)
 184                 priv->clk_csr = SXGBE_CSR_350_400M;
 185         else if (clk_rate <= SXGBE_CSR_F_500M)
 186                 priv->clk_csr = SXGBE_CSR_400_500M;
 187 }
 188
 189 /* minimum number of free TX descriptors required to wake up TX process */
 190 #define SXGBE_TX_THRESH(x)      (x->dma_tx_size/4)
 191
 192 static inline u32 sxgbe_tx_avail(struct sxgbe_tx_queue *queue, int tx_qsize)
 193 {
 194         return queue->dirty_tx + tx_qsize - queue->cur_tx - 1;
 195 }
 196
 197 /**
 198  * sxgbe_adjust_link
 199  * @dev: net device structure
 200  * Description: it adjusts the link parameters.
 201  */
 202 static void sxgbe_adjust_link(struct net_device *dev)
 203 {
 204         struct sxgbe_priv_data *priv = netdev_priv(dev);
 205         struct phy_device *phydev = dev->phydev;
 206         u8 new_state = 0;
 207         u8 speed = 0xff;
 208
 209         if (!phydev)
 210                 return;
 211
 212         /* SXGBE is not supporting auto-negotiation and
 213          * half duplex mode. so, not handling duplex change
 214          * in this function. only handling speed and link status
 215          */
 216         if (phydev->link) {
 217                 if (phydev->speed != priv->speed) {
 218                         new_state = 1;
 219                         switch (phydev->speed) {
 220                         case SPEED_10000:
 221                                 speed = SXGBE_SPEED_10G;
 222                                 break;
 223                         case SPEED_2500:
 224                                 speed = SXGBE_SPEED_2_5G;
 225                                 break;
 226                         case SPEED_1000:
 227                                 speed = SXGBE_SPEED_1G;
 228                                 break;
 229                         default:
 230                                 netif_err(priv, link, dev,
 231                                           "Speed (%d) not supported\n",
 232                                           phydev->speed);
 233                         }
 234
 235                         priv->speed = phydev->speed;
 236                         priv->hw->mac->set_speed(priv->ioaddr, speed);
 237                 }
 238
 239                 if (!priv->oldlink) {
 240                         new_state = 1;
 241                         priv->oldlink = 1;
 242                 }
 243         } else if (priv->oldlink) {
 244                 new_state = 1;
 245                 priv->oldlink = 0;
 246                 priv->speed = SPEED_UNKNOWN;
 247         }
 248
 249         if (new_state & netif_msg_link(priv))
 250                 phy_print_status(phydev);
 251
 252         /* Alter the MAC settings for EEE */
 253         sxgbe_eee_adjust(priv);
 254 }
 255
 256 /**
 257  * sxgbe_init_phy - PHY initialization
 258  * @dev: net device structure
 259  * Description: it initializes the driver's PHY state, and attaches the PHY
 260  * to the mac driver.
 261  *  Return value:
 262  *  0 on success
 263  */
 264 static int sxgbe_init_phy(struct net_device *ndev)
 265 {
 266         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
 267         char bus_id[MII_BUS_ID_SIZE];
 268         struct phy_device *phydev;
 269         struct sxgbe_priv_data *priv = netdev_priv(ndev);
 270         int phy_iface = priv->plat->interface;
 271
 272         /* assign default link status */
 273         priv->oldlink = 0;
 274         priv->speed = SPEED_UNKNOWN;
 275         priv->oldduplex = DUPLEX_UNKNOWN;
 276
 277         if (priv->plat->phy_bus_name)
 278                 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
 279                          priv->plat->phy_bus_name, priv->plat->bus_id);
 280         else
 281                 snprintf(bus_id, MII_BUS_ID_SIZE, "sxgbe-%x",
 282                          priv->plat->bus_id);
 283
 284         snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
 285                  priv->plat->phy_addr);
 286         netdev_dbg(ndev, "%s: trying to attach to %s\n", __func__, phy_id_fmt);
 287
 288         phydev = phy_connect(ndev, phy_id_fmt, &sxgbe_adjust_link, phy_iface);
 289
 290         if (IS_ERR(phydev)) {
 291                 netdev_err(ndev, "Could not attach to PHY\n");
 292                 return PTR_ERR(phydev);
 293         }
 294
 295         /* Stop Advertising 1000BASE Capability if interface is not GMII */
 296         if ((phy_iface == PHY_INTERFACE_MODE_MII) ||
 297             (phy_iface == PHY_INTERFACE_MODE_RMII))
 298                 phy_set_max_speed(phydev, SPEED_1000);
 299
 300         if (phydev->phy_id == 0) {
 301                 phy_disconnect(phydev);
 302                 return -ENODEV;
 303         }
 304
 305         netdev_dbg(ndev, "%s: attached to PHY (UID 0x%x) Link = %d\n",
 306                    __func__, phydev->phy_id, phydev->link);
 307
 308         return 0;
 309 }
 310
 311 /**
 312  * sxgbe_clear_descriptors: clear descriptors
 313  * @priv: driver private structure
 314  * Description: this function is called to clear the tx and rx descriptors
 315  * in case of both basic and extended descriptors are used.
 316  */
 317 static void sxgbe_clear_descriptors(struct sxgbe_priv_data *priv)
 318 {
 319         int i, j;
 320         unsigned int txsize = priv->dma_tx_size;
 321         unsigned int rxsize = priv->dma_rx_size;
 322
 323         /* Clear the Rx/Tx descriptors */
 324         for (j = 0; j < SXGBE_RX_QUEUES; j++) {
 325                 for (i = 0; i < rxsize; i++)
 326                         priv->hw->desc->init_rx_desc(&priv->rxq[j]->dma_rx[i],
 327                                                      priv->use_riwt, priv->mode,
 328                                                      (i == rxsize - 1));
 329         }
 330
 331         for (j = 0; j < SXGBE_TX_QUEUES; j++) {
 332                 for (i = 0; i < txsize; i++)
 333                         priv->hw->desc->init_tx_desc(&priv->txq[j]->dma_tx[i]);
 334         }
 335 }
 336
 337 static int sxgbe_init_rx_buffers(struct net_device *dev,
 338                                  struct sxgbe_rx_norm_desc *p, int i,
 339                                  unsigned int dma_buf_sz,
 340                                  struct sxgbe_rx_queue *rx_ring)
 341 {
 342         struct sxgbe_priv_data *priv = netdev_priv(dev);
 343         struct sk_buff *skb;
 344
 345         skb = __netdev_alloc_skb_ip_align(dev, dma_buf_sz, GFP_KERNEL);
 346         if (!skb)
 347                 return -ENOMEM;
 348
 349         rx_ring->rx_skbuff[i] = skb;
 350         rx_ring->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
 351                                                    dma_buf_sz, DMA_FROM_DEVICE);
 352
 353         if (dma_mapping_error(priv->device, rx_ring->rx_skbuff_dma[i])) {
 354                 netdev_err(dev, "%s: DMA mapping error\n", __func__);
 355                 dev_kfree_skb_any(skb);
 356                 return -EINVAL;
 357         }
 358
 359         p->rdes23.rx_rd_des23.buf2_addr = rx_ring->rx_skbuff_dma[i];
 360
 361         return 0;
 362 }
 363
 364 /**
 365  * sxgbe_free_rx_buffers - free what sxgbe_init_rx_buffers() allocated
 366  * @dev: net device structure
 367  * @rx_ring: ring to be freed
 368  * @rx_rsize: ring size
 369  * Description:  this function initializes the DMA RX descriptor
 370  */
 371 static void sxgbe_free_rx_buffers(struct net_device *dev,
 372                                   struct sxgbe_rx_norm_desc *p, int i,
 373                                   unsigned int dma_buf_sz,
 374                                   struct sxgbe_rx_queue *rx_ring)
 375 {
 376         struct sxgbe_priv_data *priv = netdev_priv(dev);
 377
 378         kfree_skb(rx_ring->rx_skbuff[i]);
 379         dma_unmap_single(priv->device, rx_ring->rx_skbuff_dma[i],
 380                          dma_buf_sz, DMA_FROM_DEVICE);
 381 }
 382
 383 /**
 384  * init_tx_ring - init the TX descriptor ring
 385  * @dev: net device structure
 386  * @tx_ring: ring to be initialised
 387  * @tx_rsize: ring size
 388  * Description:  this function initializes the DMA TX descriptor
 389  */
 390 static int init_tx_ring(struct device *dev, u8 queue_no,
 391                         struct sxgbe_tx_queue *tx_ring, int tx_rsize)
 392 {
 393         /* TX ring is not allcoated */
 394         if (!tx_ring) {
 395                 dev_err(dev, "No memory for TX queue of SXGBE\n");
 396                 return -ENOMEM;
 397         }
 398
 399         /* allocate memory for TX descriptors */
 400         tx_ring->dma_tx = dma_alloc_coherent(dev,
 401                                              tx_rsize * sizeof(struct sxgbe_tx_norm_desc),
 402                                              &tx_ring->dma_tx_phy, GFP_KERNEL);
 403         if (!tx_ring->dma_tx)
 404                 return -ENOMEM;
 405
 406         /* allocate memory for TX skbuff array */
 407         tx_ring->tx_skbuff_dma = devm_kcalloc(dev, tx_rsize,
 408                                               sizeof(dma_addr_t), GFP_KERNEL);
 409         if (!tx_ring->tx_skbuff_dma)
 410                 goto dmamem_err;
 411
 412         tx_ring->tx_skbuff = devm_kcalloc(dev, tx_rsize,
 413                                           sizeof(struct sk_buff *), GFP_KERNEL);
 414
 415         if (!tx_ring->tx_skbuff)
 416                 goto dmamem_err;
 417
 418         /* assign queue number */
 419         tx_ring->queue_no = queue_no;
 420
 421         /* initialise counters */
 422         tx_ring->dirty_tx = 0;
 423         tx_ring->cur_tx = 0;
 424
 425         return 0;
 426
 427 dmamem_err:
 428         dma_free_coherent(dev, tx_rsize * sizeof(struct sxgbe_tx_norm_desc),
 429                           tx_ring->dma_tx, tx_ring->dma_tx_phy);
 430         return -ENOMEM;
 431 }
 432
 433 /**
 434  * free_rx_ring - free the RX descriptor ring
 435  * @dev: net device structure
 436  * @rx_ring: ring to be initialised
 437  * @rx_rsize: ring size
 438  * Description:  this function initializes the DMA RX descriptor
 439  */
 440 static void free_rx_ring(struct device *dev, struct sxgbe_rx_queue *rx_ring,
 441                          int rx_rsize)
 442 {
 443         dma_free_coherent(dev, rx_rsize * sizeof(struct sxgbe_rx_norm_desc),
 444                           rx_ring->dma_rx, rx_ring->dma_rx_phy);
 445         kfree(rx_ring->rx_skbuff_dma);
 446         kfree(rx_ring->rx_skbuff);
 447 }
 448
 449 /**
 450  * init_rx_ring - init the RX descriptor ring
 451  * @dev: net device structure
 452  * @rx_ring: ring to be initialised
 453  * @rx_rsize: ring size
 454  * Description:  this function initializes the DMA RX descriptor
 455  */
 456 static int init_rx_ring(struct net_device *dev, u8 queue_no,
 457                         struct sxgbe_rx_queue *rx_ring, int rx_rsize)
 458 {
 459         struct sxgbe_priv_data *priv = netdev_priv(dev);
 460         int desc_index;
 461         unsigned int bfsize = 0;
 462         unsigned int ret = 0;
 463
 464         /* Set the max buffer size according to the MTU. */
 465         bfsize = ALIGN(dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN, 8);
 466
 467         netif_dbg(priv, probe, dev, "%s: bfsize %d\n", __func__, bfsize);
 468
 469         /* RX ring is not allcoated */
 470         if (rx_ring == NULL) {
 471                 netdev_err(dev, "No memory for RX queue\n");
 472                 return -ENOMEM;
 473         }
 474
 475         /* assign queue number */
 476         rx_ring->queue_no = queue_no;
 477
 478         /* allocate memory for RX descriptors */
 479         rx_ring->dma_rx = dma_alloc_coherent(priv->device,
 480                                              rx_rsize * sizeof(struct sxgbe_rx_norm_desc),
 481                                              &rx_ring->dma_rx_phy, GFP_KERNEL);
 482
 483         if (rx_ring->dma_rx == NULL)
 484                 return -ENOMEM;
 485
 486         /* allocate memory for RX skbuff array */
 487         rx_ring->rx_skbuff_dma = kmalloc_array(rx_rsize,
 488                                                sizeof(dma_addr_t), GFP_KERNEL);
 489         if (!rx_ring->rx_skbuff_dma) {
 490                 ret = -ENOMEM;
 491                 goto err_free_dma_rx;
 492         }
 493
 494         rx_ring->rx_skbuff = kmalloc_array(rx_rsize,
 495                                            sizeof(struct sk_buff *), GFP_KERNEL);
 496         if (!rx_ring->rx_skbuff) {
 497                 ret = -ENOMEM;
 498                 goto err_free_skbuff_dma;
 499         }
 500
 501         /* initialise the buffers */
 502         for (desc_index = 0; desc_index < rx_rsize; desc_index++) {
 503                 struct sxgbe_rx_norm_desc *p;
 504                 p = rx_ring->dma_rx + desc_index;
 505                 ret = sxgbe_init_rx_buffers(dev, p, desc_index,
 506                                             bfsize, rx_ring);
 507                 if (ret)
 508                         goto err_free_rx_buffers;
 509         }
 510
 511         /* initialise counters */
 512         rx_ring->cur_rx = 0;
 513         rx_ring->dirty_rx = (unsigned int)(desc_index - rx_rsize);
 514         priv->dma_buf_sz = bfsize;
 515
 516         return 0;
 517
 518 err_free_rx_buffers:
 519         while (--desc_index >= 0) {
 520                 struct sxgbe_rx_norm_desc *p;
 521
 522                 p = rx_ring->dma_rx + desc_index;
 523                 sxgbe_free_rx_buffers(dev, p, desc_index, bfsize, rx_ring);
 524         }
 525         kfree(rx_ring->rx_skbuff);
 526 err_free_skbuff_dma:
 527         kfree(rx_ring->rx_skbuff_dma);
 528 err_free_dma_rx:
 529         dma_free_coherent(priv->device,
 530                           rx_rsize * sizeof(struct sxgbe_rx_norm_desc),
 531                           rx_ring->dma_rx, rx_ring->dma_rx_phy);
 532
 533         return ret;
 534 }
 535 /**
 536  * free_tx_ring - free the TX descriptor ring
 537  * @dev: net device structure
 538  * @tx_ring: ring to be initialised
 539  * @tx_rsize: ring size
 540  * Description:  this function initializes the DMA TX descriptor
 541  */
 542 static void free_tx_ring(struct device *dev, struct sxgbe_tx_queue *tx_ring,
 543                          int tx_rsize)
 544 {
 545         dma_free_coherent(dev, tx_rsize * sizeof(struct sxgbe_tx_norm_desc),
 546                           tx_ring->dma_tx, tx_ring->dma_tx_phy);
 547 }
 548
 549 /**
 550  * init_dma_desc_rings - init the RX/TX descriptor rings
 551  * @dev: net device structure
 552  * Description:  this function initializes the DMA RX/TX descriptors
 553  * and allocates the socket buffers. It suppors the chained and ring
 554  * modes.
 555  */
 556 static int init_dma_desc_rings(struct net_device *netd)
 557 {
 558         int queue_num, ret;
 559         struct sxgbe_priv_data *priv = netdev_priv(netd);
 560         int tx_rsize = priv->dma_tx_size;
 561         int rx_rsize = priv->dma_rx_size;
 562
 563         /* Allocate memory for queue structures and TX descs */
 564         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
 565                 ret = init_tx_ring(priv->device, queue_num,
 566                                    priv->txq[queue_num], tx_rsize);
 567                 if (ret) {
 568                         dev_err(&netd->dev, "TX DMA ring allocation failed!\n");
 569                         goto txalloc_err;
 570                 }
 571
 572                 /* save private pointer in each ring this
 573                  * pointer is needed during cleaing TX queue
 574                  */
 575                 priv->txq[queue_num]->priv_ptr = priv;
 576         }
 577
 578         /* Allocate memory for queue structures and RX descs */
 579         SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
 580                 ret = init_rx_ring(netd, queue_num,
 581                                    priv->rxq[queue_num], rx_rsize);
 582                 if (ret) {
 583                         netdev_err(netd, "RX DMA ring allocation failed!!\n");
 584                         goto rxalloc_err;
 585                 }
 586
 587                 /* save private pointer in each ring this
 588                  * pointer is needed during cleaing TX queue
 589                  */
 590                 priv->rxq[queue_num]->priv_ptr = priv;
 591         }
 592
 593         sxgbe_clear_descriptors(priv);
 594
 595         return 0;
 596
 597 txalloc_err:
 598         while (queue_num--)
 599                 free_tx_ring(priv->device, priv->txq[queue_num], tx_rsize);
 600         return ret;
 601
 602 rxalloc_err:
 603         while (queue_num--)
 604                 free_rx_ring(priv->device, priv->rxq[queue_num], rx_rsize);
 605         return ret;
 606 }
 607
 608 static void tx_free_ring_skbufs(struct sxgbe_tx_queue *txqueue)
 609 {
 610         int dma_desc;
 611         struct sxgbe_priv_data *priv = txqueue->priv_ptr;
 612         int tx_rsize = priv->dma_tx_size;
 613
 614         for (dma_desc = 0; dma_desc < tx_rsize; dma_desc++) {
 615                 struct sxgbe_tx_norm_desc *tdesc = txqueue->dma_tx + dma_desc;
 616
 617                 if (txqueue->tx_skbuff_dma[dma_desc])
 618                         dma_unmap_single(priv->device,
 619                                          txqueue->tx_skbuff_dma[dma_desc],
 620                                          priv->hw->desc->get_tx_len(tdesc),
 621                                          DMA_TO_DEVICE);
 622
 623                 dev_kfree_skb_any(txqueue->tx_skbuff[dma_desc]);
 624                 txqueue->tx_skbuff[dma_desc] = NULL;
 625                 txqueue->tx_skbuff_dma[dma_desc] = 0;
 626         }
 627 }
 628
 629
 630 static void dma_free_tx_skbufs(struct sxgbe_priv_data *priv)
 631 {
 632         int queue_num;
 633
 634         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
 635                 struct sxgbe_tx_queue *tqueue = priv->txq[queue_num];
 636                 tx_free_ring_skbufs(tqueue);
 637         }
 638 }
 639
 640 static void free_dma_desc_resources(struct sxgbe_priv_data *priv)
 641 {
 642         int queue_num;
 643         int tx_rsize = priv->dma_tx_size;
 644         int rx_rsize = priv->dma_rx_size;
 645
 646         /* Release the DMA TX buffers */
 647         dma_free_tx_skbufs(priv);
 648
 649         /* Release the TX ring memory also */
 650         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
 651                 free_tx_ring(priv->device, priv->txq[queue_num], tx_rsize);
 652         }
 653
 654         /* Release the RX ring memory also */
 655         SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
 656                 free_rx_ring(priv->device, priv->rxq[queue_num], rx_rsize);
 657         }
 658 }
 659
 660 static int txring_mem_alloc(struct sxgbe_priv_data *priv)
 661 {
 662         int queue_num;
 663
 664         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
 665                 priv->txq[queue_num] = devm_kmalloc(priv->device,
 666                                                     sizeof(struct sxgbe_tx_queue), GFP_KERNEL);
 667                 if (!priv->txq[queue_num])
 668                         return -ENOMEM;
 669         }
 670
 671         return 0;
 672 }
 673
 674 static int rxring_mem_alloc(struct sxgbe_priv_data *priv)
 675 {
 676         int queue_num;
 677
 678         SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
 679                 priv->rxq[queue_num] = devm_kmalloc(priv->device,
 680                                                     sizeof(struct sxgbe_rx_queue), GFP_KERNEL);
 681                 if (!priv->rxq[queue_num])
 682                         return -ENOMEM;
 683         }
 684
 685         return 0;
 686 }
 687
 688 /**
 689  *  sxgbe_mtl_operation_mode - HW MTL operation mode
 690  *  @priv: driver private structure
 691  *  Description: it sets the MTL operation mode: tx/rx MTL thresholds
 692  *  or Store-And-Forward capability.
 693  */
 694 static void sxgbe_mtl_operation_mode(struct sxgbe_priv_data *priv)
 695 {
 696         int queue_num;
 697
 698         /* TX/RX threshold control */
 699         if (likely(priv->plat->force_sf_dma_mode)) {
 700                 /* set TC mode for TX QUEUES */
 701                 SXGBE_FOR_EACH_QUEUE(priv->hw_cap.tx_mtl_queues, queue_num)
 702                         priv->hw->mtl->set_tx_mtl_mode(priv->ioaddr, queue_num,
 703                                                        SXGBE_MTL_SFMODE);
 704                 priv->tx_tc = SXGBE_MTL_SFMODE;
 705
 706                 /* set TC mode for RX QUEUES */
 707                 SXGBE_FOR_EACH_QUEUE(priv->hw_cap.rx_mtl_queues, queue_num)
 708                         priv->hw->mtl->set_rx_mtl_mode(priv->ioaddr, queue_num,
 709                                                        SXGBE_MTL_SFMODE);
 710                 priv->rx_tc = SXGBE_MTL_SFMODE;
 711         } else if (unlikely(priv->plat->force_thresh_dma_mode)) {
 712                 /* set TC mode for TX QUEUES */
 713                 SXGBE_FOR_EACH_QUEUE(priv->hw_cap.tx_mtl_queues, queue_num)
 714                         priv->hw->mtl->set_tx_mtl_mode(priv->ioaddr, queue_num,
 715                                                        priv->tx_tc);
 716                 /* set TC mode for RX QUEUES */
 717                 SXGBE_FOR_EACH_QUEUE(priv->hw_cap.rx_mtl_queues, queue_num)
 718                         priv->hw->mtl->set_rx_mtl_mode(priv->ioaddr, queue_num,
 719                                                        priv->rx_tc);
 720         } else {
 721                 pr_err("ERROR: %s: Invalid TX threshold mode\n", __func__);
 722         }
 723 }
 724
 725 /**
 726  * sxgbe_tx_queue_clean:
 727  * @priv: driver private structure
 728  * Description: it reclaims resources after transmission completes.
 729  */
 730 static void sxgbe_tx_queue_clean(struct sxgbe_tx_queue *tqueue)
 731 {
 732         struct sxgbe_priv_data *priv = tqueue->priv_ptr;
 733         unsigned int tx_rsize = priv->dma_tx_size;
 734         struct netdev_queue *dev_txq;
 735         u8 queue_no = tqueue->queue_no;
 736
 737         dev_txq = netdev_get_tx_queue(priv->dev, queue_no);
 738
 739         __netif_tx_lock(dev_txq, smp_processor_id());
 740
 741         priv->xstats.tx_clean++;
 742         while (tqueue->dirty_tx != tqueue->cur_tx) {
 743                 unsigned int entry = tqueue->dirty_tx % tx_rsize;
 744                 struct sk_buff *skb = tqueue->tx_skbuff[entry];
 745                 struct sxgbe_tx_norm_desc *p;
 746
 747                 p = tqueue->dma_tx + entry;
 748
 749                 /* Check if the descriptor is owned by the DMA. */
 750                 if (priv->hw->desc->get_tx_owner(p))
 751                         break;
 752
 753                 if (netif_msg_tx_done(priv))
 754                         pr_debug("%s: curr %d, dirty %d\n",
 755                                  __func__, tqueue->cur_tx, tqueue->dirty_tx);
 756
 757                 if (likely(tqueue->tx_skbuff_dma[entry])) {
 758                         dma_unmap_single(priv->device,
 759                                          tqueue->tx_skbuff_dma[entry],
 760                                          priv->hw->desc->get_tx_len(p),
 761                                          DMA_TO_DEVICE);
 762                         tqueue->tx_skbuff_dma[entry] = 0;
 763                 }
 764
 765                 if (likely(skb)) {
 766                         dev_kfree_skb(skb);
 767                         tqueue->tx_skbuff[entry] = NULL;
 768                 }
 769
 770                 priv->hw->desc->release_tx_desc(p);
 771
 772                 tqueue->dirty_tx++;
 773         }
 774
 775         /* wake up queue */
 776         if (unlikely(netif_tx_queue_stopped(dev_txq) &&
 777             sxgbe_tx_avail(tqueue, tx_rsize) > SXGBE_TX_THRESH(priv))) {
 778                 if (netif_msg_tx_done(priv))
 779                         pr_debug("%s: restart transmit\n", __func__);
 780                 netif_tx_wake_queue(dev_txq);
 781         }
 782
 783         __netif_tx_unlock(dev_txq);
 784 }
 785
 786 /**
 787  * sxgbe_tx_clean:
 788  * @priv: driver private structure
 789  * Description: it reclaims resources after transmission completes.
 790  */
 791 static void sxgbe_tx_all_clean(struct sxgbe_priv_data * const priv)
 792 {
 793         u8 queue_num;
 794
 795         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
 796                 struct sxgbe_tx_queue *tqueue = priv->txq[queue_num];
 797
 798                 sxgbe_tx_queue_clean(tqueue);
 799         }
 800
 801         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
 802                 sxgbe_enable_eee_mode(priv);
 803                 mod_timer(&priv->eee_ctrl_timer, SXGBE_LPI_TIMER(eee_timer));
 804         }
 805 }
 806
 807 /**
 808  * sxgbe_restart_tx_queue: irq tx error mng function
 809  * @priv: driver private structure
 810  * Description: it cleans the descriptors and restarts the transmission
 811  * in case of errors.
 812  */
 813 static void sxgbe_restart_tx_queue(struct sxgbe_priv_data *priv, int queue_num)
 814 {
 815         struct sxgbe_tx_queue *tx_ring = priv->txq[queue_num];
 816         struct netdev_queue *dev_txq = netdev_get_tx_queue(priv->dev,
 817                                                            queue_num);
 818
 819         /* stop the queue */
 820         netif_tx_stop_queue(dev_txq);
 821
 822         /* stop the tx dma */
 823         priv->hw->dma->stop_tx_queue(priv->ioaddr, queue_num);
 824
 825         /* free the skbuffs of the ring */
 826         tx_free_ring_skbufs(tx_ring);
 827
 828         /* initialise counters */
 829         tx_ring->cur_tx = 0;
 830         tx_ring->dirty_tx = 0;
 831
 832         /* start the tx dma */
 833         priv->hw->dma->start_tx_queue(priv->ioaddr, queue_num);
 834
 835         priv->dev->stats.tx_errors++;
 836
 837         /* wakeup the queue */
 838         netif_tx_wake_queue(dev_txq);
 839 }
 840
 841 /**
 842  * sxgbe_reset_all_tx_queues: irq tx error mng function
 843  * @priv: driver private structure
 844  * Description: it cleans all the descriptors and
 845  * restarts the transmission on all queues in case of errors.
 846  */
 847 static void sxgbe_reset_all_tx_queues(struct sxgbe_priv_data *priv)
 848 {
 849         int queue_num;
 850
 851         /* On TX timeout of net device, resetting of all queues
 852          * may not be proper way, revisit this later if needed
 853          */
 854         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num)
 855                 sxgbe_restart_tx_queue(priv, queue_num);
 856 }
 857
 858 /**
 859  * sxgbe_get_hw_features: get XMAC capabilities from the HW cap. register.
 860  * @priv: driver private structure
 861  * Description:
 862  *  new GMAC chip generations have a new register to indicate the
 863  *  presence of the optional feature/functions.
 864  *  This can be also used to override the value passed through the
 865  *  platform and necessary for old MAC10/100 and GMAC chips.
 866  */
 867 static int sxgbe_get_hw_features(struct sxgbe_priv_data * const priv)
 868 {
 869         int rval = 0;
 870         struct sxgbe_hw_features *features = &priv->hw_cap;
 871
 872         /* Read First Capability Register CAP[0] */
 873         rval = priv->hw->mac->get_hw_feature(priv->ioaddr, 0);
 874         if (rval) {
 875                 features->pmt_remote_wake_up =
 876                         SXGBE_HW_FEAT_PMT_TEMOTE_WOP(rval);
 877                 features->pmt_magic_frame = SXGBE_HW_FEAT_PMT_MAGIC_PKT(rval);
 878                 features->atime_stamp = SXGBE_HW_FEAT_IEEE1500_2008(rval);
 879                 features->tx_csum_offload =
 880                         SXGBE_HW_FEAT_TX_CSUM_OFFLOAD(rval);
 881                 features->rx_csum_offload =
 882                         SXGBE_HW_FEAT_RX_CSUM_OFFLOAD(rval);
 883                 features->multi_macaddr = SXGBE_HW_FEAT_MACADDR_COUNT(rval);
 884                 features->tstamp_srcselect = SXGBE_HW_FEAT_TSTMAP_SRC(rval);
 885                 features->sa_vlan_insert = SXGBE_HW_FEAT_SRCADDR_VLAN(rval);
 886                 features->eee = SXGBE_HW_FEAT_EEE(rval);
 887         }
 888
 889         /* Read First Capability Register CAP[1] */
 890         rval = priv->hw->mac->get_hw_feature(priv->ioaddr, 1);
 891         if (rval) {
 892                 features->rxfifo_size = SXGBE_HW_FEAT_RX_FIFO_SIZE(rval);
 893                 features->txfifo_size = SXGBE_HW_FEAT_TX_FIFO_SIZE(rval);
 894                 features->atstmap_hword = SXGBE_HW_FEAT_TX_FIFO_SIZE(rval);
 895                 features->dcb_enable = SXGBE_HW_FEAT_DCB(rval);
 896                 features->splithead_enable = SXGBE_HW_FEAT_SPLIT_HDR(rval);
 897                 features->tcpseg_offload = SXGBE_HW_FEAT_TSO(rval);
 898                 features->debug_mem = SXGBE_HW_FEAT_DEBUG_MEM_IFACE(rval);
 899                 features->rss_enable = SXGBE_HW_FEAT_RSS(rval);
 900                 features->hash_tsize = SXGBE_HW_FEAT_HASH_TABLE_SIZE(rval);
 901                 features->l3l4_filer_size = SXGBE_HW_FEAT_L3L4_FILTER_NUM(rval);
 902         }
 903
 904         /* Read First Capability Register CAP[2] */
 905         rval = priv->hw->mac->get_hw_feature(priv->ioaddr, 2);
 906         if (rval) {
 907                 features->rx_mtl_queues = SXGBE_HW_FEAT_RX_MTL_QUEUES(rval);
 908                 features->tx_mtl_queues = SXGBE_HW_FEAT_TX_MTL_QUEUES(rval);
 909                 features->rx_dma_channels = SXGBE_HW_FEAT_RX_DMA_CHANNELS(rval);
 910                 features->tx_dma_channels = SXGBE_HW_FEAT_TX_DMA_CHANNELS(rval);
 911                 features->pps_output_count = SXGBE_HW_FEAT_PPS_OUTPUTS(rval);
 912                 features->aux_input_count = SXGBE_HW_FEAT_AUX_SNAPSHOTS(rval);
 913         }
 914
 915         return rval;
 916 }
 917
 918 /**
 919  * sxgbe_check_ether_addr: check if the MAC addr is valid
 920  * @priv: driver private structure
 921  * Description:
 922  * it is to verify if the MAC address is valid, in case of failures it
 923  * generates a random MAC address
 924  */
 925 static void sxgbe_check_ether_addr(struct sxgbe_priv_data *priv)
 926 {
 927         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
 928                 priv->hw->mac->get_umac_addr((void __iomem *)
 929                                              priv->ioaddr,
 930                                              priv->dev->dev_addr, 0);
 931                 if (!is_valid_ether_addr(priv->dev->dev_addr))
 932                         eth_hw_addr_random(priv->dev);
 933         }
 934         dev_info(priv->device, "device MAC address %pM\n",
 935                  priv->dev->dev_addr);
 936 }
 937
 938 /**
 939  * sxgbe_init_dma_engine: DMA init.
 940  * @priv: driver private structure
 941  * Description:
 942  * It inits the DMA invoking the specific SXGBE callback.
 943  * Some DMA parameters can be passed from the platform;
 944  * in case of these are not passed a default is kept for the MAC or GMAC.
 945  */
 946 static int sxgbe_init_dma_engine(struct sxgbe_priv_data *priv)
 947 {
 948         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_map = 0;
 949         int queue_num;
 950
 951         if (priv->plat->dma_cfg) {
 952                 pbl = priv->plat->dma_cfg->pbl;
 953                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
 954                 burst_map = priv->plat->dma_cfg->burst_map;
 955         }
 956
 957         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num)
 958                 priv->hw->dma->cha_init(priv->ioaddr, queue_num,
 959                                         fixed_burst, pbl,
 960                                         (priv->txq[queue_num])->dma_tx_phy,
 961                                         (priv->rxq[queue_num])->dma_rx_phy,
 962                                         priv->dma_tx_size, priv->dma_rx_size);
 963
 964         return priv->hw->dma->init(priv->ioaddr, fixed_burst, burst_map);
 965 }
 966
 967 /**
 968  * sxgbe_init_mtl_engine: MTL init.
 969  * @priv: driver private structure
 970  * Description:
 971  * It inits the MTL invoking the specific SXGBE callback.
 972  */
 973 static void sxgbe_init_mtl_engine(struct sxgbe_priv_data *priv)
 974 {
 975         int queue_num;
 976
 977         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
 978                 priv->hw->mtl->mtl_set_txfifosize(priv->ioaddr, queue_num,
 979                                                   priv->hw_cap.tx_mtl_qsize);
 980                 priv->hw->mtl->mtl_enable_txqueue(priv->ioaddr, queue_num);
 981         }
 982 }
 983
 984 /**
 985  * sxgbe_disable_mtl_engine: MTL disable.
 986  * @priv: driver private structure
 987  * Description:
 988  * It disables the MTL queues by invoking the specific SXGBE callback.
 989  */
 990 static void sxgbe_disable_mtl_engine(struct sxgbe_priv_data *priv)
 991 {
 992         int queue_num;
 993
 994         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num)
 995                 priv->hw->mtl->mtl_disable_txqueue(priv->ioaddr, queue_num);
 996 }
 997
 998
 999 /**
1000  * sxgbe_tx_timer: mitigation sw timer for tx.
1001  * @t: timer pointer
1002  * Description:
1003  * This is the timer handler to directly invoke the sxgbe_tx_clean.
1004  */
1005 static void sxgbe_tx_timer(struct timer_list *t)
1006 {
1007         struct sxgbe_tx_queue *p = from_timer(p, t, txtimer);
1008         sxgbe_tx_queue_clean(p);
1009 }
1010
1011 /**
1012  * sxgbe_init_tx_coalesce: init tx mitigation options.
1013  * @priv: driver private structure
1014  * Description:
1015  * This inits the transmit coalesce parameters: i.e. timer rate,
1016  * timer handler and default threshold used for enabling the
1017  * interrupt on completion bit.
1018  */
1019 static void sxgbe_tx_init_coalesce(struct sxgbe_priv_data *priv)
1020 {
1021         u8 queue_num;
1022
1023         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
1024                 struct sxgbe_tx_queue *p = priv->txq[queue_num];
1025                 p->tx_coal_frames =  SXGBE_TX_FRAMES;
1026                 p->tx_coal_timer = SXGBE_COAL_TX_TIMER;
1027                 timer_setup(&p->txtimer, sxgbe_tx_timer, 0);
1028                 p->txtimer.expires = SXGBE_COAL_TIMER(p->tx_coal_timer);
1029                 add_timer(&p->txtimer);
1030         }
1031 }
1032
1033 static void sxgbe_tx_del_timer(struct sxgbe_priv_data *priv)
1034 {
1035         u8 queue_num;
1036
1037         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
1038                 struct sxgbe_tx_queue *p = priv->txq[queue_num];
1039                 del_timer_sync(&p->txtimer);
1040         }
1041 }
1042
1043 /**
1044  *  sxgbe_open - open entry point of the driver
1045  *  @dev : pointer to the device structure.
1046  *  Description:
1047  *  This function is the open entry point of the driver.
1048  *  Return value:
1049  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1050  *  file on failure.
1051  */
1052 static int sxgbe_open(struct net_device *dev)
1053 {
1054         struct sxgbe_priv_data *priv = netdev_priv(dev);
1055         int ret, queue_num;
1056
1057         clk_prepare_enable(priv->sxgbe_clk);
1058
1059         sxgbe_check_ether_addr(priv);
1060
1061         /* Init the phy */
1062         ret = sxgbe_init_phy(dev);
1063         if (ret) {
1064                 netdev_err(dev, "%s: Cannot attach to PHY (error: %d)\n",
1065                            __func__, ret);
1066                 goto phy_error;
1067         }
1068
1069         /* Create and initialize the TX/RX descriptors chains. */
1070         priv->dma_tx_size = SXGBE_ALIGN(DMA_TX_SIZE);
1071         priv->dma_rx_size = SXGBE_ALIGN(DMA_RX_SIZE);
1072         priv->dma_buf_sz = SXGBE_ALIGN(DMA_BUFFER_SIZE);
1073         priv->tx_tc = TC_DEFAULT;
1074         priv->rx_tc = TC_DEFAULT;
1075         init_dma_desc_rings(dev);
1076
1077         /* DMA initialization and SW reset */
1078         ret = sxgbe_init_dma_engine(priv);
1079         if (ret < 0) {
1080                 netdev_err(dev, "%s: DMA initialization failed\n", __func__);
1081                 goto init_error;
1082         }
1083
1084         /*  MTL initialization */
1085         sxgbe_init_mtl_engine(priv);
1086
1087         /* Copy the MAC addr into the HW  */
1088         priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
1089
1090         /* Initialize the MAC Core */
1091         priv->hw->mac->core_init(priv->ioaddr);
1092         SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
1093                 priv->hw->mac->enable_rxqueue(priv->ioaddr, queue_num);
1094         }
1095
1096         /* Request the IRQ lines */
1097         ret = devm_request_irq(priv->device, priv->irq, sxgbe_common_interrupt,
1098                                IRQF_SHARED, dev->name, dev);
1099         if (unlikely(ret < 0)) {
1100                 netdev_err(dev, "%s: ERROR: allocating the IRQ %d (error: %d)\n",
1101                            __func__, priv->irq, ret);
1102                 goto init_error;
1103         }
1104
1105         /* If the LPI irq is different from the mac irq
1106          * register a dedicated handler
1107          */
1108         if (priv->lpi_irq != dev->irq) {
1109                 ret = devm_request_irq(priv->device, priv->lpi_irq,
1110                                        sxgbe_common_interrupt,
1111                                        IRQF_SHARED, dev->name, dev);
1112                 if (unlikely(ret < 0)) {
1113                         netdev_err(dev, "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1114                                    __func__, priv->lpi_irq, ret);
1115                         goto init_error;
1116                 }
1117         }
1118
1119         /* Request TX DMA irq lines */
1120         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
1121                 ret = devm_request_irq(priv->device,
1122                                        (priv->txq[queue_num])->irq_no,
1123                                        sxgbe_tx_interrupt, 0,
1124                                        dev->name, priv->txq[queue_num]);
1125                 if (unlikely(ret < 0)) {
1126                         netdev_err(dev, "%s: ERROR: allocating TX IRQ %d (error: %d)\n",
1127                                    __func__, priv->irq, ret);
1128                         goto init_error;
1129                 }
1130         }
1131
1132         /* Request RX DMA irq lines */
1133         SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
1134                 ret = devm_request_irq(priv->device,
1135                                        (priv->rxq[queue_num])->irq_no,
1136                                        sxgbe_rx_interrupt, 0,
1137                                        dev->name, priv->rxq[queue_num]);
1138                 if (unlikely(ret < 0)) {
1139                         netdev_err(dev, "%s: ERROR: allocating TX IRQ %d (error: %d)\n",
1140                                    __func__, priv->irq, ret);
1141                         goto init_error;
1142                 }
1143         }
1144
1145         /* Enable the MAC Rx/Tx */
1146         priv->hw->mac->enable_tx(priv->ioaddr, true);
1147         priv->hw->mac->enable_rx(priv->ioaddr, true);
1148
1149         /* Set the HW DMA mode and the COE */
1150         sxgbe_mtl_operation_mode(priv);
1151
1152         /* Extra statistics */
1153         memset(&priv->xstats, 0, sizeof(struct sxgbe_extra_stats));
1154
1155         priv->xstats.tx_threshold = priv->tx_tc;
1156         priv->xstats.rx_threshold = priv->rx_tc;
1157
1158         /* Start the ball rolling... */
1159         netdev_dbg(dev, "DMA RX/TX processes started...\n");
1160         priv->hw->dma->start_tx(priv->ioaddr, SXGBE_TX_QUEUES);
1161         priv->hw->dma->start_rx(priv->ioaddr, SXGBE_RX_QUEUES);
1162
1163         if (dev->phydev)
1164                 phy_start(dev->phydev);
1165
1166         /* initialise TX coalesce parameters */
1167         sxgbe_tx_init_coalesce(priv);
1168
1169         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1170                 priv->rx_riwt = SXGBE_MAX_DMA_RIWT;
1171                 priv->hw->dma->rx_watchdog(priv->ioaddr, SXGBE_MAX_DMA_RIWT);
1172         }
1173
1174         priv->tx_lpi_timer = SXGBE_DEFAULT_LPI_TIMER;
1175         priv->eee_enabled = sxgbe_eee_init(priv);
1176
1177         napi_enable(&priv->napi);
1178         netif_start_queue(dev);
1179
1180         return 0;
1181
1182 init_error:
1183         free_dma_desc_resources(priv);
1184         if (dev->phydev)
1185                 phy_disconnect(dev->phydev);
1186 phy_error:
1187         clk_disable_unprepare(priv->sxgbe_clk);
1188
1189         return ret;
1190 }
1191
1192 /**
1193  *  sxgbe_release - close entry point of the driver
1194  *  @dev : device pointer.
1195  *  Description:
1196  *  This is the stop entry point of the driver.
1197  */
1198 static int sxgbe_release(struct net_device *dev)
1199 {
1200         struct sxgbe_priv_data *priv = netdev_priv(dev);
1201
1202         if (priv->eee_enabled)
1203                 del_timer_sync(&priv->eee_ctrl_timer);
1204
1205         /* Stop and disconnect the PHY */
1206         if (dev->phydev) {
1207                 phy_stop(dev->phydev);
1208                 phy_disconnect(dev->phydev);
1209         }
1210
1211         netif_tx_stop_all_queues(dev);
1212
1213         napi_disable(&priv->napi);
1214
1215         /* delete TX timers */
1216         sxgbe_tx_del_timer(priv);
1217
1218         /* Stop TX/RX DMA and clear the descriptors */
1219         priv->hw->dma->stop_tx(priv->ioaddr, SXGBE_TX_QUEUES);
1220         priv->hw->dma->stop_rx(priv->ioaddr, SXGBE_RX_QUEUES);
1221
1222         /* disable MTL queue */
1223         sxgbe_disable_mtl_engine(priv);
1224
1225         /* Release and free the Rx/Tx resources */
1226         free_dma_desc_resources(priv);
1227
1228         /* Disable the MAC Rx/Tx */
1229         priv->hw->mac->enable_tx(priv->ioaddr, false);
1230         priv->hw->mac->enable_rx(priv->ioaddr, false);
1231
1232         clk_disable_unprepare(priv->sxgbe_clk);
1233
1234         return 0;
1235 }
1236 /* Prepare first Tx descriptor for doing TSO operation */
1237 static void sxgbe_tso_prepare(struct sxgbe_priv_data *priv,
1238                               struct sxgbe_tx_norm_desc *first_desc,
1239                               struct sk_buff *skb)
1240 {
1241         unsigned int total_hdr_len, tcp_hdr_len;
1242
1243         /* Write first Tx descriptor with appropriate value */
1244         tcp_hdr_len = tcp_hdrlen(skb);
1245         total_hdr_len = skb_transport_offset(skb) + tcp_hdr_len;
1246
1247         first_desc->tdes01 = dma_map_single(priv->device, skb->data,
1248                                             total_hdr_len, DMA_TO_DEVICE);
1249         if (dma_mapping_error(priv->device, first_desc->tdes01))
1250                 pr_err("%s: TX dma mapping failed!!\n", __func__);
1251
1252         first_desc->tdes23.tx_rd_des23.first_desc = 1;
1253         priv->hw->desc->tx_desc_enable_tse(first_desc, 1, total_hdr_len,
1254                                            tcp_hdr_len,
1255                                            skb->len - total_hdr_len);
1256 }
1257
1258 /**
1259  *  sxgbe_xmit: Tx entry point of the driver
1260  *  @skb : the socket buffer
1261  *  @dev : device pointer
1262  *  Description : this is the tx entry point of the driver.
1263  *  It programs the chain or the ring and supports oversized frames
1264  *  and SG feature.
1265  */
1266 static netdev_tx_t sxgbe_xmit(struct sk_buff *skb, struct net_device *dev)
1267 {
1268         unsigned int entry, frag_num;
1269         int cksum_flag = 0;
1270         struct netdev_queue *dev_txq;
1271         unsigned txq_index = skb_get_queue_mapping(skb);
1272         struct sxgbe_priv_data *priv = netdev_priv(dev);
1273         unsigned int tx_rsize = priv->dma_tx_size;
1274         struct sxgbe_tx_queue *tqueue = priv->txq[txq_index];
1275         struct sxgbe_tx_norm_desc *tx_desc, *first_desc;
1276         struct sxgbe_tx_ctxt_desc *ctxt_desc = NULL;
1277         int nr_frags = skb_shinfo(skb)->nr_frags;
1278         int no_pagedlen = skb_headlen(skb);
1279         int is_jumbo = 0;
1280         u16 cur_mss = skb_shinfo(skb)->gso_size;
1281         u32 ctxt_desc_req = 0;
1282
1283         /* get the TX queue handle */
1284         dev_txq = netdev_get_tx_queue(dev, txq_index);
1285
1286         if (unlikely(skb_is_gso(skb) && tqueue->prev_mss != cur_mss))
1287                 ctxt_desc_req = 1;
1288
1289         if (unlikely(skb_vlan_tag_present(skb) ||
1290                      ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1291                       tqueue->hwts_tx_en)))
1292                 ctxt_desc_req = 1;
1293
1294         if (priv->tx_path_in_lpi_mode)
1295                 sxgbe_disable_eee_mode(priv);
1296
1297         if (unlikely(sxgbe_tx_avail(tqueue, tx_rsize) < nr_frags + 1)) {
1298                 if (!netif_tx_queue_stopped(dev_txq)) {
1299                         netif_tx_stop_queue(dev_txq);
1300                         netdev_err(dev, "%s: Tx Ring is full when %d queue is awake\n",
1301                                    __func__, txq_index);
1302                 }
1303                 return NETDEV_TX_BUSY;
1304         }
1305
1306         entry = tqueue->cur_tx % tx_rsize;
1307         tx_desc = tqueue->dma_tx + entry;
1308
1309         first_desc = tx_desc;
1310         if (ctxt_desc_req)
1311                 ctxt_desc = (struct sxgbe_tx_ctxt_desc *)first_desc;
1312
1313         /* save the skb address */
1314         tqueue->tx_skbuff[entry] = skb;
1315
1316         if (!is_jumbo) {
1317                 if (likely(skb_is_gso(skb))) {
1318                         /* TSO support */
1319                         if (unlikely(tqueue->prev_mss != cur_mss)) {
1320                                 priv->hw->desc->tx_ctxt_desc_set_mss(
1321                                                 ctxt_desc, cur_mss);
1322                                 priv->hw->desc->tx_ctxt_desc_set_tcmssv(
1323                                                 ctxt_desc);
1324                                 priv->hw->desc->tx_ctxt_desc_reset_ostc(
1325                                                 ctxt_desc);
1326                                 priv->hw->desc->tx_ctxt_desc_set_ctxt(
1327                                                 ctxt_desc);
1328                                 priv->hw->desc->tx_ctxt_desc_set_owner(
1329                                                 ctxt_desc);
1330
1331                                 entry = (++tqueue->cur_tx) % tx_rsize;
1332                                 first_desc = tqueue->dma_tx + entry;
1333
1334                                 tqueue->prev_mss = cur_mss;
1335                         }
1336                         sxgbe_tso_prepare(priv, first_desc, skb);
1337                 } else {
1338                         tx_desc->tdes01 = dma_map_single(priv->device,
1339                                                          skb->data, no_pagedlen, DMA_TO_DEVICE);
1340                         if (dma_mapping_error(priv->device, tx_desc->tdes01))
1341                                 netdev_err(dev, "%s: TX dma mapping failed!!\n",
1342                                            __func__);
1343
1344                         priv->hw->desc->prepare_tx_desc(tx_desc, 1, no_pagedlen,
1345                                                         no_pagedlen, cksum_flag);
1346                 }
1347         }
1348
1349         for (frag_num = 0; frag_num < nr_frags; frag_num++) {
1350                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_num];
1351                 int len = skb_frag_size(frag);
1352
1353                 entry = (++tqueue->cur_tx) % tx_rsize;
1354                 tx_desc = tqueue->dma_tx + entry;
1355                 tx_desc->tdes01 = skb_frag_dma_map(priv->device, frag, 0, len,
1356                                                    DMA_TO_DEVICE);
1357
1358                 tqueue->tx_skbuff_dma[entry] = tx_desc->tdes01;
1359                 tqueue->tx_skbuff[entry] = NULL;
1360
1361                 /* prepare the descriptor */
1362                 priv->hw->desc->prepare_tx_desc(tx_desc, 0, len,
1363                                                 len, cksum_flag);
1364                 /* memory barrier to flush descriptor */
1365                 wmb();
1366
1367                 /* set the owner */
1368                 priv->hw->desc->set_tx_owner(tx_desc);
1369         }
1370
1371         /* close the descriptors */
1372         priv->hw->desc->close_tx_desc(tx_desc);
1373
1374         /* memory barrier to flush descriptor */
1375         wmb();
1376
1377         tqueue->tx_count_frames += nr_frags + 1;
1378         if (tqueue->tx_count_frames > tqueue->tx_coal_frames) {
1379                 priv->hw->desc->clear_tx_ic(tx_desc);
1380                 priv->xstats.tx_reset_ic_bit++;
1381                 mod_timer(&tqueue->txtimer,
1382                           SXGBE_COAL_TIMER(tqueue->tx_coal_timer));
1383         } else {
1384                 tqueue->tx_count_frames = 0;
1385         }
1386
1387         /* set owner for first desc */
1388         priv->hw->desc->set_tx_owner(first_desc);
1389
1390         /* memory barrier to flush descriptor */
1391         wmb();
1392
1393         tqueue->cur_tx++;
1394
1395         /* display current ring */
1396         netif_dbg(priv, pktdata, dev, "%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d\n",
1397                   __func__, tqueue->cur_tx % tx_rsize,
1398                   tqueue->dirty_tx % tx_rsize, entry,
1399                   first_desc, nr_frags);
1400
1401         if (unlikely(sxgbe_tx_avail(tqueue, tx_rsize) <= (MAX_SKB_FRAGS + 1))) {
1402                 netif_dbg(priv, hw, dev, "%s: stop transmitted packets\n",
1403                           __func__);
1404                 netif_tx_stop_queue(dev_txq);
1405         }
1406
1407         dev->stats.tx_bytes += skb->len;
1408
1409         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1410                      tqueue->hwts_tx_en)) {
1411                 /* declare that device is doing timestamping */
1412                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1413                 priv->hw->desc->tx_enable_tstamp(first_desc);
1414         }
1415
1416         skb_tx_timestamp(skb);
1417
1418         priv->hw->dma->enable_dma_transmission(priv->ioaddr, txq_index);
1419
1420         return NETDEV_TX_OK;
1421 }
1422
1423 /**
1424  * sxgbe_rx_refill: refill used skb preallocated buffers
1425  * @priv: driver private structure
1426  * Description : this is to reallocate the skb for the reception process
1427  * that is based on zero-copy.
1428  */
1429 static void sxgbe_rx_refill(struct sxgbe_priv_data *priv)
1430 {
1431         unsigned int rxsize = priv->dma_rx_size;
1432         int bfsize = priv->dma_buf_sz;
1433         u8 qnum = priv->cur_rx_qnum;
1434
1435         for (; priv->rxq[qnum]->cur_rx - priv->rxq[qnum]->dirty_rx > 0;
1436              priv->rxq[qnum]->dirty_rx++) {
1437                 unsigned int entry = priv->rxq[qnum]->dirty_rx % rxsize;
1438                 struct sxgbe_rx_norm_desc *p;
1439
1440                 p = priv->rxq[qnum]->dma_rx + entry;
1441
1442                 if (likely(priv->rxq[qnum]->rx_skbuff[entry] == NULL)) {
1443                         struct sk_buff *skb;
1444
1445                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
1446
1447                         if (unlikely(skb == NULL))
1448                                 break;
1449
1450                         priv->rxq[qnum]->rx_skbuff[entry] = skb;
1451                         priv->rxq[qnum]->rx_skbuff_dma[entry] =
1452                                 dma_map_single(priv->device, skb->data, bfsize,
1453                                                DMA_FROM_DEVICE);
1454
1455                         p->rdes23.rx_rd_des23.buf2_addr =
1456                                 priv->rxq[qnum]->rx_skbuff_dma[entry];
1457                 }
1458
1459                 /* Added memory barrier for RX descriptor modification */
1460                 wmb();
1461                 priv->hw->desc->set_rx_owner(p);
1462                 priv->hw->desc->set_rx_int_on_com(p);
1463                 /* Added memory barrier for RX descriptor modification */
1464                 wmb();
1465         }
1466 }
1467
1468 /**
1469  * sxgbe_rx: receive the frames from the remote host
1470  * @priv: driver private structure
1471  * @limit: napi bugget.
1472  * Description :  this the function called by the napi poll method.
1473  * It gets all the frames inside the ring.
1474  */
1475 static int sxgbe_rx(struct sxgbe_priv_data *priv, int limit)
1476 {
1477         u8 qnum = priv->cur_rx_qnum;
1478         unsigned int rxsize = priv->dma_rx_size;
1479         unsigned int entry = priv->rxq[qnum]->cur_rx;
1480         unsigned int next_entry = 0;
1481         unsigned int count = 0;
1482         int checksum;
1483         int status;
1484
1485         while (count < limit) {
1486                 struct sxgbe_rx_norm_desc *p;
1487                 struct sk_buff *skb;
1488                 int frame_len;
1489
1490                 p = priv->rxq[qnum]->dma_rx + entry;
1491
1492                 if (priv->hw->desc->get_rx_owner(p))
1493                         break;
1494
1495                 count++;
1496
1497                 next_entry = (++priv->rxq[qnum]->cur_rx) % rxsize;
1498                 prefetch(priv->rxq[qnum]->dma_rx + next_entry);
1499
1500                 /* Read the status of the incoming frame and also get checksum
1501                  * value based on whether it is enabled in SXGBE hardware or
1502                  * not.
1503                  */
1504                 status = priv->hw->desc->rx_wbstatus(p, &priv->xstats,
1505                                                      &checksum);
1506                 if (unlikely(status < 0)) {
1507                         entry = next_entry;
1508                         continue;
1509                 }
1510                 if (unlikely(!priv->rxcsum_insertion))
1511                         checksum = CHECKSUM_NONE;
1512
1513                 skb = priv->rxq[qnum]->rx_skbuff[entry];
1514
1515                 if (unlikely(!skb))
1516                         netdev_err(priv->dev, "rx descriptor is not consistent\n");
1517
1518                 prefetch(skb->data - NET_IP_ALIGN);
1519                 priv->rxq[qnum]->rx_skbuff[entry] = NULL;
1520
1521                 frame_len = priv->hw->desc->get_rx_frame_len(p);
1522
1523                 skb_put(skb, frame_len);
1524
1525                 skb->ip_summed = checksum;
1526                 if (checksum == CHECKSUM_NONE)
1527                         netif_receive_skb(skb);
1528                 else
1529                         napi_gro_receive(&priv->napi, skb);
1530
1531                 entry = next_entry;
1532         }
1533
1534         sxgbe_rx_refill(priv);
1535
1536         return count;
1537 }
1538
1539 /**
1540  *  sxgbe_poll - sxgbe poll method (NAPI)
1541  *  @napi : pointer to the napi structure.
1542  *  @budget : maximum number of packets that the current CPU can receive from
1543  *            all interfaces.
1544  *  Description :
1545  *  To look at the incoming frames and clear the tx resources.
1546  */
1547 static int sxgbe_poll(struct napi_struct *napi, int budget)
1548 {
1549         struct sxgbe_priv_data *priv = container_of(napi,
1550                                                     struct sxgbe_priv_data, napi);
1551         int work_done = 0;
1552         u8 qnum = priv->cur_rx_qnum;
1553
1554         priv->xstats.napi_poll++;
1555         /* first, clean the tx queues */
1556         sxgbe_tx_all_clean(priv);
1557
1558         work_done = sxgbe_rx(priv, budget);
1559         if (work_done < budget) {
1560                 napi_complete_done(napi, work_done);
1561                 priv->hw->dma->enable_dma_irq(priv->ioaddr, qnum);
1562         }
1563
1564         return work_done;
1565 }
1566
1567 /**
1568  *  sxgbe_tx_timeout
1569  *  @dev : Pointer to net device structure
1570  *  Description: this function is called when a packet transmission fails to
1571  *   complete within a reasonable time. The driver will mark the error in the
1572  *   netdev structure and arrange for the device to be reset to a sane state
1573  *   in order to transmit a new packet.
1574  */
1575 static void sxgbe_tx_timeout(struct net_device *dev, unsigned int txqueue)
1576 {
1577         struct sxgbe_priv_data *priv = netdev_priv(dev);
1578
1579         sxgbe_reset_all_tx_queues(priv);
1580 }
1581
1582 /**
1583  *  sxgbe_common_interrupt - main ISR
1584  *  @irq: interrupt number.
1585  *  @dev_id: to pass the net device pointer.
1586  *  Description: this is the main driver interrupt service routine.
1587  *  It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI
1588  *  interrupts.
1589  */
1590 static irqreturn_t sxgbe_common_interrupt(int irq, void *dev_id)
1591 {
1592         struct net_device *netdev = (struct net_device *)dev_id;
1593         struct sxgbe_priv_data *priv = netdev_priv(netdev);
1594         int status;
1595
1596         status = priv->hw->mac->host_irq_status(priv->ioaddr, &priv->xstats);
1597         /* For LPI we need to save the tx status */
1598         if (status & TX_ENTRY_LPI_MODE) {
1599                 priv->xstats.tx_lpi_entry_n++;
1600                 priv->tx_path_in_lpi_mode = true;
1601         }
1602         if (status & TX_EXIT_LPI_MODE) {
1603                 priv->xstats.tx_lpi_exit_n++;
1604                 priv->tx_path_in_lpi_mode = false;
1605         }
1606         if (status & RX_ENTRY_LPI_MODE)
1607                 priv->xstats.rx_lpi_entry_n++;
1608         if (status & RX_EXIT_LPI_MODE)
1609                 priv->xstats.rx_lpi_exit_n++;
1610
1611         return IRQ_HANDLED;
1612 }
1613
1614 /**
1615  *  sxgbe_tx_interrupt - TX DMA ISR
1616  *  @irq: interrupt number.
1617  *  @dev_id: to pass the net device pointer.
1618  *  Description: this is the tx dma interrupt service routine.
1619  */
1620 static irqreturn_t sxgbe_tx_interrupt(int irq, void *dev_id)
1621 {
1622         int status;
1623         struct sxgbe_tx_queue *txq = (struct sxgbe_tx_queue *)dev_id;
1624         struct sxgbe_priv_data *priv = txq->priv_ptr;
1625
1626         /* get the channel status */
1627         status = priv->hw->dma->tx_dma_int_status(priv->ioaddr, txq->queue_no,
1628                                                   &priv->xstats);
1629         /* check for normal path */
1630         if (likely((status & handle_tx)))
1631                 napi_schedule(&priv->napi);
1632
1633         /* check for unrecoverable error */
1634         if (unlikely((status & tx_hard_error)))
1635                 sxgbe_restart_tx_queue(priv, txq->queue_no);
1636
1637         /* check for TC configuration change */
1638         if (unlikely((status & tx_bump_tc) &&
1639                      (priv->tx_tc != SXGBE_MTL_SFMODE) &&
1640                      (priv->tx_tc < 512))) {
1641                 /* step of TX TC is 32 till 128, otherwise 64 */
1642                 priv->tx_tc += (priv->tx_tc < 128) ? 32 : 64;
1643                 priv->hw->mtl->set_tx_mtl_mode(priv->ioaddr,
1644                                                txq->queue_no, priv->tx_tc);
1645                 priv->xstats.tx_threshold = priv->tx_tc;
1646         }
1647
1648         return IRQ_HANDLED;
1649 }
1650
1651 /**
1652  *  sxgbe_rx_interrupt - RX DMA ISR
1653  *  @irq: interrupt number.
1654  *  @dev_id: to pass the net device pointer.
1655  *  Description: this is the rx dma interrupt service routine.
1656  */
1657 static irqreturn_t sxgbe_rx_interrupt(int irq, void *dev_id)
1658 {
1659         int status;
1660         struct sxgbe_rx_queue *rxq = (struct sxgbe_rx_queue *)dev_id;
1661         struct sxgbe_priv_data *priv = rxq->priv_ptr;
1662
1663         /* get the channel status */
1664         status = priv->hw->dma->rx_dma_int_status(priv->ioaddr, rxq->queue_no,
1665                                                   &priv->xstats);
1666
1667         if (likely((status & handle_rx) && (napi_schedule_prep(&priv->napi)))) {
1668                 priv->hw->dma->disable_dma_irq(priv->ioaddr, rxq->queue_no);
1669                 __napi_schedule(&priv->napi);
1670         }
1671
1672         /* check for TC configuration change */
1673         if (unlikely((status & rx_bump_tc) &&
1674                      (priv->rx_tc != SXGBE_MTL_SFMODE) &&
1675                      (priv->rx_tc < 128))) {
1676                 /* step of TC is 32 */
1677                 priv->rx_tc += 32;
1678                 priv->hw->mtl->set_rx_mtl_mode(priv->ioaddr,
1679                                                rxq->queue_no, priv->rx_tc);
1680                 priv->xstats.rx_threshold = priv->rx_tc;
1681         }
1682
1683         return IRQ_HANDLED;
1684 }
1685
1686 static inline u64 sxgbe_get_stat64(void __iomem *ioaddr, int reg_lo, int reg_hi)
1687 {
1688         u64 val = readl(ioaddr + reg_lo);
1689
1690         val |= ((u64)readl(ioaddr + reg_hi)) << 32;
1691
1692         return val;
1693 }
1694
1695
1696 /*  sxgbe_get_stats64 - entry point to see statistical information of device
1697  *  @dev : device pointer.
1698  *  @stats : pointer to hold all the statistical information of device.
1699  *  Description:
1700  *  This function is a driver entry point whenever ifconfig command gets
1701  *  executed to see device statistics. Statistics are number of
1702  *  bytes sent or received, errors occurred etc.
1703  */
1704 static void sxgbe_get_stats64(struct net_device *dev,
1705                               struct rtnl_link_stats64 *stats)
1706 {
1707         struct sxgbe_priv_data *priv = netdev_priv(dev);
1708         void __iomem *ioaddr = priv->ioaddr;
1709         u64 count;
1710
1711         spin_lock(&priv->stats_lock);
1712         /* Freeze the counter registers before reading value otherwise it may
1713          * get updated by hardware while we are reading them
1714          */
1715         writel(SXGBE_MMC_CTRL_CNT_FRZ, ioaddr + SXGBE_MMC_CTL_REG);
1716
1717         stats->rx_bytes = sxgbe_get_stat64(ioaddr,
1718                                            SXGBE_MMC_RXOCTETLO_GCNT_REG,
1719                                            SXGBE_MMC_RXOCTETHI_GCNT_REG);
1720
1721         stats->rx_packets = sxgbe_get_stat64(ioaddr,
1722                                              SXGBE_MMC_RXFRAMELO_GBCNT_REG,
1723                                              SXGBE_MMC_RXFRAMEHI_GBCNT_REG);
1724
1725         stats->multicast = sxgbe_get_stat64(ioaddr,
1726                                             SXGBE_MMC_RXMULTILO_GCNT_REG,
1727                                             SXGBE_MMC_RXMULTIHI_GCNT_REG);
1728
1729         stats->rx_crc_errors = sxgbe_get_stat64(ioaddr,
1730                                                 SXGBE_MMC_RXCRCERRLO_REG,
1731                                                 SXGBE_MMC_RXCRCERRHI_REG);
1732
1733         stats->rx_length_errors = sxgbe_get_stat64(ioaddr,
1734                                                   SXGBE_MMC_RXLENERRLO_REG,
1735                                                   SXGBE_MMC_RXLENERRHI_REG);
1736
1737         stats->rx_missed_errors = sxgbe_get_stat64(ioaddr,
1738                                                    SXGBE_MMC_RXFIFOOVERFLOWLO_GBCNT_REG,
1739                                                    SXGBE_MMC_RXFIFOOVERFLOWHI_GBCNT_REG);
1740
1741         stats->tx_bytes = sxgbe_get_stat64(ioaddr,
1742                                            SXGBE_MMC_TXOCTETLO_GCNT_REG,
1743                                            SXGBE_MMC_TXOCTETHI_GCNT_REG);
1744
1745         count = sxgbe_get_stat64(ioaddr, SXGBE_MMC_TXFRAMELO_GBCNT_REG,
1746                                  SXGBE_MMC_TXFRAMEHI_GBCNT_REG);
1747
1748         stats->tx_errors = sxgbe_get_stat64(ioaddr, SXGBE_MMC_TXFRAMELO_GCNT_REG,
1749                                             SXGBE_MMC_TXFRAMEHI_GCNT_REG);
1750         stats->tx_errors = count - stats->tx_errors;
1751         stats->tx_packets = count;
1752         stats->tx_fifo_errors = sxgbe_get_stat64(ioaddr, SXGBE_MMC_TXUFLWLO_GBCNT_REG,
1753                                                  SXGBE_MMC_TXUFLWHI_GBCNT_REG);
1754         writel(0, ioaddr + SXGBE_MMC_CTL_REG);
1755         spin_unlock(&priv->stats_lock);
1756 }
1757
1758 /*  sxgbe_set_features - entry point to set offload features of the device.
1759  *  @dev : device pointer.
1760  *  @features : features which are required to be set.
1761  *  Description:
1762  *  This function is a driver entry point and called by Linux kernel whenever
1763  *  any device features are set or reset by user.
1764  *  Return value:
1765  *  This function returns 0 after setting or resetting device features.
1766  */
1767 static int sxgbe_set_features(struct net_device *dev,
1768                               netdev_features_t features)
1769 {
1770         struct sxgbe_priv_data *priv = netdev_priv(dev);
1771         netdev_features_t changed = dev->features ^ features;
1772
1773         if (changed & NETIF_F_RXCSUM) {
1774                 if (features & NETIF_F_RXCSUM) {
1775                         priv->hw->mac->enable_rx_csum(priv->ioaddr);
1776                         priv->rxcsum_insertion = true;
1777                 } else {
1778                         priv->hw->mac->disable_rx_csum(priv->ioaddr);
1779                         priv->rxcsum_insertion = false;
1780                 }
1781         }
1782
1783         return 0;
1784 }
1785
1786 /*  sxgbe_change_mtu - entry point to change MTU size for the device.
1787  *  @dev : device pointer.
1788  *  @new_mtu : the new MTU size for the device.
1789  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
1790  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
1791  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
1792  *  Return value:
1793  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1794  *  file on failure.
1795  */
1796 static int sxgbe_change_mtu(struct net_device *dev, int new_mtu)
1797 {
1798         dev->mtu = new_mtu;
1799
1800         if (!netif_running(dev))
1801                 return 0;
1802
1803         /* Recevice ring buffer size is needed to be set based on MTU. If MTU is
1804          * changed then reinitilisation of the receive ring buffers need to be
1805          * done. Hence bring interface down and bring interface back up
1806          */
1807         sxgbe_release(dev);
1808         return sxgbe_open(dev);
1809 }
1810
1811 static void sxgbe_set_umac_addr(void __iomem *ioaddr, unsigned char *addr,
1812                                 unsigned int reg_n)
1813 {
1814         unsigned long data;
1815
1816         data = (addr[5] << 8) | addr[4];
1817         /* For MAC Addr registers se have to set the Address Enable (AE)
1818          * bit that has no effect on the High Reg 0 where the bit 31 (MO)
1819          * is RO.
1820          */
1821         writel(data | SXGBE_HI_REG_AE, ioaddr + SXGBE_ADDR_HIGH(reg_n));
1822         data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
1823         writel(data, ioaddr + SXGBE_ADDR_LOW(reg_n));
1824 }
1825
1826 /**
1827  * sxgbe_set_rx_mode - entry point for setting different receive mode of
1828  * a device. unicast, multicast addressing
1829  * @dev : pointer to the device structure
1830  * Description:
1831  * This function is a driver entry point which gets called by the kernel
1832  * whenever different receive mode like unicast, multicast and promiscuous
1833  * must be enabled/disabled.
1834  * Return value:
1835  * void.
1836  */
1837 static void sxgbe_set_rx_mode(struct net_device *dev)
1838 {
1839         struct sxgbe_priv_data *priv = netdev_priv(dev);
1840         void __iomem *ioaddr = (void __iomem *)priv->ioaddr;
1841         unsigned int value = 0;
1842         u32 mc_filter[2];
1843         struct netdev_hw_addr *ha;
1844         int reg = 1;
1845
1846         netdev_dbg(dev, "%s: # mcasts %d, # unicast %d\n",
1847                    __func__, netdev_mc_count(dev), netdev_uc_count(dev));
1848
1849         if (dev->flags & IFF_PROMISC) {
1850                 value = SXGBE_FRAME_FILTER_PR;
1851
1852         } else if ((netdev_mc_count(dev) > SXGBE_HASH_TABLE_SIZE) ||
1853                    (dev->flags & IFF_ALLMULTI)) {
1854                 value = SXGBE_FRAME_FILTER_PM;  /* pass all multi */
1855                 writel(0xffffffff, ioaddr + SXGBE_HASH_HIGH);
1856                 writel(0xffffffff, ioaddr + SXGBE_HASH_LOW);
1857
1858         } else if (!netdev_mc_empty(dev)) {
1859                 /* Hash filter for multicast */
1860                 value = SXGBE_FRAME_FILTER_HMC;
1861
1862                 memset(mc_filter, 0, sizeof(mc_filter));
1863                 netdev_for_each_mc_addr(ha, dev) {
1864                         /* The upper 6 bits of the calculated CRC are used to
1865                          * index the contens of the hash table
1866                          */
1867                         int bit_nr = bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26;
1868
1869                         /* The most significant bit determines the register to
1870                          * use (H/L) while the other 5 bits determine the bit
1871                          * within the register.
1872                          */
1873                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1874                 }
1875                 writel(mc_filter[0], ioaddr + SXGBE_HASH_LOW);
1876                 writel(mc_filter[1], ioaddr + SXGBE_HASH_HIGH);
1877         }
1878
1879         /* Handle multiple unicast addresses (perfect filtering) */
1880         if (netdev_uc_count(dev) > SXGBE_MAX_PERFECT_ADDRESSES)
1881                 /* Switch to promiscuous mode if more than 16 addrs
1882                  * are required
1883                  */
1884                 value |= SXGBE_FRAME_FILTER_PR;
1885         else {
1886                 netdev_for_each_uc_addr(ha, dev) {
1887                         sxgbe_set_umac_addr(ioaddr, ha->addr, reg);
1888                         reg++;
1889                 }
1890         }
1891 #ifdef FRAME_FILTER_DEBUG
1892         /* Enable Receive all mode (to debug filtering_fail errors) */
1893         value |= SXGBE_FRAME_FILTER_RA;
1894 #endif
1895         writel(value, ioaddr + SXGBE_FRAME_FILTER);
1896
1897         netdev_dbg(dev, "Filter: 0x%08x\n\tHash: HI 0x%08x, LO 0x%08x\n",
1898                    readl(ioaddr + SXGBE_FRAME_FILTER),
1899                    readl(ioaddr + SXGBE_HASH_HIGH),
1900                    readl(ioaddr + SXGBE_HASH_LOW));
1901 }
1902
1903 #ifdef CONFIG_NET_POLL_CONTROLLER
1904 /**
1905  * sxgbe_poll_controller - entry point for polling receive by device
1906  * @dev : pointer to the device structure
1907  * Description:
1908  * This function is used by NETCONSOLE and other diagnostic tools
1909  * to allow network I/O with interrupts disabled.
1910  * Return value:
1911  * Void.
1912  */
1913 static void sxgbe_poll_controller(struct net_device *dev)
1914 {
1915         struct sxgbe_priv_data *priv = netdev_priv(dev);
1916
1917         disable_irq(priv->irq);
1918         sxgbe_rx_interrupt(priv->irq, dev);
1919         enable_irq(priv->irq);
1920 }
1921 #endif
1922
1923 /*  sxgbe_ioctl - Entry point for the Ioctl
1924  *  @dev: Device pointer.
1925  *  @rq: An IOCTL specefic structure, that can contain a pointer to
1926  *  a proprietary structure used to pass information to the driver.
1927  *  @cmd: IOCTL command
1928  *  Description:
1929  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
1930  */
1931 static int sxgbe_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1932 {
1933         int ret = -EOPNOTSUPP;
1934
1935         if (!netif_running(dev))
1936                 return -EINVAL;
1937
1938         switch (cmd) {
1939         case SIOCGMIIPHY:
1940         case SIOCGMIIREG:
1941         case SIOCSMIIREG:
1942                 ret = phy_do_ioctl(dev, rq, cmd);
1943                 break;
1944         default:
1945                 break;
1946         }
1947
1948         return ret;
1949 }
1950
1951 static const struct net_device_ops sxgbe_netdev_ops = {
1952         .ndo_open               = sxgbe_open,
1953         .ndo_start_xmit         = sxgbe_xmit,
1954         .ndo_stop               = sxgbe_release,
1955         .ndo_get_stats64        = sxgbe_get_stats64,
1956         .ndo_change_mtu         = sxgbe_change_mtu,
1957         .ndo_set_features       = sxgbe_set_features,
1958         .ndo_set_rx_mode        = sxgbe_set_rx_mode,
1959         .ndo_tx_timeout         = sxgbe_tx_timeout,
1960         .ndo_do_ioctl           = sxgbe_ioctl,
1961 #ifdef CONFIG_NET_POLL_CONTROLLER
1962         .ndo_poll_controller    = sxgbe_poll_controller,
1963 #endif
1964         .ndo_set_mac_address    = eth_mac_addr,
1965 };
1966
1967 /* Get the hardware ops */
1968 static void sxgbe_get_ops(struct sxgbe_ops * const ops_ptr)
1969 {
1970         ops_ptr->mac            = sxgbe_get_core_ops();
1971         ops_ptr->desc           = sxgbe_get_desc_ops();
1972         ops_ptr->dma            = sxgbe_get_dma_ops();
1973         ops_ptr->mtl            = sxgbe_get_mtl_ops();
1974
1975         /* set the MDIO communication Address/Data regisers */
1976         ops_ptr->mii.addr       = SXGBE_MDIO_SCMD_ADD_REG;
1977         ops_ptr->mii.data       = SXGBE_MDIO_SCMD_DATA_REG;
1978
1979         /* Assigning the default link settings
1980          * no SXGBE defined default values to be set in registers,
1981          * so assigning as 0 for port and duplex
1982          */
1983         ops_ptr->link.port      = 0;
1984         ops_ptr->link.duplex    = 0;
1985         ops_ptr->link.speed     = SXGBE_SPEED_10G;
1986 }
1987
1988 /**
1989  *  sxgbe_hw_init - Init the GMAC device
1990  *  @priv: driver private structure
1991  *  Description: this function checks the HW capability
1992  *  (if supported) and sets the driver's features.
1993  */
1994 static int sxgbe_hw_init(struct sxgbe_priv_data * const priv)
1995 {
1996         u32 ctrl_ids;
1997
1998         priv->hw = kmalloc(sizeof(*priv->hw), GFP_KERNEL);
1999         if(!priv->hw)
2000                 return -ENOMEM;
2001
2002         /* get the hardware ops */
2003         sxgbe_get_ops(priv->hw);
2004
2005         /* get the controller id */
2006         ctrl_ids = priv->hw->mac->get_controller_version(priv->ioaddr);
2007         priv->hw->ctrl_uid = (ctrl_ids & 0x00ff0000) >> 16;
2008         priv->hw->ctrl_id = (ctrl_ids & 0x000000ff);
2009         pr_info("user ID: 0x%x, Controller ID: 0x%x\n",
2010                 priv->hw->ctrl_uid, priv->hw->ctrl_id);
2011
2012         /* get the H/W features */
2013         if (!sxgbe_get_hw_features(priv))
2014                 pr_info("Hardware features not found\n");
2015
2016         if (priv->hw_cap.tx_csum_offload)
2017                 pr_info("TX Checksum offload supported\n");
2018
2019         if (priv->hw_cap.rx_csum_offload)
2020                 pr_info("RX Checksum offload supported\n");
2021
2022         return 0;
2023 }
2024
2025 static int sxgbe_sw_reset(void __iomem *addr)
2026 {
2027         int retry_count = 10;
2028
2029         writel(SXGBE_DMA_SOFT_RESET, addr + SXGBE_DMA_MODE_REG);
2030         while (retry_count--) {
2031                 if (!(readl(addr + SXGBE_DMA_MODE_REG) &
2032                       SXGBE_DMA_SOFT_RESET))
2033                         break;
2034                 mdelay(10);
2035         }
2036
2037         if (retry_count < 0)
2038                 return -EBUSY;
2039
2040         return 0;
2041 }
2042
2043 /**
2044  * sxgbe_drv_probe
2045  * @device: device pointer
2046  * @plat_dat: platform data pointer
2047  * @addr: iobase memory address
2048  * Description: this is the main probe function used to
2049  * call the alloc_etherdev, allocate the priv structure.
2050  */
2051 struct sxgbe_priv_data *sxgbe_drv_probe(struct device *device,
2052                                         struct sxgbe_plat_data *plat_dat,
2053                                         void __iomem *addr)
2054 {
2055         struct sxgbe_priv_data *priv;
2056         struct net_device *ndev;
2057         int ret;
2058         u8 queue_num;
2059
2060         ndev = alloc_etherdev_mqs(sizeof(struct sxgbe_priv_data),
2061                                   SXGBE_TX_QUEUES, SXGBE_RX_QUEUES);
2062         if (!ndev)
2063                 return NULL;
2064
2065         SET_NETDEV_DEV(ndev, device);
2066
2067         priv = netdev_priv(ndev);
2068         priv->device = device;
2069         priv->dev = ndev;
2070
2071         sxgbe_set_ethtool_ops(ndev);
2072         priv->plat = plat_dat;
2073         priv->ioaddr = addr;
2074
2075         ret = sxgbe_sw_reset(priv->ioaddr);
2076         if (ret)
2077                 goto error_free_netdev;
2078
2079         /* Verify driver arguments */
2080         sxgbe_verify_args();
2081
2082         /* Init MAC and get the capabilities */
2083         ret = sxgbe_hw_init(priv);
2084         if (ret)
2085                 goto error_free_netdev;
2086
2087         /* allocate memory resources for Descriptor rings */
2088         ret = txring_mem_alloc(priv);
2089         if (ret)
2090                 goto error_free_hw;
2091
2092         ret = rxring_mem_alloc(priv);
2093         if (ret)
2094                 goto error_free_hw;
2095
2096         ndev->netdev_ops = &sxgbe_netdev_ops;
2097
2098         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2099                 NETIF_F_RXCSUM | NETIF_F_TSO | NETIF_F_TSO6 |
2100                 NETIF_F_GRO;
2101         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2102         ndev->watchdog_timeo = msecs_to_jiffies(TX_TIMEO);
2103
2104         /* assign filtering support */
2105         ndev->priv_flags |= IFF_UNICAST_FLT;
2106
2107         /* MTU range: 68 - 9000 */
2108         ndev->min_mtu = MIN_MTU;
2109         ndev->max_mtu = MAX_MTU;
2110
2111         priv->msg_enable = netif_msg_init(debug, default_msg_level);
2112
2113         /* Enable TCP segmentation offload for all DMA channels */
2114         if (priv->hw_cap.tcpseg_offload) {
2115                 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
2116                         priv->hw->dma->enable_tso(priv->ioaddr, queue_num);
2117                 }
2118         }
2119
2120         /* Enable Rx checksum offload */
2121         if (priv->hw_cap.rx_csum_offload) {
2122                 priv->hw->mac->enable_rx_csum(priv->ioaddr);
2123                 priv->rxcsum_insertion = true;
2124         }
2125
2126         /* Initialise pause frame settings */
2127         priv->rx_pause = 1;
2128         priv->tx_pause = 1;
2129
2130         /* Rx Watchdog is available, enable depend on platform data */
2131         if (!priv->plat->riwt_off) {
2132                 priv->use_riwt = 1;
2133                 pr_info("Enable RX Mitigation via HW Watchdog Timer\n");
2134         }
2135
2136         netif_napi_add(ndev, &priv->napi, sxgbe_poll, 64);
2137
2138         spin_lock_init(&priv->stats_lock);
2139
2140         priv->sxgbe_clk = clk_get(priv->device, SXGBE_RESOURCE_NAME);
2141         if (IS_ERR(priv->sxgbe_clk)) {
2142                 netdev_warn(ndev, "%s: warning: cannot get CSR clock\n",
2143                             __func__);
2144                 goto error_napi_del;
2145         }
2146
2147         /* If a specific clk_csr value is passed from the platform
2148          * this means that the CSR Clock Range selection cannot be
2149          * changed at run-time and it is fixed. Viceversa the driver'll try to
2150          * set the MDC clock dynamically according to the csr actual
2151          * clock input.
2152          */
2153         if (!priv->plat->clk_csr)
2154                 sxgbe_clk_csr_set(priv);
2155         else
2156                 priv->clk_csr = priv->plat->clk_csr;
2157
2158         /* MDIO bus Registration */
2159         ret = sxgbe_mdio_register(ndev);
2160         if (ret < 0) {
2161                 netdev_dbg(ndev, "%s: MDIO bus (id: %d) registration failed\n",
2162                            __func__, priv->plat->bus_id);
2163                 goto error_clk_put;
2164         }
2165
2166         ret = register_netdev(ndev);
2167         if (ret) {
2168                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2169                 goto error_mdio_unregister;
2170         }
2171
2172         sxgbe_check_ether_addr(priv);
2173
2174         return priv;
2175
2176 error_mdio_unregister:
2177         sxgbe_mdio_unregister(ndev);
2178 error_clk_put:
2179         clk_put(priv->sxgbe_clk);
2180 error_napi_del:
2181         netif_napi_del(&priv->napi);
2182 error_free_hw:
2183         kfree(priv->hw);
2184 error_free_netdev:
2185         free_netdev(ndev);
2186
2187         return NULL;
2188 }
2189
2190 /**
2191  * sxgbe_drv_remove
2192  * @ndev: net device pointer
2193  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2194  * changes the link status, releases the DMA descriptor rings.
2195  */
2196 int sxgbe_drv_remove(struct net_device *ndev)
2197 {
2198         struct sxgbe_priv_data *priv = netdev_priv(ndev);
2199         u8 queue_num;
2200
2201         netdev_info(ndev, "%s: removing driver\n", __func__);
2202
2203         SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
2204                 priv->hw->mac->disable_rxqueue(priv->ioaddr, queue_num);
2205         }
2206
2207         priv->hw->dma->stop_rx(priv->ioaddr, SXGBE_RX_QUEUES);
2208         priv->hw->dma->stop_tx(priv->ioaddr, SXGBE_TX_QUEUES);
2209
2210         priv->hw->mac->enable_tx(priv->ioaddr, false);
2211         priv->hw->mac->enable_rx(priv->ioaddr, false);
2212
2213         unregister_netdev(ndev);
2214
2215         sxgbe_mdio_unregister(ndev);
2216
2217         clk_put(priv->sxgbe_clk);
2218
2219         netif_napi_del(&priv->napi);
2220
2221         kfree(priv->hw);
2222
2223         free_netdev(ndev);
2224
2225         return 0;
2226 }
2227
2228 #ifdef CONFIG_PM
2229 int sxgbe_suspend(struct net_device *ndev)
2230 {
2231         return 0;
2232 }
2233
2234 int sxgbe_resume(struct net_device *ndev)
2235 {
2236         return 0;
2237 }
2238
2239 int sxgbe_freeze(struct net_device *ndev)
2240 {
2241         return -ENOSYS;
2242 }
2243
2244 int sxgbe_restore(struct net_device *ndev)
2245 {
2246         return -ENOSYS;
2247 }
2248 #endif /* CONFIG_PM */
2249
2250 /* Driver is configured as Platform driver */
2251 static int __init sxgbe_init(void)
2252 {
2253         int ret;
2254
2255         ret = sxgbe_register_platform();
2256         if (ret)
2257                 goto err;
2258         return 0;
2259 err:
2260         pr_err("driver registration failed\n");
2261         return ret;
2262 }
2263
2264 static void __exit sxgbe_exit(void)
2265 {
2266         sxgbe_unregister_platform();
2267 }
2268
2269 module_init(sxgbe_init);
2270 module_exit(sxgbe_exit);
2271
2272 #ifndef MODULE
2273 static int __init sxgbe_cmdline_opt(char *str)
2274 {
2275         char *opt;
2276
2277         if (!str || !*str)
2278                 return -EINVAL;
2279         while ((opt = strsep(&str, ",")) != NULL) {
2280                 if (!strncmp(opt, "eee_timer:", 6)) {
2281                         if (kstrtoint(opt + 10, 0, &eee_timer))
2282                                 goto err;
2283                 }
2284         }
2285         return 0;
2286
2287 err:
2288         pr_err("%s: ERROR broken module parameter conversion\n", __func__);
2289         return -EINVAL;
2290 }
2291
2292 __setup("sxgbeeth=", sxgbe_cmdline_opt);
2293 #endif /* MODULE */
2294
2295
2296
2297 MODULE_DESCRIPTION("Samsung 10G/2.5G/1G Ethernet PLATFORM driver");
2298
2299 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
2300 MODULE_PARM_DESC(eee_timer, "EEE-LPI Default LS timer value");
2301
2302 MODULE_AUTHOR("Siva Reddy Kallam <siva.kallam@samsung.com>");
2303 MODULE_AUTHOR("ByungHo An <bh74.an@samsung.com>");
2304 MODULE_AUTHOR("Girish K S <ks.giri@samsung.com>");
2305 MODULE_AUTHOR("Vipul Pandya <vipul.pandya@samsung.com>");
2306
2307 MODULE_LICENSE("GPL");