1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
4 ST Ethernet IPs are built around a Synopsys IP Core.
6 Copyright(C) 2007-2011 STMicroelectronics Ltd
9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
11 Documentation available at:
12 http://www.stlinux.com
14 https://bugzilla.stlinux.com/
15 *******************************************************************************/
17 #include <linux/clk.h>
18 #include <linux/kernel.h>
19 #include <linux/interrupt.h>
21 #include <linux/tcp.h>
22 #include <linux/skbuff.h>
23 #include <linux/ethtool.h>
24 #include <linux/if_ether.h>
25 #include <linux/crc32.h>
26 #include <linux/mii.h>
28 #include <linux/if_vlan.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/slab.h>
31 #include <linux/prefetch.h>
32 #include <linux/pinctrl/consumer.h>
33 #ifdef CONFIG_DEBUG_FS
34 #include <linux/debugfs.h>
35 #include <linux/seq_file.h>
36 #endif /* CONFIG_DEBUG_FS */
37 #include <linux/net_tstamp.h>
38 #include <linux/phylink.h>
39 #include <linux/udp.h>
40 #include <net/pkt_cls.h>
41 #include "stmmac_ptp.h"
43 #include <linux/reset.h>
44 #include <linux/of_mdio.h>
45 #include "dwmac1000.h"
49 #define STMMAC_ALIGN(x) __ALIGN_KERNEL(x, SMP_CACHE_BYTES)
50 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
52 /* Module parameters */
54 static int watchdog = TX_TIMEO;
55 module_param(watchdog, int, 0644);
56 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
58 static int debug = -1;
59 module_param(debug, int, 0644);
60 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
62 static int phyaddr = -1;
63 module_param(phyaddr, int, 0444);
64 MODULE_PARM_DESC(phyaddr, "Physical device address");
66 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4)
67 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4)
69 static int flow_ctrl = FLOW_AUTO;
70 module_param(flow_ctrl, int, 0644);
71 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
73 static int pause = PAUSE_TIME;
74 module_param(pause, int, 0644);
75 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
78 static int tc = TC_DEFAULT;
79 module_param(tc, int, 0644);
80 MODULE_PARM_DESC(tc, "DMA threshold control value");
82 #define DEFAULT_BUFSIZE 1536
83 static int buf_sz = DEFAULT_BUFSIZE;
84 module_param(buf_sz, int, 0644);
85 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
87 #define STMMAC_RX_COPYBREAK 256
89 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
90 NETIF_MSG_LINK | NETIF_MSG_IFUP |
91 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
93 #define STMMAC_DEFAULT_LPI_TIMER 1000
94 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
95 module_param(eee_timer, int, 0644);
96 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
97 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
99 /* By default the driver will use the ring mode to manage tx and rx descriptors,
100 * but allow user to force to use the chain instead of the ring
102 static unsigned int chain_mode;
103 module_param(chain_mode, int, 0444);
104 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
106 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
108 #ifdef CONFIG_DEBUG_FS
109 static void stmmac_init_fs(struct net_device *dev);
110 static void stmmac_exit_fs(struct net_device *dev);
113 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
116 * stmmac_verify_args - verify the driver parameters.
117 * Description: it checks the driver parameters and set a default in case of
120 static void stmmac_verify_args(void)
122 if (unlikely(watchdog < 0))
124 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
125 buf_sz = DEFAULT_BUFSIZE;
126 if (unlikely(flow_ctrl > 1))
127 flow_ctrl = FLOW_AUTO;
128 else if (likely(flow_ctrl < 0))
129 flow_ctrl = FLOW_OFF;
130 if (unlikely((pause < 0) || (pause > 0xffff)))
133 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
137 * stmmac_disable_all_queues - Disable all queues
138 * @priv: driver private structure
140 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
142 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
143 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
144 u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
147 for (queue = 0; queue < maxq; queue++) {
148 struct stmmac_channel *ch = &priv->channel[queue];
150 if (queue < rx_queues_cnt)
151 napi_disable(&ch->rx_napi);
152 if (queue < tx_queues_cnt)
153 napi_disable(&ch->tx_napi);
158 * stmmac_enable_all_queues - Enable all queues
159 * @priv: driver private structure
161 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
163 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
164 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
165 u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
168 for (queue = 0; queue < maxq; queue++) {
169 struct stmmac_channel *ch = &priv->channel[queue];
171 if (queue < rx_queues_cnt)
172 napi_enable(&ch->rx_napi);
173 if (queue < tx_queues_cnt)
174 napi_enable(&ch->tx_napi);
179 * stmmac_stop_all_queues - Stop all queues
180 * @priv: driver private structure
182 static void stmmac_stop_all_queues(struct stmmac_priv *priv)
184 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
187 for (queue = 0; queue < tx_queues_cnt; queue++)
188 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
192 * stmmac_start_all_queues - Start all queues
193 * @priv: driver private structure
195 static void stmmac_start_all_queues(struct stmmac_priv *priv)
197 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
200 for (queue = 0; queue < tx_queues_cnt; queue++)
201 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue));
204 static void stmmac_service_event_schedule(struct stmmac_priv *priv)
206 if (!test_bit(STMMAC_DOWN, &priv->state) &&
207 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state))
208 queue_work(priv->wq, &priv->service_task);
211 static void stmmac_global_err(struct stmmac_priv *priv)
213 netif_carrier_off(priv->dev);
214 set_bit(STMMAC_RESET_REQUESTED, &priv->state);
215 stmmac_service_event_schedule(priv);
219 * stmmac_clk_csr_set - dynamically set the MDC clock
220 * @priv: driver private structure
221 * Description: this is to dynamically set the MDC clock according to the csr
224 * If a specific clk_csr value is passed from the platform
225 * this means that the CSR Clock Range selection cannot be
226 * changed at run-time and it is fixed (as reported in the driver
227 * documentation). Viceversa the driver will try to set the MDC
228 * clock dynamically according to the actual clock input.
230 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
234 clk_rate = clk_get_rate(priv->plat->stmmac_clk);
236 /* Platform provided default clk_csr would be assumed valid
237 * for all other cases except for the below mentioned ones.
238 * For values higher than the IEEE 802.3 specified frequency
239 * we can not estimate the proper divider as it is not known
240 * the frequency of clk_csr_i. So we do not change the default
243 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
244 if (clk_rate < CSR_F_35M)
245 priv->clk_csr = STMMAC_CSR_20_35M;
246 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
247 priv->clk_csr = STMMAC_CSR_35_60M;
248 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
249 priv->clk_csr = STMMAC_CSR_60_100M;
250 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
251 priv->clk_csr = STMMAC_CSR_100_150M;
252 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
253 priv->clk_csr = STMMAC_CSR_150_250M;
254 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
255 priv->clk_csr = STMMAC_CSR_250_300M;
258 if (priv->plat->has_sun8i) {
259 if (clk_rate > 160000000)
260 priv->clk_csr = 0x03;
261 else if (clk_rate > 80000000)
262 priv->clk_csr = 0x02;
263 else if (clk_rate > 40000000)
264 priv->clk_csr = 0x01;
269 if (priv->plat->has_xgmac) {
270 if (clk_rate > 400000000)
272 else if (clk_rate > 350000000)
274 else if (clk_rate > 300000000)
276 else if (clk_rate > 250000000)
278 else if (clk_rate > 150000000)
285 static void print_pkt(unsigned char *buf, int len)
287 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
288 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
291 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
293 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
296 if (tx_q->dirty_tx > tx_q->cur_tx)
297 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
299 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1;
305 * stmmac_rx_dirty - Get RX queue dirty
306 * @priv: driver private structure
307 * @queue: RX queue index
309 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
311 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
314 if (rx_q->dirty_rx <= rx_q->cur_rx)
315 dirty = rx_q->cur_rx - rx_q->dirty_rx;
317 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx;
323 * stmmac_enable_eee_mode - check and enter in LPI mode
324 * @priv: driver private structure
325 * Description: this function is to verify and enter in LPI mode in case of
328 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
330 u32 tx_cnt = priv->plat->tx_queues_to_use;
333 /* check if all TX queues have the work finished */
334 for (queue = 0; queue < tx_cnt; queue++) {
335 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
337 if (tx_q->dirty_tx != tx_q->cur_tx)
338 return; /* still unfinished work */
341 /* Check and enter in LPI mode */
342 if (!priv->tx_path_in_lpi_mode)
343 stmmac_set_eee_mode(priv, priv->hw,
344 priv->plat->en_tx_lpi_clockgating);
348 * stmmac_disable_eee_mode - disable and exit from LPI mode
349 * @priv: driver private structure
350 * Description: this function is to exit and disable EEE in case of
351 * LPI state is true. This is called by the xmit.
353 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
355 stmmac_reset_eee_mode(priv, priv->hw);
356 del_timer_sync(&priv->eee_ctrl_timer);
357 priv->tx_path_in_lpi_mode = false;
361 * stmmac_eee_ctrl_timer - EEE TX SW timer.
364 * if there is no data transfer and if we are not in LPI state,
365 * then MAC Transmitter can be moved to LPI state.
367 static void stmmac_eee_ctrl_timer(struct timer_list *t)
369 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer);
371 stmmac_enable_eee_mode(priv);
372 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
376 * stmmac_eee_init - init EEE
377 * @priv: driver private structure
379 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
380 * can also manage EEE, this function enable the LPI state and start related
383 bool stmmac_eee_init(struct stmmac_priv *priv)
385 int tx_lpi_timer = priv->tx_lpi_timer;
387 /* Using PCS we cannot dial with the phy registers at this stage
388 * so we do not support extra feature like EEE.
390 if ((priv->hw->pcs == STMMAC_PCS_RGMII) ||
391 (priv->hw->pcs == STMMAC_PCS_TBI) ||
392 (priv->hw->pcs == STMMAC_PCS_RTBI))
395 /* Check if MAC core supports the EEE feature. */
396 if (!priv->dma_cap.eee)
399 mutex_lock(&priv->lock);
401 /* Check if it needs to be deactivated */
402 if (!priv->eee_active) {
403 if (priv->eee_enabled) {
404 netdev_dbg(priv->dev, "disable EEE\n");
405 del_timer_sync(&priv->eee_ctrl_timer);
406 stmmac_set_eee_timer(priv, priv->hw, 0, tx_lpi_timer);
408 mutex_unlock(&priv->lock);
412 if (priv->eee_active && !priv->eee_enabled) {
413 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0);
414 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
415 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS,
419 mutex_unlock(&priv->lock);
420 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
424 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
425 * @priv: driver private structure
426 * @p : descriptor pointer
427 * @skb : the socket buffer
429 * This function will read timestamp from the descriptor & pass it to stack.
430 * and also perform some sanity checks.
432 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
433 struct dma_desc *p, struct sk_buff *skb)
435 struct skb_shared_hwtstamps shhwtstamp;
439 if (!priv->hwts_tx_en)
442 /* exit if skb doesn't support hw tstamp */
443 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
446 /* check tx tstamp status */
447 if (stmmac_get_tx_timestamp_status(priv, p)) {
448 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
450 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) {
455 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
456 shhwtstamp.hwtstamp = ns_to_ktime(ns);
458 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
459 /* pass tstamp to stack */
460 skb_tstamp_tx(skb, &shhwtstamp);
464 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
465 * @priv: driver private structure
466 * @p : descriptor pointer
467 * @np : next descriptor pointer
468 * @skb : the socket buffer
470 * This function will read received packet's timestamp from the descriptor
471 * and pass it to stack. It also perform some sanity checks.
473 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
474 struct dma_desc *np, struct sk_buff *skb)
476 struct skb_shared_hwtstamps *shhwtstamp = NULL;
477 struct dma_desc *desc = p;
480 if (!priv->hwts_rx_en)
482 /* For GMAC4, the valid timestamp is from CTX next desc. */
483 if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
486 /* Check if timestamp is available */
487 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
488 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
489 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
490 shhwtstamp = skb_hwtstamps(skb);
491 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
492 shhwtstamp->hwtstamp = ns_to_ktime(ns);
494 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
499 * stmmac_hwtstamp_set - control hardware timestamping.
500 * @dev: device pointer.
501 * @ifr: An IOCTL specific structure, that can contain a pointer to
502 * a proprietary structure used to pass information to the driver.
504 * This function configures the MAC to enable/disable both outgoing(TX)
505 * and incoming(RX) packets time stamping based on user input.
507 * 0 on success and an appropriate -ve integer on failure.
509 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
511 struct stmmac_priv *priv = netdev_priv(dev);
512 struct hwtstamp_config config;
513 struct timespec64 now;
517 u32 ptp_over_ipv4_udp = 0;
518 u32 ptp_over_ipv6_udp = 0;
519 u32 ptp_over_ethernet = 0;
520 u32 snap_type_sel = 0;
521 u32 ts_master_en = 0;
527 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
529 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
530 netdev_alert(priv->dev, "No support for HW time stamping\n");
531 priv->hwts_tx_en = 0;
532 priv->hwts_rx_en = 0;
537 if (copy_from_user(&config, ifr->ifr_data,
541 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
542 __func__, config.flags, config.tx_type, config.rx_filter);
544 /* reserved for future extensions */
548 if (config.tx_type != HWTSTAMP_TX_OFF &&
549 config.tx_type != HWTSTAMP_TX_ON)
553 switch (config.rx_filter) {
554 case HWTSTAMP_FILTER_NONE:
555 /* time stamp no incoming packet at all */
556 config.rx_filter = HWTSTAMP_FILTER_NONE;
559 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
560 /* PTP v1, UDP, any kind of event packet */
561 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
562 /* 'xmac' hardware can support Sync, Pdelay_Req and
563 * Pdelay_resp by setting bit14 and bits17/16 to 01
564 * This leaves Delay_Req timestamps out.
565 * Enable all events *and* general purpose message
568 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
569 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
570 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
573 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
574 /* PTP v1, UDP, Sync packet */
575 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
576 /* take time stamp for SYNC messages only */
577 ts_event_en = PTP_TCR_TSEVNTENA;
579 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
580 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
583 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
584 /* PTP v1, UDP, Delay_req packet */
585 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
586 /* take time stamp for Delay_Req messages only */
587 ts_master_en = PTP_TCR_TSMSTRENA;
588 ts_event_en = PTP_TCR_TSEVNTENA;
590 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
591 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
594 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
595 /* PTP v2, UDP, any kind of event packet */
596 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
597 ptp_v2 = PTP_TCR_TSVER2ENA;
598 /* take time stamp for all event messages */
599 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
601 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
602 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
605 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
606 /* PTP v2, UDP, Sync packet */
607 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
608 ptp_v2 = PTP_TCR_TSVER2ENA;
609 /* take time stamp for SYNC messages only */
610 ts_event_en = PTP_TCR_TSEVNTENA;
612 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
613 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
616 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
617 /* PTP v2, UDP, Delay_req packet */
618 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
619 ptp_v2 = PTP_TCR_TSVER2ENA;
620 /* take time stamp for Delay_Req messages only */
621 ts_master_en = PTP_TCR_TSMSTRENA;
622 ts_event_en = PTP_TCR_TSEVNTENA;
624 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
625 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
628 case HWTSTAMP_FILTER_PTP_V2_EVENT:
629 /* PTP v2/802.AS1 any layer, any kind of event packet */
630 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
631 ptp_v2 = PTP_TCR_TSVER2ENA;
632 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
633 ts_event_en = PTP_TCR_TSEVNTENA;
634 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
635 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
636 ptp_over_ethernet = PTP_TCR_TSIPENA;
639 case HWTSTAMP_FILTER_PTP_V2_SYNC:
640 /* PTP v2/802.AS1, any layer, Sync packet */
641 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
642 ptp_v2 = PTP_TCR_TSVER2ENA;
643 /* take time stamp for SYNC messages only */
644 ts_event_en = PTP_TCR_TSEVNTENA;
646 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
647 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
648 ptp_over_ethernet = PTP_TCR_TSIPENA;
651 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
652 /* PTP v2/802.AS1, any layer, Delay_req packet */
653 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
654 ptp_v2 = PTP_TCR_TSVER2ENA;
655 /* take time stamp for Delay_Req messages only */
656 ts_master_en = PTP_TCR_TSMSTRENA;
657 ts_event_en = PTP_TCR_TSEVNTENA;
659 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
660 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
661 ptp_over_ethernet = PTP_TCR_TSIPENA;
664 case HWTSTAMP_FILTER_NTP_ALL:
665 case HWTSTAMP_FILTER_ALL:
666 /* time stamp any incoming packet */
667 config.rx_filter = HWTSTAMP_FILTER_ALL;
668 tstamp_all = PTP_TCR_TSENALL;
675 switch (config.rx_filter) {
676 case HWTSTAMP_FILTER_NONE:
677 config.rx_filter = HWTSTAMP_FILTER_NONE;
680 /* PTP v1, UDP, any kind of event packet */
681 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
685 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
686 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
688 if (!priv->hwts_tx_en && !priv->hwts_rx_en)
689 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0);
691 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
692 tstamp_all | ptp_v2 | ptp_over_ethernet |
693 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
694 ts_master_en | snap_type_sel);
695 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value);
697 /* program Sub Second Increment reg */
698 stmmac_config_sub_second_increment(priv,
699 priv->ptpaddr, priv->plat->clk_ptp_rate,
701 temp = div_u64(1000000000ULL, sec_inc);
703 /* Store sub second increment and flags for later use */
704 priv->sub_second_inc = sec_inc;
705 priv->systime_flags = value;
707 /* calculate default added value:
709 * addend = (2^32)/freq_div_ratio;
710 * where, freq_div_ratio = 1e9ns/sec_inc
712 temp = (u64)(temp << 32);
713 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
714 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);
716 /* initialize system time */
717 ktime_get_real_ts64(&now);
719 /* lower 32 bits of tv_sec are safe until y2106 */
720 stmmac_init_systime(priv, priv->ptpaddr,
721 (u32)now.tv_sec, now.tv_nsec);
724 memcpy(&priv->tstamp_config, &config, sizeof(config));
726 return copy_to_user(ifr->ifr_data, &config,
727 sizeof(config)) ? -EFAULT : 0;
731 * stmmac_hwtstamp_get - read hardware timestamping.
732 * @dev: device pointer.
733 * @ifr: An IOCTL specific structure, that can contain a pointer to
734 * a proprietary structure used to pass information to the driver.
736 * This function obtain the current hardware timestamping settings
739 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
741 struct stmmac_priv *priv = netdev_priv(dev);
742 struct hwtstamp_config *config = &priv->tstamp_config;
744 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
747 return copy_to_user(ifr->ifr_data, config,
748 sizeof(*config)) ? -EFAULT : 0;
752 * stmmac_init_ptp - init PTP
753 * @priv: driver private structure
754 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
755 * This is done by looking at the HW cap. register.
756 * This function also registers the ptp driver.
758 static int stmmac_init_ptp(struct stmmac_priv *priv)
760 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
762 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
766 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */
767 if (xmac && priv->dma_cap.atime_stamp)
769 /* Dwmac 3.x core with extend_desc can support adv_ts */
770 else if (priv->extend_desc && priv->dma_cap.atime_stamp)
773 if (priv->dma_cap.time_stamp)
774 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
777 netdev_info(priv->dev,
778 "IEEE 1588-2008 Advanced Timestamp supported\n");
780 priv->hwts_tx_en = 0;
781 priv->hwts_rx_en = 0;
783 stmmac_ptp_register(priv);
788 static void stmmac_release_ptp(struct stmmac_priv *priv)
790 if (priv->plat->clk_ptp_ref)
791 clk_disable_unprepare(priv->plat->clk_ptp_ref);
792 stmmac_ptp_unregister(priv);
796 * stmmac_mac_flow_ctrl - Configure flow control in all queues
797 * @priv: driver private structure
798 * Description: It is used for configuring the flow control in all queues
800 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
802 u32 tx_cnt = priv->plat->tx_queues_to_use;
804 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
805 priv->pause, tx_cnt);
808 static void stmmac_validate(struct phylink_config *config,
809 unsigned long *supported,
810 struct phylink_link_state *state)
812 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
813 __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, };
814 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
815 int tx_cnt = priv->plat->tx_queues_to_use;
816 int max_speed = priv->plat->max_speed;
818 phylink_set(mac_supported, 10baseT_Half);
819 phylink_set(mac_supported, 10baseT_Full);
820 phylink_set(mac_supported, 100baseT_Half);
821 phylink_set(mac_supported, 100baseT_Full);
822 phylink_set(mac_supported, 1000baseT_Half);
823 phylink_set(mac_supported, 1000baseT_Full);
824 phylink_set(mac_supported, 1000baseKX_Full);
826 phylink_set(mac_supported, Autoneg);
827 phylink_set(mac_supported, Pause);
828 phylink_set(mac_supported, Asym_Pause);
829 phylink_set_port_modes(mac_supported);
831 /* Cut down 1G if asked to */
832 if ((max_speed > 0) && (max_speed < 1000)) {
833 phylink_set(mask, 1000baseT_Full);
834 phylink_set(mask, 1000baseX_Full);
835 } else if (priv->plat->has_xgmac) {
836 if (!max_speed || (max_speed >= 2500)) {
837 phylink_set(mac_supported, 2500baseT_Full);
838 phylink_set(mac_supported, 2500baseX_Full);
840 if (!max_speed || (max_speed >= 5000)) {
841 phylink_set(mac_supported, 5000baseT_Full);
843 if (!max_speed || (max_speed >= 10000)) {
844 phylink_set(mac_supported, 10000baseSR_Full);
845 phylink_set(mac_supported, 10000baseLR_Full);
846 phylink_set(mac_supported, 10000baseER_Full);
847 phylink_set(mac_supported, 10000baseLRM_Full);
848 phylink_set(mac_supported, 10000baseT_Full);
849 phylink_set(mac_supported, 10000baseKX4_Full);
850 phylink_set(mac_supported, 10000baseKR_Full);
854 /* Half-Duplex can only work with single queue */
856 phylink_set(mask, 10baseT_Half);
857 phylink_set(mask, 100baseT_Half);
858 phylink_set(mask, 1000baseT_Half);
861 bitmap_and(supported, supported, mac_supported,
862 __ETHTOOL_LINK_MODE_MASK_NBITS);
863 bitmap_andnot(supported, supported, mask,
864 __ETHTOOL_LINK_MODE_MASK_NBITS);
865 bitmap_and(state->advertising, state->advertising, mac_supported,
866 __ETHTOOL_LINK_MODE_MASK_NBITS);
867 bitmap_andnot(state->advertising, state->advertising, mask,
868 __ETHTOOL_LINK_MODE_MASK_NBITS);
871 static void stmmac_mac_pcs_get_state(struct phylink_config *config,
872 struct phylink_link_state *state)
877 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode,
878 const struct phylink_link_state *state)
880 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
883 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
884 ctrl &= ~priv->hw->link.speed_mask;
886 if (state->interface == PHY_INTERFACE_MODE_USXGMII) {
887 switch (state->speed) {
889 ctrl |= priv->hw->link.xgmii.speed10000;
892 ctrl |= priv->hw->link.xgmii.speed5000;
895 ctrl |= priv->hw->link.xgmii.speed2500;
901 switch (state->speed) {
903 ctrl |= priv->hw->link.speed2500;
906 ctrl |= priv->hw->link.speed1000;
909 ctrl |= priv->hw->link.speed100;
912 ctrl |= priv->hw->link.speed10;
919 priv->speed = state->speed;
921 if (priv->plat->fix_mac_speed)
922 priv->plat->fix_mac_speed(priv->plat->bsp_priv, state->speed);
925 ctrl &= ~priv->hw->link.duplex;
927 ctrl |= priv->hw->link.duplex;
929 /* Flow Control operation */
931 stmmac_mac_flow_ctrl(priv, state->duplex);
933 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
936 static void stmmac_mac_an_restart(struct phylink_config *config)
941 static void stmmac_mac_link_down(struct phylink_config *config,
942 unsigned int mode, phy_interface_t interface)
944 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
946 stmmac_mac_set(priv, priv->ioaddr, false);
947 priv->eee_active = false;
948 stmmac_eee_init(priv);
949 stmmac_set_eee_pls(priv, priv->hw, false);
952 static void stmmac_mac_link_up(struct phylink_config *config,
953 unsigned int mode, phy_interface_t interface,
954 struct phy_device *phy)
956 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
958 stmmac_mac_set(priv, priv->ioaddr, true);
959 if (phy && priv->dma_cap.eee) {
960 priv->eee_active = phy_init_eee(phy, 1) >= 0;
961 priv->eee_enabled = stmmac_eee_init(priv);
962 stmmac_set_eee_pls(priv, priv->hw, true);
966 static const struct phylink_mac_ops stmmac_phylink_mac_ops = {
967 .validate = stmmac_validate,
968 .mac_pcs_get_state = stmmac_mac_pcs_get_state,
969 .mac_config = stmmac_mac_config,
970 .mac_an_restart = stmmac_mac_an_restart,
971 .mac_link_down = stmmac_mac_link_down,
972 .mac_link_up = stmmac_mac_link_up,
976 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
977 * @priv: driver private structure
978 * Description: this is to verify if the HW supports the PCS.
979 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
980 * configured for the TBI, RTBI, or SGMII PHY interface.
982 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
984 int interface = priv->plat->interface;
986 if (priv->dma_cap.pcs) {
987 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
988 (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
989 (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
990 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
991 netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
992 priv->hw->pcs = STMMAC_PCS_RGMII;
993 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
994 netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
995 priv->hw->pcs = STMMAC_PCS_SGMII;
1001 * stmmac_init_phy - PHY initialization
1002 * @dev: net device structure
1003 * Description: it initializes the driver's PHY state, and attaches the PHY
1004 * to the mac driver.
1008 static int stmmac_init_phy(struct net_device *dev)
1010 struct stmmac_priv *priv = netdev_priv(dev);
1011 struct device_node *node;
1014 node = priv->plat->phylink_node;
1017 ret = phylink_of_phy_connect(priv->phylink, node, 0);
1019 /* Some DT bindings do not set-up the PHY handle. Let's try to
1023 int addr = priv->plat->phy_addr;
1024 struct phy_device *phydev;
1026 phydev = mdiobus_get_phy(priv->mii, addr);
1028 netdev_err(priv->dev, "no phy at addr %d\n", addr);
1032 ret = phylink_connect_phy(priv->phylink, phydev);
1038 static int stmmac_phy_setup(struct stmmac_priv *priv)
1040 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
1041 int mode = priv->plat->phy_interface;
1042 struct phylink *phylink;
1044 priv->phylink_config.dev = &priv->dev->dev;
1045 priv->phylink_config.type = PHYLINK_NETDEV;
1047 phylink = phylink_create(&priv->phylink_config, fwnode,
1048 mode, &stmmac_phylink_mac_ops);
1049 if (IS_ERR(phylink))
1050 return PTR_ERR(phylink);
1052 priv->phylink = phylink;
1056 static void stmmac_display_rx_rings(struct stmmac_priv *priv)
1058 u32 rx_cnt = priv->plat->rx_queues_to_use;
1062 /* Display RX rings */
1063 for (queue = 0; queue < rx_cnt; queue++) {
1064 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1066 pr_info("\tRX Queue %u rings\n", queue);
1068 if (priv->extend_desc)
1069 head_rx = (void *)rx_q->dma_erx;
1071 head_rx = (void *)rx_q->dma_rx;
1073 /* Display RX ring */
1074 stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true);
1078 static void stmmac_display_tx_rings(struct stmmac_priv *priv)
1080 u32 tx_cnt = priv->plat->tx_queues_to_use;
1084 /* Display TX rings */
1085 for (queue = 0; queue < tx_cnt; queue++) {
1086 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1088 pr_info("\tTX Queue %d rings\n", queue);
1090 if (priv->extend_desc)
1091 head_tx = (void *)tx_q->dma_etx;
1093 head_tx = (void *)tx_q->dma_tx;
1095 stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false);
1099 static void stmmac_display_rings(struct stmmac_priv *priv)
1101 /* Display RX ring */
1102 stmmac_display_rx_rings(priv);
1104 /* Display TX ring */
1105 stmmac_display_tx_rings(priv);
1108 static int stmmac_set_bfsize(int mtu, int bufsize)
1112 if (mtu >= BUF_SIZE_4KiB)
1113 ret = BUF_SIZE_8KiB;
1114 else if (mtu >= BUF_SIZE_2KiB)
1115 ret = BUF_SIZE_4KiB;
1116 else if (mtu > DEFAULT_BUFSIZE)
1117 ret = BUF_SIZE_2KiB;
1119 ret = DEFAULT_BUFSIZE;
1125 * stmmac_clear_rx_descriptors - clear RX descriptors
1126 * @priv: driver private structure
1127 * @queue: RX queue index
1128 * Description: this function is called to clear the RX descriptors
1129 * in case of both basic and extended descriptors are used.
1131 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
1133 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1136 /* Clear the RX descriptors */
1137 for (i = 0; i < DMA_RX_SIZE; i++)
1138 if (priv->extend_desc)
1139 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
1140 priv->use_riwt, priv->mode,
1141 (i == DMA_RX_SIZE - 1),
1144 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
1145 priv->use_riwt, priv->mode,
1146 (i == DMA_RX_SIZE - 1),
1151 * stmmac_clear_tx_descriptors - clear tx descriptors
1152 * @priv: driver private structure
1153 * @queue: TX queue index.
1154 * Description: this function is called to clear the TX descriptors
1155 * in case of both basic and extended descriptors are used.
1157 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
1159 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1162 /* Clear the TX descriptors */
1163 for (i = 0; i < DMA_TX_SIZE; i++)
1164 if (priv->extend_desc)
1165 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1166 priv->mode, (i == DMA_TX_SIZE - 1));
1168 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1169 priv->mode, (i == DMA_TX_SIZE - 1));
1173 * stmmac_clear_descriptors - clear descriptors
1174 * @priv: driver private structure
1175 * Description: this function is called to clear the TX and RX descriptors
1176 * in case of both basic and extended descriptors are used.
1178 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
1180 u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1181 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1184 /* Clear the RX descriptors */
1185 for (queue = 0; queue < rx_queue_cnt; queue++)
1186 stmmac_clear_rx_descriptors(priv, queue);
1188 /* Clear the TX descriptors */
1189 for (queue = 0; queue < tx_queue_cnt; queue++)
1190 stmmac_clear_tx_descriptors(priv, queue);
1194 * stmmac_init_rx_buffers - init the RX descriptor buffer.
1195 * @priv: driver private structure
1196 * @p: descriptor pointer
1197 * @i: descriptor index
1199 * @queue: RX queue index
1200 * Description: this function is called to allocate a receive buffer, perform
1201 * the DMA mapping and init the descriptor.
1203 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
1204 int i, gfp_t flags, u32 queue)
1206 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1207 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1209 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
1214 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool);
1218 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
1219 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr);
1221 buf->sec_page = NULL;
1224 buf->addr = page_pool_get_dma_addr(buf->page);
1225 stmmac_set_desc_addr(priv, p, buf->addr);
1226 if (priv->dma_buf_sz == BUF_SIZE_16KiB)
1227 stmmac_init_desc3(priv, p);
1233 * stmmac_free_rx_buffer - free RX dma buffers
1234 * @priv: private structure
1235 * @queue: RX queue index
1238 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1240 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1241 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1244 page_pool_put_page(rx_q->page_pool, buf->page, false);
1248 page_pool_put_page(rx_q->page_pool, buf->sec_page, false);
1249 buf->sec_page = NULL;
1253 * stmmac_free_tx_buffer - free RX dma buffers
1254 * @priv: private structure
1255 * @queue: RX queue index
1258 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1260 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1262 if (tx_q->tx_skbuff_dma[i].buf) {
1263 if (tx_q->tx_skbuff_dma[i].map_as_page)
1264 dma_unmap_page(priv->device,
1265 tx_q->tx_skbuff_dma[i].buf,
1266 tx_q->tx_skbuff_dma[i].len,
1269 dma_unmap_single(priv->device,
1270 tx_q->tx_skbuff_dma[i].buf,
1271 tx_q->tx_skbuff_dma[i].len,
1275 if (tx_q->tx_skbuff[i]) {
1276 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1277 tx_q->tx_skbuff[i] = NULL;
1278 tx_q->tx_skbuff_dma[i].buf = 0;
1279 tx_q->tx_skbuff_dma[i].map_as_page = false;
1284 * init_dma_rx_desc_rings - init the RX descriptor rings
1285 * @dev: net device structure
1287 * Description: this function initializes the DMA RX descriptors
1288 * and allocates the socket buffers. It supports the chained and ring
1291 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
1293 struct stmmac_priv *priv = netdev_priv(dev);
1294 u32 rx_count = priv->plat->rx_queues_to_use;
1300 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu);
1304 if (bfsize < BUF_SIZE_16KiB)
1305 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1307 priv->dma_buf_sz = bfsize;
1309 /* RX INITIALIZATION */
1310 netif_dbg(priv, probe, priv->dev,
1311 "SKB addresses:\nskb\t\tskb data\tdma data\n");
1313 for (queue = 0; queue < rx_count; queue++) {
1314 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1316 netif_dbg(priv, probe, priv->dev,
1317 "(%s) dma_rx_phy=0x%08x\n", __func__,
1318 (u32)rx_q->dma_rx_phy);
1320 stmmac_clear_rx_descriptors(priv, queue);
1322 for (i = 0; i < DMA_RX_SIZE; i++) {
1325 if (priv->extend_desc)
1326 p = &((rx_q->dma_erx + i)->basic);
1328 p = rx_q->dma_rx + i;
1330 ret = stmmac_init_rx_buffers(priv, p, i, flags,
1333 goto err_init_rx_buffers;
1337 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1339 /* Setup the chained descriptor addresses */
1340 if (priv->mode == STMMAC_CHAIN_MODE) {
1341 if (priv->extend_desc)
1342 stmmac_mode_init(priv, rx_q->dma_erx,
1343 rx_q->dma_rx_phy, DMA_RX_SIZE, 1);
1345 stmmac_mode_init(priv, rx_q->dma_rx,
1346 rx_q->dma_rx_phy, DMA_RX_SIZE, 0);
1354 err_init_rx_buffers:
1355 while (queue >= 0) {
1357 stmmac_free_rx_buffer(priv, queue, i);
1370 * init_dma_tx_desc_rings - init the TX descriptor rings
1371 * @dev: net device structure.
1372 * Description: this function initializes the DMA TX descriptors
1373 * and allocates the socket buffers. It supports the chained and ring
1376 static int init_dma_tx_desc_rings(struct net_device *dev)
1378 struct stmmac_priv *priv = netdev_priv(dev);
1379 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1383 for (queue = 0; queue < tx_queue_cnt; queue++) {
1384 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1386 netif_dbg(priv, probe, priv->dev,
1387 "(%s) dma_tx_phy=0x%08x\n", __func__,
1388 (u32)tx_q->dma_tx_phy);
1390 /* Setup the chained descriptor addresses */
1391 if (priv->mode == STMMAC_CHAIN_MODE) {
1392 if (priv->extend_desc)
1393 stmmac_mode_init(priv, tx_q->dma_etx,
1394 tx_q->dma_tx_phy, DMA_TX_SIZE, 1);
1396 stmmac_mode_init(priv, tx_q->dma_tx,
1397 tx_q->dma_tx_phy, DMA_TX_SIZE, 0);
1400 for (i = 0; i < DMA_TX_SIZE; i++) {
1402 if (priv->extend_desc)
1403 p = &((tx_q->dma_etx + i)->basic);
1405 p = tx_q->dma_tx + i;
1407 stmmac_clear_desc(priv, p);
1409 tx_q->tx_skbuff_dma[i].buf = 0;
1410 tx_q->tx_skbuff_dma[i].map_as_page = false;
1411 tx_q->tx_skbuff_dma[i].len = 0;
1412 tx_q->tx_skbuff_dma[i].last_segment = false;
1413 tx_q->tx_skbuff[i] = NULL;
1420 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
1427 * init_dma_desc_rings - init the RX/TX descriptor rings
1428 * @dev: net device structure
1430 * Description: this function initializes the DMA RX/TX descriptors
1431 * and allocates the socket buffers. It supports the chained and ring
1434 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1436 struct stmmac_priv *priv = netdev_priv(dev);
1439 ret = init_dma_rx_desc_rings(dev, flags);
1443 ret = init_dma_tx_desc_rings(dev);
1445 stmmac_clear_descriptors(priv);
1447 if (netif_msg_hw(priv))
1448 stmmac_display_rings(priv);
1454 * dma_free_rx_skbufs - free RX dma buffers
1455 * @priv: private structure
1456 * @queue: RX queue index
1458 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)
1462 for (i = 0; i < DMA_RX_SIZE; i++)
1463 stmmac_free_rx_buffer(priv, queue, i);
1467 * dma_free_tx_skbufs - free TX dma buffers
1468 * @priv: private structure
1469 * @queue: TX queue index
1471 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
1475 for (i = 0; i < DMA_TX_SIZE; i++)
1476 stmmac_free_tx_buffer(priv, queue, i);
1480 * free_dma_rx_desc_resources - free RX dma desc resources
1481 * @priv: private structure
1483 static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
1485 u32 rx_count = priv->plat->rx_queues_to_use;
1488 /* Free RX queue resources */
1489 for (queue = 0; queue < rx_count; queue++) {
1490 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1492 /* Release the DMA RX socket buffers */
1493 dma_free_rx_skbufs(priv, queue);
1495 /* Free DMA regions of consistent memory previously allocated */
1496 if (!priv->extend_desc)
1497 dma_free_coherent(priv->device,
1498 DMA_RX_SIZE * sizeof(struct dma_desc),
1499 rx_q->dma_rx, rx_q->dma_rx_phy);
1501 dma_free_coherent(priv->device, DMA_RX_SIZE *
1502 sizeof(struct dma_extended_desc),
1503 rx_q->dma_erx, rx_q->dma_rx_phy);
1505 kfree(rx_q->buf_pool);
1506 if (rx_q->page_pool)
1507 page_pool_destroy(rx_q->page_pool);
1512 * free_dma_tx_desc_resources - free TX dma desc resources
1513 * @priv: private structure
1515 static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
1517 u32 tx_count = priv->plat->tx_queues_to_use;
1520 /* Free TX queue resources */
1521 for (queue = 0; queue < tx_count; queue++) {
1522 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1524 /* Release the DMA TX socket buffers */
1525 dma_free_tx_skbufs(priv, queue);
1527 /* Free DMA regions of consistent memory previously allocated */
1528 if (!priv->extend_desc)
1529 dma_free_coherent(priv->device,
1530 DMA_TX_SIZE * sizeof(struct dma_desc),
1531 tx_q->dma_tx, tx_q->dma_tx_phy);
1533 dma_free_coherent(priv->device, DMA_TX_SIZE *
1534 sizeof(struct dma_extended_desc),
1535 tx_q->dma_etx, tx_q->dma_tx_phy);
1537 kfree(tx_q->tx_skbuff_dma);
1538 kfree(tx_q->tx_skbuff);
1543 * alloc_dma_rx_desc_resources - alloc RX resources.
1544 * @priv: private structure
1545 * Description: according to which descriptor can be used (extend or basic)
1546 * this function allocates the resources for TX and RX paths. In case of
1547 * reception, for example, it pre-allocated the RX socket buffer in order to
1548 * allow zero-copy mechanism.
1550 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
1552 u32 rx_count = priv->plat->rx_queues_to_use;
1556 /* RX queues buffers and DMA */
1557 for (queue = 0; queue < rx_count; queue++) {
1558 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1559 struct page_pool_params pp_params = { 0 };
1560 unsigned int num_pages;
1562 rx_q->queue_index = queue;
1563 rx_q->priv_data = priv;
1565 pp_params.flags = PP_FLAG_DMA_MAP;
1566 pp_params.pool_size = DMA_RX_SIZE;
1567 num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE);
1568 pp_params.order = ilog2(num_pages);
1569 pp_params.nid = dev_to_node(priv->device);
1570 pp_params.dev = priv->device;
1571 pp_params.dma_dir = DMA_FROM_DEVICE;
1573 rx_q->page_pool = page_pool_create(&pp_params);
1574 if (IS_ERR(rx_q->page_pool)) {
1575 ret = PTR_ERR(rx_q->page_pool);
1576 rx_q->page_pool = NULL;
1580 rx_q->buf_pool = kcalloc(DMA_RX_SIZE, sizeof(*rx_q->buf_pool),
1582 if (!rx_q->buf_pool)
1585 if (priv->extend_desc) {
1586 rx_q->dma_erx = dma_alloc_coherent(priv->device,
1587 DMA_RX_SIZE * sizeof(struct dma_extended_desc),
1594 rx_q->dma_rx = dma_alloc_coherent(priv->device,
1595 DMA_RX_SIZE * sizeof(struct dma_desc),
1606 free_dma_rx_desc_resources(priv);
1612 * alloc_dma_tx_desc_resources - alloc TX resources.
1613 * @priv: private structure
1614 * Description: according to which descriptor can be used (extend or basic)
1615 * this function allocates the resources for TX and RX paths. In case of
1616 * reception, for example, it pre-allocated the RX socket buffer in order to
1617 * allow zero-copy mechanism.
1619 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
1621 u32 tx_count = priv->plat->tx_queues_to_use;
1625 /* TX queues buffers and DMA */
1626 for (queue = 0; queue < tx_count; queue++) {
1627 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1629 tx_q->queue_index = queue;
1630 tx_q->priv_data = priv;
1632 tx_q->tx_skbuff_dma = kcalloc(DMA_TX_SIZE,
1633 sizeof(*tx_q->tx_skbuff_dma),
1635 if (!tx_q->tx_skbuff_dma)
1638 tx_q->tx_skbuff = kcalloc(DMA_TX_SIZE,
1639 sizeof(struct sk_buff *),
1641 if (!tx_q->tx_skbuff)
1644 if (priv->extend_desc) {
1645 tx_q->dma_etx = dma_alloc_coherent(priv->device,
1646 DMA_TX_SIZE * sizeof(struct dma_extended_desc),
1652 tx_q->dma_tx = dma_alloc_coherent(priv->device,
1653 DMA_TX_SIZE * sizeof(struct dma_desc),
1664 free_dma_tx_desc_resources(priv);
1670 * alloc_dma_desc_resources - alloc TX/RX resources.
1671 * @priv: private structure
1672 * Description: according to which descriptor can be used (extend or basic)
1673 * this function allocates the resources for TX and RX paths. In case of
1674 * reception, for example, it pre-allocated the RX socket buffer in order to
1675 * allow zero-copy mechanism.
1677 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1680 int ret = alloc_dma_rx_desc_resources(priv);
1685 ret = alloc_dma_tx_desc_resources(priv);
1691 * free_dma_desc_resources - free dma desc resources
1692 * @priv: private structure
1694 static void free_dma_desc_resources(struct stmmac_priv *priv)
1696 /* Release the DMA RX socket buffers */
1697 free_dma_rx_desc_resources(priv);
1699 /* Release the DMA TX socket buffers */
1700 free_dma_tx_desc_resources(priv);
1704 * stmmac_mac_enable_rx_queues - Enable MAC rx queues
1705 * @priv: driver private structure
1706 * Description: It is used for enabling the rx queues in the MAC
1708 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
1710 u32 rx_queues_count = priv->plat->rx_queues_to_use;
1714 for (queue = 0; queue < rx_queues_count; queue++) {
1715 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
1716 stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
1721 * stmmac_start_rx_dma - start RX DMA channel
1722 * @priv: driver private structure
1723 * @chan: RX channel index
1725 * This starts a RX DMA channel
1727 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
1729 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
1730 stmmac_start_rx(priv, priv->ioaddr, chan);
1734 * stmmac_start_tx_dma - start TX DMA channel
1735 * @priv: driver private structure
1736 * @chan: TX channel index
1738 * This starts a TX DMA channel
1740 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
1742 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
1743 stmmac_start_tx(priv, priv->ioaddr, chan);
1747 * stmmac_stop_rx_dma - stop RX DMA channel
1748 * @priv: driver private structure
1749 * @chan: RX channel index
1751 * This stops a RX DMA channel
1753 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
1755 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
1756 stmmac_stop_rx(priv, priv->ioaddr, chan);
1760 * stmmac_stop_tx_dma - stop TX DMA channel
1761 * @priv: driver private structure
1762 * @chan: TX channel index
1764 * This stops a TX DMA channel
1766 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
1768 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
1769 stmmac_stop_tx(priv, priv->ioaddr, chan);
1773 * stmmac_start_all_dma - start all RX and TX DMA channels
1774 * @priv: driver private structure
1776 * This starts all the RX and TX DMA channels
1778 static void stmmac_start_all_dma(struct stmmac_priv *priv)
1780 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1781 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1784 for (chan = 0; chan < rx_channels_count; chan++)
1785 stmmac_start_rx_dma(priv, chan);
1787 for (chan = 0; chan < tx_channels_count; chan++)
1788 stmmac_start_tx_dma(priv, chan);
1792 * stmmac_stop_all_dma - stop all RX and TX DMA channels
1793 * @priv: driver private structure
1795 * This stops the RX and TX DMA channels
1797 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
1799 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1800 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1803 for (chan = 0; chan < rx_channels_count; chan++)
1804 stmmac_stop_rx_dma(priv, chan);
1806 for (chan = 0; chan < tx_channels_count; chan++)
1807 stmmac_stop_tx_dma(priv, chan);
1811 * stmmac_dma_operation_mode - HW DMA operation mode
1812 * @priv: driver private structure
1813 * Description: it is used for configuring the DMA operation mode register in
1814 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1816 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1818 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1819 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1820 int rxfifosz = priv->plat->rx_fifo_size;
1821 int txfifosz = priv->plat->tx_fifo_size;
1828 rxfifosz = priv->dma_cap.rx_fifo_size;
1830 txfifosz = priv->dma_cap.tx_fifo_size;
1832 /* Adjust for real per queue fifo size */
1833 rxfifosz /= rx_channels_count;
1834 txfifosz /= tx_channels_count;
1836 if (priv->plat->force_thresh_dma_mode) {
1839 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1841 * In case of GMAC, SF mode can be enabled
1842 * to perform the TX COE in HW. This depends on:
1843 * 1) TX COE if actually supported
1844 * 2) There is no bugged Jumbo frame support
1845 * that needs to not insert csum in the TDES.
1847 txmode = SF_DMA_MODE;
1848 rxmode = SF_DMA_MODE;
1849 priv->xstats.threshold = SF_DMA_MODE;
1852 rxmode = SF_DMA_MODE;
1855 /* configure all channels */
1856 for (chan = 0; chan < rx_channels_count; chan++) {
1857 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
1859 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
1861 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz,
1865 for (chan = 0; chan < tx_channels_count; chan++) {
1866 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
1868 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
1874 * stmmac_tx_clean - to manage the transmission completion
1875 * @priv: driver private structure
1876 * @queue: TX queue index
1877 * Description: it reclaims the transmit resources after transmission completes.
1879 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
1881 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1882 unsigned int bytes_compl = 0, pkts_compl = 0;
1883 unsigned int entry, count = 0;
1885 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue));
1887 priv->xstats.tx_clean++;
1889 entry = tx_q->dirty_tx;
1890 while ((entry != tx_q->cur_tx) && (count < budget)) {
1891 struct sk_buff *skb = tx_q->tx_skbuff[entry];
1895 if (priv->extend_desc)
1896 p = (struct dma_desc *)(tx_q->dma_etx + entry);
1898 p = tx_q->dma_tx + entry;
1900 status = stmmac_tx_status(priv, &priv->dev->stats,
1901 &priv->xstats, p, priv->ioaddr);
1902 /* Check if the descriptor is owned by the DMA */
1903 if (unlikely(status & tx_dma_own))
1908 /* Make sure descriptor fields are read after reading
1913 /* Just consider the last segment and ...*/
1914 if (likely(!(status & tx_not_ls))) {
1915 /* ... verify the status error condition */
1916 if (unlikely(status & tx_err)) {
1917 priv->dev->stats.tx_errors++;
1919 priv->dev->stats.tx_packets++;
1920 priv->xstats.tx_pkt_n++;
1922 stmmac_get_tx_hwtstamp(priv, p, skb);
1925 if (likely(tx_q->tx_skbuff_dma[entry].buf)) {
1926 if (tx_q->tx_skbuff_dma[entry].map_as_page)
1927 dma_unmap_page(priv->device,
1928 tx_q->tx_skbuff_dma[entry].buf,
1929 tx_q->tx_skbuff_dma[entry].len,
1932 dma_unmap_single(priv->device,
1933 tx_q->tx_skbuff_dma[entry].buf,
1934 tx_q->tx_skbuff_dma[entry].len,
1936 tx_q->tx_skbuff_dma[entry].buf = 0;
1937 tx_q->tx_skbuff_dma[entry].len = 0;
1938 tx_q->tx_skbuff_dma[entry].map_as_page = false;
1941 stmmac_clean_desc3(priv, tx_q, p);
1943 tx_q->tx_skbuff_dma[entry].last_segment = false;
1944 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
1946 if (likely(skb != NULL)) {
1948 bytes_compl += skb->len;
1949 dev_consume_skb_any(skb);
1950 tx_q->tx_skbuff[entry] = NULL;
1953 stmmac_release_tx_desc(priv, p, priv->mode);
1955 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1957 tx_q->dirty_tx = entry;
1959 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
1960 pkts_compl, bytes_compl);
1962 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
1964 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) {
1966 netif_dbg(priv, tx_done, priv->dev,
1967 "%s: restart transmit\n", __func__);
1968 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
1971 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1972 stmmac_enable_eee_mode(priv);
1973 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1976 /* We still have pending packets, let's call for a new scheduling */
1977 if (tx_q->dirty_tx != tx_q->cur_tx)
1978 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
1980 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
1986 * stmmac_tx_err - to manage the tx error
1987 * @priv: driver private structure
1988 * @chan: channel index
1989 * Description: it cleans the descriptors and restarts the transmission
1990 * in case of transmission errors.
1992 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
1994 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
1997 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
1999 stmmac_stop_tx_dma(priv, chan);
2000 dma_free_tx_skbufs(priv, chan);
2001 for (i = 0; i < DMA_TX_SIZE; i++)
2002 if (priv->extend_desc)
2003 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
2004 priv->mode, (i == DMA_TX_SIZE - 1));
2006 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
2007 priv->mode, (i == DMA_TX_SIZE - 1));
2011 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
2012 stmmac_start_tx_dma(priv, chan);
2014 priv->dev->stats.tx_errors++;
2015 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
2019 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel
2020 * @priv: driver private structure
2021 * @txmode: TX operating mode
2022 * @rxmode: RX operating mode
2023 * @chan: channel index
2024 * Description: it is used for configuring of the DMA operation mode in
2025 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
2028 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
2029 u32 rxmode, u32 chan)
2031 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2032 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2033 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2034 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2035 int rxfifosz = priv->plat->rx_fifo_size;
2036 int txfifosz = priv->plat->tx_fifo_size;
2039 rxfifosz = priv->dma_cap.rx_fifo_size;
2041 txfifosz = priv->dma_cap.tx_fifo_size;
2043 /* Adjust for real per queue fifo size */
2044 rxfifosz /= rx_channels_count;
2045 txfifosz /= tx_channels_count;
2047 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode);
2048 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode);
2051 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
2055 ret = stmmac_safety_feat_irq_status(priv, priv->dev,
2056 priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
2057 if (ret && (ret != -EINVAL)) {
2058 stmmac_global_err(priv);
2065 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan)
2067 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
2068 &priv->xstats, chan);
2069 struct stmmac_channel *ch = &priv->channel[chan];
2071 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
2072 if (napi_schedule_prep(&ch->rx_napi)) {
2073 stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
2074 __napi_schedule_irqoff(&ch->rx_napi);
2075 status |= handle_tx;
2079 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use))
2080 napi_schedule_irqoff(&ch->tx_napi);
2086 * stmmac_dma_interrupt - DMA ISR
2087 * @priv: driver private structure
2088 * Description: this is the DMA ISR. It is called by the main ISR.
2089 * It calls the dwmac dma routine and schedule poll method in case of some
2092 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
2094 u32 tx_channel_count = priv->plat->tx_queues_to_use;
2095 u32 rx_channel_count = priv->plat->rx_queues_to_use;
2096 u32 channels_to_check = tx_channel_count > rx_channel_count ?
2097 tx_channel_count : rx_channel_count;
2099 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
2101 /* Make sure we never check beyond our status buffer. */
2102 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
2103 channels_to_check = ARRAY_SIZE(status);
2105 for (chan = 0; chan < channels_to_check; chan++)
2106 status[chan] = stmmac_napi_check(priv, chan);
2108 for (chan = 0; chan < tx_channel_count; chan++) {
2109 if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
2110 /* Try to bump up the dma threshold on this failure */
2111 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
2114 if (priv->plat->force_thresh_dma_mode)
2115 stmmac_set_dma_operation_mode(priv,
2120 stmmac_set_dma_operation_mode(priv,
2124 priv->xstats.threshold = tc;
2126 } else if (unlikely(status[chan] == tx_hard_error)) {
2127 stmmac_tx_err(priv, chan);
2133 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2134 * @priv: driver private structure
2135 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2137 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2139 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2140 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2142 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr);
2144 if (priv->dma_cap.rmon) {
2145 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode);
2146 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2148 netdev_info(priv->dev, "No MAC Management Counters available\n");
2152 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2153 * @priv: driver private structure
2155 * new GMAC chip generations have a new register to indicate the
2156 * presence of the optional feature/functions.
2157 * This can be also used to override the value passed through the
2158 * platform and necessary for old MAC10/100 and GMAC chips.
2160 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2162 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
2166 * stmmac_check_ether_addr - check if the MAC addr is valid
2167 * @priv: driver private structure
2169 * it is to verify if the MAC address is valid, in case of failures it
2170 * generates a random MAC address
2172 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2174 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2175 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0);
2176 if (!is_valid_ether_addr(priv->dev->dev_addr))
2177 eth_hw_addr_random(priv->dev);
2178 dev_info(priv->device, "device MAC address %pM\n",
2179 priv->dev->dev_addr);
2184 * stmmac_init_dma_engine - DMA init.
2185 * @priv: driver private structure
2187 * It inits the DMA invoking the specific MAC/GMAC callback.
2188 * Some DMA parameters can be passed from the platform;
2189 * in case of these are not passed a default is kept for the MAC or GMAC.
2191 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2193 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2194 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2195 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2196 struct stmmac_rx_queue *rx_q;
2197 struct stmmac_tx_queue *tx_q;
2202 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2203 dev_err(priv->device, "Invalid DMA configuration\n");
2207 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2210 ret = stmmac_reset(priv, priv->ioaddr);
2212 dev_err(priv->device, "Failed to reset the dma\n");
2216 /* DMA Configuration */
2217 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);
2219 if (priv->plat->axi)
2220 stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
2222 /* DMA CSR Channel configuration */
2223 for (chan = 0; chan < dma_csr_ch; chan++)
2224 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
2226 /* DMA RX Channel Configuration */
2227 for (chan = 0; chan < rx_channels_count; chan++) {
2228 rx_q = &priv->rx_queue[chan];
2230 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2231 rx_q->dma_rx_phy, chan);
2233 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2234 (DMA_RX_SIZE * sizeof(struct dma_desc));
2235 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
2236 rx_q->rx_tail_addr, chan);
2239 /* DMA TX Channel Configuration */
2240 for (chan = 0; chan < tx_channels_count; chan++) {
2241 tx_q = &priv->tx_queue[chan];
2243 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2244 tx_q->dma_tx_phy, chan);
2246 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
2247 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
2248 tx_q->tx_tail_addr, chan);
2254 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
2256 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2258 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer));
2262 * stmmac_tx_timer - mitigation sw timer for tx.
2263 * @data: data pointer
2265 * This is the timer handler to directly invoke the stmmac_tx_clean.
2267 static void stmmac_tx_timer(struct timer_list *t)
2269 struct stmmac_tx_queue *tx_q = from_timer(tx_q, t, txtimer);
2270 struct stmmac_priv *priv = tx_q->priv_data;
2271 struct stmmac_channel *ch;
2273 ch = &priv->channel[tx_q->queue_index];
2276 * If NAPI is already running we can miss some events. Let's rearm
2277 * the timer and try again.
2279 if (likely(napi_schedule_prep(&ch->tx_napi)))
2280 __napi_schedule(&ch->tx_napi);
2282 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
2286 * stmmac_init_coalesce - init mitigation options.
2287 * @priv: driver private structure
2289 * This inits the coalesce parameters: i.e. timer rate,
2290 * timer handler and default threshold used for enabling the
2291 * interrupt on completion bit.
2293 static void stmmac_init_coalesce(struct stmmac_priv *priv)
2295 u32 tx_channel_count = priv->plat->tx_queues_to_use;
2298 priv->tx_coal_frames = STMMAC_TX_FRAMES;
2299 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
2300 priv->rx_coal_frames = STMMAC_RX_FRAMES;
2302 for (chan = 0; chan < tx_channel_count; chan++) {
2303 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2305 timer_setup(&tx_q->txtimer, stmmac_tx_timer, 0);
2309 static void stmmac_set_rings_length(struct stmmac_priv *priv)
2311 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2312 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2315 /* set TX ring length */
2316 for (chan = 0; chan < tx_channels_count; chan++)
2317 stmmac_set_tx_ring_len(priv, priv->ioaddr,
2318 (DMA_TX_SIZE - 1), chan);
2320 /* set RX ring length */
2321 for (chan = 0; chan < rx_channels_count; chan++)
2322 stmmac_set_rx_ring_len(priv, priv->ioaddr,
2323 (DMA_RX_SIZE - 1), chan);
2327 * stmmac_set_tx_queue_weight - Set TX queue weight
2328 * @priv: driver private structure
2329 * Description: It is used for setting TX queues weight
2331 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
2333 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2337 for (queue = 0; queue < tx_queues_count; queue++) {
2338 weight = priv->plat->tx_queues_cfg[queue].weight;
2339 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue);
2344 * stmmac_configure_cbs - Configure CBS in TX queue
2345 * @priv: driver private structure
2346 * Description: It is used for configuring CBS in AVB TX queues
2348 static void stmmac_configure_cbs(struct stmmac_priv *priv)
2350 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2354 /* queue 0 is reserved for legacy traffic */
2355 for (queue = 1; queue < tx_queues_count; queue++) {
2356 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
2357 if (mode_to_use == MTL_QUEUE_DCB)
2360 stmmac_config_cbs(priv, priv->hw,
2361 priv->plat->tx_queues_cfg[queue].send_slope,
2362 priv->plat->tx_queues_cfg[queue].idle_slope,
2363 priv->plat->tx_queues_cfg[queue].high_credit,
2364 priv->plat->tx_queues_cfg[queue].low_credit,
2370 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
2371 * @priv: driver private structure
2372 * Description: It is used for mapping RX queues to RX dma channels
2374 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
2376 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2380 for (queue = 0; queue < rx_queues_count; queue++) {
2381 chan = priv->plat->rx_queues_cfg[queue].chan;
2382 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
2387 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
2388 * @priv: driver private structure
2389 * Description: It is used for configuring the RX Queue Priority
2391 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
2393 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2397 for (queue = 0; queue < rx_queues_count; queue++) {
2398 if (!priv->plat->rx_queues_cfg[queue].use_prio)
2401 prio = priv->plat->rx_queues_cfg[queue].prio;
2402 stmmac_rx_queue_prio(priv, priv->hw, prio, queue);
2407 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
2408 * @priv: driver private structure
2409 * Description: It is used for configuring the TX Queue Priority
2411 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
2413 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2417 for (queue = 0; queue < tx_queues_count; queue++) {
2418 if (!priv->plat->tx_queues_cfg[queue].use_prio)
2421 prio = priv->plat->tx_queues_cfg[queue].prio;
2422 stmmac_tx_queue_prio(priv, priv->hw, prio, queue);
2427 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
2428 * @priv: driver private structure
2429 * Description: It is used for configuring the RX queue routing
2431 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
2433 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2437 for (queue = 0; queue < rx_queues_count; queue++) {
2438 /* no specific packet type routing specified for the queue */
2439 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
2442 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
2443 stmmac_rx_queue_routing(priv, priv->hw, packet, queue);
2447 static void stmmac_mac_config_rss(struct stmmac_priv *priv)
2449 if (!priv->dma_cap.rssen || !priv->plat->rss_en) {
2450 priv->rss.enable = false;
2454 if (priv->dev->features & NETIF_F_RXHASH)
2455 priv->rss.enable = true;
2457 priv->rss.enable = false;
2459 stmmac_rss_configure(priv, priv->hw, &priv->rss,
2460 priv->plat->rx_queues_to_use);
2464 * stmmac_mtl_configuration - Configure MTL
2465 * @priv: driver private structure
2466 * Description: It is used for configurring MTL
2468 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
2470 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2471 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2473 if (tx_queues_count > 1)
2474 stmmac_set_tx_queue_weight(priv);
2476 /* Configure MTL RX algorithms */
2477 if (rx_queues_count > 1)
2478 stmmac_prog_mtl_rx_algorithms(priv, priv->hw,
2479 priv->plat->rx_sched_algorithm);
2481 /* Configure MTL TX algorithms */
2482 if (tx_queues_count > 1)
2483 stmmac_prog_mtl_tx_algorithms(priv, priv->hw,
2484 priv->plat->tx_sched_algorithm);
2486 /* Configure CBS in AVB TX queues */
2487 if (tx_queues_count > 1)
2488 stmmac_configure_cbs(priv);
2490 /* Map RX MTL to DMA channels */
2491 stmmac_rx_queue_dma_chan_map(priv);
2493 /* Enable MAC RX Queues */
2494 stmmac_mac_enable_rx_queues(priv);
2496 /* Set RX priorities */
2497 if (rx_queues_count > 1)
2498 stmmac_mac_config_rx_queues_prio(priv);
2500 /* Set TX priorities */
2501 if (tx_queues_count > 1)
2502 stmmac_mac_config_tx_queues_prio(priv);
2504 /* Set RX routing */
2505 if (rx_queues_count > 1)
2506 stmmac_mac_config_rx_queues_routing(priv);
2508 /* Receive Side Scaling */
2509 if (rx_queues_count > 1)
2510 stmmac_mac_config_rss(priv);
2513 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
2515 if (priv->dma_cap.asp) {
2516 netdev_info(priv->dev, "Enabling Safety Features\n");
2517 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp);
2519 netdev_info(priv->dev, "No Safety Features support found\n");
2524 * stmmac_hw_setup - setup mac in a usable state.
2525 * @dev : pointer to the device structure.
2527 * this is the main function to setup the HW in a usable state because the
2528 * dma engine is reset, the core registers are configured (e.g. AXI,
2529 * Checksum features, timers). The DMA is ready to start receiving and
2532 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2535 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
2537 struct stmmac_priv *priv = netdev_priv(dev);
2538 u32 rx_cnt = priv->plat->rx_queues_to_use;
2539 u32 tx_cnt = priv->plat->tx_queues_to_use;
2543 /* DMA initialization and SW reset */
2544 ret = stmmac_init_dma_engine(priv);
2546 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
2551 /* Copy the MAC addr into the HW */
2552 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
2554 /* PS and related bits will be programmed according to the speed */
2555 if (priv->hw->pcs) {
2556 int speed = priv->plat->mac_port_sel_speed;
2558 if ((speed == SPEED_10) || (speed == SPEED_100) ||
2559 (speed == SPEED_1000)) {
2560 priv->hw->ps = speed;
2562 dev_warn(priv->device, "invalid port speed\n");
2567 /* Initialize the MAC Core */
2568 stmmac_core_init(priv, priv->hw, dev);
2571 stmmac_mtl_configuration(priv);
2573 /* Initialize Safety Features */
2574 stmmac_safety_feat_configuration(priv);
2576 ret = stmmac_rx_ipc(priv, priv->hw);
2578 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
2579 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2580 priv->hw->rx_csum = 0;
2583 /* Enable the MAC Rx/Tx */
2584 stmmac_mac_set(priv, priv->ioaddr, true);
2586 /* Set the HW DMA mode and the COE */
2587 stmmac_dma_operation_mode(priv);
2589 stmmac_mmc_setup(priv);
2592 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
2594 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret);
2596 ret = stmmac_init_ptp(priv);
2597 if (ret == -EOPNOTSUPP)
2598 netdev_warn(priv->dev, "PTP not supported by HW\n");
2600 netdev_warn(priv->dev, "PTP init failed\n");
2603 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
2605 if (priv->use_riwt) {
2607 priv->rx_riwt = DEF_DMA_RIWT;
2609 ret = stmmac_rx_watchdog(priv, priv->ioaddr, priv->rx_riwt, rx_cnt);
2613 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0);
2615 /* set TX and RX rings length */
2616 stmmac_set_rings_length(priv);
2620 for (chan = 0; chan < tx_cnt; chan++)
2621 stmmac_enable_tso(priv, priv->ioaddr, 1, chan);
2624 /* Enable Split Header */
2625 if (priv->sph && priv->hw->rx_csum) {
2626 for (chan = 0; chan < rx_cnt; chan++)
2627 stmmac_enable_sph(priv, priv->ioaddr, 1, chan);
2630 /* VLAN Tag Insertion */
2631 if (priv->dma_cap.vlins)
2632 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT);
2634 /* Start the ball rolling... */
2635 stmmac_start_all_dma(priv);
2640 static void stmmac_hw_teardown(struct net_device *dev)
2642 struct stmmac_priv *priv = netdev_priv(dev);
2644 clk_disable_unprepare(priv->plat->clk_ptp_ref);
2648 * stmmac_open - open entry point of the driver
2649 * @dev : pointer to the device structure.
2651 * This function is the open entry point of the driver.
2653 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2656 static int stmmac_open(struct net_device *dev)
2658 struct stmmac_priv *priv = netdev_priv(dev);
2662 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
2663 priv->hw->pcs != STMMAC_PCS_TBI &&
2664 priv->hw->pcs != STMMAC_PCS_RTBI) {
2665 ret = stmmac_init_phy(dev);
2667 netdev_err(priv->dev,
2668 "%s: Cannot attach to PHY (error: %d)\n",
2674 /* Extra statistics */
2675 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
2676 priv->xstats.threshold = tc;
2678 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
2679 priv->rx_copybreak = STMMAC_RX_COPYBREAK;
2681 ret = alloc_dma_desc_resources(priv);
2683 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
2685 goto dma_desc_error;
2688 ret = init_dma_desc_rings(dev, GFP_KERNEL);
2690 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
2695 ret = stmmac_hw_setup(dev, true);
2697 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
2701 stmmac_init_coalesce(priv);
2703 phylink_start(priv->phylink);
2705 /* Request the IRQ lines */
2706 ret = request_irq(dev->irq, stmmac_interrupt,
2707 IRQF_SHARED, dev->name, dev);
2708 if (unlikely(ret < 0)) {
2709 netdev_err(priv->dev,
2710 "%s: ERROR: allocating the IRQ %d (error: %d)\n",
2711 __func__, dev->irq, ret);
2715 /* Request the Wake IRQ in case of another line is used for WoL */
2716 if (priv->wol_irq != dev->irq) {
2717 ret = request_irq(priv->wol_irq, stmmac_interrupt,
2718 IRQF_SHARED, dev->name, dev);
2719 if (unlikely(ret < 0)) {
2720 netdev_err(priv->dev,
2721 "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
2722 __func__, priv->wol_irq, ret);
2727 /* Request the IRQ lines */
2728 if (priv->lpi_irq > 0) {
2729 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
2731 if (unlikely(ret < 0)) {
2732 netdev_err(priv->dev,
2733 "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
2734 __func__, priv->lpi_irq, ret);
2739 stmmac_enable_all_queues(priv);
2740 stmmac_start_all_queues(priv);
2745 if (priv->wol_irq != dev->irq)
2746 free_irq(priv->wol_irq, dev);
2748 free_irq(dev->irq, dev);
2750 phylink_stop(priv->phylink);
2752 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2753 del_timer_sync(&priv->tx_queue[chan].txtimer);
2755 stmmac_hw_teardown(dev);
2757 free_dma_desc_resources(priv);
2759 phylink_disconnect_phy(priv->phylink);
2764 * stmmac_release - close entry point of the driver
2765 * @dev : device pointer.
2767 * This is the stop entry point of the driver.
2769 static int stmmac_release(struct net_device *dev)
2771 struct stmmac_priv *priv = netdev_priv(dev);
2774 if (priv->eee_enabled)
2775 del_timer_sync(&priv->eee_ctrl_timer);
2777 /* Stop and disconnect the PHY */
2778 phylink_stop(priv->phylink);
2779 phylink_disconnect_phy(priv->phylink);
2781 stmmac_stop_all_queues(priv);
2783 stmmac_disable_all_queues(priv);
2785 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2786 del_timer_sync(&priv->tx_queue[chan].txtimer);
2788 /* Free the IRQ lines */
2789 free_irq(dev->irq, dev);
2790 if (priv->wol_irq != dev->irq)
2791 free_irq(priv->wol_irq, dev);
2792 if (priv->lpi_irq > 0)
2793 free_irq(priv->lpi_irq, dev);
2795 /* Stop TX/RX DMA and clear the descriptors */
2796 stmmac_stop_all_dma(priv);
2798 /* Release and free the Rx/Tx resources */
2799 free_dma_desc_resources(priv);
2801 /* Disable the MAC Rx/Tx */
2802 stmmac_mac_set(priv, priv->ioaddr, false);
2804 netif_carrier_off(dev);
2806 stmmac_release_ptp(priv);
2811 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb,
2812 struct stmmac_tx_queue *tx_q)
2814 u16 tag = 0x0, inner_tag = 0x0;
2815 u32 inner_type = 0x0;
2818 if (!priv->dma_cap.vlins)
2820 if (!skb_vlan_tag_present(skb))
2822 if (skb->vlan_proto == htons(ETH_P_8021AD)) {
2823 inner_tag = skb_vlan_tag_get(skb);
2824 inner_type = STMMAC_VLAN_INSERT;
2827 tag = skb_vlan_tag_get(skb);
2829 p = tx_q->dma_tx + tx_q->cur_tx;
2830 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type))
2833 stmmac_set_tx_owner(priv, p);
2834 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2839 * stmmac_tso_allocator - close entry point of the driver
2840 * @priv: driver private structure
2841 * @des: buffer start address
2842 * @total_len: total length to fill in descriptors
2843 * @last_segmant: condition for the last descriptor
2844 * @queue: TX queue index
2846 * This function fills descriptor and request new descriptors according to
2847 * buffer length to fill
2849 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des,
2850 int total_len, bool last_segment, u32 queue)
2852 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2853 struct dma_desc *desc;
2857 tmp_len = total_len;
2859 while (tmp_len > 0) {
2860 dma_addr_t curr_addr;
2862 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2863 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2864 desc = tx_q->dma_tx + tx_q->cur_tx;
2866 curr_addr = des + (total_len - tmp_len);
2867 if (priv->dma_cap.addr64 <= 32)
2868 desc->des0 = cpu_to_le32(curr_addr);
2870 stmmac_set_desc_addr(priv, desc, curr_addr);
2872 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
2873 TSO_MAX_BUFF_SIZE : tmp_len;
2875 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size,
2877 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
2880 tmp_len -= TSO_MAX_BUFF_SIZE;
2885 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
2886 * @skb : the socket buffer
2887 * @dev : device pointer
2888 * Description: this is the transmit function that is called on TSO frames
2889 * (support available on GMAC4 and newer chips).
2890 * Diagram below show the ring programming in case of TSO frames:
2894 * | DES0 |---> buffer1 = L2/L3/L4 header
2895 * | DES1 |---> TCP Payload (can continue on next descr...)
2896 * | DES2 |---> buffer 1 and 2 len
2897 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
2903 * | DES0 | --| Split TCP Payload on Buffers 1 and 2
2905 * | DES2 | --> buffer 1 and 2 len
2909 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
2911 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
2913 struct dma_desc *desc, *first, *mss_desc = NULL;
2914 struct stmmac_priv *priv = netdev_priv(dev);
2915 int nfrags = skb_shinfo(skb)->nr_frags;
2916 u32 queue = skb_get_queue_mapping(skb);
2917 unsigned int first_entry, tx_packets;
2918 int tmp_pay_len = 0, first_tx;
2919 struct stmmac_tx_queue *tx_q;
2920 u8 proto_hdr_len, hdr;
2921 bool has_vlan, set_ic;
2926 tx_q = &priv->tx_queue[queue];
2927 first_tx = tx_q->cur_tx;
2929 /* Compute header lengths */
2930 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
2931 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr);
2932 hdr = sizeof(struct udphdr);
2934 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2935 hdr = tcp_hdrlen(skb);
2938 /* Desc availability based on threshold should be enough safe */
2939 if (unlikely(stmmac_tx_avail(priv, queue) <
2940 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
2941 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
2942 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
2944 /* This is a hard error, log it. */
2945 netdev_err(priv->dev,
2946 "%s: Tx Ring full when queue awake\n",
2949 return NETDEV_TX_BUSY;
2952 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
2954 mss = skb_shinfo(skb)->gso_size;
2956 /* set new MSS value if needed */
2957 if (mss != tx_q->mss) {
2958 mss_desc = tx_q->dma_tx + tx_q->cur_tx;
2959 stmmac_set_mss(priv, mss_desc, mss);
2961 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2962 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2965 if (netif_msg_tx_queued(priv)) {
2966 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2967 __func__, hdr, proto_hdr_len, pay_len, mss);
2968 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
2972 /* Check if VLAN can be inserted by HW */
2973 has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
2975 first_entry = tx_q->cur_tx;
2976 WARN_ON(tx_q->tx_skbuff[first_entry]);
2978 desc = tx_q->dma_tx + first_entry;
2982 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
2984 /* first descriptor: fill Headers on Buf1 */
2985 des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
2987 if (dma_mapping_error(priv->device, des))
2990 tx_q->tx_skbuff_dma[first_entry].buf = des;
2991 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
2993 if (priv->dma_cap.addr64 <= 32) {
2994 first->des0 = cpu_to_le32(des);
2996 /* Fill start of payload in buff2 of first descriptor */
2998 first->des1 = cpu_to_le32(des + proto_hdr_len);
3000 /* If needed take extra descriptors to fill the remaining payload */
3001 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
3003 stmmac_set_desc_addr(priv, first, des);
3004 tmp_pay_len = pay_len;
3005 des += proto_hdr_len;
3009 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
3011 /* Prepare fragments */
3012 for (i = 0; i < nfrags; i++) {
3013 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3015 des = skb_frag_dma_map(priv->device, frag, 0,
3016 skb_frag_size(frag),
3018 if (dma_mapping_error(priv->device, des))
3021 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
3022 (i == nfrags - 1), queue);
3024 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
3025 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
3026 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
3029 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
3031 /* Only the last descriptor gets to point to the skb. */
3032 tx_q->tx_skbuff[tx_q->cur_tx] = skb;
3034 /* Manage tx mitigation */
3035 tx_packets = (tx_q->cur_tx + 1) - first_tx;
3036 tx_q->tx_count_frames += tx_packets;
3038 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en)
3040 else if (!priv->tx_coal_frames)
3042 else if (tx_packets > priv->tx_coal_frames)
3044 else if ((tx_q->tx_count_frames % priv->tx_coal_frames) < tx_packets)
3050 desc = &tx_q->dma_tx[tx_q->cur_tx];
3051 tx_q->tx_count_frames = 0;
3052 stmmac_set_tx_ic(priv, desc);
3053 priv->xstats.tx_set_ic_bit++;
3055 stmmac_tx_timer_arm(priv, queue);
3058 /* We've used all descriptors we need for this skb, however,
3059 * advance cur_tx so that it references a fresh descriptor.
3060 * ndo_start_xmit will fill this descriptor the next time it's
3061 * called and stmmac_tx_clean may clean up to this descriptor.
3063 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
3065 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
3066 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
3068 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
3071 dev->stats.tx_bytes += skb->len;
3072 priv->xstats.tx_tso_frames++;
3073 priv->xstats.tx_tso_nfrags += nfrags;
3075 if (priv->sarc_type)
3076 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
3078 skb_tx_timestamp(skb);
3080 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3081 priv->hwts_tx_en)) {
3082 /* declare that device is doing timestamping */
3083 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3084 stmmac_enable_tx_timestamp(priv, first);
3087 /* Complete the first descriptor before granting the DMA */
3088 stmmac_prepare_tso_tx_desc(priv, first, 1,
3091 1, tx_q->tx_skbuff_dma[first_entry].last_segment,
3092 hdr / 4, (skb->len - proto_hdr_len));
3094 /* If context desc is used to change MSS */
3096 /* Make sure that first descriptor has been completely
3097 * written, including its own bit. This is because MSS is
3098 * actually before first descriptor, so we need to make
3099 * sure that MSS's own bit is the last thing written.
3102 stmmac_set_tx_owner(priv, mss_desc);
3105 /* The own bit must be the latest setting done when prepare the
3106 * descriptor and then barrier is needed to make sure that
3107 * all is coherent before granting the DMA engine.
3111 if (netif_msg_pktdata(priv)) {
3112 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
3113 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3114 tx_q->cur_tx, first, nfrags);
3116 stmmac_display_ring(priv, (void *)tx_q->dma_tx, DMA_TX_SIZE, 0);
3118 pr_info(">>> frame to be transmitted: ");
3119 print_pkt(skb->data, skb_headlen(skb));
3122 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3124 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
3125 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3127 return NETDEV_TX_OK;
3130 dev_err(priv->device, "Tx dma map failed\n");
3132 priv->dev->stats.tx_dropped++;
3133 return NETDEV_TX_OK;
3137 * stmmac_xmit - Tx entry point of the driver
3138 * @skb : the socket buffer
3139 * @dev : device pointer
3140 * Description : this is the tx entry point of the driver.
3141 * It programs the chain or the ring and supports oversized frames
3144 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
3146 unsigned int first_entry, tx_packets, enh_desc;
3147 struct stmmac_priv *priv = netdev_priv(dev);
3148 unsigned int nopaged_len = skb_headlen(skb);
3149 int i, csum_insertion = 0, is_jumbo = 0;
3150 u32 queue = skb_get_queue_mapping(skb);
3151 int nfrags = skb_shinfo(skb)->nr_frags;
3152 int gso = skb_shinfo(skb)->gso_type;
3153 struct dma_desc *desc, *first;
3154 struct stmmac_tx_queue *tx_q;
3155 bool has_vlan, set_ic;
3156 int entry, first_tx;
3159 tx_q = &priv->tx_queue[queue];
3160 first_tx = tx_q->cur_tx;
3162 if (priv->tx_path_in_lpi_mode)
3163 stmmac_disable_eee_mode(priv);
3165 /* Manage oversized TCP frames for GMAC4 device */
3166 if (skb_is_gso(skb) && priv->tso) {
3167 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6))
3168 return stmmac_tso_xmit(skb, dev);
3169 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4))
3170 return stmmac_tso_xmit(skb, dev);
3173 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
3174 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
3175 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
3177 /* This is a hard error, log it. */
3178 netdev_err(priv->dev,
3179 "%s: Tx Ring full when queue awake\n",
3182 return NETDEV_TX_BUSY;
3185 /* Check if VLAN can be inserted by HW */
3186 has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
3188 entry = tx_q->cur_tx;
3189 first_entry = entry;
3190 WARN_ON(tx_q->tx_skbuff[first_entry]);
3192 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
3194 if (likely(priv->extend_desc))
3195 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3197 desc = tx_q->dma_tx + entry;
3202 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
3204 enh_desc = priv->plat->enh_desc;
3205 /* To program the descriptors according to the size of the frame */
3207 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc);
3209 if (unlikely(is_jumbo)) {
3210 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion);
3211 if (unlikely(entry < 0) && (entry != -EINVAL))
3215 for (i = 0; i < nfrags; i++) {
3216 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3217 int len = skb_frag_size(frag);
3218 bool last_segment = (i == (nfrags - 1));
3220 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3221 WARN_ON(tx_q->tx_skbuff[entry]);
3223 if (likely(priv->extend_desc))
3224 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3226 desc = tx_q->dma_tx + entry;
3228 des = skb_frag_dma_map(priv->device, frag, 0, len,
3230 if (dma_mapping_error(priv->device, des))
3231 goto dma_map_err; /* should reuse desc w/o issues */
3233 tx_q->tx_skbuff_dma[entry].buf = des;
3235 stmmac_set_desc_addr(priv, desc, des);
3237 tx_q->tx_skbuff_dma[entry].map_as_page = true;
3238 tx_q->tx_skbuff_dma[entry].len = len;
3239 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
3241 /* Prepare the descriptor and set the own bit too */
3242 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion,
3243 priv->mode, 1, last_segment, skb->len);
3246 /* Only the last descriptor gets to point to the skb. */
3247 tx_q->tx_skbuff[entry] = skb;
3249 /* According to the coalesce parameter the IC bit for the latest
3250 * segment is reset and the timer re-started to clean the tx status.
3251 * This approach takes care about the fragments: desc is the first
3252 * element in case of no SG.
3254 tx_packets = (entry + 1) - first_tx;
3255 tx_q->tx_count_frames += tx_packets;
3257 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en)
3259 else if (!priv->tx_coal_frames)
3261 else if (tx_packets > priv->tx_coal_frames)
3263 else if ((tx_q->tx_count_frames % priv->tx_coal_frames) < tx_packets)
3269 if (likely(priv->extend_desc))
3270 desc = &tx_q->dma_etx[entry].basic;
3272 desc = &tx_q->dma_tx[entry];
3274 tx_q->tx_count_frames = 0;
3275 stmmac_set_tx_ic(priv, desc);
3276 priv->xstats.tx_set_ic_bit++;
3278 stmmac_tx_timer_arm(priv, queue);
3281 /* We've used all descriptors we need for this skb, however,
3282 * advance cur_tx so that it references a fresh descriptor.
3283 * ndo_start_xmit will fill this descriptor the next time it's
3284 * called and stmmac_tx_clean may clean up to this descriptor.
3286 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3287 tx_q->cur_tx = entry;
3289 if (netif_msg_pktdata(priv)) {
3292 netdev_dbg(priv->dev,
3293 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
3294 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3295 entry, first, nfrags);
3297 if (priv->extend_desc)
3298 tx_head = (void *)tx_q->dma_etx;
3300 tx_head = (void *)tx_q->dma_tx;
3302 stmmac_display_ring(priv, tx_head, DMA_TX_SIZE, false);
3304 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
3305 print_pkt(skb->data, skb->len);
3308 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
3309 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
3311 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
3314 dev->stats.tx_bytes += skb->len;
3316 if (priv->sarc_type)
3317 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
3319 skb_tx_timestamp(skb);
3321 /* Ready to fill the first descriptor and set the OWN bit w/o any
3322 * problems because all the descriptors are actually ready to be
3323 * passed to the DMA engine.
3325 if (likely(!is_jumbo)) {
3326 bool last_segment = (nfrags == 0);
3328 des = dma_map_single(priv->device, skb->data,
3329 nopaged_len, DMA_TO_DEVICE);
3330 if (dma_mapping_error(priv->device, des))
3333 tx_q->tx_skbuff_dma[first_entry].buf = des;
3335 stmmac_set_desc_addr(priv, first, des);
3337 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
3338 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
3340 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3341 priv->hwts_tx_en)) {
3342 /* declare that device is doing timestamping */
3343 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3344 stmmac_enable_tx_timestamp(priv, first);
3347 /* Prepare the first descriptor setting the OWN bit too */
3348 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
3349 csum_insertion, priv->mode, 1, last_segment,
3352 stmmac_set_tx_owner(priv, first);
3355 /* The own bit must be the latest setting done when prepare the
3356 * descriptor and then barrier is needed to make sure that
3357 * all is coherent before granting the DMA engine.
3361 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3363 stmmac_enable_dma_transmission(priv, priv->ioaddr);
3365 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
3366 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3368 return NETDEV_TX_OK;
3371 netdev_err(priv->dev, "Tx DMA map failed\n");
3373 priv->dev->stats.tx_dropped++;
3374 return NETDEV_TX_OK;
3377 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
3379 struct vlan_ethhdr *veth;
3383 veth = (struct vlan_ethhdr *)skb->data;
3384 vlan_proto = veth->h_vlan_proto;
3386 if ((vlan_proto == htons(ETH_P_8021Q) &&
3387 dev->features & NETIF_F_HW_VLAN_CTAG_RX) ||
3388 (vlan_proto == htons(ETH_P_8021AD) &&
3389 dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
3390 /* pop the vlan tag */
3391 vlanid = ntohs(veth->h_vlan_TCI);
3392 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2);
3393 skb_pull(skb, VLAN_HLEN);
3394 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid);
3399 static inline int stmmac_rx_threshold_count(struct stmmac_rx_queue *rx_q)
3401 if (rx_q->rx_zeroc_thresh < STMMAC_RX_THRESH)
3408 * stmmac_rx_refill - refill used skb preallocated buffers
3409 * @priv: driver private structure
3410 * @queue: RX queue index
3411 * Description : this is to reallocate the skb for the reception process
3412 * that is based on zero-copy.
3414 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
3416 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3417 int len, dirty = stmmac_rx_dirty(priv, queue);
3418 unsigned int entry = rx_q->dirty_rx;
3420 len = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE;
3422 while (dirty-- > 0) {
3423 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
3427 if (priv->extend_desc)
3428 p = (struct dma_desc *)(rx_q->dma_erx + entry);
3430 p = rx_q->dma_rx + entry;
3433 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
3438 if (priv->sph && !buf->sec_page) {
3439 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool);
3443 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
3445 dma_sync_single_for_device(priv->device, buf->sec_addr,
3446 len, DMA_FROM_DEVICE);
3449 buf->addr = page_pool_get_dma_addr(buf->page);
3451 /* Sync whole allocation to device. This will invalidate old
3454 dma_sync_single_for_device(priv->device, buf->addr, len,
3457 stmmac_set_desc_addr(priv, p, buf->addr);
3458 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr);
3459 stmmac_refill_desc3(priv, rx_q, p);
3461 rx_q->rx_count_frames++;
3462 rx_q->rx_count_frames += priv->rx_coal_frames;
3463 if (rx_q->rx_count_frames > priv->rx_coal_frames)
3464 rx_q->rx_count_frames = 0;
3466 use_rx_wd = !priv->rx_coal_frames;
3467 use_rx_wd |= rx_q->rx_count_frames > 0;
3468 if (!priv->use_riwt)
3472 stmmac_set_rx_owner(priv, p, use_rx_wd);
3474 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
3476 rx_q->dirty_rx = entry;
3477 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
3478 (rx_q->dirty_rx * sizeof(struct dma_desc));
3479 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
3482 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv,
3484 int status, unsigned int len)
3486 int ret, coe = priv->hw->rx_csum;
3487 unsigned int plen = 0, hlen = 0;
3489 /* Not first descriptor, buffer is always zero */
3490 if (priv->sph && len)
3493 /* First descriptor, get split header length */
3494 ret = stmmac_get_rx_header_len(priv, p, &hlen);
3495 if (priv->sph && hlen) {
3496 priv->xstats.rx_split_hdr_pkt_n++;
3500 /* First descriptor, not last descriptor and not split header */
3501 if (status & rx_not_ls)
3502 return priv->dma_buf_sz;
3504 plen = stmmac_get_rx_frame_len(priv, p, coe);
3506 /* First descriptor and last descriptor and not split header */
3507 return min_t(unsigned int, priv->dma_buf_sz, plen);
3510 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv,
3512 int status, unsigned int len)
3514 int coe = priv->hw->rx_csum;
3515 unsigned int plen = 0;
3517 /* Not split header, buffer is not available */
3521 /* Not last descriptor */
3522 if (status & rx_not_ls)
3523 return priv->dma_buf_sz;
3525 plen = stmmac_get_rx_frame_len(priv, p, coe);
3527 /* Last descriptor */
3532 * stmmac_rx - manage the receive process
3533 * @priv: driver private structure
3534 * @limit: napi bugget
3535 * @queue: RX queue index.
3536 * Description : this the function called by the napi poll method.
3537 * It gets all the frames inside the ring.
3539 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
3541 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3542 struct stmmac_channel *ch = &priv->channel[queue];
3543 unsigned int count = 0, error = 0, len = 0;
3544 int status = 0, coe = priv->hw->rx_csum;
3545 unsigned int next_entry = rx_q->cur_rx;
3546 struct sk_buff *skb = NULL;
3548 if (netif_msg_rx_status(priv)) {
3551 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
3552 if (priv->extend_desc)
3553 rx_head = (void *)rx_q->dma_erx;
3555 rx_head = (void *)rx_q->dma_rx;
3557 stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true);
3559 while (count < limit) {
3560 unsigned int buf1_len = 0, buf2_len = 0;
3561 enum pkt_hash_types hash_type;
3562 struct stmmac_rx_buffer *buf;
3563 struct dma_desc *np, *p;
3567 if (!count && rx_q->state_saved) {
3568 skb = rx_q->state.skb;
3569 error = rx_q->state.error;
3570 len = rx_q->state.len;
3572 rx_q->state_saved = false;
3585 buf = &rx_q->buf_pool[entry];
3587 if (priv->extend_desc)
3588 p = (struct dma_desc *)(rx_q->dma_erx + entry);
3590 p = rx_q->dma_rx + entry;
3592 /* read the status of the incoming frame */
3593 status = stmmac_rx_status(priv, &priv->dev->stats,
3595 /* check if managed by the DMA otherwise go ahead */
3596 if (unlikely(status & dma_own))
3599 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE);
3600 next_entry = rx_q->cur_rx;
3602 if (priv->extend_desc)
3603 np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
3605 np = rx_q->dma_rx + next_entry;
3609 if (priv->extend_desc)
3610 stmmac_rx_extended_status(priv, &priv->dev->stats,
3611 &priv->xstats, rx_q->dma_erx + entry);
3612 if (unlikely(status == discard_frame)) {
3613 page_pool_recycle_direct(rx_q->page_pool, buf->page);
3616 if (!priv->hwts_rx_en)
3617 priv->dev->stats.rx_errors++;
3620 if (unlikely(error && (status & rx_not_ls)))
3622 if (unlikely(error)) {
3629 /* Buffer is good. Go on. */
3631 prefetch(page_address(buf->page));
3633 prefetch(page_address(buf->sec_page));
3635 buf1_len = stmmac_rx_buf1_len(priv, p, status, len);
3637 buf2_len = stmmac_rx_buf2_len(priv, p, status, len);
3640 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
3641 * Type frames (LLC/LLC-SNAP)
3643 * llc_snap is never checked in GMAC >= 4, so this ACS
3644 * feature is always disabled and packets need to be
3645 * stripped manually.
3647 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
3648 unlikely(status != llc_snap)) {
3650 buf2_len -= ETH_FCS_LEN;
3652 buf1_len -= ETH_FCS_LEN;
3658 skb = napi_alloc_skb(&ch->rx_napi, buf1_len);
3660 priv->dev->stats.rx_dropped++;
3665 dma_sync_single_for_cpu(priv->device, buf->addr,
3666 buf1_len, DMA_FROM_DEVICE);
3667 skb_copy_to_linear_data(skb, page_address(buf->page),
3669 skb_put(skb, buf1_len);
3671 /* Data payload copied into SKB, page ready for recycle */
3672 page_pool_recycle_direct(rx_q->page_pool, buf->page);
3674 } else if (buf1_len) {
3675 dma_sync_single_for_cpu(priv->device, buf->addr,
3676 buf1_len, DMA_FROM_DEVICE);
3677 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
3678 buf->page, 0, buf1_len,
3681 /* Data payload appended into SKB */
3682 page_pool_release_page(rx_q->page_pool, buf->page);
3687 dma_sync_single_for_cpu(priv->device, buf->sec_addr,
3688 buf2_len, DMA_FROM_DEVICE);
3689 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
3690 buf->sec_page, 0, buf2_len,
3693 /* Data payload appended into SKB */
3694 page_pool_release_page(rx_q->page_pool, buf->sec_page);
3695 buf->sec_page = NULL;
3699 if (likely(status & rx_not_ls))
3704 /* Got entire packet into SKB. Finish it. */
3706 stmmac_get_rx_hwtstamp(priv, p, np, skb);
3707 stmmac_rx_vlan(priv->dev, skb);
3708 skb->protocol = eth_type_trans(skb, priv->dev);
3711 skb_checksum_none_assert(skb);
3713 skb->ip_summed = CHECKSUM_UNNECESSARY;
3715 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type))
3716 skb_set_hash(skb, hash, hash_type);
3718 skb_record_rx_queue(skb, queue);
3719 napi_gro_receive(&ch->rx_napi, skb);
3722 priv->dev->stats.rx_packets++;
3723 priv->dev->stats.rx_bytes += len;
3727 if (status & rx_not_ls || skb) {
3728 rx_q->state_saved = true;
3729 rx_q->state.skb = skb;
3730 rx_q->state.error = error;
3731 rx_q->state.len = len;
3734 stmmac_rx_refill(priv, queue);
3736 priv->xstats.rx_pkt_n += count;
3741 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget)
3743 struct stmmac_channel *ch =
3744 container_of(napi, struct stmmac_channel, rx_napi);
3745 struct stmmac_priv *priv = ch->priv_data;
3746 u32 chan = ch->index;
3749 priv->xstats.napi_poll++;
3751 work_done = stmmac_rx(priv, budget, chan);
3752 if (work_done < budget && napi_complete_done(napi, work_done))
3753 stmmac_enable_dma_irq(priv, priv->ioaddr, chan);
3757 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget)
3759 struct stmmac_channel *ch =
3760 container_of(napi, struct stmmac_channel, tx_napi);
3761 struct stmmac_priv *priv = ch->priv_data;
3762 struct stmmac_tx_queue *tx_q;
3763 u32 chan = ch->index;
3766 priv->xstats.napi_poll++;
3768 work_done = stmmac_tx_clean(priv, DMA_TX_SIZE, chan);
3769 work_done = min(work_done, budget);
3771 if (work_done < budget)
3772 napi_complete_done(napi, work_done);
3774 /* Force transmission restart */
3775 tx_q = &priv->tx_queue[chan];
3776 if (tx_q->cur_tx != tx_q->dirty_tx) {
3777 stmmac_enable_dma_transmission(priv, priv->ioaddr);
3778 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr,
3787 * @dev : Pointer to net device structure
3788 * Description: this function is called when a packet transmission fails to
3789 * complete within a reasonable time. The driver will mark the error in the
3790 * netdev structure and arrange for the device to be reset to a sane state
3791 * in order to transmit a new packet.
3793 static void stmmac_tx_timeout(struct net_device *dev)
3795 struct stmmac_priv *priv = netdev_priv(dev);
3797 stmmac_global_err(priv);
3801 * stmmac_set_rx_mode - entry point for multicast addressing
3802 * @dev : pointer to the device structure
3804 * This function is a driver entry point which gets called by the kernel
3805 * whenever multicast addresses must be enabled/disabled.
3809 static void stmmac_set_rx_mode(struct net_device *dev)
3811 struct stmmac_priv *priv = netdev_priv(dev);
3813 stmmac_set_filter(priv, priv->hw, dev);
3817 * stmmac_change_mtu - entry point to change MTU size for the device.
3818 * @dev : device pointer.
3819 * @new_mtu : the new MTU size for the device.
3820 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
3821 * to drive packet transmission. Ethernet has an MTU of 1500 octets
3822 * (ETH_DATA_LEN). This value can be changed with ifconfig.
3824 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3827 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
3829 struct stmmac_priv *priv = netdev_priv(dev);
3831 if (netif_running(dev)) {
3832 netdev_err(priv->dev, "must be stopped to change its MTU\n");
3838 netdev_update_features(dev);
3843 static netdev_features_t stmmac_fix_features(struct net_device *dev,
3844 netdev_features_t features)
3846 struct stmmac_priv *priv = netdev_priv(dev);
3848 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
3849 features &= ~NETIF_F_RXCSUM;
3851 if (!priv->plat->tx_coe)
3852 features &= ~NETIF_F_CSUM_MASK;
3854 /* Some GMAC devices have a bugged Jumbo frame support that
3855 * needs to have the Tx COE disabled for oversized frames
3856 * (due to limited buffer sizes). In this case we disable
3857 * the TX csum insertion in the TDES and not use SF.
3859 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
3860 features &= ~NETIF_F_CSUM_MASK;
3862 /* Disable tso if asked by ethtool */
3863 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3864 if (features & NETIF_F_TSO)
3873 static int stmmac_set_features(struct net_device *netdev,
3874 netdev_features_t features)
3876 struct stmmac_priv *priv = netdev_priv(netdev);
3880 /* Keep the COE Type in case of csum is supporting */
3881 if (features & NETIF_F_RXCSUM)
3882 priv->hw->rx_csum = priv->plat->rx_coe;
3884 priv->hw->rx_csum = 0;
3885 /* No check needed because rx_coe has been set before and it will be
3886 * fixed in case of issue.
3888 stmmac_rx_ipc(priv, priv->hw);
3890 sph_en = (priv->hw->rx_csum > 0) && priv->sph;
3891 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++)
3892 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
3898 * stmmac_interrupt - main ISR
3899 * @irq: interrupt number.
3900 * @dev_id: to pass the net device pointer.
3901 * Description: this is the main driver interrupt service routine.
3903 * o DMA service routine (to manage incoming frame reception and transmission
3905 * o Core interrupts to manage: remote wake-up, management counter, LPI
3908 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
3910 struct net_device *dev = (struct net_device *)dev_id;
3911 struct stmmac_priv *priv = netdev_priv(dev);
3912 u32 rx_cnt = priv->plat->rx_queues_to_use;
3913 u32 tx_cnt = priv->plat->tx_queues_to_use;
3918 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
3919 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
3922 pm_wakeup_event(priv->device, 0);
3924 if (unlikely(!dev)) {
3925 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
3929 /* Check if adapter is up */
3930 if (test_bit(STMMAC_DOWN, &priv->state))
3932 /* Check if a fatal error happened */
3933 if (stmmac_safety_feat_interrupt(priv))
3936 /* To handle GMAC own interrupts */
3937 if ((priv->plat->has_gmac) || xmac) {
3938 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
3941 if (unlikely(status)) {
3942 /* For LPI we need to save the tx status */
3943 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
3944 priv->tx_path_in_lpi_mode = true;
3945 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
3946 priv->tx_path_in_lpi_mode = false;
3949 for (queue = 0; queue < queues_count; queue++) {
3950 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3952 mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw,
3954 if (mtl_status != -EINVAL)
3955 status |= mtl_status;
3957 if (status & CORE_IRQ_MTL_RX_OVERFLOW)
3958 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
3963 /* PCS link status */
3964 if (priv->hw->pcs) {
3965 if (priv->xstats.pcs_link)
3966 netif_carrier_on(dev);
3968 netif_carrier_off(dev);
3972 /* To handle DMA interrupts */
3973 stmmac_dma_interrupt(priv);
3978 #ifdef CONFIG_NET_POLL_CONTROLLER
3979 /* Polling receive - used by NETCONSOLE and other diagnostic tools
3980 * to allow network I/O with interrupts disabled.
3982 static void stmmac_poll_controller(struct net_device *dev)
3984 disable_irq(dev->irq);
3985 stmmac_interrupt(dev->irq, dev);
3986 enable_irq(dev->irq);
3991 * stmmac_ioctl - Entry point for the Ioctl
3992 * @dev: Device pointer.
3993 * @rq: An IOCTL specefic structure, that can contain a pointer to
3994 * a proprietary structure used to pass information to the driver.
3995 * @cmd: IOCTL command
3997 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
3999 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
4001 struct stmmac_priv *priv = netdev_priv (dev);
4002 int ret = -EOPNOTSUPP;
4004 if (!netif_running(dev))
4011 ret = phylink_mii_ioctl(priv->phylink, rq, cmd);
4014 ret = stmmac_hwtstamp_set(dev, rq);
4017 ret = stmmac_hwtstamp_get(dev, rq);
4026 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
4029 struct stmmac_priv *priv = cb_priv;
4030 int ret = -EOPNOTSUPP;
4032 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data))
4035 stmmac_disable_all_queues(priv);
4038 case TC_SETUP_CLSU32:
4039 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data);
4041 case TC_SETUP_CLSFLOWER:
4042 ret = stmmac_tc_setup_cls(priv, priv, type_data);
4048 stmmac_enable_all_queues(priv);
4052 static LIST_HEAD(stmmac_block_cb_list);
4054 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
4057 struct stmmac_priv *priv = netdev_priv(ndev);
4060 case TC_SETUP_BLOCK:
4061 return flow_block_cb_setup_simple(type_data,
4062 &stmmac_block_cb_list,
4063 stmmac_setup_tc_block_cb,
4065 case TC_SETUP_QDISC_CBS:
4066 return stmmac_tc_setup_cbs(priv, priv, type_data);
4072 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb,
4073 struct net_device *sb_dev)
4075 int gso = skb_shinfo(skb)->gso_type;
4077 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) {
4079 * There is no way to determine the number of TSO/USO
4080 * capable Queues. Let's use always the Queue 0
4081 * because if TSO/USO is supported then at least this
4082 * one will be capable.
4087 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues;
4090 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
4092 struct stmmac_priv *priv = netdev_priv(ndev);
4095 ret = eth_mac_addr(ndev, addr);
4099 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
4104 #ifdef CONFIG_DEBUG_FS
4105 static struct dentry *stmmac_fs_dir;
4107 static void sysfs_display_ring(void *head, int size, int extend_desc,
4108 struct seq_file *seq)
4111 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
4112 struct dma_desc *p = (struct dma_desc *)head;
4114 for (i = 0; i < size; i++) {
4116 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
4117 i, (unsigned int)virt_to_phys(ep),
4118 le32_to_cpu(ep->basic.des0),
4119 le32_to_cpu(ep->basic.des1),
4120 le32_to_cpu(ep->basic.des2),
4121 le32_to_cpu(ep->basic.des3));
4124 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
4125 i, (unsigned int)virt_to_phys(p),
4126 le32_to_cpu(p->des0), le32_to_cpu(p->des1),
4127 le32_to_cpu(p->des2), le32_to_cpu(p->des3));
4130 seq_printf(seq, "\n");
4134 static int stmmac_rings_status_show(struct seq_file *seq, void *v)
4136 struct net_device *dev = seq->private;
4137 struct stmmac_priv *priv = netdev_priv(dev);
4138 u32 rx_count = priv->plat->rx_queues_to_use;
4139 u32 tx_count = priv->plat->tx_queues_to_use;
4142 if ((dev->flags & IFF_UP) == 0)
4145 for (queue = 0; queue < rx_count; queue++) {
4146 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4148 seq_printf(seq, "RX Queue %d:\n", queue);
4150 if (priv->extend_desc) {
4151 seq_printf(seq, "Extended descriptor ring:\n");
4152 sysfs_display_ring((void *)rx_q->dma_erx,
4153 DMA_RX_SIZE, 1, seq);
4155 seq_printf(seq, "Descriptor ring:\n");
4156 sysfs_display_ring((void *)rx_q->dma_rx,
4157 DMA_RX_SIZE, 0, seq);
4161 for (queue = 0; queue < tx_count; queue++) {
4162 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4164 seq_printf(seq, "TX Queue %d:\n", queue);
4166 if (priv->extend_desc) {
4167 seq_printf(seq, "Extended descriptor ring:\n");
4168 sysfs_display_ring((void *)tx_q->dma_etx,
4169 DMA_TX_SIZE, 1, seq);
4171 seq_printf(seq, "Descriptor ring:\n");
4172 sysfs_display_ring((void *)tx_q->dma_tx,
4173 DMA_TX_SIZE, 0, seq);
4179 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status);
4181 static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
4183 struct net_device *dev = seq->private;
4184 struct stmmac_priv *priv = netdev_priv(dev);
4186 if (!priv->hw_cap_support) {
4187 seq_printf(seq, "DMA HW features not supported\n");
4191 seq_printf(seq, "==============================\n");
4192 seq_printf(seq, "\tDMA HW features\n");
4193 seq_printf(seq, "==============================\n");
4195 seq_printf(seq, "\t10/100 Mbps: %s\n",
4196 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
4197 seq_printf(seq, "\t1000 Mbps: %s\n",
4198 (priv->dma_cap.mbps_1000) ? "Y" : "N");
4199 seq_printf(seq, "\tHalf duplex: %s\n",
4200 (priv->dma_cap.half_duplex) ? "Y" : "N");
4201 seq_printf(seq, "\tHash Filter: %s\n",
4202 (priv->dma_cap.hash_filter) ? "Y" : "N");
4203 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
4204 (priv->dma_cap.multi_addr) ? "Y" : "N");
4205 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
4206 (priv->dma_cap.pcs) ? "Y" : "N");
4207 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
4208 (priv->dma_cap.sma_mdio) ? "Y" : "N");
4209 seq_printf(seq, "\tPMT Remote wake up: %s\n",
4210 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
4211 seq_printf(seq, "\tPMT Magic Frame: %s\n",
4212 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
4213 seq_printf(seq, "\tRMON module: %s\n",
4214 (priv->dma_cap.rmon) ? "Y" : "N");
4215 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
4216 (priv->dma_cap.time_stamp) ? "Y" : "N");
4217 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
4218 (priv->dma_cap.atime_stamp) ? "Y" : "N");
4219 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
4220 (priv->dma_cap.eee) ? "Y" : "N");
4221 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
4222 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
4223 (priv->dma_cap.tx_coe) ? "Y" : "N");
4224 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
4225 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
4226 (priv->dma_cap.rx_coe) ? "Y" : "N");
4228 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
4229 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
4230 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
4231 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
4233 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
4234 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
4235 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
4236 priv->dma_cap.number_rx_channel);
4237 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
4238 priv->dma_cap.number_tx_channel);
4239 seq_printf(seq, "\tEnhanced descriptors: %s\n",
4240 (priv->dma_cap.enh_desc) ? "Y" : "N");
4244 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap);
4246 static void stmmac_init_fs(struct net_device *dev)
4248 struct stmmac_priv *priv = netdev_priv(dev);
4250 /* Create per netdev entries */
4251 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
4253 /* Entry to report DMA RX/TX rings */
4254 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev,
4255 &stmmac_rings_status_fops);
4257 /* Entry to report the DMA HW features */
4258 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev,
4259 &stmmac_dma_cap_fops);
4262 static void stmmac_exit_fs(struct net_device *dev)
4264 struct stmmac_priv *priv = netdev_priv(dev);
4266 debugfs_remove_recursive(priv->dbgfs_dir);
4268 #endif /* CONFIG_DEBUG_FS */
4270 static u32 stmmac_vid_crc32_le(__le16 vid_le)
4272 unsigned char *data = (unsigned char *)&vid_le;
4273 unsigned char data_byte = 0;
4278 bits = get_bitmask_order(VLAN_VID_MASK);
4279 for (i = 0; i < bits; i++) {
4281 data_byte = data[i / 8];
4283 temp = ((crc & 1) ^ data_byte) & 1;
4294 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double)
4301 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
4302 __le16 vid_le = cpu_to_le16(vid);
4303 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28;
4308 if (!priv->dma_cap.vlhash) {
4309 if (count > 2) /* VID = 0 always passes filter */
4312 pmatch = cpu_to_le16(vid);
4316 return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double);
4319 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)
4321 struct stmmac_priv *priv = netdev_priv(ndev);
4322 bool is_double = false;
4325 if (be16_to_cpu(proto) == ETH_P_8021AD)
4328 set_bit(vid, priv->active_vlans);
4329 ret = stmmac_vlan_update(priv, is_double);
4331 clear_bit(vid, priv->active_vlans);
4338 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid)
4340 struct stmmac_priv *priv = netdev_priv(ndev);
4341 bool is_double = false;
4343 if (be16_to_cpu(proto) == ETH_P_8021AD)
4346 clear_bit(vid, priv->active_vlans);
4347 return stmmac_vlan_update(priv, is_double);
4350 static const struct net_device_ops stmmac_netdev_ops = {
4351 .ndo_open = stmmac_open,
4352 .ndo_start_xmit = stmmac_xmit,
4353 .ndo_stop = stmmac_release,
4354 .ndo_change_mtu = stmmac_change_mtu,
4355 .ndo_fix_features = stmmac_fix_features,
4356 .ndo_set_features = stmmac_set_features,
4357 .ndo_set_rx_mode = stmmac_set_rx_mode,
4358 .ndo_tx_timeout = stmmac_tx_timeout,
4359 .ndo_do_ioctl = stmmac_ioctl,
4360 .ndo_setup_tc = stmmac_setup_tc,
4361 .ndo_select_queue = stmmac_select_queue,
4362 #ifdef CONFIG_NET_POLL_CONTROLLER
4363 .ndo_poll_controller = stmmac_poll_controller,
4365 .ndo_set_mac_address = stmmac_set_mac_address,
4366 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid,
4367 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid,
4370 static void stmmac_reset_subtask(struct stmmac_priv *priv)
4372 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state))
4374 if (test_bit(STMMAC_DOWN, &priv->state))
4377 netdev_err(priv->dev, "Reset adapter.\n");
4380 netif_trans_update(priv->dev);
4381 while (test_and_set_bit(STMMAC_RESETING, &priv->state))
4382 usleep_range(1000, 2000);
4384 set_bit(STMMAC_DOWN, &priv->state);
4385 dev_close(priv->dev);
4386 dev_open(priv->dev, NULL);
4387 clear_bit(STMMAC_DOWN, &priv->state);
4388 clear_bit(STMMAC_RESETING, &priv->state);
4392 static void stmmac_service_task(struct work_struct *work)
4394 struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
4397 stmmac_reset_subtask(priv);
4398 clear_bit(STMMAC_SERVICE_SCHED, &priv->state);
4402 * stmmac_hw_init - Init the MAC device
4403 * @priv: driver private structure
4404 * Description: this function is to configure the MAC device according to
4405 * some platform parameters or the HW capability register. It prepares the
4406 * driver to use either ring or chain modes and to setup either enhanced or
4407 * normal descriptors.
4409 static int stmmac_hw_init(struct stmmac_priv *priv)
4413 /* dwmac-sun8i only work in chain mode */
4414 if (priv->plat->has_sun8i)
4416 priv->chain_mode = chain_mode;
4418 /* Initialize HW Interface */
4419 ret = stmmac_hwif_init(priv);
4423 /* Get the HW capability (new GMAC newer than 3.50a) */
4424 priv->hw_cap_support = stmmac_get_hw_features(priv);
4425 if (priv->hw_cap_support) {
4426 dev_info(priv->device, "DMA HW capability register supported\n");
4428 /* We can override some gmac/dma configuration fields: e.g.
4429 * enh_desc, tx_coe (e.g. that are passed through the
4430 * platform) with the values from the HW capability
4431 * register (if supported).
4433 priv->plat->enh_desc = priv->dma_cap.enh_desc;
4434 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
4435 priv->hw->pmt = priv->plat->pmt;
4436 if (priv->dma_cap.hash_tb_sz) {
4437 priv->hw->multicast_filter_bins =
4438 (BIT(priv->dma_cap.hash_tb_sz) << 5);
4439 priv->hw->mcast_bits_log2 =
4440 ilog2(priv->hw->multicast_filter_bins);
4443 /* TXCOE doesn't work in thresh DMA mode */
4444 if (priv->plat->force_thresh_dma_mode)
4445 priv->plat->tx_coe = 0;
4447 priv->plat->tx_coe = priv->dma_cap.tx_coe;
4449 /* In case of GMAC4 rx_coe is from HW cap register. */
4450 priv->plat->rx_coe = priv->dma_cap.rx_coe;
4452 if (priv->dma_cap.rx_coe_type2)
4453 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
4454 else if (priv->dma_cap.rx_coe_type1)
4455 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
4458 dev_info(priv->device, "No HW DMA feature register supported\n");
4461 if (priv->plat->rx_coe) {
4462 priv->hw->rx_csum = priv->plat->rx_coe;
4463 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
4464 if (priv->synopsys_id < DWMAC_CORE_4_00)
4465 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
4467 if (priv->plat->tx_coe)
4468 dev_info(priv->device, "TX Checksum insertion supported\n");
4470 if (priv->plat->pmt) {
4471 dev_info(priv->device, "Wake-Up On Lan supported\n");
4472 device_set_wakeup_capable(priv->device, 1);
4475 if (priv->dma_cap.tsoen)
4476 dev_info(priv->device, "TSO supported\n");
4478 /* Run HW quirks, if any */
4479 if (priv->hwif_quirks) {
4480 ret = priv->hwif_quirks(priv);
4485 /* Rx Watchdog is available in the COREs newer than the 3.40.
4486 * In some case, for example on bugged HW this feature
4487 * has to be disable and this can be done by passing the
4488 * riwt_off field from the platform.
4490 if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
4491 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
4493 dev_info(priv->device,
4494 "Enable RX Mitigation via HW Watchdog Timer\n");
4502 * @device: device pointer
4503 * @plat_dat: platform data pointer
4504 * @res: stmmac resource pointer
4505 * Description: this is the main probe function used to
4506 * call the alloc_etherdev, allocate the priv structure.
4508 * returns 0 on success, otherwise errno.
4510 int stmmac_dvr_probe(struct device *device,
4511 struct plat_stmmacenet_data *plat_dat,
4512 struct stmmac_resources *res)
4514 struct net_device *ndev = NULL;
4515 struct stmmac_priv *priv;
4516 u32 queue, rxq, maxq;
4519 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv),
4520 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES);
4524 SET_NETDEV_DEV(ndev, device);
4526 priv = netdev_priv(ndev);
4527 priv->device = device;
4530 stmmac_set_ethtool_ops(ndev);
4531 priv->pause = pause;
4532 priv->plat = plat_dat;
4533 priv->ioaddr = res->addr;
4534 priv->dev->base_addr = (unsigned long)res->addr;
4536 priv->dev->irq = res->irq;
4537 priv->wol_irq = res->wol_irq;
4538 priv->lpi_irq = res->lpi_irq;
4540 if (!IS_ERR_OR_NULL(res->mac))
4541 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
4543 dev_set_drvdata(device, priv->dev);
4545 /* Verify driver arguments */
4546 stmmac_verify_args();
4548 /* Allocate workqueue */
4549 priv->wq = create_singlethread_workqueue("stmmac_wq");
4551 dev_err(priv->device, "failed to create workqueue\n");
4555 INIT_WORK(&priv->service_task, stmmac_service_task);
4557 /* Override with kernel parameters if supplied XXX CRS XXX
4558 * this needs to have multiple instances
4560 if ((phyaddr >= 0) && (phyaddr <= 31))
4561 priv->plat->phy_addr = phyaddr;
4563 if (priv->plat->stmmac_rst) {
4564 ret = reset_control_assert(priv->plat->stmmac_rst);
4565 reset_control_deassert(priv->plat->stmmac_rst);
4566 /* Some reset controllers have only reset callback instead of
4567 * assert + deassert callbacks pair.
4569 if (ret == -ENOTSUPP)
4570 reset_control_reset(priv->plat->stmmac_rst);
4573 /* Init MAC and get the capabilities */
4574 ret = stmmac_hw_init(priv);
4578 stmmac_check_ether_addr(priv);
4580 /* Configure real RX and TX queues */
4581 netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use);
4582 netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use);
4584 ndev->netdev_ops = &stmmac_netdev_ops;
4586 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4589 ret = stmmac_tc_init(priv, priv);
4591 ndev->hw_features |= NETIF_F_HW_TC;
4594 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
4595 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
4596 if (priv->plat->has_gmac4)
4597 ndev->hw_features |= NETIF_F_GSO_UDP_L4;
4599 dev_info(priv->device, "TSO feature enabled\n");
4602 if (priv->dma_cap.sphen) {
4603 ndev->hw_features |= NETIF_F_GRO;
4605 dev_info(priv->device, "SPH feature enabled\n");
4608 if (priv->dma_cap.addr64) {
4609 ret = dma_set_mask_and_coherent(device,
4610 DMA_BIT_MASK(priv->dma_cap.addr64));
4612 dev_info(priv->device, "Using %d bits DMA width\n",
4613 priv->dma_cap.addr64);
4616 * If more than 32 bits can be addressed, make sure to
4617 * enable enhanced addressing mode.
4619 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
4620 priv->plat->dma_cfg->eame = true;
4622 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32));
4624 dev_err(priv->device, "Failed to set DMA Mask\n");
4628 priv->dma_cap.addr64 = 32;
4632 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
4633 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
4634 #ifdef STMMAC_VLAN_TAG_USED
4635 /* Both mac100 and gmac support receive VLAN tag detection */
4636 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
4637 if (priv->dma_cap.vlhash) {
4638 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4639 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
4641 if (priv->dma_cap.vlins) {
4642 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX;
4643 if (priv->dma_cap.dvlan)
4644 ndev->features |= NETIF_F_HW_VLAN_STAG_TX;
4647 priv->msg_enable = netif_msg_init(debug, default_msg_level);
4649 /* Initialize RSS */
4650 rxq = priv->plat->rx_queues_to_use;
4651 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key));
4652 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
4653 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq);
4655 if (priv->dma_cap.rssen && priv->plat->rss_en)
4656 ndev->features |= NETIF_F_RXHASH;
4658 /* MTU range: 46 - hw-specific max */
4659 ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
4660 if (priv->plat->has_xgmac)
4661 ndev->max_mtu = XGMAC_JUMBO_LEN;
4662 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
4663 ndev->max_mtu = JUMBO_LEN;
4665 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
4666 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
4667 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
4669 if ((priv->plat->maxmtu < ndev->max_mtu) &&
4670 (priv->plat->maxmtu >= ndev->min_mtu))
4671 ndev->max_mtu = priv->plat->maxmtu;
4672 else if (priv->plat->maxmtu < ndev->min_mtu)
4673 dev_warn(priv->device,
4674 "%s: warning: maxmtu having invalid value (%d)\n",
4675 __func__, priv->plat->maxmtu);
4678 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
4680 /* Setup channels NAPI */
4681 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
4683 for (queue = 0; queue < maxq; queue++) {
4684 struct stmmac_channel *ch = &priv->channel[queue];
4686 ch->priv_data = priv;
4689 if (queue < priv->plat->rx_queues_to_use) {
4690 netif_napi_add(ndev, &ch->rx_napi, stmmac_napi_poll_rx,
4693 if (queue < priv->plat->tx_queues_to_use) {
4694 netif_tx_napi_add(ndev, &ch->tx_napi,
4695 stmmac_napi_poll_tx,
4700 mutex_init(&priv->lock);
4702 /* If a specific clk_csr value is passed from the platform
4703 * this means that the CSR Clock Range selection cannot be
4704 * changed at run-time and it is fixed. Viceversa the driver'll try to
4705 * set the MDC clock dynamically according to the csr actual
4708 if (priv->plat->clk_csr >= 0)
4709 priv->clk_csr = priv->plat->clk_csr;
4711 stmmac_clk_csr_set(priv);
4713 stmmac_check_pcs_mode(priv);
4715 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4716 priv->hw->pcs != STMMAC_PCS_TBI &&
4717 priv->hw->pcs != STMMAC_PCS_RTBI) {
4718 /* MDIO bus Registration */
4719 ret = stmmac_mdio_register(ndev);
4721 dev_err(priv->device,
4722 "%s: MDIO bus (id: %d) registration failed",
4723 __func__, priv->plat->bus_id);
4724 goto error_mdio_register;
4728 ret = stmmac_phy_setup(priv);
4730 netdev_err(ndev, "failed to setup phy (%d)\n", ret);
4731 goto error_phy_setup;
4734 ret = register_netdev(ndev);
4736 dev_err(priv->device, "%s: ERROR %i registering the device\n",
4738 goto error_netdev_register;
4741 #ifdef CONFIG_DEBUG_FS
4742 stmmac_init_fs(ndev);
4747 error_netdev_register:
4748 phylink_destroy(priv->phylink);
4750 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4751 priv->hw->pcs != STMMAC_PCS_TBI &&
4752 priv->hw->pcs != STMMAC_PCS_RTBI)
4753 stmmac_mdio_unregister(ndev);
4754 error_mdio_register:
4755 for (queue = 0; queue < maxq; queue++) {
4756 struct stmmac_channel *ch = &priv->channel[queue];
4758 if (queue < priv->plat->rx_queues_to_use)
4759 netif_napi_del(&ch->rx_napi);
4760 if (queue < priv->plat->tx_queues_to_use)
4761 netif_napi_del(&ch->tx_napi);
4764 destroy_workqueue(priv->wq);
4768 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
4772 * @dev: device pointer
4773 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
4774 * changes the link status, releases the DMA descriptor rings.
4776 int stmmac_dvr_remove(struct device *dev)
4778 struct net_device *ndev = dev_get_drvdata(dev);
4779 struct stmmac_priv *priv = netdev_priv(ndev);
4781 netdev_info(priv->dev, "%s: removing driver", __func__);
4783 #ifdef CONFIG_DEBUG_FS
4784 stmmac_exit_fs(ndev);
4786 stmmac_stop_all_dma(priv);
4788 stmmac_mac_set(priv, priv->ioaddr, false);
4789 netif_carrier_off(ndev);
4790 unregister_netdev(ndev);
4791 phylink_destroy(priv->phylink);
4792 if (priv->plat->stmmac_rst)
4793 reset_control_assert(priv->plat->stmmac_rst);
4794 clk_disable_unprepare(priv->plat->pclk);
4795 clk_disable_unprepare(priv->plat->stmmac_clk);
4796 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4797 priv->hw->pcs != STMMAC_PCS_TBI &&
4798 priv->hw->pcs != STMMAC_PCS_RTBI)
4799 stmmac_mdio_unregister(ndev);
4800 destroy_workqueue(priv->wq);
4801 mutex_destroy(&priv->lock);
4805 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
4808 * stmmac_suspend - suspend callback
4809 * @dev: device pointer
4810 * Description: this is the function to suspend the device and it is called
4811 * by the platform driver to stop the network queue, release the resources,
4812 * program the PMT register (for WoL), clean and release driver resources.
4814 int stmmac_suspend(struct device *dev)
4816 struct net_device *ndev = dev_get_drvdata(dev);
4817 struct stmmac_priv *priv = netdev_priv(ndev);
4819 if (!ndev || !netif_running(ndev))
4822 phylink_mac_change(priv->phylink, false);
4824 mutex_lock(&priv->lock);
4826 netif_device_detach(ndev);
4827 stmmac_stop_all_queues(priv);
4829 stmmac_disable_all_queues(priv);
4831 /* Stop TX/RX DMA */
4832 stmmac_stop_all_dma(priv);
4834 /* Enable Power down mode by programming the PMT regs */
4835 if (device_may_wakeup(priv->device)) {
4836 stmmac_pmt(priv, priv->hw, priv->wolopts);
4839 mutex_unlock(&priv->lock);
4841 phylink_stop(priv->phylink);
4843 mutex_lock(&priv->lock);
4845 stmmac_mac_set(priv, priv->ioaddr, false);
4846 pinctrl_pm_select_sleep_state(priv->device);
4847 /* Disable clock in case of PWM is off */
4848 if (priv->plat->clk_ptp_ref)
4849 clk_disable_unprepare(priv->plat->clk_ptp_ref);
4850 clk_disable_unprepare(priv->plat->pclk);
4851 clk_disable_unprepare(priv->plat->stmmac_clk);
4853 mutex_unlock(&priv->lock);
4855 priv->speed = SPEED_UNKNOWN;
4858 EXPORT_SYMBOL_GPL(stmmac_suspend);
4861 * stmmac_reset_queues_param - reset queue parameters
4862 * @dev: device pointer
4864 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
4866 u32 rx_cnt = priv->plat->rx_queues_to_use;
4867 u32 tx_cnt = priv->plat->tx_queues_to_use;
4870 for (queue = 0; queue < rx_cnt; queue++) {
4871 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4877 for (queue = 0; queue < tx_cnt; queue++) {
4878 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4887 * stmmac_resume - resume callback
4888 * @dev: device pointer
4889 * Description: when resume this function is invoked to setup the DMA and CORE
4890 * in a usable state.
4892 int stmmac_resume(struct device *dev)
4894 struct net_device *ndev = dev_get_drvdata(dev);
4895 struct stmmac_priv *priv = netdev_priv(ndev);
4897 if (!netif_running(ndev))
4900 /* Power Down bit, into the PM register, is cleared
4901 * automatically as soon as a magic packet or a Wake-up frame
4902 * is received. Anyway, it's better to manually clear
4903 * this bit because it can generate problems while resuming
4904 * from another devices (e.g. serial console).
4906 if (device_may_wakeup(priv->device)) {
4907 mutex_lock(&priv->lock);
4908 stmmac_pmt(priv, priv->hw, 0);
4909 mutex_unlock(&priv->lock);
4912 pinctrl_pm_select_default_state(priv->device);
4913 /* enable the clk previously disabled */
4914 clk_prepare_enable(priv->plat->stmmac_clk);
4915 clk_prepare_enable(priv->plat->pclk);
4916 if (priv->plat->clk_ptp_ref)
4917 clk_prepare_enable(priv->plat->clk_ptp_ref);
4918 /* reset the phy so that it's ready */
4920 stmmac_mdio_reset(priv->mii);
4923 netif_device_attach(ndev);
4925 mutex_lock(&priv->lock);
4927 stmmac_reset_queues_param(priv);
4929 stmmac_clear_descriptors(priv);
4931 stmmac_hw_setup(ndev, false);
4932 stmmac_init_coalesce(priv);
4933 stmmac_set_rx_mode(ndev);
4935 stmmac_enable_all_queues(priv);
4937 stmmac_start_all_queues(priv);
4939 mutex_unlock(&priv->lock);
4941 if (!device_may_wakeup(priv->device)) {
4943 phylink_start(priv->phylink);
4947 phylink_mac_change(priv->phylink, true);
4951 EXPORT_SYMBOL_GPL(stmmac_resume);
4954 static int __init stmmac_cmdline_opt(char *str)
4960 while ((opt = strsep(&str, ",")) != NULL) {
4961 if (!strncmp(opt, "debug:", 6)) {
4962 if (kstrtoint(opt + 6, 0, &debug))
4964 } else if (!strncmp(opt, "phyaddr:", 8)) {
4965 if (kstrtoint(opt + 8, 0, &phyaddr))
4967 } else if (!strncmp(opt, "buf_sz:", 7)) {
4968 if (kstrtoint(opt + 7, 0, &buf_sz))
4970 } else if (!strncmp(opt, "tc:", 3)) {
4971 if (kstrtoint(opt + 3, 0, &tc))
4973 } else if (!strncmp(opt, "watchdog:", 9)) {
4974 if (kstrtoint(opt + 9, 0, &watchdog))
4976 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
4977 if (kstrtoint(opt + 10, 0, &flow_ctrl))
4979 } else if (!strncmp(opt, "pause:", 6)) {
4980 if (kstrtoint(opt + 6, 0, &pause))
4982 } else if (!strncmp(opt, "eee_timer:", 10)) {
4983 if (kstrtoint(opt + 10, 0, &eee_timer))
4985 } else if (!strncmp(opt, "chain_mode:", 11)) {
4986 if (kstrtoint(opt + 11, 0, &chain_mode))
4993 pr_err("%s: ERROR broken module parameter conversion", __func__);
4997 __setup("stmmaceth=", stmmac_cmdline_opt);
5000 static int __init stmmac_init(void)
5002 #ifdef CONFIG_DEBUG_FS
5003 /* Create debugfs main directory if it doesn't exist yet */
5005 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
5011 static void __exit stmmac_exit(void)
5013 #ifdef CONFIG_DEBUG_FS
5014 debugfs_remove_recursive(stmmac_fs_dir);
5018 module_init(stmmac_init)
5019 module_exit(stmmac_exit)
5021 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
5022 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
5023 MODULE_LICENSE("GPL");