drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*******************************************************************************
   3   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   4   ST Ethernet IPs are built around a Synopsys IP Core.
   5
   6         Copyright(C) 2007-2011 STMicroelectronics Ltd
   7
   8
   9   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  10
  11   Documentation available at:
  12         http://www.stlinux.com
  13   Support available at:
  14         https://bugzilla.stlinux.com/
  15 *******************************************************************************/
  16
  17 #include <linux/clk.h>
  18 #include <linux/kernel.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ip.h>
  21 #include <linux/tcp.h>
  22 #include <linux/skbuff.h>
  23 #include <linux/ethtool.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/crc32.h>
  26 #include <linux/mii.h>
  27 #include <linux/if.h>
  28 #include <linux/if_vlan.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/slab.h>
  31 #include <linux/prefetch.h>
  32 #include <linux/pinctrl/consumer.h>
  33 #ifdef CONFIG_DEBUG_FS
  34 #include <linux/debugfs.h>
  35 #include <linux/seq_file.h>
  36 #endif /* CONFIG_DEBUG_FS */
  37 #include <linux/net_tstamp.h>
  38 #include <linux/phylink.h>
  39 #include <linux/udp.h>
  40 #include <net/pkt_cls.h>
  41 #include "stmmac_ptp.h"
  42 #include "stmmac.h"
  43 #include <linux/reset.h>
  44 #include <linux/of_mdio.h>
  45 #include "dwmac1000.h"
  46 #include "dwxgmac2.h"
  47 #include "hwif.h"
  48
  49 #define STMMAC_ALIGN(x)         ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16)
  50 #define TSO_MAX_BUFF_SIZE       (SZ_16K - 1)
  51
  52 /* Module parameters */
  53 #define TX_TIMEO        5000
  54 static int watchdog = TX_TIMEO;
  55 module_param(watchdog, int, 0644);
  56 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  57
  58 static int debug = -1;
  59 module_param(debug, int, 0644);
  60 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  61
  62 static int phyaddr = -1;
  63 module_param(phyaddr, int, 0444);
  64 MODULE_PARM_DESC(phyaddr, "Physical device address");
  65
  66 #define STMMAC_TX_THRESH        (DMA_TX_SIZE / 4)
  67 #define STMMAC_RX_THRESH        (DMA_RX_SIZE / 4)
  68
  69 static int flow_ctrl = FLOW_AUTO;
  70 module_param(flow_ctrl, int, 0644);
  71 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
  72
  73 static int pause = PAUSE_TIME;
  74 module_param(pause, int, 0644);
  75 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
  76
  77 #define TC_DEFAULT 64
  78 static int tc = TC_DEFAULT;
  79 module_param(tc, int, 0644);
  80 MODULE_PARM_DESC(tc, "DMA threshold control value");
  81
  82 #define DEFAULT_BUFSIZE 1536
  83 static int buf_sz = DEFAULT_BUFSIZE;
  84 module_param(buf_sz, int, 0644);
  85 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
  86
  87 #define STMMAC_RX_COPYBREAK     256
  88
  89 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
  90                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
  91                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
  92
  93 #define STMMAC_DEFAULT_LPI_TIMER        1000
  94 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
  95 module_param(eee_timer, int, 0644);
  96 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
  97 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
  98
  99 /* By default the driver will use the ring mode to manage tx and rx descriptors,
 100  * but allow user to force to use the chain instead of the ring
 101  */
 102 static unsigned int chain_mode;
 103 module_param(chain_mode, int, 0444);
 104 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 105
 106 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 107
 108 #ifdef CONFIG_DEBUG_FS
 109 static void stmmac_init_fs(struct net_device *dev);
 110 static void stmmac_exit_fs(struct net_device *dev);
 111 #endif
 112
 113 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 114
 115 /**
 116  * stmmac_verify_args - verify the driver parameters.
 117  * Description: it checks the driver parameters and set a default in case of
 118  * errors.
 119  */
 120 static void stmmac_verify_args(void)
 121 {
 122         if (unlikely(watchdog < 0))
 123                 watchdog = TX_TIMEO;
 124         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
 125                 buf_sz = DEFAULT_BUFSIZE;
 126         if (unlikely(flow_ctrl > 1))
 127                 flow_ctrl = FLOW_AUTO;
 128         else if (likely(flow_ctrl < 0))
 129                 flow_ctrl = FLOW_OFF;
 130         if (unlikely((pause < 0) || (pause > 0xffff)))
 131                 pause = PAUSE_TIME;
 132         if (eee_timer < 0)
 133                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 134 }
 135
 136 /**
 137  * stmmac_disable_all_queues - Disable all queues
 138  * @priv: driver private structure
 139  */
 140 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
 141 {
 142         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 143         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 144         u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
 145         u32 queue;
 146
 147         for (queue = 0; queue < maxq; queue++) {
 148                 struct stmmac_channel *ch = &priv->channel[queue];
 149
 150                 if (queue < rx_queues_cnt)
 151                         napi_disable(&ch->rx_napi);
 152                 if (queue < tx_queues_cnt)
 153                         napi_disable(&ch->tx_napi);
 154         }
 155 }
 156
 157 /**
 158  * stmmac_enable_all_queues - Enable all queues
 159  * @priv: driver private structure
 160  */
 161 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
 162 {
 163         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 164         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 165         u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
 166         u32 queue;
 167
 168         for (queue = 0; queue < maxq; queue++) {
 169                 struct stmmac_channel *ch = &priv->channel[queue];
 170
 171                 if (queue < rx_queues_cnt)
 172                         napi_enable(&ch->rx_napi);
 173                 if (queue < tx_queues_cnt)
 174                         napi_enable(&ch->tx_napi);
 175         }
 176 }
 177
 178 /**
 179  * stmmac_stop_all_queues - Stop all queues
 180  * @priv: driver private structure
 181  */
 182 static void stmmac_stop_all_queues(struct stmmac_priv *priv)
 183 {
 184         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 185         u32 queue;
 186
 187         for (queue = 0; queue < tx_queues_cnt; queue++)
 188                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
 189 }
 190
 191 /**
 192  * stmmac_start_all_queues - Start all queues
 193  * @priv: driver private structure
 194  */
 195 static void stmmac_start_all_queues(struct stmmac_priv *priv)
 196 {
 197         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 198         u32 queue;
 199
 200         for (queue = 0; queue < tx_queues_cnt; queue++)
 201                 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue));
 202 }
 203
 204 static void stmmac_service_event_schedule(struct stmmac_priv *priv)
 205 {
 206         if (!test_bit(STMMAC_DOWN, &priv->state) &&
 207             !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state))
 208                 queue_work(priv->wq, &priv->service_task);
 209 }
 210
 211 static void stmmac_global_err(struct stmmac_priv *priv)
 212 {
 213         netif_carrier_off(priv->dev);
 214         set_bit(STMMAC_RESET_REQUESTED, &priv->state);
 215         stmmac_service_event_schedule(priv);
 216 }
 217
 218 /**
 219  * stmmac_clk_csr_set - dynamically set the MDC clock
 220  * @priv: driver private structure
 221  * Description: this is to dynamically set the MDC clock according to the csr
 222  * clock input.
 223  * Note:
 224  *      If a specific clk_csr value is passed from the platform
 225  *      this means that the CSR Clock Range selection cannot be
 226  *      changed at run-time and it is fixed (as reported in the driver
 227  *      documentation). Viceversa the driver will try to set the MDC
 228  *      clock dynamically according to the actual clock input.
 229  */
 230 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 231 {
 232         u32 clk_rate;
 233
 234         clk_rate = clk_get_rate(priv->plat->stmmac_clk);
 235
 236         /* Platform provided default clk_csr would be assumed valid
 237          * for all other cases except for the below mentioned ones.
 238          * For values higher than the IEEE 802.3 specified frequency
 239          * we can not estimate the proper divider as it is not known
 240          * the frequency of clk_csr_i. So we do not change the default
 241          * divider.
 242          */
 243         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 244                 if (clk_rate < CSR_F_35M)
 245                         priv->clk_csr = STMMAC_CSR_20_35M;
 246                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 247                         priv->clk_csr = STMMAC_CSR_35_60M;
 248                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 249                         priv->clk_csr = STMMAC_CSR_60_100M;
 250                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 251                         priv->clk_csr = STMMAC_CSR_100_150M;
 252                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 253                         priv->clk_csr = STMMAC_CSR_150_250M;
 254                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 255                         priv->clk_csr = STMMAC_CSR_250_300M;
 256         }
 257
 258         if (priv->plat->has_sun8i) {
 259                 if (clk_rate > 160000000)
 260                         priv->clk_csr = 0x03;
 261                 else if (clk_rate > 80000000)
 262                         priv->clk_csr = 0x02;
 263                 else if (clk_rate > 40000000)
 264                         priv->clk_csr = 0x01;
 265                 else
 266                         priv->clk_csr = 0;
 267         }
 268
 269         if (priv->plat->has_xgmac) {
 270                 if (clk_rate > 400000000)
 271                         priv->clk_csr = 0x5;
 272                 else if (clk_rate > 350000000)
 273                         priv->clk_csr = 0x4;
 274                 else if (clk_rate > 300000000)
 275                         priv->clk_csr = 0x3;
 276                 else if (clk_rate > 250000000)
 277                         priv->clk_csr = 0x2;
 278                 else if (clk_rate > 150000000)
 279                         priv->clk_csr = 0x1;
 280                 else
 281                         priv->clk_csr = 0x0;
 282         }
 283 }
 284
 285 static void print_pkt(unsigned char *buf, int len)
 286 {
 287         pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
 288         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
 289 }
 290
 291 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
 292 {
 293         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
 294         u32 avail;
 295
 296         if (tx_q->dirty_tx > tx_q->cur_tx)
 297                 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
 298         else
 299                 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1;
 300
 301         return avail;
 302 }
 303
 304 /**
 305  * stmmac_rx_dirty - Get RX queue dirty
 306  * @priv: driver private structure
 307  * @queue: RX queue index
 308  */
 309 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
 310 {
 311         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
 312         u32 dirty;
 313
 314         if (rx_q->dirty_rx <= rx_q->cur_rx)
 315                 dirty = rx_q->cur_rx - rx_q->dirty_rx;
 316         else
 317                 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx;
 318
 319         return dirty;
 320 }
 321
 322 /**
 323  * stmmac_enable_eee_mode - check and enter in LPI mode
 324  * @priv: driver private structure
 325  * Description: this function is to verify and enter in LPI mode in case of
 326  * EEE.
 327  */
 328 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 329 {
 330         u32 tx_cnt = priv->plat->tx_queues_to_use;
 331         u32 queue;
 332
 333         /* check if all TX queues have the work finished */
 334         for (queue = 0; queue < tx_cnt; queue++) {
 335                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
 336
 337                 if (tx_q->dirty_tx != tx_q->cur_tx)
 338                         return; /* still unfinished work */
 339         }
 340
 341         /* Check and enter in LPI mode */
 342         if (!priv->tx_path_in_lpi_mode)
 343                 stmmac_set_eee_mode(priv, priv->hw,
 344                                 priv->plat->en_tx_lpi_clockgating);
 345 }
 346
 347 /**
 348  * stmmac_disable_eee_mode - disable and exit from LPI mode
 349  * @priv: driver private structure
 350  * Description: this function is to exit and disable EEE in case of
 351  * LPI state is true. This is called by the xmit.
 352  */
 353 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 354 {
 355         stmmac_reset_eee_mode(priv, priv->hw);
 356         del_timer_sync(&priv->eee_ctrl_timer);
 357         priv->tx_path_in_lpi_mode = false;
 358 }
 359
 360 /**
 361  * stmmac_eee_ctrl_timer - EEE TX SW timer.
 362  * @arg : data hook
 363  * Description:
 364  *  if there is no data transfer and if we are not in LPI state,
 365  *  then MAC Transmitter can be moved to LPI state.
 366  */
 367 static void stmmac_eee_ctrl_timer(struct timer_list *t)
 368 {
 369         struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer);
 370
 371         stmmac_enable_eee_mode(priv);
 372         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 373 }
 374
 375 /**
 376  * stmmac_eee_init - init EEE
 377  * @priv: driver private structure
 378  * Description:
 379  *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
 380  *  can also manage EEE, this function enable the LPI state and start related
 381  *  timer.
 382  */
 383 bool stmmac_eee_init(struct stmmac_priv *priv)
 384 {
 385         int tx_lpi_timer = priv->tx_lpi_timer;
 386
 387         /* Using PCS we cannot dial with the phy registers at this stage
 388          * so we do not support extra feature like EEE.
 389          */
 390         if ((priv->hw->pcs == STMMAC_PCS_RGMII) ||
 391             (priv->hw->pcs == STMMAC_PCS_TBI) ||
 392             (priv->hw->pcs == STMMAC_PCS_RTBI))
 393                 return false;
 394
 395         /* Check if MAC core supports the EEE feature. */
 396         if (!priv->dma_cap.eee)
 397                 return false;
 398
 399         mutex_lock(&priv->lock);
 400
 401         /* Check if it needs to be deactivated */
 402         if (!priv->eee_active) {
 403                 if (priv->eee_enabled) {
 404                         netdev_dbg(priv->dev, "disable EEE\n");
 405                         del_timer_sync(&priv->eee_ctrl_timer);
 406                         stmmac_set_eee_timer(priv, priv->hw, 0, tx_lpi_timer);
 407                 }
 408                 mutex_unlock(&priv->lock);
 409                 return false;
 410         }
 411
 412         if (priv->eee_active && !priv->eee_enabled) {
 413                 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0);
 414                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 415                 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS,
 416                                      tx_lpi_timer);
 417         }
 418
 419         mutex_unlock(&priv->lock);
 420         netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
 421         return true;
 422 }
 423
 424 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
 425  * @priv: driver private structure
 426  * @p : descriptor pointer
 427  * @skb : the socket buffer
 428  * Description :
 429  * This function will read timestamp from the descriptor & pass it to stack.
 430  * and also perform some sanity checks.
 431  */
 432 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 433                                    struct dma_desc *p, struct sk_buff *skb)
 434 {
 435         struct skb_shared_hwtstamps shhwtstamp;
 436         bool found = false;
 437         u64 ns = 0;
 438
 439         if (!priv->hwts_tx_en)
 440                 return;
 441
 442         /* exit if skb doesn't support hw tstamp */
 443         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 444                 return;
 445
 446         /* check tx tstamp status */
 447         if (stmmac_get_tx_timestamp_status(priv, p)) {
 448                 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
 449                 found = true;
 450         } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) {
 451                 found = true;
 452         }
 453
 454         if (found) {
 455                 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 456                 shhwtstamp.hwtstamp = ns_to_ktime(ns);
 457
 458                 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
 459                 /* pass tstamp to stack */
 460                 skb_tstamp_tx(skb, &shhwtstamp);
 461         }
 462 }
 463
 464 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
 465  * @priv: driver private structure
 466  * @p : descriptor pointer
 467  * @np : next descriptor pointer
 468  * @skb : the socket buffer
 469  * Description :
 470  * This function will read received packet's timestamp from the descriptor
 471  * and pass it to stack. It also perform some sanity checks.
 472  */
 473 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
 474                                    struct dma_desc *np, struct sk_buff *skb)
 475 {
 476         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 477         struct dma_desc *desc = p;
 478         u64 ns = 0;
 479
 480         if (!priv->hwts_rx_en)
 481                 return;
 482         /* For GMAC4, the valid timestamp is from CTX next desc. */
 483         if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
 484                 desc = np;
 485
 486         /* Check if timestamp is available */
 487         if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
 488                 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
 489                 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
 490                 shhwtstamp = skb_hwtstamps(skb);
 491                 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 492                 shhwtstamp->hwtstamp = ns_to_ktime(ns);
 493         } else  {
 494                 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
 495         }
 496 }
 497
 498 /**
 499  *  stmmac_hwtstamp_set - control hardware timestamping.
 500  *  @dev: device pointer.
 501  *  @ifr: An IOCTL specific structure, that can contain a pointer to
 502  *  a proprietary structure used to pass information to the driver.
 503  *  Description:
 504  *  This function configures the MAC to enable/disable both outgoing(TX)
 505  *  and incoming(RX) packets time stamping based on user input.
 506  *  Return Value:
 507  *  0 on success and an appropriate -ve integer on failure.
 508  */
 509 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
 510 {
 511         struct stmmac_priv *priv = netdev_priv(dev);
 512         struct hwtstamp_config config;
 513         struct timespec64 now;
 514         u64 temp = 0;
 515         u32 ptp_v2 = 0;
 516         u32 tstamp_all = 0;
 517         u32 ptp_over_ipv4_udp = 0;
 518         u32 ptp_over_ipv6_udp = 0;
 519         u32 ptp_over_ethernet = 0;
 520         u32 snap_type_sel = 0;
 521         u32 ts_master_en = 0;
 522         u32 ts_event_en = 0;
 523         u32 sec_inc = 0;
 524         u32 value = 0;
 525         bool xmac;
 526
 527         xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
 528
 529         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 530                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 531                 priv->hwts_tx_en = 0;
 532                 priv->hwts_rx_en = 0;
 533
 534                 return -EOPNOTSUPP;
 535         }
 536
 537         if (copy_from_user(&config, ifr->ifr_data,
 538                            sizeof(config)))
 539                 return -EFAULT;
 540
 541         netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 542                    __func__, config.flags, config.tx_type, config.rx_filter);
 543
 544         /* reserved for future extensions */
 545         if (config.flags)
 546                 return -EINVAL;
 547
 548         if (config.tx_type != HWTSTAMP_TX_OFF &&
 549             config.tx_type != HWTSTAMP_TX_ON)
 550                 return -ERANGE;
 551
 552         if (priv->adv_ts) {
 553                 switch (config.rx_filter) {
 554                 case HWTSTAMP_FILTER_NONE:
 555                         /* time stamp no incoming packet at all */
 556                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 557                         break;
 558
 559                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 560                         /* PTP v1, UDP, any kind of event packet */
 561                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 562                         /* 'xmac' hardware can support Sync, Pdelay_Req and
 563                          * Pdelay_resp by setting bit14 and bits17/16 to 01
 564                          * This leaves Delay_Req timestamps out.
 565                          * Enable all events *and* general purpose message
 566                          * timestamping
 567                          */
 568                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 569                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 570                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 571                         break;
 572
 573                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 574                         /* PTP v1, UDP, Sync packet */
 575                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 576                         /* take time stamp for SYNC messages only */
 577                         ts_event_en = PTP_TCR_TSEVNTENA;
 578
 579                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 580                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 581                         break;
 582
 583                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 584                         /* PTP v1, UDP, Delay_req packet */
 585                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 586                         /* take time stamp for Delay_Req messages only */
 587                         ts_master_en = PTP_TCR_TSMSTRENA;
 588                         ts_event_en = PTP_TCR_TSEVNTENA;
 589
 590                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 591                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 592                         break;
 593
 594                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 595                         /* PTP v2, UDP, any kind of event packet */
 596                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 597                         ptp_v2 = PTP_TCR_TSVER2ENA;
 598                         /* take time stamp for all event messages */
 599                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 600
 601                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 602                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 603                         break;
 604
 605                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 606                         /* PTP v2, UDP, Sync packet */
 607                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 608                         ptp_v2 = PTP_TCR_TSVER2ENA;
 609                         /* take time stamp for SYNC messages only */
 610                         ts_event_en = PTP_TCR_TSEVNTENA;
 611
 612                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 613                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 614                         break;
 615
 616                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 617                         /* PTP v2, UDP, Delay_req packet */
 618                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 619                         ptp_v2 = PTP_TCR_TSVER2ENA;
 620                         /* take time stamp for Delay_Req messages only */
 621                         ts_master_en = PTP_TCR_TSMSTRENA;
 622                         ts_event_en = PTP_TCR_TSEVNTENA;
 623
 624                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 625                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 626                         break;
 627
 628                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 629                         /* PTP v2/802.AS1 any layer, any kind of event packet */
 630                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 631                         ptp_v2 = PTP_TCR_TSVER2ENA;
 632                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 633                         ts_event_en = PTP_TCR_TSEVNTENA;
 634                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 635                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 636                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 637                         break;
 638
 639                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 640                         /* PTP v2/802.AS1, any layer, Sync packet */
 641                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 642                         ptp_v2 = PTP_TCR_TSVER2ENA;
 643                         /* take time stamp for SYNC messages only */
 644                         ts_event_en = PTP_TCR_TSEVNTENA;
 645
 646                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 647                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 648                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 649                         break;
 650
 651                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 652                         /* PTP v2/802.AS1, any layer, Delay_req packet */
 653                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 654                         ptp_v2 = PTP_TCR_TSVER2ENA;
 655                         /* take time stamp for Delay_Req messages only */
 656                         ts_master_en = PTP_TCR_TSMSTRENA;
 657                         ts_event_en = PTP_TCR_TSEVNTENA;
 658
 659                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 660                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 661                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 662                         break;
 663
 664                 case HWTSTAMP_FILTER_NTP_ALL:
 665                 case HWTSTAMP_FILTER_ALL:
 666                         /* time stamp any incoming packet */
 667                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 668                         tstamp_all = PTP_TCR_TSENALL;
 669                         break;
 670
 671                 default:
 672                         return -ERANGE;
 673                 }
 674         } else {
 675                 switch (config.rx_filter) {
 676                 case HWTSTAMP_FILTER_NONE:
 677                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 678                         break;
 679                 default:
 680                         /* PTP v1, UDP, any kind of event packet */
 681                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 682                         break;
 683                 }
 684         }
 685         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 686         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
 687
 688         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
 689                 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0);
 690         else {
 691                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
 692                          tstamp_all | ptp_v2 | ptp_over_ethernet |
 693                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
 694                          ts_master_en | snap_type_sel);
 695                 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value);
 696
 697                 /* program Sub Second Increment reg */
 698                 stmmac_config_sub_second_increment(priv,
 699                                 priv->ptpaddr, priv->plat->clk_ptp_rate,
 700                                 xmac, &sec_inc);
 701                 temp = div_u64(1000000000ULL, sec_inc);
 702
 703                 /* Store sub second increment and flags for later use */
 704                 priv->sub_second_inc = sec_inc;
 705                 priv->systime_flags = value;
 706
 707                 /* calculate default added value:
 708                  * formula is :
 709                  * addend = (2^32)/freq_div_ratio;
 710                  * where, freq_div_ratio = 1e9ns/sec_inc
 711                  */
 712                 temp = (u64)(temp << 32);
 713                 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
 714                 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);
 715
 716                 /* initialize system time */
 717                 ktime_get_real_ts64(&now);
 718
 719                 /* lower 32 bits of tv_sec are safe until y2106 */
 720                 stmmac_init_systime(priv, priv->ptpaddr,
 721                                 (u32)now.tv_sec, now.tv_nsec);
 722         }
 723
 724         memcpy(&priv->tstamp_config, &config, sizeof(config));
 725
 726         return copy_to_user(ifr->ifr_data, &config,
 727                             sizeof(config)) ? -EFAULT : 0;
 728 }
 729
 730 /**
 731  *  stmmac_hwtstamp_get - read hardware timestamping.
 732  *  @dev: device pointer.
 733  *  @ifr: An IOCTL specific structure, that can contain a pointer to
 734  *  a proprietary structure used to pass information to the driver.
 735  *  Description:
 736  *  This function obtain the current hardware timestamping settings
 737     as requested.
 738  */
 739 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
 740 {
 741         struct stmmac_priv *priv = netdev_priv(dev);
 742         struct hwtstamp_config *config = &priv->tstamp_config;
 743
 744         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 745                 return -EOPNOTSUPP;
 746
 747         return copy_to_user(ifr->ifr_data, config,
 748                             sizeof(*config)) ? -EFAULT : 0;
 749 }
 750
 751 /**
 752  * stmmac_init_ptp - init PTP
 753  * @priv: driver private structure
 754  * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
 755  * This is done by looking at the HW cap. register.
 756  * This function also registers the ptp driver.
 757  */
 758 static int stmmac_init_ptp(struct stmmac_priv *priv)
 759 {
 760         bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
 761
 762         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 763                 return -EOPNOTSUPP;
 764
 765         priv->adv_ts = 0;
 766         /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */
 767         if (xmac && priv->dma_cap.atime_stamp)
 768                 priv->adv_ts = 1;
 769         /* Dwmac 3.x core with extend_desc can support adv_ts */
 770         else if (priv->extend_desc && priv->dma_cap.atime_stamp)
 771                 priv->adv_ts = 1;
 772
 773         if (priv->dma_cap.time_stamp)
 774                 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
 775
 776         if (priv->adv_ts)
 777                 netdev_info(priv->dev,
 778                             "IEEE 1588-2008 Advanced Timestamp supported\n");
 779
 780         priv->hwts_tx_en = 0;
 781         priv->hwts_rx_en = 0;
 782
 783         stmmac_ptp_register(priv);
 784
 785         return 0;
 786 }
 787
 788 static void stmmac_release_ptp(struct stmmac_priv *priv)
 789 {
 790         if (priv->plat->clk_ptp_ref)
 791                 clk_disable_unprepare(priv->plat->clk_ptp_ref);
 792         stmmac_ptp_unregister(priv);
 793 }
 794
 795 /**
 796  *  stmmac_mac_flow_ctrl - Configure flow control in all queues
 797  *  @priv: driver private structure
 798  *  Description: It is used for configuring the flow control in all queues
 799  */
 800 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
 801 {
 802         u32 tx_cnt = priv->plat->tx_queues_to_use;
 803
 804         stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
 805                         priv->pause, tx_cnt);
 806 }
 807
 808 static void stmmac_validate(struct phylink_config *config,
 809                             unsigned long *supported,
 810                             struct phylink_link_state *state)
 811 {
 812         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 813         __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, };
 814         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 815         int tx_cnt = priv->plat->tx_queues_to_use;
 816         int max_speed = priv->plat->max_speed;
 817
 818         phylink_set(mac_supported, 10baseT_Half);
 819         phylink_set(mac_supported, 10baseT_Full);
 820         phylink_set(mac_supported, 100baseT_Half);
 821         phylink_set(mac_supported, 100baseT_Full);
 822         phylink_set(mac_supported, 1000baseT_Half);
 823         phylink_set(mac_supported, 1000baseT_Full);
 824         phylink_set(mac_supported, 1000baseKX_Full);
 825
 826         phylink_set(mac_supported, Autoneg);
 827         phylink_set(mac_supported, Pause);
 828         phylink_set(mac_supported, Asym_Pause);
 829         phylink_set_port_modes(mac_supported);
 830
 831         /* Cut down 1G if asked to */
 832         if ((max_speed > 0) && (max_speed < 1000)) {
 833                 phylink_set(mask, 1000baseT_Full);
 834                 phylink_set(mask, 1000baseX_Full);
 835         } else if (priv->plat->has_xgmac) {
 836                 if (!max_speed || (max_speed >= 2500)) {
 837                         phylink_set(mac_supported, 2500baseT_Full);
 838                         phylink_set(mac_supported, 2500baseX_Full);
 839                 }
 840                 if (!max_speed || (max_speed >= 5000)) {
 841                         phylink_set(mac_supported, 5000baseT_Full);
 842                 }
 843                 if (!max_speed || (max_speed >= 10000)) {
 844                         phylink_set(mac_supported, 10000baseSR_Full);
 845                         phylink_set(mac_supported, 10000baseLR_Full);
 846                         phylink_set(mac_supported, 10000baseER_Full);
 847                         phylink_set(mac_supported, 10000baseLRM_Full);
 848                         phylink_set(mac_supported, 10000baseT_Full);
 849                         phylink_set(mac_supported, 10000baseKX4_Full);
 850                         phylink_set(mac_supported, 10000baseKR_Full);
 851                 }
 852         }
 853
 854         /* Half-Duplex can only work with single queue */
 855         if (tx_cnt > 1) {
 856                 phylink_set(mask, 10baseT_Half);
 857                 phylink_set(mask, 100baseT_Half);
 858                 phylink_set(mask, 1000baseT_Half);
 859         }
 860
 861         bitmap_and(supported, supported, mac_supported,
 862                    __ETHTOOL_LINK_MODE_MASK_NBITS);
 863         bitmap_andnot(supported, supported, mask,
 864                       __ETHTOOL_LINK_MODE_MASK_NBITS);
 865         bitmap_and(state->advertising, state->advertising, mac_supported,
 866                    __ETHTOOL_LINK_MODE_MASK_NBITS);
 867         bitmap_andnot(state->advertising, state->advertising, mask,
 868                       __ETHTOOL_LINK_MODE_MASK_NBITS);
 869 }
 870
 871 static void stmmac_mac_pcs_get_state(struct phylink_config *config,
 872                                      struct phylink_link_state *state)
 873 {
 874         state->link = 0;
 875 }
 876
 877 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode,
 878                               const struct phylink_link_state *state)
 879 {
 880         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 881         u32 ctrl;
 882
 883         ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 884         ctrl &= ~priv->hw->link.speed_mask;
 885
 886         if (state->interface == PHY_INTERFACE_MODE_USXGMII) {
 887                 switch (state->speed) {
 888                 case SPEED_10000:
 889                         ctrl |= priv->hw->link.xgmii.speed10000;
 890                         break;
 891                 case SPEED_5000:
 892                         ctrl |= priv->hw->link.xgmii.speed5000;
 893                         break;
 894                 case SPEED_2500:
 895                         ctrl |= priv->hw->link.xgmii.speed2500;
 896                         break;
 897                 default:
 898                         return;
 899                 }
 900         } else {
 901                 switch (state->speed) {
 902                 case SPEED_2500:
 903                         ctrl |= priv->hw->link.speed2500;
 904                         break;
 905                 case SPEED_1000:
 906                         ctrl |= priv->hw->link.speed1000;
 907                         break;
 908                 case SPEED_100:
 909                         ctrl |= priv->hw->link.speed100;
 910                         break;
 911                 case SPEED_10:
 912                         ctrl |= priv->hw->link.speed10;
 913                         break;
 914                 default:
 915                         return;
 916                 }
 917         }
 918
 919         priv->speed = state->speed;
 920
 921         if (priv->plat->fix_mac_speed)
 922                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, state->speed);
 923
 924         if (!state->duplex)
 925                 ctrl &= ~priv->hw->link.duplex;
 926         else
 927                 ctrl |= priv->hw->link.duplex;
 928
 929         /* Flow Control operation */
 930         if (state->pause)
 931                 stmmac_mac_flow_ctrl(priv, state->duplex);
 932
 933         writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 934 }
 935
 936 static void stmmac_mac_an_restart(struct phylink_config *config)
 937 {
 938         /* Not Supported */
 939 }
 940
 941 static void stmmac_mac_link_down(struct phylink_config *config,
 942                                  unsigned int mode, phy_interface_t interface)
 943 {
 944         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 945
 946         stmmac_mac_set(priv, priv->ioaddr, false);
 947         priv->eee_active = false;
 948         stmmac_eee_init(priv);
 949         stmmac_set_eee_pls(priv, priv->hw, false);
 950 }
 951
 952 static void stmmac_mac_link_up(struct phylink_config *config,
 953                                unsigned int mode, phy_interface_t interface,
 954                                struct phy_device *phy)
 955 {
 956         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 957
 958         stmmac_mac_set(priv, priv->ioaddr, true);
 959         if (phy && priv->dma_cap.eee) {
 960                 priv->eee_active = phy_init_eee(phy, 1) >= 0;
 961                 priv->eee_enabled = stmmac_eee_init(priv);
 962                 stmmac_set_eee_pls(priv, priv->hw, true);
 963         }
 964 }
 965
 966 static const struct phylink_mac_ops stmmac_phylink_mac_ops = {
 967         .validate = stmmac_validate,
 968         .mac_pcs_get_state = stmmac_mac_pcs_get_state,
 969         .mac_config = stmmac_mac_config,
 970         .mac_an_restart = stmmac_mac_an_restart,
 971         .mac_link_down = stmmac_mac_link_down,
 972         .mac_link_up = stmmac_mac_link_up,
 973 };
 974
 975 /**
 976  * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
 977  * @priv: driver private structure
 978  * Description: this is to verify if the HW supports the PCS.
 979  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
 980  * configured for the TBI, RTBI, or SGMII PHY interface.
 981  */
 982 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
 983 {
 984         int interface = priv->plat->interface;
 985
 986         if (priv->dma_cap.pcs) {
 987                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
 988                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 989                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
 990                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 991                         netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
 992                         priv->hw->pcs = STMMAC_PCS_RGMII;
 993                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
 994                         netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
 995                         priv->hw->pcs = STMMAC_PCS_SGMII;
 996                 }
 997         }
 998 }
 999
1000 /**
1001  * stmmac_init_phy - PHY initialization
1002  * @dev: net device structure
1003  * Description: it initializes the driver's PHY state, and attaches the PHY
1004  * to the mac driver.
1005  *  Return value:
1006  *  0 on success
1007  */
1008 static int stmmac_init_phy(struct net_device *dev)
1009 {
1010         struct stmmac_priv *priv = netdev_priv(dev);
1011         struct device_node *node;
1012         int ret;
1013
1014         node = priv->plat->phylink_node;
1015
1016         if (node)
1017                 ret = phylink_of_phy_connect(priv->phylink, node, 0);
1018
1019         /* Some DT bindings do not set-up the PHY handle. Let's try to
1020          * manually parse it
1021          */
1022         if (!node || ret) {
1023                 int addr = priv->plat->phy_addr;
1024                 struct phy_device *phydev;
1025
1026                 phydev = mdiobus_get_phy(priv->mii, addr);
1027                 if (!phydev) {
1028                         netdev_err(priv->dev, "no phy at addr %d\n", addr);
1029                         return -ENODEV;
1030                 }
1031
1032                 ret = phylink_connect_phy(priv->phylink, phydev);
1033         }
1034
1035         return ret;
1036 }
1037
1038 static int stmmac_phy_setup(struct stmmac_priv *priv)
1039 {
1040         struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
1041         int mode = priv->plat->phy_interface;
1042         struct phylink *phylink;
1043
1044         priv->phylink_config.dev = &priv->dev->dev;
1045         priv->phylink_config.type = PHYLINK_NETDEV;
1046
1047         phylink = phylink_create(&priv->phylink_config, fwnode,
1048                                  mode, &stmmac_phylink_mac_ops);
1049         if (IS_ERR(phylink))
1050                 return PTR_ERR(phylink);
1051
1052         priv->phylink = phylink;
1053         return 0;
1054 }
1055
1056 static void stmmac_display_rx_rings(struct stmmac_priv *priv)
1057 {
1058         u32 rx_cnt = priv->plat->rx_queues_to_use;
1059         void *head_rx;
1060         u32 queue;
1061
1062         /* Display RX rings */
1063         for (queue = 0; queue < rx_cnt; queue++) {
1064                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1065
1066                 pr_info("\tRX Queue %u rings\n", queue);
1067
1068                 if (priv->extend_desc)
1069                         head_rx = (void *)rx_q->dma_erx;
1070                 else
1071                         head_rx = (void *)rx_q->dma_rx;
1072
1073                 /* Display RX ring */
1074                 stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true);
1075         }
1076 }
1077
1078 static void stmmac_display_tx_rings(struct stmmac_priv *priv)
1079 {
1080         u32 tx_cnt = priv->plat->tx_queues_to_use;
1081         void *head_tx;
1082         u32 queue;
1083
1084         /* Display TX rings */
1085         for (queue = 0; queue < tx_cnt; queue++) {
1086                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1087
1088                 pr_info("\tTX Queue %d rings\n", queue);
1089
1090                 if (priv->extend_desc)
1091                         head_tx = (void *)tx_q->dma_etx;
1092                 else
1093                         head_tx = (void *)tx_q->dma_tx;
1094
1095                 stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false);
1096         }
1097 }
1098
1099 static void stmmac_display_rings(struct stmmac_priv *priv)
1100 {
1101         /* Display RX ring */
1102         stmmac_display_rx_rings(priv);
1103
1104         /* Display TX ring */
1105         stmmac_display_tx_rings(priv);
1106 }
1107
1108 static int stmmac_set_bfsize(int mtu, int bufsize)
1109 {
1110         int ret = bufsize;
1111
1112         if (mtu >= BUF_SIZE_8KiB)
1113                 ret = BUF_SIZE_16KiB;
1114         else if (mtu >= BUF_SIZE_4KiB)
1115                 ret = BUF_SIZE_8KiB;
1116         else if (mtu >= BUF_SIZE_2KiB)
1117                 ret = BUF_SIZE_4KiB;
1118         else if (mtu > DEFAULT_BUFSIZE)
1119                 ret = BUF_SIZE_2KiB;
1120         else
1121                 ret = DEFAULT_BUFSIZE;
1122
1123         return ret;
1124 }
1125
1126 /**
1127  * stmmac_clear_rx_descriptors - clear RX descriptors
1128  * @priv: driver private structure
1129  * @queue: RX queue index
1130  * Description: this function is called to clear the RX descriptors
1131  * in case of both basic and extended descriptors are used.
1132  */
1133 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
1134 {
1135         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1136         int i;
1137
1138         /* Clear the RX descriptors */
1139         for (i = 0; i < DMA_RX_SIZE; i++)
1140                 if (priv->extend_desc)
1141                         stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
1142                                         priv->use_riwt, priv->mode,
1143                                         (i == DMA_RX_SIZE - 1),
1144                                         priv->dma_buf_sz);
1145                 else
1146                         stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
1147                                         priv->use_riwt, priv->mode,
1148                                         (i == DMA_RX_SIZE - 1),
1149                                         priv->dma_buf_sz);
1150 }
1151
1152 /**
1153  * stmmac_clear_tx_descriptors - clear tx descriptors
1154  * @priv: driver private structure
1155  * @queue: TX queue index.
1156  * Description: this function is called to clear the TX descriptors
1157  * in case of both basic and extended descriptors are used.
1158  */
1159 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
1160 {
1161         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1162         int i;
1163
1164         /* Clear the TX descriptors */
1165         for (i = 0; i < DMA_TX_SIZE; i++)
1166                 if (priv->extend_desc)
1167                         stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1168                                         priv->mode, (i == DMA_TX_SIZE - 1));
1169                 else
1170                         stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1171                                         priv->mode, (i == DMA_TX_SIZE - 1));
1172 }
1173
1174 /**
1175  * stmmac_clear_descriptors - clear descriptors
1176  * @priv: driver private structure
1177  * Description: this function is called to clear the TX and RX descriptors
1178  * in case of both basic and extended descriptors are used.
1179  */
1180 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
1181 {
1182         u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1183         u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1184         u32 queue;
1185
1186         /* Clear the RX descriptors */
1187         for (queue = 0; queue < rx_queue_cnt; queue++)
1188                 stmmac_clear_rx_descriptors(priv, queue);
1189
1190         /* Clear the TX descriptors */
1191         for (queue = 0; queue < tx_queue_cnt; queue++)
1192                 stmmac_clear_tx_descriptors(priv, queue);
1193 }
1194
1195 /**
1196  * stmmac_init_rx_buffers - init the RX descriptor buffer.
1197  * @priv: driver private structure
1198  * @p: descriptor pointer
1199  * @i: descriptor index
1200  * @flags: gfp flag
1201  * @queue: RX queue index
1202  * Description: this function is called to allocate a receive buffer, perform
1203  * the DMA mapping and init the descriptor.
1204  */
1205 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
1206                                   int i, gfp_t flags, u32 queue)
1207 {
1208         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1209         struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1210
1211         buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
1212         if (!buf->page)
1213                 return -ENOMEM;
1214
1215         if (priv->sph) {
1216                 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool);
1217                 if (!buf->sec_page)
1218                         return -ENOMEM;
1219
1220                 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
1221                 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr);
1222         } else {
1223                 buf->sec_page = NULL;
1224         }
1225
1226         buf->addr = page_pool_get_dma_addr(buf->page);
1227         stmmac_set_desc_addr(priv, p, buf->addr);
1228         if (priv->dma_buf_sz == BUF_SIZE_16KiB)
1229                 stmmac_init_desc3(priv, p);
1230
1231         return 0;
1232 }
1233
1234 /**
1235  * stmmac_free_rx_buffer - free RX dma buffers
1236  * @priv: private structure
1237  * @queue: RX queue index
1238  * @i: buffer index.
1239  */
1240 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1241 {
1242         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1243         struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1244
1245         if (buf->page)
1246                 page_pool_put_page(rx_q->page_pool, buf->page, false);
1247         buf->page = NULL;
1248
1249         if (buf->sec_page)
1250                 page_pool_put_page(rx_q->page_pool, buf->sec_page, false);
1251         buf->sec_page = NULL;
1252 }
1253
1254 /**
1255  * stmmac_free_tx_buffer - free RX dma buffers
1256  * @priv: private structure
1257  * @queue: RX queue index
1258  * @i: buffer index.
1259  */
1260 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1261 {
1262         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1263
1264         if (tx_q->tx_skbuff_dma[i].buf) {
1265                 if (tx_q->tx_skbuff_dma[i].map_as_page)
1266                         dma_unmap_page(priv->device,
1267                                        tx_q->tx_skbuff_dma[i].buf,
1268                                        tx_q->tx_skbuff_dma[i].len,
1269                                        DMA_TO_DEVICE);
1270                 else
1271                         dma_unmap_single(priv->device,
1272                                          tx_q->tx_skbuff_dma[i].buf,
1273                                          tx_q->tx_skbuff_dma[i].len,
1274                                          DMA_TO_DEVICE);
1275         }
1276
1277         if (tx_q->tx_skbuff[i]) {
1278                 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1279                 tx_q->tx_skbuff[i] = NULL;
1280                 tx_q->tx_skbuff_dma[i].buf = 0;
1281                 tx_q->tx_skbuff_dma[i].map_as_page = false;
1282         }
1283 }
1284
1285 /**
1286  * init_dma_rx_desc_rings - init the RX descriptor rings
1287  * @dev: net device structure
1288  * @flags: gfp flag.
1289  * Description: this function initializes the DMA RX descriptors
1290  * and allocates the socket buffers. It supports the chained and ring
1291  * modes.
1292  */
1293 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
1294 {
1295         struct stmmac_priv *priv = netdev_priv(dev);
1296         u32 rx_count = priv->plat->rx_queues_to_use;
1297         int ret = -ENOMEM;
1298         int queue;
1299         int i;
1300
1301         /* RX INITIALIZATION */
1302         netif_dbg(priv, probe, priv->dev,
1303                   "SKB addresses:\nskb\t\tskb data\tdma data\n");
1304
1305         for (queue = 0; queue < rx_count; queue++) {
1306                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1307
1308                 netif_dbg(priv, probe, priv->dev,
1309                           "(%s) dma_rx_phy=0x%08x\n", __func__,
1310                           (u32)rx_q->dma_rx_phy);
1311
1312                 stmmac_clear_rx_descriptors(priv, queue);
1313
1314                 for (i = 0; i < DMA_RX_SIZE; i++) {
1315                         struct dma_desc *p;
1316
1317                         if (priv->extend_desc)
1318                                 p = &((rx_q->dma_erx + i)->basic);
1319                         else
1320                                 p = rx_q->dma_rx + i;
1321
1322                         ret = stmmac_init_rx_buffers(priv, p, i, flags,
1323                                                      queue);
1324                         if (ret)
1325                                 goto err_init_rx_buffers;
1326                 }
1327
1328                 rx_q->cur_rx = 0;
1329                 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1330
1331                 /* Setup the chained descriptor addresses */
1332                 if (priv->mode == STMMAC_CHAIN_MODE) {
1333                         if (priv->extend_desc)
1334                                 stmmac_mode_init(priv, rx_q->dma_erx,
1335                                                 rx_q->dma_rx_phy, DMA_RX_SIZE, 1);
1336                         else
1337                                 stmmac_mode_init(priv, rx_q->dma_rx,
1338                                                 rx_q->dma_rx_phy, DMA_RX_SIZE, 0);
1339                 }
1340         }
1341
1342         return 0;
1343
1344 err_init_rx_buffers:
1345         while (queue >= 0) {
1346                 while (--i >= 0)
1347                         stmmac_free_rx_buffer(priv, queue, i);
1348
1349                 if (queue == 0)
1350                         break;
1351
1352                 i = DMA_RX_SIZE;
1353                 queue--;
1354         }
1355
1356         return ret;
1357 }
1358
1359 /**
1360  * init_dma_tx_desc_rings - init the TX descriptor rings
1361  * @dev: net device structure.
1362  * Description: this function initializes the DMA TX descriptors
1363  * and allocates the socket buffers. It supports the chained and ring
1364  * modes.
1365  */
1366 static int init_dma_tx_desc_rings(struct net_device *dev)
1367 {
1368         struct stmmac_priv *priv = netdev_priv(dev);
1369         u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1370         u32 queue;
1371         int i;
1372
1373         for (queue = 0; queue < tx_queue_cnt; queue++) {
1374                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1375
1376                 netif_dbg(priv, probe, priv->dev,
1377                           "(%s) dma_tx_phy=0x%08x\n", __func__,
1378                          (u32)tx_q->dma_tx_phy);
1379
1380                 /* Setup the chained descriptor addresses */
1381                 if (priv->mode == STMMAC_CHAIN_MODE) {
1382                         if (priv->extend_desc)
1383                                 stmmac_mode_init(priv, tx_q->dma_etx,
1384                                                 tx_q->dma_tx_phy, DMA_TX_SIZE, 1);
1385                         else
1386                                 stmmac_mode_init(priv, tx_q->dma_tx,
1387                                                 tx_q->dma_tx_phy, DMA_TX_SIZE, 0);
1388                 }
1389
1390                 for (i = 0; i < DMA_TX_SIZE; i++) {
1391                         struct dma_desc *p;
1392                         if (priv->extend_desc)
1393                                 p = &((tx_q->dma_etx + i)->basic);
1394                         else
1395                                 p = tx_q->dma_tx + i;
1396
1397                         stmmac_clear_desc(priv, p);
1398
1399                         tx_q->tx_skbuff_dma[i].buf = 0;
1400                         tx_q->tx_skbuff_dma[i].map_as_page = false;
1401                         tx_q->tx_skbuff_dma[i].len = 0;
1402                         tx_q->tx_skbuff_dma[i].last_segment = false;
1403                         tx_q->tx_skbuff[i] = NULL;
1404                 }
1405
1406                 tx_q->dirty_tx = 0;
1407                 tx_q->cur_tx = 0;
1408                 tx_q->mss = 0;
1409
1410                 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
1411         }
1412
1413         return 0;
1414 }
1415
1416 /**
1417  * init_dma_desc_rings - init the RX/TX descriptor rings
1418  * @dev: net device structure
1419  * @flags: gfp flag.
1420  * Description: this function initializes the DMA RX/TX descriptors
1421  * and allocates the socket buffers. It supports the chained and ring
1422  * modes.
1423  */
1424 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1425 {
1426         struct stmmac_priv *priv = netdev_priv(dev);
1427         int ret;
1428
1429         ret = init_dma_rx_desc_rings(dev, flags);
1430         if (ret)
1431                 return ret;
1432
1433         ret = init_dma_tx_desc_rings(dev);
1434
1435         stmmac_clear_descriptors(priv);
1436
1437         if (netif_msg_hw(priv))
1438                 stmmac_display_rings(priv);
1439
1440         return ret;
1441 }
1442
1443 /**
1444  * dma_free_rx_skbufs - free RX dma buffers
1445  * @priv: private structure
1446  * @queue: RX queue index
1447  */
1448 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)
1449 {
1450         int i;
1451
1452         for (i = 0; i < DMA_RX_SIZE; i++)
1453                 stmmac_free_rx_buffer(priv, queue, i);
1454 }
1455
1456 /**
1457  * dma_free_tx_skbufs - free TX dma buffers
1458  * @priv: private structure
1459  * @queue: TX queue index
1460  */
1461 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
1462 {
1463         int i;
1464
1465         for (i = 0; i < DMA_TX_SIZE; i++)
1466                 stmmac_free_tx_buffer(priv, queue, i);
1467 }
1468
1469 /**
1470  * free_dma_rx_desc_resources - free RX dma desc resources
1471  * @priv: private structure
1472  */
1473 static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
1474 {
1475         u32 rx_count = priv->plat->rx_queues_to_use;
1476         u32 queue;
1477
1478         /* Free RX queue resources */
1479         for (queue = 0; queue < rx_count; queue++) {
1480                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1481
1482                 /* Release the DMA RX socket buffers */
1483                 dma_free_rx_skbufs(priv, queue);
1484
1485                 /* Free DMA regions of consistent memory previously allocated */
1486                 if (!priv->extend_desc)
1487                         dma_free_coherent(priv->device,
1488                                           DMA_RX_SIZE * sizeof(struct dma_desc),
1489                                           rx_q->dma_rx, rx_q->dma_rx_phy);
1490                 else
1491                         dma_free_coherent(priv->device, DMA_RX_SIZE *
1492                                           sizeof(struct dma_extended_desc),
1493                                           rx_q->dma_erx, rx_q->dma_rx_phy);
1494
1495                 kfree(rx_q->buf_pool);
1496                 if (rx_q->page_pool)
1497                         page_pool_destroy(rx_q->page_pool);
1498         }
1499 }
1500
1501 /**
1502  * free_dma_tx_desc_resources - free TX dma desc resources
1503  * @priv: private structure
1504  */
1505 static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
1506 {
1507         u32 tx_count = priv->plat->tx_queues_to_use;
1508         u32 queue;
1509
1510         /* Free TX queue resources */
1511         for (queue = 0; queue < tx_count; queue++) {
1512                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1513
1514                 /* Release the DMA TX socket buffers */
1515                 dma_free_tx_skbufs(priv, queue);
1516
1517                 /* Free DMA regions of consistent memory previously allocated */
1518                 if (!priv->extend_desc)
1519                         dma_free_coherent(priv->device,
1520                                           DMA_TX_SIZE * sizeof(struct dma_desc),
1521                                           tx_q->dma_tx, tx_q->dma_tx_phy);
1522                 else
1523                         dma_free_coherent(priv->device, DMA_TX_SIZE *
1524                                           sizeof(struct dma_extended_desc),
1525                                           tx_q->dma_etx, tx_q->dma_tx_phy);
1526
1527                 kfree(tx_q->tx_skbuff_dma);
1528                 kfree(tx_q->tx_skbuff);
1529         }
1530 }
1531
1532 /**
1533  * alloc_dma_rx_desc_resources - alloc RX resources.
1534  * @priv: private structure
1535  * Description: according to which descriptor can be used (extend or basic)
1536  * this function allocates the resources for TX and RX paths. In case of
1537  * reception, for example, it pre-allocated the RX socket buffer in order to
1538  * allow zero-copy mechanism.
1539  */
1540 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
1541 {
1542         u32 rx_count = priv->plat->rx_queues_to_use;
1543         int ret = -ENOMEM;
1544         u32 queue;
1545
1546         /* RX queues buffers and DMA */
1547         for (queue = 0; queue < rx_count; queue++) {
1548                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1549                 struct page_pool_params pp_params = { 0 };
1550                 unsigned int num_pages;
1551
1552                 rx_q->queue_index = queue;
1553                 rx_q->priv_data = priv;
1554
1555                 pp_params.flags = PP_FLAG_DMA_MAP;
1556                 pp_params.pool_size = DMA_RX_SIZE;
1557                 num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE);
1558                 pp_params.order = ilog2(num_pages);
1559                 pp_params.nid = dev_to_node(priv->device);
1560                 pp_params.dev = priv->device;
1561                 pp_params.dma_dir = DMA_FROM_DEVICE;
1562
1563                 rx_q->page_pool = page_pool_create(&pp_params);
1564                 if (IS_ERR(rx_q->page_pool)) {
1565                         ret = PTR_ERR(rx_q->page_pool);
1566                         rx_q->page_pool = NULL;
1567                         goto err_dma;
1568                 }
1569
1570                 rx_q->buf_pool = kcalloc(DMA_RX_SIZE, sizeof(*rx_q->buf_pool),
1571                                          GFP_KERNEL);
1572                 if (!rx_q->buf_pool)
1573                         goto err_dma;
1574
1575                 if (priv->extend_desc) {
1576                         rx_q->dma_erx = dma_alloc_coherent(priv->device,
1577                                                            DMA_RX_SIZE * sizeof(struct dma_extended_desc),
1578                                                            &rx_q->dma_rx_phy,
1579                                                            GFP_KERNEL);
1580                         if (!rx_q->dma_erx)
1581                                 goto err_dma;
1582
1583                 } else {
1584                         rx_q->dma_rx = dma_alloc_coherent(priv->device,
1585                                                           DMA_RX_SIZE * sizeof(struct dma_desc),
1586                                                           &rx_q->dma_rx_phy,
1587                                                           GFP_KERNEL);
1588                         if (!rx_q->dma_rx)
1589                                 goto err_dma;
1590                 }
1591         }
1592
1593         return 0;
1594
1595 err_dma:
1596         free_dma_rx_desc_resources(priv);
1597
1598         return ret;
1599 }
1600
1601 /**
1602  * alloc_dma_tx_desc_resources - alloc TX resources.
1603  * @priv: private structure
1604  * Description: according to which descriptor can be used (extend or basic)
1605  * this function allocates the resources for TX and RX paths. In case of
1606  * reception, for example, it pre-allocated the RX socket buffer in order to
1607  * allow zero-copy mechanism.
1608  */
1609 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
1610 {
1611         u32 tx_count = priv->plat->tx_queues_to_use;
1612         int ret = -ENOMEM;
1613         u32 queue;
1614
1615         /* TX queues buffers and DMA */
1616         for (queue = 0; queue < tx_count; queue++) {
1617                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1618
1619                 tx_q->queue_index = queue;
1620                 tx_q->priv_data = priv;
1621
1622                 tx_q->tx_skbuff_dma = kcalloc(DMA_TX_SIZE,
1623                                               sizeof(*tx_q->tx_skbuff_dma),
1624                                               GFP_KERNEL);
1625                 if (!tx_q->tx_skbuff_dma)
1626                         goto err_dma;
1627
1628                 tx_q->tx_skbuff = kcalloc(DMA_TX_SIZE,
1629                                           sizeof(struct sk_buff *),
1630                                           GFP_KERNEL);
1631                 if (!tx_q->tx_skbuff)
1632                         goto err_dma;
1633
1634                 if (priv->extend_desc) {
1635                         tx_q->dma_etx = dma_alloc_coherent(priv->device,
1636                                                            DMA_TX_SIZE * sizeof(struct dma_extended_desc),
1637                                                            &tx_q->dma_tx_phy,
1638                                                            GFP_KERNEL);
1639                         if (!tx_q->dma_etx)
1640                                 goto err_dma;
1641                 } else {
1642                         tx_q->dma_tx = dma_alloc_coherent(priv->device,
1643                                                           DMA_TX_SIZE * sizeof(struct dma_desc),
1644                                                           &tx_q->dma_tx_phy,
1645                                                           GFP_KERNEL);
1646                         if (!tx_q->dma_tx)
1647                                 goto err_dma;
1648                 }
1649         }
1650
1651         return 0;
1652
1653 err_dma:
1654         free_dma_tx_desc_resources(priv);
1655
1656         return ret;
1657 }
1658
1659 /**
1660  * alloc_dma_desc_resources - alloc TX/RX resources.
1661  * @priv: private structure
1662  * Description: according to which descriptor can be used (extend or basic)
1663  * this function allocates the resources for TX and RX paths. In case of
1664  * reception, for example, it pre-allocated the RX socket buffer in order to
1665  * allow zero-copy mechanism.
1666  */
1667 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1668 {
1669         /* RX Allocation */
1670         int ret = alloc_dma_rx_desc_resources(priv);
1671
1672         if (ret)
1673                 return ret;
1674
1675         ret = alloc_dma_tx_desc_resources(priv);
1676
1677         return ret;
1678 }
1679
1680 /**
1681  * free_dma_desc_resources - free dma desc resources
1682  * @priv: private structure
1683  */
1684 static void free_dma_desc_resources(struct stmmac_priv *priv)
1685 {
1686         /* Release the DMA RX socket buffers */
1687         free_dma_rx_desc_resources(priv);
1688
1689         /* Release the DMA TX socket buffers */
1690         free_dma_tx_desc_resources(priv);
1691 }
1692
1693 /**
1694  *  stmmac_mac_enable_rx_queues - Enable MAC rx queues
1695  *  @priv: driver private structure
1696  *  Description: It is used for enabling the rx queues in the MAC
1697  */
1698 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
1699 {
1700         u32 rx_queues_count = priv->plat->rx_queues_to_use;
1701         int queue;
1702         u8 mode;
1703
1704         for (queue = 0; queue < rx_queues_count; queue++) {
1705                 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
1706                 stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
1707         }
1708 }
1709
1710 /**
1711  * stmmac_start_rx_dma - start RX DMA channel
1712  * @priv: driver private structure
1713  * @chan: RX channel index
1714  * Description:
1715  * This starts a RX DMA channel
1716  */
1717 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
1718 {
1719         netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
1720         stmmac_start_rx(priv, priv->ioaddr, chan);
1721 }
1722
1723 /**
1724  * stmmac_start_tx_dma - start TX DMA channel
1725  * @priv: driver private structure
1726  * @chan: TX channel index
1727  * Description:
1728  * This starts a TX DMA channel
1729  */
1730 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
1731 {
1732         netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
1733         stmmac_start_tx(priv, priv->ioaddr, chan);
1734 }
1735
1736 /**
1737  * stmmac_stop_rx_dma - stop RX DMA channel
1738  * @priv: driver private structure
1739  * @chan: RX channel index
1740  * Description:
1741  * This stops a RX DMA channel
1742  */
1743 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
1744 {
1745         netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
1746         stmmac_stop_rx(priv, priv->ioaddr, chan);
1747 }
1748
1749 /**
1750  * stmmac_stop_tx_dma - stop TX DMA channel
1751  * @priv: driver private structure
1752  * @chan: TX channel index
1753  * Description:
1754  * This stops a TX DMA channel
1755  */
1756 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
1757 {
1758         netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
1759         stmmac_stop_tx(priv, priv->ioaddr, chan);
1760 }
1761
1762 /**
1763  * stmmac_start_all_dma - start all RX and TX DMA channels
1764  * @priv: driver private structure
1765  * Description:
1766  * This starts all the RX and TX DMA channels
1767  */
1768 static void stmmac_start_all_dma(struct stmmac_priv *priv)
1769 {
1770         u32 rx_channels_count = priv->plat->rx_queues_to_use;
1771         u32 tx_channels_count = priv->plat->tx_queues_to_use;
1772         u32 chan = 0;
1773
1774         for (chan = 0; chan < rx_channels_count; chan++)
1775                 stmmac_start_rx_dma(priv, chan);
1776
1777         for (chan = 0; chan < tx_channels_count; chan++)
1778                 stmmac_start_tx_dma(priv, chan);
1779 }
1780
1781 /**
1782  * stmmac_stop_all_dma - stop all RX and TX DMA channels
1783  * @priv: driver private structure
1784  * Description:
1785  * This stops the RX and TX DMA channels
1786  */
1787 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
1788 {
1789         u32 rx_channels_count = priv->plat->rx_queues_to_use;
1790         u32 tx_channels_count = priv->plat->tx_queues_to_use;
1791         u32 chan = 0;
1792
1793         for (chan = 0; chan < rx_channels_count; chan++)
1794                 stmmac_stop_rx_dma(priv, chan);
1795
1796         for (chan = 0; chan < tx_channels_count; chan++)
1797                 stmmac_stop_tx_dma(priv, chan);
1798 }
1799
1800 /**
1801  *  stmmac_dma_operation_mode - HW DMA operation mode
1802  *  @priv: driver private structure
1803  *  Description: it is used for configuring the DMA operation mode register in
1804  *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1805  */
1806 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1807 {
1808         u32 rx_channels_count = priv->plat->rx_queues_to_use;
1809         u32 tx_channels_count = priv->plat->tx_queues_to_use;
1810         int rxfifosz = priv->plat->rx_fifo_size;
1811         int txfifosz = priv->plat->tx_fifo_size;
1812         u32 txmode = 0;
1813         u32 rxmode = 0;
1814         u32 chan = 0;
1815         u8 qmode = 0;
1816
1817         if (rxfifosz == 0)
1818                 rxfifosz = priv->dma_cap.rx_fifo_size;
1819         if (txfifosz == 0)
1820                 txfifosz = priv->dma_cap.tx_fifo_size;
1821
1822         /* Adjust for real per queue fifo size */
1823         rxfifosz /= rx_channels_count;
1824         txfifosz /= tx_channels_count;
1825
1826         if (priv->plat->force_thresh_dma_mode) {
1827                 txmode = tc;
1828                 rxmode = tc;
1829         } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1830                 /*
1831                  * In case of GMAC, SF mode can be enabled
1832                  * to perform the TX COE in HW. This depends on:
1833                  * 1) TX COE if actually supported
1834                  * 2) There is no bugged Jumbo frame support
1835                  *    that needs to not insert csum in the TDES.
1836                  */
1837                 txmode = SF_DMA_MODE;
1838                 rxmode = SF_DMA_MODE;
1839                 priv->xstats.threshold = SF_DMA_MODE;
1840         } else {
1841                 txmode = tc;
1842                 rxmode = SF_DMA_MODE;
1843         }
1844
1845         /* configure all channels */
1846         for (chan = 0; chan < rx_channels_count; chan++) {
1847                 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
1848
1849                 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
1850                                 rxfifosz, qmode);
1851                 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz,
1852                                 chan);
1853         }
1854
1855         for (chan = 0; chan < tx_channels_count; chan++) {
1856                 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
1857
1858                 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
1859                                 txfifosz, qmode);
1860         }
1861 }
1862
1863 /**
1864  * stmmac_tx_clean - to manage the transmission completion
1865  * @priv: driver private structure
1866  * @queue: TX queue index
1867  * Description: it reclaims the transmit resources after transmission completes.
1868  */
1869 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
1870 {
1871         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1872         unsigned int bytes_compl = 0, pkts_compl = 0;
1873         unsigned int entry, count = 0;
1874
1875         __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue));
1876
1877         priv->xstats.tx_clean++;
1878
1879         entry = tx_q->dirty_tx;
1880         while ((entry != tx_q->cur_tx) && (count < budget)) {
1881                 struct sk_buff *skb = tx_q->tx_skbuff[entry];
1882                 struct dma_desc *p;
1883                 int status;
1884
1885                 if (priv->extend_desc)
1886                         p = (struct dma_desc *)(tx_q->dma_etx + entry);
1887                 else
1888                         p = tx_q->dma_tx + entry;
1889
1890                 status = stmmac_tx_status(priv, &priv->dev->stats,
1891                                 &priv->xstats, p, priv->ioaddr);
1892                 /* Check if the descriptor is owned by the DMA */
1893                 if (unlikely(status & tx_dma_own))
1894                         break;
1895
1896                 count++;
1897
1898                 /* Make sure descriptor fields are read after reading
1899                  * the own bit.
1900                  */
1901                 dma_rmb();
1902
1903                 /* Just consider the last segment and ...*/
1904                 if (likely(!(status & tx_not_ls))) {
1905                         /* ... verify the status error condition */
1906                         if (unlikely(status & tx_err)) {
1907                                 priv->dev->stats.tx_errors++;
1908                         } else {
1909                                 priv->dev->stats.tx_packets++;
1910                                 priv->xstats.tx_pkt_n++;
1911                         }
1912                         stmmac_get_tx_hwtstamp(priv, p, skb);
1913                 }
1914
1915                 if (likely(tx_q->tx_skbuff_dma[entry].buf)) {
1916                         if (tx_q->tx_skbuff_dma[entry].map_as_page)
1917                                 dma_unmap_page(priv->device,
1918                                                tx_q->tx_skbuff_dma[entry].buf,
1919                                                tx_q->tx_skbuff_dma[entry].len,
1920                                                DMA_TO_DEVICE);
1921                         else
1922                                 dma_unmap_single(priv->device,
1923                                                  tx_q->tx_skbuff_dma[entry].buf,
1924                                                  tx_q->tx_skbuff_dma[entry].len,
1925                                                  DMA_TO_DEVICE);
1926                         tx_q->tx_skbuff_dma[entry].buf = 0;
1927                         tx_q->tx_skbuff_dma[entry].len = 0;
1928                         tx_q->tx_skbuff_dma[entry].map_as_page = false;
1929                 }
1930
1931                 stmmac_clean_desc3(priv, tx_q, p);
1932
1933                 tx_q->tx_skbuff_dma[entry].last_segment = false;
1934                 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
1935
1936                 if (likely(skb != NULL)) {
1937                         pkts_compl++;
1938                         bytes_compl += skb->len;
1939                         dev_consume_skb_any(skb);
1940                         tx_q->tx_skbuff[entry] = NULL;
1941                 }
1942
1943                 stmmac_release_tx_desc(priv, p, priv->mode);
1944
1945                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1946         }
1947         tx_q->dirty_tx = entry;
1948
1949         netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
1950                                   pkts_compl, bytes_compl);
1951
1952         if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
1953                                                                 queue))) &&
1954             stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) {
1955
1956                 netif_dbg(priv, tx_done, priv->dev,
1957                           "%s: restart transmit\n", __func__);
1958                 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
1959         }
1960
1961         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1962                 stmmac_enable_eee_mode(priv);
1963                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1964         }
1965
1966         /* We still have pending packets, let's call for a new scheduling */
1967         if (tx_q->dirty_tx != tx_q->cur_tx)
1968                 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
1969
1970         __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
1971
1972         return count;
1973 }
1974
1975 /**
1976  * stmmac_tx_err - to manage the tx error
1977  * @priv: driver private structure
1978  * @chan: channel index
1979  * Description: it cleans the descriptors and restarts the transmission
1980  * in case of transmission errors.
1981  */
1982 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
1983 {
1984         struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
1985         int i;
1986
1987         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
1988
1989         stmmac_stop_tx_dma(priv, chan);
1990         dma_free_tx_skbufs(priv, chan);
1991         for (i = 0; i < DMA_TX_SIZE; i++)
1992                 if (priv->extend_desc)
1993                         stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1994                                         priv->mode, (i == DMA_TX_SIZE - 1));
1995                 else
1996                         stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1997                                         priv->mode, (i == DMA_TX_SIZE - 1));
1998         tx_q->dirty_tx = 0;
1999         tx_q->cur_tx = 0;
2000         tx_q->mss = 0;
2001         netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
2002         stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2003                             tx_q->dma_tx_phy, chan);
2004         stmmac_start_tx_dma(priv, chan);
2005
2006         priv->dev->stats.tx_errors++;
2007         netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
2008 }
2009
2010 /**
2011  *  stmmac_set_dma_operation_mode - Set DMA operation mode by channel
2012  *  @priv: driver private structure
2013  *  @txmode: TX operating mode
2014  *  @rxmode: RX operating mode
2015  *  @chan: channel index
2016  *  Description: it is used for configuring of the DMA operation mode in
2017  *  runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
2018  *  mode.
2019  */
2020 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
2021                                           u32 rxmode, u32 chan)
2022 {
2023         u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2024         u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2025         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2026         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2027         int rxfifosz = priv->plat->rx_fifo_size;
2028         int txfifosz = priv->plat->tx_fifo_size;
2029
2030         if (rxfifosz == 0)
2031                 rxfifosz = priv->dma_cap.rx_fifo_size;
2032         if (txfifosz == 0)
2033                 txfifosz = priv->dma_cap.tx_fifo_size;
2034
2035         /* Adjust for real per queue fifo size */
2036         rxfifosz /= rx_channels_count;
2037         txfifosz /= tx_channels_count;
2038
2039         stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode);
2040         stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode);
2041 }
2042
2043 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
2044 {
2045         int ret;
2046
2047         ret = stmmac_safety_feat_irq_status(priv, priv->dev,
2048                         priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
2049         if (ret && (ret != -EINVAL)) {
2050                 stmmac_global_err(priv);
2051                 return true;
2052         }
2053
2054         return false;
2055 }
2056
2057 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan)
2058 {
2059         int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
2060                                                  &priv->xstats, chan);
2061         struct stmmac_channel *ch = &priv->channel[chan];
2062
2063         if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
2064                 if (napi_schedule_prep(&ch->rx_napi)) {
2065                         stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
2066                         __napi_schedule_irqoff(&ch->rx_napi);
2067                         status |= handle_tx;
2068                 }
2069         }
2070
2071         if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use))
2072                 napi_schedule_irqoff(&ch->tx_napi);
2073
2074         return status;
2075 }
2076
2077 /**
2078  * stmmac_dma_interrupt - DMA ISR
2079  * @priv: driver private structure
2080  * Description: this is the DMA ISR. It is called by the main ISR.
2081  * It calls the dwmac dma routine and schedule poll method in case of some
2082  * work can be done.
2083  */
2084 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
2085 {
2086         u32 tx_channel_count = priv->plat->tx_queues_to_use;
2087         u32 rx_channel_count = priv->plat->rx_queues_to_use;
2088         u32 channels_to_check = tx_channel_count > rx_channel_count ?
2089                                 tx_channel_count : rx_channel_count;
2090         u32 chan;
2091         int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
2092
2093         /* Make sure we never check beyond our status buffer. */
2094         if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
2095                 channels_to_check = ARRAY_SIZE(status);
2096
2097         for (chan = 0; chan < channels_to_check; chan++)
2098                 status[chan] = stmmac_napi_check(priv, chan);
2099
2100         for (chan = 0; chan < tx_channel_count; chan++) {
2101                 if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
2102                         /* Try to bump up the dma threshold on this failure */
2103                         if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
2104                             (tc <= 256)) {
2105                                 tc += 64;
2106                                 if (priv->plat->force_thresh_dma_mode)
2107                                         stmmac_set_dma_operation_mode(priv,
2108                                                                       tc,
2109                                                                       tc,
2110                                                                       chan);
2111                                 else
2112                                         stmmac_set_dma_operation_mode(priv,
2113                                                                     tc,
2114                                                                     SF_DMA_MODE,
2115                                                                     chan);
2116                                 priv->xstats.threshold = tc;
2117                         }
2118                 } else if (unlikely(status[chan] == tx_hard_error)) {
2119                         stmmac_tx_err(priv, chan);
2120                 }
2121         }
2122 }
2123
2124 /**
2125  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2126  * @priv: driver private structure
2127  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2128  */
2129 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2130 {
2131         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2132                             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2133
2134         stmmac_mmc_intr_all_mask(priv, priv->mmcaddr);
2135
2136         if (priv->dma_cap.rmon) {
2137                 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode);
2138                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2139         } else
2140                 netdev_info(priv->dev, "No MAC Management Counters available\n");
2141 }
2142
2143 /**
2144  * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2145  * @priv: driver private structure
2146  * Description:
2147  *  new GMAC chip generations have a new register to indicate the
2148  *  presence of the optional feature/functions.
2149  *  This can be also used to override the value passed through the
2150  *  platform and necessary for old MAC10/100 and GMAC chips.
2151  */
2152 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2153 {
2154         return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
2155 }
2156
2157 /**
2158  * stmmac_check_ether_addr - check if the MAC addr is valid
2159  * @priv: driver private structure
2160  * Description:
2161  * it is to verify if the MAC address is valid, in case of failures it
2162  * generates a random MAC address
2163  */
2164 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2165 {
2166         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2167                 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0);
2168                 if (!is_valid_ether_addr(priv->dev->dev_addr))
2169                         eth_hw_addr_random(priv->dev);
2170                 dev_info(priv->device, "device MAC address %pM\n",
2171                          priv->dev->dev_addr);
2172         }
2173 }
2174
2175 /**
2176  * stmmac_init_dma_engine - DMA init.
2177  * @priv: driver private structure
2178  * Description:
2179  * It inits the DMA invoking the specific MAC/GMAC callback.
2180  * Some DMA parameters can be passed from the platform;
2181  * in case of these are not passed a default is kept for the MAC or GMAC.
2182  */
2183 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2184 {
2185         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2186         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2187         u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2188         struct stmmac_rx_queue *rx_q;
2189         struct stmmac_tx_queue *tx_q;
2190         u32 chan = 0;
2191         int atds = 0;
2192         int ret = 0;
2193
2194         if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2195                 dev_err(priv->device, "Invalid DMA configuration\n");
2196                 return -EINVAL;
2197         }
2198
2199         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2200                 atds = 1;
2201
2202         ret = stmmac_reset(priv, priv->ioaddr);
2203         if (ret) {
2204                 dev_err(priv->device, "Failed to reset the dma\n");
2205                 return ret;
2206         }
2207
2208         /* DMA Configuration */
2209         stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);
2210
2211         if (priv->plat->axi)
2212                 stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
2213
2214         /* DMA CSR Channel configuration */
2215         for (chan = 0; chan < dma_csr_ch; chan++)
2216                 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
2217
2218         /* DMA RX Channel Configuration */
2219         for (chan = 0; chan < rx_channels_count; chan++) {
2220                 rx_q = &priv->rx_queue[chan];
2221
2222                 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2223                                     rx_q->dma_rx_phy, chan);
2224
2225                 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2226                             (DMA_RX_SIZE * sizeof(struct dma_desc));
2227                 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
2228                                        rx_q->rx_tail_addr, chan);
2229         }
2230
2231         /* DMA TX Channel Configuration */
2232         for (chan = 0; chan < tx_channels_count; chan++) {
2233                 tx_q = &priv->tx_queue[chan];
2234
2235                 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2236                                     tx_q->dma_tx_phy, chan);
2237
2238                 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
2239                 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
2240                                        tx_q->tx_tail_addr, chan);
2241         }
2242
2243         return ret;
2244 }
2245
2246 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
2247 {
2248         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2249
2250         mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer));
2251 }
2252
2253 /**
2254  * stmmac_tx_timer - mitigation sw timer for tx.
2255  * @data: data pointer
2256  * Description:
2257  * This is the timer handler to directly invoke the stmmac_tx_clean.
2258  */
2259 static void stmmac_tx_timer(struct timer_list *t)
2260 {
2261         struct stmmac_tx_queue *tx_q = from_timer(tx_q, t, txtimer);
2262         struct stmmac_priv *priv = tx_q->priv_data;
2263         struct stmmac_channel *ch;
2264
2265         ch = &priv->channel[tx_q->queue_index];
2266
2267         /*
2268          * If NAPI is already running we can miss some events. Let's rearm
2269          * the timer and try again.
2270          */
2271         if (likely(napi_schedule_prep(&ch->tx_napi)))
2272                 __napi_schedule(&ch->tx_napi);
2273         else
2274                 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
2275 }
2276
2277 /**
2278  * stmmac_init_coalesce - init mitigation options.
2279  * @priv: driver private structure
2280  * Description:
2281  * This inits the coalesce parameters: i.e. timer rate,
2282  * timer handler and default threshold used for enabling the
2283  * interrupt on completion bit.
2284  */
2285 static void stmmac_init_coalesce(struct stmmac_priv *priv)
2286 {
2287         u32 tx_channel_count = priv->plat->tx_queues_to_use;
2288         u32 chan;
2289
2290         priv->tx_coal_frames = STMMAC_TX_FRAMES;
2291         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
2292         priv->rx_coal_frames = STMMAC_RX_FRAMES;
2293
2294         for (chan = 0; chan < tx_channel_count; chan++) {
2295                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2296
2297                 timer_setup(&tx_q->txtimer, stmmac_tx_timer, 0);
2298         }
2299 }
2300
2301 static void stmmac_set_rings_length(struct stmmac_priv *priv)
2302 {
2303         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2304         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2305         u32 chan;
2306
2307         /* set TX ring length */
2308         for (chan = 0; chan < tx_channels_count; chan++)
2309                 stmmac_set_tx_ring_len(priv, priv->ioaddr,
2310                                 (DMA_TX_SIZE - 1), chan);
2311
2312         /* set RX ring length */
2313         for (chan = 0; chan < rx_channels_count; chan++)
2314                 stmmac_set_rx_ring_len(priv, priv->ioaddr,
2315                                 (DMA_RX_SIZE - 1), chan);
2316 }
2317
2318 /**
2319  *  stmmac_set_tx_queue_weight - Set TX queue weight
2320  *  @priv: driver private structure
2321  *  Description: It is used for setting TX queues weight
2322  */
2323 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
2324 {
2325         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2326         u32 weight;
2327         u32 queue;
2328
2329         for (queue = 0; queue < tx_queues_count; queue++) {
2330                 weight = priv->plat->tx_queues_cfg[queue].weight;
2331                 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue);
2332         }
2333 }
2334
2335 /**
2336  *  stmmac_configure_cbs - Configure CBS in TX queue
2337  *  @priv: driver private structure
2338  *  Description: It is used for configuring CBS in AVB TX queues
2339  */
2340 static void stmmac_configure_cbs(struct stmmac_priv *priv)
2341 {
2342         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2343         u32 mode_to_use;
2344         u32 queue;
2345
2346         /* queue 0 is reserved for legacy traffic */
2347         for (queue = 1; queue < tx_queues_count; queue++) {
2348                 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
2349                 if (mode_to_use == MTL_QUEUE_DCB)
2350                         continue;
2351
2352                 stmmac_config_cbs(priv, priv->hw,
2353                                 priv->plat->tx_queues_cfg[queue].send_slope,
2354                                 priv->plat->tx_queues_cfg[queue].idle_slope,
2355                                 priv->plat->tx_queues_cfg[queue].high_credit,
2356                                 priv->plat->tx_queues_cfg[queue].low_credit,
2357                                 queue);
2358         }
2359 }
2360
2361 /**
2362  *  stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
2363  *  @priv: driver private structure
2364  *  Description: It is used for mapping RX queues to RX dma channels
2365  */
2366 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
2367 {
2368         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2369         u32 queue;
2370         u32 chan;
2371
2372         for (queue = 0; queue < rx_queues_count; queue++) {
2373                 chan = priv->plat->rx_queues_cfg[queue].chan;
2374                 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
2375         }
2376 }
2377
2378 /**
2379  *  stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
2380  *  @priv: driver private structure
2381  *  Description: It is used for configuring the RX Queue Priority
2382  */
2383 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
2384 {
2385         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2386         u32 queue;
2387         u32 prio;
2388
2389         for (queue = 0; queue < rx_queues_count; queue++) {
2390                 if (!priv->plat->rx_queues_cfg[queue].use_prio)
2391                         continue;
2392
2393                 prio = priv->plat->rx_queues_cfg[queue].prio;
2394                 stmmac_rx_queue_prio(priv, priv->hw, prio, queue);
2395         }
2396 }
2397
2398 /**
2399  *  stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
2400  *  @priv: driver private structure
2401  *  Description: It is used for configuring the TX Queue Priority
2402  */
2403 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
2404 {
2405         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2406         u32 queue;
2407         u32 prio;
2408
2409         for (queue = 0; queue < tx_queues_count; queue++) {
2410                 if (!priv->plat->tx_queues_cfg[queue].use_prio)
2411                         continue;
2412
2413                 prio = priv->plat->tx_queues_cfg[queue].prio;
2414                 stmmac_tx_queue_prio(priv, priv->hw, prio, queue);
2415         }
2416 }
2417
2418 /**
2419  *  stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
2420  *  @priv: driver private structure
2421  *  Description: It is used for configuring the RX queue routing
2422  */
2423 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
2424 {
2425         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2426         u32 queue;
2427         u8 packet;
2428
2429         for (queue = 0; queue < rx_queues_count; queue++) {
2430                 /* no specific packet type routing specified for the queue */
2431                 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
2432                         continue;
2433
2434                 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
2435                 stmmac_rx_queue_routing(priv, priv->hw, packet, queue);
2436         }
2437 }
2438
2439 static void stmmac_mac_config_rss(struct stmmac_priv *priv)
2440 {
2441         if (!priv->dma_cap.rssen || !priv->plat->rss_en) {
2442                 priv->rss.enable = false;
2443                 return;
2444         }
2445
2446         if (priv->dev->features & NETIF_F_RXHASH)
2447                 priv->rss.enable = true;
2448         else
2449                 priv->rss.enable = false;
2450
2451         stmmac_rss_configure(priv, priv->hw, &priv->rss,
2452                              priv->plat->rx_queues_to_use);
2453 }
2454
2455 /**
2456  *  stmmac_mtl_configuration - Configure MTL
2457  *  @priv: driver private structure
2458  *  Description: It is used for configurring MTL
2459  */
2460 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
2461 {
2462         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2463         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2464
2465         if (tx_queues_count > 1)
2466                 stmmac_set_tx_queue_weight(priv);
2467
2468         /* Configure MTL RX algorithms */
2469         if (rx_queues_count > 1)
2470                 stmmac_prog_mtl_rx_algorithms(priv, priv->hw,
2471                                 priv->plat->rx_sched_algorithm);
2472
2473         /* Configure MTL TX algorithms */
2474         if (tx_queues_count > 1)
2475                 stmmac_prog_mtl_tx_algorithms(priv, priv->hw,
2476                                 priv->plat->tx_sched_algorithm);
2477
2478         /* Configure CBS in AVB TX queues */
2479         if (tx_queues_count > 1)
2480                 stmmac_configure_cbs(priv);
2481
2482         /* Map RX MTL to DMA channels */
2483         stmmac_rx_queue_dma_chan_map(priv);
2484
2485         /* Enable MAC RX Queues */
2486         stmmac_mac_enable_rx_queues(priv);
2487
2488         /* Set RX priorities */
2489         if (rx_queues_count > 1)
2490                 stmmac_mac_config_rx_queues_prio(priv);
2491
2492         /* Set TX priorities */
2493         if (tx_queues_count > 1)
2494                 stmmac_mac_config_tx_queues_prio(priv);
2495
2496         /* Set RX routing */
2497         if (rx_queues_count > 1)
2498                 stmmac_mac_config_rx_queues_routing(priv);
2499
2500         /* Receive Side Scaling */
2501         if (rx_queues_count > 1)
2502                 stmmac_mac_config_rss(priv);
2503 }
2504
2505 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
2506 {
2507         if (priv->dma_cap.asp) {
2508                 netdev_info(priv->dev, "Enabling Safety Features\n");
2509                 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp);
2510         } else {
2511                 netdev_info(priv->dev, "No Safety Features support found\n");
2512         }
2513 }
2514
2515 /**
2516  * stmmac_hw_setup - setup mac in a usable state.
2517  *  @dev : pointer to the device structure.
2518  *  Description:
2519  *  this is the main function to setup the HW in a usable state because the
2520  *  dma engine is reset, the core registers are configured (e.g. AXI,
2521  *  Checksum features, timers). The DMA is ready to start receiving and
2522  *  transmitting.
2523  *  Return value:
2524  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2525  *  file on failure.
2526  */
2527 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
2528 {
2529         struct stmmac_priv *priv = netdev_priv(dev);
2530         u32 rx_cnt = priv->plat->rx_queues_to_use;
2531         u32 tx_cnt = priv->plat->tx_queues_to_use;
2532         u32 chan;
2533         int ret;
2534
2535         /* DMA initialization and SW reset */
2536         ret = stmmac_init_dma_engine(priv);
2537         if (ret < 0) {
2538                 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
2539                            __func__);
2540                 return ret;
2541         }
2542
2543         /* Copy the MAC addr into the HW  */
2544         stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
2545
2546         /* PS and related bits will be programmed according to the speed */
2547         if (priv->hw->pcs) {
2548                 int speed = priv->plat->mac_port_sel_speed;
2549
2550                 if ((speed == SPEED_10) || (speed == SPEED_100) ||
2551                     (speed == SPEED_1000)) {
2552                         priv->hw->ps = speed;
2553                 } else {
2554                         dev_warn(priv->device, "invalid port speed\n");
2555                         priv->hw->ps = 0;
2556                 }
2557         }
2558
2559         /* Initialize the MAC Core */
2560         stmmac_core_init(priv, priv->hw, dev);
2561
2562         /* Initialize MTL*/
2563         stmmac_mtl_configuration(priv);
2564
2565         /* Initialize Safety Features */
2566         stmmac_safety_feat_configuration(priv);
2567
2568         ret = stmmac_rx_ipc(priv, priv->hw);
2569         if (!ret) {
2570                 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
2571                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2572                 priv->hw->rx_csum = 0;
2573         }
2574
2575         /* Enable the MAC Rx/Tx */
2576         stmmac_mac_set(priv, priv->ioaddr, true);
2577
2578         /* Set the HW DMA mode and the COE */
2579         stmmac_dma_operation_mode(priv);
2580
2581         stmmac_mmc_setup(priv);
2582
2583         if (init_ptp) {
2584                 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
2585                 if (ret < 0)
2586                         netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret);
2587
2588                 ret = stmmac_init_ptp(priv);
2589                 if (ret == -EOPNOTSUPP)
2590                         netdev_warn(priv->dev, "PTP not supported by HW\n");
2591                 else if (ret)
2592                         netdev_warn(priv->dev, "PTP init failed\n");
2593         }
2594
2595         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
2596
2597         if (priv->use_riwt) {
2598                 if (!priv->rx_riwt)
2599                         priv->rx_riwt = DEF_DMA_RIWT;
2600
2601                 ret = stmmac_rx_watchdog(priv, priv->ioaddr, priv->rx_riwt, rx_cnt);
2602         }
2603
2604         if (priv->hw->pcs)
2605                 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0);
2606
2607         /* set TX and RX rings length */
2608         stmmac_set_rings_length(priv);
2609
2610         /* Enable TSO */
2611         if (priv->tso) {
2612                 for (chan = 0; chan < tx_cnt; chan++)
2613                         stmmac_enable_tso(priv, priv->ioaddr, 1, chan);
2614         }
2615
2616         /* Enable Split Header */
2617         if (priv->sph && priv->hw->rx_csum) {
2618                 for (chan = 0; chan < rx_cnt; chan++)
2619                         stmmac_enable_sph(priv, priv->ioaddr, 1, chan);
2620         }
2621
2622         /* VLAN Tag Insertion */
2623         if (priv->dma_cap.vlins)
2624                 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT);
2625
2626         /* Start the ball rolling... */
2627         stmmac_start_all_dma(priv);
2628
2629         return 0;
2630 }
2631
2632 static void stmmac_hw_teardown(struct net_device *dev)
2633 {
2634         struct stmmac_priv *priv = netdev_priv(dev);
2635
2636         clk_disable_unprepare(priv->plat->clk_ptp_ref);
2637 }
2638
2639 /**
2640  *  stmmac_open - open entry point of the driver
2641  *  @dev : pointer to the device structure.
2642  *  Description:
2643  *  This function is the open entry point of the driver.
2644  *  Return value:
2645  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2646  *  file on failure.
2647  */
2648 static int stmmac_open(struct net_device *dev)
2649 {
2650         struct stmmac_priv *priv = netdev_priv(dev);
2651         int bfsize = 0;
2652         u32 chan;
2653         int ret;
2654
2655         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
2656             priv->hw->pcs != STMMAC_PCS_TBI &&
2657             priv->hw->pcs != STMMAC_PCS_RTBI) {
2658                 ret = stmmac_init_phy(dev);
2659                 if (ret) {
2660                         netdev_err(priv->dev,
2661                                    "%s: Cannot attach to PHY (error: %d)\n",
2662                                    __func__, ret);
2663                         return ret;
2664                 }
2665         }
2666
2667         /* Extra statistics */
2668         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
2669         priv->xstats.threshold = tc;
2670
2671         bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu);
2672         if (bfsize < 0)
2673                 bfsize = 0;
2674
2675         if (bfsize < BUF_SIZE_16KiB)
2676                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
2677
2678         priv->dma_buf_sz = bfsize;
2679         buf_sz = bfsize;
2680
2681         priv->rx_copybreak = STMMAC_RX_COPYBREAK;
2682
2683         ret = alloc_dma_desc_resources(priv);
2684         if (ret < 0) {
2685                 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
2686                            __func__);
2687                 goto dma_desc_error;
2688         }
2689
2690         ret = init_dma_desc_rings(dev, GFP_KERNEL);
2691         if (ret < 0) {
2692                 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
2693                            __func__);
2694                 goto init_error;
2695         }
2696
2697         ret = stmmac_hw_setup(dev, true);
2698         if (ret < 0) {
2699                 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
2700                 goto init_error;
2701         }
2702
2703         stmmac_init_coalesce(priv);
2704
2705         phylink_start(priv->phylink);
2706
2707         /* Request the IRQ lines */
2708         ret = request_irq(dev->irq, stmmac_interrupt,
2709                           IRQF_SHARED, dev->name, dev);
2710         if (unlikely(ret < 0)) {
2711                 netdev_err(priv->dev,
2712                            "%s: ERROR: allocating the IRQ %d (error: %d)\n",
2713                            __func__, dev->irq, ret);
2714                 goto irq_error;
2715         }
2716
2717         /* Request the Wake IRQ in case of another line is used for WoL */
2718         if (priv->wol_irq != dev->irq) {
2719                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
2720                                   IRQF_SHARED, dev->name, dev);
2721                 if (unlikely(ret < 0)) {
2722                         netdev_err(priv->dev,
2723                                    "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
2724                                    __func__, priv->wol_irq, ret);
2725                         goto wolirq_error;
2726                 }
2727         }
2728
2729         /* Request the IRQ lines */
2730         if (priv->lpi_irq > 0) {
2731                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
2732                                   dev->name, dev);
2733                 if (unlikely(ret < 0)) {
2734                         netdev_err(priv->dev,
2735                                    "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
2736                                    __func__, priv->lpi_irq, ret);
2737                         goto lpiirq_error;
2738                 }
2739         }
2740
2741         stmmac_enable_all_queues(priv);
2742         stmmac_start_all_queues(priv);
2743
2744         return 0;
2745
2746 lpiirq_error:
2747         if (priv->wol_irq != dev->irq)
2748                 free_irq(priv->wol_irq, dev);
2749 wolirq_error:
2750         free_irq(dev->irq, dev);
2751 irq_error:
2752         phylink_stop(priv->phylink);
2753
2754         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2755                 del_timer_sync(&priv->tx_queue[chan].txtimer);
2756
2757         stmmac_hw_teardown(dev);
2758 init_error:
2759         free_dma_desc_resources(priv);
2760 dma_desc_error:
2761         phylink_disconnect_phy(priv->phylink);
2762         return ret;
2763 }
2764
2765 /**
2766  *  stmmac_release - close entry point of the driver
2767  *  @dev : device pointer.
2768  *  Description:
2769  *  This is the stop entry point of the driver.
2770  */
2771 static int stmmac_release(struct net_device *dev)
2772 {
2773         struct stmmac_priv *priv = netdev_priv(dev);
2774         u32 chan;
2775
2776         if (priv->eee_enabled)
2777                 del_timer_sync(&priv->eee_ctrl_timer);
2778
2779         /* Stop and disconnect the PHY */
2780         phylink_stop(priv->phylink);
2781         phylink_disconnect_phy(priv->phylink);
2782
2783         stmmac_stop_all_queues(priv);
2784
2785         stmmac_disable_all_queues(priv);
2786
2787         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2788                 del_timer_sync(&priv->tx_queue[chan].txtimer);
2789
2790         /* Free the IRQ lines */
2791         free_irq(dev->irq, dev);
2792         if (priv->wol_irq != dev->irq)
2793                 free_irq(priv->wol_irq, dev);
2794         if (priv->lpi_irq > 0)
2795                 free_irq(priv->lpi_irq, dev);
2796
2797         /* Stop TX/RX DMA and clear the descriptors */
2798         stmmac_stop_all_dma(priv);
2799
2800         /* Release and free the Rx/Tx resources */
2801         free_dma_desc_resources(priv);
2802
2803         /* Disable the MAC Rx/Tx */
2804         stmmac_mac_set(priv, priv->ioaddr, false);
2805
2806         netif_carrier_off(dev);
2807
2808         stmmac_release_ptp(priv);
2809
2810         return 0;
2811 }
2812
2813 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb,
2814                                struct stmmac_tx_queue *tx_q)
2815 {
2816         u16 tag = 0x0, inner_tag = 0x0;
2817         u32 inner_type = 0x0;
2818         struct dma_desc *p;
2819
2820         if (!priv->dma_cap.vlins)
2821                 return false;
2822         if (!skb_vlan_tag_present(skb))
2823                 return false;
2824         if (skb->vlan_proto == htons(ETH_P_8021AD)) {
2825                 inner_tag = skb_vlan_tag_get(skb);
2826                 inner_type = STMMAC_VLAN_INSERT;
2827         }
2828
2829         tag = skb_vlan_tag_get(skb);
2830
2831         p = tx_q->dma_tx + tx_q->cur_tx;
2832         if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type))
2833                 return false;
2834
2835         stmmac_set_tx_owner(priv, p);
2836         tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2837         return true;
2838 }
2839
2840 /**
2841  *  stmmac_tso_allocator - close entry point of the driver
2842  *  @priv: driver private structure
2843  *  @des: buffer start address
2844  *  @total_len: total length to fill in descriptors
2845  *  @last_segmant: condition for the last descriptor
2846  *  @queue: TX queue index
2847  *  Description:
2848  *  This function fills descriptor and request new descriptors according to
2849  *  buffer length to fill
2850  */
2851 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des,
2852                                  int total_len, bool last_segment, u32 queue)
2853 {
2854         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2855         struct dma_desc *desc;
2856         u32 buff_size;
2857         int tmp_len;
2858
2859         tmp_len = total_len;
2860
2861         while (tmp_len > 0) {
2862                 dma_addr_t curr_addr;
2863
2864                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2865                 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2866                 desc = tx_q->dma_tx + tx_q->cur_tx;
2867
2868                 curr_addr = des + (total_len - tmp_len);
2869                 if (priv->dma_cap.addr64 <= 32)
2870                         desc->des0 = cpu_to_le32(curr_addr);
2871                 else
2872                         stmmac_set_desc_addr(priv, desc, curr_addr);
2873
2874                 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
2875                             TSO_MAX_BUFF_SIZE : tmp_len;
2876
2877                 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size,
2878                                 0, 1,
2879                                 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
2880                                 0, 0);
2881
2882                 tmp_len -= TSO_MAX_BUFF_SIZE;
2883         }
2884 }
2885
2886 /**
2887  *  stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
2888  *  @skb : the socket buffer
2889  *  @dev : device pointer
2890  *  Description: this is the transmit function that is called on TSO frames
2891  *  (support available on GMAC4 and newer chips).
2892  *  Diagram below show the ring programming in case of TSO frames:
2893  *
2894  *  First Descriptor
2895  *   --------
2896  *   | DES0 |---> buffer1 = L2/L3/L4 header
2897  *   | DES1 |---> TCP Payload (can continue on next descr...)
2898  *   | DES2 |---> buffer 1 and 2 len
2899  *   | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
2900  *   --------
2901  *      |
2902  *     ...
2903  *      |
2904  *   --------
2905  *   | DES0 | --| Split TCP Payload on Buffers 1 and 2
2906  *   | DES1 | --|
2907  *   | DES2 | --> buffer 1 and 2 len
2908  *   | DES3 |
2909  *   --------
2910  *
2911  * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
2912  */
2913 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
2914 {
2915         struct dma_desc *desc, *first, *mss_desc = NULL;
2916         struct stmmac_priv *priv = netdev_priv(dev);
2917         int nfrags = skb_shinfo(skb)->nr_frags;
2918         u32 queue = skb_get_queue_mapping(skb);
2919         unsigned int first_entry, tx_packets;
2920         int tmp_pay_len = 0, first_tx;
2921         struct stmmac_tx_queue *tx_q;
2922         u8 proto_hdr_len, hdr;
2923         bool has_vlan, set_ic;
2924         u32 pay_len, mss;
2925         dma_addr_t des;
2926         int i;
2927
2928         tx_q = &priv->tx_queue[queue];
2929         first_tx = tx_q->cur_tx;
2930
2931         /* Compute header lengths */
2932         if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
2933                 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr);
2934                 hdr = sizeof(struct udphdr);
2935         } else {
2936                 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2937                 hdr = tcp_hdrlen(skb);
2938         }
2939
2940         /* Desc availability based on threshold should be enough safe */
2941         if (unlikely(stmmac_tx_avail(priv, queue) <
2942                 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
2943                 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
2944                         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
2945                                                                 queue));
2946                         /* This is a hard error, log it. */
2947                         netdev_err(priv->dev,
2948                                    "%s: Tx Ring full when queue awake\n",
2949                                    __func__);
2950                 }
2951                 return NETDEV_TX_BUSY;
2952         }
2953
2954         pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
2955
2956         mss = skb_shinfo(skb)->gso_size;
2957
2958         /* set new MSS value if needed */
2959         if (mss != tx_q->mss) {
2960                 mss_desc = tx_q->dma_tx + tx_q->cur_tx;
2961                 stmmac_set_mss(priv, mss_desc, mss);
2962                 tx_q->mss = mss;
2963                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2964                 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2965         }
2966
2967         if (netif_msg_tx_queued(priv)) {
2968                 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2969                         __func__, hdr, proto_hdr_len, pay_len, mss);
2970                 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
2971                         skb->data_len);
2972         }
2973
2974         /* Check if VLAN can be inserted by HW */
2975         has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
2976
2977         first_entry = tx_q->cur_tx;
2978         WARN_ON(tx_q->tx_skbuff[first_entry]);
2979
2980         desc = tx_q->dma_tx + first_entry;
2981         first = desc;
2982
2983         if (has_vlan)
2984                 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
2985
2986         /* first descriptor: fill Headers on Buf1 */
2987         des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
2988                              DMA_TO_DEVICE);
2989         if (dma_mapping_error(priv->device, des))
2990                 goto dma_map_err;
2991
2992         tx_q->tx_skbuff_dma[first_entry].buf = des;
2993         tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
2994
2995         if (priv->dma_cap.addr64 <= 32) {
2996                 first->des0 = cpu_to_le32(des);
2997
2998                 /* Fill start of payload in buff2 of first descriptor */
2999                 if (pay_len)
3000                         first->des1 = cpu_to_le32(des + proto_hdr_len);
3001
3002                 /* If needed take extra descriptors to fill the remaining payload */
3003                 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
3004         } else {
3005                 stmmac_set_desc_addr(priv, first, des);
3006                 tmp_pay_len = pay_len;
3007                 des += proto_hdr_len;
3008                 pay_len = 0;
3009         }
3010
3011         stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
3012
3013         /* Prepare fragments */
3014         for (i = 0; i < nfrags; i++) {
3015                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3016
3017                 des = skb_frag_dma_map(priv->device, frag, 0,
3018                                        skb_frag_size(frag),
3019                                        DMA_TO_DEVICE);
3020                 if (dma_mapping_error(priv->device, des))
3021                         goto dma_map_err;
3022
3023                 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
3024                                      (i == nfrags - 1), queue);
3025
3026                 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
3027                 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
3028                 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
3029         }
3030
3031         tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
3032
3033         /* Only the last descriptor gets to point to the skb. */
3034         tx_q->tx_skbuff[tx_q->cur_tx] = skb;
3035
3036         /* Manage tx mitigation */
3037         tx_packets = (tx_q->cur_tx + 1) - first_tx;
3038         tx_q->tx_count_frames += tx_packets;
3039
3040         if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en)
3041                 set_ic = true;
3042         else if (!priv->tx_coal_frames)
3043                 set_ic = false;
3044         else if (tx_packets > priv->tx_coal_frames)
3045                 set_ic = true;
3046         else if ((tx_q->tx_count_frames % priv->tx_coal_frames) < tx_packets)
3047                 set_ic = true;
3048         else
3049                 set_ic = false;
3050
3051         if (set_ic) {
3052                 desc = &tx_q->dma_tx[tx_q->cur_tx];
3053                 tx_q->tx_count_frames = 0;
3054                 stmmac_set_tx_ic(priv, desc);
3055                 priv->xstats.tx_set_ic_bit++;
3056         }
3057
3058         /* We've used all descriptors we need for this skb, however,
3059          * advance cur_tx so that it references a fresh descriptor.
3060          * ndo_start_xmit will fill this descriptor the next time it's
3061          * called and stmmac_tx_clean may clean up to this descriptor.
3062          */
3063         tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
3064
3065         if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
3066                 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
3067                           __func__);
3068                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
3069         }
3070
3071         dev->stats.tx_bytes += skb->len;
3072         priv->xstats.tx_tso_frames++;
3073         priv->xstats.tx_tso_nfrags += nfrags;
3074
3075         if (priv->sarc_type)
3076                 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
3077
3078         skb_tx_timestamp(skb);
3079
3080         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3081                      priv->hwts_tx_en)) {
3082                 /* declare that device is doing timestamping */
3083                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3084                 stmmac_enable_tx_timestamp(priv, first);
3085         }
3086
3087         /* Complete the first descriptor before granting the DMA */
3088         stmmac_prepare_tso_tx_desc(priv, first, 1,
3089                         proto_hdr_len,
3090                         pay_len,
3091                         1, tx_q->tx_skbuff_dma[first_entry].last_segment,
3092                         hdr / 4, (skb->len - proto_hdr_len));
3093
3094         /* If context desc is used to change MSS */
3095         if (mss_desc) {
3096                 /* Make sure that first descriptor has been completely
3097                  * written, including its own bit. This is because MSS is
3098                  * actually before first descriptor, so we need to make
3099                  * sure that MSS's own bit is the last thing written.
3100                  */
3101                 dma_wmb();
3102                 stmmac_set_tx_owner(priv, mss_desc);
3103         }
3104
3105         /* The own bit must be the latest setting done when prepare the
3106          * descriptor and then barrier is needed to make sure that
3107          * all is coherent before granting the DMA engine.
3108          */
3109         wmb();
3110
3111         if (netif_msg_pktdata(priv)) {
3112                 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
3113                         __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3114                         tx_q->cur_tx, first, nfrags);
3115
3116                 stmmac_display_ring(priv, (void *)tx_q->dma_tx, DMA_TX_SIZE, 0);
3117
3118                 pr_info(">>> frame to be transmitted: ");
3119                 print_pkt(skb->data, skb_headlen(skb));
3120         }
3121
3122         netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3123
3124         tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
3125         stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3126         stmmac_tx_timer_arm(priv, queue);
3127
3128         return NETDEV_TX_OK;
3129
3130 dma_map_err:
3131         dev_err(priv->device, "Tx dma map failed\n");
3132         dev_kfree_skb(skb);
3133         priv->dev->stats.tx_dropped++;
3134         return NETDEV_TX_OK;
3135 }
3136
3137 /**
3138  *  stmmac_xmit - Tx entry point of the driver
3139  *  @skb : the socket buffer
3140  *  @dev : device pointer
3141  *  Description : this is the tx entry point of the driver.
3142  *  It programs the chain or the ring and supports oversized frames
3143  *  and SG feature.
3144  */
3145 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
3146 {
3147         unsigned int first_entry, tx_packets, enh_desc;
3148         struct stmmac_priv *priv = netdev_priv(dev);
3149         unsigned int nopaged_len = skb_headlen(skb);
3150         int i, csum_insertion = 0, is_jumbo = 0;
3151         u32 queue = skb_get_queue_mapping(skb);
3152         int nfrags = skb_shinfo(skb)->nr_frags;
3153         int gso = skb_shinfo(skb)->gso_type;
3154         struct dma_desc *desc, *first;
3155         struct stmmac_tx_queue *tx_q;
3156         bool has_vlan, set_ic;
3157         int entry, first_tx;
3158         dma_addr_t des;
3159
3160         tx_q = &priv->tx_queue[queue];
3161         first_tx = tx_q->cur_tx;
3162
3163         if (priv->tx_path_in_lpi_mode)
3164                 stmmac_disable_eee_mode(priv);
3165
3166         /* Manage oversized TCP frames for GMAC4 device */
3167         if (skb_is_gso(skb) && priv->tso) {
3168                 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6))
3169                         return stmmac_tso_xmit(skb, dev);
3170                 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4))
3171                         return stmmac_tso_xmit(skb, dev);
3172         }
3173
3174         if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
3175                 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
3176                         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
3177                                                                 queue));
3178                         /* This is a hard error, log it. */
3179                         netdev_err(priv->dev,
3180                                    "%s: Tx Ring full when queue awake\n",
3181                                    __func__);
3182                 }
3183                 return NETDEV_TX_BUSY;
3184         }
3185
3186         /* Check if VLAN can be inserted by HW */
3187         has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
3188
3189         entry = tx_q->cur_tx;
3190         first_entry = entry;
3191         WARN_ON(tx_q->tx_skbuff[first_entry]);
3192
3193         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
3194
3195         if (likely(priv->extend_desc))
3196                 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3197         else
3198                 desc = tx_q->dma_tx + entry;
3199
3200         first = desc;
3201
3202         if (has_vlan)
3203                 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
3204
3205         enh_desc = priv->plat->enh_desc;
3206         /* To program the descriptors according to the size of the frame */
3207         if (enh_desc)
3208                 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc);
3209
3210         if (unlikely(is_jumbo)) {
3211                 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion);
3212                 if (unlikely(entry < 0) && (entry != -EINVAL))
3213                         goto dma_map_err;
3214         }
3215
3216         for (i = 0; i < nfrags; i++) {
3217                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3218                 int len = skb_frag_size(frag);
3219                 bool last_segment = (i == (nfrags - 1));
3220
3221                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3222                 WARN_ON(tx_q->tx_skbuff[entry]);
3223
3224                 if (likely(priv->extend_desc))
3225                         desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3226                 else
3227                         desc = tx_q->dma_tx + entry;
3228
3229                 des = skb_frag_dma_map(priv->device, frag, 0, len,
3230                                        DMA_TO_DEVICE);
3231                 if (dma_mapping_error(priv->device, des))
3232                         goto dma_map_err; /* should reuse desc w/o issues */
3233
3234                 tx_q->tx_skbuff_dma[entry].buf = des;
3235
3236                 stmmac_set_desc_addr(priv, desc, des);
3237
3238                 tx_q->tx_skbuff_dma[entry].map_as_page = true;
3239                 tx_q->tx_skbuff_dma[entry].len = len;
3240                 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
3241
3242                 /* Prepare the descriptor and set the own bit too */
3243                 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion,
3244                                 priv->mode, 1, last_segment, skb->len);
3245         }
3246
3247         /* Only the last descriptor gets to point to the skb. */
3248         tx_q->tx_skbuff[entry] = skb;
3249
3250         /* According to the coalesce parameter the IC bit for the latest
3251          * segment is reset and the timer re-started to clean the tx status.
3252          * This approach takes care about the fragments: desc is the first
3253          * element in case of no SG.
3254          */
3255         tx_packets = (entry + 1) - first_tx;
3256         tx_q->tx_count_frames += tx_packets;
3257
3258         if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en)
3259                 set_ic = true;
3260         else if (!priv->tx_coal_frames)
3261                 set_ic = false;
3262         else if (tx_packets > priv->tx_coal_frames)
3263                 set_ic = true;
3264         else if ((tx_q->tx_count_frames % priv->tx_coal_frames) < tx_packets)
3265                 set_ic = true;
3266         else
3267                 set_ic = false;
3268
3269         if (set_ic) {
3270                 if (likely(priv->extend_desc))
3271                         desc = &tx_q->dma_etx[entry].basic;
3272                 else
3273                         desc = &tx_q->dma_tx[entry];
3274
3275                 tx_q->tx_count_frames = 0;
3276                 stmmac_set_tx_ic(priv, desc);
3277                 priv->xstats.tx_set_ic_bit++;
3278         }
3279
3280         /* We've used all descriptors we need for this skb, however,
3281          * advance cur_tx so that it references a fresh descriptor.
3282          * ndo_start_xmit will fill this descriptor the next time it's
3283          * called and stmmac_tx_clean may clean up to this descriptor.
3284          */
3285         entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3286         tx_q->cur_tx = entry;
3287
3288         if (netif_msg_pktdata(priv)) {
3289                 void *tx_head;
3290
3291                 netdev_dbg(priv->dev,
3292                            "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
3293                            __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3294                            entry, first, nfrags);
3295
3296                 if (priv->extend_desc)
3297                         tx_head = (void *)tx_q->dma_etx;
3298                 else
3299                         tx_head = (void *)tx_q->dma_tx;
3300
3301                 stmmac_display_ring(priv, tx_head, DMA_TX_SIZE, false);
3302
3303                 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
3304                 print_pkt(skb->data, skb->len);
3305         }
3306
3307         if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
3308                 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
3309                           __func__);
3310                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
3311         }
3312
3313         dev->stats.tx_bytes += skb->len;
3314
3315         if (priv->sarc_type)
3316                 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
3317
3318         skb_tx_timestamp(skb);
3319
3320         /* Ready to fill the first descriptor and set the OWN bit w/o any
3321          * problems because all the descriptors are actually ready to be
3322          * passed to the DMA engine.
3323          */
3324         if (likely(!is_jumbo)) {
3325                 bool last_segment = (nfrags == 0);
3326
3327                 des = dma_map_single(priv->device, skb->data,
3328                                      nopaged_len, DMA_TO_DEVICE);
3329                 if (dma_mapping_error(priv->device, des))
3330                         goto dma_map_err;
3331
3332                 tx_q->tx_skbuff_dma[first_entry].buf = des;
3333
3334                 stmmac_set_desc_addr(priv, first, des);
3335
3336                 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
3337                 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
3338
3339                 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3340                              priv->hwts_tx_en)) {
3341                         /* declare that device is doing timestamping */
3342                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3343                         stmmac_enable_tx_timestamp(priv, first);
3344                 }
3345
3346                 /* Prepare the first descriptor setting the OWN bit too */
3347                 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
3348                                 csum_insertion, priv->mode, 1, last_segment,
3349                                 skb->len);
3350         } else {
3351                 stmmac_set_tx_owner(priv, first);
3352         }
3353
3354         /* The own bit must be the latest setting done when prepare the
3355          * descriptor and then barrier is needed to make sure that
3356          * all is coherent before granting the DMA engine.
3357          */
3358         wmb();
3359
3360         netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3361
3362         stmmac_enable_dma_transmission(priv, priv->ioaddr);
3363
3364         tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
3365         stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3366         stmmac_tx_timer_arm(priv, queue);
3367
3368         return NETDEV_TX_OK;
3369
3370 dma_map_err:
3371         netdev_err(priv->dev, "Tx DMA map failed\n");
3372         dev_kfree_skb(skb);
3373         priv->dev->stats.tx_dropped++;
3374         return NETDEV_TX_OK;
3375 }
3376
3377 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
3378 {
3379         struct vlan_ethhdr *veth;
3380         __be16 vlan_proto;
3381         u16 vlanid;
3382
3383         veth = (struct vlan_ethhdr *)skb->data;
3384         vlan_proto = veth->h_vlan_proto;
3385
3386         if ((vlan_proto == htons(ETH_P_8021Q) &&
3387              dev->features & NETIF_F_HW_VLAN_CTAG_RX) ||
3388             (vlan_proto == htons(ETH_P_8021AD) &&
3389              dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
3390                 /* pop the vlan tag */
3391                 vlanid = ntohs(veth->h_vlan_TCI);
3392                 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2);
3393                 skb_pull(skb, VLAN_HLEN);
3394                 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid);
3395         }
3396 }
3397
3398
3399 static inline int stmmac_rx_threshold_count(struct stmmac_rx_queue *rx_q)
3400 {
3401         if (rx_q->rx_zeroc_thresh < STMMAC_RX_THRESH)
3402                 return 0;
3403
3404         return 1;
3405 }
3406
3407 /**
3408  * stmmac_rx_refill - refill used skb preallocated buffers
3409  * @priv: driver private structure
3410  * @queue: RX queue index
3411  * Description : this is to reallocate the skb for the reception process
3412  * that is based on zero-copy.
3413  */
3414 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
3415 {
3416         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3417         int len, dirty = stmmac_rx_dirty(priv, queue);
3418         unsigned int entry = rx_q->dirty_rx;
3419
3420         len = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE;
3421
3422         while (dirty-- > 0) {
3423                 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
3424                 struct dma_desc *p;
3425                 bool use_rx_wd;
3426
3427                 if (priv->extend_desc)
3428                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
3429                 else
3430                         p = rx_q->dma_rx + entry;
3431
3432                 if (!buf->page) {
3433                         buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
3434                         if (!buf->page)
3435                                 break;
3436                 }
3437
3438                 if (priv->sph && !buf->sec_page) {
3439                         buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool);
3440                         if (!buf->sec_page)
3441                                 break;
3442
3443                         buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
3444
3445                         dma_sync_single_for_device(priv->device, buf->sec_addr,
3446                                                    len, DMA_FROM_DEVICE);
3447                 }
3448
3449                 buf->addr = page_pool_get_dma_addr(buf->page);
3450
3451                 /* Sync whole allocation to device. This will invalidate old
3452                  * data.
3453                  */
3454                 dma_sync_single_for_device(priv->device, buf->addr, len,
3455                                            DMA_FROM_DEVICE);
3456
3457                 stmmac_set_desc_addr(priv, p, buf->addr);
3458                 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr);
3459                 stmmac_refill_desc3(priv, rx_q, p);
3460
3461                 rx_q->rx_count_frames++;
3462                 rx_q->rx_count_frames += priv->rx_coal_frames;
3463                 if (rx_q->rx_count_frames > priv->rx_coal_frames)
3464                         rx_q->rx_count_frames = 0;
3465
3466                 use_rx_wd = !priv->rx_coal_frames;
3467                 use_rx_wd |= rx_q->rx_count_frames > 0;
3468                 if (!priv->use_riwt)
3469                         use_rx_wd = false;
3470
3471                 dma_wmb();
3472                 stmmac_set_rx_owner(priv, p, use_rx_wd);
3473
3474                 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
3475         }
3476         rx_q->dirty_rx = entry;
3477         rx_q->rx_tail_addr = rx_q->dma_rx_phy +
3478                             (rx_q->dirty_rx * sizeof(struct dma_desc));
3479         stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
3480 }
3481
3482 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv,
3483                                        struct dma_desc *p,
3484                                        int status, unsigned int len)
3485 {
3486         int ret, coe = priv->hw->rx_csum;
3487         unsigned int plen = 0, hlen = 0;
3488
3489         /* Not first descriptor, buffer is always zero */
3490         if (priv->sph && len)
3491                 return 0;
3492
3493         /* First descriptor, get split header length */
3494         ret = stmmac_get_rx_header_len(priv, p, &hlen);
3495         if (priv->sph && hlen) {
3496                 priv->xstats.rx_split_hdr_pkt_n++;
3497                 return hlen;
3498         }
3499
3500         /* First descriptor, not last descriptor and not split header */
3501         if (status & rx_not_ls)
3502                 return priv->dma_buf_sz;
3503
3504         plen = stmmac_get_rx_frame_len(priv, p, coe);
3505
3506         /* First descriptor and last descriptor and not split header */
3507         return min_t(unsigned int, priv->dma_buf_sz, plen);
3508 }
3509
3510 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv,
3511                                        struct dma_desc *p,
3512                                        int status, unsigned int len)
3513 {
3514         int coe = priv->hw->rx_csum;
3515         unsigned int plen = 0;
3516
3517         /* Not split header, buffer is not available */
3518         if (!priv->sph)
3519                 return 0;
3520
3521         /* Not last descriptor */
3522         if (status & rx_not_ls)
3523                 return priv->dma_buf_sz;
3524
3525         plen = stmmac_get_rx_frame_len(priv, p, coe);
3526
3527         /* Last descriptor */
3528         return plen - len;
3529 }
3530
3531 /**
3532  * stmmac_rx - manage the receive process
3533  * @priv: driver private structure
3534  * @limit: napi bugget
3535  * @queue: RX queue index.
3536  * Description :  this the function called by the napi poll method.
3537  * It gets all the frames inside the ring.
3538  */
3539 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
3540 {
3541         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3542         struct stmmac_channel *ch = &priv->channel[queue];
3543         unsigned int count = 0, error = 0, len = 0;
3544         int status = 0, coe = priv->hw->rx_csum;
3545         unsigned int next_entry = rx_q->cur_rx;
3546         struct sk_buff *skb = NULL;
3547
3548         if (netif_msg_rx_status(priv)) {
3549                 void *rx_head;
3550
3551                 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
3552                 if (priv->extend_desc)
3553                         rx_head = (void *)rx_q->dma_erx;
3554                 else
3555                         rx_head = (void *)rx_q->dma_rx;
3556
3557                 stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true);
3558         }
3559         while (count < limit) {
3560                 unsigned int buf1_len = 0, buf2_len = 0;
3561                 enum pkt_hash_types hash_type;
3562                 struct stmmac_rx_buffer *buf;
3563                 struct dma_desc *np, *p;
3564                 int entry;
3565                 u32 hash;
3566
3567                 if (!count && rx_q->state_saved) {
3568                         skb = rx_q->state.skb;
3569                         error = rx_q->state.error;
3570                         len = rx_q->state.len;
3571                 } else {
3572                         rx_q->state_saved = false;
3573                         skb = NULL;
3574                         error = 0;
3575                         len = 0;
3576                 }
3577
3578                 if (count >= limit)
3579                         break;
3580
3581 read_again:
3582                 buf1_len = 0;
3583                 buf2_len = 0;
3584                 entry = next_entry;
3585                 buf = &rx_q->buf_pool[entry];
3586
3587                 if (priv->extend_desc)
3588                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
3589                 else
3590                         p = rx_q->dma_rx + entry;
3591
3592                 /* read the status of the incoming frame */
3593                 status = stmmac_rx_status(priv, &priv->dev->stats,
3594                                 &priv->xstats, p);
3595                 /* check if managed by the DMA otherwise go ahead */
3596                 if (unlikely(status & dma_own))
3597                         break;
3598
3599                 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE);
3600                 next_entry = rx_q->cur_rx;
3601
3602                 if (priv->extend_desc)
3603                         np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
3604                 else
3605                         np = rx_q->dma_rx + next_entry;
3606
3607                 prefetch(np);
3608
3609                 if (priv->extend_desc)
3610                         stmmac_rx_extended_status(priv, &priv->dev->stats,
3611                                         &priv->xstats, rx_q->dma_erx + entry);
3612                 if (unlikely(status == discard_frame)) {
3613                         page_pool_recycle_direct(rx_q->page_pool, buf->page);
3614                         buf->page = NULL;
3615                         error = 1;
3616                         if (!priv->hwts_rx_en)
3617                                 priv->dev->stats.rx_errors++;
3618                 }
3619
3620                 if (unlikely(error && (status & rx_not_ls)))
3621                         goto read_again;
3622                 if (unlikely(error)) {
3623                         dev_kfree_skb(skb);
3624                         skb = NULL;
3625                         count++;
3626                         continue;
3627                 }
3628
3629                 /* Buffer is good. Go on. */
3630
3631                 prefetch(page_address(buf->page));
3632                 if (buf->sec_page)
3633                         prefetch(page_address(buf->sec_page));
3634
3635                 buf1_len = stmmac_rx_buf1_len(priv, p, status, len);
3636                 len += buf1_len;
3637                 buf2_len = stmmac_rx_buf2_len(priv, p, status, len);
3638                 len += buf2_len;
3639
3640                 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
3641                  * Type frames (LLC/LLC-SNAP)
3642                  *
3643                  * llc_snap is never checked in GMAC >= 4, so this ACS
3644                  * feature is always disabled and packets need to be
3645                  * stripped manually.
3646                  */
3647                 if (likely(!(status & rx_not_ls)) &&
3648                     (likely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
3649                      unlikely(status != llc_snap))) {
3650                         if (buf2_len)
3651                                 buf2_len -= ETH_FCS_LEN;
3652                         else
3653                                 buf1_len -= ETH_FCS_LEN;
3654
3655                         len -= ETH_FCS_LEN;
3656                 }
3657
3658                 if (!skb) {
3659                         skb = napi_alloc_skb(&ch->rx_napi, buf1_len);
3660                         if (!skb) {
3661                                 priv->dev->stats.rx_dropped++;
3662                                 count++;
3663                                 goto drain_data;
3664                         }
3665
3666                         dma_sync_single_for_cpu(priv->device, buf->addr,
3667                                                 buf1_len, DMA_FROM_DEVICE);
3668                         skb_copy_to_linear_data(skb, page_address(buf->page),
3669                                                 buf1_len);
3670                         skb_put(skb, buf1_len);
3671
3672                         /* Data payload copied into SKB, page ready for recycle */
3673                         page_pool_recycle_direct(rx_q->page_pool, buf->page);
3674                         buf->page = NULL;
3675                 } else if (buf1_len) {
3676                         dma_sync_single_for_cpu(priv->device, buf->addr,
3677                                                 buf1_len, DMA_FROM_DEVICE);
3678                         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
3679                                         buf->page, 0, buf1_len,
3680                                         priv->dma_buf_sz);
3681
3682                         /* Data payload appended into SKB */
3683                         page_pool_release_page(rx_q->page_pool, buf->page);
3684                         buf->page = NULL;
3685                 }
3686
3687                 if (buf2_len) {
3688                         dma_sync_single_for_cpu(priv->device, buf->sec_addr,
3689                                                 buf2_len, DMA_FROM_DEVICE);
3690                         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
3691                                         buf->sec_page, 0, buf2_len,
3692                                         priv->dma_buf_sz);
3693
3694                         /* Data payload appended into SKB */
3695                         page_pool_release_page(rx_q->page_pool, buf->sec_page);
3696                         buf->sec_page = NULL;
3697                 }
3698
3699 drain_data:
3700                 if (likely(status & rx_not_ls))
3701                         goto read_again;
3702                 if (!skb)
3703                         continue;
3704
3705                 /* Got entire packet into SKB. Finish it. */
3706
3707                 stmmac_get_rx_hwtstamp(priv, p, np, skb);
3708                 stmmac_rx_vlan(priv->dev, skb);
3709                 skb->protocol = eth_type_trans(skb, priv->dev);
3710
3711                 if (unlikely(!coe))
3712                         skb_checksum_none_assert(skb);
3713                 else
3714                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3715
3716                 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type))
3717                         skb_set_hash(skb, hash, hash_type);
3718
3719                 skb_record_rx_queue(skb, queue);
3720                 napi_gro_receive(&ch->rx_napi, skb);
3721                 skb = NULL;
3722
3723                 priv->dev->stats.rx_packets++;
3724                 priv->dev->stats.rx_bytes += len;
3725                 count++;
3726         }
3727
3728         if (status & rx_not_ls || skb) {
3729                 rx_q->state_saved = true;
3730                 rx_q->state.skb = skb;
3731                 rx_q->state.error = error;
3732                 rx_q->state.len = len;
3733         }
3734
3735         stmmac_rx_refill(priv, queue);
3736
3737         priv->xstats.rx_pkt_n += count;
3738
3739         return count;
3740 }
3741
3742 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget)
3743 {
3744         struct stmmac_channel *ch =
3745                 container_of(napi, struct stmmac_channel, rx_napi);
3746         struct stmmac_priv *priv = ch->priv_data;
3747         u32 chan = ch->index;
3748         int work_done;
3749
3750         priv->xstats.napi_poll++;
3751
3752         work_done = stmmac_rx(priv, budget, chan);
3753         if (work_done < budget && napi_complete_done(napi, work_done))
3754                 stmmac_enable_dma_irq(priv, priv->ioaddr, chan);
3755         return work_done;
3756 }
3757
3758 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget)
3759 {
3760         struct stmmac_channel *ch =
3761                 container_of(napi, struct stmmac_channel, tx_napi);
3762         struct stmmac_priv *priv = ch->priv_data;
3763         struct stmmac_tx_queue *tx_q;
3764         u32 chan = ch->index;
3765         int work_done;
3766
3767         priv->xstats.napi_poll++;
3768
3769         work_done = stmmac_tx_clean(priv, DMA_TX_SIZE, chan);
3770         work_done = min(work_done, budget);
3771
3772         if (work_done < budget)
3773                 napi_complete_done(napi, work_done);
3774
3775         /* Force transmission restart */
3776         tx_q = &priv->tx_queue[chan];
3777         if (tx_q->cur_tx != tx_q->dirty_tx) {
3778                 stmmac_enable_dma_transmission(priv, priv->ioaddr);
3779                 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr,
3780                                        chan);
3781         }
3782
3783         return work_done;
3784 }
3785
3786 /**
3787  *  stmmac_tx_timeout
3788  *  @dev : Pointer to net device structure
3789  *  Description: this function is called when a packet transmission fails to
3790  *   complete within a reasonable time. The driver will mark the error in the
3791  *   netdev structure and arrange for the device to be reset to a sane state
3792  *   in order to transmit a new packet.
3793  */
3794 static void stmmac_tx_timeout(struct net_device *dev)
3795 {
3796         struct stmmac_priv *priv = netdev_priv(dev);
3797
3798         stmmac_global_err(priv);
3799 }
3800
3801 /**
3802  *  stmmac_set_rx_mode - entry point for multicast addressing
3803  *  @dev : pointer to the device structure
3804  *  Description:
3805  *  This function is a driver entry point which gets called by the kernel
3806  *  whenever multicast addresses must be enabled/disabled.
3807  *  Return value:
3808  *  void.
3809  */
3810 static void stmmac_set_rx_mode(struct net_device *dev)
3811 {
3812         struct stmmac_priv *priv = netdev_priv(dev);
3813
3814         stmmac_set_filter(priv, priv->hw, dev);
3815 }
3816
3817 /**
3818  *  stmmac_change_mtu - entry point to change MTU size for the device.
3819  *  @dev : device pointer.
3820  *  @new_mtu : the new MTU size for the device.
3821  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
3822  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
3823  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
3824  *  Return value:
3825  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3826  *  file on failure.
3827  */
3828 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
3829 {
3830         struct stmmac_priv *priv = netdev_priv(dev);
3831         int txfifosz = priv->plat->tx_fifo_size;
3832
3833         if (txfifosz == 0)
3834                 txfifosz = priv->dma_cap.tx_fifo_size;
3835
3836         txfifosz /= priv->plat->tx_queues_to_use;
3837
3838         if (netif_running(dev)) {
3839                 netdev_err(priv->dev, "must be stopped to change its MTU\n");
3840                 return -EBUSY;
3841         }
3842
3843         new_mtu = STMMAC_ALIGN(new_mtu);
3844
3845         /* If condition true, FIFO is too small or MTU too large */
3846         if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB))
3847                 return -EINVAL;
3848
3849         dev->mtu = new_mtu;
3850
3851         netdev_update_features(dev);
3852
3853         return 0;
3854 }
3855
3856 static netdev_features_t stmmac_fix_features(struct net_device *dev,
3857                                              netdev_features_t features)
3858 {
3859         struct stmmac_priv *priv = netdev_priv(dev);
3860
3861         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
3862                 features &= ~NETIF_F_RXCSUM;
3863
3864         if (!priv->plat->tx_coe)
3865                 features &= ~NETIF_F_CSUM_MASK;
3866
3867         /* Some GMAC devices have a bugged Jumbo frame support that
3868          * needs to have the Tx COE disabled for oversized frames
3869          * (due to limited buffer sizes). In this case we disable
3870          * the TX csum insertion in the TDES and not use SF.
3871          */
3872         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
3873                 features &= ~NETIF_F_CSUM_MASK;
3874
3875         /* Disable tso if asked by ethtool */
3876         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3877                 if (features & NETIF_F_TSO)
3878                         priv->tso = true;
3879                 else
3880                         priv->tso = false;
3881         }
3882
3883         return features;
3884 }
3885
3886 static int stmmac_set_features(struct net_device *netdev,
3887                                netdev_features_t features)
3888 {
3889         struct stmmac_priv *priv = netdev_priv(netdev);
3890         bool sph_en;
3891         u32 chan;
3892
3893         /* Keep the COE Type in case of csum is supporting */
3894         if (features & NETIF_F_RXCSUM)
3895                 priv->hw->rx_csum = priv->plat->rx_coe;
3896         else
3897                 priv->hw->rx_csum = 0;
3898         /* No check needed because rx_coe has been set before and it will be
3899          * fixed in case of issue.
3900          */
3901         stmmac_rx_ipc(priv, priv->hw);
3902
3903         sph_en = (priv->hw->rx_csum > 0) && priv->sph;
3904         for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++)
3905                 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
3906
3907         return 0;
3908 }
3909
3910 /**
3911  *  stmmac_interrupt - main ISR
3912  *  @irq: interrupt number.
3913  *  @dev_id: to pass the net device pointer.
3914  *  Description: this is the main driver interrupt service routine.
3915  *  It can call:
3916  *  o DMA service routine (to manage incoming frame reception and transmission
3917  *    status)
3918  *  o Core interrupts to manage: remote wake-up, management counter, LPI
3919  *    interrupts.
3920  */
3921 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
3922 {
3923         struct net_device *dev = (struct net_device *)dev_id;
3924         struct stmmac_priv *priv = netdev_priv(dev);
3925         u32 rx_cnt = priv->plat->rx_queues_to_use;
3926         u32 tx_cnt = priv->plat->tx_queues_to_use;
3927         u32 queues_count;
3928         u32 queue;
3929         bool xmac;
3930
3931         xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
3932         queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
3933
3934         if (priv->irq_wake)
3935                 pm_wakeup_event(priv->device, 0);
3936
3937         if (unlikely(!dev)) {
3938                 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
3939                 return IRQ_NONE;
3940         }
3941
3942         /* Check if adapter is up */
3943         if (test_bit(STMMAC_DOWN, &priv->state))
3944                 return IRQ_HANDLED;
3945         /* Check if a fatal error happened */
3946         if (stmmac_safety_feat_interrupt(priv))
3947                 return IRQ_HANDLED;
3948
3949         /* To handle GMAC own interrupts */
3950         if ((priv->plat->has_gmac) || xmac) {
3951                 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
3952                 int mtl_status;
3953
3954                 if (unlikely(status)) {
3955                         /* For LPI we need to save the tx status */
3956                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
3957                                 priv->tx_path_in_lpi_mode = true;
3958                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
3959                                 priv->tx_path_in_lpi_mode = false;
3960                 }
3961
3962                 for (queue = 0; queue < queues_count; queue++) {
3963                         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3964
3965                         mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw,
3966                                                                 queue);
3967                         if (mtl_status != -EINVAL)
3968                                 status |= mtl_status;
3969
3970                         if (status & CORE_IRQ_MTL_RX_OVERFLOW)
3971                                 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
3972                                                        rx_q->rx_tail_addr,
3973                                                        queue);
3974                 }
3975
3976                 /* PCS link status */
3977                 if (priv->hw->pcs) {
3978                         if (priv->xstats.pcs_link)
3979                                 netif_carrier_on(dev);
3980                         else
3981                                 netif_carrier_off(dev);
3982                 }
3983         }
3984
3985         /* To handle DMA interrupts */
3986         stmmac_dma_interrupt(priv);
3987
3988         return IRQ_HANDLED;
3989 }
3990
3991 #ifdef CONFIG_NET_POLL_CONTROLLER
3992 /* Polling receive - used by NETCONSOLE and other diagnostic tools
3993  * to allow network I/O with interrupts disabled.
3994  */
3995 static void stmmac_poll_controller(struct net_device *dev)
3996 {
3997         disable_irq(dev->irq);
3998         stmmac_interrupt(dev->irq, dev);
3999         enable_irq(dev->irq);
4000 }
4001 #endif
4002
4003 /**
4004  *  stmmac_ioctl - Entry point for the Ioctl
4005  *  @dev: Device pointer.
4006  *  @rq: An IOCTL specefic structure, that can contain a pointer to
4007  *  a proprietary structure used to pass information to the driver.
4008  *  @cmd: IOCTL command
4009  *  Description:
4010  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
4011  */
4012 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
4013 {
4014         struct stmmac_priv *priv = netdev_priv (dev);
4015         int ret = -EOPNOTSUPP;
4016
4017         if (!netif_running(dev))
4018                 return -EINVAL;
4019
4020         switch (cmd) {
4021         case SIOCGMIIPHY:
4022         case SIOCGMIIREG:
4023         case SIOCSMIIREG:
4024                 ret = phylink_mii_ioctl(priv->phylink, rq, cmd);
4025                 break;
4026         case SIOCSHWTSTAMP:
4027                 ret = stmmac_hwtstamp_set(dev, rq);
4028                 break;
4029         case SIOCGHWTSTAMP:
4030                 ret = stmmac_hwtstamp_get(dev, rq);
4031                 break;
4032         default:
4033                 break;
4034         }
4035
4036         return ret;
4037 }
4038
4039 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
4040                                     void *cb_priv)
4041 {
4042         struct stmmac_priv *priv = cb_priv;
4043         int ret = -EOPNOTSUPP;
4044
4045         if (!tc_cls_can_offload_and_chain0(priv->dev, type_data))
4046                 return ret;
4047
4048         stmmac_disable_all_queues(priv);
4049
4050         switch (type) {
4051         case TC_SETUP_CLSU32:
4052                 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data);
4053                 break;
4054         case TC_SETUP_CLSFLOWER:
4055                 ret = stmmac_tc_setup_cls(priv, priv, type_data);
4056                 break;
4057         default:
4058                 break;
4059         }
4060
4061         stmmac_enable_all_queues(priv);
4062         return ret;
4063 }
4064
4065 static LIST_HEAD(stmmac_block_cb_list);
4066
4067 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
4068                            void *type_data)
4069 {
4070         struct stmmac_priv *priv = netdev_priv(ndev);
4071
4072         switch (type) {
4073         case TC_SETUP_BLOCK:
4074                 return flow_block_cb_setup_simple(type_data,
4075                                                   &stmmac_block_cb_list,
4076                                                   stmmac_setup_tc_block_cb,
4077                                                   priv, priv, true);
4078         case TC_SETUP_QDISC_CBS:
4079                 return stmmac_tc_setup_cbs(priv, priv, type_data);
4080         default:
4081                 return -EOPNOTSUPP;
4082         }
4083 }
4084
4085 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb,
4086                                struct net_device *sb_dev)
4087 {
4088         int gso = skb_shinfo(skb)->gso_type;
4089
4090         if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) {
4091                 /*
4092                  * There is no way to determine the number of TSO/USO
4093                  * capable Queues. Let's use always the Queue 0
4094                  * because if TSO/USO is supported then at least this
4095                  * one will be capable.
4096                  */
4097                 return 0;
4098         }
4099
4100         return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues;
4101 }
4102
4103 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
4104 {
4105         struct stmmac_priv *priv = netdev_priv(ndev);
4106         int ret = 0;
4107
4108         ret = eth_mac_addr(ndev, addr);
4109         if (ret)
4110                 return ret;
4111
4112         stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
4113
4114         return ret;
4115 }
4116
4117 #ifdef CONFIG_DEBUG_FS
4118 static struct dentry *stmmac_fs_dir;
4119
4120 static void sysfs_display_ring(void *head, int size, int extend_desc,
4121                                struct seq_file *seq)
4122 {
4123         int i;
4124         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
4125         struct dma_desc *p = (struct dma_desc *)head;
4126
4127         for (i = 0; i < size; i++) {
4128                 if (extend_desc) {
4129                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
4130                                    i, (unsigned int)virt_to_phys(ep),
4131                                    le32_to_cpu(ep->basic.des0),
4132                                    le32_to_cpu(ep->basic.des1),
4133                                    le32_to_cpu(ep->basic.des2),
4134                                    le32_to_cpu(ep->basic.des3));
4135                         ep++;
4136                 } else {
4137                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
4138                                    i, (unsigned int)virt_to_phys(p),
4139                                    le32_to_cpu(p->des0), le32_to_cpu(p->des1),
4140                                    le32_to_cpu(p->des2), le32_to_cpu(p->des3));
4141                         p++;
4142                 }
4143                 seq_printf(seq, "\n");
4144         }
4145 }
4146
4147 static int stmmac_rings_status_show(struct seq_file *seq, void *v)
4148 {
4149         struct net_device *dev = seq->private;
4150         struct stmmac_priv *priv = netdev_priv(dev);
4151         u32 rx_count = priv->plat->rx_queues_to_use;
4152         u32 tx_count = priv->plat->tx_queues_to_use;
4153         u32 queue;
4154
4155         if ((dev->flags & IFF_UP) == 0)
4156                 return 0;
4157
4158         for (queue = 0; queue < rx_count; queue++) {
4159                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4160
4161                 seq_printf(seq, "RX Queue %d:\n", queue);
4162
4163                 if (priv->extend_desc) {
4164                         seq_printf(seq, "Extended descriptor ring:\n");
4165                         sysfs_display_ring((void *)rx_q->dma_erx,
4166                                            DMA_RX_SIZE, 1, seq);
4167                 } else {
4168                         seq_printf(seq, "Descriptor ring:\n");
4169                         sysfs_display_ring((void *)rx_q->dma_rx,
4170                                            DMA_RX_SIZE, 0, seq);
4171                 }
4172         }
4173
4174         for (queue = 0; queue < tx_count; queue++) {
4175                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4176
4177                 seq_printf(seq, "TX Queue %d:\n", queue);
4178
4179                 if (priv->extend_desc) {
4180                         seq_printf(seq, "Extended descriptor ring:\n");
4181                         sysfs_display_ring((void *)tx_q->dma_etx,
4182                                            DMA_TX_SIZE, 1, seq);
4183                 } else {
4184                         seq_printf(seq, "Descriptor ring:\n");
4185                         sysfs_display_ring((void *)tx_q->dma_tx,
4186                                            DMA_TX_SIZE, 0, seq);
4187                 }
4188         }
4189
4190         return 0;
4191 }
4192 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status);
4193
4194 static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
4195 {
4196         struct net_device *dev = seq->private;
4197         struct stmmac_priv *priv = netdev_priv(dev);
4198
4199         if (!priv->hw_cap_support) {
4200                 seq_printf(seq, "DMA HW features not supported\n");
4201                 return 0;
4202         }
4203
4204         seq_printf(seq, "==============================\n");
4205         seq_printf(seq, "\tDMA HW features\n");
4206         seq_printf(seq, "==============================\n");
4207
4208         seq_printf(seq, "\t10/100 Mbps: %s\n",
4209                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
4210         seq_printf(seq, "\t1000 Mbps: %s\n",
4211                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
4212         seq_printf(seq, "\tHalf duplex: %s\n",
4213                    (priv->dma_cap.half_duplex) ? "Y" : "N");
4214         seq_printf(seq, "\tHash Filter: %s\n",
4215                    (priv->dma_cap.hash_filter) ? "Y" : "N");
4216         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
4217                    (priv->dma_cap.multi_addr) ? "Y" : "N");
4218         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
4219                    (priv->dma_cap.pcs) ? "Y" : "N");
4220         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
4221                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
4222         seq_printf(seq, "\tPMT Remote wake up: %s\n",
4223                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
4224         seq_printf(seq, "\tPMT Magic Frame: %s\n",
4225                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
4226         seq_printf(seq, "\tRMON module: %s\n",
4227                    (priv->dma_cap.rmon) ? "Y" : "N");
4228         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
4229                    (priv->dma_cap.time_stamp) ? "Y" : "N");
4230         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
4231                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
4232         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
4233                    (priv->dma_cap.eee) ? "Y" : "N");
4234         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
4235         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
4236                    (priv->dma_cap.tx_coe) ? "Y" : "N");
4237         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
4238                 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
4239                            (priv->dma_cap.rx_coe) ? "Y" : "N");
4240         } else {
4241                 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
4242                            (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
4243                 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
4244                            (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
4245         }
4246         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
4247                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
4248         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
4249                    priv->dma_cap.number_rx_channel);
4250         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
4251                    priv->dma_cap.number_tx_channel);
4252         seq_printf(seq, "\tEnhanced descriptors: %s\n",
4253                    (priv->dma_cap.enh_desc) ? "Y" : "N");
4254
4255         return 0;
4256 }
4257 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap);
4258
4259 static void stmmac_init_fs(struct net_device *dev)
4260 {
4261         struct stmmac_priv *priv = netdev_priv(dev);
4262
4263         /* Create per netdev entries */
4264         priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
4265
4266         /* Entry to report DMA RX/TX rings */
4267         debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev,
4268                             &stmmac_rings_status_fops);
4269
4270         /* Entry to report the DMA HW features */
4271         debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev,
4272                             &stmmac_dma_cap_fops);
4273 }
4274
4275 static void stmmac_exit_fs(struct net_device *dev)
4276 {
4277         struct stmmac_priv *priv = netdev_priv(dev);
4278
4279         debugfs_remove_recursive(priv->dbgfs_dir);
4280 }
4281 #endif /* CONFIG_DEBUG_FS */
4282
4283 static u32 stmmac_vid_crc32_le(__le16 vid_le)
4284 {
4285         unsigned char *data = (unsigned char *)&vid_le;
4286         unsigned char data_byte = 0;
4287         u32 crc = ~0x0;
4288         u32 temp = 0;
4289         int i, bits;
4290
4291         bits = get_bitmask_order(VLAN_VID_MASK);
4292         for (i = 0; i < bits; i++) {
4293                 if ((i % 8) == 0)
4294                         data_byte = data[i / 8];
4295
4296                 temp = ((crc & 1) ^ data_byte) & 1;
4297                 crc >>= 1;
4298                 data_byte >>= 1;
4299
4300                 if (temp)
4301                         crc ^= 0xedb88320;
4302         }
4303
4304         return crc;
4305 }
4306
4307 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double)
4308 {
4309         u32 crc, hash = 0;
4310         __le16 pmatch = 0;
4311         int count = 0;
4312         u16 vid = 0;
4313
4314         for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
4315                 __le16 vid_le = cpu_to_le16(vid);
4316                 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28;
4317                 hash |= (1 << crc);
4318                 count++;
4319         }
4320
4321         if (!priv->dma_cap.vlhash) {
4322                 if (count > 2) /* VID = 0 always passes filter */
4323                         return -EOPNOTSUPP;
4324
4325                 pmatch = cpu_to_le16(vid);
4326                 hash = 0;
4327         }
4328
4329         return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double);
4330 }
4331
4332 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)
4333 {
4334         struct stmmac_priv *priv = netdev_priv(ndev);
4335         bool is_double = false;
4336         int ret;
4337
4338         if (be16_to_cpu(proto) == ETH_P_8021AD)
4339                 is_double = true;
4340
4341         set_bit(vid, priv->active_vlans);
4342         ret = stmmac_vlan_update(priv, is_double);
4343         if (ret) {
4344                 clear_bit(vid, priv->active_vlans);
4345                 return ret;
4346         }
4347
4348         return ret;
4349 }
4350
4351 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid)
4352 {
4353         struct stmmac_priv *priv = netdev_priv(ndev);
4354         bool is_double = false;
4355
4356         if (be16_to_cpu(proto) == ETH_P_8021AD)
4357                 is_double = true;
4358
4359         clear_bit(vid, priv->active_vlans);
4360         return stmmac_vlan_update(priv, is_double);
4361 }
4362
4363 static const struct net_device_ops stmmac_netdev_ops = {
4364         .ndo_open = stmmac_open,
4365         .ndo_start_xmit = stmmac_xmit,
4366         .ndo_stop = stmmac_release,
4367         .ndo_change_mtu = stmmac_change_mtu,
4368         .ndo_fix_features = stmmac_fix_features,
4369         .ndo_set_features = stmmac_set_features,
4370         .ndo_set_rx_mode = stmmac_set_rx_mode,
4371         .ndo_tx_timeout = stmmac_tx_timeout,
4372         .ndo_do_ioctl = stmmac_ioctl,
4373         .ndo_setup_tc = stmmac_setup_tc,
4374         .ndo_select_queue = stmmac_select_queue,
4375 #ifdef CONFIG_NET_POLL_CONTROLLER
4376         .ndo_poll_controller = stmmac_poll_controller,
4377 #endif
4378         .ndo_set_mac_address = stmmac_set_mac_address,
4379         .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid,
4380         .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid,
4381 };
4382
4383 static void stmmac_reset_subtask(struct stmmac_priv *priv)
4384 {
4385         if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state))
4386                 return;
4387         if (test_bit(STMMAC_DOWN, &priv->state))
4388                 return;
4389
4390         netdev_err(priv->dev, "Reset adapter.\n");
4391
4392         rtnl_lock();
4393         netif_trans_update(priv->dev);
4394         while (test_and_set_bit(STMMAC_RESETING, &priv->state))
4395                 usleep_range(1000, 2000);
4396
4397         set_bit(STMMAC_DOWN, &priv->state);
4398         dev_close(priv->dev);
4399         dev_open(priv->dev, NULL);
4400         clear_bit(STMMAC_DOWN, &priv->state);
4401         clear_bit(STMMAC_RESETING, &priv->state);
4402         rtnl_unlock();
4403 }
4404
4405 static void stmmac_service_task(struct work_struct *work)
4406 {
4407         struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
4408                         service_task);
4409
4410         stmmac_reset_subtask(priv);
4411         clear_bit(STMMAC_SERVICE_SCHED, &priv->state);
4412 }
4413
4414 /**
4415  *  stmmac_hw_init - Init the MAC device
4416  *  @priv: driver private structure
4417  *  Description: this function is to configure the MAC device according to
4418  *  some platform parameters or the HW capability register. It prepares the
4419  *  driver to use either ring or chain modes and to setup either enhanced or
4420  *  normal descriptors.
4421  */
4422 static int stmmac_hw_init(struct stmmac_priv *priv)
4423 {
4424         int ret;
4425
4426         /* dwmac-sun8i only work in chain mode */
4427         if (priv->plat->has_sun8i)
4428                 chain_mode = 1;
4429         priv->chain_mode = chain_mode;
4430
4431         /* Initialize HW Interface */
4432         ret = stmmac_hwif_init(priv);
4433         if (ret)
4434                 return ret;
4435
4436         /* Get the HW capability (new GMAC newer than 3.50a) */
4437         priv->hw_cap_support = stmmac_get_hw_features(priv);
4438         if (priv->hw_cap_support) {
4439                 dev_info(priv->device, "DMA HW capability register supported\n");
4440
4441                 /* We can override some gmac/dma configuration fields: e.g.
4442                  * enh_desc, tx_coe (e.g. that are passed through the
4443                  * platform) with the values from the HW capability
4444                  * register (if supported).
4445                  */
4446                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
4447                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
4448                 priv->hw->pmt = priv->plat->pmt;
4449                 if (priv->dma_cap.hash_tb_sz) {
4450                         priv->hw->multicast_filter_bins =
4451                                         (BIT(priv->dma_cap.hash_tb_sz) << 5);
4452                         priv->hw->mcast_bits_log2 =
4453                                         ilog2(priv->hw->multicast_filter_bins);
4454                 }
4455
4456                 /* TXCOE doesn't work in thresh DMA mode */
4457                 if (priv->plat->force_thresh_dma_mode)
4458                         priv->plat->tx_coe = 0;
4459                 else
4460                         priv->plat->tx_coe = priv->dma_cap.tx_coe;
4461
4462                 /* In case of GMAC4 rx_coe is from HW cap register. */
4463                 priv->plat->rx_coe = priv->dma_cap.rx_coe;
4464
4465                 if (priv->dma_cap.rx_coe_type2)
4466                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
4467                 else if (priv->dma_cap.rx_coe_type1)
4468                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
4469
4470         } else {
4471                 dev_info(priv->device, "No HW DMA feature register supported\n");
4472         }
4473
4474         if (priv->plat->rx_coe) {
4475                 priv->hw->rx_csum = priv->plat->rx_coe;
4476                 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
4477                 if (priv->synopsys_id < DWMAC_CORE_4_00)
4478                         dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
4479         }
4480         if (priv->plat->tx_coe)
4481                 dev_info(priv->device, "TX Checksum insertion supported\n");
4482
4483         if (priv->plat->pmt) {
4484                 dev_info(priv->device, "Wake-Up On Lan supported\n");
4485                 device_set_wakeup_capable(priv->device, 1);
4486         }
4487
4488         if (priv->dma_cap.tsoen)
4489                 dev_info(priv->device, "TSO supported\n");
4490
4491         /* Run HW quirks, if any */
4492         if (priv->hwif_quirks) {
4493                 ret = priv->hwif_quirks(priv);
4494                 if (ret)
4495                         return ret;
4496         }
4497
4498         /* Rx Watchdog is available in the COREs newer than the 3.40.
4499          * In some case, for example on bugged HW this feature
4500          * has to be disable and this can be done by passing the
4501          * riwt_off field from the platform.
4502          */
4503         if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
4504             (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
4505                 priv->use_riwt = 1;
4506                 dev_info(priv->device,
4507                          "Enable RX Mitigation via HW Watchdog Timer\n");
4508         }
4509
4510         return 0;
4511 }
4512
4513 /**
4514  * stmmac_dvr_probe
4515  * @device: device pointer
4516  * @plat_dat: platform data pointer
4517  * @res: stmmac resource pointer
4518  * Description: this is the main probe function used to
4519  * call the alloc_etherdev, allocate the priv structure.
4520  * Return:
4521  * returns 0 on success, otherwise errno.
4522  */
4523 int stmmac_dvr_probe(struct device *device,
4524                      struct plat_stmmacenet_data *plat_dat,
4525                      struct stmmac_resources *res)
4526 {
4527         struct net_device *ndev = NULL;
4528         struct stmmac_priv *priv;
4529         u32 queue, rxq, maxq;
4530         int i, ret = 0;
4531
4532         ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv),
4533                                        MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES);
4534         if (!ndev)
4535                 return -ENOMEM;
4536
4537         SET_NETDEV_DEV(ndev, device);
4538
4539         priv = netdev_priv(ndev);
4540         priv->device = device;
4541         priv->dev = ndev;
4542
4543         stmmac_set_ethtool_ops(ndev);
4544         priv->pause = pause;
4545         priv->plat = plat_dat;
4546         priv->ioaddr = res->addr;
4547         priv->dev->base_addr = (unsigned long)res->addr;
4548
4549         priv->dev->irq = res->irq;
4550         priv->wol_irq = res->wol_irq;
4551         priv->lpi_irq = res->lpi_irq;
4552
4553         if (!IS_ERR_OR_NULL(res->mac))
4554                 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
4555
4556         dev_set_drvdata(device, priv->dev);
4557
4558         /* Verify driver arguments */
4559         stmmac_verify_args();
4560
4561         /* Allocate workqueue */
4562         priv->wq = create_singlethread_workqueue("stmmac_wq");
4563         if (!priv->wq) {
4564                 dev_err(priv->device, "failed to create workqueue\n");
4565                 return -ENOMEM;
4566         }
4567
4568         INIT_WORK(&priv->service_task, stmmac_service_task);
4569
4570         /* Override with kernel parameters if supplied XXX CRS XXX
4571          * this needs to have multiple instances
4572          */
4573         if ((phyaddr >= 0) && (phyaddr <= 31))
4574                 priv->plat->phy_addr = phyaddr;
4575
4576         if (priv->plat->stmmac_rst) {
4577                 ret = reset_control_assert(priv->plat->stmmac_rst);
4578                 reset_control_deassert(priv->plat->stmmac_rst);
4579                 /* Some reset controllers have only reset callback instead of
4580                  * assert + deassert callbacks pair.
4581                  */
4582                 if (ret == -ENOTSUPP)
4583                         reset_control_reset(priv->plat->stmmac_rst);
4584         }
4585
4586         /* Init MAC and get the capabilities */
4587         ret = stmmac_hw_init(priv);
4588         if (ret)
4589                 goto error_hw_init;
4590
4591         stmmac_check_ether_addr(priv);
4592
4593         /* Configure real RX and TX queues */
4594         netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use);
4595         netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use);
4596
4597         ndev->netdev_ops = &stmmac_netdev_ops;
4598
4599         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4600                             NETIF_F_RXCSUM;
4601
4602         ret = stmmac_tc_init(priv, priv);
4603         if (!ret) {
4604                 ndev->hw_features |= NETIF_F_HW_TC;
4605         }
4606
4607         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
4608                 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
4609                 if (priv->plat->has_gmac4)
4610                         ndev->hw_features |= NETIF_F_GSO_UDP_L4;
4611                 priv->tso = true;
4612                 dev_info(priv->device, "TSO feature enabled\n");
4613         }
4614
4615         if (priv->dma_cap.sphen) {
4616                 ndev->hw_features |= NETIF_F_GRO;
4617                 priv->sph = true;
4618                 dev_info(priv->device, "SPH feature enabled\n");
4619         }
4620
4621         if (priv->dma_cap.addr64) {
4622                 ret = dma_set_mask_and_coherent(device,
4623                                 DMA_BIT_MASK(priv->dma_cap.addr64));
4624                 if (!ret) {
4625                         dev_info(priv->device, "Using %d bits DMA width\n",
4626                                  priv->dma_cap.addr64);
4627
4628                         /*
4629                          * If more than 32 bits can be addressed, make sure to
4630                          * enable enhanced addressing mode.
4631                          */
4632                         if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
4633                                 priv->plat->dma_cfg->eame = true;
4634                 } else {
4635                         ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32));
4636                         if (ret) {
4637                                 dev_err(priv->device, "Failed to set DMA Mask\n");
4638                                 goto error_hw_init;
4639                         }
4640
4641                         priv->dma_cap.addr64 = 32;
4642                 }
4643         }
4644
4645         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
4646         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
4647 #ifdef STMMAC_VLAN_TAG_USED
4648         /* Both mac100 and gmac support receive VLAN tag detection */
4649         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
4650         if (priv->dma_cap.vlhash) {
4651                 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4652                 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
4653         }
4654         if (priv->dma_cap.vlins) {
4655                 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX;
4656                 if (priv->dma_cap.dvlan)
4657                         ndev->features |= NETIF_F_HW_VLAN_STAG_TX;
4658         }
4659 #endif
4660         priv->msg_enable = netif_msg_init(debug, default_msg_level);
4661
4662         /* Initialize RSS */
4663         rxq = priv->plat->rx_queues_to_use;
4664         netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key));
4665         for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
4666                 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq);
4667
4668         if (priv->dma_cap.rssen && priv->plat->rss_en)
4669                 ndev->features |= NETIF_F_RXHASH;
4670
4671         /* MTU range: 46 - hw-specific max */
4672         ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
4673         if (priv->plat->has_xgmac)
4674                 ndev->max_mtu = XGMAC_JUMBO_LEN;
4675         else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
4676                 ndev->max_mtu = JUMBO_LEN;
4677         else
4678                 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
4679         /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
4680          * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
4681          */
4682         if ((priv->plat->maxmtu < ndev->max_mtu) &&
4683             (priv->plat->maxmtu >= ndev->min_mtu))
4684                 ndev->max_mtu = priv->plat->maxmtu;
4685         else if (priv->plat->maxmtu < ndev->min_mtu)
4686                 dev_warn(priv->device,
4687                          "%s: warning: maxmtu having invalid value (%d)\n",
4688                          __func__, priv->plat->maxmtu);
4689
4690         if (flow_ctrl)
4691                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
4692
4693         /* Setup channels NAPI */
4694         maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
4695
4696         for (queue = 0; queue < maxq; queue++) {
4697                 struct stmmac_channel *ch = &priv->channel[queue];
4698
4699                 ch->priv_data = priv;
4700                 ch->index = queue;
4701
4702                 if (queue < priv->plat->rx_queues_to_use) {
4703                         netif_napi_add(ndev, &ch->rx_napi, stmmac_napi_poll_rx,
4704                                        NAPI_POLL_WEIGHT);
4705                 }
4706                 if (queue < priv->plat->tx_queues_to_use) {
4707                         netif_tx_napi_add(ndev, &ch->tx_napi,
4708                                           stmmac_napi_poll_tx,
4709                                           NAPI_POLL_WEIGHT);
4710                 }
4711         }
4712
4713         mutex_init(&priv->lock);
4714
4715         /* If a specific clk_csr value is passed from the platform
4716          * this means that the CSR Clock Range selection cannot be
4717          * changed at run-time and it is fixed. Viceversa the driver'll try to
4718          * set the MDC clock dynamically according to the csr actual
4719          * clock input.
4720          */
4721         if (priv->plat->clk_csr >= 0)
4722                 priv->clk_csr = priv->plat->clk_csr;
4723         else
4724                 stmmac_clk_csr_set(priv);
4725
4726         stmmac_check_pcs_mode(priv);
4727
4728         if (priv->hw->pcs != STMMAC_PCS_RGMII  &&
4729             priv->hw->pcs != STMMAC_PCS_TBI &&
4730             priv->hw->pcs != STMMAC_PCS_RTBI) {
4731                 /* MDIO bus Registration */
4732                 ret = stmmac_mdio_register(ndev);
4733                 if (ret < 0) {
4734                         dev_err(priv->device,
4735                                 "%s: MDIO bus (id: %d) registration failed",
4736                                 __func__, priv->plat->bus_id);
4737                         goto error_mdio_register;
4738                 }
4739         }
4740
4741         ret = stmmac_phy_setup(priv);
4742         if (ret) {
4743                 netdev_err(ndev, "failed to setup phy (%d)\n", ret);
4744                 goto error_phy_setup;
4745         }
4746
4747         ret = register_netdev(ndev);
4748         if (ret) {
4749                 dev_err(priv->device, "%s: ERROR %i registering the device\n",
4750                         __func__, ret);
4751                 goto error_netdev_register;
4752         }
4753
4754 #ifdef CONFIG_DEBUG_FS
4755         stmmac_init_fs(ndev);
4756 #endif
4757
4758         return ret;
4759
4760 error_netdev_register:
4761         phylink_destroy(priv->phylink);
4762 error_phy_setup:
4763         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4764             priv->hw->pcs != STMMAC_PCS_TBI &&
4765             priv->hw->pcs != STMMAC_PCS_RTBI)
4766                 stmmac_mdio_unregister(ndev);
4767 error_mdio_register:
4768         for (queue = 0; queue < maxq; queue++) {
4769                 struct stmmac_channel *ch = &priv->channel[queue];
4770
4771                 if (queue < priv->plat->rx_queues_to_use)
4772                         netif_napi_del(&ch->rx_napi);
4773                 if (queue < priv->plat->tx_queues_to_use)
4774                         netif_napi_del(&ch->tx_napi);
4775         }
4776 error_hw_init:
4777         destroy_workqueue(priv->wq);
4778
4779         return ret;
4780 }
4781 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
4782
4783 /**
4784  * stmmac_dvr_remove
4785  * @dev: device pointer
4786  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
4787  * changes the link status, releases the DMA descriptor rings.
4788  */
4789 int stmmac_dvr_remove(struct device *dev)
4790 {
4791         struct net_device *ndev = dev_get_drvdata(dev);
4792         struct stmmac_priv *priv = netdev_priv(ndev);
4793
4794         netdev_info(priv->dev, "%s: removing driver", __func__);
4795
4796 #ifdef CONFIG_DEBUG_FS
4797         stmmac_exit_fs(ndev);
4798 #endif
4799         stmmac_stop_all_dma(priv);
4800
4801         stmmac_mac_set(priv, priv->ioaddr, false);
4802         netif_carrier_off(ndev);
4803         unregister_netdev(ndev);
4804         phylink_destroy(priv->phylink);
4805         if (priv->plat->stmmac_rst)
4806                 reset_control_assert(priv->plat->stmmac_rst);
4807         clk_disable_unprepare(priv->plat->pclk);
4808         clk_disable_unprepare(priv->plat->stmmac_clk);
4809         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4810             priv->hw->pcs != STMMAC_PCS_TBI &&
4811             priv->hw->pcs != STMMAC_PCS_RTBI)
4812                 stmmac_mdio_unregister(ndev);
4813         destroy_workqueue(priv->wq);
4814         mutex_destroy(&priv->lock);
4815
4816         return 0;
4817 }
4818 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
4819
4820 /**
4821  * stmmac_suspend - suspend callback
4822  * @dev: device pointer
4823  * Description: this is the function to suspend the device and it is called
4824  * by the platform driver to stop the network queue, release the resources,
4825  * program the PMT register (for WoL), clean and release driver resources.
4826  */
4827 int stmmac_suspend(struct device *dev)
4828 {
4829         struct net_device *ndev = dev_get_drvdata(dev);
4830         struct stmmac_priv *priv = netdev_priv(ndev);
4831
4832         if (!ndev || !netif_running(ndev))
4833                 return 0;
4834
4835         phylink_mac_change(priv->phylink, false);
4836
4837         mutex_lock(&priv->lock);
4838
4839         netif_device_detach(ndev);
4840         stmmac_stop_all_queues(priv);
4841
4842         stmmac_disable_all_queues(priv);
4843
4844         /* Stop TX/RX DMA */
4845         stmmac_stop_all_dma(priv);
4846
4847         /* Enable Power down mode by programming the PMT regs */
4848         if (device_may_wakeup(priv->device)) {
4849                 stmmac_pmt(priv, priv->hw, priv->wolopts);
4850                 priv->irq_wake = 1;
4851         } else {
4852                 mutex_unlock(&priv->lock);
4853                 rtnl_lock();
4854                 phylink_stop(priv->phylink);
4855                 rtnl_unlock();
4856                 mutex_lock(&priv->lock);
4857
4858                 stmmac_mac_set(priv, priv->ioaddr, false);
4859                 pinctrl_pm_select_sleep_state(priv->device);
4860                 /* Disable clock in case of PWM is off */
4861                 if (priv->plat->clk_ptp_ref)
4862                         clk_disable_unprepare(priv->plat->clk_ptp_ref);
4863                 clk_disable_unprepare(priv->plat->pclk);
4864                 clk_disable_unprepare(priv->plat->stmmac_clk);
4865         }
4866         mutex_unlock(&priv->lock);
4867
4868         priv->speed = SPEED_UNKNOWN;
4869         return 0;
4870 }
4871 EXPORT_SYMBOL_GPL(stmmac_suspend);
4872
4873 /**
4874  * stmmac_reset_queues_param - reset queue parameters
4875  * @dev: device pointer
4876  */
4877 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
4878 {
4879         u32 rx_cnt = priv->plat->rx_queues_to_use;
4880         u32 tx_cnt = priv->plat->tx_queues_to_use;
4881         u32 queue;
4882
4883         for (queue = 0; queue < rx_cnt; queue++) {
4884                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4885
4886                 rx_q->cur_rx = 0;
4887                 rx_q->dirty_rx = 0;
4888         }
4889
4890         for (queue = 0; queue < tx_cnt; queue++) {
4891                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4892
4893                 tx_q->cur_tx = 0;
4894                 tx_q->dirty_tx = 0;
4895                 tx_q->mss = 0;
4896         }
4897 }
4898
4899 /**
4900  * stmmac_resume - resume callback
4901  * @dev: device pointer
4902  * Description: when resume this function is invoked to setup the DMA and CORE
4903  * in a usable state.
4904  */
4905 int stmmac_resume(struct device *dev)
4906 {
4907         struct net_device *ndev = dev_get_drvdata(dev);
4908         struct stmmac_priv *priv = netdev_priv(ndev);
4909
4910         if (!netif_running(ndev))
4911                 return 0;
4912
4913         /* Power Down bit, into the PM register, is cleared
4914          * automatically as soon as a magic packet or a Wake-up frame
4915          * is received. Anyway, it's better to manually clear
4916          * this bit because it can generate problems while resuming
4917          * from another devices (e.g. serial console).
4918          */
4919         if (device_may_wakeup(priv->device)) {
4920                 mutex_lock(&priv->lock);
4921                 stmmac_pmt(priv, priv->hw, 0);
4922                 mutex_unlock(&priv->lock);
4923                 priv->irq_wake = 0;
4924         } else {
4925                 pinctrl_pm_select_default_state(priv->device);
4926                 /* enable the clk previously disabled */
4927                 clk_prepare_enable(priv->plat->stmmac_clk);
4928                 clk_prepare_enable(priv->plat->pclk);
4929                 if (priv->plat->clk_ptp_ref)
4930                         clk_prepare_enable(priv->plat->clk_ptp_ref);
4931                 /* reset the phy so that it's ready */
4932                 if (priv->mii)
4933                         stmmac_mdio_reset(priv->mii);
4934         }
4935
4936         netif_device_attach(ndev);
4937
4938         mutex_lock(&priv->lock);
4939
4940         stmmac_reset_queues_param(priv);
4941
4942         stmmac_clear_descriptors(priv);
4943
4944         stmmac_hw_setup(ndev, false);
4945         stmmac_init_coalesce(priv);
4946         stmmac_set_rx_mode(ndev);
4947
4948         stmmac_enable_all_queues(priv);
4949
4950         stmmac_start_all_queues(priv);
4951
4952         mutex_unlock(&priv->lock);
4953
4954         if (!device_may_wakeup(priv->device)) {
4955                 rtnl_lock();
4956                 phylink_start(priv->phylink);
4957                 rtnl_unlock();
4958         }
4959
4960         phylink_mac_change(priv->phylink, true);
4961
4962         return 0;
4963 }
4964 EXPORT_SYMBOL_GPL(stmmac_resume);
4965
4966 #ifndef MODULE
4967 static int __init stmmac_cmdline_opt(char *str)
4968 {
4969         char *opt;
4970
4971         if (!str || !*str)
4972                 return -EINVAL;
4973         while ((opt = strsep(&str, ",")) != NULL) {
4974                 if (!strncmp(opt, "debug:", 6)) {
4975                         if (kstrtoint(opt + 6, 0, &debug))
4976                                 goto err;
4977                 } else if (!strncmp(opt, "phyaddr:", 8)) {
4978                         if (kstrtoint(opt + 8, 0, &phyaddr))
4979                                 goto err;
4980                 } else if (!strncmp(opt, "buf_sz:", 7)) {
4981                         if (kstrtoint(opt + 7, 0, &buf_sz))
4982                                 goto err;
4983                 } else if (!strncmp(opt, "tc:", 3)) {
4984                         if (kstrtoint(opt + 3, 0, &tc))
4985                                 goto err;
4986                 } else if (!strncmp(opt, "watchdog:", 9)) {
4987                         if (kstrtoint(opt + 9, 0, &watchdog))
4988                                 goto err;
4989                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
4990                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
4991                                 goto err;
4992                 } else if (!strncmp(opt, "pause:", 6)) {
4993                         if (kstrtoint(opt + 6, 0, &pause))
4994                                 goto err;
4995                 } else if (!strncmp(opt, "eee_timer:", 10)) {
4996                         if (kstrtoint(opt + 10, 0, &eee_timer))
4997                                 goto err;
4998                 } else if (!strncmp(opt, "chain_mode:", 11)) {
4999                         if (kstrtoint(opt + 11, 0, &chain_mode))
5000                                 goto err;
5001                 }
5002         }
5003         return 0;
5004
5005 err:
5006         pr_err("%s: ERROR broken module parameter conversion", __func__);
5007         return -EINVAL;
5008 }
5009
5010 __setup("stmmaceth=", stmmac_cmdline_opt);
5011 #endif /* MODULE */
5012
5013 static int __init stmmac_init(void)
5014 {
5015 #ifdef CONFIG_DEBUG_FS
5016         /* Create debugfs main directory if it doesn't exist yet */
5017         if (!stmmac_fs_dir)
5018                 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
5019 #endif
5020
5021         return 0;
5022 }
5023
5024 static void __exit stmmac_exit(void)
5025 {
5026 #ifdef CONFIG_DEBUG_FS
5027         debugfs_remove_recursive(stmmac_fs_dir);
5028 #endif
5029 }
5030
5031 module_init(stmmac_init)
5032 module_exit(stmmac_exit)
5033
5034 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
5035 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
5036 MODULE_LICENSE("GPL");