2 * Texas Instruments Ethernet Switch Driver
4 * Copyright (C) 2012 Texas Instruments
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/kernel.h>
18 #include <linux/clk.h>
19 #include <linux/timer.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/irqreturn.h>
23 #include <linux/interrupt.h>
24 #include <linux/if_ether.h>
25 #include <linux/etherdevice.h>
26 #include <linux/netdevice.h>
27 #include <linux/net_tstamp.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/delay.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/gpio.h>
34 #include <linux/of_mdio.h>
35 #include <linux/of_net.h>
36 #include <linux/of_device.h>
37 #include <linux/if_vlan.h>
39 #include <linux/pinctrl/consumer.h>
44 #include "davinci_cpdma.h"
46 #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
47 NETIF_MSG_DRV | NETIF_MSG_LINK | \
48 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
49 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
50 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
51 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
52 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
55 #define cpsw_info(priv, type, format, ...) \
57 if (netif_msg_##type(priv) && net_ratelimit()) \
58 dev_info(priv->dev, format, ## __VA_ARGS__); \
61 #define cpsw_err(priv, type, format, ...) \
63 if (netif_msg_##type(priv) && net_ratelimit()) \
64 dev_err(priv->dev, format, ## __VA_ARGS__); \
67 #define cpsw_dbg(priv, type, format, ...) \
69 if (netif_msg_##type(priv) && net_ratelimit()) \
70 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
73 #define cpsw_notice(priv, type, format, ...) \
75 if (netif_msg_##type(priv) && net_ratelimit()) \
76 dev_notice(priv->dev, format, ## __VA_ARGS__); \
79 #define ALE_ALL_PORTS 0x7
81 #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
82 #define CPSW_MINOR_VERSION(reg) (reg & 0xff)
83 #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
85 #define CPSW_VERSION_1 0x19010a
86 #define CPSW_VERSION_2 0x19010c
87 #define CPSW_VERSION_3 0x19010f
88 #define CPSW_VERSION_4 0x190112
90 #define HOST_PORT_NUM 0
91 #define SLIVER_SIZE 0x40
93 #define CPSW1_HOST_PORT_OFFSET 0x028
94 #define CPSW1_SLAVE_OFFSET 0x050
95 #define CPSW1_SLAVE_SIZE 0x040
96 #define CPSW1_CPDMA_OFFSET 0x100
97 #define CPSW1_STATERAM_OFFSET 0x200
98 #define CPSW1_HW_STATS 0x400
99 #define CPSW1_CPTS_OFFSET 0x500
100 #define CPSW1_ALE_OFFSET 0x600
101 #define CPSW1_SLIVER_OFFSET 0x700
103 #define CPSW2_HOST_PORT_OFFSET 0x108
104 #define CPSW2_SLAVE_OFFSET 0x200
105 #define CPSW2_SLAVE_SIZE 0x100
106 #define CPSW2_CPDMA_OFFSET 0x800
107 #define CPSW2_HW_STATS 0x900
108 #define CPSW2_STATERAM_OFFSET 0xa00
109 #define CPSW2_CPTS_OFFSET 0xc00
110 #define CPSW2_ALE_OFFSET 0xd00
111 #define CPSW2_SLIVER_OFFSET 0xd80
112 #define CPSW2_BD_OFFSET 0x2000
114 #define CPDMA_RXTHRESH 0x0c0
115 #define CPDMA_RXFREE 0x0e0
116 #define CPDMA_TXHDP 0x00
117 #define CPDMA_RXHDP 0x20
118 #define CPDMA_TXCP 0x40
119 #define CPDMA_RXCP 0x60
121 #define CPSW_POLL_WEIGHT 64
122 #define CPSW_MIN_PACKET_SIZE 60
123 #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
125 #define RX_PRIORITY_MAPPING 0x76543210
126 #define TX_PRIORITY_MAPPING 0x33221100
127 #define CPDMA_TX_PRIORITY_MAP 0x01234567
129 #define CPSW_VLAN_AWARE BIT(1)
130 #define CPSW_ALE_VLAN_AWARE 1
132 #define CPSW_FIFO_NORMAL_MODE (0 << 16)
133 #define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
134 #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
136 #define CPSW_INTPACEEN (0x3f << 16)
137 #define CPSW_INTPRESCALE_MASK (0x7FF << 0)
138 #define CPSW_CMINTMAX_CNT 63
139 #define CPSW_CMINTMIN_CNT 2
140 #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
141 #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
143 #define cpsw_slave_index(cpsw, priv) \
144 ((cpsw->data.dual_emac) ? priv->emac_port : \
145 cpsw->data.active_slave)
147 #define CPSW_MAX_QUEUES 8
148 #define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256
150 static int debug_level;
151 module_param(debug_level, int, 0);
152 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
154 static int ale_ageout = 10;
155 module_param(ale_ageout, int, 0);
156 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
158 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
159 module_param(rx_packet_max, int, 0);
160 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
162 static int descs_pool_size = CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT;
163 module_param(descs_pool_size, int, 0444);
164 MODULE_PARM_DESC(descs_pool_size, "Number of CPDMA CPPI descriptors in pool");
166 struct cpsw_wr_regs {
186 struct cpsw_ss_regs {
203 #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
204 #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
205 #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
206 #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
207 #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
208 #define CPSW1_TS_CTL 0x14 /* Time Sync Control */
209 #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
210 #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
213 #define CPSW2_CONTROL 0x00 /* Control Register */
214 #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
215 #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
216 #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
217 #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
218 #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
219 #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
221 /* CPSW_PORT_V1 and V2 */
222 #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
223 #define SA_HI 0x24 /* CPGMAC_SL Source Address High */
224 #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
226 /* CPSW_PORT_V2 only */
227 #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
228 #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
229 #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
230 #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
231 #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
232 #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
233 #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
234 #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
236 /* Bit definitions for the CPSW2_CONTROL register */
237 #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
238 #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
239 #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
240 #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
241 #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
242 #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
243 #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
244 #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
245 #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
246 #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
247 #define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */
248 #define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */
249 #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
250 #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
251 #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
252 #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
253 #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
255 #define CTRL_V2_TS_BITS \
256 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
257 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)
259 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
260 #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
261 #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
264 #define CTRL_V3_TS_BITS \
265 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
266 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
269 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
270 #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
271 #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
273 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
274 #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
275 #define TS_SEQ_ID_OFFSET_MASK (0x3f)
276 #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
277 #define TS_MSG_TYPE_EN_MASK (0xffff)
279 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
280 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
282 /* Bit definitions for the CPSW1_TS_CTL register */
283 #define CPSW_V1_TS_RX_EN BIT(0)
284 #define CPSW_V1_TS_TX_EN BIT(4)
285 #define CPSW_V1_MSG_TYPE_OFS 16
287 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
288 #define CPSW_V1_SEQ_ID_OFS_SHIFT 16
290 struct cpsw_host_regs {
296 u32 cpdma_tx_pri_map;
297 u32 cpdma_rx_chan_map;
300 struct cpsw_sliver_regs {
313 struct cpsw_hw_stats {
315 u32 rxbroadcastframes;
316 u32 rxmulticastframes;
319 u32 rxaligncodeerrors;
320 u32 rxoversizedframes;
322 u32 rxundersizedframes;
327 u32 txbroadcastframes;
328 u32 txmulticastframes;
330 u32 txdeferredframes;
331 u32 txcollisionframes;
332 u32 txsinglecollframes;
333 u32 txmultcollframes;
334 u32 txexcessivecollisions;
335 u32 txlatecollisions;
337 u32 txcarriersenseerrors;
340 u32 octetframes65t127;
341 u32 octetframes128t255;
342 u32 octetframes256t511;
343 u32 octetframes512t1023;
344 u32 octetframes1024tup;
353 struct cpsw_sliver_regs __iomem *sliver;
356 struct cpsw_slave_data *data;
357 struct phy_device *phy;
358 struct net_device *ndev;
363 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
365 return __raw_readl(slave->regs + offset);
368 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
370 __raw_writel(val, slave->regs + offset);
374 struct cpdma_chan *ch;
380 struct cpsw_platform_data data;
381 struct napi_struct napi_rx;
382 struct napi_struct napi_tx;
383 struct cpsw_ss_regs __iomem *regs;
384 struct cpsw_wr_regs __iomem *wr_regs;
385 u8 __iomem *hw_stats;
386 struct cpsw_host_regs __iomem *host_port_regs;
391 struct cpsw_slave *slaves;
392 struct cpdma_ctlr *dma;
393 struct cpsw_vector txv[CPSW_MAX_QUEUES];
394 struct cpsw_vector rxv[CPSW_MAX_QUEUES];
395 struct cpsw_ale *ale;
397 bool rx_irq_disabled;
398 bool tx_irq_disabled;
399 u32 irqs_table[IRQ_NUM];
401 int rx_ch_num, tx_ch_num;
406 struct net_device *ndev;
409 u8 mac_addr[ETH_ALEN];
413 struct cpsw_common *cpsw;
417 char stat_string[ETH_GSTRING_LEN];
429 #define CPSW_STAT(m) CPSW_STATS, \
430 sizeof(((struct cpsw_hw_stats *)0)->m), \
431 offsetof(struct cpsw_hw_stats, m)
432 #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
433 sizeof(((struct cpdma_chan_stats *)0)->m), \
434 offsetof(struct cpdma_chan_stats, m)
435 #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
436 sizeof(((struct cpdma_chan_stats *)0)->m), \
437 offsetof(struct cpdma_chan_stats, m)
439 static const struct cpsw_stats cpsw_gstrings_stats[] = {
440 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
441 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
442 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
443 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
444 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
445 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
446 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
447 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
448 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
449 { "Rx Fragments", CPSW_STAT(rxfragments) },
450 { "Rx Octets", CPSW_STAT(rxoctets) },
451 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
452 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
453 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
454 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
455 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
456 { "Collisions", CPSW_STAT(txcollisionframes) },
457 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
458 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
459 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
460 { "Late Collisions", CPSW_STAT(txlatecollisions) },
461 { "Tx Underrun", CPSW_STAT(txunderrun) },
462 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
463 { "Tx Octets", CPSW_STAT(txoctets) },
464 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
465 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
466 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
467 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
468 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
469 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
470 { "Net Octets", CPSW_STAT(netoctets) },
471 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
472 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
473 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
476 static const struct cpsw_stats cpsw_gstrings_ch_stats[] = {
477 { "head_enqueue", CPDMA_RX_STAT(head_enqueue) },
478 { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
479 { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
480 { "misqueued", CPDMA_RX_STAT(misqueued) },
481 { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
482 { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
483 { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
484 { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
485 { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
486 { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
487 { "good_dequeue", CPDMA_RX_STAT(good_dequeue) },
488 { "requeue", CPDMA_RX_STAT(requeue) },
489 { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
492 #define CPSW_STATS_COMMON_LEN ARRAY_SIZE(cpsw_gstrings_stats)
493 #define CPSW_STATS_CH_LEN ARRAY_SIZE(cpsw_gstrings_ch_stats)
495 #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
496 #define napi_to_cpsw(napi) container_of(napi, struct cpsw_common, napi)
497 #define for_each_slave(priv, func, arg...) \
499 struct cpsw_slave *slave; \
500 struct cpsw_common *cpsw = (priv)->cpsw; \
502 if (cpsw->data.dual_emac) \
503 (func)((cpsw)->slaves + priv->emac_port, ##arg);\
505 for (n = cpsw->data.slaves, \
506 slave = cpsw->slaves; \
508 (func)(slave++, ##arg); \
511 #define cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb) \
513 if (!cpsw->data.dual_emac) \
515 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
516 ndev = cpsw->slaves[0].ndev; \
518 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
519 ndev = cpsw->slaves[1].ndev; \
523 #define cpsw_add_mcast(cpsw, priv, addr) \
525 if (cpsw->data.dual_emac) { \
526 struct cpsw_slave *slave = cpsw->slaves + \
528 int slave_port = cpsw_get_slave_port( \
530 cpsw_ale_add_mcast(cpsw->ale, addr, \
531 1 << slave_port | ALE_PORT_HOST, \
532 ALE_VLAN, slave->port_vlan, 0); \
534 cpsw_ale_add_mcast(cpsw->ale, addr, \
540 static inline int cpsw_get_slave_port(u32 slave_num)
542 return slave_num + 1;
545 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
547 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
548 struct cpsw_ale *ale = cpsw->ale;
551 if (cpsw->data.dual_emac) {
554 /* Enabling promiscuous mode for one interface will be
555 * common for both the interface as the interface shares
556 * the same hardware resource.
558 for (i = 0; i < cpsw->data.slaves; i++)
559 if (cpsw->slaves[i].ndev->flags & IFF_PROMISC)
562 if (!enable && flag) {
564 dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
569 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
571 dev_dbg(&ndev->dev, "promiscuity enabled\n");
574 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
575 dev_dbg(&ndev->dev, "promiscuity disabled\n");
579 unsigned long timeout = jiffies + HZ;
581 /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
582 for (i = 0; i <= cpsw->data.slaves; i++) {
583 cpsw_ale_control_set(ale, i,
584 ALE_PORT_NOLEARN, 1);
585 cpsw_ale_control_set(ale, i,
586 ALE_PORT_NO_SA_UPDATE, 1);
589 /* Clear All Untouched entries */
590 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
593 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
595 } while (time_after(timeout, jiffies));
596 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
598 /* Clear all mcast from ALE */
599 cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
601 /* Flood All Unicast Packets to Host port */
602 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
603 dev_dbg(&ndev->dev, "promiscuity enabled\n");
605 /* Don't Flood All Unicast Packets to Host port */
606 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
608 /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
609 for (i = 0; i <= cpsw->data.slaves; i++) {
610 cpsw_ale_control_set(ale, i,
611 ALE_PORT_NOLEARN, 0);
612 cpsw_ale_control_set(ale, i,
613 ALE_PORT_NO_SA_UPDATE, 0);
615 dev_dbg(&ndev->dev, "promiscuity disabled\n");
620 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
622 struct cpsw_priv *priv = netdev_priv(ndev);
623 struct cpsw_common *cpsw = priv->cpsw;
626 if (cpsw->data.dual_emac)
627 vid = cpsw->slaves[priv->emac_port].port_vlan;
629 vid = cpsw->data.default_vlan;
631 if (ndev->flags & IFF_PROMISC) {
632 /* Enable promiscuous mode */
633 cpsw_set_promiscious(ndev, true);
634 cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI);
637 /* Disable promiscuous mode */
638 cpsw_set_promiscious(ndev, false);
641 /* Restore allmulti on vlans if necessary */
642 cpsw_ale_set_allmulti(cpsw->ale, priv->ndev->flags & IFF_ALLMULTI);
644 /* Clear all mcast from ALE */
645 cpsw_ale_flush_multicast(cpsw->ale, ALE_ALL_PORTS, vid);
647 if (!netdev_mc_empty(ndev)) {
648 struct netdev_hw_addr *ha;
650 /* program multicast address list into ALE register */
651 netdev_for_each_mc_addr(ha, ndev) {
652 cpsw_add_mcast(cpsw, priv, (u8 *)ha->addr);
657 static void cpsw_intr_enable(struct cpsw_common *cpsw)
659 __raw_writel(0xFF, &cpsw->wr_regs->tx_en);
660 __raw_writel(0xFF, &cpsw->wr_regs->rx_en);
662 cpdma_ctlr_int_ctrl(cpsw->dma, true);
666 static void cpsw_intr_disable(struct cpsw_common *cpsw)
668 __raw_writel(0, &cpsw->wr_regs->tx_en);
669 __raw_writel(0, &cpsw->wr_regs->rx_en);
671 cpdma_ctlr_int_ctrl(cpsw->dma, false);
675 static void cpsw_tx_handler(void *token, int len, int status)
677 struct netdev_queue *txq;
678 struct sk_buff *skb = token;
679 struct net_device *ndev = skb->dev;
680 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
682 /* Check whether the queue is stopped due to stalled tx dma, if the
683 * queue is stopped then start the queue as we have free desc for tx
685 txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
686 if (unlikely(netif_tx_queue_stopped(txq)))
687 netif_tx_wake_queue(txq);
689 cpts_tx_timestamp(cpsw->cpts, skb);
690 ndev->stats.tx_packets++;
691 ndev->stats.tx_bytes += len;
692 dev_kfree_skb_any(skb);
695 static void cpsw_rx_handler(void *token, int len, int status)
697 struct cpdma_chan *ch;
698 struct sk_buff *skb = token;
699 struct sk_buff *new_skb;
700 struct net_device *ndev = skb->dev;
702 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
704 cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb);
706 if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
707 bool ndev_status = false;
708 struct cpsw_slave *slave = cpsw->slaves;
711 if (cpsw->data.dual_emac) {
712 /* In dual emac mode check for all interfaces */
713 for (n = cpsw->data.slaves; n; n--, slave++)
714 if (netif_running(slave->ndev))
718 if (ndev_status && (status >= 0)) {
719 /* The packet received is for the interface which
720 * is already down and the other interface is up
721 * and running, instead of freeing which results
722 * in reducing of the number of rx descriptor in
723 * DMA engine, requeue skb back to cpdma.
729 /* the interface is going down, skbs are purged */
730 dev_kfree_skb_any(skb);
734 new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max);
736 skb_copy_queue_mapping(new_skb, skb);
738 cpts_rx_timestamp(cpsw->cpts, skb);
739 skb->protocol = eth_type_trans(skb, ndev);
740 netif_receive_skb(skb);
741 ndev->stats.rx_bytes += len;
742 ndev->stats.rx_packets++;
743 kmemleak_not_leak(new_skb);
745 ndev->stats.rx_dropped++;
750 if (netif_dormant(ndev)) {
751 dev_kfree_skb_any(new_skb);
755 ch = cpsw->rxv[skb_get_queue_mapping(new_skb)].ch;
756 ret = cpdma_chan_submit(ch, new_skb, new_skb->data,
757 skb_tailroom(new_skb), 0);
758 if (WARN_ON(ret < 0))
759 dev_kfree_skb_any(new_skb);
762 static void cpsw_split_res(struct net_device *ndev)
764 struct cpsw_priv *priv = netdev_priv(ndev);
765 u32 consumed_rate = 0, bigest_rate = 0;
766 struct cpsw_common *cpsw = priv->cpsw;
767 struct cpsw_vector *txv = cpsw->txv;
768 int i, ch_weight, rlim_ch_num = 0;
769 int budget, bigest_rate_ch = 0;
770 u32 ch_rate, max_rate;
773 for (i = 0; i < cpsw->tx_ch_num; i++) {
774 ch_rate = cpdma_chan_get_rate(txv[i].ch);
779 consumed_rate += ch_rate;
782 if (cpsw->tx_ch_num == rlim_ch_num) {
783 max_rate = consumed_rate;
784 } else if (!rlim_ch_num) {
785 ch_budget = CPSW_POLL_WEIGHT / cpsw->tx_ch_num;
787 max_rate = consumed_rate;
789 max_rate = cpsw->speed * 1000;
791 /* if max_rate is less then expected due to reduced link speed,
792 * split proportionally according next potential max speed
794 if (max_rate < consumed_rate)
797 if (max_rate < consumed_rate)
800 ch_budget = (consumed_rate * CPSW_POLL_WEIGHT) / max_rate;
801 ch_budget = (CPSW_POLL_WEIGHT - ch_budget) /
802 (cpsw->tx_ch_num - rlim_ch_num);
803 bigest_rate = (max_rate - consumed_rate) /
804 (cpsw->tx_ch_num - rlim_ch_num);
807 /* split tx weight/budget */
808 budget = CPSW_POLL_WEIGHT;
809 for (i = 0; i < cpsw->tx_ch_num; i++) {
810 ch_rate = cpdma_chan_get_rate(txv[i].ch);
812 txv[i].budget = (ch_rate * CPSW_POLL_WEIGHT) / max_rate;
815 if (ch_rate > bigest_rate) {
817 bigest_rate = ch_rate;
820 ch_weight = (ch_rate * 100) / max_rate;
823 cpdma_chan_set_weight(cpsw->txv[i].ch, ch_weight);
825 txv[i].budget = ch_budget;
828 cpdma_chan_set_weight(cpsw->txv[i].ch, 0);
831 budget -= txv[i].budget;
835 txv[bigest_rate_ch].budget += budget;
837 /* split rx budget */
838 budget = CPSW_POLL_WEIGHT;
839 ch_budget = budget / cpsw->rx_ch_num;
840 for (i = 0; i < cpsw->rx_ch_num; i++) {
841 cpsw->rxv[i].budget = ch_budget;
846 cpsw->rxv[0].budget += budget;
849 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
851 struct cpsw_common *cpsw = dev_id;
853 writel(0, &cpsw->wr_regs->tx_en);
854 cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX);
856 if (cpsw->quirk_irq) {
857 disable_irq_nosync(cpsw->irqs_table[1]);
858 cpsw->tx_irq_disabled = true;
861 napi_schedule(&cpsw->napi_tx);
865 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
867 struct cpsw_common *cpsw = dev_id;
869 cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX);
870 writel(0, &cpsw->wr_regs->rx_en);
872 if (cpsw->quirk_irq) {
873 disable_irq_nosync(cpsw->irqs_table[0]);
874 cpsw->rx_irq_disabled = true;
877 napi_schedule(&cpsw->napi_rx);
881 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
884 int num_tx, cur_budget, ch;
885 struct cpsw_common *cpsw = napi_to_cpsw(napi_tx);
886 struct cpsw_vector *txv;
888 /* process every unprocessed channel */
889 ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
890 for (ch = 0, num_tx = 0; ch_map; ch_map >>= 1, ch++) {
891 if (!(ch_map & 0x01))
894 txv = &cpsw->txv[ch];
895 if (unlikely(txv->budget > budget - num_tx))
896 cur_budget = budget - num_tx;
898 cur_budget = txv->budget;
900 num_tx += cpdma_chan_process(txv->ch, cur_budget);
901 if (num_tx >= budget)
905 if (num_tx < budget) {
906 napi_complete(napi_tx);
907 writel(0xff, &cpsw->wr_regs->tx_en);
908 if (cpsw->quirk_irq && cpsw->tx_irq_disabled) {
909 cpsw->tx_irq_disabled = false;
910 enable_irq(cpsw->irqs_table[1]);
917 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
920 int num_rx, cur_budget, ch;
921 struct cpsw_common *cpsw = napi_to_cpsw(napi_rx);
922 struct cpsw_vector *rxv;
924 /* process every unprocessed channel */
925 ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
926 for (ch = 0, num_rx = 0; ch_map; ch_map >>= 1, ch++) {
927 if (!(ch_map & 0x01))
930 rxv = &cpsw->rxv[ch];
931 if (unlikely(rxv->budget > budget - num_rx))
932 cur_budget = budget - num_rx;
934 cur_budget = rxv->budget;
936 num_rx += cpdma_chan_process(rxv->ch, cur_budget);
937 if (num_rx >= budget)
941 if (num_rx < budget) {
942 napi_complete(napi_rx);
943 writel(0xff, &cpsw->wr_regs->rx_en);
944 if (cpsw->quirk_irq && cpsw->rx_irq_disabled) {
945 cpsw->rx_irq_disabled = false;
946 enable_irq(cpsw->irqs_table[0]);
953 static inline void soft_reset(const char *module, void __iomem *reg)
955 unsigned long timeout = jiffies + HZ;
957 __raw_writel(1, reg);
960 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
962 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
965 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
966 ((mac)[2] << 16) | ((mac)[3] << 24))
967 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
969 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
970 struct cpsw_priv *priv)
972 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
973 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
976 static void _cpsw_adjust_link(struct cpsw_slave *slave,
977 struct cpsw_priv *priv, bool *link)
979 struct phy_device *phy = slave->phy;
982 struct cpsw_common *cpsw = priv->cpsw;
987 slave_port = cpsw_get_slave_port(slave->slave_num);
990 mac_control = cpsw->data.mac_control;
992 /* enable forwarding */
993 cpsw_ale_control_set(cpsw->ale, slave_port,
994 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
996 if (phy->speed == 1000)
997 mac_control |= BIT(7); /* GIGABITEN */
999 mac_control |= BIT(0); /* FULLDUPLEXEN */
1001 /* set speed_in input in case RMII mode is used in 100Mbps */
1002 if (phy->speed == 100)
1003 mac_control |= BIT(15);
1004 else if (phy->speed == 10)
1005 mac_control |= BIT(18); /* In Band mode */
1008 mac_control |= BIT(3);
1011 mac_control |= BIT(4);
1016 /* disable forwarding */
1017 cpsw_ale_control_set(cpsw->ale, slave_port,
1018 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1021 if (mac_control != slave->mac_control) {
1022 phy_print_status(phy);
1023 __raw_writel(mac_control, &slave->sliver->mac_control);
1026 slave->mac_control = mac_control;
1029 static int cpsw_get_common_speed(struct cpsw_common *cpsw)
1033 for (i = 0, speed = 0; i < cpsw->data.slaves; i++)
1034 if (cpsw->slaves[i].phy && cpsw->slaves[i].phy->link)
1035 speed += cpsw->slaves[i].phy->speed;
1040 static int cpsw_need_resplit(struct cpsw_common *cpsw)
1045 /* re-split resources only in case speed was changed */
1046 speed = cpsw_get_common_speed(cpsw);
1047 if (speed == cpsw->speed || !speed)
1050 cpsw->speed = speed;
1052 for (i = 0, rlim_ch_num = 0; i < cpsw->tx_ch_num; i++) {
1053 ch_rate = cpdma_chan_get_rate(cpsw->txv[i].ch);
1060 /* cases not dependent on speed */
1061 if (!rlim_ch_num || rlim_ch_num == cpsw->tx_ch_num)
1067 static void cpsw_adjust_link(struct net_device *ndev)
1069 struct cpsw_priv *priv = netdev_priv(ndev);
1070 struct cpsw_common *cpsw = priv->cpsw;
1073 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1076 if (cpsw_need_resplit(cpsw))
1077 cpsw_split_res(ndev);
1079 netif_carrier_on(ndev);
1080 if (netif_running(ndev))
1081 netif_tx_wake_all_queues(ndev);
1083 netif_carrier_off(ndev);
1084 netif_tx_stop_all_queues(ndev);
1088 static int cpsw_get_coalesce(struct net_device *ndev,
1089 struct ethtool_coalesce *coal)
1091 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1093 coal->rx_coalesce_usecs = cpsw->coal_intvl;
1097 static int cpsw_set_coalesce(struct net_device *ndev,
1098 struct ethtool_coalesce *coal)
1100 struct cpsw_priv *priv = netdev_priv(ndev);
1102 u32 num_interrupts = 0;
1106 struct cpsw_common *cpsw = priv->cpsw;
1108 coal_intvl = coal->rx_coalesce_usecs;
1110 int_ctrl = readl(&cpsw->wr_regs->int_control);
1111 prescale = cpsw->bus_freq_mhz * 4;
1113 if (!coal->rx_coalesce_usecs) {
1114 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
1118 if (coal_intvl < CPSW_CMINTMIN_INTVL)
1119 coal_intvl = CPSW_CMINTMIN_INTVL;
1121 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
1122 /* Interrupt pacer works with 4us Pulse, we can
1123 * throttle further by dilating the 4us pulse.
1125 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
1127 if (addnl_dvdr > 1) {
1128 prescale *= addnl_dvdr;
1129 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
1130 coal_intvl = (CPSW_CMINTMAX_INTVL
1134 coal_intvl = CPSW_CMINTMAX_INTVL;
1138 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
1139 writel(num_interrupts, &cpsw->wr_regs->rx_imax);
1140 writel(num_interrupts, &cpsw->wr_regs->tx_imax);
1142 int_ctrl |= CPSW_INTPACEEN;
1143 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
1144 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
1147 writel(int_ctrl, &cpsw->wr_regs->int_control);
1149 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
1150 cpsw->coal_intvl = coal_intvl;
1155 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
1157 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1161 return (CPSW_STATS_COMMON_LEN +
1162 (cpsw->rx_ch_num + cpsw->tx_ch_num) *
1169 static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir)
1175 ch_stats_len = CPSW_STATS_CH_LEN * ch_num;
1176 for (i = 0; i < ch_stats_len; i++) {
1177 line = i % CPSW_STATS_CH_LEN;
1178 snprintf(*p, ETH_GSTRING_LEN,
1179 "%s DMA chan %d: %s", rx_dir ? "Rx" : "Tx",
1180 i / CPSW_STATS_CH_LEN,
1181 cpsw_gstrings_ch_stats[line].stat_string);
1182 *p += ETH_GSTRING_LEN;
1186 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1188 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1192 switch (stringset) {
1194 for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) {
1195 memcpy(p, cpsw_gstrings_stats[i].stat_string,
1197 p += ETH_GSTRING_LEN;
1200 cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1);
1201 cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0);
1206 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1207 struct ethtool_stats *stats, u64 *data)
1210 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1211 struct cpdma_chan_stats ch_stats;
1214 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1215 for (l = 0; l < CPSW_STATS_COMMON_LEN; l++)
1216 data[l] = readl(cpsw->hw_stats +
1217 cpsw_gstrings_stats[l].stat_offset);
1219 for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1220 cpdma_chan_get_stats(cpsw->rxv[ch].ch, &ch_stats);
1221 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1222 p = (u8 *)&ch_stats +
1223 cpsw_gstrings_ch_stats[i].stat_offset;
1224 data[l] = *(u32 *)p;
1228 for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1229 cpdma_chan_get_stats(cpsw->txv[ch].ch, &ch_stats);
1230 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1231 p = (u8 *)&ch_stats +
1232 cpsw_gstrings_ch_stats[i].stat_offset;
1233 data[l] = *(u32 *)p;
1238 static int cpsw_common_res_usage_state(struct cpsw_common *cpsw)
1241 u32 usage_count = 0;
1243 for (i = 0; i < cpsw->data.slaves; i++)
1244 if (cpsw->slaves[i].open_stat)
1250 static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv,
1251 struct sk_buff *skb,
1252 struct cpdma_chan *txch)
1254 struct cpsw_common *cpsw = priv->cpsw;
1256 return cpdma_chan_submit(txch, skb, skb->data, skb->len,
1257 priv->emac_port + cpsw->data.dual_emac);
1260 static inline void cpsw_add_dual_emac_def_ale_entries(
1261 struct cpsw_priv *priv, struct cpsw_slave *slave,
1264 struct cpsw_common *cpsw = priv->cpsw;
1265 u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
1267 if (cpsw->version == CPSW_VERSION_1)
1268 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1270 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1271 cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask,
1272 port_mask, port_mask, 0);
1273 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1274 port_mask, ALE_VLAN, slave->port_vlan, 0);
1275 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1276 HOST_PORT_NUM, ALE_VLAN |
1277 ALE_SECURE, slave->port_vlan);
1280 static void soft_reset_slave(struct cpsw_slave *slave)
1284 snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1285 soft_reset(name, &slave->sliver->soft_reset);
1288 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1291 struct cpsw_common *cpsw = priv->cpsw;
1293 soft_reset_slave(slave);
1295 /* setup priority mapping */
1296 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1298 switch (cpsw->version) {
1299 case CPSW_VERSION_1:
1300 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1302 case CPSW_VERSION_2:
1303 case CPSW_VERSION_3:
1304 case CPSW_VERSION_4:
1305 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1309 /* setup max packet size, and mac address */
1310 __raw_writel(cpsw->rx_packet_max, &slave->sliver->rx_maxlen);
1311 cpsw_set_slave_mac(slave, priv);
1313 slave->mac_control = 0; /* no link yet */
1315 slave_port = cpsw_get_slave_port(slave->slave_num);
1317 if (cpsw->data.dual_emac)
1318 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1320 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1321 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1323 if (slave->data->phy_node) {
1324 slave->phy = of_phy_connect(priv->ndev, slave->data->phy_node,
1325 &cpsw_adjust_link, 0, slave->data->phy_if);
1327 dev_err(priv->dev, "phy \"%s\" not found on slave %d\n",
1328 slave->data->phy_node->full_name,
1333 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1334 &cpsw_adjust_link, slave->data->phy_if);
1335 if (IS_ERR(slave->phy)) {
1337 "phy \"%s\" not found on slave %d, err %ld\n",
1338 slave->data->phy_id, slave->slave_num,
1339 PTR_ERR(slave->phy));
1345 phy_attached_info(slave->phy);
1347 phy_start(slave->phy);
1349 /* Configure GMII_SEL register */
1350 cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num);
1353 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1355 struct cpsw_common *cpsw = priv->cpsw;
1356 const int vlan = cpsw->data.default_vlan;
1359 int unreg_mcast_mask;
1361 reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1364 writel(vlan, &cpsw->host_port_regs->port_vlan);
1366 for (i = 0; i < cpsw->data.slaves; i++)
1367 slave_write(cpsw->slaves + i, vlan, reg);
1369 if (priv->ndev->flags & IFF_ALLMULTI)
1370 unreg_mcast_mask = ALE_ALL_PORTS;
1372 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1374 cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS,
1375 ALE_ALL_PORTS, ALE_ALL_PORTS,
1379 static void cpsw_init_host_port(struct cpsw_priv *priv)
1383 struct cpsw_common *cpsw = priv->cpsw;
1385 /* soft reset the controller and initialize ale */
1386 soft_reset("cpsw", &cpsw->regs->soft_reset);
1387 cpsw_ale_start(cpsw->ale);
1389 /* switch to vlan unaware mode */
1390 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
1391 CPSW_ALE_VLAN_AWARE);
1392 control_reg = readl(&cpsw->regs->control);
1393 control_reg |= CPSW_VLAN_AWARE;
1394 writel(control_reg, &cpsw->regs->control);
1395 fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1396 CPSW_FIFO_NORMAL_MODE;
1397 writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl);
1399 /* setup host port priority mapping */
1400 __raw_writel(CPDMA_TX_PRIORITY_MAP,
1401 &cpsw->host_port_regs->cpdma_tx_pri_map);
1402 __raw_writel(0, &cpsw->host_port_regs->cpdma_rx_chan_map);
1404 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM,
1405 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1407 if (!cpsw->data.dual_emac) {
1408 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1410 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1411 ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
1415 static int cpsw_fill_rx_channels(struct cpsw_priv *priv)
1417 struct cpsw_common *cpsw = priv->cpsw;
1418 struct sk_buff *skb;
1422 for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1423 ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxv[ch].ch);
1424 for (i = 0; i < ch_buf_num; i++) {
1425 skb = __netdev_alloc_skb_ip_align(priv->ndev,
1426 cpsw->rx_packet_max,
1429 cpsw_err(priv, ifup, "cannot allocate skb\n");
1433 skb_set_queue_mapping(skb, ch);
1434 ret = cpdma_chan_submit(cpsw->rxv[ch].ch, skb,
1435 skb->data, skb_tailroom(skb),
1438 cpsw_err(priv, ifup,
1439 "cannot submit skb to channel %d rx, error %d\n",
1444 kmemleak_not_leak(skb);
1447 cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n",
1454 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw)
1458 slave_port = cpsw_get_slave_port(slave->slave_num);
1462 phy_stop(slave->phy);
1463 phy_disconnect(slave->phy);
1465 cpsw_ale_control_set(cpsw->ale, slave_port,
1466 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1467 soft_reset_slave(slave);
1470 static int cpsw_ndo_open(struct net_device *ndev)
1472 struct cpsw_priv *priv = netdev_priv(ndev);
1473 struct cpsw_common *cpsw = priv->cpsw;
1477 ret = pm_runtime_get_sync(cpsw->dev);
1479 pm_runtime_put_noidle(cpsw->dev);
1483 if (!cpsw_common_res_usage_state(cpsw))
1484 cpsw_intr_disable(cpsw);
1485 netif_carrier_off(ndev);
1487 /* Notify the stack of the actual queue counts. */
1488 ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num);
1490 dev_err(priv->dev, "cannot set real number of tx queues\n");
1494 ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num);
1496 dev_err(priv->dev, "cannot set real number of rx queues\n");
1500 reg = cpsw->version;
1502 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1503 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1504 CPSW_RTL_VERSION(reg));
1506 /* initialize host and slave ports */
1507 if (!cpsw_common_res_usage_state(cpsw))
1508 cpsw_init_host_port(priv);
1509 for_each_slave(priv, cpsw_slave_open, priv);
1511 /* Add default VLAN */
1512 if (!cpsw->data.dual_emac)
1513 cpsw_add_default_vlan(priv);
1515 cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan,
1516 ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
1518 if (!cpsw_common_res_usage_state(cpsw)) {
1519 /* disable priority elevation */
1520 __raw_writel(0, &cpsw->regs->ptype);
1522 /* enable statistics collection only on all ports */
1523 __raw_writel(0x7, &cpsw->regs->stat_port_en);
1525 /* Enable internal fifo flow control */
1526 writel(0x7, &cpsw->regs->flow_control);
1528 napi_enable(&cpsw->napi_rx);
1529 napi_enable(&cpsw->napi_tx);
1531 if (cpsw->tx_irq_disabled) {
1532 cpsw->tx_irq_disabled = false;
1533 enable_irq(cpsw->irqs_table[1]);
1536 if (cpsw->rx_irq_disabled) {
1537 cpsw->rx_irq_disabled = false;
1538 enable_irq(cpsw->irqs_table[0]);
1541 ret = cpsw_fill_rx_channels(priv);
1545 if (cpts_register(cpsw->cpts))
1546 dev_err(priv->dev, "error registering cpts device\n");
1550 /* Enable Interrupt pacing if configured */
1551 if (cpsw->coal_intvl != 0) {
1552 struct ethtool_coalesce coal;
1554 coal.rx_coalesce_usecs = cpsw->coal_intvl;
1555 cpsw_set_coalesce(ndev, &coal);
1558 cpdma_ctlr_start(cpsw->dma);
1559 cpsw_intr_enable(cpsw);
1561 if (cpsw->data.dual_emac)
1562 cpsw->slaves[priv->emac_port].open_stat = true;
1567 cpdma_ctlr_stop(cpsw->dma);
1568 for_each_slave(priv, cpsw_slave_stop, cpsw);
1569 pm_runtime_put_sync(cpsw->dev);
1570 netif_carrier_off(priv->ndev);
1574 static int cpsw_ndo_stop(struct net_device *ndev)
1576 struct cpsw_priv *priv = netdev_priv(ndev);
1577 struct cpsw_common *cpsw = priv->cpsw;
1579 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1580 netif_tx_stop_all_queues(priv->ndev);
1581 netif_carrier_off(priv->ndev);
1583 if (cpsw_common_res_usage_state(cpsw) <= 1) {
1584 napi_disable(&cpsw->napi_rx);
1585 napi_disable(&cpsw->napi_tx);
1586 cpts_unregister(cpsw->cpts);
1587 cpsw_intr_disable(cpsw);
1588 cpdma_ctlr_stop(cpsw->dma);
1589 cpsw_ale_stop(cpsw->ale);
1591 for_each_slave(priv, cpsw_slave_stop, cpsw);
1593 if (cpsw_need_resplit(cpsw))
1594 cpsw_split_res(ndev);
1596 pm_runtime_put_sync(cpsw->dev);
1597 if (cpsw->data.dual_emac)
1598 cpsw->slaves[priv->emac_port].open_stat = false;
1602 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1603 struct net_device *ndev)
1605 struct cpsw_priv *priv = netdev_priv(ndev);
1606 struct cpsw_common *cpsw = priv->cpsw;
1607 struct netdev_queue *txq;
1608 struct cpdma_chan *txch;
1611 netif_trans_update(ndev);
1613 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1614 cpsw_err(priv, tx_err, "packet pad failed\n");
1615 ndev->stats.tx_dropped++;
1616 return NETDEV_TX_OK;
1619 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1620 cpts_is_tx_enabled(cpsw->cpts))
1621 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1623 skb_tx_timestamp(skb);
1625 q_idx = skb_get_queue_mapping(skb);
1626 if (q_idx >= cpsw->tx_ch_num)
1627 q_idx = q_idx % cpsw->tx_ch_num;
1629 txch = cpsw->txv[q_idx].ch;
1630 ret = cpsw_tx_packet_submit(priv, skb, txch);
1631 if (unlikely(ret != 0)) {
1632 cpsw_err(priv, tx_err, "desc submit failed\n");
1636 /* If there is no more tx desc left free then we need to
1637 * tell the kernel to stop sending us tx frames.
1639 if (unlikely(!cpdma_check_free_tx_desc(txch))) {
1640 txq = netdev_get_tx_queue(ndev, q_idx);
1641 netif_tx_stop_queue(txq);
1644 return NETDEV_TX_OK;
1646 ndev->stats.tx_dropped++;
1647 txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
1648 netif_tx_stop_queue(txq);
1649 return NETDEV_TX_BUSY;
1652 #if IS_ENABLED(CONFIG_TI_CPTS)
1654 static void cpsw_hwtstamp_v1(struct cpsw_common *cpsw)
1656 struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave];
1659 if (!cpts_is_tx_enabled(cpsw->cpts) &&
1660 !cpts_is_rx_enabled(cpsw->cpts)) {
1661 slave_write(slave, 0, CPSW1_TS_CTL);
1665 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1666 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1668 if (cpts_is_tx_enabled(cpsw->cpts))
1669 ts_en |= CPSW_V1_TS_TX_EN;
1671 if (cpts_is_rx_enabled(cpsw->cpts))
1672 ts_en |= CPSW_V1_TS_RX_EN;
1674 slave_write(slave, ts_en, CPSW1_TS_CTL);
1675 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1678 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1680 struct cpsw_slave *slave;
1681 struct cpsw_common *cpsw = priv->cpsw;
1684 slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1686 ctrl = slave_read(slave, CPSW2_CONTROL);
1687 switch (cpsw->version) {
1688 case CPSW_VERSION_2:
1689 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1691 if (cpts_is_tx_enabled(cpsw->cpts))
1692 ctrl |= CTRL_V2_TX_TS_BITS;
1694 if (cpts_is_rx_enabled(cpsw->cpts))
1695 ctrl |= CTRL_V2_RX_TS_BITS;
1697 case CPSW_VERSION_3:
1699 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1701 if (cpts_is_tx_enabled(cpsw->cpts))
1702 ctrl |= CTRL_V3_TX_TS_BITS;
1704 if (cpts_is_rx_enabled(cpsw->cpts))
1705 ctrl |= CTRL_V3_RX_TS_BITS;
1709 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1711 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1712 slave_write(slave, ctrl, CPSW2_CONTROL);
1713 __raw_writel(ETH_P_1588, &cpsw->regs->ts_ltype);
1716 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1718 struct cpsw_priv *priv = netdev_priv(dev);
1719 struct hwtstamp_config cfg;
1720 struct cpsw_common *cpsw = priv->cpsw;
1721 struct cpts *cpts = cpsw->cpts;
1723 if (cpsw->version != CPSW_VERSION_1 &&
1724 cpsw->version != CPSW_VERSION_2 &&
1725 cpsw->version != CPSW_VERSION_3)
1728 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1731 /* reserved for future extensions */
1735 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1738 switch (cfg.rx_filter) {
1739 case HWTSTAMP_FILTER_NONE:
1740 cpts_rx_enable(cpts, 0);
1742 case HWTSTAMP_FILTER_ALL:
1743 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1744 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1745 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1747 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1748 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1749 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1750 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1751 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1752 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1753 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1754 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1755 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1756 cpts_rx_enable(cpts, 1);
1757 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1763 cpts_tx_enable(cpts, cfg.tx_type == HWTSTAMP_TX_ON);
1765 switch (cpsw->version) {
1766 case CPSW_VERSION_1:
1767 cpsw_hwtstamp_v1(cpsw);
1769 case CPSW_VERSION_2:
1770 case CPSW_VERSION_3:
1771 cpsw_hwtstamp_v2(priv);
1777 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1780 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1782 struct cpsw_common *cpsw = ndev_to_cpsw(dev);
1783 struct cpts *cpts = cpsw->cpts;
1784 struct hwtstamp_config cfg;
1786 if (cpsw->version != CPSW_VERSION_1 &&
1787 cpsw->version != CPSW_VERSION_2 &&
1788 cpsw->version != CPSW_VERSION_3)
1792 cfg.tx_type = cpts_is_tx_enabled(cpts) ?
1793 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1794 cfg.rx_filter = (cpts_is_rx_enabled(cpts) ?
1795 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1797 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1800 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1805 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1809 #endif /*CONFIG_TI_CPTS*/
1811 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1813 struct cpsw_priv *priv = netdev_priv(dev);
1814 struct cpsw_common *cpsw = priv->cpsw;
1815 int slave_no = cpsw_slave_index(cpsw, priv);
1817 if (!netif_running(dev))
1822 return cpsw_hwtstamp_set(dev, req);
1824 return cpsw_hwtstamp_get(dev, req);
1827 if (!cpsw->slaves[slave_no].phy)
1829 return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd);
1832 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1834 struct cpsw_priv *priv = netdev_priv(ndev);
1835 struct cpsw_common *cpsw = priv->cpsw;
1838 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1839 ndev->stats.tx_errors++;
1840 cpsw_intr_disable(cpsw);
1841 for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1842 cpdma_chan_stop(cpsw->txv[ch].ch);
1843 cpdma_chan_start(cpsw->txv[ch].ch);
1846 cpsw_intr_enable(cpsw);
1849 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1851 struct cpsw_priv *priv = netdev_priv(ndev);
1852 struct sockaddr *addr = (struct sockaddr *)p;
1853 struct cpsw_common *cpsw = priv->cpsw;
1858 if (!is_valid_ether_addr(addr->sa_data))
1859 return -EADDRNOTAVAIL;
1861 ret = pm_runtime_get_sync(cpsw->dev);
1863 pm_runtime_put_noidle(cpsw->dev);
1867 if (cpsw->data.dual_emac) {
1868 vid = cpsw->slaves[priv->emac_port].port_vlan;
1872 cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1874 cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM,
1877 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1878 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1879 for_each_slave(priv, cpsw_set_slave_mac, priv);
1881 pm_runtime_put(cpsw->dev);
1886 #ifdef CONFIG_NET_POLL_CONTROLLER
1887 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1889 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1891 cpsw_intr_disable(cpsw);
1892 cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw);
1893 cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw);
1894 cpsw_intr_enable(cpsw);
1898 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1902 int unreg_mcast_mask = 0;
1904 struct cpsw_common *cpsw = priv->cpsw;
1906 if (cpsw->data.dual_emac) {
1907 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1909 if (priv->ndev->flags & IFF_ALLMULTI)
1910 unreg_mcast_mask = port_mask;
1912 port_mask = ALE_ALL_PORTS;
1914 if (priv->ndev->flags & IFF_ALLMULTI)
1915 unreg_mcast_mask = ALE_ALL_PORTS;
1917 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1920 ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask,
1925 ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1926 HOST_PORT_NUM, ALE_VLAN, vid);
1930 ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1931 port_mask, ALE_VLAN, vid, 0);
1933 goto clean_vlan_ucast;
1937 cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
1938 HOST_PORT_NUM, ALE_VLAN, vid);
1940 cpsw_ale_del_vlan(cpsw->ale, vid, 0);
1944 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1945 __be16 proto, u16 vid)
1947 struct cpsw_priv *priv = netdev_priv(ndev);
1948 struct cpsw_common *cpsw = priv->cpsw;
1951 if (vid == cpsw->data.default_vlan)
1954 ret = pm_runtime_get_sync(cpsw->dev);
1956 pm_runtime_put_noidle(cpsw->dev);
1960 if (cpsw->data.dual_emac) {
1961 /* In dual EMAC, reserved VLAN id should not be used for
1962 * creating VLAN interfaces as this can break the dual
1963 * EMAC port separation
1967 for (i = 0; i < cpsw->data.slaves; i++) {
1968 if (vid == cpsw->slaves[i].port_vlan)
1973 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1974 ret = cpsw_add_vlan_ale_entry(priv, vid);
1976 pm_runtime_put(cpsw->dev);
1980 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1981 __be16 proto, u16 vid)
1983 struct cpsw_priv *priv = netdev_priv(ndev);
1984 struct cpsw_common *cpsw = priv->cpsw;
1987 if (vid == cpsw->data.default_vlan)
1990 ret = pm_runtime_get_sync(cpsw->dev);
1992 pm_runtime_put_noidle(cpsw->dev);
1996 if (cpsw->data.dual_emac) {
1999 for (i = 0; i < cpsw->data.slaves; i++) {
2000 if (vid == cpsw->slaves[i].port_vlan)
2005 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
2006 ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0);
2010 ret = cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
2011 HOST_PORT_NUM, ALE_VLAN, vid);
2015 ret = cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast,
2017 pm_runtime_put(cpsw->dev);
2021 static int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate)
2023 struct cpsw_priv *priv = netdev_priv(ndev);
2024 struct cpsw_common *cpsw = priv->cpsw;
2025 struct cpsw_slave *slave;
2030 ch_rate = netdev_get_tx_queue(ndev, queue)->tx_maxrate;
2031 if (ch_rate == rate)
2034 ch_rate = rate * 1000;
2035 min_rate = cpdma_chan_get_min_rate(cpsw->dma);
2036 if ((ch_rate < min_rate && ch_rate)) {
2037 dev_err(priv->dev, "The channel rate cannot be less than %dMbps",
2042 if (rate > cpsw->speed) {
2043 dev_err(priv->dev, "The channel rate cannot be more than 2Gbps");
2047 ret = pm_runtime_get_sync(cpsw->dev);
2049 pm_runtime_put_noidle(cpsw->dev);
2053 ret = cpdma_chan_set_rate(cpsw->txv[queue].ch, ch_rate);
2054 pm_runtime_put(cpsw->dev);
2059 /* update rates for slaves tx queues */
2060 for (i = 0; i < cpsw->data.slaves; i++) {
2061 slave = &cpsw->slaves[i];
2065 netdev_get_tx_queue(slave->ndev, queue)->tx_maxrate = rate;
2068 cpsw_split_res(ndev);
2072 static const struct net_device_ops cpsw_netdev_ops = {
2073 .ndo_open = cpsw_ndo_open,
2074 .ndo_stop = cpsw_ndo_stop,
2075 .ndo_start_xmit = cpsw_ndo_start_xmit,
2076 .ndo_set_mac_address = cpsw_ndo_set_mac_address,
2077 .ndo_do_ioctl = cpsw_ndo_ioctl,
2078 .ndo_validate_addr = eth_validate_addr,
2079 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
2080 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
2081 .ndo_set_tx_maxrate = cpsw_ndo_set_tx_maxrate,
2082 #ifdef CONFIG_NET_POLL_CONTROLLER
2083 .ndo_poll_controller = cpsw_ndo_poll_controller,
2085 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
2086 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
2089 static int cpsw_get_regs_len(struct net_device *ndev)
2091 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2093 return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
2096 static void cpsw_get_regs(struct net_device *ndev,
2097 struct ethtool_regs *regs, void *p)
2100 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2102 /* update CPSW IP version */
2103 regs->version = cpsw->version;
2105 cpsw_ale_dump(cpsw->ale, reg);
2108 static void cpsw_get_drvinfo(struct net_device *ndev,
2109 struct ethtool_drvinfo *info)
2111 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2112 struct platform_device *pdev = to_platform_device(cpsw->dev);
2114 strlcpy(info->driver, "cpsw", sizeof(info->driver));
2115 strlcpy(info->version, "1.0", sizeof(info->version));
2116 strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info));
2119 static u32 cpsw_get_msglevel(struct net_device *ndev)
2121 struct cpsw_priv *priv = netdev_priv(ndev);
2122 return priv->msg_enable;
2125 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
2127 struct cpsw_priv *priv = netdev_priv(ndev);
2128 priv->msg_enable = value;
2131 #if IS_ENABLED(CONFIG_TI_CPTS)
2132 static int cpsw_get_ts_info(struct net_device *ndev,
2133 struct ethtool_ts_info *info)
2135 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2137 info->so_timestamping =
2138 SOF_TIMESTAMPING_TX_HARDWARE |
2139 SOF_TIMESTAMPING_TX_SOFTWARE |
2140 SOF_TIMESTAMPING_RX_HARDWARE |
2141 SOF_TIMESTAMPING_RX_SOFTWARE |
2142 SOF_TIMESTAMPING_SOFTWARE |
2143 SOF_TIMESTAMPING_RAW_HARDWARE;
2144 info->phc_index = cpsw->cpts->phc_index;
2146 (1 << HWTSTAMP_TX_OFF) |
2147 (1 << HWTSTAMP_TX_ON);
2149 (1 << HWTSTAMP_FILTER_NONE) |
2150 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2154 static int cpsw_get_ts_info(struct net_device *ndev,
2155 struct ethtool_ts_info *info)
2157 info->so_timestamping =
2158 SOF_TIMESTAMPING_TX_SOFTWARE |
2159 SOF_TIMESTAMPING_RX_SOFTWARE |
2160 SOF_TIMESTAMPING_SOFTWARE;
2161 info->phc_index = -1;
2163 info->rx_filters = 0;
2168 static int cpsw_get_link_ksettings(struct net_device *ndev,
2169 struct ethtool_link_ksettings *ecmd)
2171 struct cpsw_priv *priv = netdev_priv(ndev);
2172 struct cpsw_common *cpsw = priv->cpsw;
2173 int slave_no = cpsw_slave_index(cpsw, priv);
2175 if (cpsw->slaves[slave_no].phy)
2176 return phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy,
2182 static int cpsw_set_link_ksettings(struct net_device *ndev,
2183 const struct ethtool_link_ksettings *ecmd)
2185 struct cpsw_priv *priv = netdev_priv(ndev);
2186 struct cpsw_common *cpsw = priv->cpsw;
2187 int slave_no = cpsw_slave_index(cpsw, priv);
2189 if (cpsw->slaves[slave_no].phy)
2190 return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy,
2196 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2198 struct cpsw_priv *priv = netdev_priv(ndev);
2199 struct cpsw_common *cpsw = priv->cpsw;
2200 int slave_no = cpsw_slave_index(cpsw, priv);
2205 if (cpsw->slaves[slave_no].phy)
2206 phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol);
2209 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2211 struct cpsw_priv *priv = netdev_priv(ndev);
2212 struct cpsw_common *cpsw = priv->cpsw;
2213 int slave_no = cpsw_slave_index(cpsw, priv);
2215 if (cpsw->slaves[slave_no].phy)
2216 return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol);
2221 static void cpsw_get_pauseparam(struct net_device *ndev,
2222 struct ethtool_pauseparam *pause)
2224 struct cpsw_priv *priv = netdev_priv(ndev);
2226 pause->autoneg = AUTONEG_DISABLE;
2227 pause->rx_pause = priv->rx_pause ? true : false;
2228 pause->tx_pause = priv->tx_pause ? true : false;
2231 static int cpsw_set_pauseparam(struct net_device *ndev,
2232 struct ethtool_pauseparam *pause)
2234 struct cpsw_priv *priv = netdev_priv(ndev);
2237 priv->rx_pause = pause->rx_pause ? true : false;
2238 priv->tx_pause = pause->tx_pause ? true : false;
2240 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
2244 static int cpsw_ethtool_op_begin(struct net_device *ndev)
2246 struct cpsw_priv *priv = netdev_priv(ndev);
2247 struct cpsw_common *cpsw = priv->cpsw;
2250 ret = pm_runtime_get_sync(cpsw->dev);
2252 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
2253 pm_runtime_put_noidle(cpsw->dev);
2259 static void cpsw_ethtool_op_complete(struct net_device *ndev)
2261 struct cpsw_priv *priv = netdev_priv(ndev);
2264 ret = pm_runtime_put(priv->cpsw->dev);
2266 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
2269 static void cpsw_get_channels(struct net_device *ndev,
2270 struct ethtool_channels *ch)
2272 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2274 ch->max_combined = 0;
2275 ch->max_rx = CPSW_MAX_QUEUES;
2276 ch->max_tx = CPSW_MAX_QUEUES;
2278 ch->other_count = 0;
2279 ch->rx_count = cpsw->rx_ch_num;
2280 ch->tx_count = cpsw->tx_ch_num;
2281 ch->combined_count = 0;
2284 static int cpsw_check_ch_settings(struct cpsw_common *cpsw,
2285 struct ethtool_channels *ch)
2287 if (ch->combined_count)
2290 /* verify we have at least one channel in each direction */
2291 if (!ch->rx_count || !ch->tx_count)
2294 if (ch->rx_count > cpsw->data.channels ||
2295 ch->tx_count > cpsw->data.channels)
2301 static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx)
2303 int (*poll)(struct napi_struct *, int);
2304 struct cpsw_common *cpsw = priv->cpsw;
2305 void (*handler)(void *, int, int);
2306 struct netdev_queue *queue;
2307 struct cpsw_vector *vec;
2311 ch = &cpsw->rx_ch_num;
2313 handler = cpsw_rx_handler;
2314 poll = cpsw_rx_poll;
2316 ch = &cpsw->tx_ch_num;
2318 handler = cpsw_tx_handler;
2319 poll = cpsw_tx_poll;
2322 while (*ch < ch_num) {
2323 vec[*ch].ch = cpdma_chan_create(cpsw->dma, *ch, handler, rx);
2324 queue = netdev_get_tx_queue(priv->ndev, *ch);
2325 queue->tx_maxrate = 0;
2327 if (IS_ERR(vec[*ch].ch))
2328 return PTR_ERR(vec[*ch].ch);
2333 cpsw_info(priv, ifup, "created new %d %s channel\n", *ch,
2334 (rx ? "rx" : "tx"));
2338 while (*ch > ch_num) {
2341 ret = cpdma_chan_destroy(vec[*ch].ch);
2345 cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch,
2346 (rx ? "rx" : "tx"));
2352 static int cpsw_update_channels(struct cpsw_priv *priv,
2353 struct ethtool_channels *ch)
2357 ret = cpsw_update_channels_res(priv, ch->rx_count, 1);
2361 ret = cpsw_update_channels_res(priv, ch->tx_count, 0);
2368 static int cpsw_set_channels(struct net_device *ndev,
2369 struct ethtool_channels *chs)
2371 struct cpsw_priv *priv = netdev_priv(ndev);
2372 struct cpsw_common *cpsw = priv->cpsw;
2373 struct cpsw_slave *slave;
2376 ret = cpsw_check_ch_settings(cpsw, chs);
2380 /* Disable NAPI scheduling */
2381 cpsw_intr_disable(cpsw);
2383 /* Stop all transmit queues for every network device.
2384 * Disable re-using rx descriptors with dormant_on.
2386 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2387 if (!(slave->ndev && netif_running(slave->ndev)))
2390 netif_tx_stop_all_queues(slave->ndev);
2391 netif_dormant_on(slave->ndev);
2394 /* Handle rest of tx packets and stop cpdma channels */
2395 cpdma_ctlr_stop(cpsw->dma);
2396 ret = cpsw_update_channels(priv, chs);
2400 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2401 if (!(slave->ndev && netif_running(slave->ndev)))
2404 /* Inform stack about new count of queues */
2405 ret = netif_set_real_num_tx_queues(slave->ndev,
2408 dev_err(priv->dev, "cannot set real number of tx queues\n");
2412 ret = netif_set_real_num_rx_queues(slave->ndev,
2415 dev_err(priv->dev, "cannot set real number of rx queues\n");
2419 /* Enable rx packets handling */
2420 netif_dormant_off(slave->ndev);
2423 if (cpsw_common_res_usage_state(cpsw)) {
2424 ret = cpsw_fill_rx_channels(priv);
2428 cpsw_split_res(ndev);
2430 /* After this receive is started */
2431 cpdma_ctlr_start(cpsw->dma);
2432 cpsw_intr_enable(cpsw);
2435 /* Resume transmit for every affected interface */
2436 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2437 if (!(slave->ndev && netif_running(slave->ndev)))
2439 netif_tx_start_all_queues(slave->ndev);
2443 dev_err(priv->dev, "cannot update channels number, closing device\n");
2448 static int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
2450 struct cpsw_priv *priv = netdev_priv(ndev);
2451 struct cpsw_common *cpsw = priv->cpsw;
2452 int slave_no = cpsw_slave_index(cpsw, priv);
2454 if (cpsw->slaves[slave_no].phy)
2455 return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata);
2460 static int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
2462 struct cpsw_priv *priv = netdev_priv(ndev);
2463 struct cpsw_common *cpsw = priv->cpsw;
2464 int slave_no = cpsw_slave_index(cpsw, priv);
2466 if (cpsw->slaves[slave_no].phy)
2467 return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata);
2472 static int cpsw_nway_reset(struct net_device *ndev)
2474 struct cpsw_priv *priv = netdev_priv(ndev);
2475 struct cpsw_common *cpsw = priv->cpsw;
2476 int slave_no = cpsw_slave_index(cpsw, priv);
2478 if (cpsw->slaves[slave_no].phy)
2479 return genphy_restart_aneg(cpsw->slaves[slave_no].phy);
2484 static void cpsw_get_ringparam(struct net_device *ndev,
2485 struct ethtool_ringparam *ering)
2487 struct cpsw_priv *priv = netdev_priv(ndev);
2488 struct cpsw_common *cpsw = priv->cpsw;
2491 ering->tx_max_pending = 0;
2492 ering->tx_pending = cpdma_get_num_tx_descs(cpsw->dma);
2493 ering->rx_max_pending = descs_pool_size - CPSW_MAX_QUEUES;
2494 ering->rx_pending = cpdma_get_num_rx_descs(cpsw->dma);
2497 static int cpsw_set_ringparam(struct net_device *ndev,
2498 struct ethtool_ringparam *ering)
2500 struct cpsw_priv *priv = netdev_priv(ndev);
2501 struct cpsw_common *cpsw = priv->cpsw;
2502 struct cpsw_slave *slave;
2505 /* ignore ering->tx_pending - only rx_pending adjustment is supported */
2507 if (ering->rx_mini_pending || ering->rx_jumbo_pending ||
2508 ering->rx_pending < CPSW_MAX_QUEUES ||
2509 ering->rx_pending > (descs_pool_size - CPSW_MAX_QUEUES))
2512 if (ering->rx_pending == cpdma_get_num_rx_descs(cpsw->dma))
2515 /* Disable NAPI scheduling */
2516 cpsw_intr_disable(cpsw);
2518 /* Stop all transmit queues for every network device.
2519 * Disable re-using rx descriptors with dormant_on.
2521 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2522 if (!(slave->ndev && netif_running(slave->ndev)))
2525 netif_tx_stop_all_queues(slave->ndev);
2526 netif_dormant_on(slave->ndev);
2529 /* Handle rest of tx packets and stop cpdma channels */
2530 cpdma_ctlr_stop(cpsw->dma);
2532 cpdma_set_num_rx_descs(cpsw->dma, ering->rx_pending);
2534 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2535 if (!(slave->ndev && netif_running(slave->ndev)))
2538 /* Enable rx packets handling */
2539 netif_dormant_off(slave->ndev);
2542 if (cpsw_common_res_usage_state(cpsw)) {
2543 cpdma_chan_split_pool(cpsw->dma);
2545 ret = cpsw_fill_rx_channels(priv);
2549 /* After this receive is started */
2550 cpdma_ctlr_start(cpsw->dma);
2551 cpsw_intr_enable(cpsw);
2554 /* Resume transmit for every affected interface */
2555 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2556 if (!(slave->ndev && netif_running(slave->ndev)))
2558 netif_tx_start_all_queues(slave->ndev);
2562 dev_err(priv->dev, "cannot set ring params, closing device\n");
2567 static const struct ethtool_ops cpsw_ethtool_ops = {
2568 .get_drvinfo = cpsw_get_drvinfo,
2569 .get_msglevel = cpsw_get_msglevel,
2570 .set_msglevel = cpsw_set_msglevel,
2571 .get_link = ethtool_op_get_link,
2572 .get_ts_info = cpsw_get_ts_info,
2573 .get_coalesce = cpsw_get_coalesce,
2574 .set_coalesce = cpsw_set_coalesce,
2575 .get_sset_count = cpsw_get_sset_count,
2576 .get_strings = cpsw_get_strings,
2577 .get_ethtool_stats = cpsw_get_ethtool_stats,
2578 .get_pauseparam = cpsw_get_pauseparam,
2579 .set_pauseparam = cpsw_set_pauseparam,
2580 .get_wol = cpsw_get_wol,
2581 .set_wol = cpsw_set_wol,
2582 .get_regs_len = cpsw_get_regs_len,
2583 .get_regs = cpsw_get_regs,
2584 .begin = cpsw_ethtool_op_begin,
2585 .complete = cpsw_ethtool_op_complete,
2586 .get_channels = cpsw_get_channels,
2587 .set_channels = cpsw_set_channels,
2588 .get_link_ksettings = cpsw_get_link_ksettings,
2589 .set_link_ksettings = cpsw_set_link_ksettings,
2590 .get_eee = cpsw_get_eee,
2591 .set_eee = cpsw_set_eee,
2592 .nway_reset = cpsw_nway_reset,
2593 .get_ringparam = cpsw_get_ringparam,
2594 .set_ringparam = cpsw_set_ringparam,
2597 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw,
2598 u32 slave_reg_ofs, u32 sliver_reg_ofs)
2600 void __iomem *regs = cpsw->regs;
2601 int slave_num = slave->slave_num;
2602 struct cpsw_slave_data *data = cpsw->data.slave_data + slave_num;
2605 slave->regs = regs + slave_reg_ofs;
2606 slave->sliver = regs + sliver_reg_ofs;
2607 slave->port_vlan = data->dual_emac_res_vlan;
2610 static int cpsw_probe_dt(struct cpsw_platform_data *data,
2611 struct platform_device *pdev)
2613 struct device_node *node = pdev->dev.of_node;
2614 struct device_node *slave_node;
2621 if (of_property_read_u32(node, "slaves", &prop)) {
2622 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
2625 data->slaves = prop;
2627 if (of_property_read_u32(node, "active_slave", &prop)) {
2628 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
2631 data->active_slave = prop;
2633 data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
2634 * sizeof(struct cpsw_slave_data),
2636 if (!data->slave_data)
2639 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
2640 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
2643 data->channels = prop;
2645 if (of_property_read_u32(node, "ale_entries", &prop)) {
2646 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
2649 data->ale_entries = prop;
2651 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
2652 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
2655 data->bd_ram_size = prop;
2657 if (of_property_read_u32(node, "mac_control", &prop)) {
2658 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2661 data->mac_control = prop;
2663 if (of_property_read_bool(node, "dual_emac"))
2664 data->dual_emac = 1;
2667 * Populate all the child nodes here...
2669 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2670 /* We do not want to force this, as in some cases may not have child */
2672 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2674 for_each_available_child_of_node(node, slave_node) {
2675 struct cpsw_slave_data *slave_data = data->slave_data + i;
2676 const void *mac_addr = NULL;
2680 /* This is no slave child node, continue */
2681 if (strcmp(slave_node->name, "slave"))
2684 slave_data->phy_node = of_parse_phandle(slave_node,
2686 parp = of_get_property(slave_node, "phy_id", &lenp);
2687 if (slave_data->phy_node) {
2689 "slave[%d] using phy-handle=\"%s\"\n",
2690 i, slave_data->phy_node->full_name);
2691 } else if (of_phy_is_fixed_link(slave_node)) {
2692 /* In the case of a fixed PHY, the DT node associated
2693 * to the PHY is the Ethernet MAC DT node.
2695 ret = of_phy_register_fixed_link(slave_node);
2697 if (ret != -EPROBE_DEFER)
2698 dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret);
2701 slave_data->phy_node = of_node_get(slave_node);
2704 struct device_node *mdio_node;
2705 struct platform_device *mdio;
2707 if (lenp != (sizeof(__be32) * 2)) {
2708 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2711 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2712 phyid = be32_to_cpup(parp+1);
2713 mdio = of_find_device_by_node(mdio_node);
2714 of_node_put(mdio_node);
2716 dev_err(&pdev->dev, "Missing mdio platform device\n");
2719 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2720 PHY_ID_FMT, mdio->name, phyid);
2721 put_device(&mdio->dev);
2724 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2728 slave_data->phy_if = of_get_phy_mode(slave_node);
2729 if (slave_data->phy_if < 0) {
2730 dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2732 return slave_data->phy_if;
2736 mac_addr = of_get_mac_address(slave_node);
2738 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2740 ret = ti_cm_get_macid(&pdev->dev, i,
2741 slave_data->mac_addr);
2745 if (data->dual_emac) {
2746 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2748 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2749 slave_data->dual_emac_res_vlan = i+1;
2750 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2751 slave_data->dual_emac_res_vlan, i);
2753 slave_data->dual_emac_res_vlan = prop;
2758 if (i == data->slaves)
2765 static void cpsw_remove_dt(struct platform_device *pdev)
2767 struct net_device *ndev = platform_get_drvdata(pdev);
2768 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2769 struct cpsw_platform_data *data = &cpsw->data;
2770 struct device_node *node = pdev->dev.of_node;
2771 struct device_node *slave_node;
2774 for_each_available_child_of_node(node, slave_node) {
2775 struct cpsw_slave_data *slave_data = &data->slave_data[i];
2777 if (strcmp(slave_node->name, "slave"))
2780 if (of_phy_is_fixed_link(slave_node))
2781 of_phy_deregister_fixed_link(slave_node);
2783 of_node_put(slave_data->phy_node);
2786 if (i == data->slaves)
2790 of_platform_depopulate(&pdev->dev);
2793 static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
2795 struct cpsw_common *cpsw = priv->cpsw;
2796 struct cpsw_platform_data *data = &cpsw->data;
2797 struct net_device *ndev;
2798 struct cpsw_priv *priv_sl2;
2801 ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2803 dev_err(cpsw->dev, "cpsw: error allocating net_device\n");
2807 priv_sl2 = netdev_priv(ndev);
2808 priv_sl2->cpsw = cpsw;
2809 priv_sl2->ndev = ndev;
2810 priv_sl2->dev = &ndev->dev;
2811 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2813 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2814 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2816 dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n",
2817 priv_sl2->mac_addr);
2819 random_ether_addr(priv_sl2->mac_addr);
2820 dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n",
2821 priv_sl2->mac_addr);
2823 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2825 priv_sl2->emac_port = 1;
2826 cpsw->slaves[1].ndev = ndev;
2827 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2829 ndev->netdev_ops = &cpsw_netdev_ops;
2830 ndev->ethtool_ops = &cpsw_ethtool_ops;
2832 /* register the network device */
2833 SET_NETDEV_DEV(ndev, cpsw->dev);
2834 ret = register_netdev(ndev);
2836 dev_err(cpsw->dev, "cpsw: error registering net device\n");
2844 #define CPSW_QUIRK_IRQ BIT(0)
2846 static struct platform_device_id cpsw_devtype[] = {
2848 /* keep it for existing comaptibles */
2850 .driver_data = CPSW_QUIRK_IRQ,
2852 .name = "am335x-cpsw",
2853 .driver_data = CPSW_QUIRK_IRQ,
2855 .name = "am4372-cpsw",
2858 .name = "dra7-cpsw",
2864 MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2873 static const struct of_device_id cpsw_of_mtable[] = {
2874 { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2875 { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2876 { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2877 { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2880 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2882 static int cpsw_probe(struct platform_device *pdev)
2885 struct cpsw_platform_data *data;
2886 struct net_device *ndev;
2887 struct cpsw_priv *priv;
2888 struct cpdma_params dma_params;
2889 struct cpsw_ale_params ale_params;
2890 void __iomem *ss_regs;
2891 void __iomem *cpts_regs;
2892 struct resource *res, *ss_res;
2893 const struct of_device_id *of_id;
2894 struct gpio_descs *mode;
2895 u32 slave_offset, sliver_offset, slave_size;
2896 struct cpsw_common *cpsw;
2900 cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL);
2904 cpsw->dev = &pdev->dev;
2906 ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2908 dev_err(&pdev->dev, "error allocating net_device\n");
2912 platform_set_drvdata(pdev, ndev);
2913 priv = netdev_priv(ndev);
2916 priv->dev = &ndev->dev;
2917 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2918 cpsw->rx_packet_max = max(rx_packet_max, 128);
2920 mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2922 ret = PTR_ERR(mode);
2923 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2924 goto clean_ndev_ret;
2928 * This may be required here for child devices.
2930 pm_runtime_enable(&pdev->dev);
2932 /* Select default pin state */
2933 pinctrl_pm_select_default_state(&pdev->dev);
2935 /* Need to enable clocks with runtime PM api to access module
2938 ret = pm_runtime_get_sync(&pdev->dev);
2940 pm_runtime_put_noidle(&pdev->dev);
2941 goto clean_runtime_disable_ret;
2944 ret = cpsw_probe_dt(&cpsw->data, pdev);
2949 cpsw->rx_ch_num = 1;
2950 cpsw->tx_ch_num = 1;
2952 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2953 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2954 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2956 eth_random_addr(priv->mac_addr);
2957 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2960 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2962 cpsw->slaves = devm_kzalloc(&pdev->dev,
2963 sizeof(struct cpsw_slave) * data->slaves,
2965 if (!cpsw->slaves) {
2969 for (i = 0; i < data->slaves; i++)
2970 cpsw->slaves[i].slave_num = i;
2972 cpsw->slaves[0].ndev = ndev;
2973 priv->emac_port = 0;
2975 clk = devm_clk_get(&pdev->dev, "fck");
2977 dev_err(priv->dev, "fck is not found\n");
2981 cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000;
2983 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2984 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2985 if (IS_ERR(ss_regs)) {
2986 ret = PTR_ERR(ss_regs);
2989 cpsw->regs = ss_regs;
2991 cpsw->version = readl(&cpsw->regs->id_ver);
2993 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2994 cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2995 if (IS_ERR(cpsw->wr_regs)) {
2996 ret = PTR_ERR(cpsw->wr_regs);
3000 memset(&dma_params, 0, sizeof(dma_params));
3001 memset(&ale_params, 0, sizeof(ale_params));
3003 switch (cpsw->version) {
3004 case CPSW_VERSION_1:
3005 cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
3006 cpts_regs = ss_regs + CPSW1_CPTS_OFFSET;
3007 cpsw->hw_stats = ss_regs + CPSW1_HW_STATS;
3008 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
3009 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
3010 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
3011 slave_offset = CPSW1_SLAVE_OFFSET;
3012 slave_size = CPSW1_SLAVE_SIZE;
3013 sliver_offset = CPSW1_SLIVER_OFFSET;
3014 dma_params.desc_mem_phys = 0;
3016 case CPSW_VERSION_2:
3017 case CPSW_VERSION_3:
3018 case CPSW_VERSION_4:
3019 cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
3020 cpts_regs = ss_regs + CPSW2_CPTS_OFFSET;
3021 cpsw->hw_stats = ss_regs + CPSW2_HW_STATS;
3022 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
3023 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
3024 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
3025 slave_offset = CPSW2_SLAVE_OFFSET;
3026 slave_size = CPSW2_SLAVE_SIZE;
3027 sliver_offset = CPSW2_SLIVER_OFFSET;
3028 dma_params.desc_mem_phys =
3029 (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
3032 dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version);
3036 for (i = 0; i < cpsw->data.slaves; i++) {
3037 struct cpsw_slave *slave = &cpsw->slaves[i];
3039 cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset);
3040 slave_offset += slave_size;
3041 sliver_offset += SLIVER_SIZE;
3044 dma_params.dev = &pdev->dev;
3045 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
3046 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
3047 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
3048 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
3049 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
3051 dma_params.num_chan = data->channels;
3052 dma_params.has_soft_reset = true;
3053 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
3054 dma_params.desc_mem_size = data->bd_ram_size;
3055 dma_params.desc_align = 16;
3056 dma_params.has_ext_regs = true;
3057 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
3058 dma_params.bus_freq_mhz = cpsw->bus_freq_mhz;
3059 dma_params.descs_pool_size = descs_pool_size;
3061 cpsw->dma = cpdma_ctlr_create(&dma_params);
3063 dev_err(priv->dev, "error initializing dma\n");
3068 cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_tx_handler, 0);
3069 cpsw->rxv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1);
3070 if (WARN_ON(!cpsw->rxv[0].ch || !cpsw->txv[0].ch)) {
3071 dev_err(priv->dev, "error initializing dma channels\n");
3076 ale_params.dev = &ndev->dev;
3077 ale_params.ale_ageout = ale_ageout;
3078 ale_params.ale_entries = data->ale_entries;
3079 ale_params.ale_ports = data->slaves;
3081 cpsw->ale = cpsw_ale_create(&ale_params);
3083 dev_err(priv->dev, "error initializing ale engine\n");
3088 cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpsw->dev->of_node);
3089 if (IS_ERR(cpsw->cpts)) {
3090 ret = PTR_ERR(cpsw->cpts);
3094 ndev->irq = platform_get_irq(pdev, 1);
3095 if (ndev->irq < 0) {
3096 dev_err(priv->dev, "error getting irq resource\n");
3101 of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
3103 pdev->id_entry = of_id->data;
3104 if (pdev->id_entry->driver_data)
3105 cpsw->quirk_irq = true;
3108 /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
3109 * MISC IRQs which are always kept disabled with this driver so
3110 * we will not request them.
3112 * If anyone wants to implement support for those, make sure to
3113 * first request and append them to irqs_table array.
3117 irq = platform_get_irq(pdev, 1);
3123 cpsw->irqs_table[0] = irq;
3124 ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
3125 0, dev_name(&pdev->dev), cpsw);
3127 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3132 irq = platform_get_irq(pdev, 2);
3138 cpsw->irqs_table[1] = irq;
3139 ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
3140 0, dev_name(&pdev->dev), cpsw);
3142 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3146 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3148 ndev->netdev_ops = &cpsw_netdev_ops;
3149 ndev->ethtool_ops = &cpsw_ethtool_ops;
3150 netif_napi_add(ndev, &cpsw->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
3151 netif_tx_napi_add(ndev, &cpsw->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
3152 cpsw_split_res(ndev);
3154 /* register the network device */
3155 SET_NETDEV_DEV(ndev, &pdev->dev);
3156 ret = register_netdev(ndev);
3158 dev_err(priv->dev, "error registering net device\n");
3163 cpsw_notice(priv, probe,
3164 "initialized device (regs %pa, irq %d, pool size %d)\n",
3165 &ss_res->start, ndev->irq, dma_params.descs_pool_size);
3166 if (cpsw->data.dual_emac) {
3167 ret = cpsw_probe_dual_emac(priv);
3169 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
3170 goto clean_unregister_netdev_ret;
3174 pm_runtime_put(&pdev->dev);
3178 clean_unregister_netdev_ret:
3179 unregister_netdev(ndev);
3181 cpsw_ale_destroy(cpsw->ale);
3183 cpdma_ctlr_destroy(cpsw->dma);
3185 cpsw_remove_dt(pdev);
3186 pm_runtime_put_sync(&pdev->dev);
3187 clean_runtime_disable_ret:
3188 pm_runtime_disable(&pdev->dev);
3190 free_netdev(priv->ndev);
3194 static int cpsw_remove(struct platform_device *pdev)
3196 struct net_device *ndev = platform_get_drvdata(pdev);
3197 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3200 ret = pm_runtime_get_sync(&pdev->dev);
3202 pm_runtime_put_noidle(&pdev->dev);
3206 if (cpsw->data.dual_emac)
3207 unregister_netdev(cpsw->slaves[1].ndev);
3208 unregister_netdev(ndev);
3210 cpts_release(cpsw->cpts);
3211 cpsw_ale_destroy(cpsw->ale);
3212 cpdma_ctlr_destroy(cpsw->dma);
3213 cpsw_remove_dt(pdev);
3214 pm_runtime_put_sync(&pdev->dev);
3215 pm_runtime_disable(&pdev->dev);
3216 if (cpsw->data.dual_emac)
3217 free_netdev(cpsw->slaves[1].ndev);
3222 #ifdef CONFIG_PM_SLEEP
3223 static int cpsw_suspend(struct device *dev)
3225 struct platform_device *pdev = to_platform_device(dev);
3226 struct net_device *ndev = platform_get_drvdata(pdev);
3227 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3229 if (cpsw->data.dual_emac) {
3232 for (i = 0; i < cpsw->data.slaves; i++) {
3233 if (netif_running(cpsw->slaves[i].ndev))
3234 cpsw_ndo_stop(cpsw->slaves[i].ndev);
3237 if (netif_running(ndev))
3238 cpsw_ndo_stop(ndev);
3241 /* Select sleep pin state */
3242 pinctrl_pm_select_sleep_state(dev);
3247 static int cpsw_resume(struct device *dev)
3249 struct platform_device *pdev = to_platform_device(dev);
3250 struct net_device *ndev = platform_get_drvdata(pdev);
3251 struct cpsw_common *cpsw = netdev_priv(ndev);
3253 /* Select default pin state */
3254 pinctrl_pm_select_default_state(dev);
3256 /* shut up ASSERT_RTNL() warning in netif_set_real_num_tx/rx_queues */
3258 if (cpsw->data.dual_emac) {
3261 for (i = 0; i < cpsw->data.slaves; i++) {
3262 if (netif_running(cpsw->slaves[i].ndev))
3263 cpsw_ndo_open(cpsw->slaves[i].ndev);
3266 if (netif_running(ndev))
3267 cpsw_ndo_open(ndev);
3275 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
3277 static struct platform_driver cpsw_driver = {
3281 .of_match_table = cpsw_of_mtable,
3283 .probe = cpsw_probe,
3284 .remove = cpsw_remove,
3287 module_platform_driver(cpsw_driver);
3289 MODULE_LICENSE("GPL");
3290 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
3291 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
3292 MODULE_DESCRIPTION("TI CPSW Ethernet driver");