2 * drivers/net/phy/marvell.c
4 * Driver for Marvell PHYs
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
10 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
18 #include <linux/kernel.h>
19 #include <linux/string.h>
20 #include <linux/ctype.h>
21 #include <linux/errno.h>
22 #include <linux/unistd.h>
23 #include <linux/hwmon.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
29 #include <linux/skbuff.h>
30 #include <linux/spinlock.h>
32 #include <linux/module.h>
33 #include <linux/mii.h>
34 #include <linux/ethtool.h>
35 #include <linux/phy.h>
36 #include <linux/marvell_phy.h>
41 #include <linux/uaccess.h>
43 #define MII_MARVELL_PHY_PAGE 22
45 #define MII_M1011_IEVENT 0x13
46 #define MII_M1011_IEVENT_CLEAR 0x0000
48 #define MII_M1011_IMASK 0x12
49 #define MII_M1011_IMASK_INIT 0x6400
50 #define MII_M1011_IMASK_CLEAR 0x0000
52 #define MII_M1011_PHY_SCR 0x10
53 #define MII_M1011_PHY_SCR_MDI 0x0000
54 #define MII_M1011_PHY_SCR_MDI_X 0x0020
55 #define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
57 #define MII_M1145_PHY_EXT_ADDR_PAGE 0x16
58 #define MII_M1145_PHY_EXT_SR 0x1b
59 #define MII_M1145_PHY_EXT_CR 0x14
60 #define MII_M1145_RGMII_RX_DELAY 0x0080
61 #define MII_M1145_RGMII_TX_DELAY 0x0002
62 #define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
63 #define MII_M1145_HWCFG_MODE_MASK 0xf
64 #define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
66 #define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
67 #define MII_M1145_HWCFG_MODE_MASK 0xf
68 #define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
70 #define MII_M1111_PHY_LED_CONTROL 0x18
71 #define MII_M1111_PHY_LED_DIRECT 0x4100
72 #define MII_M1111_PHY_LED_COMBINE 0x411c
73 #define MII_M1111_PHY_EXT_CR 0x14
74 #define MII_M1111_RX_DELAY 0x80
75 #define MII_M1111_TX_DELAY 0x2
76 #define MII_M1111_PHY_EXT_SR 0x1b
78 #define MII_M1111_HWCFG_MODE_MASK 0xf
79 #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
80 #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
81 #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
82 #define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
83 #define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
84 #define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
86 #define MII_M1111_COPPER 0
87 #define MII_M1111_FIBER 1
89 #define MII_88E1121_PHY_MSCR_PAGE 2
90 #define MII_88E1121_PHY_MSCR_REG 21
91 #define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
92 #define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
93 #define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
95 #define MII_88E1121_MISC_TEST 0x1a
96 #define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK 0x1f00
97 #define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT 8
98 #define MII_88E1510_MISC_TEST_TEMP_IRQ_EN BIT(7)
99 #define MII_88E1510_MISC_TEST_TEMP_IRQ BIT(6)
100 #define MII_88E1121_MISC_TEST_TEMP_SENSOR_EN BIT(5)
101 #define MII_88E1121_MISC_TEST_TEMP_MASK 0x1f
103 #define MII_88E1510_TEMP_SENSOR 0x1b
104 #define MII_88E1510_TEMP_SENSOR_MASK 0xff
106 #define MII_88E1318S_PHY_MSCR1_REG 16
107 #define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
109 /* Copper Specific Interrupt Enable Register */
110 #define MII_88E1318S_PHY_CSIER 0x12
111 /* WOL Event Interrupt Enable */
112 #define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
114 /* LED Timer Control Register */
115 #define MII_88E1318S_PHY_LED_PAGE 0x03
116 #define MII_88E1318S_PHY_LED_TCR 0x12
117 #define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
118 #define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
119 #define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
121 /* Magic Packet MAC address registers */
122 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
123 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
124 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
126 #define MII_88E1318S_PHY_WOL_PAGE 0x11
127 #define MII_88E1318S_PHY_WOL_CTRL 0x10
128 #define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
129 #define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
131 #define MII_88E1121_PHY_LED_CTRL 16
132 #define MII_88E1121_PHY_LED_PAGE 3
133 #define MII_88E1121_PHY_LED_DEF 0x0030
135 #define MII_M1011_PHY_STATUS 0x11
136 #define MII_M1011_PHY_STATUS_1000 0x8000
137 #define MII_M1011_PHY_STATUS_100 0x4000
138 #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
139 #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
140 #define MII_M1011_PHY_STATUS_RESOLVED 0x0800
141 #define MII_M1011_PHY_STATUS_LINK 0x0400
143 #define MII_M1116R_CONTROL_REG_MAC 21
145 #define MII_88E3016_PHY_SPEC_CTRL 0x10
146 #define MII_88E3016_DISABLE_SCRAMBLER 0x0200
147 #define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
149 #define MII_88E1510_GEN_CTRL_REG_1 0x14
150 #define MII_88E1510_GEN_CTRL_REG_1_MODE_MASK 0x7
151 #define MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII 0x1 /* SGMII to copper */
152 #define MII_88E1510_GEN_CTRL_REG_1_RESET 0x8000 /* Soft reset */
154 #define LPA_FIBER_1000HALF 0x40
155 #define LPA_FIBER_1000FULL 0x20
157 #define LPA_PAUSE_FIBER 0x180
158 #define LPA_PAUSE_ASYM_FIBER 0x100
160 #define ADVERTISE_FIBER_1000HALF 0x40
161 #define ADVERTISE_FIBER_1000FULL 0x20
163 #define ADVERTISE_PAUSE_FIBER 0x180
164 #define ADVERTISE_PAUSE_ASYM_FIBER 0x100
166 #define REGISTER_LINK_STATUS 0x400
167 #define NB_FIBER_STATS 1
169 MODULE_DESCRIPTION("Marvell PHY driver");
170 MODULE_AUTHOR("Andy Fleming");
171 MODULE_LICENSE("GPL");
173 struct marvell_hw_stat {
180 static struct marvell_hw_stat marvell_hw_stats[] = {
181 { "phy_receive_errors_copper", 0, 21, 16},
182 { "phy_idle_errors", 0, 10, 8 },
183 { "phy_receive_errors_fiber", 1, 21, 16},
186 struct marvell_priv {
187 u64 stats[ARRAY_SIZE(marvell_hw_stats)];
189 struct device *hwmon_dev;
192 static int marvell_get_page(struct phy_device *phydev)
194 return phy_read(phydev, MII_MARVELL_PHY_PAGE);
197 static int marvell_set_page(struct phy_device *phydev, int page)
199 return phy_write(phydev, MII_MARVELL_PHY_PAGE, page);
202 static int marvell_ack_interrupt(struct phy_device *phydev)
206 /* Clear the interrupts by reading the reg */
207 err = phy_read(phydev, MII_M1011_IEVENT);
215 static int marvell_config_intr(struct phy_device *phydev)
219 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
220 err = phy_write(phydev, MII_M1011_IMASK,
221 MII_M1011_IMASK_INIT);
223 err = phy_write(phydev, MII_M1011_IMASK,
224 MII_M1011_IMASK_CLEAR);
229 static int marvell_set_polarity(struct phy_device *phydev, int polarity)
235 /* get the current settings */
236 reg = phy_read(phydev, MII_M1011_PHY_SCR);
241 val &= ~MII_M1011_PHY_SCR_AUTO_CROSS;
244 val |= MII_M1011_PHY_SCR_MDI;
247 val |= MII_M1011_PHY_SCR_MDI_X;
249 case ETH_TP_MDI_AUTO:
250 case ETH_TP_MDI_INVALID:
252 val |= MII_M1011_PHY_SCR_AUTO_CROSS;
257 /* Set the new polarity value in the register */
258 err = phy_write(phydev, MII_M1011_PHY_SCR, val);
266 static int marvell_config_aneg(struct phy_device *phydev)
270 /* The Marvell PHY has an errata which requires
271 * that certain registers get written in order
272 * to restart autonegotiation
274 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
279 err = phy_write(phydev, 0x1d, 0x1f);
283 err = phy_write(phydev, 0x1e, 0x200c);
287 err = phy_write(phydev, 0x1d, 0x5);
291 err = phy_write(phydev, 0x1e, 0);
295 err = phy_write(phydev, 0x1e, 0x100);
299 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
303 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
304 MII_M1111_PHY_LED_DIRECT);
308 err = genphy_config_aneg(phydev);
312 if (phydev->autoneg != AUTONEG_ENABLE) {
315 /* A write to speed/duplex bits (that is performed by
316 * genphy_config_aneg() call above) must be followed by
317 * a software reset. Otherwise, the write has no effect.
319 bmcr = phy_read(phydev, MII_BMCR);
323 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
331 static int m88e1111_config_aneg(struct phy_device *phydev)
335 /* The Marvell PHY has an errata which requires
336 * that certain registers get written in order
337 * to restart autonegotiation
339 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
341 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
345 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
346 MII_M1111_PHY_LED_DIRECT);
350 err = genphy_config_aneg(phydev);
354 if (phydev->autoneg != AUTONEG_ENABLE) {
357 /* A write to speed/duplex bits (that is performed by
358 * genphy_config_aneg() call above) must be followed by
359 * a software reset. Otherwise, the write has no effect.
361 bmcr = phy_read(phydev, MII_BMCR);
365 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
373 #ifdef CONFIG_OF_MDIO
374 /* Set and/or override some configuration registers based on the
375 * marvell,reg-init property stored in the of_node for the phydev.
377 * marvell,reg-init = <reg-page reg mask value>,...;
379 * There may be one or more sets of <reg-page reg mask value>:
381 * reg-page: which register bank to use.
383 * mask: if non-zero, ANDed with existing register value.
384 * value: ORed with the masked value and written to the regiser.
387 static int marvell_of_reg_init(struct phy_device *phydev)
390 int len, i, saved_page, current_page, ret;
392 if (!phydev->mdio.dev.of_node)
395 paddr = of_get_property(phydev->mdio.dev.of_node,
396 "marvell,reg-init", &len);
397 if (!paddr || len < (4 * sizeof(*paddr)))
400 saved_page = marvell_get_page(phydev);
403 current_page = saved_page;
406 len /= sizeof(*paddr);
407 for (i = 0; i < len - 3; i += 4) {
408 u16 page = be32_to_cpup(paddr + i);
409 u16 reg = be32_to_cpup(paddr + i + 1);
410 u16 mask = be32_to_cpup(paddr + i + 2);
411 u16 val_bits = be32_to_cpup(paddr + i + 3);
414 if (page != current_page) {
416 ret = marvell_set_page(phydev, page);
423 val = phy_read(phydev, reg);
432 ret = phy_write(phydev, reg, val);
437 if (current_page != saved_page) {
438 i = marvell_set_page(phydev, saved_page);
445 static int marvell_of_reg_init(struct phy_device *phydev)
449 #endif /* CONFIG_OF_MDIO */
451 static int m88e1121_config_aneg(struct phy_device *phydev)
453 int err, oldpage, mscr;
455 oldpage = marvell_get_page(phydev);
457 err = marvell_set_page(phydev, MII_88E1121_PHY_MSCR_PAGE);
461 if (phy_interface_is_rgmii(phydev)) {
462 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
463 MII_88E1121_PHY_MSCR_DELAY_MASK;
465 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
466 mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
467 MII_88E1121_PHY_MSCR_TX_DELAY);
468 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
469 mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
470 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
471 mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
473 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
478 marvell_set_page(phydev, oldpage);
480 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
484 err = phy_write(phydev, MII_M1011_PHY_SCR,
485 MII_M1011_PHY_SCR_AUTO_CROSS);
489 return genphy_config_aneg(phydev);
492 static int m88e1318_config_aneg(struct phy_device *phydev)
494 int err, oldpage, mscr;
496 oldpage = marvell_get_page(phydev);
498 err = marvell_set_page(phydev, MII_88E1121_PHY_MSCR_PAGE);
502 mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
503 mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
505 err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr);
509 err = marvell_set_page(phydev, oldpage);
513 return m88e1121_config_aneg(phydev);
517 * ethtool_adv_to_fiber_adv_t
518 * @ethadv: the ethtool advertisement settings
520 * A small helper function that translates ethtool advertisement
521 * settings to phy autonegotiation advertisements for the
522 * MII_ADV register for fiber link.
524 static inline u32 ethtool_adv_to_fiber_adv_t(u32 ethadv)
528 if (ethadv & ADVERTISED_1000baseT_Half)
529 result |= ADVERTISE_FIBER_1000HALF;
530 if (ethadv & ADVERTISED_1000baseT_Full)
531 result |= ADVERTISE_FIBER_1000FULL;
533 if ((ethadv & ADVERTISE_PAUSE_ASYM) && (ethadv & ADVERTISE_PAUSE_CAP))
534 result |= LPA_PAUSE_ASYM_FIBER;
535 else if (ethadv & ADVERTISE_PAUSE_CAP)
536 result |= (ADVERTISE_PAUSE_FIBER
537 & (~ADVERTISE_PAUSE_ASYM_FIBER));
543 * marvell_config_aneg_fiber - restart auto-negotiation or write BMCR
544 * @phydev: target phy_device struct
546 * Description: If auto-negotiation is enabled, we configure the
547 * advertising, and then restart auto-negotiation. If it is not
548 * enabled, then we write the BMCR. Adapted for fiber link in
549 * some Marvell's devices.
551 static int marvell_config_aneg_fiber(struct phy_device *phydev)
558 if (phydev->autoneg != AUTONEG_ENABLE)
559 return genphy_setup_forced(phydev);
561 /* Only allow advertising what this PHY supports */
562 phydev->advertising &= phydev->supported;
563 advertise = phydev->advertising;
565 /* Setup fiber advertisement */
566 adv = phy_read(phydev, MII_ADVERTISE);
571 adv &= ~(ADVERTISE_FIBER_1000HALF | ADVERTISE_FIBER_1000FULL
573 adv |= ethtool_adv_to_fiber_adv_t(advertise);
576 err = phy_write(phydev, MII_ADVERTISE, adv);
584 /* Advertisement hasn't changed, but maybe aneg was never on to
585 * begin with? Or maybe phy was isolated?
587 int ctl = phy_read(phydev, MII_BMCR);
592 if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE))
593 changed = 1; /* do restart aneg */
596 /* Only restart aneg if we are advertising something different
597 * than we were before.
600 changed = genphy_restart_aneg(phydev);
605 static int m88e1510_config_aneg(struct phy_device *phydev)
609 err = marvell_set_page(phydev, MII_M1111_COPPER);
613 /* Configure the copper link first */
614 err = m88e1318_config_aneg(phydev);
618 /* Then the fiber link */
619 err = marvell_set_page(phydev, MII_M1111_FIBER);
623 err = marvell_config_aneg_fiber(phydev);
627 return marvell_set_page(phydev, MII_M1111_COPPER);
630 marvell_set_page(phydev, MII_M1111_COPPER);
634 static int marvell_config_init(struct phy_device *phydev)
636 /* Set registers from marvell,reg-init DT property */
637 return marvell_of_reg_init(phydev);
640 static int m88e1116r_config_init(struct phy_device *phydev)
645 temp = phy_read(phydev, MII_BMCR);
647 err = phy_write(phydev, MII_BMCR, temp);
653 err = marvell_set_page(phydev, MII_M1111_COPPER);
657 temp = phy_read(phydev, MII_M1011_PHY_SCR);
658 temp |= (7 << 12); /* max number of gigabit attempts */
659 temp |= (1 << 11); /* enable downshift */
660 temp |= MII_M1011_PHY_SCR_AUTO_CROSS;
661 err = phy_write(phydev, MII_M1011_PHY_SCR, temp);
665 err = marvell_set_page(phydev, MII_88E1121_PHY_MSCR_PAGE);
668 temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC);
671 err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp);
674 err = marvell_set_page(phydev, MII_M1111_COPPER);
678 temp = phy_read(phydev, MII_BMCR);
680 err = phy_write(phydev, MII_BMCR, temp);
686 return marvell_config_init(phydev);
689 static int m88e3016_config_init(struct phy_device *phydev)
693 /* Enable Scrambler and Auto-Crossover */
694 reg = phy_read(phydev, MII_88E3016_PHY_SPEC_CTRL);
698 reg &= ~MII_88E3016_DISABLE_SCRAMBLER;
699 reg |= MII_88E3016_AUTO_MDIX_CROSSOVER;
701 reg = phy_write(phydev, MII_88E3016_PHY_SPEC_CTRL, reg);
705 return marvell_config_init(phydev);
708 static int m88e1111_config_init_rgmii(struct phy_device *phydev)
713 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
717 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
718 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
719 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
720 temp &= ~MII_M1111_TX_DELAY;
721 temp |= MII_M1111_RX_DELAY;
722 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
723 temp &= ~MII_M1111_RX_DELAY;
724 temp |= MII_M1111_TX_DELAY;
727 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
731 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
735 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
737 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
738 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
740 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
742 return phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
745 static int m88e1111_config_init_sgmii(struct phy_device *phydev)
750 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
754 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
755 temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
756 temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
758 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
762 /* make sure copper is selected */
763 err = phy_read(phydev, MII_M1145_PHY_EXT_ADDR_PAGE);
767 return phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, err & (~0xff));
770 static int m88e1111_config_init_rtbi(struct phy_device *phydev)
775 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
779 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
780 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
784 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
788 temp &= ~(MII_M1111_HWCFG_MODE_MASK |
789 MII_M1111_HWCFG_FIBER_COPPER_RES);
790 temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
792 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
797 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
802 temp = phy_read(phydev, MII_BMCR);
803 while (temp & BMCR_RESET);
805 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
809 temp &= ~(MII_M1111_HWCFG_MODE_MASK |
810 MII_M1111_HWCFG_FIBER_COPPER_RES);
811 temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI |
812 MII_M1111_HWCFG_FIBER_COPPER_AUTO;
814 return phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
817 static int m88e1111_config_init(struct phy_device *phydev)
821 if (phy_interface_is_rgmii(phydev)) {
822 err = m88e1111_config_init_rgmii(phydev);
827 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
828 err = m88e1111_config_init_sgmii(phydev);
833 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
834 err = m88e1111_config_init_rtbi(phydev);
839 err = marvell_of_reg_init(phydev);
843 return phy_write(phydev, MII_BMCR, BMCR_RESET);
846 static int m88e1121_config_init(struct phy_device *phydev)
850 oldpage = marvell_get_page(phydev);
852 err = marvell_set_page(phydev, MII_88E1121_PHY_LED_PAGE);
856 /* Default PHY LED config: LED[0] .. Link, LED[1] .. Activity */
857 err = phy_write(phydev, MII_88E1121_PHY_LED_CTRL,
858 MII_88E1121_PHY_LED_DEF);
862 marvell_set_page(phydev, oldpage);
864 /* Set marvell,reg-init configuration from device tree */
865 return marvell_config_init(phydev);
868 static int m88e1510_config_init(struct phy_device *phydev)
873 /* SGMII-to-Copper mode initialization */
874 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
876 err = marvell_set_page(phydev, 18);
880 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
881 temp = phy_read(phydev, MII_88E1510_GEN_CTRL_REG_1);
882 temp &= ~MII_88E1510_GEN_CTRL_REG_1_MODE_MASK;
883 temp |= MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII;
884 err = phy_write(phydev, MII_88E1510_GEN_CTRL_REG_1, temp);
888 /* PHY reset is necessary after changing MODE[2:0] */
889 temp |= MII_88E1510_GEN_CTRL_REG_1_RESET;
890 err = phy_write(phydev, MII_88E1510_GEN_CTRL_REG_1, temp);
894 /* Reset page selection */
895 err = marvell_set_page(phydev, MII_M1111_COPPER);
900 return m88e1121_config_init(phydev);
903 static int m88e1118_config_aneg(struct phy_device *phydev)
907 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
911 err = phy_write(phydev, MII_M1011_PHY_SCR,
912 MII_M1011_PHY_SCR_AUTO_CROSS);
916 err = genphy_config_aneg(phydev);
920 static int m88e1118_config_init(struct phy_device *phydev)
925 err = marvell_set_page(phydev, MII_88E1121_PHY_MSCR_PAGE);
929 /* Enable 1000 Mbit */
930 err = phy_write(phydev, 0x15, 0x1070);
935 err = marvell_set_page(phydev, MII_88E1318S_PHY_LED_PAGE);
939 /* Adjust LED Control */
940 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
941 err = phy_write(phydev, 0x10, 0x1100);
943 err = phy_write(phydev, 0x10, 0x021e);
947 err = marvell_of_reg_init(phydev);
952 err = marvell_set_page(phydev, MII_M1111_COPPER);
956 return phy_write(phydev, MII_BMCR, BMCR_RESET);
959 static int m88e1149_config_init(struct phy_device *phydev)
964 err = marvell_set_page(phydev, MII_88E1121_PHY_MSCR_PAGE);
968 /* Enable 1000 Mbit */
969 err = phy_write(phydev, 0x15, 0x1048);
973 err = marvell_of_reg_init(phydev);
978 err = marvell_set_page(phydev, MII_M1111_COPPER);
982 return phy_write(phydev, MII_BMCR, BMCR_RESET);
985 static int m88e1145_config_init_rgmii(struct phy_device *phydev)
988 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
993 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
995 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
999 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
1000 err = phy_write(phydev, 0x1d, 0x0012);
1004 temp = phy_read(phydev, 0x1e);
1009 temp |= 2 << 9; /* 36 ohm */
1010 temp |= 2 << 6; /* 39 ohm */
1012 err = phy_write(phydev, 0x1e, temp);
1016 err = phy_write(phydev, 0x1d, 0x3);
1020 err = phy_write(phydev, 0x1e, 0x8000);
1025 static int m88e1145_config_init_sgmii(struct phy_device *phydev)
1027 int temp = phy_read(phydev, MII_M1145_PHY_EXT_SR);
1032 temp &= ~MII_M1145_HWCFG_MODE_MASK;
1033 temp |= MII_M1145_HWCFG_MODE_SGMII_NO_CLK;
1034 temp |= MII_M1145_HWCFG_FIBER_COPPER_AUTO;
1036 return phy_write(phydev, MII_M1145_PHY_EXT_SR, temp);
1039 static int m88e1145_config_init(struct phy_device *phydev)
1043 /* Take care of errata E0 & E1 */
1044 err = phy_write(phydev, 0x1d, 0x001b);
1048 err = phy_write(phydev, 0x1e, 0x418f);
1052 err = phy_write(phydev, 0x1d, 0x0016);
1056 err = phy_write(phydev, 0x1e, 0xa2da);
1060 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
1061 err = m88e1145_config_init_rgmii(phydev);
1066 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1067 err = m88e1145_config_init_sgmii(phydev);
1072 err = marvell_of_reg_init(phydev);
1080 * fiber_lpa_to_ethtool_lpa_t
1081 * @lpa: value of the MII_LPA register for fiber link
1083 * A small helper function that translates MII_LPA
1084 * bits to ethtool LP advertisement settings.
1086 static u32 fiber_lpa_to_ethtool_lpa_t(u32 lpa)
1090 if (lpa & LPA_FIBER_1000HALF)
1091 result |= ADVERTISED_1000baseT_Half;
1092 if (lpa & LPA_FIBER_1000FULL)
1093 result |= ADVERTISED_1000baseT_Full;
1099 * marvell_update_link - update link status in real time in @phydev
1100 * @phydev: target phy_device struct
1102 * Description: Update the value in phydev->link to reflect the
1103 * current link value.
1105 static int marvell_update_link(struct phy_device *phydev, int fiber)
1109 /* Use the generic register for copper link, or specific
1110 * register for fiber case
1113 status = phy_read(phydev, MII_M1011_PHY_STATUS);
1117 if ((status & REGISTER_LINK_STATUS) == 0)
1122 return genphy_update_link(phydev);
1128 static int marvell_read_status_page_an(struct phy_device *phydev,
1136 status = phy_read(phydev, MII_M1011_PHY_STATUS);
1140 lpa = phy_read(phydev, MII_LPA);
1144 lpagb = phy_read(phydev, MII_STAT1000);
1148 adv = phy_read(phydev, MII_ADVERTISE);
1154 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
1155 phydev->duplex = DUPLEX_FULL;
1157 phydev->duplex = DUPLEX_HALF;
1159 status = status & MII_M1011_PHY_STATUS_SPD_MASK;
1161 phydev->asym_pause = 0;
1164 case MII_M1011_PHY_STATUS_1000:
1165 phydev->speed = SPEED_1000;
1168 case MII_M1011_PHY_STATUS_100:
1169 phydev->speed = SPEED_100;
1173 phydev->speed = SPEED_10;
1178 phydev->lp_advertising =
1179 mii_stat1000_to_ethtool_lpa_t(lpagb) |
1180 mii_lpa_to_ethtool_lpa_t(lpa);
1182 if (phydev->duplex == DUPLEX_FULL) {
1183 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
1184 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
1187 /* The fiber link is only 1000M capable */
1188 phydev->lp_advertising = fiber_lpa_to_ethtool_lpa_t(lpa);
1190 if (phydev->duplex == DUPLEX_FULL) {
1191 if (!(lpa & LPA_PAUSE_FIBER)) {
1193 phydev->asym_pause = 0;
1194 } else if ((lpa & LPA_PAUSE_ASYM_FIBER)) {
1196 phydev->asym_pause = 1;
1199 phydev->asym_pause = 0;
1206 static int marvell_read_status_page_fixed(struct phy_device *phydev)
1208 int bmcr = phy_read(phydev, MII_BMCR);
1213 if (bmcr & BMCR_FULLDPLX)
1214 phydev->duplex = DUPLEX_FULL;
1216 phydev->duplex = DUPLEX_HALF;
1218 if (bmcr & BMCR_SPEED1000)
1219 phydev->speed = SPEED_1000;
1220 else if (bmcr & BMCR_SPEED100)
1221 phydev->speed = SPEED_100;
1223 phydev->speed = SPEED_10;
1226 phydev->asym_pause = 0;
1227 phydev->lp_advertising = 0;
1232 /* marvell_read_status_page
1235 * Check the link, then figure out the current state
1236 * by comparing what we advertise with what the link partner
1237 * advertises. Start by checking the gigabit possibilities,
1238 * then move on to 10/100.
1240 static int marvell_read_status_page(struct phy_device *phydev, int page)
1245 /* Detect and update the link, but return if there
1248 if (page == MII_M1111_FIBER)
1253 err = marvell_update_link(phydev, fiber);
1257 if (phydev->autoneg == AUTONEG_ENABLE)
1258 err = marvell_read_status_page_an(phydev, fiber);
1260 err = marvell_read_status_page_fixed(phydev);
1265 /* marvell_read_status
1267 * Some Marvell's phys have two modes: fiber and copper.
1268 * Both need status checked.
1270 * First, check the fiber link and status.
1271 * If the fiber link is down, check the copper link and status which
1272 * will be the default value if both link are down.
1274 static int marvell_read_status(struct phy_device *phydev)
1278 /* Check the fiber mode first */
1279 if (phydev->supported & SUPPORTED_FIBRE &&
1280 phydev->interface != PHY_INTERFACE_MODE_SGMII) {
1281 err = marvell_set_page(phydev, MII_M1111_FIBER);
1285 err = marvell_read_status_page(phydev, MII_M1111_FIBER);
1289 /* If the fiber link is up, it is the selected and
1290 * used link. In this case, we need to stay in the
1291 * fiber page. Please to be careful about that, avoid
1292 * to restore Copper page in other functions which
1293 * could break the behaviour for some fiber phy like
1299 /* If fiber link is down, check and save copper mode state */
1300 err = marvell_set_page(phydev, MII_M1111_COPPER);
1305 return marvell_read_status_page(phydev, MII_M1111_COPPER);
1308 marvell_set_page(phydev, MII_M1111_COPPER);
1314 * Some Marvell's phys have two modes: fiber and copper.
1315 * Both need to be suspended
1317 static int marvell_suspend(struct phy_device *phydev)
1321 /* Suspend the fiber mode first */
1322 if (!(phydev->supported & SUPPORTED_FIBRE)) {
1323 err = marvell_set_page(phydev, MII_M1111_FIBER);
1327 /* With the page set, use the generic suspend */
1328 err = genphy_suspend(phydev);
1332 /* Then, the copper link */
1333 err = marvell_set_page(phydev, MII_M1111_COPPER);
1338 /* With the page set, use the generic suspend */
1339 return genphy_suspend(phydev);
1342 marvell_set_page(phydev, MII_M1111_COPPER);
1348 * Some Marvell's phys have two modes: fiber and copper.
1349 * Both need to be resumed
1351 static int marvell_resume(struct phy_device *phydev)
1355 /* Resume the fiber mode first */
1356 if (!(phydev->supported & SUPPORTED_FIBRE)) {
1357 err = marvell_set_page(phydev, MII_M1111_FIBER);
1361 /* With the page set, use the generic resume */
1362 err = genphy_resume(phydev);
1366 /* Then, the copper link */
1367 err = marvell_set_page(phydev, MII_M1111_COPPER);
1372 /* With the page set, use the generic resume */
1373 return genphy_resume(phydev);
1376 marvell_set_page(phydev, MII_M1111_COPPER);
1380 static int marvell_aneg_done(struct phy_device *phydev)
1382 int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
1384 return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
1387 static int m88e1121_did_interrupt(struct phy_device *phydev)
1391 imask = phy_read(phydev, MII_M1011_IEVENT);
1393 if (imask & MII_M1011_IMASK_INIT)
1399 static void m88e1318_get_wol(struct phy_device *phydev,
1400 struct ethtool_wolinfo *wol)
1402 wol->supported = WAKE_MAGIC;
1405 if (marvell_set_page(phydev, MII_88E1318S_PHY_WOL_PAGE) < 0)
1408 if (phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL) &
1409 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
1410 wol->wolopts |= WAKE_MAGIC;
1412 if (marvell_set_page(phydev, MII_M1111_COPPER) < 0)
1416 static int m88e1318_set_wol(struct phy_device *phydev,
1417 struct ethtool_wolinfo *wol)
1419 int err, oldpage, temp;
1421 oldpage = marvell_get_page(phydev);
1423 if (wol->wolopts & WAKE_MAGIC) {
1424 /* Explicitly switch to page 0x00, just to be sure */
1425 err = marvell_set_page(phydev, MII_M1111_COPPER);
1429 /* Enable the WOL interrupt */
1430 temp = phy_read(phydev, MII_88E1318S_PHY_CSIER);
1431 temp |= MII_88E1318S_PHY_CSIER_WOL_EIE;
1432 err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp);
1436 err = marvell_set_page(phydev, MII_88E1318S_PHY_LED_PAGE);
1440 /* Setup LED[2] as interrupt pin (active low) */
1441 temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR);
1442 temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT;
1443 temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE;
1444 temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW;
1445 err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp);
1449 err = marvell_set_page(phydev, MII_88E1318S_PHY_WOL_PAGE);
1453 /* Store the device address for the magic packet */
1454 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
1455 ((phydev->attached_dev->dev_addr[5] << 8) |
1456 phydev->attached_dev->dev_addr[4]));
1459 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
1460 ((phydev->attached_dev->dev_addr[3] << 8) |
1461 phydev->attached_dev->dev_addr[2]));
1464 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
1465 ((phydev->attached_dev->dev_addr[1] << 8) |
1466 phydev->attached_dev->dev_addr[0]));
1470 /* Clear WOL status and enable magic packet matching */
1471 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
1472 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
1473 temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
1474 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
1478 err = marvell_set_page(phydev, MII_88E1318S_PHY_WOL_PAGE);
1482 /* Clear WOL status and disable magic packet matching */
1483 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
1484 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
1485 temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
1486 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
1491 err = marvell_set_page(phydev, oldpage);
1498 static int marvell_get_sset_count(struct phy_device *phydev)
1500 if (phydev->supported & SUPPORTED_FIBRE)
1501 return ARRAY_SIZE(marvell_hw_stats);
1503 return ARRAY_SIZE(marvell_hw_stats) - NB_FIBER_STATS;
1506 static void marvell_get_strings(struct phy_device *phydev, u8 *data)
1510 for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++) {
1511 memcpy(data + i * ETH_GSTRING_LEN,
1512 marvell_hw_stats[i].string, ETH_GSTRING_LEN);
1517 #define UINT64_MAX (u64)(~((u64)0))
1519 static u64 marvell_get_stat(struct phy_device *phydev, int i)
1521 struct marvell_hw_stat stat = marvell_hw_stats[i];
1522 struct marvell_priv *priv = phydev->priv;
1523 int err, oldpage, val;
1526 oldpage = marvell_get_page(phydev);
1527 err = marvell_set_page(phydev, stat.page);
1531 val = phy_read(phydev, stat.reg);
1535 val = val & ((1 << stat.bits) - 1);
1536 priv->stats[i] += val;
1537 ret = priv->stats[i];
1540 marvell_set_page(phydev, oldpage);
1545 static void marvell_get_stats(struct phy_device *phydev,
1546 struct ethtool_stats *stats, u64 *data)
1550 for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++)
1551 data[i] = marvell_get_stat(phydev, i);
1555 static int m88e1121_get_temp(struct phy_device *phydev, long *temp)
1562 mutex_lock(&phydev->lock);
1564 ret = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x6);
1568 /* Enable temperature sensor */
1569 ret = phy_read(phydev, MII_88E1121_MISC_TEST);
1573 ret = phy_write(phydev, MII_88E1121_MISC_TEST,
1574 ret | MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
1578 /* Wait for temperature to stabilize */
1579 usleep_range(10000, 12000);
1581 val = phy_read(phydev, MII_88E1121_MISC_TEST);
1587 /* Disable temperature sensor */
1588 ret = phy_write(phydev, MII_88E1121_MISC_TEST,
1589 ret & ~MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
1593 *temp = ((val & MII_88E1121_MISC_TEST_TEMP_MASK) - 5) * 5000;
1596 phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x0);
1597 mutex_unlock(&phydev->lock);
1602 static int m88e1121_hwmon_read(struct device *dev,
1603 enum hwmon_sensor_types type,
1604 u32 attr, int channel, long *temp)
1606 struct phy_device *phydev = dev_get_drvdata(dev);
1610 case hwmon_temp_input:
1611 err = m88e1121_get_temp(phydev, temp);
1620 static umode_t m88e1121_hwmon_is_visible(const void *data,
1621 enum hwmon_sensor_types type,
1622 u32 attr, int channel)
1624 if (type != hwmon_temp)
1628 case hwmon_temp_input:
1635 static u32 m88e1121_hwmon_chip_config[] = {
1636 HWMON_C_REGISTER_TZ,
1640 static const struct hwmon_channel_info m88e1121_hwmon_chip = {
1642 .config = m88e1121_hwmon_chip_config,
1645 static u32 m88e1121_hwmon_temp_config[] = {
1650 static const struct hwmon_channel_info m88e1121_hwmon_temp = {
1652 .config = m88e1121_hwmon_temp_config,
1655 static const struct hwmon_channel_info *m88e1121_hwmon_info[] = {
1656 &m88e1121_hwmon_chip,
1657 &m88e1121_hwmon_temp,
1661 static const struct hwmon_ops m88e1121_hwmon_hwmon_ops = {
1662 .is_visible = m88e1121_hwmon_is_visible,
1663 .read = m88e1121_hwmon_read,
1666 static const struct hwmon_chip_info m88e1121_hwmon_chip_info = {
1667 .ops = &m88e1121_hwmon_hwmon_ops,
1668 .info = m88e1121_hwmon_info,
1671 static int m88e1510_get_temp(struct phy_device *phydev, long *temp)
1677 mutex_lock(&phydev->lock);
1679 ret = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x6);
1683 ret = phy_read(phydev, MII_88E1510_TEMP_SENSOR);
1687 *temp = ((ret & MII_88E1510_TEMP_SENSOR_MASK) - 25) * 1000;
1690 phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x0);
1691 mutex_unlock(&phydev->lock);
1696 int m88e1510_get_temp_critical(struct phy_device *phydev, long *temp)
1702 mutex_lock(&phydev->lock);
1704 ret = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x6);
1708 ret = phy_read(phydev, MII_88E1121_MISC_TEST);
1712 *temp = (((ret & MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK) >>
1713 MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT) * 5) - 25;
1718 phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x0);
1719 mutex_unlock(&phydev->lock);
1724 int m88e1510_set_temp_critical(struct phy_device *phydev, long temp)
1728 mutex_lock(&phydev->lock);
1730 ret = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x6);
1734 ret = phy_read(phydev, MII_88E1121_MISC_TEST);
1739 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
1740 ret = phy_write(phydev, MII_88E1121_MISC_TEST,
1741 (ret & ~MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK) |
1742 (temp << MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT));
1745 phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x0);
1746 mutex_unlock(&phydev->lock);
1751 int m88e1510_get_temp_alarm(struct phy_device *phydev, long *alarm)
1757 mutex_lock(&phydev->lock);
1759 ret = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x6);
1763 ret = phy_read(phydev, MII_88E1121_MISC_TEST);
1766 *alarm = !!(ret & MII_88E1510_MISC_TEST_TEMP_IRQ);
1769 phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE, 0x0);
1770 mutex_unlock(&phydev->lock);
1775 static int m88e1510_hwmon_read(struct device *dev,
1776 enum hwmon_sensor_types type,
1777 u32 attr, int channel, long *temp)
1779 struct phy_device *phydev = dev_get_drvdata(dev);
1783 case hwmon_temp_input:
1784 err = m88e1510_get_temp(phydev, temp);
1786 case hwmon_temp_crit:
1787 err = m88e1510_get_temp_critical(phydev, temp);
1789 case hwmon_temp_max_alarm:
1790 err = m88e1510_get_temp_alarm(phydev, temp);
1799 static int m88e1510_hwmon_write(struct device *dev,
1800 enum hwmon_sensor_types type,
1801 u32 attr, int channel, long temp)
1803 struct phy_device *phydev = dev_get_drvdata(dev);
1807 case hwmon_temp_crit:
1808 err = m88e1510_set_temp_critical(phydev, temp);
1816 static umode_t m88e1510_hwmon_is_visible(const void *data,
1817 enum hwmon_sensor_types type,
1818 u32 attr, int channel)
1820 if (type != hwmon_temp)
1824 case hwmon_temp_input:
1825 case hwmon_temp_max_alarm:
1827 case hwmon_temp_crit:
1834 static u32 m88e1510_hwmon_temp_config[] = {
1835 HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_MAX_ALARM,
1839 static const struct hwmon_channel_info m88e1510_hwmon_temp = {
1841 .config = m88e1510_hwmon_temp_config,
1844 static const struct hwmon_channel_info *m88e1510_hwmon_info[] = {
1845 &m88e1121_hwmon_chip,
1846 &m88e1510_hwmon_temp,
1850 static const struct hwmon_ops m88e1510_hwmon_hwmon_ops = {
1851 .is_visible = m88e1510_hwmon_is_visible,
1852 .read = m88e1510_hwmon_read,
1853 .write = m88e1510_hwmon_write,
1856 static const struct hwmon_chip_info m88e1510_hwmon_chip_info = {
1857 .ops = &m88e1510_hwmon_hwmon_ops,
1858 .info = m88e1510_hwmon_info,
1861 static int marvell_hwmon_name(struct phy_device *phydev)
1863 struct marvell_priv *priv = phydev->priv;
1864 struct device *dev = &phydev->mdio.dev;
1865 const char *devname = dev_name(dev);
1866 size_t len = strlen(devname);
1869 priv->hwmon_name = devm_kzalloc(dev, len, GFP_KERNEL);
1870 if (!priv->hwmon_name)
1873 for (i = j = 0; i < len && devname[i]; i++) {
1874 if (isalnum(devname[i]))
1875 priv->hwmon_name[j++] = devname[i];
1881 static int marvell_hwmon_probe(struct phy_device *phydev,
1882 const struct hwmon_chip_info *chip)
1884 struct marvell_priv *priv = phydev->priv;
1885 struct device *dev = &phydev->mdio.dev;
1888 err = marvell_hwmon_name(phydev);
1892 priv->hwmon_dev = devm_hwmon_device_register_with_info(
1893 dev, priv->hwmon_name, phydev, chip, NULL);
1895 return PTR_ERR_OR_ZERO(priv->hwmon_dev);
1898 static int m88e1121_hwmon_probe(struct phy_device *phydev)
1900 return marvell_hwmon_probe(phydev, &m88e1121_hwmon_chip_info);
1903 static int m88e1510_hwmon_probe(struct phy_device *phydev)
1905 return marvell_hwmon_probe(phydev, &m88e1510_hwmon_chip_info);
1908 static int m88e1121_hwmon_probe(struct phy_device *phydev)
1913 static int m88e1510_hwmon_probe(struct phy_device *phydev)
1919 static int marvell_probe(struct phy_device *phydev)
1921 struct marvell_priv *priv;
1923 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
1927 phydev->priv = priv;
1932 static int m88e1121_probe(struct phy_device *phydev)
1936 err = marvell_probe(phydev);
1940 return m88e1121_hwmon_probe(phydev);
1943 static int m88e1510_probe(struct phy_device *phydev)
1947 err = marvell_probe(phydev);
1951 return m88e1510_hwmon_probe(phydev);
1954 static struct phy_driver marvell_drivers[] = {
1956 .phy_id = MARVELL_PHY_ID_88E1101,
1957 .phy_id_mask = MARVELL_PHY_ID_MASK,
1958 .name = "Marvell 88E1101",
1959 .features = PHY_GBIT_FEATURES,
1960 .flags = PHY_HAS_INTERRUPT,
1961 .probe = marvell_probe,
1962 .config_init = &marvell_config_init,
1963 .config_aneg = &marvell_config_aneg,
1964 .read_status = &genphy_read_status,
1965 .ack_interrupt = &marvell_ack_interrupt,
1966 .config_intr = &marvell_config_intr,
1967 .resume = &genphy_resume,
1968 .suspend = &genphy_suspend,
1969 .get_sset_count = marvell_get_sset_count,
1970 .get_strings = marvell_get_strings,
1971 .get_stats = marvell_get_stats,
1974 .phy_id = MARVELL_PHY_ID_88E1112,
1975 .phy_id_mask = MARVELL_PHY_ID_MASK,
1976 .name = "Marvell 88E1112",
1977 .features = PHY_GBIT_FEATURES,
1978 .flags = PHY_HAS_INTERRUPT,
1979 .probe = marvell_probe,
1980 .config_init = &m88e1111_config_init,
1981 .config_aneg = &marvell_config_aneg,
1982 .read_status = &genphy_read_status,
1983 .ack_interrupt = &marvell_ack_interrupt,
1984 .config_intr = &marvell_config_intr,
1985 .resume = &genphy_resume,
1986 .suspend = &genphy_suspend,
1987 .get_sset_count = marvell_get_sset_count,
1988 .get_strings = marvell_get_strings,
1989 .get_stats = marvell_get_stats,
1992 .phy_id = MARVELL_PHY_ID_88E1111,
1993 .phy_id_mask = MARVELL_PHY_ID_MASK,
1994 .name = "Marvell 88E1111",
1995 .features = PHY_GBIT_FEATURES,
1996 .flags = PHY_HAS_INTERRUPT,
1997 .probe = marvell_probe,
1998 .config_init = &m88e1111_config_init,
1999 .config_aneg = &m88e1111_config_aneg,
2000 .read_status = &marvell_read_status,
2001 .ack_interrupt = &marvell_ack_interrupt,
2002 .config_intr = &marvell_config_intr,
2003 .resume = &genphy_resume,
2004 .suspend = &genphy_suspend,
2005 .get_sset_count = marvell_get_sset_count,
2006 .get_strings = marvell_get_strings,
2007 .get_stats = marvell_get_stats,
2010 .phy_id = MARVELL_PHY_ID_88E1118,
2011 .phy_id_mask = MARVELL_PHY_ID_MASK,
2012 .name = "Marvell 88E1118",
2013 .features = PHY_GBIT_FEATURES,
2014 .flags = PHY_HAS_INTERRUPT,
2015 .probe = marvell_probe,
2016 .config_init = &m88e1118_config_init,
2017 .config_aneg = &m88e1118_config_aneg,
2018 .read_status = &genphy_read_status,
2019 .ack_interrupt = &marvell_ack_interrupt,
2020 .config_intr = &marvell_config_intr,
2021 .resume = &genphy_resume,
2022 .suspend = &genphy_suspend,
2023 .get_sset_count = marvell_get_sset_count,
2024 .get_strings = marvell_get_strings,
2025 .get_stats = marvell_get_stats,
2028 .phy_id = MARVELL_PHY_ID_88E1121R,
2029 .phy_id_mask = MARVELL_PHY_ID_MASK,
2030 .name = "Marvell 88E1121R",
2031 .features = PHY_GBIT_FEATURES,
2032 .flags = PHY_HAS_INTERRUPT,
2033 .probe = &m88e1121_probe,
2034 .config_init = &m88e1121_config_init,
2035 .config_aneg = &m88e1121_config_aneg,
2036 .read_status = &marvell_read_status,
2037 .ack_interrupt = &marvell_ack_interrupt,
2038 .config_intr = &marvell_config_intr,
2039 .did_interrupt = &m88e1121_did_interrupt,
2040 .resume = &genphy_resume,
2041 .suspend = &genphy_suspend,
2042 .get_sset_count = marvell_get_sset_count,
2043 .get_strings = marvell_get_strings,
2044 .get_stats = marvell_get_stats,
2047 .phy_id = MARVELL_PHY_ID_88E1318S,
2048 .phy_id_mask = MARVELL_PHY_ID_MASK,
2049 .name = "Marvell 88E1318S",
2050 .features = PHY_GBIT_FEATURES,
2051 .flags = PHY_HAS_INTERRUPT,
2052 .probe = marvell_probe,
2053 .config_init = &m88e1121_config_init,
2054 .config_aneg = &m88e1318_config_aneg,
2055 .read_status = &marvell_read_status,
2056 .ack_interrupt = &marvell_ack_interrupt,
2057 .config_intr = &marvell_config_intr,
2058 .did_interrupt = &m88e1121_did_interrupt,
2059 .get_wol = &m88e1318_get_wol,
2060 .set_wol = &m88e1318_set_wol,
2061 .resume = &genphy_resume,
2062 .suspend = &genphy_suspend,
2063 .get_sset_count = marvell_get_sset_count,
2064 .get_strings = marvell_get_strings,
2065 .get_stats = marvell_get_stats,
2068 .phy_id = MARVELL_PHY_ID_88E1145,
2069 .phy_id_mask = MARVELL_PHY_ID_MASK,
2070 .name = "Marvell 88E1145",
2071 .features = PHY_GBIT_FEATURES,
2072 .flags = PHY_HAS_INTERRUPT,
2073 .probe = marvell_probe,
2074 .config_init = &m88e1145_config_init,
2075 .config_aneg = &marvell_config_aneg,
2076 .read_status = &genphy_read_status,
2077 .ack_interrupt = &marvell_ack_interrupt,
2078 .config_intr = &marvell_config_intr,
2079 .resume = &genphy_resume,
2080 .suspend = &genphy_suspend,
2081 .get_sset_count = marvell_get_sset_count,
2082 .get_strings = marvell_get_strings,
2083 .get_stats = marvell_get_stats,
2086 .phy_id = MARVELL_PHY_ID_88E1149R,
2087 .phy_id_mask = MARVELL_PHY_ID_MASK,
2088 .name = "Marvell 88E1149R",
2089 .features = PHY_GBIT_FEATURES,
2090 .flags = PHY_HAS_INTERRUPT,
2091 .probe = marvell_probe,
2092 .config_init = &m88e1149_config_init,
2093 .config_aneg = &m88e1118_config_aneg,
2094 .read_status = &genphy_read_status,
2095 .ack_interrupt = &marvell_ack_interrupt,
2096 .config_intr = &marvell_config_intr,
2097 .resume = &genphy_resume,
2098 .suspend = &genphy_suspend,
2099 .get_sset_count = marvell_get_sset_count,
2100 .get_strings = marvell_get_strings,
2101 .get_stats = marvell_get_stats,
2104 .phy_id = MARVELL_PHY_ID_88E1240,
2105 .phy_id_mask = MARVELL_PHY_ID_MASK,
2106 .name = "Marvell 88E1240",
2107 .features = PHY_GBIT_FEATURES,
2108 .flags = PHY_HAS_INTERRUPT,
2109 .probe = marvell_probe,
2110 .config_init = &m88e1111_config_init,
2111 .config_aneg = &marvell_config_aneg,
2112 .read_status = &genphy_read_status,
2113 .ack_interrupt = &marvell_ack_interrupt,
2114 .config_intr = &marvell_config_intr,
2115 .resume = &genphy_resume,
2116 .suspend = &genphy_suspend,
2117 .get_sset_count = marvell_get_sset_count,
2118 .get_strings = marvell_get_strings,
2119 .get_stats = marvell_get_stats,
2122 .phy_id = MARVELL_PHY_ID_88E1116R,
2123 .phy_id_mask = MARVELL_PHY_ID_MASK,
2124 .name = "Marvell 88E1116R",
2125 .features = PHY_GBIT_FEATURES,
2126 .flags = PHY_HAS_INTERRUPT,
2127 .probe = marvell_probe,
2128 .config_init = &m88e1116r_config_init,
2129 .config_aneg = &genphy_config_aneg,
2130 .read_status = &genphy_read_status,
2131 .ack_interrupt = &marvell_ack_interrupt,
2132 .config_intr = &marvell_config_intr,
2133 .resume = &genphy_resume,
2134 .suspend = &genphy_suspend,
2135 .get_sset_count = marvell_get_sset_count,
2136 .get_strings = marvell_get_strings,
2137 .get_stats = marvell_get_stats,
2140 .phy_id = MARVELL_PHY_ID_88E1510,
2141 .phy_id_mask = MARVELL_PHY_ID_MASK,
2142 .name = "Marvell 88E1510",
2143 .features = PHY_GBIT_FEATURES | SUPPORTED_FIBRE,
2144 .flags = PHY_HAS_INTERRUPT,
2145 .probe = &m88e1510_probe,
2146 .config_init = &m88e1510_config_init,
2147 .config_aneg = &m88e1510_config_aneg,
2148 .read_status = &marvell_read_status,
2149 .ack_interrupt = &marvell_ack_interrupt,
2150 .config_intr = &marvell_config_intr,
2151 .did_interrupt = &m88e1121_did_interrupt,
2152 .get_wol = &m88e1318_get_wol,
2153 .set_wol = &m88e1318_set_wol,
2154 .resume = &marvell_resume,
2155 .suspend = &marvell_suspend,
2156 .get_sset_count = marvell_get_sset_count,
2157 .get_strings = marvell_get_strings,
2158 .get_stats = marvell_get_stats,
2161 .phy_id = MARVELL_PHY_ID_88E1540,
2162 .phy_id_mask = MARVELL_PHY_ID_MASK,
2163 .name = "Marvell 88E1540",
2164 .features = PHY_GBIT_FEATURES,
2165 .flags = PHY_HAS_INTERRUPT,
2166 .probe = m88e1510_probe,
2167 .config_init = &marvell_config_init,
2168 .config_aneg = &m88e1510_config_aneg,
2169 .read_status = &marvell_read_status,
2170 .ack_interrupt = &marvell_ack_interrupt,
2171 .config_intr = &marvell_config_intr,
2172 .did_interrupt = &m88e1121_did_interrupt,
2173 .resume = &genphy_resume,
2174 .suspend = &genphy_suspend,
2175 .get_sset_count = marvell_get_sset_count,
2176 .get_strings = marvell_get_strings,
2177 .get_stats = marvell_get_stats,
2180 .phy_id = MARVELL_PHY_ID_88E1545,
2181 .phy_id_mask = MARVELL_PHY_ID_MASK,
2182 .name = "Marvell 88E1545",
2183 .probe = m88e1510_probe,
2184 .features = PHY_GBIT_FEATURES,
2185 .flags = PHY_HAS_INTERRUPT,
2186 .config_init = &marvell_config_init,
2187 .config_aneg = &m88e1510_config_aneg,
2188 .read_status = &marvell_read_status,
2189 .ack_interrupt = &marvell_ack_interrupt,
2190 .config_intr = &marvell_config_intr,
2191 .did_interrupt = &m88e1121_did_interrupt,
2192 .resume = &genphy_resume,
2193 .suspend = &genphy_suspend,
2194 .get_sset_count = marvell_get_sset_count,
2195 .get_strings = marvell_get_strings,
2196 .get_stats = marvell_get_stats,
2199 .phy_id = MARVELL_PHY_ID_88E3016,
2200 .phy_id_mask = MARVELL_PHY_ID_MASK,
2201 .name = "Marvell 88E3016",
2202 .features = PHY_BASIC_FEATURES,
2203 .flags = PHY_HAS_INTERRUPT,
2204 .probe = marvell_probe,
2205 .config_aneg = &genphy_config_aneg,
2206 .config_init = &m88e3016_config_init,
2207 .aneg_done = &marvell_aneg_done,
2208 .read_status = &marvell_read_status,
2209 .ack_interrupt = &marvell_ack_interrupt,
2210 .config_intr = &marvell_config_intr,
2211 .did_interrupt = &m88e1121_did_interrupt,
2212 .resume = &genphy_resume,
2213 .suspend = &genphy_suspend,
2214 .get_sset_count = marvell_get_sset_count,
2215 .get_strings = marvell_get_strings,
2216 .get_stats = marvell_get_stats,
2219 .phy_id = MARVELL_PHY_ID_88E6390,
2220 .phy_id_mask = MARVELL_PHY_ID_MASK,
2221 .name = "Marvell 88E6390",
2222 .features = PHY_GBIT_FEATURES,
2223 .flags = PHY_HAS_INTERRUPT,
2224 .probe = m88e1510_probe,
2225 .config_init = &marvell_config_init,
2226 .config_aneg = &m88e1510_config_aneg,
2227 .read_status = &marvell_read_status,
2228 .ack_interrupt = &marvell_ack_interrupt,
2229 .config_intr = &marvell_config_intr,
2230 .did_interrupt = &m88e1121_did_interrupt,
2231 .resume = &genphy_resume,
2232 .suspend = &genphy_suspend,
2233 .get_sset_count = marvell_get_sset_count,
2234 .get_strings = marvell_get_strings,
2235 .get_stats = marvell_get_stats,
2239 module_phy_driver(marvell_drivers);
2241 static struct mdio_device_id __maybe_unused marvell_tbl[] = {
2242 { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
2243 { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
2244 { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
2245 { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
2246 { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
2247 { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
2248 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
2249 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
2250 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
2251 { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
2252 { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
2253 { MARVELL_PHY_ID_88E1540, MARVELL_PHY_ID_MASK },
2254 { MARVELL_PHY_ID_88E1545, MARVELL_PHY_ID_MASK },
2255 { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
2256 { MARVELL_PHY_ID_88E6390, MARVELL_PHY_ID_MASK },
2260 MODULE_DEVICE_TABLE(mdio, marvell_tbl);