2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/aer.h>
37 #include <linux/tcp.h>
39 #include <linux/delay.h>
40 #include <linux/workqueue.h>
41 #include <linux/if_vlan.h>
42 #include <linux/prefetch.h>
43 #include <linux/debugfs.h>
44 #include <linux/mii.h>
48 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
49 #define SKY2_VLAN_TAG_USED 1
54 #define DRV_NAME "sky2"
55 #define DRV_VERSION "1.20"
56 #define PFX DRV_NAME " "
59 * The Yukon II chipset takes 64 bit command blocks (called list elements)
60 * that are organized into three (receive, transmit, status) different rings
64 #define RX_LE_SIZE 1024
65 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
66 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
67 #define RX_DEF_PENDING RX_MAX_PENDING
68 #define RX_SKB_ALIGN 8
70 #define TX_RING_SIZE 512
71 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
72 #define TX_MIN_PENDING 64
73 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
75 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
76 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77 #define TX_WATCHDOG (5 * HZ)
78 #define NAPI_WEIGHT 64
79 #define PHY_RETRIES 1000
81 #define SKY2_EEPROM_MAGIC 0x9955aabb
84 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
86 static const u32 default_msg =
87 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
88 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
89 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
91 static int debug = -1; /* defaults above */
92 module_param(debug, int, 0);
93 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
95 static int copybreak __read_mostly = 128;
96 module_param(copybreak, int, 0);
97 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
99 static int disable_msi = 0;
100 module_param(disable_msi, int, 0);
101 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
103 static const struct pci_device_id sky2_id_table[] = {
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
142 MODULE_DEVICE_TABLE(pci, sky2_id_table);
144 /* Avoid conditionals by using array */
145 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
146 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
147 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
149 /* This driver supports yukon2 chipset only */
150 static const char *yukon2_name[] = {
152 "EC Ultra", /* 0xb4 */
153 "Extreme", /* 0xb5 */
159 static void sky2_set_multicast(struct net_device *dev);
161 /* Access to PHY via serial interconnect */
162 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
166 gma_write16(hw, port, GM_SMI_DATA, val);
167 gma_write16(hw, port, GM_SMI_CTRL,
168 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
170 for (i = 0; i < PHY_RETRIES; i++) {
171 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
175 if (!(ctrl & GM_SMI_CT_BUSY))
181 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
185 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
189 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
193 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
194 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
196 for (i = 0; i < PHY_RETRIES; i++) {
197 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
201 if (ctrl & GM_SMI_CT_RD_VAL) {
202 *val = gma_read16(hw, port, GM_SMI_DATA);
209 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
212 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
216 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
219 __gm_phy_read(hw, port, reg, &v);
224 static void sky2_power_on(struct sky2_hw *hw)
226 /* switch power to VCC (WA for VAUX problem) */
227 sky2_write8(hw, B0_POWER_CTRL,
228 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
230 /* disable Core Clock Division, */
231 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
233 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
234 /* enable bits are inverted */
235 sky2_write8(hw, B2_Y2_CLK_GATE,
236 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
237 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
238 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
240 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
242 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
243 struct pci_dev *pdev = hw->pdev;
246 pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
248 pci_read_config_dword(pdev, PCI_DEV_REG4, ®);
249 /* set all bits to 0 except bits 15..12 and 8 */
250 reg &= P_ASPM_CONTROL_MSK;
251 pci_write_config_dword(pdev, PCI_DEV_REG4, reg);
253 pci_read_config_dword(pdev, PCI_DEV_REG5, ®);
254 /* set all bits to 0 except bits 28 & 27 */
255 reg &= P_CTL_TIM_VMAIN_AV_MSK;
256 pci_write_config_dword(pdev, PCI_DEV_REG5, reg);
258 pci_write_config_dword(pdev, PCI_CFG_REG_1, 0);
260 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
261 reg = sky2_read32(hw, B2_GP_IO);
262 reg |= GLB_GPIO_STAT_RACE_DIS;
263 sky2_write32(hw, B2_GP_IO, reg);
265 sky2_read32(hw, B2_GP_IO);
269 static void sky2_power_aux(struct sky2_hw *hw)
271 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
272 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
274 /* enable bits are inverted */
275 sky2_write8(hw, B2_Y2_CLK_GATE,
276 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
277 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
278 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
280 /* switch power to VAUX */
281 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
282 sky2_write8(hw, B0_POWER_CTRL,
283 (PC_VAUX_ENA | PC_VCC_ENA |
284 PC_VAUX_ON | PC_VCC_OFF));
287 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
291 /* disable all GMAC IRQ's */
292 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
294 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
295 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
296 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
297 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
299 reg = gma_read16(hw, port, GM_RX_CTRL);
300 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
301 gma_write16(hw, port, GM_RX_CTRL, reg);
304 /* flow control to advertise bits */
305 static const u16 copper_fc_adv[] = {
307 [FC_TX] = PHY_M_AN_ASP,
308 [FC_RX] = PHY_M_AN_PC,
309 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
312 /* flow control to advertise bits when using 1000BaseX */
313 static const u16 fiber_fc_adv[] = {
314 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
315 [FC_TX] = PHY_M_P_ASYM_MD_X,
316 [FC_RX] = PHY_M_P_SYM_MD_X,
317 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
320 /* flow control to GMA disable bits */
321 static const u16 gm_fc_disable[] = {
322 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
323 [FC_TX] = GM_GPCR_FC_RX_DIS,
324 [FC_RX] = GM_GPCR_FC_TX_DIS,
329 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
331 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
332 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
334 if (sky2->autoneg == AUTONEG_ENABLE &&
335 !(hw->flags & SKY2_HW_NEWER_PHY)) {
336 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
338 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
340 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
342 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
343 if (hw->chip_id == CHIP_ID_YUKON_EC)
344 /* set downshift counter to 3x and enable downshift */
345 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
347 /* set master & slave downshift counter to 1x */
348 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
350 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
353 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
354 if (sky2_is_copper(hw)) {
355 if (!(hw->flags & SKY2_HW_GIGABIT)) {
356 /* enable automatic crossover */
357 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
359 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
360 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
363 /* Enable Class A driver for FE+ A0 */
364 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
365 spec |= PHY_M_FESC_SEL_CL_A;
366 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
369 /* disable energy detect */
370 ctrl &= ~PHY_M_PC_EN_DET_MSK;
372 /* enable automatic crossover */
373 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
375 /* downshift on PHY 88E1112 and 88E1149 is changed */
376 if (sky2->autoneg == AUTONEG_ENABLE
377 && (hw->flags & SKY2_HW_NEWER_PHY)) {
378 /* set downshift counter to 3x and enable downshift */
379 ctrl &= ~PHY_M_PC_DSC_MSK;
380 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
384 /* workaround for deviation #4.88 (CRC errors) */
385 /* disable Automatic Crossover */
387 ctrl &= ~PHY_M_PC_MDIX_MSK;
390 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
392 /* special setup for PHY 88E1112 Fiber */
393 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
394 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
396 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
397 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl &= ~PHY_M_MAC_MD_MSK;
400 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
401 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
403 if (hw->pmd_type == 'P') {
404 /* select page 1 to access Fiber registers */
405 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
407 /* for SFP-module set SIGDET polarity to low */
408 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
409 ctrl |= PHY_M_FIB_SIGD_POL;
410 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
413 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
421 if (sky2->autoneg == AUTONEG_ENABLE) {
422 if (sky2_is_copper(hw)) {
423 if (sky2->advertising & ADVERTISED_1000baseT_Full)
424 ct1000 |= PHY_M_1000C_AFD;
425 if (sky2->advertising & ADVERTISED_1000baseT_Half)
426 ct1000 |= PHY_M_1000C_AHD;
427 if (sky2->advertising & ADVERTISED_100baseT_Full)
428 adv |= PHY_M_AN_100_FD;
429 if (sky2->advertising & ADVERTISED_100baseT_Half)
430 adv |= PHY_M_AN_100_HD;
431 if (sky2->advertising & ADVERTISED_10baseT_Full)
432 adv |= PHY_M_AN_10_FD;
433 if (sky2->advertising & ADVERTISED_10baseT_Half)
434 adv |= PHY_M_AN_10_HD;
436 adv |= copper_fc_adv[sky2->flow_mode];
437 } else { /* special defines for FIBER (88E1040S only) */
438 if (sky2->advertising & ADVERTISED_1000baseT_Full)
439 adv |= PHY_M_AN_1000X_AFD;
440 if (sky2->advertising & ADVERTISED_1000baseT_Half)
441 adv |= PHY_M_AN_1000X_AHD;
443 adv |= fiber_fc_adv[sky2->flow_mode];
446 /* Restart Auto-negotiation */
447 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
449 /* forced speed/duplex settings */
450 ct1000 = PHY_M_1000C_MSE;
452 /* Disable auto update for duplex flow control and speed */
453 reg |= GM_GPCR_AU_ALL_DIS;
455 switch (sky2->speed) {
457 ctrl |= PHY_CT_SP1000;
458 reg |= GM_GPCR_SPEED_1000;
461 ctrl |= PHY_CT_SP100;
462 reg |= GM_GPCR_SPEED_100;
466 if (sky2->duplex == DUPLEX_FULL) {
467 reg |= GM_GPCR_DUP_FULL;
468 ctrl |= PHY_CT_DUP_MD;
469 } else if (sky2->speed < SPEED_1000)
470 sky2->flow_mode = FC_NONE;
473 reg |= gm_fc_disable[sky2->flow_mode];
475 /* Forward pause packets to GMAC? */
476 if (sky2->flow_mode & FC_RX)
477 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
479 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
482 gma_write16(hw, port, GM_GP_CTRL, reg);
484 if (hw->flags & SKY2_HW_GIGABIT)
485 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
487 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
488 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
490 /* Setup Phy LED's */
491 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
494 switch (hw->chip_id) {
495 case CHIP_ID_YUKON_FE:
496 /* on 88E3082 these bits are at 11..9 (shifted left) */
497 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
499 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
501 /* delete ACT LED control bits */
502 ctrl &= ~PHY_M_FELP_LED1_MSK;
503 /* change ACT LED control to blink mode */
504 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
505 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
508 case CHIP_ID_YUKON_FE_P:
509 /* Enable Link Partner Next Page */
510 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
511 ctrl |= PHY_M_PC_ENA_LIP_NP;
513 /* disable Energy Detect and enable scrambler */
514 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
515 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
517 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
518 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
519 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
520 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
522 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
525 case CHIP_ID_YUKON_XL:
526 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
528 /* select page 3 to access LED control register */
529 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
531 /* set LED Function Control register */
532 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
533 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
534 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
535 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
536 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
538 /* set Polarity Control register */
539 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
540 (PHY_M_POLC_LS1_P_MIX(4) |
541 PHY_M_POLC_IS0_P_MIX(4) |
542 PHY_M_POLC_LOS_CTRL(2) |
543 PHY_M_POLC_INIT_CTRL(2) |
544 PHY_M_POLC_STA1_CTRL(2) |
545 PHY_M_POLC_STA0_CTRL(2)));
547 /* restore page register */
548 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
551 case CHIP_ID_YUKON_EC_U:
552 case CHIP_ID_YUKON_EX:
553 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
555 /* select page 3 to access LED control register */
556 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
558 /* set LED Function Control register */
559 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
560 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
561 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
562 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
563 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
565 /* set Blink Rate in LED Timer Control Register */
566 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
567 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
568 /* restore page register */
569 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
573 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
574 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
575 /* turn off the Rx LED (LED_RX) */
576 ledover &= ~PHY_M_LED_MO_RX;
579 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
580 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
581 /* apply fixes in PHY AFE */
582 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
584 /* increase differential signal amplitude in 10BASE-T */
585 gm_phy_write(hw, port, 0x18, 0xaa99);
586 gm_phy_write(hw, port, 0x17, 0x2011);
588 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
589 gm_phy_write(hw, port, 0x18, 0xa204);
590 gm_phy_write(hw, port, 0x17, 0x2002);
592 /* set page register to 0 */
593 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
594 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
595 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
596 /* apply workaround for integrated resistors calibration */
597 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
598 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
599 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
600 /* no effect on Yukon-XL */
601 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
603 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
604 /* turn on 100 Mbps LED (LED_LINK100) */
605 ledover |= PHY_M_LED_MO_100;
609 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
613 /* Enable phy interrupt on auto-negotiation complete (or link up) */
614 if (sky2->autoneg == AUTONEG_ENABLE)
615 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
617 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
620 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
622 struct pci_dev *pdev = hw->pdev;
624 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
625 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
627 pci_read_config_dword(pdev, PCI_DEV_REG1, ®1);
628 /* Turn on/off phy power saving */
630 reg1 &= ~phy_power[port];
632 reg1 |= phy_power[port];
634 if (onoff && hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
635 reg1 |= coma_mode[port];
637 pci_write_config_dword(pdev, PCI_DEV_REG1, reg1);
638 pci_read_config_dword(pdev, PCI_DEV_REG1, ®1);
643 /* Force a renegotiation */
644 static void sky2_phy_reinit(struct sky2_port *sky2)
646 spin_lock_bh(&sky2->phy_lock);
647 sky2_phy_init(sky2->hw, sky2->port);
648 spin_unlock_bh(&sky2->phy_lock);
651 /* Put device in state to listen for Wake On Lan */
652 static void sky2_wol_init(struct sky2_port *sky2)
654 struct sky2_hw *hw = sky2->hw;
655 unsigned port = sky2->port;
656 enum flow_control save_mode;
660 /* Bring hardware out of reset */
661 sky2_write16(hw, B0_CTST, CS_RST_CLR);
662 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
664 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
665 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
668 * sky2_reset will re-enable on resume
670 save_mode = sky2->flow_mode;
671 ctrl = sky2->advertising;
673 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
674 sky2->flow_mode = FC_NONE;
675 sky2_phy_power(hw, port, 1);
676 sky2_phy_reinit(sky2);
678 sky2->flow_mode = save_mode;
679 sky2->advertising = ctrl;
681 /* Set GMAC to no flow control and auto update for speed/duplex */
682 gma_write16(hw, port, GM_GP_CTRL,
683 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
684 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
686 /* Set WOL address */
687 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
688 sky2->netdev->dev_addr, ETH_ALEN);
690 /* Turn on appropriate WOL control bits */
691 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
693 if (sky2->wol & WAKE_PHY)
694 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
696 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
698 if (sky2->wol & WAKE_MAGIC)
699 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
701 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
703 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
704 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
706 /* Turn on legacy PCI-Express PME mode */
707 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1);
708 reg1 |= PCI_Y2_PME_LEGACY;
709 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
712 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
716 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
718 struct net_device *dev = hw->dev[port];
720 if (dev->mtu <= ETH_DATA_LEN)
721 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
722 TX_JUMBO_DIS | TX_STFW_ENA);
724 else if (hw->chip_id != CHIP_ID_YUKON_EC_U)
725 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
726 TX_STFW_ENA | TX_JUMBO_ENA);
728 /* set Tx GMAC FIFO Almost Empty Threshold */
729 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
730 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
732 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
733 TX_JUMBO_ENA | TX_STFW_DIS);
735 /* Can't do offload because of lack of store/forward */
736 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
740 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
742 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
746 const u8 *addr = hw->dev[port]->dev_addr;
748 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
749 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
751 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
753 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
754 /* WA DEV_472 -- looks like crossed wires on port 2 */
755 /* clear GMAC 1 Control reset */
756 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
758 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
759 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
760 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
761 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
762 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
765 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
767 /* Enable Transmit FIFO Underrun */
768 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
770 spin_lock_bh(&sky2->phy_lock);
771 sky2_phy_init(hw, port);
772 spin_unlock_bh(&sky2->phy_lock);
775 reg = gma_read16(hw, port, GM_PHY_ADDR);
776 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
778 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
779 gma_read16(hw, port, i);
780 gma_write16(hw, port, GM_PHY_ADDR, reg);
782 /* transmit control */
783 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
785 /* receive control reg: unicast + multicast + no FCS */
786 gma_write16(hw, port, GM_RX_CTRL,
787 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
789 /* transmit flow control */
790 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
792 /* transmit parameter */
793 gma_write16(hw, port, GM_TX_PARAM,
794 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
795 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
796 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
797 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
799 /* serial mode register */
800 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
801 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
803 if (hw->dev[port]->mtu > ETH_DATA_LEN)
804 reg |= GM_SMOD_JUMBO_ENA;
806 gma_write16(hw, port, GM_SERIAL_MODE, reg);
808 /* virtual address for data */
809 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
811 /* physical address: used for pause frames */
812 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
814 /* ignore counter overflows */
815 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
816 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
817 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
819 /* Configure Rx MAC FIFO */
820 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
821 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
822 if (hw->chip_id == CHIP_ID_YUKON_EX ||
823 hw->chip_id == CHIP_ID_YUKON_FE_P)
824 rx_reg |= GMF_RX_OVER_ON;
826 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
828 /* Flush Rx MAC FIFO on any flow control or error */
829 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
831 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
832 reg = RX_GMF_FL_THR_DEF + 1;
833 /* Another magic mystery workaround from sk98lin */
834 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
835 hw->chip_rev == CHIP_REV_YU_FE2_A0)
837 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
839 /* Configure Tx MAC FIFO */
840 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
841 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
843 /* On chips without ram buffer, pause is controled by MAC level */
844 if (sky2_read8(hw, B2_E_0) == 0) {
845 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
846 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
848 sky2_set_tx_stfwd(hw, port);
853 /* Assign Ram Buffer allocation to queue */
854 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
858 /* convert from K bytes to qwords used for hw register */
861 end = start + space - 1;
863 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
864 sky2_write32(hw, RB_ADDR(q, RB_START), start);
865 sky2_write32(hw, RB_ADDR(q, RB_END), end);
866 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
867 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
869 if (q == Q_R1 || q == Q_R2) {
870 u32 tp = space - space/4;
872 /* On receive queue's set the thresholds
873 * give receiver priority when > 3/4 full
874 * send pause when down to 2K
876 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
877 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
880 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
881 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
883 /* Enable store & forward on Tx queue's because
884 * Tx FIFO is only 1K on Yukon
886 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
889 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
890 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
893 /* Setup Bus Memory Interface */
894 static void sky2_qset(struct sky2_hw *hw, u16 q)
896 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
897 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
898 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
899 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
902 /* Setup prefetch unit registers. This is the interface between
903 * hardware and driver list elements
905 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
908 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
909 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
910 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
911 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
912 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
913 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
915 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
918 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
920 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
922 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
927 static void tx_init(struct sky2_port *sky2)
929 struct sky2_tx_le *le;
931 sky2->tx_prod = sky2->tx_cons = 0;
933 sky2->tx_last_mss = 0;
935 le = get_tx_le(sky2);
937 le->opcode = OP_ADDR64 | HW_OWNER;
941 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
942 struct sky2_tx_le *le)
944 return sky2->tx_ring + (le - sky2->tx_le);
947 /* Update chip's next pointer */
948 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
950 /* Make sure write' to descriptors are complete before we tell hardware */
952 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
954 /* Synchronize I/O on since next processor may write to tail */
959 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
961 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
962 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
967 /* Build description to hardware for one receive segment */
968 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
969 dma_addr_t map, unsigned len)
971 struct sky2_rx_le *le;
972 u32 hi = upper_32_bits(map);
974 if (sky2->rx_addr64 != hi) {
975 le = sky2_next_rx(sky2);
976 le->addr = cpu_to_le32(hi);
977 le->opcode = OP_ADDR64 | HW_OWNER;
978 sky2->rx_addr64 = upper_32_bits(map + len);
981 le = sky2_next_rx(sky2);
982 le->addr = cpu_to_le32((u32) map);
983 le->length = cpu_to_le16(len);
984 le->opcode = op | HW_OWNER;
987 /* Build description to hardware for one possibly fragmented skb */
988 static void sky2_rx_submit(struct sky2_port *sky2,
989 const struct rx_ring_info *re)
993 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
995 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
996 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1000 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1003 struct sk_buff *skb = re->skb;
1006 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1007 pci_unmap_len_set(re, data_size, size);
1009 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1010 re->frag_addr[i] = pci_map_page(pdev,
1011 skb_shinfo(skb)->frags[i].page,
1012 skb_shinfo(skb)->frags[i].page_offset,
1013 skb_shinfo(skb)->frags[i].size,
1014 PCI_DMA_FROMDEVICE);
1017 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1019 struct sk_buff *skb = re->skb;
1022 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1023 PCI_DMA_FROMDEVICE);
1025 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1026 pci_unmap_page(pdev, re->frag_addr[i],
1027 skb_shinfo(skb)->frags[i].size,
1028 PCI_DMA_FROMDEVICE);
1031 /* Tell chip where to start receive checksum.
1032 * Actually has two checksums, but set both same to avoid possible byte
1035 static void rx_set_checksum(struct sky2_port *sky2)
1037 struct sky2_rx_le *le = sky2_next_rx(sky2);
1039 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1041 le->opcode = OP_TCPSTART | HW_OWNER;
1043 sky2_write32(sky2->hw,
1044 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1045 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1049 * The RX Stop command will not work for Yukon-2 if the BMU does not
1050 * reach the end of packet and since we can't make sure that we have
1051 * incoming data, we must reset the BMU while it is not doing a DMA
1052 * transfer. Since it is possible that the RX path is still active,
1053 * the RX RAM buffer will be stopped first, so any possible incoming
1054 * data will not trigger a DMA. After the RAM buffer is stopped, the
1055 * BMU is polled until any DMA in progress is ended and only then it
1058 static void sky2_rx_stop(struct sky2_port *sky2)
1060 struct sky2_hw *hw = sky2->hw;
1061 unsigned rxq = rxqaddr[sky2->port];
1064 /* disable the RAM Buffer receive queue */
1065 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1067 for (i = 0; i < 0xffff; i++)
1068 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1069 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1072 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1073 sky2->netdev->name);
1075 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1077 /* reset the Rx prefetch unit */
1078 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1082 /* Clean out receive buffer area, assumes receiver hardware stopped */
1083 static void sky2_rx_clean(struct sky2_port *sky2)
1087 memset(sky2->rx_le, 0, RX_LE_BYTES);
1088 for (i = 0; i < sky2->rx_pending; i++) {
1089 struct rx_ring_info *re = sky2->rx_ring + i;
1092 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1099 /* Basic MII support */
1100 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1102 struct mii_ioctl_data *data = if_mii(ifr);
1103 struct sky2_port *sky2 = netdev_priv(dev);
1104 struct sky2_hw *hw = sky2->hw;
1105 int err = -EOPNOTSUPP;
1107 if (!netif_running(dev))
1108 return -ENODEV; /* Phy still in reset */
1112 data->phy_id = PHY_ADDR_MARV;
1118 spin_lock_bh(&sky2->phy_lock);
1119 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1120 spin_unlock_bh(&sky2->phy_lock);
1122 data->val_out = val;
1127 if (!capable(CAP_NET_ADMIN))
1130 spin_lock_bh(&sky2->phy_lock);
1131 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1133 spin_unlock_bh(&sky2->phy_lock);
1139 #ifdef SKY2_VLAN_TAG_USED
1140 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1142 struct sky2_port *sky2 = netdev_priv(dev);
1143 struct sky2_hw *hw = sky2->hw;
1144 u16 port = sky2->port;
1146 netif_tx_lock_bh(dev);
1147 napi_disable(&hw->napi);
1151 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1153 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1156 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1158 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1162 napi_enable(&hw->napi);
1163 netif_tx_unlock_bh(dev);
1168 * Allocate an skb for receiving. If the MTU is large enough
1169 * make the skb non-linear with a fragment list of pages.
1171 * It appears the hardware has a bug in the FIFO logic that
1172 * cause it to hang if the FIFO gets overrun and the receive buffer
1173 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1174 * aligned except if slab debugging is enabled.
1176 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1178 struct sk_buff *skb;
1182 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1186 p = (unsigned long) skb->data;
1187 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1189 for (i = 0; i < sky2->rx_nfrags; i++) {
1190 struct page *page = alloc_page(GFP_ATOMIC);
1194 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1204 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1206 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1210 * Allocate and setup receiver buffer pool.
1211 * Normal case this ends up creating one list element for skb
1212 * in the receive ring. Worst case if using large MTU and each
1213 * allocation falls on a different 64 bit region, that results
1214 * in 6 list elements per ring entry.
1215 * One element is used for checksum enable/disable, and one
1216 * extra to avoid wrap.
1218 static int sky2_rx_start(struct sky2_port *sky2)
1220 struct sky2_hw *hw = sky2->hw;
1221 struct rx_ring_info *re;
1222 unsigned rxq = rxqaddr[sky2->port];
1223 unsigned i, size, space, thresh;
1225 sky2->rx_put = sky2->rx_next = 0;
1228 /* On PCI express lowering the watermark gives better performance */
1229 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1230 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1232 /* These chips have no ram buffer?
1233 * MAC Rx RAM Read is controlled by hardware */
1234 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1235 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1236 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1237 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1239 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1241 if (!(hw->flags & SKY2_HW_NEW_LE))
1242 rx_set_checksum(sky2);
1244 /* Space needed for frame data + headers rounded up */
1245 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1247 /* Stopping point for hardware truncation */
1248 thresh = (size - 8) / sizeof(u32);
1250 /* Account for overhead of skb - to avoid order > 0 allocation */
1251 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1252 + sizeof(struct skb_shared_info);
1254 sky2->rx_nfrags = space >> PAGE_SHIFT;
1255 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1257 if (sky2->rx_nfrags != 0) {
1258 /* Compute residue after pages */
1259 space = sky2->rx_nfrags << PAGE_SHIFT;
1266 /* Optimize to handle small packets and headers */
1267 if (size < copybreak)
1269 if (size < ETH_HLEN)
1272 sky2->rx_data_size = size;
1275 for (i = 0; i < sky2->rx_pending; i++) {
1276 re = sky2->rx_ring + i;
1278 re->skb = sky2_rx_alloc(sky2);
1282 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1283 sky2_rx_submit(sky2, re);
1287 * The receiver hangs if it receives frames larger than the
1288 * packet buffer. As a workaround, truncate oversize frames, but
1289 * the register is limited to 9 bits, so if you do frames > 2052
1290 * you better get the MTU right!
1293 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1295 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1296 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1299 /* Tell chip about available buffers */
1300 sky2_rx_update(sky2, rxq);
1303 sky2_rx_clean(sky2);
1307 /* Bring up network interface. */
1308 static int sky2_up(struct net_device *dev)
1310 struct sky2_port *sky2 = netdev_priv(dev);
1311 struct sky2_hw *hw = sky2->hw;
1312 unsigned port = sky2->port;
1314 int cap, err = -ENOMEM;
1315 struct net_device *otherdev = hw->dev[sky2->port^1];
1318 * On dual port PCI-X card, there is an problem where status
1319 * can be received out of order due to split transactions
1321 if (otherdev && netif_running(otherdev) &&
1322 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1325 pci_read_config_word(hw->pdev, cap + PCI_X_CMD, &cmd);
1326 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1327 pci_write_config_word(hw->pdev, cap + PCI_X_CMD, cmd);
1330 if (netif_msg_ifup(sky2))
1331 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1333 netif_carrier_off(dev);
1335 /* must be power of 2 */
1336 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1338 sizeof(struct sky2_tx_le),
1343 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1350 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1354 memset(sky2->rx_le, 0, RX_LE_BYTES);
1356 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1361 sky2_phy_power(hw, port, 1);
1363 sky2_mac_init(hw, port);
1365 /* Register is number of 4K blocks on internal RAM buffer. */
1366 ramsize = sky2_read8(hw, B2_E_0) * 4;
1370 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1372 rxspace = ramsize / 2;
1374 rxspace = 8 + (2*(ramsize - 16))/3;
1376 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1377 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1379 /* Make sure SyncQ is disabled */
1380 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1384 sky2_qset(hw, txqaddr[port]);
1386 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1387 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1388 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1390 /* Set almost empty threshold */
1391 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1392 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1393 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1395 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1398 err = sky2_rx_start(sky2);
1402 /* Enable interrupts from phy/mac for port */
1403 imask = sky2_read32(hw, B0_IMSK);
1404 imask |= portirq_msk[port];
1405 sky2_write32(hw, B0_IMSK, imask);
1411 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1412 sky2->rx_le, sky2->rx_le_map);
1416 pci_free_consistent(hw->pdev,
1417 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1418 sky2->tx_le, sky2->tx_le_map);
1421 kfree(sky2->tx_ring);
1422 kfree(sky2->rx_ring);
1424 sky2->tx_ring = NULL;
1425 sky2->rx_ring = NULL;
1429 /* Modular subtraction in ring */
1430 static inline int tx_dist(unsigned tail, unsigned head)
1432 return (head - tail) & (TX_RING_SIZE - 1);
1435 /* Number of list elements available for next tx */
1436 static inline int tx_avail(const struct sky2_port *sky2)
1438 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1441 /* Estimate of number of transmit list elements required */
1442 static unsigned tx_le_req(const struct sk_buff *skb)
1446 count = sizeof(dma_addr_t) / sizeof(u32);
1447 count += skb_shinfo(skb)->nr_frags * count;
1449 if (skb_is_gso(skb))
1452 if (skb->ip_summed == CHECKSUM_PARTIAL)
1459 * Put one packet in ring for transmit.
1460 * A single packet can generate multiple list elements, and
1461 * the number of ring elements will probably be less than the number
1462 * of list elements used.
1464 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1466 struct sky2_port *sky2 = netdev_priv(dev);
1467 struct sky2_hw *hw = sky2->hw;
1468 struct sky2_tx_le *le = NULL;
1469 struct tx_ring_info *re;
1476 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1477 return NETDEV_TX_BUSY;
1479 if (unlikely(netif_msg_tx_queued(sky2)))
1480 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1481 dev->name, sky2->tx_prod, skb->len);
1483 len = skb_headlen(skb);
1484 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1485 addr64 = upper_32_bits(mapping);
1487 /* Send high bits if changed or crosses boundary */
1488 if (addr64 != sky2->tx_addr64 ||
1489 upper_32_bits(mapping + len) != sky2->tx_addr64) {
1490 le = get_tx_le(sky2);
1491 le->addr = cpu_to_le32(addr64);
1492 le->opcode = OP_ADDR64 | HW_OWNER;
1493 sky2->tx_addr64 = upper_32_bits(mapping + len);
1496 /* Check for TCP Segmentation Offload */
1497 mss = skb_shinfo(skb)->gso_size;
1500 if (!(hw->flags & SKY2_HW_NEW_LE))
1501 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1503 if (mss != sky2->tx_last_mss) {
1504 le = get_tx_le(sky2);
1505 le->addr = cpu_to_le32(mss);
1507 if (hw->flags & SKY2_HW_NEW_LE)
1508 le->opcode = OP_MSS | HW_OWNER;
1510 le->opcode = OP_LRGLEN | HW_OWNER;
1511 sky2->tx_last_mss = mss;
1516 #ifdef SKY2_VLAN_TAG_USED
1517 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1518 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1520 le = get_tx_le(sky2);
1522 le->opcode = OP_VLAN|HW_OWNER;
1524 le->opcode |= OP_VLAN;
1525 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1530 /* Handle TCP checksum offload */
1531 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1532 /* On Yukon EX (some versions) encoding change. */
1533 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1534 ctrl |= CALSUM; /* auto checksum */
1536 const unsigned offset = skb_transport_offset(skb);
1539 tcpsum = offset << 16; /* sum start */
1540 tcpsum |= offset + skb->csum_offset; /* sum write */
1542 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1543 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1546 if (tcpsum != sky2->tx_tcpsum) {
1547 sky2->tx_tcpsum = tcpsum;
1549 le = get_tx_le(sky2);
1550 le->addr = cpu_to_le32(tcpsum);
1551 le->length = 0; /* initial checksum value */
1552 le->ctrl = 1; /* one packet */
1553 le->opcode = OP_TCPLISW | HW_OWNER;
1558 le = get_tx_le(sky2);
1559 le->addr = cpu_to_le32((u32) mapping);
1560 le->length = cpu_to_le16(len);
1562 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1564 re = tx_le_re(sky2, le);
1566 pci_unmap_addr_set(re, mapaddr, mapping);
1567 pci_unmap_len_set(re, maplen, len);
1569 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1570 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1572 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1573 frag->size, PCI_DMA_TODEVICE);
1574 addr64 = upper_32_bits(mapping);
1575 if (addr64 != sky2->tx_addr64) {
1576 le = get_tx_le(sky2);
1577 le->addr = cpu_to_le32(addr64);
1579 le->opcode = OP_ADDR64 | HW_OWNER;
1580 sky2->tx_addr64 = addr64;
1583 le = get_tx_le(sky2);
1584 le->addr = cpu_to_le32((u32) mapping);
1585 le->length = cpu_to_le16(frag->size);
1587 le->opcode = OP_BUFFER | HW_OWNER;
1589 re = tx_le_re(sky2, le);
1591 pci_unmap_addr_set(re, mapaddr, mapping);
1592 pci_unmap_len_set(re, maplen, frag->size);
1597 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1598 netif_stop_queue(dev);
1600 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1602 dev->trans_start = jiffies;
1603 return NETDEV_TX_OK;
1607 * Free ring elements from starting at tx_cons until "done"
1609 * NB: the hardware will tell us about partial completion of multi-part
1610 * buffers so make sure not to free skb to early.
1612 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1614 struct net_device *dev = sky2->netdev;
1615 struct pci_dev *pdev = sky2->hw->pdev;
1618 BUG_ON(done >= TX_RING_SIZE);
1620 for (idx = sky2->tx_cons; idx != done;
1621 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1622 struct sky2_tx_le *le = sky2->tx_le + idx;
1623 struct tx_ring_info *re = sky2->tx_ring + idx;
1625 switch(le->opcode & ~HW_OWNER) {
1628 pci_unmap_single(pdev,
1629 pci_unmap_addr(re, mapaddr),
1630 pci_unmap_len(re, maplen),
1634 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1635 pci_unmap_len(re, maplen),
1640 if (le->ctrl & EOP) {
1641 if (unlikely(netif_msg_tx_done(sky2)))
1642 printk(KERN_DEBUG "%s: tx done %u\n",
1645 dev->stats.tx_packets++;
1646 dev->stats.tx_bytes += re->skb->len;
1648 dev_kfree_skb_any(re->skb);
1649 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1653 sky2->tx_cons = idx;
1656 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1657 netif_wake_queue(dev);
1660 /* Cleanup all untransmitted buffers, assume transmitter not running */
1661 static void sky2_tx_clean(struct net_device *dev)
1663 struct sky2_port *sky2 = netdev_priv(dev);
1665 netif_tx_lock_bh(dev);
1666 sky2_tx_complete(sky2, sky2->tx_prod);
1667 netif_tx_unlock_bh(dev);
1670 /* Network shutdown */
1671 static int sky2_down(struct net_device *dev)
1673 struct sky2_port *sky2 = netdev_priv(dev);
1674 struct sky2_hw *hw = sky2->hw;
1675 unsigned port = sky2->port;
1679 /* Never really got started! */
1683 if (netif_msg_ifdown(sky2))
1684 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1686 /* Stop more packets from being queued */
1687 netif_stop_queue(dev);
1689 /* Disable port IRQ */
1690 imask = sky2_read32(hw, B0_IMSK);
1691 imask &= ~portirq_msk[port];
1692 sky2_write32(hw, B0_IMSK, imask);
1694 synchronize_irq(hw->pdev->irq);
1696 sky2_gmac_reset(hw, port);
1698 /* Stop transmitter */
1699 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1700 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1702 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1703 RB_RST_SET | RB_DIS_OP_MD);
1705 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1706 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1707 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1709 /* Make sure no packets are pending */
1710 napi_synchronize(&hw->napi);
1712 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1714 /* Workaround shared GMAC reset */
1715 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1716 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1717 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1719 /* Disable Force Sync bit and Enable Alloc bit */
1720 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1721 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1723 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1724 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1725 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1727 /* Reset the PCI FIFO of the async Tx queue */
1728 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1729 BMU_RST_SET | BMU_FIFO_RST);
1731 /* Reset the Tx prefetch units */
1732 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1735 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1739 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1740 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1742 sky2_phy_power(hw, port, 0);
1744 netif_carrier_off(dev);
1746 /* turn off LED's */
1747 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1750 sky2_rx_clean(sky2);
1752 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1753 sky2->rx_le, sky2->rx_le_map);
1754 kfree(sky2->rx_ring);
1756 pci_free_consistent(hw->pdev,
1757 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1758 sky2->tx_le, sky2->tx_le_map);
1759 kfree(sky2->tx_ring);
1764 sky2->rx_ring = NULL;
1765 sky2->tx_ring = NULL;
1770 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1772 if (hw->flags & SKY2_HW_FIBRE_PHY)
1775 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1776 if (aux & PHY_M_PS_SPEED_100)
1782 switch (aux & PHY_M_PS_SPEED_MSK) {
1783 case PHY_M_PS_SPEED_1000:
1785 case PHY_M_PS_SPEED_100:
1792 static void sky2_link_up(struct sky2_port *sky2)
1794 struct sky2_hw *hw = sky2->hw;
1795 unsigned port = sky2->port;
1797 static const char *fc_name[] = {
1805 reg = gma_read16(hw, port, GM_GP_CTRL);
1806 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1807 gma_write16(hw, port, GM_GP_CTRL, reg);
1809 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1811 netif_carrier_on(sky2->netdev);
1813 mod_timer(&hw->watchdog_timer, jiffies + 1);
1815 /* Turn on link LED */
1816 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1817 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1819 if (netif_msg_link(sky2))
1820 printk(KERN_INFO PFX
1821 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1822 sky2->netdev->name, sky2->speed,
1823 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1824 fc_name[sky2->flow_status]);
1827 static void sky2_link_down(struct sky2_port *sky2)
1829 struct sky2_hw *hw = sky2->hw;
1830 unsigned port = sky2->port;
1833 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1835 reg = gma_read16(hw, port, GM_GP_CTRL);
1836 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1837 gma_write16(hw, port, GM_GP_CTRL, reg);
1839 netif_carrier_off(sky2->netdev);
1841 /* Turn on link LED */
1842 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1844 if (netif_msg_link(sky2))
1845 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1847 sky2_phy_init(hw, port);
1850 static enum flow_control sky2_flow(int rx, int tx)
1853 return tx ? FC_BOTH : FC_RX;
1855 return tx ? FC_TX : FC_NONE;
1858 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1860 struct sky2_hw *hw = sky2->hw;
1861 unsigned port = sky2->port;
1864 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1865 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1866 if (lpa & PHY_M_AN_RF) {
1867 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1871 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1872 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1873 sky2->netdev->name);
1877 sky2->speed = sky2_phy_speed(hw, aux);
1878 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1880 /* Since the pause result bits seem to in different positions on
1881 * different chips. look at registers.
1883 if (hw->flags & SKY2_HW_FIBRE_PHY) {
1884 /* Shift for bits in fiber PHY */
1885 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1886 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1888 if (advert & ADVERTISE_1000XPAUSE)
1889 advert |= ADVERTISE_PAUSE_CAP;
1890 if (advert & ADVERTISE_1000XPSE_ASYM)
1891 advert |= ADVERTISE_PAUSE_ASYM;
1892 if (lpa & LPA_1000XPAUSE)
1893 lpa |= LPA_PAUSE_CAP;
1894 if (lpa & LPA_1000XPAUSE_ASYM)
1895 lpa |= LPA_PAUSE_ASYM;
1898 sky2->flow_status = FC_NONE;
1899 if (advert & ADVERTISE_PAUSE_CAP) {
1900 if (lpa & LPA_PAUSE_CAP)
1901 sky2->flow_status = FC_BOTH;
1902 else if (advert & ADVERTISE_PAUSE_ASYM)
1903 sky2->flow_status = FC_RX;
1904 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1905 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1906 sky2->flow_status = FC_TX;
1909 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1910 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1911 sky2->flow_status = FC_NONE;
1913 if (sky2->flow_status & FC_TX)
1914 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1916 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1921 /* Interrupt from PHY */
1922 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1924 struct net_device *dev = hw->dev[port];
1925 struct sky2_port *sky2 = netdev_priv(dev);
1926 u16 istatus, phystat;
1928 if (!netif_running(dev))
1931 spin_lock(&sky2->phy_lock);
1932 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1933 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1935 if (netif_msg_intr(sky2))
1936 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1937 sky2->netdev->name, istatus, phystat);
1939 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1940 if (sky2_autoneg_done(sky2, phystat) == 0)
1945 if (istatus & PHY_M_IS_LSP_CHANGE)
1946 sky2->speed = sky2_phy_speed(hw, phystat);
1948 if (istatus & PHY_M_IS_DUP_CHANGE)
1950 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1952 if (istatus & PHY_M_IS_LST_CHANGE) {
1953 if (phystat & PHY_M_PS_LINK_UP)
1956 sky2_link_down(sky2);
1959 spin_unlock(&sky2->phy_lock);
1962 /* Transmit timeout is only called if we are running, carrier is up
1963 * and tx queue is full (stopped).
1965 static void sky2_tx_timeout(struct net_device *dev)
1967 struct sky2_port *sky2 = netdev_priv(dev);
1968 struct sky2_hw *hw = sky2->hw;
1970 if (netif_msg_timer(sky2))
1971 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1973 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1974 dev->name, sky2->tx_cons, sky2->tx_prod,
1975 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1976 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
1978 /* can't restart safely under softirq */
1979 schedule_work(&hw->restart_work);
1982 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1984 struct sky2_port *sky2 = netdev_priv(dev);
1985 struct sky2_hw *hw = sky2->hw;
1986 unsigned port = sky2->port;
1991 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1994 if (new_mtu > ETH_DATA_LEN &&
1995 (hw->chip_id == CHIP_ID_YUKON_FE ||
1996 hw->chip_id == CHIP_ID_YUKON_FE_P))
1999 if (!netif_running(dev)) {
2004 imask = sky2_read32(hw, B0_IMSK);
2005 sky2_write32(hw, B0_IMSK, 0);
2007 dev->trans_start = jiffies; /* prevent tx timeout */
2008 netif_stop_queue(dev);
2009 napi_disable(&hw->napi);
2011 synchronize_irq(hw->pdev->irq);
2013 if (sky2_read8(hw, B2_E_0) == 0)
2014 sky2_set_tx_stfwd(hw, port);
2016 ctl = gma_read16(hw, port, GM_GP_CTRL);
2017 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2019 sky2_rx_clean(sky2);
2023 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2024 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2026 if (dev->mtu > ETH_DATA_LEN)
2027 mode |= GM_SMOD_JUMBO_ENA;
2029 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2031 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2033 err = sky2_rx_start(sky2);
2034 sky2_write32(hw, B0_IMSK, imask);
2036 napi_enable(&hw->napi);
2041 gma_write16(hw, port, GM_GP_CTRL, ctl);
2043 netif_wake_queue(dev);
2049 /* For small just reuse existing skb for next receive */
2050 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2051 const struct rx_ring_info *re,
2054 struct sk_buff *skb;
2056 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2058 skb_reserve(skb, 2);
2059 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2060 length, PCI_DMA_FROMDEVICE);
2061 skb_copy_from_linear_data(re->skb, skb->data, length);
2062 skb->ip_summed = re->skb->ip_summed;
2063 skb->csum = re->skb->csum;
2064 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2065 length, PCI_DMA_FROMDEVICE);
2066 re->skb->ip_summed = CHECKSUM_NONE;
2067 skb_put(skb, length);
2072 /* Adjust length of skb with fragments to match received data */
2073 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2074 unsigned int length)
2079 /* put header into skb */
2080 size = min(length, hdr_space);
2085 num_frags = skb_shinfo(skb)->nr_frags;
2086 for (i = 0; i < num_frags; i++) {
2087 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2090 /* don't need this page */
2091 __free_page(frag->page);
2092 --skb_shinfo(skb)->nr_frags;
2094 size = min(length, (unsigned) PAGE_SIZE);
2097 skb->data_len += size;
2098 skb->truesize += size;
2105 /* Normal packet - take skb from ring element and put in a new one */
2106 static struct sk_buff *receive_new(struct sky2_port *sky2,
2107 struct rx_ring_info *re,
2108 unsigned int length)
2110 struct sk_buff *skb, *nskb;
2111 unsigned hdr_space = sky2->rx_data_size;
2113 /* Don't be tricky about reusing pages (yet) */
2114 nskb = sky2_rx_alloc(sky2);
2115 if (unlikely(!nskb))
2119 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2121 prefetch(skb->data);
2123 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2125 if (skb_shinfo(skb)->nr_frags)
2126 skb_put_frags(skb, hdr_space, length);
2128 skb_put(skb, length);
2133 * Receive one packet.
2134 * For larger packets, get new buffer.
2136 static struct sk_buff *sky2_receive(struct net_device *dev,
2137 u16 length, u32 status)
2139 struct sky2_port *sky2 = netdev_priv(dev);
2140 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2141 struct sk_buff *skb = NULL;
2142 u16 count = (status & GMR_FS_LEN) >> 16;
2144 #ifdef SKY2_VLAN_TAG_USED
2145 /* Account for vlan tag */
2146 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2150 if (unlikely(netif_msg_rx_status(sky2)))
2151 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2152 dev->name, sky2->rx_next, status, length);
2154 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2155 prefetch(sky2->rx_ring + sky2->rx_next);
2157 /* This chip has hardware problems that generates bogus status.
2158 * So do only marginal checking and expect higher level protocols
2159 * to handle crap frames.
2161 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2162 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2166 if (status & GMR_FS_ANY_ERR)
2169 if (!(status & GMR_FS_RX_OK))
2172 /* if length reported by DMA does not match PHY, packet was truncated */
2173 if (length != count)
2177 if (length < copybreak)
2178 skb = receive_copy(sky2, re, length);
2180 skb = receive_new(sky2, re, length);
2182 sky2_rx_submit(sky2, re);
2187 /* Truncation of overlength packets
2188 causes PHY length to not match MAC length */
2189 ++dev->stats.rx_length_errors;
2190 if (netif_msg_rx_err(sky2) && net_ratelimit())
2191 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2192 dev->name, status, length);
2196 ++dev->stats.rx_errors;
2197 if (status & GMR_FS_RX_FF_OV) {
2198 dev->stats.rx_over_errors++;
2202 if (netif_msg_rx_err(sky2) && net_ratelimit())
2203 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2204 dev->name, status, length);
2206 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2207 dev->stats.rx_length_errors++;
2208 if (status & GMR_FS_FRAGMENT)
2209 dev->stats.rx_frame_errors++;
2210 if (status & GMR_FS_CRC_ERR)
2211 dev->stats.rx_crc_errors++;
2216 /* Transmit complete */
2217 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2219 struct sky2_port *sky2 = netdev_priv(dev);
2221 if (netif_running(dev)) {
2223 sky2_tx_complete(sky2, last);
2224 netif_tx_unlock(dev);
2228 /* Process status response ring */
2229 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2232 unsigned rx[2] = { 0, 0 };
2236 struct sky2_port *sky2;
2237 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2239 struct net_device *dev;
2240 struct sk_buff *skb;
2243 u8 opcode = le->opcode;
2245 if (!(opcode & HW_OWNER))
2248 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2250 port = le->css & CSS_LINK_BIT;
2251 dev = hw->dev[port];
2252 sky2 = netdev_priv(dev);
2253 length = le16_to_cpu(le->length);
2254 status = le32_to_cpu(le->status);
2257 switch (opcode & ~HW_OWNER) {
2260 skb = sky2_receive(dev, length, status);
2261 if (unlikely(!skb)) {
2262 dev->stats.rx_dropped++;
2266 /* This chip reports checksum status differently */
2267 if (hw->flags & SKY2_HW_NEW_LE) {
2268 if (sky2->rx_csum &&
2269 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2270 (le->css & CSS_TCPUDPCSOK))
2271 skb->ip_summed = CHECKSUM_UNNECESSARY;
2273 skb->ip_summed = CHECKSUM_NONE;
2276 skb->protocol = eth_type_trans(skb, dev);
2277 dev->stats.rx_packets++;
2278 dev->stats.rx_bytes += skb->len;
2279 dev->last_rx = jiffies;
2281 #ifdef SKY2_VLAN_TAG_USED
2282 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2283 vlan_hwaccel_receive_skb(skb,
2285 be16_to_cpu(sky2->rx_tag));
2288 netif_receive_skb(skb);
2290 /* Stop after net poll weight */
2291 if (++work_done >= to_do)
2295 #ifdef SKY2_VLAN_TAG_USED
2297 sky2->rx_tag = length;
2301 sky2->rx_tag = length;
2308 /* If this happens then driver assuming wrong format */
2309 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2310 if (net_ratelimit())
2311 printk(KERN_NOTICE "%s: unexpected"
2312 " checksum status\n",
2317 /* Both checksum counters are programmed to start at
2318 * the same offset, so unless there is a problem they
2319 * should match. This failure is an early indication that
2320 * hardware receive checksumming won't work.
2322 if (likely(status >> 16 == (status & 0xffff))) {
2323 skb = sky2->rx_ring[sky2->rx_next].skb;
2324 skb->ip_summed = CHECKSUM_COMPLETE;
2325 skb->csum = status & 0xffff;
2327 printk(KERN_NOTICE PFX "%s: hardware receive "
2328 "checksum problem (status = %#x)\n",
2331 sky2_write32(sky2->hw,
2332 Q_ADDR(rxqaddr[port], Q_CSR),
2338 /* TX index reports status for both ports */
2339 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2340 sky2_tx_done(hw->dev[0], status & 0xfff);
2342 sky2_tx_done(hw->dev[1],
2343 ((status >> 24) & 0xff)
2344 | (u16)(length & 0xf) << 8);
2348 if (net_ratelimit())
2349 printk(KERN_WARNING PFX
2350 "unknown status opcode 0x%x\n", opcode);
2352 } while (hw->st_idx != idx);
2354 /* Fully processed status ring so clear irq */
2355 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2359 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
2362 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
2367 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2369 struct net_device *dev = hw->dev[port];
2371 if (net_ratelimit())
2372 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2375 if (status & Y2_IS_PAR_RD1) {
2376 if (net_ratelimit())
2377 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2380 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2383 if (status & Y2_IS_PAR_WR1) {
2384 if (net_ratelimit())
2385 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2388 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2391 if (status & Y2_IS_PAR_MAC1) {
2392 if (net_ratelimit())
2393 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2394 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2397 if (status & Y2_IS_PAR_RX1) {
2398 if (net_ratelimit())
2399 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2400 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2403 if (status & Y2_IS_TCP_TXA1) {
2404 if (net_ratelimit())
2405 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2407 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2411 static void sky2_hw_intr(struct sky2_hw *hw)
2413 struct pci_dev *pdev = hw->pdev;
2414 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2415 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2419 if (status & Y2_IS_TIST_OV)
2420 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2422 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2425 pci_read_config_word(pdev, PCI_STATUS, &pci_err);
2426 if (net_ratelimit())
2427 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2430 pci_write_config_word(pdev, PCI_STATUS,
2431 pci_err | PCI_STATUS_ERROR_BITS);
2434 if (status & Y2_IS_PCI_EXP) {
2435 /* PCI-Express uncorrectable Error occurred */
2436 int aer = pci_find_aer_capability(hw->pdev);
2440 pci_read_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS,
2442 pci_cleanup_aer_uncorrect_error_status(pdev);
2444 /* Either AER not configured, or not working
2445 * because of bad MMCONFIG, so just do recover
2448 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2449 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2453 if (net_ratelimit())
2454 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2458 if (status & Y2_HWE_L1_MASK)
2459 sky2_hw_error(hw, 0, status);
2461 if (status & Y2_HWE_L1_MASK)
2462 sky2_hw_error(hw, 1, status);
2465 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2467 struct net_device *dev = hw->dev[port];
2468 struct sky2_port *sky2 = netdev_priv(dev);
2469 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2471 if (netif_msg_intr(sky2))
2472 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2475 if (status & GM_IS_RX_CO_OV)
2476 gma_read16(hw, port, GM_RX_IRQ_SRC);
2478 if (status & GM_IS_TX_CO_OV)
2479 gma_read16(hw, port, GM_TX_IRQ_SRC);
2481 if (status & GM_IS_RX_FF_OR) {
2482 ++dev->stats.rx_fifo_errors;
2483 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2486 if (status & GM_IS_TX_FF_UR) {
2487 ++dev->stats.tx_fifo_errors;
2488 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2492 /* This should never happen it is a bug. */
2493 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2494 u16 q, unsigned ring_size)
2496 struct net_device *dev = hw->dev[port];
2497 struct sky2_port *sky2 = netdev_priv(dev);
2499 const u64 *le = (q == Q_R1 || q == Q_R2)
2500 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2502 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2503 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2504 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2505 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2507 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2510 static int sky2_rx_hung(struct net_device *dev)
2512 struct sky2_port *sky2 = netdev_priv(dev);
2513 struct sky2_hw *hw = sky2->hw;
2514 unsigned port = sky2->port;
2515 unsigned rxq = rxqaddr[port];
2516 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2517 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2518 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2519 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2521 /* If idle and MAC or PCI is stuck */
2522 if (sky2->check.last == dev->last_rx &&
2523 ((mac_rp == sky2->check.mac_rp &&
2524 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2525 /* Check if the PCI RX hang */
2526 (fifo_rp == sky2->check.fifo_rp &&
2527 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2528 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2529 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2530 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2533 sky2->check.last = dev->last_rx;
2534 sky2->check.mac_rp = mac_rp;
2535 sky2->check.mac_lev = mac_lev;
2536 sky2->check.fifo_rp = fifo_rp;
2537 sky2->check.fifo_lev = fifo_lev;
2542 static void sky2_watchdog(unsigned long arg)
2544 struct sky2_hw *hw = (struct sky2_hw *) arg;
2546 /* Check for lost IRQ once a second */
2547 if (sky2_read32(hw, B0_ISRC)) {
2548 napi_schedule(&hw->napi);
2552 for (i = 0; i < hw->ports; i++) {
2553 struct net_device *dev = hw->dev[i];
2554 if (!netif_running(dev))
2558 /* For chips with Rx FIFO, check if stuck */
2559 if ((hw->flags & SKY2_HW_FIFO_HANG_CHECK) &&
2560 sky2_rx_hung(dev)) {
2561 pr_info(PFX "%s: receiver hang detected\n",
2563 schedule_work(&hw->restart_work);
2572 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2575 /* Hardware/software error handling */
2576 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2578 if (net_ratelimit())
2579 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2581 if (status & Y2_IS_HW_ERR)
2584 if (status & Y2_IS_IRQ_MAC1)
2585 sky2_mac_intr(hw, 0);
2587 if (status & Y2_IS_IRQ_MAC2)
2588 sky2_mac_intr(hw, 1);
2590 if (status & Y2_IS_CHK_RX1)
2591 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2593 if (status & Y2_IS_CHK_RX2)
2594 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2596 if (status & Y2_IS_CHK_TXA1)
2597 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2599 if (status & Y2_IS_CHK_TXA2)
2600 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2603 static int sky2_poll(struct napi_struct *napi, int work_limit)
2605 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2606 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2610 if (unlikely(status & Y2_IS_ERROR))
2611 sky2_err_intr(hw, status);
2613 if (status & Y2_IS_IRQ_PHY1)
2614 sky2_phy_intr(hw, 0);
2616 if (status & Y2_IS_IRQ_PHY2)
2617 sky2_phy_intr(hw, 1);
2619 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2620 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2622 if (work_done >= work_limit)
2626 /* Bug/Errata workaround?
2627 * Need to kick the TX irq moderation timer.
2629 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2630 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2631 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2633 napi_complete(napi);
2634 sky2_read32(hw, B0_Y2_SP_LISR);
2640 static irqreturn_t sky2_intr(int irq, void *dev_id)
2642 struct sky2_hw *hw = dev_id;
2645 /* Reading this mask interrupts as side effect */
2646 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2647 if (status == 0 || status == ~0)
2650 prefetch(&hw->st_le[hw->st_idx]);
2652 napi_schedule(&hw->napi);
2657 #ifdef CONFIG_NET_POLL_CONTROLLER
2658 static void sky2_netpoll(struct net_device *dev)
2660 struct sky2_port *sky2 = netdev_priv(dev);
2662 napi_schedule(&sky2->hw->napi);
2666 /* Chip internal frequency for clock calculations */
2667 static u32 sky2_mhz(const struct sky2_hw *hw)
2669 switch (hw->chip_id) {
2670 case CHIP_ID_YUKON_EC:
2671 case CHIP_ID_YUKON_EC_U:
2672 case CHIP_ID_YUKON_EX:
2675 case CHIP_ID_YUKON_FE:
2678 case CHIP_ID_YUKON_FE_P:
2681 case CHIP_ID_YUKON_XL:
2689 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2691 return sky2_mhz(hw) * us;
2694 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2696 return clk / sky2_mhz(hw);
2700 static int __devinit sky2_init(struct sky2_hw *hw)
2705 /* Enable all clocks and check for bad PCI access */
2706 rc = pci_write_config_dword(hw->pdev, PCI_DEV_REG3, 0);
2710 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2712 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2713 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2715 switch(hw->chip_id) {
2716 case CHIP_ID_YUKON_XL:
2717 hw->flags = SKY2_HW_GIGABIT
2718 | SKY2_HW_NEWER_PHY;
2719 if (hw->chip_rev < 3)
2720 hw->flags |= SKY2_HW_FIFO_HANG_CHECK;
2724 case CHIP_ID_YUKON_EC_U:
2725 hw->flags = SKY2_HW_GIGABIT
2727 | SKY2_HW_ADV_POWER_CTL;
2730 case CHIP_ID_YUKON_EX:
2731 hw->flags = SKY2_HW_GIGABIT
2734 | SKY2_HW_ADV_POWER_CTL;
2736 /* New transmit checksum */
2737 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2738 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2741 case CHIP_ID_YUKON_EC:
2742 /* This rev is really old, and requires untested workarounds */
2743 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2744 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2747 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_FIFO_HANG_CHECK;
2750 case CHIP_ID_YUKON_FE:
2753 case CHIP_ID_YUKON_FE_P:
2754 hw->flags = SKY2_HW_NEWER_PHY
2756 | SKY2_HW_AUTO_TX_SUM
2757 | SKY2_HW_ADV_POWER_CTL;
2760 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2765 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2766 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2767 hw->flags |= SKY2_HW_FIBRE_PHY;
2771 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2772 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2773 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2780 static void sky2_reset(struct sky2_hw *hw)
2782 struct pci_dev *pdev = hw->pdev;
2785 u32 hwe_mask = Y2_HWE_ALL_MASK;
2788 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2789 status = sky2_read16(hw, HCU_CCSR);
2790 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2791 HCU_CCSR_UC_STATE_MSK);
2792 sky2_write16(hw, HCU_CCSR, status);
2794 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2795 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2798 sky2_write8(hw, B0_CTST, CS_RST_SET);
2799 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2801 /* allow writes to PCI config */
2802 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2804 /* clear PCI errors, if any */
2805 pci_read_config_word(pdev, PCI_STATUS, &status);
2806 status |= PCI_STATUS_ERROR_BITS;
2807 pci_write_config_word(pdev, PCI_STATUS, status);
2809 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2811 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2813 if (pci_find_aer_capability(pdev)) {
2814 /* Check for advanced error reporting */
2815 pci_cleanup_aer_uncorrect_error_status(pdev);
2816 pci_cleanup_aer_correct_error_status(pdev);
2818 dev_warn(&pdev->dev,
2819 "PCI Express Advanced Error Reporting"
2820 " not configured or MMCONFIG problem?\n");
2822 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2826 /* If error bit is stuck on ignore it */
2827 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2828 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
2830 else if (pci_enable_pcie_error_reporting(pdev))
2831 hwe_mask |= Y2_IS_PCI_EXP;
2836 for (i = 0; i < hw->ports; i++) {
2837 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2838 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2840 if (hw->chip_id == CHIP_ID_YUKON_EX)
2841 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2842 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2846 /* Clear I2C IRQ noise */
2847 sky2_write32(hw, B2_I2C_IRQ, 1);
2849 /* turn off hardware timer (unused) */
2850 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2851 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2853 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2855 /* Turn off descriptor polling */
2856 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2858 /* Turn off receive timestamp */
2859 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2860 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2862 /* enable the Tx Arbiters */
2863 for (i = 0; i < hw->ports; i++)
2864 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2866 /* Initialize ram interface */
2867 for (i = 0; i < hw->ports; i++) {
2868 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2870 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2871 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2872 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2873 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2874 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2875 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2876 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2877 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2878 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2879 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2880 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2881 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2884 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
2886 for (i = 0; i < hw->ports; i++)
2887 sky2_gmac_reset(hw, i);
2889 memset(hw->st_le, 0, STATUS_LE_BYTES);
2892 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2893 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2895 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2896 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2898 /* Set the list last index */
2899 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2901 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2902 sky2_write8(hw, STAT_FIFO_WM, 16);
2904 /* set Status-FIFO ISR watermark */
2905 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2906 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2908 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2910 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2911 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2912 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2914 /* enable status unit */
2915 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2917 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2918 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2919 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2922 static void sky2_restart(struct work_struct *work)
2924 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2925 struct net_device *dev;
2929 sky2_write32(hw, B0_IMSK, 0);
2930 sky2_read32(hw, B0_IMSK);
2931 napi_disable(&hw->napi);
2933 for (i = 0; i < hw->ports; i++) {
2935 if (netif_running(dev))
2940 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2941 napi_enable(&hw->napi);
2943 for (i = 0; i < hw->ports; i++) {
2945 if (netif_running(dev)) {
2948 printk(KERN_INFO PFX "%s: could not restart %d\n",
2958 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2960 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2963 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2965 const struct sky2_port *sky2 = netdev_priv(dev);
2967 wol->supported = sky2_wol_supported(sky2->hw);
2968 wol->wolopts = sky2->wol;
2971 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2973 struct sky2_port *sky2 = netdev_priv(dev);
2974 struct sky2_hw *hw = sky2->hw;
2976 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2979 sky2->wol = wol->wolopts;
2981 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
2982 hw->chip_id == CHIP_ID_YUKON_EX ||
2983 hw->chip_id == CHIP_ID_YUKON_FE_P)
2984 sky2_write32(hw, B0_CTST, sky2->wol
2985 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2987 if (!netif_running(dev))
2988 sky2_wol_init(sky2);
2992 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2994 if (sky2_is_copper(hw)) {
2995 u32 modes = SUPPORTED_10baseT_Half
2996 | SUPPORTED_10baseT_Full
2997 | SUPPORTED_100baseT_Half
2998 | SUPPORTED_100baseT_Full
2999 | SUPPORTED_Autoneg | SUPPORTED_TP;
3001 if (hw->flags & SKY2_HW_GIGABIT)
3002 modes |= SUPPORTED_1000baseT_Half
3003 | SUPPORTED_1000baseT_Full;
3006 return SUPPORTED_1000baseT_Half
3007 | SUPPORTED_1000baseT_Full
3012 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3014 struct sky2_port *sky2 = netdev_priv(dev);
3015 struct sky2_hw *hw = sky2->hw;
3017 ecmd->transceiver = XCVR_INTERNAL;
3018 ecmd->supported = sky2_supported_modes(hw);
3019 ecmd->phy_address = PHY_ADDR_MARV;
3020 if (sky2_is_copper(hw)) {
3021 ecmd->port = PORT_TP;
3022 ecmd->speed = sky2->speed;
3024 ecmd->speed = SPEED_1000;
3025 ecmd->port = PORT_FIBRE;
3028 ecmd->advertising = sky2->advertising;
3029 ecmd->autoneg = sky2->autoneg;
3030 ecmd->duplex = sky2->duplex;
3034 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3036 struct sky2_port *sky2 = netdev_priv(dev);
3037 const struct sky2_hw *hw = sky2->hw;
3038 u32 supported = sky2_supported_modes(hw);
3040 if (ecmd->autoneg == AUTONEG_ENABLE) {
3041 ecmd->advertising = supported;
3047 switch (ecmd->speed) {
3049 if (ecmd->duplex == DUPLEX_FULL)
3050 setting = SUPPORTED_1000baseT_Full;
3051 else if (ecmd->duplex == DUPLEX_HALF)
3052 setting = SUPPORTED_1000baseT_Half;
3057 if (ecmd->duplex == DUPLEX_FULL)
3058 setting = SUPPORTED_100baseT_Full;
3059 else if (ecmd->duplex == DUPLEX_HALF)
3060 setting = SUPPORTED_100baseT_Half;
3066 if (ecmd->duplex == DUPLEX_FULL)
3067 setting = SUPPORTED_10baseT_Full;
3068 else if (ecmd->duplex == DUPLEX_HALF)
3069 setting = SUPPORTED_10baseT_Half;
3077 if ((setting & supported) == 0)
3080 sky2->speed = ecmd->speed;
3081 sky2->duplex = ecmd->duplex;
3084 sky2->autoneg = ecmd->autoneg;
3085 sky2->advertising = ecmd->advertising;
3087 if (netif_running(dev)) {
3088 sky2_phy_reinit(sky2);
3089 sky2_set_multicast(dev);
3095 static void sky2_get_drvinfo(struct net_device *dev,
3096 struct ethtool_drvinfo *info)
3098 struct sky2_port *sky2 = netdev_priv(dev);
3100 strcpy(info->driver, DRV_NAME);
3101 strcpy(info->version, DRV_VERSION);
3102 strcpy(info->fw_version, "N/A");
3103 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3106 static const struct sky2_stat {
3107 char name[ETH_GSTRING_LEN];
3110 { "tx_bytes", GM_TXO_OK_HI },
3111 { "rx_bytes", GM_RXO_OK_HI },
3112 { "tx_broadcast", GM_TXF_BC_OK },
3113 { "rx_broadcast", GM_RXF_BC_OK },
3114 { "tx_multicast", GM_TXF_MC_OK },
3115 { "rx_multicast", GM_RXF_MC_OK },
3116 { "tx_unicast", GM_TXF_UC_OK },
3117 { "rx_unicast", GM_RXF_UC_OK },
3118 { "tx_mac_pause", GM_TXF_MPAUSE },
3119 { "rx_mac_pause", GM_RXF_MPAUSE },
3120 { "collisions", GM_TXF_COL },
3121 { "late_collision",GM_TXF_LAT_COL },
3122 { "aborted", GM_TXF_ABO_COL },
3123 { "single_collisions", GM_TXF_SNG_COL },
3124 { "multi_collisions", GM_TXF_MUL_COL },
3126 { "rx_short", GM_RXF_SHT },
3127 { "rx_runt", GM_RXE_FRAG },
3128 { "rx_64_byte_packets", GM_RXF_64B },
3129 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3130 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3131 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3132 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3133 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3134 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3135 { "rx_too_long", GM_RXF_LNG_ERR },
3136 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3137 { "rx_jabber", GM_RXF_JAB_PKT },
3138 { "rx_fcs_error", GM_RXF_FCS_ERR },
3140 { "tx_64_byte_packets", GM_TXF_64B },
3141 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3142 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3143 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3144 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3145 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3146 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3147 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3150 static u32 sky2_get_rx_csum(struct net_device *dev)
3152 struct sky2_port *sky2 = netdev_priv(dev);
3154 return sky2->rx_csum;
3157 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3159 struct sky2_port *sky2 = netdev_priv(dev);
3161 sky2->rx_csum = data;
3163 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3164 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3169 static u32 sky2_get_msglevel(struct net_device *netdev)
3171 struct sky2_port *sky2 = netdev_priv(netdev);
3172 return sky2->msg_enable;
3175 static int sky2_nway_reset(struct net_device *dev)
3177 struct sky2_port *sky2 = netdev_priv(dev);
3179 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
3182 sky2_phy_reinit(sky2);
3183 sky2_set_multicast(dev);
3188 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3190 struct sky2_hw *hw = sky2->hw;
3191 unsigned port = sky2->port;
3194 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3195 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3196 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3197 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3199 for (i = 2; i < count; i++)
3200 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3203 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3205 struct sky2_port *sky2 = netdev_priv(netdev);
3206 sky2->msg_enable = value;
3209 static int sky2_get_sset_count(struct net_device *dev, int sset)
3213 return ARRAY_SIZE(sky2_stats);
3219 static void sky2_get_ethtool_stats(struct net_device *dev,
3220 struct ethtool_stats *stats, u64 * data)
3222 struct sky2_port *sky2 = netdev_priv(dev);
3224 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3227 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3231 switch (stringset) {
3233 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3234 memcpy(data + i * ETH_GSTRING_LEN,
3235 sky2_stats[i].name, ETH_GSTRING_LEN);
3240 static int sky2_set_mac_address(struct net_device *dev, void *p)
3242 struct sky2_port *sky2 = netdev_priv(dev);
3243 struct sky2_hw *hw = sky2->hw;
3244 unsigned port = sky2->port;
3245 const struct sockaddr *addr = p;
3247 if (!is_valid_ether_addr(addr->sa_data))
3248 return -EADDRNOTAVAIL;
3250 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3251 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3252 dev->dev_addr, ETH_ALEN);
3253 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3254 dev->dev_addr, ETH_ALEN);
3256 /* virtual address for data */
3257 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3259 /* physical address: used for pause frames */
3260 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3265 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3269 bit = ether_crc(ETH_ALEN, addr) & 63;
3270 filter[bit >> 3] |= 1 << (bit & 7);
3273 static void sky2_set_multicast(struct net_device *dev)
3275 struct sky2_port *sky2 = netdev_priv(dev);
3276 struct sky2_hw *hw = sky2->hw;
3277 unsigned port = sky2->port;
3278 struct dev_mc_list *list = dev->mc_list;
3282 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3284 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3285 memset(filter, 0, sizeof(filter));
3287 reg = gma_read16(hw, port, GM_RX_CTRL);
3288 reg |= GM_RXCR_UCF_ENA;
3290 if (dev->flags & IFF_PROMISC) /* promiscuous */
3291 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3292 else if (dev->flags & IFF_ALLMULTI)
3293 memset(filter, 0xff, sizeof(filter));
3294 else if (dev->mc_count == 0 && !rx_pause)
3295 reg &= ~GM_RXCR_MCF_ENA;
3298 reg |= GM_RXCR_MCF_ENA;
3301 sky2_add_filter(filter, pause_mc_addr);
3303 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3304 sky2_add_filter(filter, list->dmi_addr);
3307 gma_write16(hw, port, GM_MC_ADDR_H1,
3308 (u16) filter[0] | ((u16) filter[1] << 8));
3309 gma_write16(hw, port, GM_MC_ADDR_H2,
3310 (u16) filter[2] | ((u16) filter[3] << 8));
3311 gma_write16(hw, port, GM_MC_ADDR_H3,
3312 (u16) filter[4] | ((u16) filter[5] << 8));
3313 gma_write16(hw, port, GM_MC_ADDR_H4,
3314 (u16) filter[6] | ((u16) filter[7] << 8));
3316 gma_write16(hw, port, GM_RX_CTRL, reg);
3319 /* Can have one global because blinking is controlled by
3320 * ethtool and that is always under RTNL mutex
3322 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
3326 switch (hw->chip_id) {
3327 case CHIP_ID_YUKON_XL:
3328 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3329 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3330 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3331 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3332 PHY_M_LEDC_INIT_CTRL(7) |
3333 PHY_M_LEDC_STA1_CTRL(7) |
3334 PHY_M_LEDC_STA0_CTRL(7))
3337 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3341 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
3342 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3343 on ? PHY_M_LED_ALL : 0);
3347 /* blink LED's for finding board */
3348 static int sky2_phys_id(struct net_device *dev, u32 data)
3350 struct sky2_port *sky2 = netdev_priv(dev);
3351 struct sky2_hw *hw = sky2->hw;
3352 unsigned port = sky2->port;
3353 u16 ledctrl, ledover = 0;
3358 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
3359 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3363 /* save initial values */
3364 spin_lock_bh(&sky2->phy_lock);
3365 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3366 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3367 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3368 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3369 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3371 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3372 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3376 while (!interrupted && ms > 0) {
3377 sky2_led(hw, port, onoff);
3380 spin_unlock_bh(&sky2->phy_lock);
3381 interrupted = msleep_interruptible(250);
3382 spin_lock_bh(&sky2->phy_lock);
3387 /* resume regularly scheduled programming */
3388 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3389 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3390 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3391 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3392 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3394 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3395 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3397 spin_unlock_bh(&sky2->phy_lock);
3402 static void sky2_get_pauseparam(struct net_device *dev,
3403 struct ethtool_pauseparam *ecmd)
3405 struct sky2_port *sky2 = netdev_priv(dev);
3407 switch (sky2->flow_mode) {
3409 ecmd->tx_pause = ecmd->rx_pause = 0;
3412 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3415 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3418 ecmd->tx_pause = ecmd->rx_pause = 1;
3421 ecmd->autoneg = sky2->autoneg;
3424 static int sky2_set_pauseparam(struct net_device *dev,
3425 struct ethtool_pauseparam *ecmd)
3427 struct sky2_port *sky2 = netdev_priv(dev);
3429 sky2->autoneg = ecmd->autoneg;
3430 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3432 if (netif_running(dev))
3433 sky2_phy_reinit(sky2);
3438 static int sky2_get_coalesce(struct net_device *dev,
3439 struct ethtool_coalesce *ecmd)
3441 struct sky2_port *sky2 = netdev_priv(dev);
3442 struct sky2_hw *hw = sky2->hw;
3444 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3445 ecmd->tx_coalesce_usecs = 0;
3447 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3448 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3450 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3452 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3453 ecmd->rx_coalesce_usecs = 0;
3455 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3456 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3458 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3460 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3461 ecmd->rx_coalesce_usecs_irq = 0;
3463 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3464 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3467 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3472 /* Note: this affect both ports */
3473 static int sky2_set_coalesce(struct net_device *dev,
3474 struct ethtool_coalesce *ecmd)
3476 struct sky2_port *sky2 = netdev_priv(dev);
3477 struct sky2_hw *hw = sky2->hw;
3478 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3480 if (ecmd->tx_coalesce_usecs > tmax ||
3481 ecmd->rx_coalesce_usecs > tmax ||
3482 ecmd->rx_coalesce_usecs_irq > tmax)
3485 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3487 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3489 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3492 if (ecmd->tx_coalesce_usecs == 0)
3493 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3495 sky2_write32(hw, STAT_TX_TIMER_INI,
3496 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3497 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3499 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3501 if (ecmd->rx_coalesce_usecs == 0)
3502 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3504 sky2_write32(hw, STAT_LEV_TIMER_INI,
3505 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3506 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3508 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3510 if (ecmd->rx_coalesce_usecs_irq == 0)
3511 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3513 sky2_write32(hw, STAT_ISR_TIMER_INI,
3514 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3515 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3517 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3521 static void sky2_get_ringparam(struct net_device *dev,
3522 struct ethtool_ringparam *ering)
3524 struct sky2_port *sky2 = netdev_priv(dev);
3526 ering->rx_max_pending = RX_MAX_PENDING;
3527 ering->rx_mini_max_pending = 0;
3528 ering->rx_jumbo_max_pending = 0;
3529 ering->tx_max_pending = TX_RING_SIZE - 1;
3531 ering->rx_pending = sky2->rx_pending;
3532 ering->rx_mini_pending = 0;
3533 ering->rx_jumbo_pending = 0;
3534 ering->tx_pending = sky2->tx_pending;
3537 static int sky2_set_ringparam(struct net_device *dev,
3538 struct ethtool_ringparam *ering)
3540 struct sky2_port *sky2 = netdev_priv(dev);
3543 if (ering->rx_pending > RX_MAX_PENDING ||
3544 ering->rx_pending < 8 ||
3545 ering->tx_pending < MAX_SKB_TX_LE ||
3546 ering->tx_pending > TX_RING_SIZE - 1)
3549 if (netif_running(dev))
3552 sky2->rx_pending = ering->rx_pending;
3553 sky2->tx_pending = ering->tx_pending;
3555 if (netif_running(dev)) {
3560 sky2_set_multicast(dev);
3566 static int sky2_get_regs_len(struct net_device *dev)
3572 * Returns copy of control register region
3573 * Note: ethtool_get_regs always provides full size (16k) buffer
3575 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3578 const struct sky2_port *sky2 = netdev_priv(dev);
3579 const void __iomem *io = sky2->hw->regs;
3584 for (b = 0; b < 128; b++) {
3585 /* This complicated switch statement is to make sure and
3586 * only access regions that are unreserved.
3587 * Some blocks are only valid on dual port cards.
3588 * and block 3 has some special diagnostic registers that
3593 /* skip diagnostic ram region */
3594 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3597 /* dual port cards only */
3598 case 5: /* Tx Arbiter 2 */
3600 case 14 ... 15: /* TX2 */
3601 case 17: case 19: /* Ram Buffer 2 */
3602 case 22 ... 23: /* Tx Ram Buffer 2 */
3603 case 25: /* Rx MAC Fifo 1 */
3604 case 27: /* Tx MAC Fifo 2 */
3605 case 31: /* GPHY 2 */
3606 case 40 ... 47: /* Pattern Ram 2 */
3607 case 52: case 54: /* TCP Segmentation 2 */
3608 case 112 ... 116: /* GMAC 2 */
3609 if (sky2->hw->ports == 1)
3612 case 0: /* Control */
3613 case 2: /* Mac address */
3614 case 4: /* Tx Arbiter 1 */
3615 case 7: /* PCI express reg */
3617 case 12 ... 13: /* TX1 */
3618 case 16: case 18:/* Rx Ram Buffer 1 */
3619 case 20 ... 21: /* Tx Ram Buffer 1 */
3620 case 24: /* Rx MAC Fifo 1 */
3621 case 26: /* Tx MAC Fifo 1 */
3622 case 28 ... 29: /* Descriptor and status unit */
3623 case 30: /* GPHY 1*/
3624 case 32 ... 39: /* Pattern Ram 1 */
3625 case 48: case 50: /* TCP Segmentation 1 */
3626 case 56 ... 60: /* PCI space */
3627 case 80 ... 84: /* GMAC 1 */
3628 memcpy_fromio(p, io, 128);
3640 /* In order to do Jumbo packets on these chips, need to turn off the
3641 * transmit store/forward. Therefore checksum offload won't work.
3643 static int no_tx_offload(struct net_device *dev)
3645 const struct sky2_port *sky2 = netdev_priv(dev);
3646 const struct sky2_hw *hw = sky2->hw;
3648 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3651 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3653 if (data && no_tx_offload(dev))
3656 return ethtool_op_set_tx_csum(dev, data);
3660 static int sky2_set_tso(struct net_device *dev, u32 data)
3662 if (data && no_tx_offload(dev))
3665 return ethtool_op_set_tso(dev, data);
3668 static int sky2_get_eeprom_len(struct net_device *dev)
3670 struct sky2_port *sky2 = netdev_priv(dev);
3673 pci_read_config_word(sky2->hw->pdev, PCI_DEV_REG2, ®2);
3674 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3677 static u32 sky2_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
3681 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
3684 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
3685 } while (!(offset & PCI_VPD_ADDR_F));
3687 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
3691 static void sky2_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
3693 pci_write_config_word(pdev, cap + PCI_VPD_DATA, val);
3694 pci_write_config_dword(pdev, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3696 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
3697 } while (offset & PCI_VPD_ADDR_F);
3700 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3703 struct sky2_port *sky2 = netdev_priv(dev);
3704 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3705 int length = eeprom->len;
3706 u16 offset = eeprom->offset;
3711 eeprom->magic = SKY2_EEPROM_MAGIC;
3713 while (length > 0) {
3714 u32 val = sky2_vpd_read(sky2->hw->pdev, cap, offset);
3715 int n = min_t(int, length, sizeof(val));
3717 memcpy(data, &val, n);
3725 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3728 struct sky2_port *sky2 = netdev_priv(dev);
3729 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3730 int length = eeprom->len;
3731 u16 offset = eeprom->offset;
3736 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3739 while (length > 0) {
3741 int n = min_t(int, length, sizeof(val));
3743 if (n < sizeof(val))
3744 val = sky2_vpd_read(sky2->hw->pdev, cap, offset);
3745 memcpy(&val, data, n);
3747 sky2_vpd_write(sky2->hw->pdev, cap, offset, val);
3757 static const struct ethtool_ops sky2_ethtool_ops = {
3758 .get_settings = sky2_get_settings,
3759 .set_settings = sky2_set_settings,
3760 .get_drvinfo = sky2_get_drvinfo,
3761 .get_wol = sky2_get_wol,
3762 .set_wol = sky2_set_wol,
3763 .get_msglevel = sky2_get_msglevel,
3764 .set_msglevel = sky2_set_msglevel,
3765 .nway_reset = sky2_nway_reset,
3766 .get_regs_len = sky2_get_regs_len,
3767 .get_regs = sky2_get_regs,
3768 .get_link = ethtool_op_get_link,
3769 .get_eeprom_len = sky2_get_eeprom_len,
3770 .get_eeprom = sky2_get_eeprom,
3771 .set_eeprom = sky2_set_eeprom,
3772 .set_sg = ethtool_op_set_sg,
3773 .set_tx_csum = sky2_set_tx_csum,
3774 .set_tso = sky2_set_tso,
3775 .get_rx_csum = sky2_get_rx_csum,
3776 .set_rx_csum = sky2_set_rx_csum,
3777 .get_strings = sky2_get_strings,
3778 .get_coalesce = sky2_get_coalesce,
3779 .set_coalesce = sky2_set_coalesce,
3780 .get_ringparam = sky2_get_ringparam,
3781 .set_ringparam = sky2_set_ringparam,
3782 .get_pauseparam = sky2_get_pauseparam,
3783 .set_pauseparam = sky2_set_pauseparam,
3784 .phys_id = sky2_phys_id,
3785 .get_sset_count = sky2_get_sset_count,
3786 .get_ethtool_stats = sky2_get_ethtool_stats,
3789 #ifdef CONFIG_SKY2_DEBUG
3791 static struct dentry *sky2_debug;
3793 static int sky2_debug_show(struct seq_file *seq, void *v)
3795 struct net_device *dev = seq->private;
3796 const struct sky2_port *sky2 = netdev_priv(dev);
3797 struct sky2_hw *hw = sky2->hw;
3798 unsigned port = sky2->port;
3802 if (!netif_running(dev))
3805 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3806 sky2_read32(hw, B0_ISRC),
3807 sky2_read32(hw, B0_IMSK),
3808 sky2_read32(hw, B0_Y2_SP_ICR));
3810 napi_disable(&hw->napi);
3811 last = sky2_read16(hw, STAT_PUT_IDX);
3813 if (hw->st_idx == last)
3814 seq_puts(seq, "Status ring (empty)\n");
3816 seq_puts(seq, "Status ring\n");
3817 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3818 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3819 const struct sky2_status_le *le = hw->st_le + idx;
3820 seq_printf(seq, "[%d] %#x %d %#x\n",
3821 idx, le->opcode, le->length, le->status);
3823 seq_puts(seq, "\n");
3826 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3827 sky2->tx_cons, sky2->tx_prod,
3828 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3829 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3831 /* Dump contents of tx ring */
3833 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3834 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3835 const struct sky2_tx_le *le = sky2->tx_le + idx;
3836 u32 a = le32_to_cpu(le->addr);
3839 seq_printf(seq, "%u:", idx);
3842 switch(le->opcode & ~HW_OWNER) {
3844 seq_printf(seq, " %#x:", a);
3847 seq_printf(seq, " mtu=%d", a);
3850 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3853 seq_printf(seq, " csum=%#x", a);
3856 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3859 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3862 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3865 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3866 a, le16_to_cpu(le->length));
3869 if (le->ctrl & EOP) {
3870 seq_putc(seq, '\n');
3875 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3876 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3877 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3878 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3880 napi_enable(&hw->napi);
3884 static int sky2_debug_open(struct inode *inode, struct file *file)
3886 return single_open(file, sky2_debug_show, inode->i_private);
3889 static const struct file_operations sky2_debug_fops = {
3890 .owner = THIS_MODULE,
3891 .open = sky2_debug_open,
3893 .llseek = seq_lseek,
3894 .release = single_release,
3898 * Use network device events to create/remove/rename
3899 * debugfs file entries
3901 static int sky2_device_event(struct notifier_block *unused,
3902 unsigned long event, void *ptr)
3904 struct net_device *dev = ptr;
3905 struct sky2_port *sky2 = netdev_priv(dev);
3907 if (dev->open != sky2_up || !sky2_debug)
3911 case NETDEV_CHANGENAME:
3912 if (sky2->debugfs) {
3913 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
3914 sky2_debug, dev->name);
3918 case NETDEV_GOING_DOWN:
3919 if (sky2->debugfs) {
3920 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3922 debugfs_remove(sky2->debugfs);
3923 sky2->debugfs = NULL;
3928 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
3931 if (IS_ERR(sky2->debugfs))
3932 sky2->debugfs = NULL;
3938 static struct notifier_block sky2_notifier = {
3939 .notifier_call = sky2_device_event,
3943 static __init void sky2_debug_init(void)
3947 ent = debugfs_create_dir("sky2", NULL);
3948 if (!ent || IS_ERR(ent))
3952 register_netdevice_notifier(&sky2_notifier);
3955 static __exit void sky2_debug_cleanup(void)
3958 unregister_netdevice_notifier(&sky2_notifier);
3959 debugfs_remove(sky2_debug);
3965 #define sky2_debug_init()
3966 #define sky2_debug_cleanup()
3970 /* Initialize network device */
3971 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3973 int highmem, int wol)
3975 struct sky2_port *sky2;
3976 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3979 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
3983 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3984 dev->irq = hw->pdev->irq;
3985 dev->open = sky2_up;
3986 dev->stop = sky2_down;
3987 dev->do_ioctl = sky2_ioctl;
3988 dev->hard_start_xmit = sky2_xmit_frame;
3989 dev->set_multicast_list = sky2_set_multicast;
3990 dev->set_mac_address = sky2_set_mac_address;
3991 dev->change_mtu = sky2_change_mtu;
3992 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3993 dev->tx_timeout = sky2_tx_timeout;
3994 dev->watchdog_timeo = TX_WATCHDOG;
3995 #ifdef CONFIG_NET_POLL_CONTROLLER
3997 dev->poll_controller = sky2_netpoll;
4000 sky2 = netdev_priv(dev);
4003 sky2->msg_enable = netif_msg_init(debug, default_msg);
4005 /* Auto speed and flow control */
4006 sky2->autoneg = AUTONEG_ENABLE;
4007 sky2->flow_mode = FC_BOTH;
4011 sky2->advertising = sky2_supported_modes(hw);
4012 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
4015 spin_lock_init(&sky2->phy_lock);
4016 sky2->tx_pending = TX_DEF_PENDING;
4017 sky2->rx_pending = RX_DEF_PENDING;
4019 hw->dev[port] = dev;
4023 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4025 dev->features |= NETIF_F_HIGHDMA;
4027 #ifdef SKY2_VLAN_TAG_USED
4028 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4029 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4030 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4031 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4032 dev->vlan_rx_register = sky2_vlan_rx_register;
4036 /* read the mac address */
4037 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4038 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4043 static void __devinit sky2_show_addr(struct net_device *dev)
4045 const struct sky2_port *sky2 = netdev_priv(dev);
4046 DECLARE_MAC_BUF(mac);
4048 if (netif_msg_probe(sky2))
4049 printk(KERN_INFO PFX "%s: addr %s\n",
4050 dev->name, print_mac(mac, dev->dev_addr));
4053 /* Handle software interrupt used during MSI test */
4054 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4056 struct sky2_hw *hw = dev_id;
4057 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4062 if (status & Y2_IS_IRQ_SW) {
4063 hw->flags |= SKY2_HW_USE_MSI;
4064 wake_up(&hw->msi_wait);
4065 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4067 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4072 /* Test interrupt path by forcing a a software IRQ */
4073 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4075 struct pci_dev *pdev = hw->pdev;
4078 init_waitqueue_head (&hw->msi_wait);
4080 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4082 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4084 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4088 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4089 sky2_read8(hw, B0_CTST);
4091 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4093 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4094 /* MSI test failed, go back to INTx mode */
4095 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4096 "switching to INTx mode.\n");
4099 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4102 sky2_write32(hw, B0_IMSK, 0);
4103 sky2_read32(hw, B0_IMSK);
4105 free_irq(pdev->irq, hw);
4110 static int __devinit pci_wake_enabled(struct pci_dev *dev)
4112 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4117 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4119 return value & PCI_PM_CTRL_PME_ENABLE;
4122 static int __devinit sky2_probe(struct pci_dev *pdev,
4123 const struct pci_device_id *ent)
4125 struct net_device *dev;
4127 int err, using_dac = 0, wol_default;
4129 err = pci_enable_device(pdev);
4131 dev_err(&pdev->dev, "cannot enable PCI device\n");
4135 err = pci_request_regions(pdev, DRV_NAME);
4137 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4138 goto err_out_disable;
4141 pci_set_master(pdev);
4143 if (sizeof(dma_addr_t) > sizeof(u32) &&
4144 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4146 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4148 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4149 "for consistent allocations\n");
4150 goto err_out_free_regions;
4153 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4155 dev_err(&pdev->dev, "no usable DMA configuration\n");
4156 goto err_out_free_regions;
4160 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4163 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
4165 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4166 goto err_out_free_regions;
4171 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4173 dev_err(&pdev->dev, "cannot map device registers\n");
4174 goto err_out_free_hw;
4178 /* The sk98lin vendor driver uses hardware byte swapping but
4179 * this driver uses software swapping.
4183 pci_read_config_dword(pdev,PCI_DEV_REG2, ®);
4184 reg &= ~PCI_REV_DESC;
4185 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
4189 /* ring for status responses */
4190 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4192 goto err_out_iounmap;
4194 err = sky2_init(hw);
4196 goto err_out_iounmap;
4198 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
4199 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4200 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
4201 hw->chip_id, hw->chip_rev);
4205 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4208 goto err_out_free_pci;
4211 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4212 err = sky2_test_msi(hw);
4213 if (err == -EOPNOTSUPP)
4214 pci_disable_msi(pdev);
4216 goto err_out_free_netdev;
4219 err = register_netdev(dev);
4221 dev_err(&pdev->dev, "cannot register net device\n");
4222 goto err_out_free_netdev;
4225 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4227 err = request_irq(pdev->irq, sky2_intr,
4228 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4231 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4232 goto err_out_unregister;
4234 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4235 napi_enable(&hw->napi);
4237 sky2_show_addr(dev);
4239 if (hw->ports > 1) {
4240 struct net_device *dev1;
4242 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4244 dev_warn(&pdev->dev, "allocation for second device failed\n");
4245 else if ((err = register_netdev(dev1))) {
4246 dev_warn(&pdev->dev,
4247 "register of second port failed (%d)\n", err);
4251 sky2_show_addr(dev1);
4254 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4255 INIT_WORK(&hw->restart_work, sky2_restart);
4257 pci_set_drvdata(pdev, hw);
4262 if (hw->flags & SKY2_HW_USE_MSI)
4263 pci_disable_msi(pdev);
4264 unregister_netdev(dev);
4265 err_out_free_netdev:
4268 sky2_write8(hw, B0_CTST, CS_RST_SET);
4269 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4274 err_out_free_regions:
4275 pci_release_regions(pdev);
4277 pci_disable_device(pdev);
4279 pci_set_drvdata(pdev, NULL);
4283 static void __devexit sky2_remove(struct pci_dev *pdev)
4285 struct sky2_hw *hw = pci_get_drvdata(pdev);
4291 del_timer_sync(&hw->watchdog_timer);
4292 cancel_work_sync(&hw->restart_work);
4294 for (i = hw->ports-1; i >= 0; --i)
4295 unregister_netdev(hw->dev[i]);
4297 sky2_write32(hw, B0_IMSK, 0);
4301 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4302 sky2_write8(hw, B0_CTST, CS_RST_SET);
4303 sky2_read8(hw, B0_CTST);
4305 free_irq(pdev->irq, hw);
4306 if (hw->flags & SKY2_HW_USE_MSI)
4307 pci_disable_msi(pdev);
4308 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4309 pci_release_regions(pdev);
4310 pci_disable_device(pdev);
4312 for (i = hw->ports-1; i >= 0; --i)
4313 free_netdev(hw->dev[i]);
4318 pci_set_drvdata(pdev, NULL);
4322 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4324 struct sky2_hw *hw = pci_get_drvdata(pdev);
4330 for (i = 0; i < hw->ports; i++) {
4331 struct net_device *dev = hw->dev[i];
4332 struct sky2_port *sky2 = netdev_priv(dev);
4334 if (netif_running(dev))
4338 sky2_wol_init(sky2);
4343 sky2_write32(hw, B0_IMSK, 0);
4344 napi_disable(&hw->napi);
4347 pci_save_state(pdev);
4348 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4349 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4354 static int sky2_resume(struct pci_dev *pdev)
4356 struct sky2_hw *hw = pci_get_drvdata(pdev);
4362 err = pci_set_power_state(pdev, PCI_D0);
4366 err = pci_restore_state(pdev);
4370 pci_enable_wake(pdev, PCI_D0, 0);
4372 /* Re-enable all clocks */
4373 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4374 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4375 hw->chip_id == CHIP_ID_YUKON_FE_P)
4376 pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
4379 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4380 napi_enable(&hw->napi);
4382 for (i = 0; i < hw->ports; i++) {
4383 struct net_device *dev = hw->dev[i];
4384 if (netif_running(dev)) {
4387 printk(KERN_ERR PFX "%s: could not up: %d\n",
4393 sky2_set_multicast(dev);
4399 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4400 pci_disable_device(pdev);
4405 static void sky2_shutdown(struct pci_dev *pdev)
4407 struct sky2_hw *hw = pci_get_drvdata(pdev);
4413 del_timer_sync(&hw->watchdog_timer);
4415 for (i = 0; i < hw->ports; i++) {
4416 struct net_device *dev = hw->dev[i];
4417 struct sky2_port *sky2 = netdev_priv(dev);
4421 sky2_wol_init(sky2);
4428 pci_enable_wake(pdev, PCI_D3hot, wol);
4429 pci_enable_wake(pdev, PCI_D3cold, wol);
4431 pci_disable_device(pdev);
4432 pci_set_power_state(pdev, PCI_D3hot);
4436 static struct pci_driver sky2_driver = {
4438 .id_table = sky2_id_table,
4439 .probe = sky2_probe,
4440 .remove = __devexit_p(sky2_remove),
4442 .suspend = sky2_suspend,
4443 .resume = sky2_resume,
4445 .shutdown = sky2_shutdown,
4448 static int __init sky2_init_module(void)
4451 return pci_register_driver(&sky2_driver);
4454 static void __exit sky2_cleanup_module(void)
4456 pci_unregister_driver(&sky2_driver);
4457 sky2_debug_cleanup();
4460 module_init(sky2_init_module);
4461 module_exit(sky2_cleanup_module);
4463 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4464 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4465 MODULE_LICENSE("GPL");
4466 MODULE_VERSION(DRV_VERSION);