drivers/net/ucc_geth.c

   1 /*
   2  * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved.
   3  *
   4  * Author: Shlomi Gridish <gridish@freescale.com>
   5  *         Li Yang <leoli@freescale.com>
   6  *
   7  * Description:
   8  * QE UCC Gigabit Ethernet Driver
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/slab.h>
  19 #include <linux/stddef.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/etherdevice.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/mm.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/mii.h>
  28 #include <linux/phy.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/of_mdio.h>
  31 #include <linux/of_platform.h>
  32
  33 #include <asm/uaccess.h>
  34 #include <asm/irq.h>
  35 #include <asm/io.h>
  36 #include <asm/immap_qe.h>
  37 #include <asm/qe.h>
  38 #include <asm/ucc.h>
  39 #include <asm/ucc_fast.h>
  40
  41 #include "ucc_geth.h"
  42 #include "fsl_pq_mdio.h"
  43
  44 #undef DEBUG
  45
  46 #define ugeth_printk(level, format, arg...)  \
  47         printk(level format "\n", ## arg)
  48
  49 #define ugeth_dbg(format, arg...)            \
  50         ugeth_printk(KERN_DEBUG , format , ## arg)
  51 #define ugeth_err(format, arg...)            \
  52         ugeth_printk(KERN_ERR , format , ## arg)
  53 #define ugeth_info(format, arg...)           \
  54         ugeth_printk(KERN_INFO , format , ## arg)
  55 #define ugeth_warn(format, arg...)           \
  56         ugeth_printk(KERN_WARNING , format , ## arg)
  57
  58 #ifdef UGETH_VERBOSE_DEBUG
  59 #define ugeth_vdbg ugeth_dbg
  60 #else
  61 #define ugeth_vdbg(fmt, args...) do { } while (0)
  62 #endif                          /* UGETH_VERBOSE_DEBUG */
  63 #define UGETH_MSG_DEFAULT       (NETIF_MSG_IFUP << 1 ) - 1
  64
  65
  66 static DEFINE_SPINLOCK(ugeth_lock);
  67
  68 static struct {
  69         u32 msg_enable;
  70 } debug = { -1 };
  71
  72 module_param_named(debug, debug.msg_enable, int, 0);
  73 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)");
  74
  75 static struct ucc_geth_info ugeth_primary_info = {
  76         .uf_info = {
  77                     .bd_mem_part = MEM_PART_SYSTEM,
  78                     .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
  79                     .max_rx_buf_length = 1536,
  80                     /* adjusted at startup if max-speed 1000 */
  81                     .urfs = UCC_GETH_URFS_INIT,
  82                     .urfet = UCC_GETH_URFET_INIT,
  83                     .urfset = UCC_GETH_URFSET_INIT,
  84                     .utfs = UCC_GETH_UTFS_INIT,
  85                     .utfet = UCC_GETH_UTFET_INIT,
  86                     .utftt = UCC_GETH_UTFTT_INIT,
  87                     .ufpt = 256,
  88                     .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
  89                     .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
  90                     .tenc = UCC_FAST_TX_ENCODING_NRZ,
  91                     .renc = UCC_FAST_RX_ENCODING_NRZ,
  92                     .tcrc = UCC_FAST_16_BIT_CRC,
  93                     .synl = UCC_FAST_SYNC_LEN_NOT_USED,
  94                     },
  95         .numQueuesTx = 1,
  96         .numQueuesRx = 1,
  97         .extendedFilteringChainPointer = ((uint32_t) NULL),
  98         .typeorlen = 3072 /*1536 */ ,
  99         .nonBackToBackIfgPart1 = 0x40,
 100         .nonBackToBackIfgPart2 = 0x60,
 101         .miminumInterFrameGapEnforcement = 0x50,
 102         .backToBackInterFrameGap = 0x60,
 103         .mblinterval = 128,
 104         .nortsrbytetime = 5,
 105         .fracsiz = 1,
 106         .strictpriorityq = 0xff,
 107         .altBebTruncation = 0xa,
 108         .excessDefer = 1,
 109         .maxRetransmission = 0xf,
 110         .collisionWindow = 0x37,
 111         .receiveFlowControl = 1,
 112         .transmitFlowControl = 1,
 113         .maxGroupAddrInHash = 4,
 114         .maxIndAddrInHash = 4,
 115         .prel = 7,
 116         .maxFrameLength = 1518,
 117         .minFrameLength = 64,
 118         .maxD1Length = 1520,
 119         .maxD2Length = 1520,
 120         .vlantype = 0x8100,
 121         .ecamptr = ((uint32_t) NULL),
 122         .eventRegMask = UCCE_OTHER,
 123         .pausePeriod = 0xf000,
 124         .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
 125         .bdRingLenTx = {
 126                         TX_BD_RING_LEN,
 127                         TX_BD_RING_LEN,
 128                         TX_BD_RING_LEN,
 129                         TX_BD_RING_LEN,
 130                         TX_BD_RING_LEN,
 131                         TX_BD_RING_LEN,
 132                         TX_BD_RING_LEN,
 133                         TX_BD_RING_LEN},
 134
 135         .bdRingLenRx = {
 136                         RX_BD_RING_LEN,
 137                         RX_BD_RING_LEN,
 138                         RX_BD_RING_LEN,
 139                         RX_BD_RING_LEN,
 140                         RX_BD_RING_LEN,
 141                         RX_BD_RING_LEN,
 142                         RX_BD_RING_LEN,
 143                         RX_BD_RING_LEN},
 144
 145         .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
 146         .largestexternallookupkeysize =
 147             QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
 148         .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE |
 149                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX |
 150                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX,
 151         .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
 152         .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
 153         .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
 154         .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
 155         .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
 156         .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1,
 157         .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1,
 158         .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 159         .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 160 };
 161
 162 static struct ucc_geth_info ugeth_info[8];
 163
 164 #ifdef DEBUG
 165 static void mem_disp(u8 *addr, int size)
 166 {
 167         u8 *i;
 168         int size16Aling = (size >> 4) << 4;
 169         int size4Aling = (size >> 2) << 2;
 170         int notAlign = 0;
 171         if (size % 16)
 172                 notAlign = 1;
 173
 174         for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
 175                 printk("0x%08x: %08x %08x %08x %08x\r\n",
 176                        (u32) i,
 177                        *((u32 *) (i)),
 178                        *((u32 *) (i + 4)),
 179                        *((u32 *) (i + 8)), *((u32 *) (i + 12)));
 180         if (notAlign == 1)
 181                 printk("0x%08x: ", (u32) i);
 182         for (; (u32) i < (u32) addr + size4Aling; i += 4)
 183                 printk("%08x ", *((u32 *) (i)));
 184         for (; (u32) i < (u32) addr + size; i++)
 185                 printk("%02x", *((u8 *) (i)));
 186         if (notAlign == 1)
 187                 printk("\r\n");
 188 }
 189 #endif /* DEBUG */
 190
 191 static struct list_head *dequeue(struct list_head *lh)
 192 {
 193         unsigned long flags;
 194
 195         spin_lock_irqsave(&ugeth_lock, flags);
 196         if (!list_empty(lh)) {
 197                 struct list_head *node = lh->next;
 198                 list_del(node);
 199                 spin_unlock_irqrestore(&ugeth_lock, flags);
 200                 return node;
 201         } else {
 202                 spin_unlock_irqrestore(&ugeth_lock, flags);
 203                 return NULL;
 204         }
 205 }
 206
 207 static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth,
 208                 u8 __iomem *bd)
 209 {
 210         struct sk_buff *skb = NULL;
 211
 212         skb = __skb_dequeue(&ugeth->rx_recycle);
 213         if (!skb)
 214                 skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
 215                                     UCC_GETH_RX_DATA_BUF_ALIGNMENT);
 216         if (skb == NULL)
 217                 return NULL;
 218
 219         /* We need the data buffer to be aligned properly.  We will reserve
 220          * as many bytes as needed to align the data properly
 221          */
 222         skb_reserve(skb,
 223                     UCC_GETH_RX_DATA_BUF_ALIGNMENT -
 224                     (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
 225                                               1)));
 226
 227         skb->dev = ugeth->ndev;
 228
 229         out_be32(&((struct qe_bd __iomem *)bd)->buf,
 230                       dma_map_single(ugeth->dev,
 231                                      skb->data,
 232                                      ugeth->ug_info->uf_info.max_rx_buf_length +
 233                                      UCC_GETH_RX_DATA_BUF_ALIGNMENT,
 234                                      DMA_FROM_DEVICE));
 235
 236         out_be32((u32 __iomem *)bd,
 237                         (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W)));
 238
 239         return skb;
 240 }
 241
 242 static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
 243 {
 244         u8 __iomem *bd;
 245         u32 bd_status;
 246         struct sk_buff *skb;
 247         int i;
 248
 249         bd = ugeth->p_rx_bd_ring[rxQ];
 250         i = 0;
 251
 252         do {
 253                 bd_status = in_be32((u32 __iomem *)bd);
 254                 skb = get_new_skb(ugeth, bd);
 255
 256                 if (!skb)       /* If can not allocate data buffer,
 257                                 abort. Cleanup will be elsewhere */
 258                         return -ENOMEM;
 259
 260                 ugeth->rx_skbuff[rxQ][i] = skb;
 261
 262                 /* advance the BD pointer */
 263                 bd += sizeof(struct qe_bd);
 264                 i++;
 265         } while (!(bd_status & R_W));
 266
 267         return 0;
 268 }
 269
 270 static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
 271                                   u32 *p_start,
 272                                   u8 num_entries,
 273                                   u32 thread_size,
 274                                   u32 thread_alignment,
 275                                   unsigned int risc,
 276                                   int skip_page_for_first_entry)
 277 {
 278         u32 init_enet_offset;
 279         u8 i;
 280         int snum;
 281
 282         for (i = 0; i < num_entries; i++) {
 283                 if ((snum = qe_get_snum()) < 0) {
 284                         if (netif_msg_ifup(ugeth))
 285                                 ugeth_err("fill_init_enet_entries: Can not get SNUM.");
 286                         return snum;
 287                 }
 288                 if ((i == 0) && skip_page_for_first_entry)
 289                 /* First entry of Rx does not have page */
 290                         init_enet_offset = 0;
 291                 else {
 292                         init_enet_offset =
 293                             qe_muram_alloc(thread_size, thread_alignment);
 294                         if (IS_ERR_VALUE(init_enet_offset)) {
 295                                 if (netif_msg_ifup(ugeth))
 296                                         ugeth_err("fill_init_enet_entries: Can not allocate DPRAM memory.");
 297                                 qe_put_snum((u8) snum);
 298                                 return -ENOMEM;
 299                         }
 300                 }
 301                 *(p_start++) =
 302                     ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
 303                     | risc;
 304         }
 305
 306         return 0;
 307 }
 308
 309 static int return_init_enet_entries(struct ucc_geth_private *ugeth,
 310                                     u32 *p_start,
 311                                     u8 num_entries,
 312                                     unsigned int risc,
 313                                     int skip_page_for_first_entry)
 314 {
 315         u32 init_enet_offset;
 316         u8 i;
 317         int snum;
 318
 319         for (i = 0; i < num_entries; i++) {
 320                 u32 val = *p_start;
 321
 322                 /* Check that this entry was actually valid --
 323                 needed in case failed in allocations */
 324                 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
 325                         snum =
 326                             (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
 327                             ENET_INIT_PARAM_SNUM_SHIFT;
 328                         qe_put_snum((u8) snum);
 329                         if (!((i == 0) && skip_page_for_first_entry)) {
 330                         /* First entry of Rx does not have page */
 331                                 init_enet_offset =
 332                                     (val & ENET_INIT_PARAM_PTR_MASK);
 333                                 qe_muram_free(init_enet_offset);
 334                         }
 335                         *p_start++ = 0;
 336                 }
 337         }
 338
 339         return 0;
 340 }
 341
 342 #ifdef DEBUG
 343 static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
 344                                   u32 __iomem *p_start,
 345                                   u8 num_entries,
 346                                   u32 thread_size,
 347                                   unsigned int risc,
 348                                   int skip_page_for_first_entry)
 349 {
 350         u32 init_enet_offset;
 351         u8 i;
 352         int snum;
 353
 354         for (i = 0; i < num_entries; i++) {
 355                 u32 val = in_be32(p_start);
 356
 357                 /* Check that this entry was actually valid --
 358                 needed in case failed in allocations */
 359                 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
 360                         snum =
 361                             (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
 362                             ENET_INIT_PARAM_SNUM_SHIFT;
 363                         qe_put_snum((u8) snum);
 364                         if (!((i == 0) && skip_page_for_first_entry)) {
 365                         /* First entry of Rx does not have page */
 366                                 init_enet_offset =
 367                                     (in_be32(p_start) &
 368                                      ENET_INIT_PARAM_PTR_MASK);
 369                                 ugeth_info("Init enet entry %d:", i);
 370                                 ugeth_info("Base address: 0x%08x",
 371                                            (u32)
 372                                            qe_muram_addr(init_enet_offset));
 373                                 mem_disp(qe_muram_addr(init_enet_offset),
 374                                          thread_size);
 375                         }
 376                         p_start++;
 377                 }
 378         }
 379
 380         return 0;
 381 }
 382 #endif
 383
 384 static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
 385 {
 386         kfree(enet_addr_cont);
 387 }
 388
 389 static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
 390 {
 391         out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
 392         out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
 393         out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
 394 }
 395
 396 static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
 397 {
 398         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
 399
 400         if (!(paddr_num < NUM_OF_PADDRS)) {
 401                 ugeth_warn("%s: Illagel paddr_num.", __func__);
 402                 return -EINVAL;
 403         }
 404
 405         p_82xx_addr_filt =
 406             (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
 407             addressfiltering;
 408
 409         /* Writing address ff.ff.ff.ff.ff.ff disables address
 410         recognition for this register */
 411         out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
 412         out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
 413         out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
 414
 415         return 0;
 416 }
 417
 418 static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
 419                                 u8 *p_enet_addr)
 420 {
 421         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
 422         u32 cecr_subblock;
 423
 424         p_82xx_addr_filt =
 425             (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
 426             addressfiltering;
 427
 428         cecr_subblock =
 429             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
 430
 431         /* Ethernet frames are defined in Little Endian mode,
 432         therefor to insert */
 433         /* the address to the hash (Big Endian mode), we reverse the bytes.*/
 434
 435         set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
 436
 437         qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
 438                      QE_CR_PROTOCOL_ETHERNET, 0);
 439 }
 440
 441 static inline int compare_addr(u8 **addr1, u8 **addr2)
 442 {
 443         return memcmp(addr1, addr2, ENET_NUM_OCTETS_PER_ADDRESS);
 444 }
 445
 446 #ifdef DEBUG
 447 static void get_statistics(struct ucc_geth_private *ugeth,
 448                            struct ucc_geth_tx_firmware_statistics *
 449                            tx_firmware_statistics,
 450                            struct ucc_geth_rx_firmware_statistics *
 451                            rx_firmware_statistics,
 452                            struct ucc_geth_hardware_statistics *hardware_statistics)
 453 {
 454         struct ucc_fast __iomem *uf_regs;
 455         struct ucc_geth __iomem *ug_regs;
 456         struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
 457         struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
 458
 459         ug_regs = ugeth->ug_regs;
 460         uf_regs = (struct ucc_fast __iomem *) ug_regs;
 461         p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
 462         p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
 463
 464         /* Tx firmware only if user handed pointer and driver actually
 465         gathers Tx firmware statistics */
 466         if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
 467                 tx_firmware_statistics->sicoltx =
 468                     in_be32(&p_tx_fw_statistics_pram->sicoltx);
 469                 tx_firmware_statistics->mulcoltx =
 470                     in_be32(&p_tx_fw_statistics_pram->mulcoltx);
 471                 tx_firmware_statistics->latecoltxfr =
 472                     in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
 473                 tx_firmware_statistics->frabortduecol =
 474                     in_be32(&p_tx_fw_statistics_pram->frabortduecol);
 475                 tx_firmware_statistics->frlostinmactxer =
 476                     in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
 477                 tx_firmware_statistics->carriersenseertx =
 478                     in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
 479                 tx_firmware_statistics->frtxok =
 480                     in_be32(&p_tx_fw_statistics_pram->frtxok);
 481                 tx_firmware_statistics->txfrexcessivedefer =
 482                     in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
 483                 tx_firmware_statistics->txpkts256 =
 484                     in_be32(&p_tx_fw_statistics_pram->txpkts256);
 485                 tx_firmware_statistics->txpkts512 =
 486                     in_be32(&p_tx_fw_statistics_pram->txpkts512);
 487                 tx_firmware_statistics->txpkts1024 =
 488                     in_be32(&p_tx_fw_statistics_pram->txpkts1024);
 489                 tx_firmware_statistics->txpktsjumbo =
 490                     in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
 491         }
 492
 493         /* Rx firmware only if user handed pointer and driver actually
 494          * gathers Rx firmware statistics */
 495         if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
 496                 int i;
 497                 rx_firmware_statistics->frrxfcser =
 498                     in_be32(&p_rx_fw_statistics_pram->frrxfcser);
 499                 rx_firmware_statistics->fraligner =
 500                     in_be32(&p_rx_fw_statistics_pram->fraligner);
 501                 rx_firmware_statistics->inrangelenrxer =
 502                     in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
 503                 rx_firmware_statistics->outrangelenrxer =
 504                     in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
 505                 rx_firmware_statistics->frtoolong =
 506                     in_be32(&p_rx_fw_statistics_pram->frtoolong);
 507                 rx_firmware_statistics->runt =
 508                     in_be32(&p_rx_fw_statistics_pram->runt);
 509                 rx_firmware_statistics->verylongevent =
 510                     in_be32(&p_rx_fw_statistics_pram->verylongevent);
 511                 rx_firmware_statistics->symbolerror =
 512                     in_be32(&p_rx_fw_statistics_pram->symbolerror);
 513                 rx_firmware_statistics->dropbsy =
 514                     in_be32(&p_rx_fw_statistics_pram->dropbsy);
 515                 for (i = 0; i < 0x8; i++)
 516                         rx_firmware_statistics->res0[i] =
 517                             p_rx_fw_statistics_pram->res0[i];
 518                 rx_firmware_statistics->mismatchdrop =
 519                     in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
 520                 rx_firmware_statistics->underpkts =
 521                     in_be32(&p_rx_fw_statistics_pram->underpkts);
 522                 rx_firmware_statistics->pkts256 =
 523                     in_be32(&p_rx_fw_statistics_pram->pkts256);
 524                 rx_firmware_statistics->pkts512 =
 525                     in_be32(&p_rx_fw_statistics_pram->pkts512);
 526                 rx_firmware_statistics->pkts1024 =
 527                     in_be32(&p_rx_fw_statistics_pram->pkts1024);
 528                 rx_firmware_statistics->pktsjumbo =
 529                     in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
 530                 rx_firmware_statistics->frlossinmacer =
 531                     in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
 532                 rx_firmware_statistics->pausefr =
 533                     in_be32(&p_rx_fw_statistics_pram->pausefr);
 534                 for (i = 0; i < 0x4; i++)
 535                         rx_firmware_statistics->res1[i] =
 536                             p_rx_fw_statistics_pram->res1[i];
 537                 rx_firmware_statistics->removevlan =
 538                     in_be32(&p_rx_fw_statistics_pram->removevlan);
 539                 rx_firmware_statistics->replacevlan =
 540                     in_be32(&p_rx_fw_statistics_pram->replacevlan);
 541                 rx_firmware_statistics->insertvlan =
 542                     in_be32(&p_rx_fw_statistics_pram->insertvlan);
 543         }
 544
 545         /* Hardware only if user handed pointer and driver actually
 546         gathers hardware statistics */
 547         if (hardware_statistics &&
 548             (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) {
 549                 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
 550                 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
 551                 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
 552                 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
 553                 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
 554                 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
 555                 hardware_statistics->txok = in_be32(&ug_regs->txok);
 556                 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
 557                 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
 558                 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
 559                 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
 560                 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
 561                 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
 562                 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
 563                 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
 564         }
 565 }
 566
 567 static void dump_bds(struct ucc_geth_private *ugeth)
 568 {
 569         int i;
 570         int length;
 571
 572         for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
 573                 if (ugeth->p_tx_bd_ring[i]) {
 574                         length =
 575                             (ugeth->ug_info->bdRingLenTx[i] *
 576                              sizeof(struct qe_bd));
 577                         ugeth_info("TX BDs[%d]", i);
 578                         mem_disp(ugeth->p_tx_bd_ring[i], length);
 579                 }
 580         }
 581         for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
 582                 if (ugeth->p_rx_bd_ring[i]) {
 583                         length =
 584                             (ugeth->ug_info->bdRingLenRx[i] *
 585                              sizeof(struct qe_bd));
 586                         ugeth_info("RX BDs[%d]", i);
 587                         mem_disp(ugeth->p_rx_bd_ring[i], length);
 588                 }
 589         }
 590 }
 591
 592 static void dump_regs(struct ucc_geth_private *ugeth)
 593 {
 594         int i;
 595
 596         ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num);
 597         ugeth_info("Base address: 0x%08x", (u32) ugeth->ug_regs);
 598
 599         ugeth_info("maccfg1    : addr - 0x%08x, val - 0x%08x",
 600                    (u32) & ugeth->ug_regs->maccfg1,
 601                    in_be32(&ugeth->ug_regs->maccfg1));
 602         ugeth_info("maccfg2    : addr - 0x%08x, val - 0x%08x",
 603                    (u32) & ugeth->ug_regs->maccfg2,
 604                    in_be32(&ugeth->ug_regs->maccfg2));
 605         ugeth_info("ipgifg     : addr - 0x%08x, val - 0x%08x",
 606                    (u32) & ugeth->ug_regs->ipgifg,
 607                    in_be32(&ugeth->ug_regs->ipgifg));
 608         ugeth_info("hafdup     : addr - 0x%08x, val - 0x%08x",
 609                    (u32) & ugeth->ug_regs->hafdup,
 610                    in_be32(&ugeth->ug_regs->hafdup));
 611         ugeth_info("ifctl      : addr - 0x%08x, val - 0x%08x",
 612                    (u32) & ugeth->ug_regs->ifctl,
 613                    in_be32(&ugeth->ug_regs->ifctl));
 614         ugeth_info("ifstat     : addr - 0x%08x, val - 0x%08x",
 615                    (u32) & ugeth->ug_regs->ifstat,
 616                    in_be32(&ugeth->ug_regs->ifstat));
 617         ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
 618                    (u32) & ugeth->ug_regs->macstnaddr1,
 619                    in_be32(&ugeth->ug_regs->macstnaddr1));
 620         ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
 621                    (u32) & ugeth->ug_regs->macstnaddr2,
 622                    in_be32(&ugeth->ug_regs->macstnaddr2));
 623         ugeth_info("uempr      : addr - 0x%08x, val - 0x%08x",
 624                    (u32) & ugeth->ug_regs->uempr,
 625                    in_be32(&ugeth->ug_regs->uempr));
 626         ugeth_info("utbipar    : addr - 0x%08x, val - 0x%08x",
 627                    (u32) & ugeth->ug_regs->utbipar,
 628                    in_be32(&ugeth->ug_regs->utbipar));
 629         ugeth_info("uescr      : addr - 0x%08x, val - 0x%04x",
 630                    (u32) & ugeth->ug_regs->uescr,
 631                    in_be16(&ugeth->ug_regs->uescr));
 632         ugeth_info("tx64       : addr - 0x%08x, val - 0x%08x",
 633                    (u32) & ugeth->ug_regs->tx64,
 634                    in_be32(&ugeth->ug_regs->tx64));
 635         ugeth_info("tx127      : addr - 0x%08x, val - 0x%08x",
 636                    (u32) & ugeth->ug_regs->tx127,
 637                    in_be32(&ugeth->ug_regs->tx127));
 638         ugeth_info("tx255      : addr - 0x%08x, val - 0x%08x",
 639                    (u32) & ugeth->ug_regs->tx255,
 640                    in_be32(&ugeth->ug_regs->tx255));
 641         ugeth_info("rx64       : addr - 0x%08x, val - 0x%08x",
 642                    (u32) & ugeth->ug_regs->rx64,
 643                    in_be32(&ugeth->ug_regs->rx64));
 644         ugeth_info("rx127      : addr - 0x%08x, val - 0x%08x",
 645                    (u32) & ugeth->ug_regs->rx127,
 646                    in_be32(&ugeth->ug_regs->rx127));
 647         ugeth_info("rx255      : addr - 0x%08x, val - 0x%08x",
 648                    (u32) & ugeth->ug_regs->rx255,
 649                    in_be32(&ugeth->ug_regs->rx255));
 650         ugeth_info("txok       : addr - 0x%08x, val - 0x%08x",
 651                    (u32) & ugeth->ug_regs->txok,
 652                    in_be32(&ugeth->ug_regs->txok));
 653         ugeth_info("txcf       : addr - 0x%08x, val - 0x%04x",
 654                    (u32) & ugeth->ug_regs->txcf,
 655                    in_be16(&ugeth->ug_regs->txcf));
 656         ugeth_info("tmca       : addr - 0x%08x, val - 0x%08x",
 657                    (u32) & ugeth->ug_regs->tmca,
 658                    in_be32(&ugeth->ug_regs->tmca));
 659         ugeth_info("tbca       : addr - 0x%08x, val - 0x%08x",
 660                    (u32) & ugeth->ug_regs->tbca,
 661                    in_be32(&ugeth->ug_regs->tbca));
 662         ugeth_info("rxfok      : addr - 0x%08x, val - 0x%08x",
 663                    (u32) & ugeth->ug_regs->rxfok,
 664                    in_be32(&ugeth->ug_regs->rxfok));
 665         ugeth_info("rxbok      : addr - 0x%08x, val - 0x%08x",
 666                    (u32) & ugeth->ug_regs->rxbok,
 667                    in_be32(&ugeth->ug_regs->rxbok));
 668         ugeth_info("rbyt       : addr - 0x%08x, val - 0x%08x",
 669                    (u32) & ugeth->ug_regs->rbyt,
 670                    in_be32(&ugeth->ug_regs->rbyt));
 671         ugeth_info("rmca       : addr - 0x%08x, val - 0x%08x",
 672                    (u32) & ugeth->ug_regs->rmca,
 673                    in_be32(&ugeth->ug_regs->rmca));
 674         ugeth_info("rbca       : addr - 0x%08x, val - 0x%08x",
 675                    (u32) & ugeth->ug_regs->rbca,
 676                    in_be32(&ugeth->ug_regs->rbca));
 677         ugeth_info("scar       : addr - 0x%08x, val - 0x%08x",
 678                    (u32) & ugeth->ug_regs->scar,
 679                    in_be32(&ugeth->ug_regs->scar));
 680         ugeth_info("scam       : addr - 0x%08x, val - 0x%08x",
 681                    (u32) & ugeth->ug_regs->scam,
 682                    in_be32(&ugeth->ug_regs->scam));
 683
 684         if (ugeth->p_thread_data_tx) {
 685                 int numThreadsTxNumerical;
 686                 switch (ugeth->ug_info->numThreadsTx) {
 687                 case UCC_GETH_NUM_OF_THREADS_1:
 688                         numThreadsTxNumerical = 1;
 689                         break;
 690                 case UCC_GETH_NUM_OF_THREADS_2:
 691                         numThreadsTxNumerical = 2;
 692                         break;
 693                 case UCC_GETH_NUM_OF_THREADS_4:
 694                         numThreadsTxNumerical = 4;
 695                         break;
 696                 case UCC_GETH_NUM_OF_THREADS_6:
 697                         numThreadsTxNumerical = 6;
 698                         break;
 699                 case UCC_GETH_NUM_OF_THREADS_8:
 700                         numThreadsTxNumerical = 8;
 701                         break;
 702                 default:
 703                         numThreadsTxNumerical = 0;
 704                         break;
 705                 }
 706
 707                 ugeth_info("Thread data TXs:");
 708                 ugeth_info("Base address: 0x%08x",
 709                            (u32) ugeth->p_thread_data_tx);
 710                 for (i = 0; i < numThreadsTxNumerical; i++) {
 711                         ugeth_info("Thread data TX[%d]:", i);
 712                         ugeth_info("Base address: 0x%08x",
 713                                    (u32) & ugeth->p_thread_data_tx[i]);
 714                         mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
 715                                  sizeof(struct ucc_geth_thread_data_tx));
 716                 }
 717         }
 718         if (ugeth->p_thread_data_rx) {
 719                 int numThreadsRxNumerical;
 720                 switch (ugeth->ug_info->numThreadsRx) {
 721                 case UCC_GETH_NUM_OF_THREADS_1:
 722                         numThreadsRxNumerical = 1;
 723                         break;
 724                 case UCC_GETH_NUM_OF_THREADS_2:
 725                         numThreadsRxNumerical = 2;
 726                         break;
 727                 case UCC_GETH_NUM_OF_THREADS_4:
 728                         numThreadsRxNumerical = 4;
 729                         break;
 730                 case UCC_GETH_NUM_OF_THREADS_6:
 731                         numThreadsRxNumerical = 6;
 732                         break;
 733                 case UCC_GETH_NUM_OF_THREADS_8:
 734                         numThreadsRxNumerical = 8;
 735                         break;
 736                 default:
 737                         numThreadsRxNumerical = 0;
 738                         break;
 739                 }
 740
 741                 ugeth_info("Thread data RX:");
 742                 ugeth_info("Base address: 0x%08x",
 743                            (u32) ugeth->p_thread_data_rx);
 744                 for (i = 0; i < numThreadsRxNumerical; i++) {
 745                         ugeth_info("Thread data RX[%d]:", i);
 746                         ugeth_info("Base address: 0x%08x",
 747                                    (u32) & ugeth->p_thread_data_rx[i]);
 748                         mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
 749                                  sizeof(struct ucc_geth_thread_data_rx));
 750                 }
 751         }
 752         if (ugeth->p_exf_glbl_param) {
 753                 ugeth_info("EXF global param:");
 754                 ugeth_info("Base address: 0x%08x",
 755                            (u32) ugeth->p_exf_glbl_param);
 756                 mem_disp((u8 *) ugeth->p_exf_glbl_param,
 757                          sizeof(*ugeth->p_exf_glbl_param));
 758         }
 759         if (ugeth->p_tx_glbl_pram) {
 760                 ugeth_info("TX global param:");
 761                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_tx_glbl_pram);
 762                 ugeth_info("temoder      : addr - 0x%08x, val - 0x%04x",
 763                            (u32) & ugeth->p_tx_glbl_pram->temoder,
 764                            in_be16(&ugeth->p_tx_glbl_pram->temoder));
 765                 ugeth_info("sqptr        : addr - 0x%08x, val - 0x%08x",
 766                            (u32) & ugeth->p_tx_glbl_pram->sqptr,
 767                            in_be32(&ugeth->p_tx_glbl_pram->sqptr));
 768                 ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
 769                            (u32) & ugeth->p_tx_glbl_pram->schedulerbasepointer,
 770                            in_be32(&ugeth->p_tx_glbl_pram->
 771                                    schedulerbasepointer));
 772                 ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
 773                            (u32) & ugeth->p_tx_glbl_pram->txrmonbaseptr,
 774                            in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
 775                 ugeth_info("tstate       : addr - 0x%08x, val - 0x%08x",
 776                            (u32) & ugeth->p_tx_glbl_pram->tstate,
 777                            in_be32(&ugeth->p_tx_glbl_pram->tstate));
 778                 ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
 779                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[0],
 780                            ugeth->p_tx_glbl_pram->iphoffset[0]);
 781                 ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
 782                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[1],
 783                            ugeth->p_tx_glbl_pram->iphoffset[1]);
 784                 ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
 785                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[2],
 786                            ugeth->p_tx_glbl_pram->iphoffset[2]);
 787                 ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
 788                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[3],
 789                            ugeth->p_tx_glbl_pram->iphoffset[3]);
 790                 ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
 791                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[4],
 792                            ugeth->p_tx_glbl_pram->iphoffset[4]);
 793                 ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
 794                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[5],
 795                            ugeth->p_tx_glbl_pram->iphoffset[5]);
 796                 ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
 797                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[6],
 798                            ugeth->p_tx_glbl_pram->iphoffset[6]);
 799                 ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
 800                            (u32) & ugeth->p_tx_glbl_pram->iphoffset[7],
 801                            ugeth->p_tx_glbl_pram->iphoffset[7]);
 802                 ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
 803                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[0],
 804                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
 805                 ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
 806                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[1],
 807                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
 808                 ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
 809                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[2],
 810                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
 811                 ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
 812                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[3],
 813                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
 814                 ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
 815                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[4],
 816                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
 817                 ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
 818                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[5],
 819                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
 820                 ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
 821                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[6],
 822                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
 823                 ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
 824                            (u32) & ugeth->p_tx_glbl_pram->vtagtable[7],
 825                            in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
 826                 ugeth_info("tqptr        : addr - 0x%08x, val - 0x%08x",
 827                            (u32) & ugeth->p_tx_glbl_pram->tqptr,
 828                            in_be32(&ugeth->p_tx_glbl_pram->tqptr));
 829         }
 830         if (ugeth->p_rx_glbl_pram) {
 831                 ugeth_info("RX global param:");
 832                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_glbl_pram);
 833                 ugeth_info("remoder         : addr - 0x%08x, val - 0x%08x",
 834                            (u32) & ugeth->p_rx_glbl_pram->remoder,
 835                            in_be32(&ugeth->p_rx_glbl_pram->remoder));
 836                 ugeth_info("rqptr           : addr - 0x%08x, val - 0x%08x",
 837                            (u32) & ugeth->p_rx_glbl_pram->rqptr,
 838                            in_be32(&ugeth->p_rx_glbl_pram->rqptr));
 839                 ugeth_info("typeorlen       : addr - 0x%08x, val - 0x%04x",
 840                            (u32) & ugeth->p_rx_glbl_pram->typeorlen,
 841                            in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
 842                 ugeth_info("rxgstpack       : addr - 0x%08x, val - 0x%02x",
 843                            (u32) & ugeth->p_rx_glbl_pram->rxgstpack,
 844                            ugeth->p_rx_glbl_pram->rxgstpack);
 845                 ugeth_info("rxrmonbaseptr   : addr - 0x%08x, val - 0x%08x",
 846                            (u32) & ugeth->p_rx_glbl_pram->rxrmonbaseptr,
 847                            in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
 848                 ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
 849                            (u32) & ugeth->p_rx_glbl_pram->intcoalescingptr,
 850                            in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
 851                 ugeth_info("rstate          : addr - 0x%08x, val - 0x%02x",
 852                            (u32) & ugeth->p_rx_glbl_pram->rstate,
 853                            ugeth->p_rx_glbl_pram->rstate);
 854                 ugeth_info("mrblr           : addr - 0x%08x, val - 0x%04x",
 855                            (u32) & ugeth->p_rx_glbl_pram->mrblr,
 856                            in_be16(&ugeth->p_rx_glbl_pram->mrblr));
 857                 ugeth_info("rbdqptr         : addr - 0x%08x, val - 0x%08x",
 858                            (u32) & ugeth->p_rx_glbl_pram->rbdqptr,
 859                            in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
 860                 ugeth_info("mflr            : addr - 0x%08x, val - 0x%04x",
 861                            (u32) & ugeth->p_rx_glbl_pram->mflr,
 862                            in_be16(&ugeth->p_rx_glbl_pram->mflr));
 863                 ugeth_info("minflr          : addr - 0x%08x, val - 0x%04x",
 864                            (u32) & ugeth->p_rx_glbl_pram->minflr,
 865                            in_be16(&ugeth->p_rx_glbl_pram->minflr));
 866                 ugeth_info("maxd1           : addr - 0x%08x, val - 0x%04x",
 867                            (u32) & ugeth->p_rx_glbl_pram->maxd1,
 868                            in_be16(&ugeth->p_rx_glbl_pram->maxd1));
 869                 ugeth_info("maxd2           : addr - 0x%08x, val - 0x%04x",
 870                            (u32) & ugeth->p_rx_glbl_pram->maxd2,
 871                            in_be16(&ugeth->p_rx_glbl_pram->maxd2));
 872                 ugeth_info("ecamptr         : addr - 0x%08x, val - 0x%08x",
 873                            (u32) & ugeth->p_rx_glbl_pram->ecamptr,
 874                            in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
 875                 ugeth_info("l2qt            : addr - 0x%08x, val - 0x%08x",
 876                            (u32) & ugeth->p_rx_glbl_pram->l2qt,
 877                            in_be32(&ugeth->p_rx_glbl_pram->l2qt));
 878                 ugeth_info("l3qt[0]         : addr - 0x%08x, val - 0x%08x",
 879                            (u32) & ugeth->p_rx_glbl_pram->l3qt[0],
 880                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
 881                 ugeth_info("l3qt[1]         : addr - 0x%08x, val - 0x%08x",
 882                            (u32) & ugeth->p_rx_glbl_pram->l3qt[1],
 883                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
 884                 ugeth_info("l3qt[2]         : addr - 0x%08x, val - 0x%08x",
 885                            (u32) & ugeth->p_rx_glbl_pram->l3qt[2],
 886                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
 887                 ugeth_info("l3qt[3]         : addr - 0x%08x, val - 0x%08x",
 888                            (u32) & ugeth->p_rx_glbl_pram->l3qt[3],
 889                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
 890                 ugeth_info("l3qt[4]         : addr - 0x%08x, val - 0x%08x",
 891                            (u32) & ugeth->p_rx_glbl_pram->l3qt[4],
 892                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
 893                 ugeth_info("l3qt[5]         : addr - 0x%08x, val - 0x%08x",
 894                            (u32) & ugeth->p_rx_glbl_pram->l3qt[5],
 895                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
 896                 ugeth_info("l3qt[6]         : addr - 0x%08x, val - 0x%08x",
 897                            (u32) & ugeth->p_rx_glbl_pram->l3qt[6],
 898                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
 899                 ugeth_info("l3qt[7]         : addr - 0x%08x, val - 0x%08x",
 900                            (u32) & ugeth->p_rx_glbl_pram->l3qt[7],
 901                            in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
 902                 ugeth_info("vlantype        : addr - 0x%08x, val - 0x%04x",
 903                            (u32) & ugeth->p_rx_glbl_pram->vlantype,
 904                            in_be16(&ugeth->p_rx_glbl_pram->vlantype));
 905                 ugeth_info("vlantci         : addr - 0x%08x, val - 0x%04x",
 906                            (u32) & ugeth->p_rx_glbl_pram->vlantci,
 907                            in_be16(&ugeth->p_rx_glbl_pram->vlantci));
 908                 for (i = 0; i < 64; i++)
 909                         ugeth_info
 910                     ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
 911                              i,
 912                              (u32) & ugeth->p_rx_glbl_pram->addressfiltering[i],
 913                              ugeth->p_rx_glbl_pram->addressfiltering[i]);
 914                 ugeth_info("exfGlobalParam  : addr - 0x%08x, val - 0x%08x",
 915                            (u32) & ugeth->p_rx_glbl_pram->exfGlobalParam,
 916                            in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
 917         }
 918         if (ugeth->p_send_q_mem_reg) {
 919                 ugeth_info("Send Q memory registers:");
 920                 ugeth_info("Base address: 0x%08x",
 921                            (u32) ugeth->p_send_q_mem_reg);
 922                 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
 923                         ugeth_info("SQQD[%d]:", i);
 924                         ugeth_info("Base address: 0x%08x",
 925                                    (u32) & ugeth->p_send_q_mem_reg->sqqd[i]);
 926                         mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
 927                                  sizeof(struct ucc_geth_send_queue_qd));
 928                 }
 929         }
 930         if (ugeth->p_scheduler) {
 931                 ugeth_info("Scheduler:");
 932                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_scheduler);
 933                 mem_disp((u8 *) ugeth->p_scheduler,
 934                          sizeof(*ugeth->p_scheduler));
 935         }
 936         if (ugeth->p_tx_fw_statistics_pram) {
 937                 ugeth_info("TX FW statistics pram:");
 938                 ugeth_info("Base address: 0x%08x",
 939                            (u32) ugeth->p_tx_fw_statistics_pram);
 940                 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
 941                          sizeof(*ugeth->p_tx_fw_statistics_pram));
 942         }
 943         if (ugeth->p_rx_fw_statistics_pram) {
 944                 ugeth_info("RX FW statistics pram:");
 945                 ugeth_info("Base address: 0x%08x",
 946                            (u32) ugeth->p_rx_fw_statistics_pram);
 947                 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
 948                          sizeof(*ugeth->p_rx_fw_statistics_pram));
 949         }
 950         if (ugeth->p_rx_irq_coalescing_tbl) {
 951                 ugeth_info("RX IRQ coalescing tables:");
 952                 ugeth_info("Base address: 0x%08x",
 953                            (u32) ugeth->p_rx_irq_coalescing_tbl);
 954                 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
 955                         ugeth_info("RX IRQ coalescing table entry[%d]:", i);
 956                         ugeth_info("Base address: 0x%08x",
 957                                    (u32) & ugeth->p_rx_irq_coalescing_tbl->
 958                                    coalescingentry[i]);
 959                         ugeth_info
 960                 ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
 961                              (u32) & ugeth->p_rx_irq_coalescing_tbl->
 962                              coalescingentry[i].interruptcoalescingmaxvalue,
 963                              in_be32(&ugeth->p_rx_irq_coalescing_tbl->
 964                                      coalescingentry[i].
 965                                      interruptcoalescingmaxvalue));
 966                         ugeth_info
 967                 ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
 968                              (u32) & ugeth->p_rx_irq_coalescing_tbl->
 969                              coalescingentry[i].interruptcoalescingcounter,
 970                              in_be32(&ugeth->p_rx_irq_coalescing_tbl->
 971                                      coalescingentry[i].
 972                                      interruptcoalescingcounter));
 973                 }
 974         }
 975         if (ugeth->p_rx_bd_qs_tbl) {
 976                 ugeth_info("RX BD QS tables:");
 977                 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_bd_qs_tbl);
 978                 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
 979                         ugeth_info("RX BD QS table[%d]:", i);
 980                         ugeth_info("Base address: 0x%08x",
 981                                    (u32) & ugeth->p_rx_bd_qs_tbl[i]);
 982                         ugeth_info
 983                             ("bdbaseptr        : addr - 0x%08x, val - 0x%08x",
 984                              (u32) & ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
 985                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
 986                         ugeth_info
 987                             ("bdptr            : addr - 0x%08x, val - 0x%08x",
 988                              (u32) & ugeth->p_rx_bd_qs_tbl[i].bdptr,
 989                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
 990                         ugeth_info
 991                             ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
 992                              (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
 993                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].
 994                                      externalbdbaseptr));
 995                         ugeth_info
 996                             ("externalbdptr    : addr - 0x%08x, val - 0x%08x",
 997                              (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
 998                              in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
 999                         ugeth_info("ucode RX Prefetched BDs:");
1000                         ugeth_info("Base address: 0x%08x",
1001                                    (u32)
1002                                    qe_muram_addr(in_be32
1003                                                  (&ugeth->p_rx_bd_qs_tbl[i].
1004                                                   bdbaseptr)));
1005                         mem_disp((u8 *)
1006                                  qe_muram_addr(in_be32
1007                                                (&ugeth->p_rx_bd_qs_tbl[i].
1008                                                 bdbaseptr)),
1009                                  sizeof(struct ucc_geth_rx_prefetched_bds));
1010                 }
1011         }
1012         if (ugeth->p_init_enet_param_shadow) {
1013                 int size;
1014                 ugeth_info("Init enet param shadow:");
1015                 ugeth_info("Base address: 0x%08x",
1016                            (u32) ugeth->p_init_enet_param_shadow);
1017                 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
1018                          sizeof(*ugeth->p_init_enet_param_shadow));
1019
1020                 size = sizeof(struct ucc_geth_thread_rx_pram);
1021                 if (ugeth->ug_info->rxExtendedFiltering) {
1022                         size +=
1023                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1024                         if (ugeth->ug_info->largestexternallookupkeysize ==
1025                             QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1026                                 size +=
1027                         THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1028                         if (ugeth->ug_info->largestexternallookupkeysize ==
1029                             QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1030                                 size +=
1031                         THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1032                 }
1033
1034                 dump_init_enet_entries(ugeth,
1035                                        &(ugeth->p_init_enet_param_shadow->
1036                                          txthread[0]),
1037                                        ENET_INIT_PARAM_MAX_ENTRIES_TX,
1038                                        sizeof(struct ucc_geth_thread_tx_pram),
1039                                        ugeth->ug_info->riscTx, 0);
1040                 dump_init_enet_entries(ugeth,
1041                                        &(ugeth->p_init_enet_param_shadow->
1042                                          rxthread[0]),
1043                                        ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1044                                        ugeth->ug_info->riscRx, 1);
1045         }
1046 }
1047 #endif /* DEBUG */
1048
1049 static void init_default_reg_vals(u32 __iomem *upsmr_register,
1050                                   u32 __iomem *maccfg1_register,
1051                                   u32 __iomem *maccfg2_register)
1052 {
1053         out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1054         out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1055         out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1056 }
1057
1058 static int init_half_duplex_params(int alt_beb,
1059                                    int back_pressure_no_backoff,
1060                                    int no_backoff,
1061                                    int excess_defer,
1062                                    u8 alt_beb_truncation,
1063                                    u8 max_retransmissions,
1064                                    u8 collision_window,
1065                                    u32 __iomem *hafdup_register)
1066 {
1067         u32 value = 0;
1068
1069         if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1070             (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1071             (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1072                 return -EINVAL;
1073
1074         value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1075
1076         if (alt_beb)
1077                 value |= HALFDUP_ALT_BEB;
1078         if (back_pressure_no_backoff)
1079                 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1080         if (no_backoff)
1081                 value |= HALFDUP_NO_BACKOFF;
1082         if (excess_defer)
1083                 value |= HALFDUP_EXCESSIVE_DEFER;
1084
1085         value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1086
1087         value |= collision_window;
1088
1089         out_be32(hafdup_register, value);
1090         return 0;
1091 }
1092
1093 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1094                                        u8 non_btb_ipg,
1095                                        u8 min_ifg,
1096                                        u8 btb_ipg,
1097                                        u32 __iomem *ipgifg_register)
1098 {
1099         u32 value = 0;
1100
1101         /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1102         IPG part 2 */
1103         if (non_btb_cs_ipg > non_btb_ipg)
1104                 return -EINVAL;
1105
1106         if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1107             (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1108             /*(min_ifg        > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1109             (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1110                 return -EINVAL;
1111
1112         value |=
1113             ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1114              IPGIFG_NBTB_CS_IPG_MASK);
1115         value |=
1116             ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1117              IPGIFG_NBTB_IPG_MASK);
1118         value |=
1119             ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1120              IPGIFG_MIN_IFG_MASK);
1121         value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1122
1123         out_be32(ipgifg_register, value);
1124         return 0;
1125 }
1126
1127 int init_flow_control_params(u32 automatic_flow_control_mode,
1128                                     int rx_flow_control_enable,
1129                                     int tx_flow_control_enable,
1130                                     u16 pause_period,
1131                                     u16 extension_field,
1132                                     u32 __iomem *upsmr_register,
1133                                     u32 __iomem *uempr_register,
1134                                     u32 __iomem *maccfg1_register)
1135 {
1136         u32 value = 0;
1137
1138         /* Set UEMPR register */
1139         value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1140         value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1141         out_be32(uempr_register, value);
1142
1143         /* Set UPSMR register */
1144         setbits32(upsmr_register, automatic_flow_control_mode);
1145
1146         value = in_be32(maccfg1_register);
1147         if (rx_flow_control_enable)
1148                 value |= MACCFG1_FLOW_RX;
1149         if (tx_flow_control_enable)
1150                 value |= MACCFG1_FLOW_TX;
1151         out_be32(maccfg1_register, value);
1152
1153         return 0;
1154 }
1155
1156 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1157                                              int auto_zero_hardware_statistics,
1158                                              u32 __iomem *upsmr_register,
1159                                              u16 __iomem *uescr_register)
1160 {
1161         u16 uescr_value = 0;
1162
1163         /* Enable hardware statistics gathering if requested */
1164         if (enable_hardware_statistics)
1165                 setbits32(upsmr_register, UCC_GETH_UPSMR_HSE);
1166
1167         /* Clear hardware statistics counters */
1168         uescr_value = in_be16(uescr_register);
1169         uescr_value |= UESCR_CLRCNT;
1170         /* Automatically zero hardware statistics counters on read,
1171         if requested */
1172         if (auto_zero_hardware_statistics)
1173                 uescr_value |= UESCR_AUTOZ;
1174         out_be16(uescr_register, uescr_value);
1175
1176         return 0;
1177 }
1178
1179 static int init_firmware_statistics_gathering_mode(int
1180                 enable_tx_firmware_statistics,
1181                 int enable_rx_firmware_statistics,
1182                 u32 __iomem *tx_rmon_base_ptr,
1183                 u32 tx_firmware_statistics_structure_address,
1184                 u32 __iomem *rx_rmon_base_ptr,
1185                 u32 rx_firmware_statistics_structure_address,
1186                 u16 __iomem *temoder_register,
1187                 u32 __iomem *remoder_register)
1188 {
1189         /* Note: this function does not check if */
1190         /* the parameters it receives are NULL   */
1191
1192         if (enable_tx_firmware_statistics) {
1193                 out_be32(tx_rmon_base_ptr,
1194                          tx_firmware_statistics_structure_address);
1195                 setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE);
1196         }
1197
1198         if (enable_rx_firmware_statistics) {
1199                 out_be32(rx_rmon_base_ptr,
1200                          rx_firmware_statistics_structure_address);
1201                 setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE);
1202         }
1203
1204         return 0;
1205 }
1206
1207 static int init_mac_station_addr_regs(u8 address_byte_0,
1208                                       u8 address_byte_1,
1209                                       u8 address_byte_2,
1210                                       u8 address_byte_3,
1211                                       u8 address_byte_4,
1212                                       u8 address_byte_5,
1213                                       u32 __iomem *macstnaddr1_register,
1214                                       u32 __iomem *macstnaddr2_register)
1215 {
1216         u32 value = 0;
1217
1218         /* Example: for a station address of 0x12345678ABCD, */
1219         /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1220
1221         /* MACSTNADDR1 Register: */
1222
1223         /* 0                      7   8                      15  */
1224         /* station address byte 5     station address byte 4     */
1225         /* 16                     23  24                     31  */
1226         /* station address byte 3     station address byte 2     */
1227         value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1228         value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1229         value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1230         value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1231
1232         out_be32(macstnaddr1_register, value);
1233
1234         /* MACSTNADDR2 Register: */
1235
1236         /* 0                      7   8                      15  */
1237         /* station address byte 1     station address byte 0     */
1238         /* 16                     23  24                     31  */
1239         /*         reserved                   reserved           */
1240         value = 0;
1241         value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1242         value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1243
1244         out_be32(macstnaddr2_register, value);
1245
1246         return 0;
1247 }
1248
1249 static int init_check_frame_length_mode(int length_check,
1250                                         u32 __iomem *maccfg2_register)
1251 {
1252         u32 value = 0;
1253
1254         value = in_be32(maccfg2_register);
1255
1256         if (length_check)
1257                 value |= MACCFG2_LC;
1258         else
1259                 value &= ~MACCFG2_LC;
1260
1261         out_be32(maccfg2_register, value);
1262         return 0;
1263 }
1264
1265 static int init_preamble_length(u8 preamble_length,
1266                                 u32 __iomem *maccfg2_register)
1267 {
1268         if ((preamble_length < 3) || (preamble_length > 7))
1269                 return -EINVAL;
1270
1271         clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK,
1272                         preamble_length << MACCFG2_PREL_SHIFT);
1273
1274         return 0;
1275 }
1276
1277 static int init_rx_parameters(int reject_broadcast,
1278                               int receive_short_frames,
1279                               int promiscuous, u32 __iomem *upsmr_register)
1280 {
1281         u32 value = 0;
1282
1283         value = in_be32(upsmr_register);
1284
1285         if (reject_broadcast)
1286                 value |= UCC_GETH_UPSMR_BRO;
1287         else
1288                 value &= ~UCC_GETH_UPSMR_BRO;
1289
1290         if (receive_short_frames)
1291                 value |= UCC_GETH_UPSMR_RSH;
1292         else
1293                 value &= ~UCC_GETH_UPSMR_RSH;
1294
1295         if (promiscuous)
1296                 value |= UCC_GETH_UPSMR_PRO;
1297         else
1298                 value &= ~UCC_GETH_UPSMR_PRO;
1299
1300         out_be32(upsmr_register, value);
1301
1302         return 0;
1303 }
1304
1305 static int init_max_rx_buff_len(u16 max_rx_buf_len,
1306                                 u16 __iomem *mrblr_register)
1307 {
1308         /* max_rx_buf_len value must be a multiple of 128 */
1309         if ((max_rx_buf_len == 0)
1310             || (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
1311                 return -EINVAL;
1312
1313         out_be16(mrblr_register, max_rx_buf_len);
1314         return 0;
1315 }
1316
1317 static int init_min_frame_len(u16 min_frame_length,
1318                               u16 __iomem *minflr_register,
1319                               u16 __iomem *mrblr_register)
1320 {
1321         u16 mrblr_value = 0;
1322
1323         mrblr_value = in_be16(mrblr_register);
1324         if (min_frame_length >= (mrblr_value - 4))
1325                 return -EINVAL;
1326
1327         out_be16(minflr_register, min_frame_length);
1328         return 0;
1329 }
1330
1331 static int adjust_enet_interface(struct ucc_geth_private *ugeth)
1332 {
1333         struct ucc_geth_info *ug_info;
1334         struct ucc_geth __iomem *ug_regs;
1335         struct ucc_fast __iomem *uf_regs;
1336         int ret_val;
1337         u32 upsmr, maccfg2, tbiBaseAddress;
1338         u16 value;
1339
1340         ugeth_vdbg("%s: IN", __func__);
1341
1342         ug_info = ugeth->ug_info;
1343         ug_regs = ugeth->ug_regs;
1344         uf_regs = ugeth->uccf->uf_regs;
1345
1346         /*                    Set MACCFG2                    */
1347         maccfg2 = in_be32(&ug_regs->maccfg2);
1348         maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
1349         if ((ugeth->max_speed == SPEED_10) ||
1350             (ugeth->max_speed == SPEED_100))
1351                 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
1352         else if (ugeth->max_speed == SPEED_1000)
1353                 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1354         maccfg2 |= ug_info->padAndCrc;
1355         out_be32(&ug_regs->maccfg2, maccfg2);
1356
1357         /*                    Set UPSMR                      */
1358         upsmr = in_be32(&uf_regs->upsmr);
1359         upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M |
1360                    UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM);
1361         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1362             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1363             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1364             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1365             (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1366             (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1367                 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RMII)
1368                         upsmr |= UCC_GETH_UPSMR_RPM;
1369                 switch (ugeth->max_speed) {
1370                 case SPEED_10:
1371                         upsmr |= UCC_GETH_UPSMR_R10M;
1372                         /* FALLTHROUGH */
1373                 case SPEED_100:
1374                         if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
1375                                 upsmr |= UCC_GETH_UPSMR_RMM;
1376                 }
1377         }
1378         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1379             (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1380                 upsmr |= UCC_GETH_UPSMR_TBIM;
1381         }
1382         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_SGMII))
1383                 upsmr |= UCC_GETH_UPSMR_SGMM;
1384
1385         out_be32(&uf_regs->upsmr, upsmr);
1386
1387         /* Disable autonegotiation in tbi mode, because by default it
1388         comes up in autonegotiation mode. */
1389         /* Note that this depends on proper setting in utbipar register. */
1390         if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1391             (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1392                 tbiBaseAddress = in_be32(&ug_regs->utbipar);
1393                 tbiBaseAddress &= UTBIPAR_PHY_ADDRESS_MASK;
1394                 tbiBaseAddress >>= UTBIPAR_PHY_ADDRESS_SHIFT;
1395                 value = ugeth->phydev->bus->read(ugeth->phydev->bus,
1396                                 (u8) tbiBaseAddress, ENET_TBI_MII_CR);
1397                 value &= ~0x1000;       /* Turn off autonegotiation */
1398                 ugeth->phydev->bus->write(ugeth->phydev->bus,
1399                                 (u8) tbiBaseAddress, ENET_TBI_MII_CR, value);
1400         }
1401
1402         init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1403
1404         ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1405         if (ret_val != 0) {
1406                 if (netif_msg_probe(ugeth))
1407                         ugeth_err("%s: Preamble length must be between 3 and 7 inclusive.",
1408                              __func__);
1409                 return ret_val;
1410         }
1411
1412         return 0;
1413 }
1414
1415 /* Called every time the controller might need to be made
1416  * aware of new link state.  The PHY code conveys this
1417  * information through variables in the ugeth structure, and this
1418  * function converts those variables into the appropriate
1419  * register values, and can bring down the device if needed.
1420  */
1421
1422 static void adjust_link(struct net_device *dev)
1423 {
1424         struct ucc_geth_private *ugeth = netdev_priv(dev);
1425         struct ucc_geth __iomem *ug_regs;
1426         struct ucc_fast __iomem *uf_regs;
1427         struct phy_device *phydev = ugeth->phydev;
1428         unsigned long flags;
1429         int new_state = 0;
1430
1431         ug_regs = ugeth->ug_regs;
1432         uf_regs = ugeth->uccf->uf_regs;
1433
1434         spin_lock_irqsave(&ugeth->lock, flags);
1435
1436         if (phydev->link) {
1437                 u32 tempval = in_be32(&ug_regs->maccfg2);
1438                 u32 upsmr = in_be32(&uf_regs->upsmr);
1439                 /* Now we make sure that we can be in full duplex mode.
1440                  * If not, we operate in half-duplex mode. */
1441                 if (phydev->duplex != ugeth->oldduplex) {
1442                         new_state = 1;
1443                         if (!(phydev->duplex))
1444                                 tempval &= ~(MACCFG2_FDX);
1445                         else
1446                                 tempval |= MACCFG2_FDX;
1447                         ugeth->oldduplex = phydev->duplex;
1448                 }
1449
1450                 if (phydev->speed != ugeth->oldspeed) {
1451                         new_state = 1;
1452                         switch (phydev->speed) {
1453                         case SPEED_1000:
1454                                 tempval = ((tempval &
1455                                             ~(MACCFG2_INTERFACE_MODE_MASK)) |
1456                                             MACCFG2_INTERFACE_MODE_BYTE);
1457                                 break;
1458                         case SPEED_100:
1459                         case SPEED_10:
1460                                 tempval = ((tempval &
1461                                             ~(MACCFG2_INTERFACE_MODE_MASK)) |
1462                                             MACCFG2_INTERFACE_MODE_NIBBLE);
1463                                 /* if reduced mode, re-set UPSMR.R10M */
1464                                 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1465                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1466                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1467                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1468                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
1469                                     (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1470                                         if (phydev->speed == SPEED_10)
1471                                                 upsmr |= UCC_GETH_UPSMR_R10M;
1472                                         else
1473                                                 upsmr &= ~UCC_GETH_UPSMR_R10M;
1474                                 }
1475                                 break;
1476                         default:
1477                                 if (netif_msg_link(ugeth))
1478                                         ugeth_warn(
1479                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!",
1480                                                 dev->name, phydev->speed);
1481                                 break;
1482                         }
1483                         ugeth->oldspeed = phydev->speed;
1484                 }
1485
1486                 out_be32(&ug_regs->maccfg2, tempval);
1487                 out_be32(&uf_regs->upsmr, upsmr);
1488
1489                 if (!ugeth->oldlink) {
1490                         new_state = 1;
1491                         ugeth->oldlink = 1;
1492                 }
1493         } else if (ugeth->oldlink) {
1494                         new_state = 1;
1495                         ugeth->oldlink = 0;
1496                         ugeth->oldspeed = 0;
1497                         ugeth->oldduplex = -1;
1498         }
1499
1500         if (new_state && netif_msg_link(ugeth))
1501                 phy_print_status(phydev);
1502
1503         spin_unlock_irqrestore(&ugeth->lock, flags);
1504 }
1505
1506 /* Initialize TBI PHY interface for communicating with the
1507  * SERDES lynx PHY on the chip.  We communicate with this PHY
1508  * through the MDIO bus on each controller, treating it as a
1509  * "normal" PHY at the address found in the UTBIPA register.  We assume
1510  * that the UTBIPA register is valid.  Either the MDIO bus code will set
1511  * it to a value that doesn't conflict with other PHYs on the bus, or the
1512  * value doesn't matter, as there are no other PHYs on the bus.
1513  */
1514 static void uec_configure_serdes(struct net_device *dev)
1515 {
1516         struct ucc_geth_private *ugeth = netdev_priv(dev);
1517         struct ucc_geth_info *ug_info = ugeth->ug_info;
1518         struct phy_device *tbiphy;
1519
1520         if (!ug_info->tbi_node) {
1521                 dev_warn(&dev->dev, "SGMII mode requires that the device "
1522                         "tree specify a tbi-handle\n");
1523                 return;
1524         }
1525
1526         tbiphy = of_phy_find_device(ug_info->tbi_node);
1527         if (!tbiphy) {
1528                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1529                 return;
1530         }
1531
1532         /*
1533          * If the link is already up, we must already be ok, and don't need to
1534          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1535          * everything for us?  Resetting it takes the link down and requires
1536          * several seconds for it to come back.
1537          */
1538         if (phy_read(tbiphy, ENET_TBI_MII_SR) & TBISR_LSTATUS)
1539                 return;
1540
1541         /* Single clk mode, mii mode off(for serdes communication) */
1542         phy_write(tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS);
1543
1544         phy_write(tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
1545
1546         phy_write(tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS);
1547 }
1548
1549 /* Configure the PHY for dev.
1550  * returns 0 if success.  -1 if failure
1551  */
1552 static int init_phy(struct net_device *dev)
1553 {
1554         struct ucc_geth_private *priv = netdev_priv(dev);
1555         struct ucc_geth_info *ug_info = priv->ug_info;
1556         struct phy_device *phydev;
1557
1558         priv->oldlink = 0;
1559         priv->oldspeed = 0;
1560         priv->oldduplex = -1;
1561
1562         phydev = of_phy_connect(dev, ug_info->phy_node, &adjust_link, 0,
1563                                 priv->phy_interface);
1564         if (!phydev)
1565                 phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1566                                                    priv->phy_interface);
1567         if (!phydev) {
1568                 dev_err(&dev->dev, "Could not attach to PHY\n");
1569                 return -ENODEV;
1570         }
1571
1572         if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
1573                 uec_configure_serdes(dev);
1574
1575         phydev->supported &= (ADVERTISED_10baseT_Half |
1576                                  ADVERTISED_10baseT_Full |
1577                                  ADVERTISED_100baseT_Half |
1578                                  ADVERTISED_100baseT_Full);
1579
1580         if (priv->max_speed == SPEED_1000)
1581                 phydev->supported |= ADVERTISED_1000baseT_Full;
1582
1583         phydev->advertising = phydev->supported;
1584
1585         priv->phydev = phydev;
1586
1587         return 0;
1588 }
1589
1590
1591
1592 static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1593 {
1594         struct ucc_fast_private *uccf;
1595         u32 cecr_subblock;
1596         u32 temp;
1597         int i = 10;
1598
1599         uccf = ugeth->uccf;
1600
1601         /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1602         clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA);
1603         out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA);  /* clear by writing 1 */
1604
1605         /* Issue host command */
1606         cecr_subblock =
1607             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1608         qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
1609                      QE_CR_PROTOCOL_ETHERNET, 0);
1610
1611         /* Wait for command to complete */
1612         do {
1613                 msleep(10);
1614                 temp = in_be32(uccf->p_ucce);
1615         } while (!(temp & UCC_GETH_UCCE_GRA) && --i);
1616
1617         uccf->stopped_tx = 1;
1618
1619         return 0;
1620 }
1621
1622 static int ugeth_graceful_stop_rx(struct ucc_geth_private * ugeth)
1623 {
1624         struct ucc_fast_private *uccf;
1625         u32 cecr_subblock;
1626         u8 temp;
1627         int i = 10;
1628
1629         uccf = ugeth->uccf;
1630
1631         /* Clear acknowledge bit */
1632         temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1633         temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
1634         out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp);
1635
1636         /* Keep issuing command and checking acknowledge bit until
1637         it is asserted, according to spec */
1638         do {
1639                 /* Issue host command */
1640                 cecr_subblock =
1641                     ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1642                                                 ucc_num);
1643                 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
1644                              QE_CR_PROTOCOL_ETHERNET, 0);
1645                 msleep(10);
1646                 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1647         } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i);
1648
1649         uccf->stopped_rx = 1;
1650
1651         return 0;
1652 }
1653
1654 static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
1655 {
1656         struct ucc_fast_private *uccf;
1657         u32 cecr_subblock;
1658
1659         uccf = ugeth->uccf;
1660
1661         cecr_subblock =
1662             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1663         qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
1664         uccf->stopped_tx = 0;
1665
1666         return 0;
1667 }
1668
1669 static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
1670 {
1671         struct ucc_fast_private *uccf;
1672         u32 cecr_subblock;
1673
1674         uccf = ugeth->uccf;
1675
1676         cecr_subblock =
1677             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1678         qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
1679                      0);
1680         uccf->stopped_rx = 0;
1681
1682         return 0;
1683 }
1684
1685 static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1686 {
1687         struct ucc_fast_private *uccf;
1688         int enabled_tx, enabled_rx;
1689
1690         uccf = ugeth->uccf;
1691
1692         /* check if the UCC number is in range. */
1693         if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1694                 if (netif_msg_probe(ugeth))
1695                         ugeth_err("%s: ucc_num out of range.", __func__);
1696                 return -EINVAL;
1697         }
1698
1699         enabled_tx = uccf->enabled_tx;
1700         enabled_rx = uccf->enabled_rx;
1701
1702         /* Get Tx and Rx going again, in case this channel was actively
1703         disabled. */
1704         if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
1705                 ugeth_restart_tx(ugeth);
1706         if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
1707                 ugeth_restart_rx(ugeth);
1708
1709         ucc_fast_enable(uccf, mode);    /* OK to do even if not disabled */
1710
1711         return 0;
1712
1713 }
1714
1715 static int ugeth_disable(struct ucc_geth_private * ugeth, enum comm_dir mode)
1716 {
1717         struct ucc_fast_private *uccf;
1718
1719         uccf = ugeth->uccf;
1720
1721         /* check if the UCC number is in range. */
1722         if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1723                 if (netif_msg_probe(ugeth))
1724                         ugeth_err("%s: ucc_num out of range.", __func__);
1725                 return -EINVAL;
1726         }
1727
1728         /* Stop any transmissions */
1729         if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
1730                 ugeth_graceful_stop_tx(ugeth);
1731
1732         /* Stop any receptions */
1733         if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
1734                 ugeth_graceful_stop_rx(ugeth);
1735
1736         ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
1737
1738         return 0;
1739 }
1740
1741 static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
1742 {
1743 #ifdef DEBUG
1744         ucc_fast_dump_regs(ugeth->uccf);
1745         dump_regs(ugeth);
1746         dump_bds(ugeth);
1747 #endif
1748 }
1749
1750 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
1751                                                        ugeth,
1752                                                        enum enet_addr_type
1753                                                        enet_addr_type)
1754 {
1755         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
1756         struct ucc_fast_private *uccf;
1757         enum comm_dir comm_dir;
1758         struct list_head *p_lh;
1759         u16 i, num;
1760         u32 __iomem *addr_h;
1761         u32 __iomem *addr_l;
1762         u8 *p_counter;
1763
1764         uccf = ugeth->uccf;
1765
1766         p_82xx_addr_filt =
1767             (struct ucc_geth_82xx_address_filtering_pram __iomem *)
1768             ugeth->p_rx_glbl_pram->addressfiltering;
1769
1770         if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
1771                 addr_h = &(p_82xx_addr_filt->gaddr_h);
1772                 addr_l = &(p_82xx_addr_filt->gaddr_l);
1773                 p_lh = &ugeth->group_hash_q;
1774                 p_counter = &(ugeth->numGroupAddrInHash);
1775         } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
1776                 addr_h = &(p_82xx_addr_filt->iaddr_h);
1777                 addr_l = &(p_82xx_addr_filt->iaddr_l);
1778                 p_lh = &ugeth->ind_hash_q;
1779                 p_counter = &(ugeth->numIndAddrInHash);
1780         } else
1781                 return -EINVAL;
1782
1783         comm_dir = 0;
1784         if (uccf->enabled_tx)
1785                 comm_dir |= COMM_DIR_TX;
1786         if (uccf->enabled_rx)
1787                 comm_dir |= COMM_DIR_RX;
1788         if (comm_dir)
1789                 ugeth_disable(ugeth, comm_dir);
1790
1791         /* Clear the hash table. */
1792         out_be32(addr_h, 0x00000000);
1793         out_be32(addr_l, 0x00000000);
1794
1795         if (!p_lh)
1796                 return 0;
1797
1798         num = *p_counter;
1799
1800         /* Delete all remaining CQ elements */
1801         for (i = 0; i < num; i++)
1802                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
1803
1804         *p_counter = 0;
1805
1806         if (comm_dir)
1807                 ugeth_enable(ugeth, comm_dir);
1808
1809         return 0;
1810 }
1811
1812 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
1813                                                     u8 paddr_num)
1814 {
1815         ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
1816         return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
1817 }
1818
1819 static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
1820 {
1821         u16 i, j;
1822         u8 __iomem *bd;
1823
1824         if (!ugeth)
1825                 return;
1826
1827         if (ugeth->uccf) {
1828                 ucc_fast_free(ugeth->uccf);
1829                 ugeth->uccf = NULL;
1830         }
1831
1832         if (ugeth->p_thread_data_tx) {
1833                 qe_muram_free(ugeth->thread_dat_tx_offset);
1834                 ugeth->p_thread_data_tx = NULL;
1835         }
1836         if (ugeth->p_thread_data_rx) {
1837                 qe_muram_free(ugeth->thread_dat_rx_offset);
1838                 ugeth->p_thread_data_rx = NULL;
1839         }
1840         if (ugeth->p_exf_glbl_param) {
1841                 qe_muram_free(ugeth->exf_glbl_param_offset);
1842                 ugeth->p_exf_glbl_param = NULL;
1843         }
1844         if (ugeth->p_rx_glbl_pram) {
1845                 qe_muram_free(ugeth->rx_glbl_pram_offset);
1846                 ugeth->p_rx_glbl_pram = NULL;
1847         }
1848         if (ugeth->p_tx_glbl_pram) {
1849                 qe_muram_free(ugeth->tx_glbl_pram_offset);
1850                 ugeth->p_tx_glbl_pram = NULL;
1851         }
1852         if (ugeth->p_send_q_mem_reg) {
1853                 qe_muram_free(ugeth->send_q_mem_reg_offset);
1854                 ugeth->p_send_q_mem_reg = NULL;
1855         }
1856         if (ugeth->p_scheduler) {
1857                 qe_muram_free(ugeth->scheduler_offset);
1858                 ugeth->p_scheduler = NULL;
1859         }
1860         if (ugeth->p_tx_fw_statistics_pram) {
1861                 qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
1862                 ugeth->p_tx_fw_statistics_pram = NULL;
1863         }
1864         if (ugeth->p_rx_fw_statistics_pram) {
1865                 qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
1866                 ugeth->p_rx_fw_statistics_pram = NULL;
1867         }
1868         if (ugeth->p_rx_irq_coalescing_tbl) {
1869                 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
1870                 ugeth->p_rx_irq_coalescing_tbl = NULL;
1871         }
1872         if (ugeth->p_rx_bd_qs_tbl) {
1873                 qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
1874                 ugeth->p_rx_bd_qs_tbl = NULL;
1875         }
1876         if (ugeth->p_init_enet_param_shadow) {
1877                 return_init_enet_entries(ugeth,
1878                                          &(ugeth->p_init_enet_param_shadow->
1879                                            rxthread[0]),
1880                                          ENET_INIT_PARAM_MAX_ENTRIES_RX,
1881                                          ugeth->ug_info->riscRx, 1);
1882                 return_init_enet_entries(ugeth,
1883                                          &(ugeth->p_init_enet_param_shadow->
1884                                            txthread[0]),
1885                                          ENET_INIT_PARAM_MAX_ENTRIES_TX,
1886                                          ugeth->ug_info->riscTx, 0);
1887                 kfree(ugeth->p_init_enet_param_shadow);
1888                 ugeth->p_init_enet_param_shadow = NULL;
1889         }
1890         for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1891                 bd = ugeth->p_tx_bd_ring[i];
1892                 if (!bd)
1893                         continue;
1894                 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
1895                         if (ugeth->tx_skbuff[i][j]) {
1896                                 dma_unmap_single(ugeth->dev,
1897                                                  in_be32(&((struct qe_bd __iomem *)bd)->buf),
1898                                                  (in_be32((u32 __iomem *)bd) &
1899                                                   BD_LENGTH_MASK),
1900                                                  DMA_TO_DEVICE);
1901                                 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
1902                                 ugeth->tx_skbuff[i][j] = NULL;
1903                         }
1904                 }
1905
1906                 kfree(ugeth->tx_skbuff[i]);
1907
1908                 if (ugeth->p_tx_bd_ring[i]) {
1909                         if (ugeth->ug_info->uf_info.bd_mem_part ==
1910                             MEM_PART_SYSTEM)
1911                                 kfree((void *)ugeth->tx_bd_ring_offset[i]);
1912                         else if (ugeth->ug_info->uf_info.bd_mem_part ==
1913                                  MEM_PART_MURAM)
1914                                 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
1915                         ugeth->p_tx_bd_ring[i] = NULL;
1916                 }
1917         }
1918         for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1919                 if (ugeth->p_rx_bd_ring[i]) {
1920                         /* Return existing data buffers in ring */
1921                         bd = ugeth->p_rx_bd_ring[i];
1922                         for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
1923                                 if (ugeth->rx_skbuff[i][j]) {
1924                                         dma_unmap_single(ugeth->dev,
1925                                                 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1926                                                 ugeth->ug_info->
1927                                                 uf_info.max_rx_buf_length +
1928                                                 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
1929                                                 DMA_FROM_DEVICE);
1930                                         dev_kfree_skb_any(
1931                                                 ugeth->rx_skbuff[i][j]);
1932                                         ugeth->rx_skbuff[i][j] = NULL;
1933                                 }
1934                                 bd += sizeof(struct qe_bd);
1935                         }
1936
1937                         kfree(ugeth->rx_skbuff[i]);
1938
1939                         if (ugeth->ug_info->uf_info.bd_mem_part ==
1940                             MEM_PART_SYSTEM)
1941                                 kfree((void *)ugeth->rx_bd_ring_offset[i]);
1942                         else if (ugeth->ug_info->uf_info.bd_mem_part ==
1943                                  MEM_PART_MURAM)
1944                                 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
1945                         ugeth->p_rx_bd_ring[i] = NULL;
1946                 }
1947         }
1948         while (!list_empty(&ugeth->group_hash_q))
1949                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1950                                         (dequeue(&ugeth->group_hash_q)));
1951         while (!list_empty(&ugeth->ind_hash_q))
1952                 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1953                                         (dequeue(&ugeth->ind_hash_q)));
1954         if (ugeth->ug_regs) {
1955                 iounmap(ugeth->ug_regs);
1956                 ugeth->ug_regs = NULL;
1957         }
1958
1959         skb_queue_purge(&ugeth->rx_recycle);
1960 }
1961
1962 static void ucc_geth_set_multi(struct net_device *dev)
1963 {
1964         struct ucc_geth_private *ugeth;
1965         struct dev_mc_list *dmi;
1966         struct ucc_fast __iomem *uf_regs;
1967         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
1968         int i;
1969
1970         ugeth = netdev_priv(dev);
1971
1972         uf_regs = ugeth->uccf->uf_regs;
1973
1974         if (dev->flags & IFF_PROMISC) {
1975                 setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
1976         } else {
1977                 clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
1978
1979                 p_82xx_addr_filt =
1980                     (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
1981                     p_rx_glbl_pram->addressfiltering;
1982
1983                 if (dev->flags & IFF_ALLMULTI) {
1984                         /* Catch all multicast addresses, so set the
1985                          * filter to all 1's.
1986                          */
1987                         out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
1988                         out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
1989                 } else {
1990                         /* Clear filter and add the addresses in the list.
1991                          */
1992                         out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
1993                         out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
1994
1995                         dmi = dev->mc_list;
1996
1997                         for (i = 0; i < dev->mc_count; i++, dmi = dmi->next) {
1998
1999                                 /* Only support group multicast for now.
2000                                  */
2001                                 if (!(dmi->dmi_addr[0] & 1))
2002                                         continue;
2003
2004                                 /* Ask CPM to run CRC and set bit in
2005                                  * filter mask.
2006                                  */
2007                                 hw_add_addr_in_hash(ugeth, dmi->dmi_addr);
2008                         }
2009                 }
2010         }
2011 }
2012
2013 static void ucc_geth_stop(struct ucc_geth_private *ugeth)
2014 {
2015         struct ucc_geth __iomem *ug_regs = ugeth->ug_regs;
2016         struct phy_device *phydev = ugeth->phydev;
2017
2018         ugeth_vdbg("%s: IN", __func__);
2019
2020         /* Disable the controller */
2021         ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2022
2023         /* Tell the kernel the link is down */
2024         phy_stop(phydev);
2025
2026         /* Mask all interrupts */
2027         out_be32(ugeth->uccf->p_uccm, 0x00000000);
2028
2029         /* Clear all interrupts */
2030         out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2031
2032         /* Disable Rx and Tx */
2033         clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2034
2035         phy_disconnect(ugeth->phydev);
2036         ugeth->phydev = NULL;
2037
2038         ucc_geth_memclean(ugeth);
2039 }
2040
2041 static int ucc_struct_init(struct ucc_geth_private *ugeth)
2042 {
2043         struct ucc_geth_info *ug_info;
2044         struct ucc_fast_info *uf_info;
2045         int i;
2046
2047         ug_info = ugeth->ug_info;
2048         uf_info = &ug_info->uf_info;
2049
2050         if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2051               (uf_info->bd_mem_part == MEM_PART_MURAM))) {
2052                 if (netif_msg_probe(ugeth))
2053                         ugeth_err("%s: Bad memory partition value.",
2054                                         __func__);
2055                 return -EINVAL;
2056         }
2057
2058         /* Rx BD lengths */
2059         for (i = 0; i < ug_info->numQueuesRx; i++) {
2060                 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2061                     (ug_info->bdRingLenRx[i] %
2062                      UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
2063                         if (netif_msg_probe(ugeth))
2064                                 ugeth_err
2065                                     ("%s: Rx BD ring length must be multiple of 4, no smaller than 8.",
2066                                         __func__);
2067                         return -EINVAL;
2068                 }
2069         }
2070
2071         /* Tx BD lengths */
2072         for (i = 0; i < ug_info->numQueuesTx; i++) {
2073                 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
2074                         if (netif_msg_probe(ugeth))
2075                                 ugeth_err
2076                                     ("%s: Tx BD ring length must be no smaller than 2.",
2077                                      __func__);
2078                         return -EINVAL;
2079                 }
2080         }
2081
2082         /* mrblr */
2083         if ((uf_info->max_rx_buf_length == 0) ||
2084             (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
2085                 if (netif_msg_probe(ugeth))
2086                         ugeth_err
2087                             ("%s: max_rx_buf_length must be non-zero multiple of 128.",
2088                              __func__);
2089                 return -EINVAL;
2090         }
2091
2092         /* num Tx queues */
2093         if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
2094                 if (netif_msg_probe(ugeth))
2095                         ugeth_err("%s: number of tx queues too large.", __func__);
2096                 return -EINVAL;
2097         }
2098
2099         /* num Rx queues */
2100         if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
2101                 if (netif_msg_probe(ugeth))
2102                         ugeth_err("%s: number of rx queues too large.", __func__);
2103                 return -EINVAL;
2104         }
2105
2106         /* l2qt */
2107         for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2108                 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
2109                         if (netif_msg_probe(ugeth))
2110                                 ugeth_err
2111                                     ("%s: VLAN priority table entry must not be"
2112                                         " larger than number of Rx queues.",
2113                                      __func__);
2114                         return -EINVAL;
2115                 }
2116         }
2117
2118         /* l3qt */
2119         for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2120                 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
2121                         if (netif_msg_probe(ugeth))
2122                                 ugeth_err
2123                                     ("%s: IP priority table entry must not be"
2124                                         " larger than number of Rx queues.",
2125                                      __func__);
2126                         return -EINVAL;
2127                 }
2128         }
2129
2130         if (ug_info->cam && !ug_info->ecamptr) {
2131                 if (netif_msg_probe(ugeth))
2132                         ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
2133                                   __func__);
2134                 return -EINVAL;
2135         }
2136
2137         if ((ug_info->numStationAddresses !=
2138              UCC_GETH_NUM_OF_STATION_ADDRESSES_1)
2139             && ug_info->rxExtendedFiltering) {
2140                 if (netif_msg_probe(ugeth))
2141                         ugeth_err("%s: Number of station addresses greater than 1 "
2142                                   "not allowed in extended parsing mode.",
2143                                   __func__);
2144                 return -EINVAL;
2145         }
2146
2147         /* Generate uccm_mask for receive */
2148         uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2149         for (i = 0; i < ug_info->numQueuesRx; i++)
2150                 uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i);
2151
2152         for (i = 0; i < ug_info->numQueuesTx; i++)
2153                 uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i);
2154         /* Initialize the general fast UCC block. */
2155         if (ucc_fast_init(uf_info, &ugeth->uccf)) {
2156                 if (netif_msg_probe(ugeth))
2157                         ugeth_err("%s: Failed to init uccf.", __func__);
2158                 return -ENOMEM;
2159         }
2160
2161         /* read the number of risc engines, update the riscTx and riscRx
2162          * if there are 4 riscs in QE
2163          */
2164         if (qe_get_num_of_risc() == 4) {
2165                 ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS;
2166                 ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS;
2167         }
2168
2169         ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs));
2170         if (!ugeth->ug_regs) {
2171                 if (netif_msg_probe(ugeth))
2172                         ugeth_err("%s: Failed to ioremap regs.", __func__);
2173                 return -ENOMEM;
2174         }
2175
2176         skb_queue_head_init(&ugeth->rx_recycle);
2177
2178         return 0;
2179 }
2180
2181 static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2182 {
2183         struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2184         struct ucc_geth_init_pram __iomem *p_init_enet_pram;
2185         struct ucc_fast_private *uccf;
2186         struct ucc_geth_info *ug_info;
2187         struct ucc_fast_info *uf_info;
2188         struct ucc_fast __iomem *uf_regs;
2189         struct ucc_geth __iomem *ug_regs;
2190         int ret_val = -EINVAL;
2191         u32 remoder = UCC_GETH_REMODER_INIT;
2192         u32 init_enet_pram_offset, cecr_subblock, command;
2193         u32 ifstat, i, j, size, l2qt, l3qt, length;
2194         u16 temoder = UCC_GETH_TEMODER_INIT;
2195         u16 test;
2196         u8 function_code = 0;
2197         u8 __iomem *bd;
2198         u8 __iomem *endOfRing;
2199         u8 numThreadsRxNumerical, numThreadsTxNumerical;
2200
2201         ugeth_vdbg("%s: IN", __func__);
2202         uccf = ugeth->uccf;
2203         ug_info = ugeth->ug_info;
2204         uf_info = &ug_info->uf_info;
2205         uf_regs = uccf->uf_regs;
2206         ug_regs = ugeth->ug_regs;
2207
2208         switch (ug_info->numThreadsRx) {
2209         case UCC_GETH_NUM_OF_THREADS_1:
2210                 numThreadsRxNumerical = 1;
2211                 break;
2212         case UCC_GETH_NUM_OF_THREADS_2:
2213                 numThreadsRxNumerical = 2;
2214                 break;
2215         case UCC_GETH_NUM_OF_THREADS_4:
2216                 numThreadsRxNumerical = 4;
2217                 break;
2218         case UCC_GETH_NUM_OF_THREADS_6:
2219                 numThreadsRxNumerical = 6;
2220                 break;
2221         case UCC_GETH_NUM_OF_THREADS_8:
2222                 numThreadsRxNumerical = 8;
2223                 break;
2224         default:
2225                 if (netif_msg_ifup(ugeth))
2226                         ugeth_err("%s: Bad number of Rx threads value.",
2227                                         __func__);
2228                 return -EINVAL;
2229                 break;
2230         }
2231
2232         switch (ug_info->numThreadsTx) {
2233         case UCC_GETH_NUM_OF_THREADS_1:
2234                 numThreadsTxNumerical = 1;
2235                 break;
2236         case UCC_GETH_NUM_OF_THREADS_2:
2237                 numThreadsTxNumerical = 2;
2238                 break;
2239         case UCC_GETH_NUM_OF_THREADS_4:
2240                 numThreadsTxNumerical = 4;
2241                 break;
2242         case UCC_GETH_NUM_OF_THREADS_6:
2243                 numThreadsTxNumerical = 6;
2244                 break;
2245         case UCC_GETH_NUM_OF_THREADS_8:
2246                 numThreadsTxNumerical = 8;
2247                 break;
2248         default:
2249                 if (netif_msg_ifup(ugeth))
2250                         ugeth_err("%s: Bad number of Tx threads value.",
2251                                         __func__);
2252                 return -EINVAL;
2253                 break;
2254         }
2255
2256         /* Calculate rx_extended_features */
2257         ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2258             ug_info->ipAddressAlignment ||
2259             (ug_info->numStationAddresses !=
2260              UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2261
2262         ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
2263             (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP)
2264             || (ug_info->vlanOperationNonTagged !=
2265                 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
2266
2267         init_default_reg_vals(&uf_regs->upsmr,
2268                               &ug_regs->maccfg1, &ug_regs->maccfg2);
2269
2270         /*                    Set UPSMR                      */
2271         /* For more details see the hardware spec.           */
2272         init_rx_parameters(ug_info->bro,
2273                            ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2274
2275         /* We're going to ignore other registers for now, */
2276         /* except as needed to get up and running         */
2277
2278         /*                    Set MACCFG1                    */
2279         /* For more details see the hardware spec.           */
2280         init_flow_control_params(ug_info->aufc,
2281                                  ug_info->receiveFlowControl,
2282                                  ug_info->transmitFlowControl,
2283                                  ug_info->pausePeriod,
2284                                  ug_info->extensionField,
2285                                  &uf_regs->upsmr,
2286                                  &ug_regs->uempr, &ug_regs->maccfg1);
2287
2288         setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
2289
2290         /*                    Set IPGIFG                     */
2291         /* For more details see the hardware spec.           */
2292         ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2293                                               ug_info->nonBackToBackIfgPart2,
2294                                               ug_info->
2295                                               miminumInterFrameGapEnforcement,
2296                                               ug_info->backToBackInterFrameGap,
2297                                               &ug_regs->ipgifg);
2298         if (ret_val != 0) {
2299                 if (netif_msg_ifup(ugeth))
2300                         ugeth_err("%s: IPGIFG initialization parameter too large.",
2301                                   __func__);
2302                 return ret_val;
2303         }
2304
2305         /*                    Set HAFDUP                     */
2306         /* For more details see the hardware spec.           */
2307         ret_val = init_half_duplex_params(ug_info->altBeb,
2308                                           ug_info->backPressureNoBackoff,
2309                                           ug_info->noBackoff,
2310                                           ug_info->excessDefer,
2311                                           ug_info->altBebTruncation,
2312                                           ug_info->maxRetransmission,
2313                                           ug_info->collisionWindow,
2314                                           &ug_regs->hafdup);
2315         if (ret_val != 0) {
2316                 if (netif_msg_ifup(ugeth))
2317                         ugeth_err("%s: Half Duplex initialization parameter too large.",
2318                           __func__);
2319                 return ret_val;
2320         }
2321
2322         /*                    Set IFSTAT                     */
2323         /* For more details see the hardware spec.           */
2324         /* Read only - resets upon read                      */
2325         ifstat = in_be32(&ug_regs->ifstat);
2326
2327         /*                    Clear UEMPR                    */
2328         /* For more details see the hardware spec.           */
2329         out_be32(&ug_regs->uempr, 0);
2330
2331         /*                    Set UESCR                      */
2332         /* For more details see the hardware spec.           */
2333         init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2334                                 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2335                                 0, &uf_regs->upsmr, &ug_regs->uescr);
2336
2337         /* Allocate Tx bds */
2338         for (j = 0; j < ug_info->numQueuesTx; j++) {
2339                 /* Allocate in multiple of
2340                    UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2341                    according to spec */
2342                 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
2343                           / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2344                     * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2345                 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
2346                     UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2347                         length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2348                 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2349                         u32 align = 4;
2350                         if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2351                                 align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2352                         ugeth->tx_bd_ring_offset[j] =
2353                                 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2354
2355                         if (ugeth->tx_bd_ring_offset[j] != 0)
2356                                 ugeth->p_tx_bd_ring[j] =
2357                                         (u8 __iomem *)((ugeth->tx_bd_ring_offset[j] +
2358                                         align) & ~(align - 1));
2359                 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2360                         ugeth->tx_bd_ring_offset[j] =
2361                             qe_muram_alloc(length,
2362                                            UCC_GETH_TX_BD_RING_ALIGNMENT);
2363                         if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j]))
2364                                 ugeth->p_tx_bd_ring[j] =
2365                                     (u8 __iomem *) qe_muram_addr(ugeth->
2366                                                          tx_bd_ring_offset[j]);
2367                 }
2368                 if (!ugeth->p_tx_bd_ring[j]) {
2369                         if (netif_msg_ifup(ugeth))
2370                                 ugeth_err
2371                                     ("%s: Can not allocate memory for Tx bd rings.",
2372                                      __func__);
2373                         return -ENOMEM;
2374                 }
2375                 /* Zero unused end of bd ring, according to spec */
2376                 memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] +
2377                        ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0,
2378                        length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
2379         }
2380
2381         /* Allocate Rx bds */
2382         for (j = 0; j < ug_info->numQueuesRx; j++) {
2383                 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
2384                 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2385                         u32 align = 4;
2386                         if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2387                                 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2388                         ugeth->rx_bd_ring_offset[j] =
2389                                 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
2390                         if (ugeth->rx_bd_ring_offset[j] != 0)
2391                                 ugeth->p_rx_bd_ring[j] =
2392                                         (u8 __iomem *)((ugeth->rx_bd_ring_offset[j] +
2393                                         align) & ~(align - 1));
2394                 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2395                         ugeth->rx_bd_ring_offset[j] =
2396                             qe_muram_alloc(length,
2397                                            UCC_GETH_RX_BD_RING_ALIGNMENT);
2398                         if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j]))
2399                                 ugeth->p_rx_bd_ring[j] =
2400                                     (u8 __iomem *) qe_muram_addr(ugeth->
2401                                                          rx_bd_ring_offset[j]);
2402                 }
2403                 if (!ugeth->p_rx_bd_ring[j]) {
2404                         if (netif_msg_ifup(ugeth))
2405                                 ugeth_err
2406                                     ("%s: Can not allocate memory for Rx bd rings.",
2407                                      __func__);
2408                         return -ENOMEM;
2409                 }
2410         }
2411
2412         /* Init Tx bds */
2413         for (j = 0; j < ug_info->numQueuesTx; j++) {
2414                 /* Setup the skbuff rings */
2415                 ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2416                                               ugeth->ug_info->bdRingLenTx[j],
2417                                               GFP_KERNEL);
2418
2419                 if (ugeth->tx_skbuff[j] == NULL) {
2420                         if (netif_msg_ifup(ugeth))
2421                                 ugeth_err("%s: Could not allocate tx_skbuff",
2422                                           __func__);
2423                         return -ENOMEM;
2424                 }
2425
2426                 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2427                         ugeth->tx_skbuff[j][i] = NULL;
2428
2429                 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2430                 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2431                 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
2432                         /* clear bd buffer */
2433                         out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2434                         /* set bd status and length */
2435                         out_be32((u32 __iomem *)bd, 0);
2436                         bd += sizeof(struct qe_bd);
2437                 }
2438                 bd -= sizeof(struct qe_bd);
2439                 /* set bd status and length */
2440                 out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */
2441         }
2442
2443         /* Init Rx bds */
2444         for (j = 0; j < ug_info->numQueuesRx; j++) {
2445                 /* Setup the skbuff rings */
2446                 ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2447                                               ugeth->ug_info->bdRingLenRx[j],
2448                                               GFP_KERNEL);
2449
2450                 if (ugeth->rx_skbuff[j] == NULL) {
2451                         if (netif_msg_ifup(ugeth))
2452                                 ugeth_err("%s: Could not allocate rx_skbuff",
2453                                           __func__);
2454                         return -ENOMEM;
2455                 }
2456
2457                 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2458                         ugeth->rx_skbuff[j][i] = NULL;
2459
2460                 ugeth->skb_currx[j] = 0;
2461                 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2462                 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
2463                         /* set bd status and length */
2464                         out_be32((u32 __iomem *)bd, R_I);
2465                         /* clear bd buffer */
2466                         out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
2467                         bd += sizeof(struct qe_bd);
2468                 }
2469                 bd -= sizeof(struct qe_bd);
2470                 /* set bd status and length */
2471                 out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */
2472         }
2473
2474         /*
2475          * Global PRAM
2476          */
2477         /* Tx global PRAM */
2478         /* Allocate global tx parameter RAM page */
2479         ugeth->tx_glbl_pram_offset =
2480             qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
2481                            UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
2482         if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) {
2483                 if (netif_msg_ifup(ugeth))
2484                         ugeth_err
2485                             ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
2486                              __func__);
2487                 return -ENOMEM;
2488         }
2489         ugeth->p_tx_glbl_pram =
2490             (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth->
2491                                                         tx_glbl_pram_offset);
2492         /* Zero out p_tx_glbl_pram */
2493         memset_io((void __iomem *)ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
2494
2495         /* Fill global PRAM */
2496
2497         /* TQPTR */
2498         /* Size varies with number of Tx threads */
2499         ugeth->thread_dat_tx_offset =
2500             qe_muram_alloc(numThreadsTxNumerical *
2501                            sizeof(struct ucc_geth_thread_data_tx) +
2502                            32 * (numThreadsTxNumerical == 1),
2503                            UCC_GETH_THREAD_DATA_ALIGNMENT);
2504         if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
2505                 if (netif_msg_ifup(ugeth))
2506                         ugeth_err
2507                             ("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
2508                              __func__);
2509                 return -ENOMEM;
2510         }
2511
2512         ugeth->p_thread_data_tx =
2513             (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth->
2514                                                         thread_dat_tx_offset);
2515         out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2516
2517         /* vtagtable */
2518         for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
2519                 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2520                          ug_info->vtagtable[i]);
2521
2522         /* iphoffset */
2523         for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
2524                 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i],
2525                                 ug_info->iphoffset[i]);
2526
2527         /* SQPTR */
2528         /* Size varies with number of Tx queues */
2529         ugeth->send_q_mem_reg_offset =
2530             qe_muram_alloc(ug_info->numQueuesTx *
2531                            sizeof(struct ucc_geth_send_queue_qd),
2532                            UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
2533         if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
2534                 if (netif_msg_ifup(ugeth))
2535                         ugeth_err
2536                             ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
2537                              __func__);
2538                 return -ENOMEM;
2539         }
2540
2541         ugeth->p_send_q_mem_reg =
2542             (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth->
2543                         send_q_mem_reg_offset);
2544         out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2545
2546         /* Setup the table */
2547         /* Assume BD rings are already established */
2548         for (i = 0; i < ug_info->numQueuesTx; i++) {
2549                 endOfRing =
2550                     ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
2551                                               1) * sizeof(struct qe_bd);
2552                 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2553                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2554                                  (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2555                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2556                                  last_bd_completed_address,
2557                                  (u32) virt_to_phys(endOfRing));
2558                 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2559                            MEM_PART_MURAM) {
2560                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2561                                  (u32) immrbar_virt_to_phys(ugeth->
2562                                                             p_tx_bd_ring[i]));
2563                         out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2564                                  last_bd_completed_address,
2565                                  (u32) immrbar_virt_to_phys(endOfRing));
2566                 }
2567         }
2568
2569         /* schedulerbasepointer */
2570
2571         if (ug_info->numQueuesTx > 1) {
2572         /* scheduler exists only if more than 1 tx queue */
2573                 ugeth->scheduler_offset =
2574                     qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
2575                                    UCC_GETH_SCHEDULER_ALIGNMENT);
2576                 if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
2577                         if (netif_msg_ifup(ugeth))
2578                                 ugeth_err
2579                                  ("%s: Can not allocate DPRAM memory for p_scheduler.",
2580                                      __func__);
2581                         return -ENOMEM;
2582                 }
2583
2584                 ugeth->p_scheduler =
2585                     (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth->
2586                                                            scheduler_offset);
2587                 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2588                          ugeth->scheduler_offset);
2589                 /* Zero out p_scheduler */
2590                 memset_io((void __iomem *)ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
2591
2592                 /* Set values in scheduler */
2593                 out_be32(&ugeth->p_scheduler->mblinterval,
2594                          ug_info->mblinterval);
2595                 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2596                          ug_info->nortsrbytetime);
2597                 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz);
2598                 out_8(&ugeth->p_scheduler->strictpriorityq,
2599                                 ug_info->strictpriorityq);
2600                 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap);
2601                 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw);
2602                 for (i = 0; i < NUM_TX_QUEUES; i++)
2603                         out_8(&ugeth->p_scheduler->weightfactor[i],
2604                             ug_info->weightfactor[i]);
2605
2606                 /* Set pointers to cpucount registers in scheduler */
2607                 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2608                 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2609                 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2610                 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2611                 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2612                 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2613                 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2614                 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2615         }
2616
2617         /* schedulerbasepointer */
2618         /* TxRMON_PTR (statistics) */
2619         if (ug_info->
2620             statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
2621                 ugeth->tx_fw_statistics_pram_offset =
2622                     qe_muram_alloc(sizeof
2623                                    (struct ucc_geth_tx_firmware_statistics_pram),
2624                                    UCC_GETH_TX_STATISTICS_ALIGNMENT);
2625                 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
2626                         if (netif_msg_ifup(ugeth))
2627                                 ugeth_err
2628                                     ("%s: Can not allocate DPRAM memory for"
2629                                         " p_tx_fw_statistics_pram.",
2630                                         __func__);
2631                         return -ENOMEM;
2632                 }
2633                 ugeth->p_tx_fw_statistics_pram =
2634                     (struct ucc_geth_tx_firmware_statistics_pram __iomem *)
2635                     qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2636                 /* Zero out p_tx_fw_statistics_pram */
2637                 memset_io((void __iomem *)ugeth->p_tx_fw_statistics_pram,
2638                        0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
2639         }
2640
2641         /* temoder */
2642         /* Already has speed set */
2643
2644         if (ug_info->numQueuesTx > 1)
2645                 temoder |= TEMODER_SCHEDULER_ENABLE;
2646         if (ug_info->ipCheckSumGenerate)
2647                 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
2648         temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2649         out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2650
2651         test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
2652
2653         /* Function code register value to be used later */
2654         function_code = UCC_BMR_BO_BE | UCC_BMR_GBL;
2655         /* Required for QE */
2656
2657         /* function code register */
2658         out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2659
2660         /* Rx global PRAM */
2661         /* Allocate global rx parameter RAM page */
2662         ugeth->rx_glbl_pram_offset =
2663             qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
2664                            UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
2665         if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) {
2666                 if (netif_msg_ifup(ugeth))
2667                         ugeth_err
2668                             ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
2669                              __func__);
2670                 return -ENOMEM;
2671         }
2672         ugeth->p_rx_glbl_pram =
2673             (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth->
2674                                                         rx_glbl_pram_offset);
2675         /* Zero out p_rx_glbl_pram */
2676         memset_io((void __iomem *)ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
2677
2678         /* Fill global PRAM */
2679
2680         /* RQPTR */
2681         /* Size varies with number of Rx threads */
2682         ugeth->thread_dat_rx_offset =
2683             qe_muram_alloc(numThreadsRxNumerical *
2684                            sizeof(struct ucc_geth_thread_data_rx),
2685                            UCC_GETH_THREAD_DATA_ALIGNMENT);
2686         if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
2687                 if (netif_msg_ifup(ugeth))
2688                         ugeth_err
2689                             ("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
2690                              __func__);
2691                 return -ENOMEM;
2692         }
2693
2694         ugeth->p_thread_data_rx =
2695             (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth->
2696                                                         thread_dat_rx_offset);
2697         out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2698
2699         /* typeorlen */
2700         out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2701
2702         /* rxrmonbaseptr (statistics) */
2703         if (ug_info->
2704             statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
2705                 ugeth->rx_fw_statistics_pram_offset =
2706                     qe_muram_alloc(sizeof
2707                                    (struct ucc_geth_rx_firmware_statistics_pram),
2708                                    UCC_GETH_RX_STATISTICS_ALIGNMENT);
2709                 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
2710                         if (netif_msg_ifup(ugeth))
2711                                 ugeth_err
2712                                         ("%s: Can not allocate DPRAM memory for"
2713                                         " p_rx_fw_statistics_pram.", __func__);
2714                         return -ENOMEM;
2715                 }
2716                 ugeth->p_rx_fw_statistics_pram =
2717                     (struct ucc_geth_rx_firmware_statistics_pram __iomem *)
2718                     qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2719                 /* Zero out p_rx_fw_statistics_pram */
2720                 memset_io((void __iomem *)ugeth->p_rx_fw_statistics_pram, 0,
2721                        sizeof(struct ucc_geth_rx_firmware_statistics_pram));
2722         }
2723
2724         /* intCoalescingPtr */
2725
2726         /* Size varies with number of Rx queues */
2727         ugeth->rx_irq_coalescing_tbl_offset =
2728             qe_muram_alloc(ug_info->numQueuesRx *
2729                            sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
2730                            + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
2731         if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
2732                 if (netif_msg_ifup(ugeth))
2733                         ugeth_err
2734                             ("%s: Can not allocate DPRAM memory for"
2735                                 " p_rx_irq_coalescing_tbl.", __func__);
2736                 return -ENOMEM;
2737         }
2738
2739         ugeth->p_rx_irq_coalescing_tbl =
2740             (struct ucc_geth_rx_interrupt_coalescing_table __iomem *)
2741             qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
2742         out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
2743                  ugeth->rx_irq_coalescing_tbl_offset);
2744
2745         /* Fill interrupt coalescing table */
2746         for (i = 0; i < ug_info->numQueuesRx; i++) {
2747                 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2748                          interruptcoalescingmaxvalue,
2749                          ug_info->interruptcoalescingmaxvalue[i]);
2750                 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2751                          interruptcoalescingcounter,
2752                          ug_info->interruptcoalescingmaxvalue[i]);
2753         }
2754
2755         /* MRBLR */
2756         init_max_rx_buff_len(uf_info->max_rx_buf_length,
2757                              &ugeth->p_rx_glbl_pram->mrblr);
2758         /* MFLR */
2759         out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
2760         /* MINFLR */
2761         init_min_frame_len(ug_info->minFrameLength,
2762                            &ugeth->p_rx_glbl_pram->minflr,
2763                            &ugeth->p_rx_glbl_pram->mrblr);
2764         /* MAXD1 */
2765         out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
2766         /* MAXD2 */
2767         out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
2768
2769         /* l2qt */
2770         l2qt = 0;
2771         for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
2772                 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
2773         out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
2774
2775         /* l3qt */
2776         for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
2777                 l3qt = 0;
2778                 for (i = 0; i < 8; i++)
2779                         l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
2780                 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
2781         }
2782
2783         /* vlantype */
2784         out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
2785
2786         /* vlantci */
2787         out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
2788
2789         /* ecamptr */
2790         out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
2791
2792         /* RBDQPTR */
2793         /* Size varies with number of Rx queues */
2794         ugeth->rx_bd_qs_tbl_offset =
2795             qe_muram_alloc(ug_info->numQueuesRx *
2796                            (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2797                             sizeof(struct ucc_geth_rx_prefetched_bds)),
2798                            UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
2799         if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
2800                 if (netif_msg_ifup(ugeth))
2801                         ugeth_err
2802                             ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
2803                              __func__);
2804                 return -ENOMEM;
2805         }
2806
2807         ugeth->p_rx_bd_qs_tbl =
2808             (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth->
2809                                     rx_bd_qs_tbl_offset);
2810         out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
2811         /* Zero out p_rx_bd_qs_tbl */
2812         memset_io((void __iomem *)ugeth->p_rx_bd_qs_tbl,
2813                0,
2814                ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2815                                        sizeof(struct ucc_geth_rx_prefetched_bds)));
2816
2817         /* Setup the table */
2818         /* Assume BD rings are already established */
2819         for (i = 0; i < ug_info->numQueuesRx; i++) {
2820                 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2821                         out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2822                                  (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
2823                 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2824                            MEM_PART_MURAM) {
2825                         out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2826                                  (u32) immrbar_virt_to_phys(ugeth->
2827                                                             p_rx_bd_ring[i]));
2828                 }
2829                 /* rest of fields handled by QE */
2830         }
2831
2832         /* remoder */
2833         /* Already has speed set */
2834
2835         if (ugeth->rx_extended_features)
2836                 remoder |= REMODER_RX_EXTENDED_FEATURES;
2837         if (ug_info->rxExtendedFiltering)
2838                 remoder |= REMODER_RX_EXTENDED_FILTERING;
2839         if (ug_info->dynamicMaxFrameLength)
2840                 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
2841         if (ug_info->dynamicMinFrameLength)
2842                 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
2843         remoder |=
2844             ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
2845         remoder |=
2846             ug_info->
2847             vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
2848         remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
2849         remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
2850         if (ug_info->ipCheckSumCheck)
2851                 remoder |= REMODER_IP_CHECKSUM_CHECK;
2852         if (ug_info->ipAddressAlignment)
2853                 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
2854         out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
2855
2856         /* Note that this function must be called */
2857         /* ONLY AFTER p_tx_fw_statistics_pram */
2858         /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
2859         init_firmware_statistics_gathering_mode((ug_info->
2860                 statisticsMode &
2861                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
2862                 (ug_info->statisticsMode &
2863                 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
2864                 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
2865                 ugeth->tx_fw_statistics_pram_offset,
2866                 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
2867                 ugeth->rx_fw_statistics_pram_offset,
2868                 &ugeth->p_tx_glbl_pram->temoder,
2869                 &ugeth->p_rx_glbl_pram->remoder);
2870
2871         /* function code register */
2872         out_8(&ugeth->p_rx_glbl_pram->rstate, function_code);
2873
2874         /* initialize extended filtering */
2875         if (ug_info->rxExtendedFiltering) {
2876                 if (!ug_info->extendedFilteringChainPointer) {
2877                         if (netif_msg_ifup(ugeth))
2878                                 ugeth_err("%s: Null Extended Filtering Chain Pointer.",
2879                                           __func__);
2880                         return -EINVAL;
2881                 }
2882
2883                 /* Allocate memory for extended filtering Mode Global
2884                 Parameters */
2885                 ugeth->exf_glbl_param_offset =
2886                     qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
2887                 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
2888                 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
2889                         if (netif_msg_ifup(ugeth))
2890                                 ugeth_err
2891                                         ("%s: Can not allocate DPRAM memory for"
2892                                         " p_exf_glbl_param.", __func__);
2893                         return -ENOMEM;
2894                 }
2895
2896                 ugeth->p_exf_glbl_param =
2897                     (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth->
2898                                  exf_glbl_param_offset);
2899                 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
2900                          ugeth->exf_glbl_param_offset);
2901                 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
2902                          (u32) ug_info->extendedFilteringChainPointer);
2903
2904         } else {                /* initialize 82xx style address filtering */
2905
2906                 /* Init individual address recognition registers to disabled */
2907
2908                 for (j = 0; j < NUM_OF_PADDRS; j++)
2909                         ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
2910
2911                 p_82xx_addr_filt =
2912                     (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
2913                     p_rx_glbl_pram->addressfiltering;
2914
2915                 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2916                         ENET_ADDR_TYPE_GROUP);
2917                 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2918                         ENET_ADDR_TYPE_INDIVIDUAL);
2919         }
2920
2921         /*
2922          * Initialize UCC at QE level
2923          */
2924
2925         command = QE_INIT_TX_RX;
2926
2927         /* Allocate shadow InitEnet command parameter structure.
2928          * This is needed because after the InitEnet command is executed,
2929          * the structure in DPRAM is released, because DPRAM is a premium
2930          * resource.
2931          * This shadow structure keeps a copy of what was done so that the
2932          * allocated resources can be released when the channel is freed.
2933          */
2934         if (!(ugeth->p_init_enet_param_shadow =
2935               kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
2936                 if (netif_msg_ifup(ugeth))
2937                         ugeth_err
2938                             ("%s: Can not allocate memory for"
2939                                 " p_UccInitEnetParamShadows.", __func__);
2940                 return -ENOMEM;
2941         }
2942         /* Zero out *p_init_enet_param_shadow */
2943         memset((char *)ugeth->p_init_enet_param_shadow,
2944                0, sizeof(struct ucc_geth_init_pram));
2945
2946         /* Fill shadow InitEnet command parameter structure */
2947
2948         ugeth->p_init_enet_param_shadow->resinit1 =
2949             ENET_INIT_PARAM_MAGIC_RES_INIT1;
2950         ugeth->p_init_enet_param_shadow->resinit2 =
2951             ENET_INIT_PARAM_MAGIC_RES_INIT2;
2952         ugeth->p_init_enet_param_shadow->resinit3 =
2953             ENET_INIT_PARAM_MAGIC_RES_INIT3;
2954         ugeth->p_init_enet_param_shadow->resinit4 =
2955             ENET_INIT_PARAM_MAGIC_RES_INIT4;
2956         ugeth->p_init_enet_param_shadow->resinit5 =
2957             ENET_INIT_PARAM_MAGIC_RES_INIT5;
2958         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2959             ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
2960         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2961             ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
2962
2963         ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2964             ugeth->rx_glbl_pram_offset | ug_info->riscRx;
2965         if ((ug_info->largestexternallookupkeysize !=
2966              QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE)
2967             && (ug_info->largestexternallookupkeysize !=
2968                 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
2969             && (ug_info->largestexternallookupkeysize !=
2970                 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
2971                 if (netif_msg_ifup(ugeth))
2972                         ugeth_err("%s: Invalid largest External Lookup Key Size.",
2973                                   __func__);
2974                 return -EINVAL;
2975         }
2976         ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
2977             ug_info->largestexternallookupkeysize;
2978         size = sizeof(struct ucc_geth_thread_rx_pram);
2979         if (ug_info->rxExtendedFiltering) {
2980                 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
2981                 if (ug_info->largestexternallookupkeysize ==
2982                     QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
2983                         size +=
2984                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
2985                 if (ug_info->largestexternallookupkeysize ==
2986                     QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
2987                         size +=
2988                             THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
2989         }
2990
2991         if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
2992                 p_init_enet_param_shadow->rxthread[0]),
2993                 (u8) (numThreadsRxNumerical + 1)
2994                 /* Rx needs one extra for terminator */
2995                 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
2996                 ug_info->riscRx, 1)) != 0) {
2997                 if (netif_msg_ifup(ugeth))
2998                                 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
2999                                         __func__);
3000                 return ret_val;
3001         }
3002
3003         ugeth->p_init_enet_param_shadow->txglobal =
3004             ugeth->tx_glbl_pram_offset | ug_info->riscTx;
3005         if ((ret_val =
3006              fill_init_enet_entries(ugeth,
3007                                     &(ugeth->p_init_enet_param_shadow->
3008                                       txthread[0]), numThreadsTxNumerical,
3009                                     sizeof(struct ucc_geth_thread_tx_pram),
3010                                     UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
3011                                     ug_info->riscTx, 0)) != 0) {
3012                 if (netif_msg_ifup(ugeth))
3013                         ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3014                                   __func__);
3015                 return ret_val;
3016         }
3017
3018         /* Load Rx bds with buffers */
3019         for (i = 0; i < ug_info->numQueuesRx; i++) {
3020                 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
3021                         if (netif_msg_ifup(ugeth))
3022                                 ugeth_err("%s: Can not fill Rx bds with buffers.",
3023                                           __func__);
3024                         return ret_val;
3025                 }
3026         }
3027
3028         /* Allocate InitEnet command parameter structure */
3029         init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
3030         if (IS_ERR_VALUE(init_enet_pram_offset)) {
3031                 if (netif_msg_ifup(ugeth))
3032                         ugeth_err
3033                             ("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
3034                              __func__);
3035                 return -ENOMEM;
3036         }
3037         p_init_enet_pram =
3038             (struct ucc_geth_init_pram __iomem *) qe_muram_addr(init_enet_pram_offset);
3039
3040         /* Copy shadow InitEnet command parameter structure into PRAM */
3041         out_8(&p_init_enet_pram->resinit1,
3042                         ugeth->p_init_enet_param_shadow->resinit1);
3043         out_8(&p_init_enet_pram->resinit2,
3044                         ugeth->p_init_enet_param_shadow->resinit2);
3045         out_8(&p_init_enet_pram->resinit3,
3046                         ugeth->p_init_enet_param_shadow->resinit3);
3047         out_8(&p_init_enet_pram->resinit4,
3048                         ugeth->p_init_enet_param_shadow->resinit4);
3049         out_be16(&p_init_enet_pram->resinit5,
3050                  ugeth->p_init_enet_param_shadow->resinit5);
3051         out_8(&p_init_enet_pram->largestexternallookupkeysize,
3052             ugeth->p_init_enet_param_shadow->largestexternallookupkeysize);
3053         out_be32(&p_init_enet_pram->rgftgfrxglobal,
3054                  ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3055         for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
3056                 out_be32(&p_init_enet_pram->rxthread[i],
3057                          ugeth->p_init_enet_param_shadow->rxthread[i]);
3058         out_be32(&p_init_enet_pram->txglobal,
3059                  ugeth->p_init_enet_param_shadow->txglobal);
3060         for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
3061                 out_be32(&p_init_enet_pram->txthread[i],
3062                          ugeth->p_init_enet_param_shadow->txthread[i]);
3063
3064         /* Issue QE command */
3065         cecr_subblock =
3066             ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
3067         qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
3068                      init_enet_pram_offset);
3069
3070         /* Free InitEnet command parameter */
3071         qe_muram_free(init_enet_pram_offset);
3072
3073         return 0;
3074 }
3075
3076 /* This is called by the kernel when a frame is ready for transmission. */
3077 /* It is pointed to by the dev->hard_start_xmit function pointer */
3078 static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3079 {
3080         struct ucc_geth_private *ugeth = netdev_priv(dev);
3081 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3082         struct ucc_fast_private *uccf;
3083 #endif
3084         u8 __iomem *bd;                 /* BD pointer */
3085         u32 bd_status;
3086         u8 txQ = 0;
3087
3088         ugeth_vdbg("%s: IN", __func__);
3089
3090         spin_lock_irq(&ugeth->lock);
3091
3092         dev->stats.tx_bytes += skb->len;
3093
3094         /* Start from the next BD that should be filled */
3095         bd = ugeth->txBd[txQ];
3096         bd_status = in_be32((u32 __iomem *)bd);
3097         /* Save the skb pointer so we can free it later */
3098         ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3099
3100         /* Update the current skb pointer (wrapping if this was the last) */
3101         ugeth->skb_curtx[txQ] =
3102             (ugeth->skb_curtx[txQ] +
3103              1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3104
3105         /* set up the buffer descriptor */
3106         out_be32(&((struct qe_bd __iomem *)bd)->buf,
3107                       dma_map_single(ugeth->dev, skb->data,
3108                               skb->len, DMA_TO_DEVICE));
3109
3110         /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
3111
3112         bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
3113
3114         /* set bd status and length */
3115         out_be32((u32 __iomem *)bd, bd_status);
3116
3117         dev->trans_start = jiffies;
3118
3119         /* Move to next BD in the ring */
3120         if (!(bd_status & T_W))
3121                 bd += sizeof(struct qe_bd);
3122         else
3123                 bd = ugeth->p_tx_bd_ring[txQ];
3124
3125         /* If the next BD still needs to be cleaned up, then the bds
3126            are full.  We need to tell the kernel to stop sending us stuff. */
3127         if (bd == ugeth->confBd[txQ]) {
3128                 if (!netif_queue_stopped(dev))
3129                         netif_stop_queue(dev);
3130         }
3131
3132         ugeth->txBd[txQ] = bd;
3133
3134         if (ugeth->p_scheduler) {
3135                 ugeth->cpucount[txQ]++;
3136                 /* Indicate to QE that there are more Tx bds ready for
3137                 transmission */
3138                 /* This is done by writing a running counter of the bd
3139                 count to the scheduler PRAM. */
3140                 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3141         }
3142
3143 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3144         uccf = ugeth->uccf;
3145         out_be16(uccf->p_utodr, UCC_FAST_TOD);
3146 #endif
3147         spin_unlock_irq(&ugeth->lock);
3148
3149         return NETDEV_TX_OK;
3150 }
3151
3152 static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
3153 {
3154         struct sk_buff *skb;
3155         u8 __iomem *bd;
3156         u16 length, howmany = 0;
3157         u32 bd_status;
3158         u8 *bdBuffer;
3159         struct net_device *dev;
3160
3161         ugeth_vdbg("%s: IN", __func__);
3162
3163         dev = ugeth->ndev;
3164
3165         /* collect received buffers */
3166         bd = ugeth->rxBd[rxQ];
3167
3168         bd_status = in_be32((u32 __iomem *)bd);
3169
3170         /* while there are received buffers and BD is full (~R_E) */
3171         while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
3172                 bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf);
3173                 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
3174                 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3175
3176                 /* determine whether buffer is first, last, first and last
3177                 (single buffer frame) or middle (not first and not last) */
3178                 if (!skb ||
3179                     (!(bd_status & (R_F | R_L))) ||
3180                     (bd_status & R_ERRORS_FATAL)) {
3181                         if (netif_msg_rx_err(ugeth))
3182                                 ugeth_err("%s, %d: ERROR!!! skb - 0x%08x",
3183                                            __func__, __LINE__, (u32) skb);
3184                         if (skb) {
3185                                 skb->data = skb->head + NET_SKB_PAD;
3186                                 __skb_queue_head(&ugeth->rx_recycle, skb);
3187                         }
3188
3189                         ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
3190                         dev->stats.rx_dropped++;
3191                 } else {
3192                         dev->stats.rx_packets++;
3193                         howmany++;
3194
3195                         /* Prep the skb for the packet */
3196                         skb_put(skb, length);
3197
3198                         /* Tell the skb what kind of packet this is */
3199                         skb->protocol = eth_type_trans(skb, ugeth->ndev);
3200
3201                         dev->stats.rx_bytes += length;
3202                         /* Send the packet up the stack */
3203                         netif_receive_skb(skb);
3204                 }
3205
3206                 skb = get_new_skb(ugeth, bd);
3207                 if (!skb) {
3208                         if (netif_msg_rx_err(ugeth))
3209                                 ugeth_warn("%s: No Rx Data Buffer", __func__);
3210                         dev->stats.rx_dropped++;
3211                         break;
3212                 }
3213
3214                 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3215
3216                 /* update to point at the next skb */
3217                 ugeth->skb_currx[rxQ] =
3218                     (ugeth->skb_currx[rxQ] +
3219                      1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3220
3221                 if (bd_status & R_W)
3222                         bd = ugeth->p_rx_bd_ring[rxQ];
3223                 else
3224                         bd += sizeof(struct qe_bd);
3225
3226                 bd_status = in_be32((u32 __iomem *)bd);
3227         }
3228
3229         ugeth->rxBd[rxQ] = bd;
3230         return howmany;
3231 }
3232
3233 static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3234 {
3235         /* Start from the next BD that should be filled */
3236         struct ucc_geth_private *ugeth = netdev_priv(dev);
3237         u8 __iomem *bd;         /* BD pointer */
3238         u32 bd_status;
3239
3240         bd = ugeth->confBd[txQ];
3241         bd_status = in_be32((u32 __iomem *)bd);
3242
3243         /* Normal processing. */
3244         while ((bd_status & T_R) == 0) {
3245                 struct sk_buff *skb;
3246
3247                 /* BD contains already transmitted buffer.   */
3248                 /* Handle the transmitted buffer and release */
3249                 /* the BD to be used with the current frame  */
3250
3251                 if ((bd == ugeth->txBd[txQ]) && (netif_queue_stopped(dev) == 0))
3252                         break;
3253
3254                 dev->stats.tx_packets++;
3255
3256                 skb = ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]];
3257
3258                 if (skb_queue_len(&ugeth->rx_recycle) < RX_BD_RING_LEN &&
3259                              skb_recycle_check(skb,
3260                                     ugeth->ug_info->uf_info.max_rx_buf_length +
3261                                     UCC_GETH_RX_DATA_BUF_ALIGNMENT))
3262                         __skb_queue_head(&ugeth->rx_recycle, skb);
3263                 else
3264                         dev_kfree_skb(skb);
3265
3266                 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3267                 ugeth->skb_dirtytx[txQ] =
3268                     (ugeth->skb_dirtytx[txQ] +
3269                      1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3270
3271                 /* We freed a buffer, so now we can restart transmission */
3272                 if (netif_queue_stopped(dev))
3273                         netif_wake_queue(dev);
3274
3275                 /* Advance the confirmation BD pointer */
3276                 if (!(bd_status & T_W))
3277                         bd += sizeof(struct qe_bd);
3278                 else
3279                         bd = ugeth->p_tx_bd_ring[txQ];
3280                 bd_status = in_be32((u32 __iomem *)bd);
3281         }
3282         ugeth->confBd[txQ] = bd;
3283         return 0;
3284 }
3285
3286 static int ucc_geth_poll(struct napi_struct *napi, int budget)
3287 {
3288         struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
3289         struct ucc_geth_info *ug_info;
3290         int howmany, i;
3291
3292         ug_info = ugeth->ug_info;
3293
3294         /* Tx event processing */
3295         spin_lock(&ugeth->lock);
3296         for (i = 0; i < ug_info->numQueuesTx; i++)
3297                 ucc_geth_tx(ugeth->ndev, i);
3298         spin_unlock(&ugeth->lock);
3299
3300         howmany = 0;
3301         for (i = 0; i < ug_info->numQueuesRx; i++)
3302                 howmany += ucc_geth_rx(ugeth, i, budget - howmany);
3303
3304         if (howmany < budget) {
3305                 napi_complete(napi);
3306                 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS);
3307         }
3308
3309         return howmany;
3310 }
3311
3312 static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
3313 {
3314         struct net_device *dev = info;
3315         struct ucc_geth_private *ugeth = netdev_priv(dev);
3316         struct ucc_fast_private *uccf;
3317         struct ucc_geth_info *ug_info;
3318         register u32 ucce;
3319         register u32 uccm;
3320
3321         ugeth_vdbg("%s: IN", __func__);
3322
3323         uccf = ugeth->uccf;
3324         ug_info = ugeth->ug_info;
3325
3326         /* read and clear events */
3327         ucce = (u32) in_be32(uccf->p_ucce);
3328         uccm = (u32) in_be32(uccf->p_uccm);
3329         ucce &= uccm;
3330         out_be32(uccf->p_ucce, ucce);
3331
3332         /* check for receive events that require processing */
3333         if (ucce & (UCCE_RX_EVENTS | UCCE_TX_EVENTS)) {
3334                 if (napi_schedule_prep(&ugeth->napi)) {
3335                         uccm &= ~(UCCE_RX_EVENTS | UCCE_TX_EVENTS);
3336                         out_be32(uccf->p_uccm, uccm);
3337                         __napi_schedule(&ugeth->napi);
3338                 }
3339         }
3340
3341         /* Errors and other events */
3342         if (ucce & UCCE_OTHER) {
3343                 if (ucce & UCC_GETH_UCCE_BSY)
3344                         dev->stats.rx_errors++;
3345                 if (ucce & UCC_GETH_UCCE_TXE)
3346                         dev->stats.tx_errors++;
3347         }
3348
3349         return IRQ_HANDLED;
3350 }
3351
3352 #ifdef CONFIG_NET_POLL_CONTROLLER
3353 /*
3354  * Polling 'interrupt' - used by things like netconsole to send skbs
3355  * without having to re-enable interrupts. It's not called while
3356  * the interrupt routine is executing.
3357  */
3358 static void ucc_netpoll(struct net_device *dev)
3359 {
3360         struct ucc_geth_private *ugeth = netdev_priv(dev);
3361         int irq = ugeth->ug_info->uf_info.irq;
3362
3363         disable_irq(irq);
3364         ucc_geth_irq_handler(irq, dev);
3365         enable_irq(irq);
3366 }
3367 #endif /* CONFIG_NET_POLL_CONTROLLER */
3368
3369 static int ucc_geth_set_mac_addr(struct net_device *dev, void *p)
3370 {
3371         struct ucc_geth_private *ugeth = netdev_priv(dev);
3372         struct sockaddr *addr = p;
3373
3374         if (!is_valid_ether_addr(addr->sa_data))
3375                 return -EADDRNOTAVAIL;
3376
3377         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3378
3379         /*
3380          * If device is not running, we will set mac addr register
3381          * when opening the device.
3382          */
3383         if (!netif_running(dev))
3384                 return 0;
3385
3386         spin_lock_irq(&ugeth->lock);
3387         init_mac_station_addr_regs(dev->dev_addr[0],
3388                                    dev->dev_addr[1],
3389                                    dev->dev_addr[2],
3390                                    dev->dev_addr[3],
3391                                    dev->dev_addr[4],
3392                                    dev->dev_addr[5],
3393                                    &ugeth->ug_regs->macstnaddr1,
3394                                    &ugeth->ug_regs->macstnaddr2);
3395         spin_unlock_irq(&ugeth->lock);
3396
3397         return 0;
3398 }
3399
3400 static int ucc_geth_init_mac(struct ucc_geth_private *ugeth)
3401 {
3402         struct net_device *dev = ugeth->ndev;
3403         int err;
3404
3405         err = ucc_struct_init(ugeth);
3406         if (err) {
3407                 if (netif_msg_ifup(ugeth))
3408                         ugeth_err("%s: Cannot configure internal struct, "
3409                                   "aborting.", dev->name);
3410                 goto err;
3411         }
3412
3413         err = ucc_geth_startup(ugeth);
3414         if (err) {
3415                 if (netif_msg_ifup(ugeth))
3416                         ugeth_err("%s: Cannot configure net device, aborting.",
3417                                   dev->name);
3418                 goto err;
3419         }
3420
3421         err = adjust_enet_interface(ugeth);
3422         if (err) {
3423                 if (netif_msg_ifup(ugeth))
3424                         ugeth_err("%s: Cannot configure net device, aborting.",
3425                                   dev->name);
3426                 goto err;
3427         }
3428
3429         /*       Set MACSTNADDR1, MACSTNADDR2                */
3430         /* For more details see the hardware spec.           */
3431         init_mac_station_addr_regs(dev->dev_addr[0],
3432                                    dev->dev_addr[1],
3433                                    dev->dev_addr[2],
3434                                    dev->dev_addr[3],
3435                                    dev->dev_addr[4],
3436                                    dev->dev_addr[5],
3437                                    &ugeth->ug_regs->macstnaddr1,
3438                                    &ugeth->ug_regs->macstnaddr2);
3439
3440         err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3441         if (err) {
3442                 if (netif_msg_ifup(ugeth))
3443                         ugeth_err("%s: Cannot enable net device, aborting.", dev->name);
3444                 goto err;
3445         }
3446
3447         return 0;
3448 err:
3449         ucc_geth_stop(ugeth);
3450         return err;
3451 }
3452
3453 /* Called when something needs to use the ethernet device */
3454 /* Returns 0 for success. */
3455 static int ucc_geth_open(struct net_device *dev)
3456 {
3457         struct ucc_geth_private *ugeth = netdev_priv(dev);
3458         int err;
3459
3460         ugeth_vdbg("%s: IN", __func__);
3461
3462         /* Test station address */
3463         if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
3464                 if (netif_msg_ifup(ugeth))
3465                         ugeth_err("%s: Multicast address used for station "
3466                                   "address - is this what you wanted?",
3467                                   __func__);
3468                 return -EINVAL;
3469         }
3470
3471         err = init_phy(dev);
3472         if (err) {
3473                 if (netif_msg_ifup(ugeth))
3474                         ugeth_err("%s: Cannot initialize PHY, aborting.",
3475                                   dev->name);
3476                 return err;
3477         }
3478
3479         err = ucc_geth_init_mac(ugeth);
3480         if (err) {
3481                 if (netif_msg_ifup(ugeth))
3482                         ugeth_err("%s: Cannot initialize MAC, aborting.",
3483                                   dev->name);
3484                 goto err;
3485         }
3486
3487         err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler,
3488                           0, "UCC Geth", dev);
3489         if (err) {
3490                 if (netif_msg_ifup(ugeth))
3491                         ugeth_err("%s: Cannot get IRQ for net device, aborting.",
3492                                   dev->name);
3493                 goto err;
3494         }
3495
3496         phy_start(ugeth->phydev);
3497         napi_enable(&ugeth->napi);
3498         netif_start_queue(dev);
3499
3500         device_set_wakeup_capable(&dev->dev,
3501                         qe_alive_during_sleep() || ugeth->phydev->irq);
3502         device_set_wakeup_enable(&dev->dev, ugeth->wol_en);
3503
3504         return err;
3505
3506 err:
3507         ucc_geth_stop(ugeth);
3508         return err;
3509 }
3510
3511 /* Stops the kernel queue, and halts the controller */
3512 static int ucc_geth_close(struct net_device *dev)
3513 {
3514         struct ucc_geth_private *ugeth = netdev_priv(dev);
3515
3516         ugeth_vdbg("%s: IN", __func__);
3517
3518         napi_disable(&ugeth->napi);
3519
3520         ucc_geth_stop(ugeth);
3521
3522         free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev);
3523
3524         netif_stop_queue(dev);
3525
3526         return 0;
3527 }
3528
3529 /* Reopen device. This will reset the MAC and PHY. */
3530 static void ucc_geth_timeout_work(struct work_struct *work)
3531 {
3532         struct ucc_geth_private *ugeth;
3533         struct net_device *dev;
3534
3535         ugeth = container_of(work, struct ucc_geth_private, timeout_work);
3536         dev = ugeth->ndev;
3537
3538         ugeth_vdbg("%s: IN", __func__);
3539
3540         dev->stats.tx_errors++;
3541
3542         ugeth_dump_regs(ugeth);
3543
3544         if (dev->flags & IFF_UP) {
3545                 /*
3546                  * Must reset MAC *and* PHY. This is done by reopening
3547                  * the device.
3548                  */
3549                 ucc_geth_close(dev);
3550                 ucc_geth_open(dev);
3551         }
3552
3553         netif_tx_schedule_all(dev);
3554 }
3555
3556 /*
3557  * ucc_geth_timeout gets called when a packet has not been
3558  * transmitted after a set amount of time.
3559  */
3560 static void ucc_geth_timeout(struct net_device *dev)
3561 {
3562         struct ucc_geth_private *ugeth = netdev_priv(dev);
3563
3564         netif_carrier_off(dev);
3565         schedule_work(&ugeth->timeout_work);
3566 }
3567
3568
3569 #ifdef CONFIG_PM
3570
3571 static int ucc_geth_suspend(struct of_device *ofdev, pm_message_t state)
3572 {
3573         struct net_device *ndev = dev_get_drvdata(&ofdev->dev);
3574         struct ucc_geth_private *ugeth = netdev_priv(ndev);
3575
3576         if (!netif_running(ndev))
3577                 return 0;
3578
3579         napi_disable(&ugeth->napi);
3580
3581         /*
3582          * Disable the controller, otherwise we'll wakeup on any network
3583          * activity.
3584          */
3585         ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
3586
3587         if (ugeth->wol_en & WAKE_MAGIC) {
3588                 setbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3589                 setbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3590                 ucc_fast_enable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3591         } else if (!(ugeth->wol_en & WAKE_PHY)) {
3592                 phy_stop(ugeth->phydev);
3593         }
3594
3595         return 0;
3596 }
3597
3598 static int ucc_geth_resume(struct of_device *ofdev)
3599 {
3600         struct net_device *ndev = dev_get_drvdata(&ofdev->dev);
3601         struct ucc_geth_private *ugeth = netdev_priv(ndev);
3602         int err;
3603
3604         if (!netif_running(ndev))
3605                 return 0;
3606
3607         if (qe_alive_during_sleep()) {
3608                 if (ugeth->wol_en & WAKE_MAGIC) {
3609                         ucc_fast_disable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3610                         clrbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3611                         clrbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3612                 }
3613                 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3614         } else {
3615                 /*
3616                  * Full reinitialization is required if QE shuts down
3617                  * during sleep.
3618                  */
3619                 ucc_geth_memclean(ugeth);
3620
3621                 err = ucc_geth_init_mac(ugeth);
3622                 if (err) {
3623                         ugeth_err("%s: Cannot initialize MAC, aborting.",
3624                                   ndev->name);
3625                         return err;
3626                 }
3627         }
3628
3629         ugeth->oldlink = 0;
3630         ugeth->oldspeed = 0;
3631         ugeth->oldduplex = -1;
3632
3633         phy_stop(ugeth->phydev);
3634         phy_start(ugeth->phydev);
3635
3636         napi_enable(&ugeth->napi);
3637         netif_start_queue(ndev);
3638
3639         return 0;
3640 }
3641
3642 #else
3643 #define ucc_geth_suspend NULL
3644 #define ucc_geth_resume NULL
3645 #endif
3646
3647 static phy_interface_t to_phy_interface(const char *phy_connection_type)
3648 {
3649         if (strcasecmp(phy_connection_type, "mii") == 0)
3650                 return PHY_INTERFACE_MODE_MII;
3651         if (strcasecmp(phy_connection_type, "gmii") == 0)
3652                 return PHY_INTERFACE_MODE_GMII;
3653         if (strcasecmp(phy_connection_type, "tbi") == 0)
3654                 return PHY_INTERFACE_MODE_TBI;
3655         if (strcasecmp(phy_connection_type, "rmii") == 0)
3656                 return PHY_INTERFACE_MODE_RMII;
3657         if (strcasecmp(phy_connection_type, "rgmii") == 0)
3658                 return PHY_INTERFACE_MODE_RGMII;
3659         if (strcasecmp(phy_connection_type, "rgmii-id") == 0)
3660                 return PHY_INTERFACE_MODE_RGMII_ID;
3661         if (strcasecmp(phy_connection_type, "rgmii-txid") == 0)
3662                 return PHY_INTERFACE_MODE_RGMII_TXID;
3663         if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0)
3664                 return PHY_INTERFACE_MODE_RGMII_RXID;
3665         if (strcasecmp(phy_connection_type, "rtbi") == 0)
3666                 return PHY_INTERFACE_MODE_RTBI;
3667         if (strcasecmp(phy_connection_type, "sgmii") == 0)
3668                 return PHY_INTERFACE_MODE_SGMII;
3669
3670         return PHY_INTERFACE_MODE_MII;
3671 }
3672
3673 static const struct net_device_ops ucc_geth_netdev_ops = {
3674         .ndo_open               = ucc_geth_open,
3675         .ndo_stop               = ucc_geth_close,
3676         .ndo_start_xmit         = ucc_geth_start_xmit,
3677         .ndo_validate_addr      = eth_validate_addr,
3678         .ndo_set_mac_address    = ucc_geth_set_mac_addr,
3679         .ndo_change_mtu         = eth_change_mtu,
3680         .ndo_set_multicast_list = ucc_geth_set_multi,
3681         .ndo_tx_timeout         = ucc_geth_timeout,
3682 #ifdef CONFIG_NET_POLL_CONTROLLER
3683         .ndo_poll_controller    = ucc_netpoll,
3684 #endif
3685 };
3686
3687 static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *match)
3688 {
3689         struct device *device = &ofdev->dev;
3690         struct device_node *np = ofdev->node;
3691         struct net_device *dev = NULL;
3692         struct ucc_geth_private *ugeth = NULL;
3693         struct ucc_geth_info *ug_info;
3694         struct resource res;
3695         int err, ucc_num, max_speed = 0;
3696         const unsigned int *prop;
3697         const char *sprop;
3698         const void *mac_addr;
3699         phy_interface_t phy_interface;
3700         static const int enet_to_speed[] = {
3701                 SPEED_10, SPEED_10, SPEED_10,
3702                 SPEED_100, SPEED_100, SPEED_100,
3703                 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000,
3704         };
3705         static const phy_interface_t enet_to_phy_interface[] = {
3706                 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII,
3707                 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII,
3708                 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
3709                 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
3710                 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
3711                 PHY_INTERFACE_MODE_SGMII,
3712         };
3713
3714         ugeth_vdbg("%s: IN", __func__);
3715
3716         prop = of_get_property(np, "cell-index", NULL);
3717         if (!prop) {
3718                 prop = of_get_property(np, "device-id", NULL);
3719                 if (!prop)
3720                         return -ENODEV;
3721         }
3722
3723         ucc_num = *prop - 1;
3724         if ((ucc_num < 0) || (ucc_num > 7))
3725                 return -ENODEV;
3726
3727         ug_info = &ugeth_info[ucc_num];
3728         if (ug_info == NULL) {
3729                 if (netif_msg_probe(&debug))
3730                         ugeth_err("%s: [%d] Missing additional data!",
3731                                         __func__, ucc_num);
3732                 return -ENODEV;
3733         }
3734
3735         ug_info->uf_info.ucc_num = ucc_num;
3736
3737         sprop = of_get_property(np, "rx-clock-name", NULL);
3738         if (sprop) {
3739                 ug_info->uf_info.rx_clock = qe_clock_source(sprop);
3740                 if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) ||
3741                     (ug_info->uf_info.rx_clock > QE_CLK24)) {
3742                         printk(KERN_ERR
3743                                 "ucc_geth: invalid rx-clock-name property\n");
3744                         return -EINVAL;
3745                 }
3746         } else {
3747                 prop = of_get_property(np, "rx-clock", NULL);
3748                 if (!prop) {
3749                         /* If both rx-clock-name and rx-clock are missing,
3750                            we want to tell people to use rx-clock-name. */
3751                         printk(KERN_ERR
3752                                 "ucc_geth: missing rx-clock-name property\n");
3753                         return -EINVAL;
3754                 }
3755                 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3756                         printk(KERN_ERR
3757                                 "ucc_geth: invalid rx-clock propperty\n");
3758                         return -EINVAL;
3759                 }
3760                 ug_info->uf_info.rx_clock = *prop;
3761         }
3762
3763         sprop = of_get_property(np, "tx-clock-name", NULL);
3764         if (sprop) {
3765                 ug_info->uf_info.tx_clock = qe_clock_source(sprop);
3766                 if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) ||
3767                     (ug_info->uf_info.tx_clock > QE_CLK24)) {
3768                         printk(KERN_ERR
3769                                 "ucc_geth: invalid tx-clock-name property\n");
3770                         return -EINVAL;
3771                 }
3772         } else {
3773                 prop = of_get_property(np, "tx-clock", NULL);
3774                 if (!prop) {
3775                         printk(KERN_ERR
3776                                 "ucc_geth: mising tx-clock-name property\n");
3777                         return -EINVAL;
3778                 }
3779                 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3780                         printk(KERN_ERR
3781                                 "ucc_geth: invalid tx-clock property\n");
3782                         return -EINVAL;
3783                 }
3784                 ug_info->uf_info.tx_clock = *prop;
3785         }
3786
3787         err = of_address_to_resource(np, 0, &res);
3788         if (err)
3789                 return -EINVAL;
3790
3791         ug_info->uf_info.regs = res.start;
3792         ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
3793
3794         ug_info->phy_node = of_parse_phandle(np, "phy-handle", 0);
3795
3796         /* Find the TBI PHY node.  If it's not there, we don't support SGMII */
3797         ug_info->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
3798
3799         /* get the phy interface type, or default to MII */
3800         prop = of_get_property(np, "phy-connection-type", NULL);
3801         if (!prop) {
3802                 /* handle interface property present in old trees */
3803                 prop = of_get_property(ug_info->phy_node, "interface", NULL);
3804                 if (prop != NULL) {
3805                         phy_interface = enet_to_phy_interface[*prop];
3806                         max_speed = enet_to_speed[*prop];
3807                 } else
3808                         phy_interface = PHY_INTERFACE_MODE_MII;
3809         } else {
3810                 phy_interface = to_phy_interface((const char *)prop);
3811         }
3812
3813         /* get speed, or derive from PHY interface */
3814         if (max_speed == 0)
3815                 switch (phy_interface) {
3816                 case PHY_INTERFACE_MODE_GMII:
3817                 case PHY_INTERFACE_MODE_RGMII:
3818                 case PHY_INTERFACE_MODE_RGMII_ID:
3819                 case PHY_INTERFACE_MODE_RGMII_RXID:
3820                 case PHY_INTERFACE_MODE_RGMII_TXID:
3821                 case PHY_INTERFACE_MODE_TBI:
3822                 case PHY_INTERFACE_MODE_RTBI:
3823                 case PHY_INTERFACE_MODE_SGMII:
3824                         max_speed = SPEED_1000;
3825                         break;
3826                 default:
3827                         max_speed = SPEED_100;
3828                         break;
3829                 }
3830
3831         if (max_speed == SPEED_1000) {
3832                 /* configure muram FIFOs for gigabit operation */
3833                 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
3834                 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
3835                 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
3836                 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
3837                 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
3838                 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
3839                 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
3840
3841                 /* If QE's snum number is 46 which means we need to support
3842                  * 4 UECs at 1000Base-T simultaneously, we need to allocate
3843                  * more Threads to Rx.
3844                  */
3845                 if (qe_get_num_of_snums() == 46)
3846                         ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6;
3847                 else
3848                         ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
3849         }
3850
3851         if (netif_msg_probe(&debug))
3852                 printk(KERN_INFO "ucc_geth: UCC%1d at 0x%8x (irq = %d) \n",
3853                         ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs,
3854                         ug_info->uf_info.irq);
3855
3856         /* Create an ethernet device instance */
3857         dev = alloc_etherdev(sizeof(*ugeth));
3858
3859         if (dev == NULL)
3860                 return -ENOMEM;
3861
3862         ugeth = netdev_priv(dev);
3863         spin_lock_init(&ugeth->lock);
3864
3865         /* Create CQs for hash tables */
3866         INIT_LIST_HEAD(&ugeth->group_hash_q);
3867         INIT_LIST_HEAD(&ugeth->ind_hash_q);
3868
3869         dev_set_drvdata(device, dev);
3870
3871         /* Set the dev->base_addr to the gfar reg region */
3872         dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
3873
3874         SET_NETDEV_DEV(dev, device);
3875
3876         /* Fill in the dev structure */
3877         uec_set_ethtool_ops(dev);
3878         dev->netdev_ops = &ucc_geth_netdev_ops;
3879         dev->watchdog_timeo = TX_TIMEOUT;
3880         INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work);
3881         netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, 64);
3882         dev->mtu = 1500;
3883
3884         ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT);
3885         ugeth->phy_interface = phy_interface;
3886         ugeth->max_speed = max_speed;
3887
3888         err = register_netdev(dev);
3889         if (err) {
3890                 if (netif_msg_probe(ugeth))
3891                         ugeth_err("%s: Cannot register net device, aborting.",
3892                                   dev->name);
3893                 free_netdev(dev);
3894                 return err;
3895         }
3896
3897         mac_addr = of_get_mac_address(np);
3898         if (mac_addr)
3899                 memcpy(dev->dev_addr, mac_addr, 6);
3900
3901         ugeth->ug_info = ug_info;
3902         ugeth->dev = device;
3903         ugeth->ndev = dev;
3904         ugeth->node = np;
3905
3906         return 0;
3907 }
3908
3909 static int ucc_geth_remove(struct of_device* ofdev)
3910 {
3911         struct device *device = &ofdev->dev;
3912         struct net_device *dev = dev_get_drvdata(device);
3913         struct ucc_geth_private *ugeth = netdev_priv(dev);
3914
3915         unregister_netdev(dev);
3916         free_netdev(dev);
3917         ucc_geth_memclean(ugeth);
3918         dev_set_drvdata(device, NULL);
3919
3920         return 0;
3921 }
3922
3923 static struct of_device_id ucc_geth_match[] = {
3924         {
3925                 .type = "network",
3926                 .compatible = "ucc_geth",
3927         },
3928         {},
3929 };
3930
3931 MODULE_DEVICE_TABLE(of, ucc_geth_match);
3932
3933 static struct of_platform_driver ucc_geth_driver = {
3934         .name           = DRV_NAME,
3935         .match_table    = ucc_geth_match,
3936         .probe          = ucc_geth_probe,
3937         .remove         = ucc_geth_remove,
3938         .suspend        = ucc_geth_suspend,
3939         .resume         = ucc_geth_resume,
3940 };
3941
3942 static int __init ucc_geth_init(void)
3943 {
3944         int i, ret;
3945
3946         if (netif_msg_drv(&debug))
3947                 printk(KERN_INFO "ucc_geth: " DRV_DESC "\n");
3948         for (i = 0; i < 8; i++)
3949                 memcpy(&(ugeth_info[i]), &ugeth_primary_info,
3950                        sizeof(ugeth_primary_info));
3951
3952         ret = of_register_platform_driver(&ucc_geth_driver);
3953
3954         return ret;
3955 }
3956
3957 static void __exit ucc_geth_exit(void)
3958 {
3959         of_unregister_platform_driver(&ucc_geth_driver);
3960 }
3961
3962 module_init(ucc_geth_init);
3963 module_exit(ucc_geth_exit);
3964
3965 MODULE_AUTHOR("Freescale Semiconductor, Inc");
3966 MODULE_DESCRIPTION(DRV_DESC);
3967 MODULE_VERSION(DRV_VERSION);
3968 MODULE_LICENSE("GPL");