1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
6 #include <linux/signal.h>
7 #include <linux/slab.h>
8 #include <linux/module.h>
9 #include <linux/netdevice.h>
10 #include <linux/etherdevice.h>
11 #include <linux/mii.h>
12 #include <linux/ethtool.h>
13 #include <linux/usb.h>
14 #include <linux/crc32.h>
15 #include <linux/if_vlan.h>
16 #include <linux/uaccess.h>
17 #include <linux/list.h>
19 #include <linux/ipv6.h>
20 #include <net/ip6_checksum.h>
21 #include <uapi/linux/mdio.h>
22 #include <linux/mdio.h>
23 #include <linux/usb/cdc.h>
24 #include <linux/suspend.h>
25 #include <linux/atomic.h>
26 #include <linux/acpi.h>
27 #include <linux/firmware.h>
28 #include <crypto/hash.h>
30 /* Information for net-next */
31 #define NETNEXT_VERSION "11"
33 /* Information for net */
34 #define NET_VERSION "10"
36 #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
37 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
38 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
39 #define MODULENAME "r8152"
41 #define R8152_PHY_ID 32
43 #define PLA_IDR 0xc000
44 #define PLA_RCR 0xc010
45 #define PLA_RMS 0xc016
46 #define PLA_RXFIFO_CTRL0 0xc0a0
47 #define PLA_RXFIFO_CTRL1 0xc0a4
48 #define PLA_RXFIFO_CTRL2 0xc0a8
49 #define PLA_DMY_REG0 0xc0b0
50 #define PLA_FMC 0xc0b4
51 #define PLA_CFG_WOL 0xc0b6
52 #define PLA_TEREDO_CFG 0xc0bc
53 #define PLA_TEREDO_WAKE_BASE 0xc0c4
54 #define PLA_MAR 0xcd00
55 #define PLA_BACKUP 0xd000
56 #define PLA_BDC_CR 0xd1a0
57 #define PLA_TEREDO_TIMER 0xd2cc
58 #define PLA_REALWOW_TIMER 0xd2e8
59 #define PLA_UPHY_TIMER 0xd388
60 #define PLA_SUSPEND_FLAG 0xd38a
61 #define PLA_INDICATE_FALG 0xd38c
62 #define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */
63 #define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */
64 #define PLA_EXTRA_STATUS 0xd398
65 #define PLA_EFUSE_DATA 0xdd00
66 #define PLA_EFUSE_CMD 0xdd02
67 #define PLA_LEDSEL 0xdd90
68 #define PLA_LED_FEATURE 0xdd92
69 #define PLA_PHYAR 0xde00
70 #define PLA_BOOT_CTRL 0xe004
71 #define PLA_GPHY_INTR_IMR 0xe022
72 #define PLA_EEE_CR 0xe040
73 #define PLA_EEEP_CR 0xe080
74 #define PLA_MAC_PWR_CTRL 0xe0c0
75 #define PLA_MAC_PWR_CTRL2 0xe0ca
76 #define PLA_MAC_PWR_CTRL3 0xe0cc
77 #define PLA_MAC_PWR_CTRL4 0xe0ce
78 #define PLA_WDT6_CTRL 0xe428
79 #define PLA_TCR0 0xe610
80 #define PLA_TCR1 0xe612
81 #define PLA_MTPS 0xe615
82 #define PLA_TXFIFO_CTRL 0xe618
83 #define PLA_RSTTALLY 0xe800
85 #define PLA_CRWECR 0xe81c
86 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
87 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
88 #define PLA_CONFIG5 0xe822
89 #define PLA_PHY_PWR 0xe84c
90 #define PLA_OOB_CTRL 0xe84f
91 #define PLA_CPCR 0xe854
92 #define PLA_MISC_0 0xe858
93 #define PLA_MISC_1 0xe85a
94 #define PLA_OCP_GPHY_BASE 0xe86c
95 #define PLA_TALLYCNT 0xe890
96 #define PLA_SFF_STS_7 0xe8de
97 #define PLA_PHYSTATUS 0xe908
98 #define PLA_BP_BA 0xfc26
99 #define PLA_BP_0 0xfc28
100 #define PLA_BP_1 0xfc2a
101 #define PLA_BP_2 0xfc2c
102 #define PLA_BP_3 0xfc2e
103 #define PLA_BP_4 0xfc30
104 #define PLA_BP_5 0xfc32
105 #define PLA_BP_6 0xfc34
106 #define PLA_BP_7 0xfc36
107 #define PLA_BP_EN 0xfc38
109 #define USB_USB2PHY 0xb41e
110 #define USB_SSPHYLINK2 0xb428
111 #define USB_U2P3_CTRL 0xb460
112 #define USB_CSR_DUMMY1 0xb464
113 #define USB_CSR_DUMMY2 0xb466
114 #define USB_DEV_STAT 0xb808
115 #define USB_CONNECT_TIMER 0xcbf8
116 #define USB_MSC_TIMER 0xcbfc
117 #define USB_BURST_SIZE 0xcfc0
118 #define USB_FW_FIX_EN0 0xcfca
119 #define USB_FW_FIX_EN1 0xcfcc
120 #define USB_LPM_CONFIG 0xcfd8
121 #define USB_CSTMR 0xcfef /* RTL8153A */
122 #define USB_FW_CTRL 0xd334 /* RTL8153B */
123 #define USB_FC_TIMER 0xd340
124 #define USB_USB_CTRL 0xd406
125 #define USB_PHY_CTRL 0xd408
126 #define USB_TX_AGG 0xd40a
127 #define USB_RX_BUF_TH 0xd40c
128 #define USB_USB_TIMER 0xd428
129 #define USB_RX_EARLY_TIMEOUT 0xd42c
130 #define USB_RX_EARLY_SIZE 0xd42e
131 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
132 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
133 #define USB_TX_DMA 0xd434
134 #define USB_UPT_RXDMA_OWN 0xd437
135 #define USB_TOLERANCE 0xd490
136 #define USB_LPM_CTRL 0xd41a
137 #define USB_BMU_RESET 0xd4b0
138 #define USB_U1U2_TIMER 0xd4da
139 #define USB_FW_TASK 0xd4e8 /* RTL8153B */
140 #define USB_UPS_CTRL 0xd800
141 #define USB_POWER_CUT 0xd80a
142 #define USB_MISC_0 0xd81a
143 #define USB_MISC_1 0xd81f
144 #define USB_AFE_CTRL2 0xd824
145 #define USB_UPS_CFG 0xd842
146 #define USB_UPS_FLAGS 0xd848
147 #define USB_WDT1_CTRL 0xe404
148 #define USB_WDT11_CTRL 0xe43c
149 #define USB_BP_BA PLA_BP_BA
150 #define USB_BP_0 PLA_BP_0
151 #define USB_BP_1 PLA_BP_1
152 #define USB_BP_2 PLA_BP_2
153 #define USB_BP_3 PLA_BP_3
154 #define USB_BP_4 PLA_BP_4
155 #define USB_BP_5 PLA_BP_5
156 #define USB_BP_6 PLA_BP_6
157 #define USB_BP_7 PLA_BP_7
158 #define USB_BP_EN PLA_BP_EN /* RTL8153A */
159 #define USB_BP_8 0xfc38 /* RTL8153B */
160 #define USB_BP_9 0xfc3a
161 #define USB_BP_10 0xfc3c
162 #define USB_BP_11 0xfc3e
163 #define USB_BP_12 0xfc40
164 #define USB_BP_13 0xfc42
165 #define USB_BP_14 0xfc44
166 #define USB_BP_15 0xfc46
167 #define USB_BP2_EN 0xfc48
170 #define OCP_ALDPS_CONFIG 0x2010
171 #define OCP_EEE_CONFIG1 0x2080
172 #define OCP_EEE_CONFIG2 0x2092
173 #define OCP_EEE_CONFIG3 0x2094
174 #define OCP_BASE_MII 0xa400
175 #define OCP_EEE_AR 0xa41a
176 #define OCP_EEE_DATA 0xa41c
177 #define OCP_PHY_STATUS 0xa420
178 #define OCP_NCTL_CFG 0xa42c
179 #define OCP_POWER_CFG 0xa430
180 #define OCP_EEE_CFG 0xa432
181 #define OCP_SRAM_ADDR 0xa436
182 #define OCP_SRAM_DATA 0xa438
183 #define OCP_DOWN_SPEED 0xa442
184 #define OCP_EEE_ABLE 0xa5c4
185 #define OCP_EEE_ADV 0xa5d0
186 #define OCP_EEE_LPABLE 0xa5d2
187 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
188 #define OCP_PHY_PATCH_STAT 0xb800
189 #define OCP_PHY_PATCH_CMD 0xb820
190 #define OCP_PHY_LOCK 0xb82e
191 #define OCP_ADC_IOFFSET 0xbcfc
192 #define OCP_ADC_CFG 0xbc06
193 #define OCP_SYSCLK_CFG 0xc416
196 #define SRAM_GREEN_CFG 0x8011
197 #define SRAM_LPF_CFG 0x8012
198 #define SRAM_10M_AMP1 0x8080
199 #define SRAM_10M_AMP2 0x8082
200 #define SRAM_IMPEDANCE 0x8084
201 #define SRAM_PHY_LOCK 0xb82e
204 #define RCR_AAP 0x00000001
205 #define RCR_APM 0x00000002
206 #define RCR_AM 0x00000004
207 #define RCR_AB 0x00000008
208 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
210 /* PLA_RXFIFO_CTRL0 */
211 #define RXFIFO_THR1_NORMAL 0x00080002
212 #define RXFIFO_THR1_OOB 0x01800003
214 /* PLA_RXFIFO_CTRL1 */
215 #define RXFIFO_THR2_FULL 0x00000060
216 #define RXFIFO_THR2_HIGH 0x00000038
217 #define RXFIFO_THR2_OOB 0x0000004a
218 #define RXFIFO_THR2_NORMAL 0x00a0
220 /* PLA_RXFIFO_CTRL2 */
221 #define RXFIFO_THR3_FULL 0x00000078
222 #define RXFIFO_THR3_HIGH 0x00000048
223 #define RXFIFO_THR3_OOB 0x0000005a
224 #define RXFIFO_THR3_NORMAL 0x0110
226 /* PLA_TXFIFO_CTRL */
227 #define TXFIFO_THR_NORMAL 0x00400008
228 #define TXFIFO_THR_NORMAL2 0x01000008
231 #define ECM_ALDPS 0x0002
234 #define FMC_FCR_MCU_EN 0x0001
237 #define EEEP_CR_EEEP_TX 0x0002
240 #define WDT6_SET_MODE 0x0010
243 #define TCR0_TX_EMPTY 0x0800
244 #define TCR0_AUTO_FIFO 0x0080
247 #define VERSION_MASK 0x7cf0
250 #define MTPS_JUMBO (12 * 1024 / 64)
251 #define MTPS_DEFAULT (6 * 1024 / 64)
254 #define TALLY_RESET 0x0001
262 #define CRWECR_NORAML 0x00
263 #define CRWECR_CONFIG 0xc0
266 #define NOW_IS_OOB 0x80
267 #define TXFIFO_EMPTY 0x20
268 #define RXFIFO_EMPTY 0x10
269 #define LINK_LIST_READY 0x02
270 #define DIS_MCU_CLROOB 0x01
271 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
274 #define RXDY_GATED_EN 0x0008
277 #define RE_INIT_LL 0x8000
278 #define MCU_BORW_EN 0x4000
281 #define CPCR_RX_VLAN 0x0040
284 #define MAGIC_EN 0x0001
287 #define TEREDO_SEL 0x8000
288 #define TEREDO_WAKE_MASK 0x7f00
289 #define TEREDO_RS_EVENT_MASK 0x00fe
290 #define OOB_TEREDO_EN 0x0001
293 #define ALDPS_PROXY_MODE 0x0001
296 #define EFUSE_READ_CMD BIT(15)
297 #define EFUSE_DATA_BIT16 BIT(7)
300 #define LINK_ON_WAKE_EN 0x0010
301 #define LINK_OFF_WAKE_EN 0x0008
304 #define BWF_EN 0x0040
305 #define MWF_EN 0x0020
306 #define UWF_EN 0x0010
307 #define LAN_WAKE_EN 0x0002
309 /* PLA_LED_FEATURE */
310 #define LED_MODE_MASK 0x0700
313 #define TX_10M_IDLE_EN 0x0080
314 #define PFM_PWM_SWITCH 0x0040
316 /* PLA_MAC_PWR_CTRL */
317 #define D3_CLK_GATED_EN 0x00004000
318 #define MCU_CLK_RATIO 0x07010f07
319 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
320 #define ALDPS_SPDWN_RATIO 0x0f87
322 /* PLA_MAC_PWR_CTRL2 */
323 #define EEE_SPDWN_RATIO 0x8007
324 #define MAC_CLK_SPDWN_EN BIT(15)
326 /* PLA_MAC_PWR_CTRL3 */
327 #define PKT_AVAIL_SPDWN_EN 0x0100
328 #define SUSPEND_SPDWN_EN 0x0004
329 #define U1U2_SPDWN_EN 0x0002
330 #define L1_SPDWN_EN 0x0001
332 /* PLA_MAC_PWR_CTRL4 */
333 #define PWRSAVE_SPDWN_EN 0x1000
334 #define RXDV_SPDWN_EN 0x0800
335 #define TX10MIDLE_EN 0x0100
336 #define TP100_SPDWN_EN 0x0020
337 #define TP500_SPDWN_EN 0x0010
338 #define TP1000_SPDWN_EN 0x0008
339 #define EEE_SPDWN_EN 0x0001
341 /* PLA_GPHY_INTR_IMR */
342 #define GPHY_STS_MSK 0x0001
343 #define SPEED_DOWN_MSK 0x0002
344 #define SPDWN_RXDV_MSK 0x0004
345 #define SPDWN_LINKCHG_MSK 0x0008
348 #define PHYAR_FLAG 0x80000000
351 #define EEE_RX_EN 0x0001
352 #define EEE_TX_EN 0x0002
355 #define AUTOLOAD_DONE 0x0002
357 /* PLA_SUSPEND_FLAG */
358 #define LINK_CHG_EVENT BIT(0)
360 /* PLA_INDICATE_FALG */
361 #define UPCOMING_RUNTIME_D3 BIT(0)
363 /* PLA_MACDBG_PRE and PLA_MACDBG_POST */
364 #define DEBUG_OE BIT(0)
365 #define DEBUG_LTSSM 0x0082
367 /* PLA_EXTRA_STATUS */
368 #define U3P3_CHECK_EN BIT(7) /* RTL_VER_05 only */
369 #define LINK_CHANGE_FLAG BIT(8)
372 #define USB2PHY_SUSPEND 0x0001
373 #define USB2PHY_L1 0x0002
376 #define pwd_dn_scale_mask 0x3ffe
377 #define pwd_dn_scale(x) ((x) << 1)
380 #define DYNAMIC_BURST 0x0001
383 #define EP4_FULL_FC 0x0001
386 #define STAT_SPEED_MASK 0x0006
387 #define STAT_SPEED_HIGH 0x0000
388 #define STAT_SPEED_FULL 0x0002
391 #define FW_FIX_SUSPEND BIT(14)
394 #define FW_IP_RESET_EN BIT(9)
397 #define LPM_U1U2_EN BIT(0)
400 #define TX_AGG_MAX_THRESHOLD 0x03
403 #define RX_THR_SUPPER 0x0c350180
404 #define RX_THR_HIGH 0x7a120180
405 #define RX_THR_SLOW 0xffff0180
406 #define RX_THR_B 0x00010001
409 #define TEST_MODE_DISABLE 0x00000001
410 #define TX_SIZE_ADJUST1 0x00000100
413 #define BMU_RESET_EP_IN 0x01
414 #define BMU_RESET_EP_OUT 0x02
416 /* USB_UPT_RXDMA_OWN */
417 #define OWN_UPDATE BIT(0)
418 #define OWN_CLEAR BIT(1)
421 #define FC_PATCH_TASK BIT(1)
424 #define POWER_CUT 0x0100
426 /* USB_PM_CTRL_STATUS */
427 #define RESUME_INDICATE 0x0001
430 #define FORCE_SUPER BIT(0)
433 #define FLOW_CTRL_PATCH_OPT BIT(1)
436 #define CTRL_TIMER_EN BIT(15)
439 #define RX_AGG_DISABLE 0x0010
440 #define RX_ZERO_EN 0x0080
443 #define U2P3_ENABLE 0x0001
446 #define PWR_EN 0x0001
447 #define PHASE2_EN 0x0008
448 #define UPS_EN BIT(4)
449 #define USP_PREWAKE BIT(5)
452 #define PCUT_STATUS 0x0001
454 /* USB_RX_EARLY_TIMEOUT */
455 #define COALESCE_SUPER 85000U
456 #define COALESCE_HIGH 250000U
457 #define COALESCE_SLOW 524280U
460 #define WTD1_EN BIT(0)
463 #define TIMER11_EN 0x0001
466 /* bit 4 ~ 5: fifo empty boundary */
467 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
468 /* bit 2 ~ 3: LMP timer */
469 #define LPM_TIMER_MASK 0x0c
470 #define LPM_TIMER_500MS 0x04 /* 500 ms */
471 #define LPM_TIMER_500US 0x0c /* 500 us */
472 #define ROK_EXIT_LPM 0x02
475 #define SEN_VAL_MASK 0xf800
476 #define SEN_VAL_NORMAL 0xa000
477 #define SEL_RXIDLE 0x0100
480 #define SAW_CNT_1MS_MASK 0x0fff
483 #define UPS_FLAGS_R_TUNE BIT(0)
484 #define UPS_FLAGS_EN_10M_CKDIV BIT(1)
485 #define UPS_FLAGS_250M_CKDIV BIT(2)
486 #define UPS_FLAGS_EN_ALDPS BIT(3)
487 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
488 #define ups_flags_speed(x) ((x) << 16)
489 #define UPS_FLAGS_EN_EEE BIT(20)
490 #define UPS_FLAGS_EN_500M_EEE BIT(21)
491 #define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
492 #define UPS_FLAGS_EEE_PLLOFF_100 BIT(23)
493 #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
494 #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
495 #define UPS_FLAGS_EN_GREEN BIT(26)
496 #define UPS_FLAGS_EN_FLOW_CTR BIT(27)
510 /* OCP_ALDPS_CONFIG */
511 #define ENPWRSAVE 0x8000
512 #define ENPDNPS 0x0200
513 #define LINKENA 0x0100
514 #define DIS_SDSAVE 0x0010
517 #define PHY_STAT_MASK 0x0007
518 #define PHY_STAT_EXT_INIT 2
519 #define PHY_STAT_LAN_ON 3
520 #define PHY_STAT_PWRDN 5
523 #define PGA_RETURN_EN BIT(1)
526 #define EEE_CLKDIV_EN 0x8000
527 #define EN_ALDPS 0x0004
528 #define EN_10M_PLLOFF 0x0001
530 /* OCP_EEE_CONFIG1 */
531 #define RG_TXLPI_MSK_HFDUP 0x8000
532 #define RG_MATCLR_EN 0x4000
533 #define EEE_10_CAP 0x2000
534 #define EEE_NWAY_EN 0x1000
535 #define TX_QUIET_EN 0x0200
536 #define RX_QUIET_EN 0x0100
537 #define sd_rise_time_mask 0x0070
538 #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
539 #define RG_RXLPI_MSK_HFDUP 0x0008
540 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
542 /* OCP_EEE_CONFIG2 */
543 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
544 #define RG_DACQUIET_EN 0x0400
545 #define RG_LDVQUIET_EN 0x0200
546 #define RG_CKRSEL 0x0020
547 #define RG_EEEPRG_EN 0x0010
549 /* OCP_EEE_CONFIG3 */
550 #define fast_snr_mask 0xff80
551 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
552 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
553 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
556 /* bit[15:14] function */
557 #define FUN_ADDR 0x0000
558 #define FUN_DATA 0x4000
559 /* bit[4:0] device addr */
562 #define CTAP_SHORT_EN 0x0040
563 #define EEE10_EN 0x0010
566 #define EN_EEE_CMODE BIT(14)
567 #define EN_EEE_1000 BIT(13)
568 #define EN_EEE_100 BIT(12)
569 #define EN_10M_CLKDIV BIT(11)
570 #define EN_10M_BGOFF 0x0080
573 #define TXDIS_STATE 0x01
574 #define ABD_STATE 0x02
576 /* OCP_PHY_PATCH_STAT */
577 #define PATCH_READY BIT(6)
579 /* OCP_PHY_PATCH_CMD */
580 #define PATCH_REQUEST BIT(4)
583 #define PATCH_LOCK BIT(0)
586 #define CKADSEL_L 0x0100
587 #define ADC_EN 0x0080
588 #define EN_EMI_L 0x0040
591 #define clk_div_expo(x) (min(x, 5) << 8)
594 #define GREEN_ETH_EN BIT(15)
595 #define R_TUNE_EN BIT(11)
598 #define LPF_AUTO_TUNE 0x8000
601 #define GDAC_IB_UPALL 0x0008
604 #define AMP_DN 0x0200
607 #define RX_DRIVING_MASK 0x6000
610 #define PHY_PATCH_LOCK 0x0001
613 #define AD_MASK 0xfee0
614 #define BND_MASK 0x0004
615 #define BD_MASK 0x0001
617 #define PASS_THRU_MASK 0x1
619 #define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */
621 enum rtl_register_content {
629 #define RTL8152_MAX_TX 4
630 #define RTL8152_MAX_RX 10
635 #define RTL8152_RX_MAX_PENDING 4096
636 #define RTL8152_RXFG_HEADSZ 256
638 #define INTR_LINK 0x0004
640 #define RTL8152_REQT_READ 0xc0
641 #define RTL8152_REQT_WRITE 0x40
642 #define RTL8152_REQ_GET_REGS 0x05
643 #define RTL8152_REQ_SET_REGS 0x05
645 #define BYTE_EN_DWORD 0xff
646 #define BYTE_EN_WORD 0x33
647 #define BYTE_EN_BYTE 0x11
648 #define BYTE_EN_SIX_BYTES 0x3f
649 #define BYTE_EN_START_MASK 0x0f
650 #define BYTE_EN_END_MASK 0xf0
652 #define RTL8153_MAX_PACKET 9216 /* 9K */
653 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
655 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
656 #define RTL8153_RMS RTL8153_MAX_PACKET
657 #define RTL8152_TX_TIMEOUT (5 * HZ)
658 #define RTL8152_NAPI_WEIGHT 64
659 #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
660 sizeof(struct rx_desc) + RX_ALIGN)
676 /* Define these values to match your device */
677 #define VENDOR_ID_REALTEK 0x0bda
678 #define VENDOR_ID_MICROSOFT 0x045e
679 #define VENDOR_ID_SAMSUNG 0x04e8
680 #define VENDOR_ID_LENOVO 0x17ef
681 #define VENDOR_ID_LINKSYS 0x13b1
682 #define VENDOR_ID_NVIDIA 0x0955
683 #define VENDOR_ID_TPLINK 0x2357
685 #define MCU_TYPE_PLA 0x0100
686 #define MCU_TYPE_USB 0x0000
688 struct tally_counter {
695 __le32 tx_one_collision;
696 __le32 tx_multi_collision;
706 #define RX_LEN_MASK 0x7fff
709 #define RD_UDP_CS BIT(23)
710 #define RD_TCP_CS BIT(22)
711 #define RD_IPV6_CS BIT(20)
712 #define RD_IPV4_CS BIT(19)
715 #define IPF BIT(23) /* IP checksum fail */
716 #define UDPF BIT(22) /* UDP checksum fail */
717 #define TCPF BIT(21) /* TCP checksum fail */
718 #define RX_VLAN_TAG BIT(16)
727 #define TX_FS BIT(31) /* First segment of a packet */
728 #define TX_LS BIT(30) /* Final segment of a packet */
729 #define GTSENDV4 BIT(28)
730 #define GTSENDV6 BIT(27)
731 #define GTTCPHO_SHIFT 18
732 #define GTTCPHO_MAX 0x7fU
733 #define TX_LEN_MAX 0x3ffffU
736 #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
737 #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
738 #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
739 #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
741 #define MSS_MAX 0x7ffU
742 #define TCPHO_SHIFT 17
743 #define TCPHO_MAX 0x7ffU
744 #define TX_VLAN_TAG BIT(16)
750 struct list_head list, info_list;
752 struct r8152 *context;
758 struct list_head list;
760 struct r8152 *context;
769 struct usb_device *udev;
770 struct napi_struct napi;
771 struct usb_interface *intf;
772 struct net_device *netdev;
773 struct urb *intr_urb;
774 struct tx_agg tx_info[RTL8152_MAX_TX];
775 struct list_head rx_info, rx_used;
776 struct list_head rx_done, tx_free;
777 struct sk_buff_head tx_queue, rx_queue;
778 spinlock_t rx_lock, tx_lock;
779 struct delayed_work schedule, hw_phy_work;
780 struct mii_if_info mii;
781 struct mutex control; /* use for hw setting */
782 #ifdef CONFIG_PM_SLEEP
783 struct notifier_block pm_notifier;
785 struct tasklet_struct tx_tl;
788 void (*init)(struct r8152 *tp);
789 int (*enable)(struct r8152 *tp);
790 void (*disable)(struct r8152 *tp);
791 void (*up)(struct r8152 *tp);
792 void (*down)(struct r8152 *tp);
793 void (*unload)(struct r8152 *tp);
794 int (*eee_get)(struct r8152 *tp, struct ethtool_eee *eee);
795 int (*eee_set)(struct r8152 *tp, struct ethtool_eee *eee);
796 bool (*in_nway)(struct r8152 *tp);
797 void (*hw_phy_cfg)(struct r8152 *tp);
798 void (*autosuspend_en)(struct r8152 *tp, bool enable);
810 u32 eee_plloff_100:1;
811 u32 eee_plloff_giga:1;
815 u32 ctap_short_off:1;
818 #define RTL_VER_SIZE 32
822 const struct firmware *fw;
824 char version[RTL_VER_SIZE];
825 int (*pre_fw)(struct r8152 *tp);
826 int (*post_fw)(struct r8152 *tp);
854 * struct fw_block - block type and total length
855 * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
856 * RTL_FW_USB and so on.
857 * @length: total length of the current block.
865 * struct fw_header - header of the firmware file
866 * @checksum: checksum of sha256 which is calculated from the whole file
867 * except the checksum field of the file. That is, calculate sha256
868 * from the version field to the end of the file.
869 * @version: version of this firmware.
870 * @blocks: the first firmware block of the file
874 char version[RTL_VER_SIZE];
875 struct fw_block blocks[0];
879 * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
880 * The layout of the firmware block is:
881 * <struct fw_mac> + <info> + <firmware data>.
882 * @fw_offset: offset of the firmware binary data. The start address of
883 * the data would be the address of struct fw_mac + @fw_offset.
884 * @fw_reg: the register to load the firmware. Depends on chip.
885 * @bp_ba_addr: the register to write break point base address. Depends on
887 * @bp_ba_value: break point base address. Depends on chip.
888 * @bp_en_addr: the register to write break point enabled mask. Depends
890 * @bp_en_value: break point enabled mask. Depends on the firmware.
891 * @bp_start: the start register of break points. Depends on chip.
892 * @bp_num: the break point number which needs to be set for this firmware.
893 * Depends on the firmware.
894 * @bp: break points. Depends on firmware.
895 * @fw_ver_reg: the register to store the fw version.
896 * @fw_ver_data: the firmware version of the current type.
897 * @info: additional information for debugging, and is followed by the
898 * binary data of firmware.
901 struct fw_block blk_hdr;
910 __le16 bp[16]; /* any value determined by firmware */
918 * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.
919 * This is used to set patch key when loading the firmware of PHY.
920 * @key_reg: the register to write the patch key.
921 * @key_data: patch key.
923 struct fw_phy_patch_key {
924 struct fw_block blk_hdr;
931 * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.
932 * The layout of the firmware block is:
933 * <struct fw_phy_nc> + <info> + <firmware data>.
934 * @fw_offset: offset of the firmware binary data. The start address of
935 * the data would be the address of struct fw_phy_nc + @fw_offset.
936 * @fw_reg: the register to load the firmware. Depends on chip.
937 * @ba_reg: the register to write the base address. Depends on chip.
938 * @ba_data: base address. Depends on chip.
939 * @patch_en_addr: the register of enabling patch mode. Depends on chip.
940 * @patch_en_value: patch mode enabled mask. Depends on the firmware.
941 * @mode_reg: the regitster of switching the mode.
942 * @mod_pre: the mode needing to be set before loading the firmware.
943 * @mod_post: the mode to be set when finishing to load the firmware.
944 * @bp_start: the start register of break points. Depends on chip.
945 * @bp_num: the break point number which needs to be set for this firmware.
946 * Depends on the firmware.
947 * @bp: break points. Depends on firmware.
948 * @info: additional information for debugging, and is followed by the
949 * binary data of firmware.
952 struct fw_block blk_hdr;
957 __le16 patch_en_addr;
958 __le16 patch_en_value;
998 #define RTL_ADVERTISED_10_HALF BIT(0)
999 #define RTL_ADVERTISED_10_FULL BIT(1)
1000 #define RTL_ADVERTISED_100_HALF BIT(2)
1001 #define RTL_ADVERTISED_100_FULL BIT(3)
1002 #define RTL_ADVERTISED_1000_HALF BIT(4)
1003 #define RTL_ADVERTISED_1000_FULL BIT(5)
1005 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
1006 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
1008 static const int multicast_filter_limit = 32;
1009 static unsigned int agg_buf_sz = 16384;
1011 #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
1012 VLAN_ETH_HLEN - ETH_FCS_LEN)
1015 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1020 tmp = kmalloc(size, GFP_KERNEL);
1024 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
1025 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
1026 value, index, tmp, size, 500);
1028 memset(data, 0xff, size);
1030 memcpy(data, tmp, size);
1038 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1043 tmp = kmemdup(data, size, GFP_KERNEL);
1047 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
1048 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
1049 value, index, tmp, size, 500);
1056 static void rtl_set_unplug(struct r8152 *tp)
1058 if (tp->udev->state == USB_STATE_NOTATTACHED) {
1059 set_bit(RTL8152_UNPLUG, &tp->flags);
1060 smp_mb__after_atomic();
1064 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
1065 void *data, u16 type)
1070 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1073 /* both size and indix must be 4 bytes align */
1074 if ((size & 3) || !size || (index & 3) || !data)
1077 if ((u32)index + (u32)size > 0xffff)
1082 ret = get_registers(tp, index, type, limit, data);
1090 ret = get_registers(tp, index, type, size, data);
1107 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
1108 u16 size, void *data, u16 type)
1111 u16 byteen_start, byteen_end, byen;
1114 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1117 /* both size and indix must be 4 bytes align */
1118 if ((size & 3) || !size || (index & 3) || !data)
1121 if ((u32)index + (u32)size > 0xffff)
1124 byteen_start = byteen & BYTE_EN_START_MASK;
1125 byteen_end = byteen & BYTE_EN_END_MASK;
1127 byen = byteen_start | (byteen_start << 4);
1128 ret = set_registers(tp, index, type | byen, 4, data);
1141 ret = set_registers(tp, index,
1142 type | BYTE_EN_DWORD,
1151 ret = set_registers(tp, index,
1152 type | BYTE_EN_DWORD,
1164 byen = byteen_end | (byteen_end >> 4);
1165 ret = set_registers(tp, index, type | byen, 4, data);
1178 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
1180 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
1184 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1186 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
1190 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1192 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
1195 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
1199 generic_ocp_read(tp, index, sizeof(data), &data, type);
1201 return __le32_to_cpu(data);
1204 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
1206 __le32 tmp = __cpu_to_le32(data);
1208 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
1211 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
1215 u16 byen = BYTE_EN_WORD;
1216 u8 shift = index & 2;
1221 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
1223 data = __le32_to_cpu(tmp);
1224 data >>= (shift * 8);
1230 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1234 u16 byen = BYTE_EN_WORD;
1235 u8 shift = index & 2;
1241 mask <<= (shift * 8);
1242 data <<= (shift * 8);
1246 tmp = __cpu_to_le32(data);
1248 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1251 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1255 u8 shift = index & 3;
1259 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1261 data = __le32_to_cpu(tmp);
1262 data >>= (shift * 8);
1268 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1272 u16 byen = BYTE_EN_BYTE;
1273 u8 shift = index & 3;
1279 mask <<= (shift * 8);
1280 data <<= (shift * 8);
1284 tmp = __cpu_to_le32(data);
1286 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1289 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1291 u16 ocp_base, ocp_index;
1293 ocp_base = addr & 0xf000;
1294 if (ocp_base != tp->ocp_base) {
1295 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1296 tp->ocp_base = ocp_base;
1299 ocp_index = (addr & 0x0fff) | 0xb000;
1300 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1303 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1305 u16 ocp_base, ocp_index;
1307 ocp_base = addr & 0xf000;
1308 if (ocp_base != tp->ocp_base) {
1309 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1310 tp->ocp_base = ocp_base;
1313 ocp_index = (addr & 0x0fff) | 0xb000;
1314 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1317 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1319 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1322 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1324 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1327 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1329 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1330 ocp_reg_write(tp, OCP_SRAM_DATA, data);
1333 static u16 sram_read(struct r8152 *tp, u16 addr)
1335 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1336 return ocp_reg_read(tp, OCP_SRAM_DATA);
1339 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1341 struct r8152 *tp = netdev_priv(netdev);
1344 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1347 if (phy_id != R8152_PHY_ID)
1350 ret = r8152_mdio_read(tp, reg);
1356 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1358 struct r8152 *tp = netdev_priv(netdev);
1360 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1363 if (phy_id != R8152_PHY_ID)
1366 r8152_mdio_write(tp, reg, val);
1370 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1372 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1374 struct r8152 *tp = netdev_priv(netdev);
1375 struct sockaddr *addr = p;
1376 int ret = -EADDRNOTAVAIL;
1378 if (!is_valid_ether_addr(addr->sa_data))
1381 ret = usb_autopm_get_interface(tp->intf);
1385 mutex_lock(&tp->control);
1387 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1389 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1390 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1391 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1393 mutex_unlock(&tp->control);
1395 usb_autopm_put_interface(tp->intf);
1400 /* Devices containing proper chips can support a persistent
1401 * host system provided MAC address.
1402 * Examples of this are Dell TB15 and Dell WD15 docks
1404 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1407 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1408 union acpi_object *obj;
1411 unsigned char buf[6];
1413 acpi_object_type mac_obj_type;
1416 if (test_bit(LENOVO_MACPASSTHRU, &tp->flags)) {
1417 mac_obj_name = "\\MACA";
1418 mac_obj_type = ACPI_TYPE_STRING;
1421 /* test for -AD variant of RTL8153 */
1422 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1423 if ((ocp_data & AD_MASK) == 0x1000) {
1424 /* test for MAC address pass-through bit */
1425 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1426 if ((ocp_data & PASS_THRU_MASK) != 1) {
1427 netif_dbg(tp, probe, tp->netdev,
1428 "No efuse for RTL8153-AD MAC pass through\n");
1432 /* test for RTL8153-BND and RTL8153-BD */
1433 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1434 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1435 netif_dbg(tp, probe, tp->netdev,
1436 "Invalid variant for MAC pass through\n");
1441 mac_obj_name = "\\_SB.AMAC";
1442 mac_obj_type = ACPI_TYPE_BUFFER;
1446 /* returns _AUXMAC_#AABBCCDDEEFF# */
1447 status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer);
1448 obj = (union acpi_object *)buffer.pointer;
1449 if (!ACPI_SUCCESS(status))
1451 if (obj->type != mac_obj_type || obj->string.length != mac_strlen) {
1452 netif_warn(tp, probe, tp->netdev,
1453 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1454 obj->type, obj->string.length);
1458 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1459 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1460 netif_warn(tp, probe, tp->netdev,
1461 "Invalid header when reading pass-thru MAC addr\n");
1464 ret = hex2bin(buf, obj->string.pointer + 9, 6);
1465 if (!(ret == 0 && is_valid_ether_addr(buf))) {
1466 netif_warn(tp, probe, tp->netdev,
1467 "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1472 memcpy(sa->sa_data, buf, 6);
1473 netif_info(tp, probe, tp->netdev,
1474 "Using pass-thru MAC addr %pM\n", sa->sa_data);
1481 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
1483 struct net_device *dev = tp->netdev;
1486 sa->sa_family = dev->type;
1488 if (tp->version == RTL_VER_01) {
1489 ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
1491 /* if device doesn't support MAC pass through this will
1492 * be expected to be non-zero
1494 ret = vendor_mac_passthru_addr_read(tp, sa);
1496 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa->sa_data);
1500 netif_err(tp, probe, dev, "Get ether addr fail\n");
1501 } else if (!is_valid_ether_addr(sa->sa_data)) {
1502 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1504 eth_hw_addr_random(dev);
1505 ether_addr_copy(sa->sa_data, dev->dev_addr);
1506 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1514 static int set_ethernet_addr(struct r8152 *tp)
1516 struct net_device *dev = tp->netdev;
1520 ret = determine_ethernet_addr(tp, &sa);
1524 if (tp->version == RTL_VER_01)
1525 ether_addr_copy(dev->dev_addr, sa.sa_data);
1527 ret = rtl8152_set_mac_address(dev, &sa);
1532 static void read_bulk_callback(struct urb *urb)
1534 struct net_device *netdev;
1535 int status = urb->status;
1538 unsigned long flags;
1548 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1551 if (!test_bit(WORK_ENABLE, &tp->flags))
1554 netdev = tp->netdev;
1556 /* When link down, the driver would cancel all bulks. */
1557 /* This avoid the re-submitting bulk */
1558 if (!netif_carrier_ok(netdev))
1561 usb_mark_last_busy(tp->udev);
1565 if (urb->actual_length < ETH_ZLEN)
1568 spin_lock_irqsave(&tp->rx_lock, flags);
1569 list_add_tail(&agg->list, &tp->rx_done);
1570 spin_unlock_irqrestore(&tp->rx_lock, flags);
1571 napi_schedule(&tp->napi);
1575 netif_device_detach(tp->netdev);
1578 return; /* the urb is in unlink state */
1580 if (net_ratelimit())
1581 netdev_warn(netdev, "maybe reset is needed?\n");
1584 if (net_ratelimit())
1585 netdev_warn(netdev, "Rx status %d\n", status);
1589 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1592 static void write_bulk_callback(struct urb *urb)
1594 struct net_device_stats *stats;
1595 struct net_device *netdev;
1598 unsigned long flags;
1599 int status = urb->status;
1609 netdev = tp->netdev;
1610 stats = &netdev->stats;
1612 if (net_ratelimit())
1613 netdev_warn(netdev, "Tx status %d\n", status);
1614 stats->tx_errors += agg->skb_num;
1616 stats->tx_packets += agg->skb_num;
1617 stats->tx_bytes += agg->skb_len;
1620 spin_lock_irqsave(&tp->tx_lock, flags);
1621 list_add_tail(&agg->list, &tp->tx_free);
1622 spin_unlock_irqrestore(&tp->tx_lock, flags);
1624 usb_autopm_put_interface_async(tp->intf);
1626 if (!netif_carrier_ok(netdev))
1629 if (!test_bit(WORK_ENABLE, &tp->flags))
1632 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1635 if (!skb_queue_empty(&tp->tx_queue))
1636 tasklet_schedule(&tp->tx_tl);
1639 static void intr_callback(struct urb *urb)
1643 int status = urb->status;
1650 if (!test_bit(WORK_ENABLE, &tp->flags))
1653 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1657 case 0: /* success */
1659 case -ECONNRESET: /* unlink */
1661 netif_device_detach(tp->netdev);
1665 netif_info(tp, intr, tp->netdev,
1666 "Stop submitting intr, status %d\n", status);
1669 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1671 /* -EPIPE: should clear the halt */
1673 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1677 d = urb->transfer_buffer;
1678 if (INTR_LINK & __le16_to_cpu(d[0])) {
1679 if (!netif_carrier_ok(tp->netdev)) {
1680 set_bit(RTL8152_LINK_CHG, &tp->flags);
1681 schedule_delayed_work(&tp->schedule, 0);
1684 if (netif_carrier_ok(tp->netdev)) {
1685 netif_stop_queue(tp->netdev);
1686 set_bit(RTL8152_LINK_CHG, &tp->flags);
1687 schedule_delayed_work(&tp->schedule, 0);
1692 res = usb_submit_urb(urb, GFP_ATOMIC);
1693 if (res == -ENODEV) {
1695 netif_device_detach(tp->netdev);
1697 netif_err(tp, intr, tp->netdev,
1698 "can't resubmit intr, status %d\n", res);
1702 static inline void *rx_agg_align(void *data)
1704 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1707 static inline void *tx_agg_align(void *data)
1709 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1712 static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
1714 list_del(&agg->info_list);
1716 usb_free_urb(agg->urb);
1717 put_page(agg->page);
1720 atomic_dec(&tp->rx_count);
1723 static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
1725 struct net_device *netdev = tp->netdev;
1726 int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1727 unsigned int order = get_order(tp->rx_buf_sz);
1728 struct rx_agg *rx_agg;
1729 unsigned long flags;
1731 rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);
1735 rx_agg->page = alloc_pages(mflags | __GFP_COMP, order);
1739 rx_agg->buffer = page_address(rx_agg->page);
1741 rx_agg->urb = usb_alloc_urb(0, mflags);
1745 rx_agg->context = tp;
1747 INIT_LIST_HEAD(&rx_agg->list);
1748 INIT_LIST_HEAD(&rx_agg->info_list);
1749 spin_lock_irqsave(&tp->rx_lock, flags);
1750 list_add_tail(&rx_agg->info_list, &tp->rx_info);
1751 spin_unlock_irqrestore(&tp->rx_lock, flags);
1753 atomic_inc(&tp->rx_count);
1758 __free_pages(rx_agg->page, order);
1764 static void free_all_mem(struct r8152 *tp)
1766 struct rx_agg *agg, *agg_next;
1767 unsigned long flags;
1770 spin_lock_irqsave(&tp->rx_lock, flags);
1772 list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
1773 free_rx_agg(tp, agg);
1775 spin_unlock_irqrestore(&tp->rx_lock, flags);
1777 WARN_ON(atomic_read(&tp->rx_count));
1779 for (i = 0; i < RTL8152_MAX_TX; i++) {
1780 usb_free_urb(tp->tx_info[i].urb);
1781 tp->tx_info[i].urb = NULL;
1783 kfree(tp->tx_info[i].buffer);
1784 tp->tx_info[i].buffer = NULL;
1785 tp->tx_info[i].head = NULL;
1788 usb_free_urb(tp->intr_urb);
1789 tp->intr_urb = NULL;
1791 kfree(tp->intr_buff);
1792 tp->intr_buff = NULL;
1795 static int alloc_all_mem(struct r8152 *tp)
1797 struct net_device *netdev = tp->netdev;
1798 struct usb_interface *intf = tp->intf;
1799 struct usb_host_interface *alt = intf->cur_altsetting;
1800 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1803 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1805 spin_lock_init(&tp->rx_lock);
1806 spin_lock_init(&tp->tx_lock);
1807 INIT_LIST_HEAD(&tp->rx_info);
1808 INIT_LIST_HEAD(&tp->tx_free);
1809 INIT_LIST_HEAD(&tp->rx_done);
1810 skb_queue_head_init(&tp->tx_queue);
1811 skb_queue_head_init(&tp->rx_queue);
1812 atomic_set(&tp->rx_count, 0);
1814 for (i = 0; i < RTL8152_MAX_RX; i++) {
1815 if (!alloc_rx_agg(tp, GFP_KERNEL))
1819 for (i = 0; i < RTL8152_MAX_TX; i++) {
1823 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1827 if (buf != tx_agg_align(buf)) {
1829 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1835 urb = usb_alloc_urb(0, GFP_KERNEL);
1841 INIT_LIST_HEAD(&tp->tx_info[i].list);
1842 tp->tx_info[i].context = tp;
1843 tp->tx_info[i].urb = urb;
1844 tp->tx_info[i].buffer = buf;
1845 tp->tx_info[i].head = tx_agg_align(buf);
1847 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1850 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1854 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1858 tp->intr_interval = (int)ep_intr->desc.bInterval;
1859 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1860 tp->intr_buff, INTBUFSIZE, intr_callback,
1861 tp, tp->intr_interval);
1870 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1872 struct tx_agg *agg = NULL;
1873 unsigned long flags;
1875 if (list_empty(&tp->tx_free))
1878 spin_lock_irqsave(&tp->tx_lock, flags);
1879 if (!list_empty(&tp->tx_free)) {
1880 struct list_head *cursor;
1882 cursor = tp->tx_free.next;
1883 list_del_init(cursor);
1884 agg = list_entry(cursor, struct tx_agg, list);
1886 spin_unlock_irqrestore(&tp->tx_lock, flags);
1891 /* r8152_csum_workaround()
1892 * The hw limits the value of the transport offset. When the offset is out of
1893 * range, calculate the checksum by sw.
1895 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1896 struct sk_buff_head *list)
1898 if (skb_shinfo(skb)->gso_size) {
1899 netdev_features_t features = tp->netdev->features;
1900 struct sk_buff_head seg_list;
1901 struct sk_buff *segs, *nskb;
1903 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1904 segs = skb_gso_segment(skb, features);
1905 if (IS_ERR(segs) || !segs)
1908 __skb_queue_head_init(&seg_list);
1914 __skb_queue_tail(&seg_list, nskb);
1917 skb_queue_splice(&seg_list, list);
1919 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1920 if (skb_checksum_help(skb) < 0)
1923 __skb_queue_head(list, skb);
1925 struct net_device_stats *stats;
1928 stats = &tp->netdev->stats;
1929 stats->tx_dropped++;
1934 /* msdn_giant_send_check()
1935 * According to the document of microsoft, the TCP Pseudo Header excludes the
1936 * packet length for IPv6 TCP large packets.
1938 static int msdn_giant_send_check(struct sk_buff *skb)
1940 const struct ipv6hdr *ipv6h;
1944 ret = skb_cow_head(skb, 0);
1948 ipv6h = ipv6_hdr(skb);
1952 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1957 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1959 if (skb_vlan_tag_present(skb)) {
1962 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1963 desc->opts2 |= cpu_to_le32(opts2);
1967 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1969 u32 opts2 = le32_to_cpu(desc->opts2);
1971 if (opts2 & RX_VLAN_TAG)
1972 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1973 swab16(opts2 & 0xffff));
1976 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1977 struct sk_buff *skb, u32 len, u32 transport_offset)
1979 u32 mss = skb_shinfo(skb)->gso_size;
1980 u32 opts1, opts2 = 0;
1981 int ret = TX_CSUM_SUCCESS;
1983 WARN_ON_ONCE(len > TX_LEN_MAX);
1985 opts1 = len | TX_FS | TX_LS;
1988 if (transport_offset > GTTCPHO_MAX) {
1989 netif_warn(tp, tx_err, tp->netdev,
1990 "Invalid transport offset 0x%x for TSO\n",
1996 switch (vlan_get_protocol(skb)) {
1997 case htons(ETH_P_IP):
2001 case htons(ETH_P_IPV6):
2002 if (msdn_giant_send_check(skb)) {
2014 opts1 |= transport_offset << GTTCPHO_SHIFT;
2015 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
2016 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2019 if (transport_offset > TCPHO_MAX) {
2020 netif_warn(tp, tx_err, tp->netdev,
2021 "Invalid transport offset 0x%x\n",
2027 switch (vlan_get_protocol(skb)) {
2028 case htons(ETH_P_IP):
2030 ip_protocol = ip_hdr(skb)->protocol;
2033 case htons(ETH_P_IPV6):
2035 ip_protocol = ipv6_hdr(skb)->nexthdr;
2039 ip_protocol = IPPROTO_RAW;
2043 if (ip_protocol == IPPROTO_TCP)
2045 else if (ip_protocol == IPPROTO_UDP)
2050 opts2 |= transport_offset << TCPHO_SHIFT;
2053 desc->opts2 = cpu_to_le32(opts2);
2054 desc->opts1 = cpu_to_le32(opts1);
2060 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
2062 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2066 __skb_queue_head_init(&skb_head);
2067 spin_lock(&tx_queue->lock);
2068 skb_queue_splice_init(tx_queue, &skb_head);
2069 spin_unlock(&tx_queue->lock);
2071 tx_data = agg->head;
2074 remain = agg_buf_sz;
2076 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
2077 struct tx_desc *tx_desc;
2078 struct sk_buff *skb;
2082 skb = __skb_dequeue(&skb_head);
2086 len = skb->len + sizeof(*tx_desc);
2089 __skb_queue_head(&skb_head, skb);
2093 tx_data = tx_agg_align(tx_data);
2094 tx_desc = (struct tx_desc *)tx_data;
2096 offset = (u32)skb_transport_offset(skb);
2098 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
2099 r8152_csum_workaround(tp, skb, &skb_head);
2103 rtl_tx_vlan_tag(tx_desc, skb);
2105 tx_data += sizeof(*tx_desc);
2108 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
2109 struct net_device_stats *stats = &tp->netdev->stats;
2111 stats->tx_dropped++;
2112 dev_kfree_skb_any(skb);
2113 tx_data -= sizeof(*tx_desc);
2118 agg->skb_len += len;
2119 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
2121 dev_kfree_skb_any(skb);
2123 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
2125 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
2129 if (!skb_queue_empty(&skb_head)) {
2130 spin_lock(&tx_queue->lock);
2131 skb_queue_splice(&skb_head, tx_queue);
2132 spin_unlock(&tx_queue->lock);
2135 netif_tx_lock(tp->netdev);
2137 if (netif_queue_stopped(tp->netdev) &&
2138 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
2139 netif_wake_queue(tp->netdev);
2141 netif_tx_unlock(tp->netdev);
2143 ret = usb_autopm_get_interface_async(tp->intf);
2147 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
2148 agg->head, (int)(tx_data - (u8 *)agg->head),
2149 (usb_complete_t)write_bulk_callback, agg);
2151 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
2153 usb_autopm_put_interface_async(tp->intf);
2159 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
2161 u8 checksum = CHECKSUM_NONE;
2164 if (!(tp->netdev->features & NETIF_F_RXCSUM))
2167 opts2 = le32_to_cpu(rx_desc->opts2);
2168 opts3 = le32_to_cpu(rx_desc->opts3);
2170 if (opts2 & RD_IPV4_CS) {
2172 checksum = CHECKSUM_NONE;
2173 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2174 checksum = CHECKSUM_UNNECESSARY;
2175 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2176 checksum = CHECKSUM_UNNECESSARY;
2177 } else if (opts2 & RD_IPV6_CS) {
2178 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2179 checksum = CHECKSUM_UNNECESSARY;
2180 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2181 checksum = CHECKSUM_UNNECESSARY;
2188 static inline bool rx_count_exceed(struct r8152 *tp)
2190 return atomic_read(&tp->rx_count) > RTL8152_MAX_RX;
2193 static inline int agg_offset(struct rx_agg *agg, void *addr)
2195 return (int)(addr - agg->buffer);
2198 static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
2200 struct rx_agg *agg, *agg_next, *agg_free = NULL;
2201 unsigned long flags;
2203 spin_lock_irqsave(&tp->rx_lock, flags);
2205 list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
2206 if (page_count(agg->page) == 1) {
2208 list_del_init(&agg->list);
2212 if (rx_count_exceed(tp)) {
2213 list_del_init(&agg->list);
2214 free_rx_agg(tp, agg);
2220 spin_unlock_irqrestore(&tp->rx_lock, flags);
2222 if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending)
2223 agg_free = alloc_rx_agg(tp, mflags);
2228 static int rx_bottom(struct r8152 *tp, int budget)
2230 unsigned long flags;
2231 struct list_head *cursor, *next, rx_queue;
2232 int ret = 0, work_done = 0;
2233 struct napi_struct *napi = &tp->napi;
2235 if (!skb_queue_empty(&tp->rx_queue)) {
2236 while (work_done < budget) {
2237 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
2238 struct net_device *netdev = tp->netdev;
2239 struct net_device_stats *stats = &netdev->stats;
2240 unsigned int pkt_len;
2246 napi_gro_receive(napi, skb);
2248 stats->rx_packets++;
2249 stats->rx_bytes += pkt_len;
2253 if (list_empty(&tp->rx_done))
2256 INIT_LIST_HEAD(&rx_queue);
2257 spin_lock_irqsave(&tp->rx_lock, flags);
2258 list_splice_init(&tp->rx_done, &rx_queue);
2259 spin_unlock_irqrestore(&tp->rx_lock, flags);
2261 list_for_each_safe(cursor, next, &rx_queue) {
2262 struct rx_desc *rx_desc;
2263 struct rx_agg *agg, *agg_free;
2268 list_del_init(cursor);
2270 agg = list_entry(cursor, struct rx_agg, list);
2272 if (urb->actual_length < ETH_ZLEN)
2275 agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
2277 rx_desc = agg->buffer;
2278 rx_data = agg->buffer;
2279 len_used += sizeof(struct rx_desc);
2281 while (urb->actual_length > len_used) {
2282 struct net_device *netdev = tp->netdev;
2283 struct net_device_stats *stats = &netdev->stats;
2284 unsigned int pkt_len, rx_frag_head_sz;
2285 struct sk_buff *skb;
2287 /* limite the skb numbers for rx_queue */
2288 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
2291 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
2292 if (pkt_len < ETH_ZLEN)
2295 len_used += pkt_len;
2296 if (urb->actual_length < len_used)
2299 pkt_len -= ETH_FCS_LEN;
2300 rx_data += sizeof(struct rx_desc);
2302 if (!agg_free || tp->rx_copybreak > pkt_len)
2303 rx_frag_head_sz = pkt_len;
2305 rx_frag_head_sz = tp->rx_copybreak;
2307 skb = napi_alloc_skb(napi, rx_frag_head_sz);
2309 stats->rx_dropped++;
2313 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
2314 memcpy(skb->data, rx_data, rx_frag_head_sz);
2315 skb_put(skb, rx_frag_head_sz);
2316 pkt_len -= rx_frag_head_sz;
2317 rx_data += rx_frag_head_sz;
2319 skb_add_rx_frag(skb, 0, agg->page,
2320 agg_offset(agg, rx_data),
2322 SKB_DATA_ALIGN(pkt_len));
2323 get_page(agg->page);
2326 skb->protocol = eth_type_trans(skb, netdev);
2327 rtl_rx_vlan_tag(rx_desc, skb);
2328 if (work_done < budget) {
2330 stats->rx_packets++;
2331 stats->rx_bytes += skb->len;
2332 napi_gro_receive(napi, skb);
2334 __skb_queue_tail(&tp->rx_queue, skb);
2338 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
2339 rx_desc = (struct rx_desc *)rx_data;
2340 len_used = agg_offset(agg, rx_data);
2341 len_used += sizeof(struct rx_desc);
2344 WARN_ON(!agg_free && page_count(agg->page) > 1);
2347 spin_lock_irqsave(&tp->rx_lock, flags);
2348 if (page_count(agg->page) == 1) {
2349 list_add(&agg_free->list, &tp->rx_used);
2351 list_add_tail(&agg->list, &tp->rx_used);
2355 spin_unlock_irqrestore(&tp->rx_lock, flags);
2360 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
2362 urb->actual_length = 0;
2363 list_add_tail(&agg->list, next);
2367 if (!list_empty(&rx_queue)) {
2368 spin_lock_irqsave(&tp->rx_lock, flags);
2369 list_splice_tail(&rx_queue, &tp->rx_done);
2370 spin_unlock_irqrestore(&tp->rx_lock, flags);
2377 static void tx_bottom(struct r8152 *tp)
2382 struct net_device *netdev = tp->netdev;
2385 if (skb_queue_empty(&tp->tx_queue))
2388 agg = r8152_get_tx_agg(tp);
2392 res = r8152_tx_agg_fill(tp, agg);
2396 if (res == -ENODEV) {
2398 netif_device_detach(netdev);
2400 struct net_device_stats *stats = &netdev->stats;
2401 unsigned long flags;
2403 netif_warn(tp, tx_err, netdev,
2404 "failed tx_urb %d\n", res);
2405 stats->tx_dropped += agg->skb_num;
2407 spin_lock_irqsave(&tp->tx_lock, flags);
2408 list_add_tail(&agg->list, &tp->tx_free);
2409 spin_unlock_irqrestore(&tp->tx_lock, flags);
2414 static void bottom_half(unsigned long data)
2418 tp = (struct r8152 *)data;
2420 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2423 if (!test_bit(WORK_ENABLE, &tp->flags))
2426 /* When link down, the driver would cancel all bulks. */
2427 /* This avoid the re-submitting bulk */
2428 if (!netif_carrier_ok(tp->netdev))
2431 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2436 static int r8152_poll(struct napi_struct *napi, int budget)
2438 struct r8152 *tp = container_of(napi, struct r8152, napi);
2441 work_done = rx_bottom(tp, budget);
2443 if (work_done < budget) {
2444 if (!napi_complete_done(napi, work_done))
2446 if (!list_empty(&tp->rx_done))
2447 napi_schedule(napi);
2455 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2459 /* The rx would be stopped, so skip submitting */
2460 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2461 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2464 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
2465 agg->buffer, tp->rx_buf_sz,
2466 (usb_complete_t)read_bulk_callback, agg);
2468 ret = usb_submit_urb(agg->urb, mem_flags);
2469 if (ret == -ENODEV) {
2471 netif_device_detach(tp->netdev);
2473 struct urb *urb = agg->urb;
2474 unsigned long flags;
2476 urb->actual_length = 0;
2477 spin_lock_irqsave(&tp->rx_lock, flags);
2478 list_add_tail(&agg->list, &tp->rx_done);
2479 spin_unlock_irqrestore(&tp->rx_lock, flags);
2481 netif_err(tp, rx_err, tp->netdev,
2482 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2484 napi_schedule(&tp->napi);
2490 static void rtl_drop_queued_tx(struct r8152 *tp)
2492 struct net_device_stats *stats = &tp->netdev->stats;
2493 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2494 struct sk_buff *skb;
2496 if (skb_queue_empty(tx_queue))
2499 __skb_queue_head_init(&skb_head);
2500 spin_lock_bh(&tx_queue->lock);
2501 skb_queue_splice_init(tx_queue, &skb_head);
2502 spin_unlock_bh(&tx_queue->lock);
2504 while ((skb = __skb_dequeue(&skb_head))) {
2506 stats->tx_dropped++;
2510 static void rtl8152_tx_timeout(struct net_device *netdev)
2512 struct r8152 *tp = netdev_priv(netdev);
2514 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2516 usb_queue_reset_device(tp->intf);
2519 static void rtl8152_set_rx_mode(struct net_device *netdev)
2521 struct r8152 *tp = netdev_priv(netdev);
2523 if (netif_carrier_ok(netdev)) {
2524 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2525 schedule_delayed_work(&tp->schedule, 0);
2529 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2531 struct r8152 *tp = netdev_priv(netdev);
2532 u32 mc_filter[2]; /* Multicast hash filter */
2536 netif_stop_queue(netdev);
2537 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2538 ocp_data &= ~RCR_ACPT_ALL;
2539 ocp_data |= RCR_AB | RCR_APM;
2541 if (netdev->flags & IFF_PROMISC) {
2542 /* Unconditionally log net taps. */
2543 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2544 ocp_data |= RCR_AM | RCR_AAP;
2545 mc_filter[1] = 0xffffffff;
2546 mc_filter[0] = 0xffffffff;
2547 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2548 (netdev->flags & IFF_ALLMULTI)) {
2549 /* Too many to filter perfectly -- accept all multicasts. */
2551 mc_filter[1] = 0xffffffff;
2552 mc_filter[0] = 0xffffffff;
2554 struct netdev_hw_addr *ha;
2558 netdev_for_each_mc_addr(ha, netdev) {
2559 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2561 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2566 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2567 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2569 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2570 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2571 netif_wake_queue(netdev);
2574 static netdev_features_t
2575 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2576 netdev_features_t features)
2578 u32 mss = skb_shinfo(skb)->gso_size;
2579 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2580 int offset = skb_transport_offset(skb);
2582 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2583 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2584 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2585 features &= ~NETIF_F_GSO_MASK;
2590 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2591 struct net_device *netdev)
2593 struct r8152 *tp = netdev_priv(netdev);
2595 skb_tx_timestamp(skb);
2597 skb_queue_tail(&tp->tx_queue, skb);
2599 if (!list_empty(&tp->tx_free)) {
2600 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2601 set_bit(SCHEDULE_TASKLET, &tp->flags);
2602 schedule_delayed_work(&tp->schedule, 0);
2604 usb_mark_last_busy(tp->udev);
2605 tasklet_schedule(&tp->tx_tl);
2607 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2608 netif_stop_queue(netdev);
2611 return NETDEV_TX_OK;
2614 static void r8152b_reset_packet_filter(struct r8152 *tp)
2618 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2619 ocp_data &= ~FMC_FCR_MCU_EN;
2620 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2621 ocp_data |= FMC_FCR_MCU_EN;
2622 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2625 static void rtl8152_nic_reset(struct r8152 *tp)
2629 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2631 for (i = 0; i < 1000; i++) {
2632 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2634 usleep_range(100, 400);
2638 static void set_tx_qlen(struct r8152 *tp)
2640 struct net_device *netdev = tp->netdev;
2642 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
2643 sizeof(struct tx_desc));
2646 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2648 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2651 static void rtl_set_eee_plus(struct r8152 *tp)
2656 speed = rtl8152_get_speed(tp);
2657 if (speed & _10bps) {
2658 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2659 ocp_data |= EEEP_CR_EEEP_TX;
2660 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2662 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2663 ocp_data &= ~EEEP_CR_EEEP_TX;
2664 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2668 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2672 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2674 ocp_data |= RXDY_GATED_EN;
2676 ocp_data &= ~RXDY_GATED_EN;
2677 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2680 static int rtl_start_rx(struct r8152 *tp)
2682 struct rx_agg *agg, *agg_next;
2683 struct list_head tmp_list;
2684 unsigned long flags;
2687 INIT_LIST_HEAD(&tmp_list);
2689 spin_lock_irqsave(&tp->rx_lock, flags);
2691 INIT_LIST_HEAD(&tp->rx_done);
2692 INIT_LIST_HEAD(&tp->rx_used);
2694 list_splice_init(&tp->rx_info, &tmp_list);
2696 spin_unlock_irqrestore(&tp->rx_lock, flags);
2698 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2699 INIT_LIST_HEAD(&agg->list);
2701 /* Only RTL8152_MAX_RX rx_agg need to be submitted. */
2702 if (++i > RTL8152_MAX_RX) {
2703 spin_lock_irqsave(&tp->rx_lock, flags);
2704 list_add_tail(&agg->list, &tp->rx_used);
2705 spin_unlock_irqrestore(&tp->rx_lock, flags);
2706 } else if (unlikely(ret < 0)) {
2707 spin_lock_irqsave(&tp->rx_lock, flags);
2708 list_add_tail(&agg->list, &tp->rx_done);
2709 spin_unlock_irqrestore(&tp->rx_lock, flags);
2711 ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
2715 spin_lock_irqsave(&tp->rx_lock, flags);
2716 WARN_ON(!list_empty(&tp->rx_info));
2717 list_splice(&tmp_list, &tp->rx_info);
2718 spin_unlock_irqrestore(&tp->rx_lock, flags);
2723 static int rtl_stop_rx(struct r8152 *tp)
2725 struct rx_agg *agg, *agg_next;
2726 struct list_head tmp_list;
2727 unsigned long flags;
2729 INIT_LIST_HEAD(&tmp_list);
2731 /* The usb_kill_urb() couldn't be used in atomic.
2732 * Therefore, move the list of rx_info to a tmp one.
2733 * Then, list_for_each_entry_safe could be used without
2737 spin_lock_irqsave(&tp->rx_lock, flags);
2738 list_splice_init(&tp->rx_info, &tmp_list);
2739 spin_unlock_irqrestore(&tp->rx_lock, flags);
2741 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2742 /* At least RTL8152_MAX_RX rx_agg have the page_count being
2743 * equal to 1, so the other ones could be freed safely.
2745 if (page_count(agg->page) > 1)
2746 free_rx_agg(tp, agg);
2748 usb_kill_urb(agg->urb);
2751 /* Move back the list of temp to the rx_info */
2752 spin_lock_irqsave(&tp->rx_lock, flags);
2753 WARN_ON(!list_empty(&tp->rx_info));
2754 list_splice(&tmp_list, &tp->rx_info);
2755 spin_unlock_irqrestore(&tp->rx_lock, flags);
2757 while (!skb_queue_empty(&tp->rx_queue))
2758 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2763 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2765 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2766 OWN_UPDATE | OWN_CLEAR);
2769 static int rtl_enable(struct r8152 *tp)
2773 r8152b_reset_packet_filter(tp);
2775 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2776 ocp_data |= CR_RE | CR_TE;
2777 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2779 switch (tp->version) {
2782 r8153b_rx_agg_chg_indicate(tp);
2788 rxdy_gated_en(tp, false);
2793 static int rtl8152_enable(struct r8152 *tp)
2795 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2799 rtl_set_eee_plus(tp);
2801 return rtl_enable(tp);
2804 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2806 u32 ocp_data = tp->coalesce / 8;
2808 switch (tp->version) {
2813 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2819 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
2820 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
2822 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2824 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
2833 static void r8153_set_rx_early_size(struct r8152 *tp)
2835 u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
2837 switch (tp->version) {
2842 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2847 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2856 static int rtl8153_enable(struct r8152 *tp)
2858 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2862 rtl_set_eee_plus(tp);
2863 r8153_set_rx_early_timeout(tp);
2864 r8153_set_rx_early_size(tp);
2866 return rtl_enable(tp);
2869 static void rtl_disable(struct r8152 *tp)
2874 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2875 rtl_drop_queued_tx(tp);
2879 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2880 ocp_data &= ~RCR_ACPT_ALL;
2881 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2883 rtl_drop_queued_tx(tp);
2885 for (i = 0; i < RTL8152_MAX_TX; i++)
2886 usb_kill_urb(tp->tx_info[i].urb);
2888 rxdy_gated_en(tp, true);
2890 for (i = 0; i < 1000; i++) {
2891 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2892 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2894 usleep_range(1000, 2000);
2897 for (i = 0; i < 1000; i++) {
2898 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2900 usleep_range(1000, 2000);
2905 rtl8152_nic_reset(tp);
2908 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2912 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2914 ocp_data |= POWER_CUT;
2916 ocp_data &= ~POWER_CUT;
2917 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2919 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2920 ocp_data &= ~RESUME_INDICATE;
2921 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2924 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2928 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2930 ocp_data |= CPCR_RX_VLAN;
2932 ocp_data &= ~CPCR_RX_VLAN;
2933 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2936 static int rtl8152_set_features(struct net_device *dev,
2937 netdev_features_t features)
2939 netdev_features_t changed = features ^ dev->features;
2940 struct r8152 *tp = netdev_priv(dev);
2943 ret = usb_autopm_get_interface(tp->intf);
2947 mutex_lock(&tp->control);
2949 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2950 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2951 rtl_rx_vlan_en(tp, true);
2953 rtl_rx_vlan_en(tp, false);
2956 mutex_unlock(&tp->control);
2958 usb_autopm_put_interface(tp->intf);
2964 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2966 static u32 __rtl_get_wol(struct r8152 *tp)
2971 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2972 if (ocp_data & LINK_ON_WAKE_EN)
2973 wolopts |= WAKE_PHY;
2975 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2976 if (ocp_data & UWF_EN)
2977 wolopts |= WAKE_UCAST;
2978 if (ocp_data & BWF_EN)
2979 wolopts |= WAKE_BCAST;
2980 if (ocp_data & MWF_EN)
2981 wolopts |= WAKE_MCAST;
2983 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2984 if (ocp_data & MAGIC_EN)
2985 wolopts |= WAKE_MAGIC;
2990 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2994 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2996 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2997 ocp_data &= ~LINK_ON_WAKE_EN;
2998 if (wolopts & WAKE_PHY)
2999 ocp_data |= LINK_ON_WAKE_EN;
3000 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3002 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3003 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
3004 if (wolopts & WAKE_UCAST)
3006 if (wolopts & WAKE_BCAST)
3008 if (wolopts & WAKE_MCAST)
3010 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
3012 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3014 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3015 ocp_data &= ~MAGIC_EN;
3016 if (wolopts & WAKE_MAGIC)
3017 ocp_data |= MAGIC_EN;
3018 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
3020 if (wolopts & WAKE_ANY)
3021 device_set_wakeup_enable(&tp->udev->dev, true);
3023 device_set_wakeup_enable(&tp->udev->dev, false);
3026 static void r8153_mac_clk_spd(struct r8152 *tp, bool enable)
3028 /* MAC clock speed down */
3030 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
3032 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2,
3034 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3035 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3036 U1U2_SPDWN_EN | L1_SPDWN_EN);
3037 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3038 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3039 TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN |
3042 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
3043 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
3044 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
3045 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
3049 static void r8153_u1u2en(struct r8152 *tp, bool enable)
3054 memset(u1u2, 0xff, sizeof(u1u2));
3056 memset(u1u2, 0x00, sizeof(u1u2));
3058 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
3061 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
3065 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
3067 ocp_data |= LPM_U1U2_EN;
3069 ocp_data &= ~LPM_U1U2_EN;
3071 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
3074 static void r8153_u2p3en(struct r8152 *tp, bool enable)
3078 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
3080 ocp_data |= U2P3_ENABLE;
3082 ocp_data &= ~U2P3_ENABLE;
3083 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
3086 static void r8153b_ups_flags(struct r8152 *tp)
3090 if (tp->ups_info.green)
3091 ups_flags |= UPS_FLAGS_EN_GREEN;
3093 if (tp->ups_info.aldps)
3094 ups_flags |= UPS_FLAGS_EN_ALDPS;
3096 if (tp->ups_info.eee)
3097 ups_flags |= UPS_FLAGS_EN_EEE;
3099 if (tp->ups_info.flow_control)
3100 ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3102 if (tp->ups_info.eee_ckdiv)
3103 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3105 if (tp->ups_info.eee_cmod_lv)
3106 ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
3108 if (tp->ups_info._10m_ckdiv)
3109 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3111 if (tp->ups_info.eee_plloff_100)
3112 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3114 if (tp->ups_info.eee_plloff_giga)
3115 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3117 if (tp->ups_info._250m_ckdiv)
3118 ups_flags |= UPS_FLAGS_250M_CKDIV;
3120 if (tp->ups_info.ctap_short_off)
3121 ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
3123 switch (tp->ups_info.speed_duplex) {
3125 ups_flags |= ups_flags_speed(1);
3128 ups_flags |= ups_flags_speed(2);
3130 case NWAY_100M_HALF:
3131 ups_flags |= ups_flags_speed(3);
3133 case NWAY_100M_FULL:
3134 ups_flags |= ups_flags_speed(4);
3136 case NWAY_1000M_FULL:
3137 ups_flags |= ups_flags_speed(5);
3139 case FORCE_10M_HALF:
3140 ups_flags |= ups_flags_speed(6);
3142 case FORCE_10M_FULL:
3143 ups_flags |= ups_flags_speed(7);
3145 case FORCE_100M_HALF:
3146 ups_flags |= ups_flags_speed(8);
3148 case FORCE_100M_FULL:
3149 ups_flags |= ups_flags_speed(9);
3155 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3158 static void r8153b_green_en(struct r8152 *tp, bool enable)
3163 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */
3164 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
3165 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
3167 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
3168 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
3169 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
3172 data = sram_read(tp, SRAM_GREEN_CFG);
3173 data |= GREEN_ETH_EN;
3174 sram_write(tp, SRAM_GREEN_CFG, data);
3176 tp->ups_info.green = enable;
3179 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
3184 for (i = 0; i < 500; i++) {
3185 data = ocp_reg_read(tp, OCP_PHY_STATUS);
3186 data &= PHY_STAT_MASK;
3188 if (data == desired)
3190 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
3191 data == PHY_STAT_EXT_INIT) {
3201 static void r8153b_ups_en(struct r8152 *tp, bool enable)
3203 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3206 r8153b_ups_flags(tp);
3208 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3209 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3211 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
3213 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
3217 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3218 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3220 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
3221 ocp_data &= ~BIT(0);
3222 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
3224 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3225 ocp_data &= ~PCUT_STATUS;
3226 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3228 data = r8153_phy_status(tp, 0);
3231 case PHY_STAT_PWRDN:
3232 case PHY_STAT_EXT_INIT:
3234 test_bit(GREEN_ETHERNET, &tp->flags));
3236 data = r8152_mdio_read(tp, MII_BMCR);
3237 data &= ~BMCR_PDOWN;
3239 r8152_mdio_write(tp, MII_BMCR, data);
3241 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
3245 if (data != PHY_STAT_LAN_ON)
3246 netif_warn(tp, link, tp->netdev,
3253 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
3257 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3259 ocp_data |= PWR_EN | PHASE2_EN;
3261 ocp_data &= ~(PWR_EN | PHASE2_EN);
3262 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3264 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3265 ocp_data &= ~PCUT_STATUS;
3266 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3269 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
3273 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3275 ocp_data |= PWR_EN | PHASE2_EN;
3277 ocp_data &= ~PWR_EN;
3278 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3280 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3281 ocp_data &= ~PCUT_STATUS;
3282 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3285 static void r8153_queue_wake(struct r8152 *tp, bool enable)
3289 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
3291 ocp_data |= UPCOMING_RUNTIME_D3;
3293 ocp_data &= ~UPCOMING_RUNTIME_D3;
3294 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
3296 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
3297 ocp_data &= ~LINK_CHG_EVENT;
3298 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
3300 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
3301 ocp_data &= ~LINK_CHANGE_FLAG;
3302 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
3305 static bool rtl_can_wakeup(struct r8152 *tp)
3307 struct usb_device *udev = tp->udev;
3309 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
3312 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
3317 __rtl_set_wol(tp, WAKE_ANY);
3319 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3321 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3322 ocp_data |= LINK_OFF_WAKE_EN;
3323 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3325 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3329 __rtl_set_wol(tp, tp->saved_wolopts);
3331 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3333 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3334 ocp_data &= ~LINK_OFF_WAKE_EN;
3335 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3337 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3341 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
3344 r8153_u1u2en(tp, false);
3345 r8153_u2p3en(tp, false);
3346 r8153_mac_clk_spd(tp, true);
3347 rtl_runtime_suspend_enable(tp, true);
3349 rtl_runtime_suspend_enable(tp, false);
3350 r8153_mac_clk_spd(tp, false);
3352 switch (tp->version) {
3359 r8153_u2p3en(tp, true);
3363 r8153_u1u2en(tp, true);
3367 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
3370 r8153_queue_wake(tp, true);
3371 r8153b_u1u2en(tp, false);
3372 r8153_u2p3en(tp, false);
3373 rtl_runtime_suspend_enable(tp, true);
3374 r8153b_ups_en(tp, true);
3376 r8153b_ups_en(tp, false);
3377 r8153_queue_wake(tp, false);
3378 rtl_runtime_suspend_enable(tp, false);
3379 r8153_u2p3en(tp, true);
3380 r8153b_u1u2en(tp, true);
3384 static void r8153_teredo_off(struct r8152 *tp)
3388 switch (tp->version) {
3396 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3397 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
3399 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3404 /* The bit 0 ~ 7 are relative with teredo settings. They are
3405 * W1C (write 1 to clear), so set all 1 to disable it.
3407 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
3414 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
3415 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
3416 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
3419 static void rtl_reset_bmu(struct r8152 *tp)
3423 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
3424 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
3425 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3426 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
3427 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3430 /* Clear the bp to stop the firmware before loading a new one */
3431 static void rtl_clear_bp(struct r8152 *tp, u16 type)
3433 switch (tp->version) {
3442 ocp_write_byte(tp, type, PLA_BP_EN, 0);
3447 if (type == MCU_TYPE_USB) {
3448 ocp_write_byte(tp, MCU_TYPE_USB, USB_BP2_EN, 0);
3450 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_8, 0);
3451 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_9, 0);
3452 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_10, 0);
3453 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_11, 0);
3454 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_12, 0);
3455 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_13, 0);
3456 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_14, 0);
3457 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_15, 0);
3459 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
3464 ocp_write_word(tp, type, PLA_BP_0, 0);
3465 ocp_write_word(tp, type, PLA_BP_1, 0);
3466 ocp_write_word(tp, type, PLA_BP_2, 0);
3467 ocp_write_word(tp, type, PLA_BP_3, 0);
3468 ocp_write_word(tp, type, PLA_BP_4, 0);
3469 ocp_write_word(tp, type, PLA_BP_5, 0);
3470 ocp_write_word(tp, type, PLA_BP_6, 0);
3471 ocp_write_word(tp, type, PLA_BP_7, 0);
3473 /* wait 3 ms to make sure the firmware is stopped */
3474 usleep_range(3000, 6000);
3475 ocp_write_word(tp, type, PLA_BP_BA, 0);
3478 static int r8153_patch_request(struct r8152 *tp, bool request)
3483 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
3485 data |= PATCH_REQUEST;
3487 data &= ~PATCH_REQUEST;
3488 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
3490 for (i = 0; request && i < 5000; i++) {
3491 usleep_range(1000, 2000);
3492 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)
3496 if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
3497 netif_err(tp, drv, tp->netdev, "patch request fail\n");
3498 r8153_patch_request(tp, false);
3505 static int r8153_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key)
3507 if (r8153_patch_request(tp, true)) {
3508 dev_err(&tp->intf->dev, "patch request fail\n");
3512 sram_write(tp, key_addr, patch_key);
3513 sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);
3518 static int r8153_post_ram_code(struct r8152 *tp, u16 key_addr)
3522 sram_write(tp, 0x0000, 0x0000);
3524 data = ocp_reg_read(tp, OCP_PHY_LOCK);
3525 data &= ~PATCH_LOCK;
3526 ocp_reg_write(tp, OCP_PHY_LOCK, data);
3528 sram_write(tp, key_addr, 0x0000);
3530 r8153_patch_request(tp, false);
3532 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base);
3537 static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)
3540 u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start;
3543 switch (tp->version) {
3549 patch_en_addr = 0xa01a;
3557 fw_offset = __le16_to_cpu(phy->fw_offset);
3558 if (fw_offset < sizeof(*phy)) {
3559 dev_err(&tp->intf->dev, "fw_offset too small\n");
3563 length = __le32_to_cpu(phy->blk_hdr.length);
3564 if (length < fw_offset) {
3565 dev_err(&tp->intf->dev, "invalid fw_offset\n");
3569 length -= __le16_to_cpu(phy->fw_offset);
3570 if (!length || (length & 1)) {
3571 dev_err(&tp->intf->dev, "invalid block length\n");
3575 if (__le16_to_cpu(phy->fw_reg) != fw_reg) {
3576 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
3580 if (__le16_to_cpu(phy->ba_reg) != ba_reg) {
3581 dev_err(&tp->intf->dev, "invalid base address register\n");
3585 if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) {
3586 dev_err(&tp->intf->dev,
3587 "invalid patch mode enabled register\n");
3591 if (__le16_to_cpu(phy->mode_reg) != mode_reg) {
3592 dev_err(&tp->intf->dev,
3593 "invalid register to switch the mode\n");
3597 if (__le16_to_cpu(phy->bp_start) != bp_start) {
3598 dev_err(&tp->intf->dev,
3599 "invalid start register of break point\n");
3603 if (__le16_to_cpu(phy->bp_num) > 4) {
3604 dev_err(&tp->intf->dev, "invalid break point number\n");
3613 static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)
3615 u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;
3620 type = __le32_to_cpu(mac->blk_hdr.type);
3621 if (type == RTL_FW_PLA) {
3622 switch (tp->version) {
3627 bp_ba_addr = PLA_BP_BA;
3629 bp_start = PLA_BP_0;
3639 bp_ba_addr = PLA_BP_BA;
3640 bp_en_addr = PLA_BP_EN;
3641 bp_start = PLA_BP_0;
3647 } else if (type == RTL_FW_USB) {
3648 switch (tp->version) {
3654 bp_ba_addr = USB_BP_BA;
3655 bp_en_addr = USB_BP_EN;
3656 bp_start = USB_BP_0;
3662 bp_ba_addr = USB_BP_BA;
3663 bp_en_addr = USB_BP2_EN;
3664 bp_start = USB_BP_0;
3677 fw_offset = __le16_to_cpu(mac->fw_offset);
3678 if (fw_offset < sizeof(*mac)) {
3679 dev_err(&tp->intf->dev, "fw_offset too small\n");
3683 length = __le32_to_cpu(mac->blk_hdr.length);
3684 if (length < fw_offset) {
3685 dev_err(&tp->intf->dev, "invalid fw_offset\n");
3689 length -= fw_offset;
3690 if (length < 4 || (length & 3)) {
3691 dev_err(&tp->intf->dev, "invalid block length\n");
3695 if (__le16_to_cpu(mac->fw_reg) != fw_reg) {
3696 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
3700 if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {
3701 dev_err(&tp->intf->dev, "invalid base address register\n");
3705 if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {
3706 dev_err(&tp->intf->dev, "invalid enabled mask register\n");
3710 if (__le16_to_cpu(mac->bp_start) != bp_start) {
3711 dev_err(&tp->intf->dev,
3712 "invalid start register of break point\n");
3716 if (__le16_to_cpu(mac->bp_num) > max_bp) {
3717 dev_err(&tp->intf->dev, "invalid break point number\n");
3721 for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {
3723 dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);
3733 /* Verify the checksum for the firmware file. It is calculated from the version
3734 * field to the end of the file. Compare the result with the checksum field to
3735 * make sure the file is correct.
3737 static long rtl8152_fw_verify_checksum(struct r8152 *tp,
3738 struct fw_header *fw_hdr, size_t size)
3740 unsigned char checksum[sizeof(fw_hdr->checksum)];
3741 struct crypto_shash *alg;
3742 struct shash_desc *sdesc;
3746 alg = crypto_alloc_shash("sha256", 0, 0);
3752 if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) {
3754 dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n",
3755 crypto_shash_digestsize(alg));
3759 len = sizeof(*sdesc) + crypto_shash_descsize(alg);
3760 sdesc = kmalloc(len, GFP_KERNEL);
3767 len = size - sizeof(fw_hdr->checksum);
3768 rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum);
3773 if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) {
3774 dev_err(&tp->intf->dev, "checksum fail\n");
3779 crypto_free_shash(alg);
3784 static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)
3786 const struct firmware *fw = rtl_fw->fw;
3787 struct fw_header *fw_hdr = (struct fw_header *)fw->data;
3788 struct fw_mac *pla = NULL, *usb = NULL;
3789 struct fw_phy_patch_key *start = NULL;
3790 struct fw_phy_nc *phy_nc = NULL;
3791 struct fw_block *stop = NULL;
3795 if (fw->size < sizeof(*fw_hdr)) {
3796 dev_err(&tp->intf->dev, "file too small\n");
3800 ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size);
3806 for (i = sizeof(*fw_hdr); i < fw->size;) {
3807 struct fw_block *block = (struct fw_block *)&fw->data[i];
3810 if ((i + sizeof(*block)) > fw->size)
3813 type = __le32_to_cpu(block->type);
3816 if (__le32_to_cpu(block->length) != sizeof(*block))
3821 dev_err(&tp->intf->dev,
3822 "multiple PLA firmware encountered");
3826 pla = (struct fw_mac *)block;
3827 if (!rtl8152_is_fw_mac_ok(tp, pla)) {
3828 dev_err(&tp->intf->dev,
3829 "check PLA firmware failed\n");
3835 dev_err(&tp->intf->dev,
3836 "multiple USB firmware encountered");
3840 usb = (struct fw_mac *)block;
3841 if (!rtl8152_is_fw_mac_ok(tp, usb)) {
3842 dev_err(&tp->intf->dev,
3843 "check USB firmware failed\n");
3847 case RTL_FW_PHY_START:
3848 if (start || phy_nc || stop) {
3849 dev_err(&tp->intf->dev,
3850 "check PHY_START fail\n");
3854 if (__le32_to_cpu(block->length) != sizeof(*start)) {
3855 dev_err(&tp->intf->dev,
3856 "Invalid length for PHY_START\n");
3860 start = (struct fw_phy_patch_key *)block;
3862 case RTL_FW_PHY_STOP:
3863 if (stop || !start) {
3864 dev_err(&tp->intf->dev,
3865 "Check PHY_STOP fail\n");
3869 if (__le32_to_cpu(block->length) != sizeof(*block)) {
3870 dev_err(&tp->intf->dev,
3871 "Invalid length for PHY_STOP\n");
3878 if (!start || stop) {
3879 dev_err(&tp->intf->dev,
3880 "check PHY_NC fail\n");
3885 dev_err(&tp->intf->dev,
3886 "multiple PHY NC encountered\n");
3890 phy_nc = (struct fw_phy_nc *)block;
3891 if (!rtl8152_is_fw_phy_nc_ok(tp, phy_nc)) {
3892 dev_err(&tp->intf->dev,
3893 "check PHY NC firmware failed\n");
3899 dev_warn(&tp->intf->dev, "Unknown type %u is found\n",
3905 i += ALIGN(__le32_to_cpu(block->length), 8);
3909 if ((phy_nc || start) && !stop) {
3910 dev_err(&tp->intf->dev, "without PHY_STOP\n");
3919 static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)
3921 u16 mode_reg, bp_index;
3925 mode_reg = __le16_to_cpu(phy->mode_reg);
3926 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre));
3927 sram_write(tp, __le16_to_cpu(phy->ba_reg),
3928 __le16_to_cpu(phy->ba_data));
3930 length = __le32_to_cpu(phy->blk_hdr.length);
3931 length -= __le16_to_cpu(phy->fw_offset);
3933 data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
3935 ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
3936 for (i = 0; i < num; i++)
3937 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
3939 sram_write(tp, __le16_to_cpu(phy->patch_en_addr),
3940 __le16_to_cpu(phy->patch_en_value));
3942 bp_index = __le16_to_cpu(phy->bp_start);
3943 num = __le16_to_cpu(phy->bp_num);
3944 for (i = 0; i < num; i++) {
3945 sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i]));
3949 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post));
3951 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
3954 static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
3956 u16 bp_en_addr, bp_index, type, bp_num, fw_ver_reg;
3961 switch (__le32_to_cpu(mac->blk_hdr.type)) {
3963 type = MCU_TYPE_PLA;
3966 type = MCU_TYPE_USB;
3972 rtl_clear_bp(tp, type);
3974 /* Enable backup/restore of MACDBG. This is required after clearing PLA
3975 * break points and before applying the PLA firmware.
3977 if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&
3978 !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {
3979 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);
3980 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);
3983 length = __le32_to_cpu(mac->blk_hdr.length);
3984 length -= __le16_to_cpu(mac->fw_offset);
3987 data += __le16_to_cpu(mac->fw_offset);
3989 generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data,
3992 ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
3993 __le16_to_cpu(mac->bp_ba_value));
3995 bp_index = __le16_to_cpu(mac->bp_start);
3996 bp_num = __le16_to_cpu(mac->bp_num);
3997 for (i = 0; i < bp_num; i++) {
3998 ocp_write_word(tp, type, bp_index, __le16_to_cpu(mac->bp[i]));
4002 bp_en_addr = __le16_to_cpu(mac->bp_en_addr);
4004 ocp_write_word(tp, type, bp_en_addr,
4005 __le16_to_cpu(mac->bp_en_value));
4007 fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);
4009 ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg,
4012 dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);
4015 static void rtl8152_apply_firmware(struct r8152 *tp)
4017 struct rtl_fw *rtl_fw = &tp->rtl_fw;
4018 const struct firmware *fw;
4019 struct fw_header *fw_hdr;
4020 struct fw_phy_patch_key *key;
4024 if (IS_ERR_OR_NULL(rtl_fw->fw))
4028 fw_hdr = (struct fw_header *)fw->data;
4033 for (i = offsetof(struct fw_header, blocks); i < fw->size;) {
4034 struct fw_block *block = (struct fw_block *)&fw->data[i];
4036 switch (__le32_to_cpu(block->type)) {
4041 rtl8152_fw_mac_apply(tp, (struct fw_mac *)block);
4043 case RTL_FW_PHY_START:
4044 key = (struct fw_phy_patch_key *)block;
4045 key_addr = __le16_to_cpu(key->key_reg);
4046 r8153_pre_ram_code(tp, key_addr,
4047 __le16_to_cpu(key->key_data));
4049 case RTL_FW_PHY_STOP:
4051 r8153_post_ram_code(tp, key_addr);
4054 rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block);
4060 i += ALIGN(__le32_to_cpu(block->length), 8);
4064 if (rtl_fw->post_fw)
4065 rtl_fw->post_fw(tp);
4067 strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE);
4068 dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);
4071 static void rtl8152_release_firmware(struct r8152 *tp)
4073 struct rtl_fw *rtl_fw = &tp->rtl_fw;
4075 if (!IS_ERR_OR_NULL(rtl_fw->fw)) {
4076 release_firmware(rtl_fw->fw);
4081 static int rtl8152_request_firmware(struct r8152 *tp)
4083 struct rtl_fw *rtl_fw = &tp->rtl_fw;
4086 if (rtl_fw->fw || !rtl_fw->fw_name) {
4087 dev_info(&tp->intf->dev, "skip request firmware\n");
4092 rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev);
4096 rc = rtl8152_check_firmware(tp, rtl_fw);
4098 release_firmware(rtl_fw->fw);
4102 rtl_fw->fw = ERR_PTR(rc);
4104 dev_warn(&tp->intf->dev,
4105 "unable to load firmware patch %s (%ld)\n",
4106 rtl_fw->fw_name, rc);
4112 static void r8152_aldps_en(struct r8152 *tp, bool enable)
4115 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
4116 LINKENA | DIS_SDSAVE);
4118 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
4124 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
4126 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
4127 ocp_reg_write(tp, OCP_EEE_DATA, reg);
4128 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
4131 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
4135 r8152_mmd_indirect(tp, dev, reg);
4136 data = ocp_reg_read(tp, OCP_EEE_DATA);
4137 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
4142 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
4144 r8152_mmd_indirect(tp, dev, reg);
4145 ocp_reg_write(tp, OCP_EEE_DATA, data);
4146 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
4149 static void r8152_eee_en(struct r8152 *tp, bool enable)
4151 u16 config1, config2, config3;
4154 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4155 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
4156 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
4157 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
4160 ocp_data |= EEE_RX_EN | EEE_TX_EN;
4161 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
4162 config1 |= sd_rise_time(1);
4163 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
4164 config3 |= fast_snr(42);
4166 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
4167 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
4169 config1 |= sd_rise_time(7);
4170 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
4171 config3 |= fast_snr(511);
4174 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
4175 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
4176 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
4177 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
4180 static void r8153_eee_en(struct r8152 *tp, bool enable)
4185 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4186 config = ocp_reg_read(tp, OCP_EEE_CFG);
4189 ocp_data |= EEE_RX_EN | EEE_TX_EN;
4192 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
4193 config &= ~EEE10_EN;
4196 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
4197 ocp_reg_write(tp, OCP_EEE_CFG, config);
4199 tp->ups_info.eee = enable;
4202 static void rtl_eee_enable(struct r8152 *tp, bool enable)
4204 switch (tp->version) {
4209 r8152_eee_en(tp, true);
4210 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
4213 r8152_eee_en(tp, false);
4214 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
4224 r8153_eee_en(tp, true);
4225 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
4227 r8153_eee_en(tp, false);
4228 ocp_reg_write(tp, OCP_EEE_ADV, 0);
4236 static void r8152b_enable_fc(struct r8152 *tp)
4240 anar = r8152_mdio_read(tp, MII_ADVERTISE);
4241 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4242 r8152_mdio_write(tp, MII_ADVERTISE, anar);
4244 tp->ups_info.flow_control = true;
4247 static void rtl8152_disable(struct r8152 *tp)
4249 r8152_aldps_en(tp, false);
4251 r8152_aldps_en(tp, true);
4254 static void r8152b_hw_phy_cfg(struct r8152 *tp)
4256 rtl8152_apply_firmware(tp);
4257 rtl_eee_enable(tp, tp->eee_en);
4258 r8152_aldps_en(tp, true);
4259 r8152b_enable_fc(tp);
4261 set_bit(PHY_RESET, &tp->flags);
4264 static void wait_oob_link_list_ready(struct r8152 *tp)
4269 for (i = 0; i < 1000; i++) {
4270 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4271 if (ocp_data & LINK_LIST_READY)
4273 usleep_range(1000, 2000);
4277 static void r8152b_exit_oob(struct r8152 *tp)
4281 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4282 ocp_data &= ~RCR_ACPT_ALL;
4283 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4285 rxdy_gated_en(tp, true);
4286 r8153_teredo_off(tp);
4287 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
4288 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
4290 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4291 ocp_data &= ~NOW_IS_OOB;
4292 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4294 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4295 ocp_data &= ~MCU_BORW_EN;
4296 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4298 wait_oob_link_list_ready(tp);
4300 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4301 ocp_data |= RE_INIT_LL;
4302 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4304 wait_oob_link_list_ready(tp);
4306 rtl8152_nic_reset(tp);
4308 /* rx share fifo credit full threshold */
4309 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
4311 if (tp->udev->speed == USB_SPEED_FULL ||
4312 tp->udev->speed == USB_SPEED_LOW) {
4313 /* rx share fifo credit near full threshold */
4314 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
4316 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
4319 /* rx share fifo credit near full threshold */
4320 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
4322 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
4326 /* TX share fifo free credit full threshold */
4327 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
4329 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
4330 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
4331 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
4332 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
4334 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
4336 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
4338 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
4339 ocp_data |= TCR0_AUTO_FIFO;
4340 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
4343 static void r8152b_enter_oob(struct r8152 *tp)
4347 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4348 ocp_data &= ~NOW_IS_OOB;
4349 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4351 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
4352 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
4353 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
4357 wait_oob_link_list_ready(tp);
4359 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4360 ocp_data |= RE_INIT_LL;
4361 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4363 wait_oob_link_list_ready(tp);
4365 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
4367 rtl_rx_vlan_en(tp, true);
4369 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
4370 ocp_data |= ALDPS_PROXY_MODE;
4371 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
4373 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4374 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
4375 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4377 rxdy_gated_en(tp, false);
4379 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4380 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
4381 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4384 static int r8153_pre_firmware_1(struct r8152 *tp)
4388 /* Wait till the WTD timer is ready. It would take at most 104 ms. */
4389 for (i = 0; i < 104; i++) {
4390 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);
4392 if (!(ocp_data & WTD1_EN))
4394 usleep_range(1000, 2000);
4400 static int r8153_post_firmware_1(struct r8152 *tp)
4402 /* set USB_BP_4 to support USB_SPEED_SUPER only */
4403 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
4404 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);
4406 /* reset UPHY timer to 36 ms */
4407 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
4412 static int r8153_pre_firmware_2(struct r8152 *tp)
4416 r8153_pre_firmware_1(tp);
4418 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
4419 ocp_data &= ~FW_FIX_SUSPEND;
4420 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
4425 static int r8153_post_firmware_2(struct r8152 *tp)
4429 /* enable bp0 if support USB_SPEED_SUPER only */
4430 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
4431 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
4433 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
4436 /* reset UPHY timer to 36 ms */
4437 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
4439 /* enable U3P3 check, set the counter to 4 */
4440 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
4442 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
4443 ocp_data |= FW_FIX_SUSPEND;
4444 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
4446 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4447 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4448 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4453 static int r8153_post_firmware_3(struct r8152 *tp)
4457 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4458 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4459 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4461 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
4462 ocp_data |= FW_IP_RESET_EN;
4463 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
4468 static int r8153b_pre_firmware_1(struct r8152 *tp)
4470 /* enable fc timer and set timer to 1 second. */
4471 ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
4472 CTRL_TIMER_EN | (1000 / 8));
4477 static int r8153b_post_firmware_1(struct r8152 *tp)
4481 /* enable bp0 for RTL8153-BND */
4482 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
4483 if (ocp_data & BND_MASK) {
4484 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
4486 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
4489 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
4490 ocp_data |= FLOW_CTRL_PATCH_OPT;
4491 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
4493 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
4494 ocp_data |= FC_PATCH_TASK;
4495 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
4497 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
4498 ocp_data |= FW_IP_RESET_EN;
4499 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
4504 static void r8153_aldps_en(struct r8152 *tp, bool enable)
4508 data = ocp_reg_read(tp, OCP_POWER_CFG);
4511 ocp_reg_write(tp, OCP_POWER_CFG, data);
4516 ocp_reg_write(tp, OCP_POWER_CFG, data);
4517 for (i = 0; i < 20; i++) {
4518 usleep_range(1000, 2000);
4519 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
4524 tp->ups_info.aldps = enable;
4527 static void r8153_hw_phy_cfg(struct r8152 *tp)
4532 /* disable ALDPS before updating the PHY parameters */
4533 r8153_aldps_en(tp, false);
4535 /* disable EEE before updating the PHY parameters */
4536 rtl_eee_enable(tp, false);
4538 rtl8152_apply_firmware(tp);
4540 if (tp->version == RTL_VER_03) {
4541 data = ocp_reg_read(tp, OCP_EEE_CFG);
4542 data &= ~CTAP_SHORT_EN;
4543 ocp_reg_write(tp, OCP_EEE_CFG, data);
4546 data = ocp_reg_read(tp, OCP_POWER_CFG);
4547 data |= EEE_CLKDIV_EN;
4548 ocp_reg_write(tp, OCP_POWER_CFG, data);
4550 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
4551 data |= EN_10M_BGOFF;
4552 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
4553 data = ocp_reg_read(tp, OCP_POWER_CFG);
4554 data |= EN_10M_PLLOFF;
4555 ocp_reg_write(tp, OCP_POWER_CFG, data);
4556 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
4558 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4559 ocp_data |= PFM_PWM_SWITCH;
4560 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4562 /* Enable LPF corner auto tune */
4563 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
4565 /* Adjust 10M Amplitude */
4566 sram_write(tp, SRAM_10M_AMP1, 0x00af);
4567 sram_write(tp, SRAM_10M_AMP2, 0x0208);
4570 rtl_eee_enable(tp, true);
4572 r8153_aldps_en(tp, true);
4573 r8152b_enable_fc(tp);
4575 switch (tp->version) {
4582 r8153_u2p3en(tp, true);
4586 set_bit(PHY_RESET, &tp->flags);
4589 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
4593 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
4594 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
4595 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
4596 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
4601 static void r8153b_hw_phy_cfg(struct r8152 *tp)
4606 /* disable ALDPS before updating the PHY parameters */
4607 r8153_aldps_en(tp, false);
4609 /* disable EEE before updating the PHY parameters */
4610 rtl_eee_enable(tp, false);
4612 rtl8152_apply_firmware(tp);
4614 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
4616 data = sram_read(tp, SRAM_GREEN_CFG);
4618 sram_write(tp, SRAM_GREEN_CFG, data);
4619 data = ocp_reg_read(tp, OCP_NCTL_CFG);
4620 data |= PGA_RETURN_EN;
4621 ocp_reg_write(tp, OCP_NCTL_CFG, data);
4623 /* ADC Bias Calibration:
4624 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
4625 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
4628 ocp_data = r8152_efuse_read(tp, 0x7d);
4629 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
4631 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
4633 /* ups mode tx-link-pulse timing adjustment:
4634 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
4635 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
4637 ocp_data = ocp_reg_read(tp, 0xc426);
4640 u32 swr_cnt_1ms_ini;
4642 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
4643 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
4644 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
4645 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
4648 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4649 ocp_data |= PFM_PWM_SWITCH;
4650 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4653 if (!r8153_patch_request(tp, true)) {
4654 data = ocp_reg_read(tp, OCP_POWER_CFG);
4655 data |= EEE_CLKDIV_EN;
4656 ocp_reg_write(tp, OCP_POWER_CFG, data);
4657 tp->ups_info.eee_ckdiv = true;
4659 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
4660 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
4661 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
4662 tp->ups_info.eee_cmod_lv = true;
4663 tp->ups_info._10m_ckdiv = true;
4664 tp->ups_info.eee_plloff_giga = true;
4666 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
4667 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
4668 tp->ups_info._250m_ckdiv = true;
4670 r8153_patch_request(tp, false);
4674 rtl_eee_enable(tp, true);
4676 r8153_aldps_en(tp, true);
4677 r8152b_enable_fc(tp);
4678 r8153_u2p3en(tp, true);
4680 set_bit(PHY_RESET, &tp->flags);
4683 static void r8153_first_init(struct r8152 *tp)
4687 r8153_mac_clk_spd(tp, false);
4688 rxdy_gated_en(tp, true);
4689 r8153_teredo_off(tp);
4691 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4692 ocp_data &= ~RCR_ACPT_ALL;
4693 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4695 rtl8152_nic_reset(tp);
4698 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4699 ocp_data &= ~NOW_IS_OOB;
4700 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4702 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4703 ocp_data &= ~MCU_BORW_EN;
4704 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4706 wait_oob_link_list_ready(tp);
4708 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4709 ocp_data |= RE_INIT_LL;
4710 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4712 wait_oob_link_list_ready(tp);
4714 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
4716 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4717 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
4718 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
4720 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
4721 ocp_data |= TCR0_AUTO_FIFO;
4722 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
4724 rtl8152_nic_reset(tp);
4726 /* rx share fifo credit full threshold */
4727 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
4728 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
4729 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
4730 /* TX share fifo free credit full threshold */
4731 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
4734 static void r8153_enter_oob(struct r8152 *tp)
4738 r8153_mac_clk_spd(tp, true);
4740 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4741 ocp_data &= ~NOW_IS_OOB;
4742 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4747 wait_oob_link_list_ready(tp);
4749 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4750 ocp_data |= RE_INIT_LL;
4751 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4753 wait_oob_link_list_ready(tp);
4755 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4756 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
4758 switch (tp->version) {
4763 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
4764 ocp_data &= ~TEREDO_WAKE_MASK;
4765 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
4770 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
4771 * type. Set it to zero. bits[7:0] are the W1C bits about
4772 * the events. Set them to all 1 to clear them.
4774 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
4781 rtl_rx_vlan_en(tp, true);
4783 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
4784 ocp_data |= ALDPS_PROXY_MODE;
4785 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
4787 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4788 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
4789 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4791 rxdy_gated_en(tp, false);
4793 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4794 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
4795 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4798 static void rtl8153_disable(struct r8152 *tp)
4800 r8153_aldps_en(tp, false);
4803 r8153_aldps_en(tp, true);
4806 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
4812 if (autoneg == AUTONEG_DISABLE) {
4813 if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
4818 bmcr = BMCR_SPEED10;
4819 if (duplex == DUPLEX_FULL) {
4820 bmcr |= BMCR_FULLDPLX;
4821 tp->ups_info.speed_duplex = FORCE_10M_FULL;
4823 tp->ups_info.speed_duplex = FORCE_10M_HALF;
4827 bmcr = BMCR_SPEED100;
4828 if (duplex == DUPLEX_FULL) {
4829 bmcr |= BMCR_FULLDPLX;
4830 tp->ups_info.speed_duplex = FORCE_100M_FULL;
4832 tp->ups_info.speed_duplex = FORCE_100M_HALF;
4836 if (tp->mii.supports_gmii) {
4837 bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
4838 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
4847 if (duplex == DUPLEX_FULL)
4848 tp->mii.full_duplex = 1;
4850 tp->mii.full_duplex = 0;
4852 tp->mii.force_media = 1;
4857 support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
4858 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
4860 if (tp->mii.supports_gmii)
4861 support |= RTL_ADVERTISED_1000_FULL;
4863 if (!(advertising & support))
4866 anar = r8152_mdio_read(tp, MII_ADVERTISE);
4867 tmp1 = anar & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
4868 ADVERTISE_100HALF | ADVERTISE_100FULL);
4869 if (advertising & RTL_ADVERTISED_10_HALF) {
4870 tmp1 |= ADVERTISE_10HALF;
4871 tp->ups_info.speed_duplex = NWAY_10M_HALF;
4873 if (advertising & RTL_ADVERTISED_10_FULL) {
4874 tmp1 |= ADVERTISE_10FULL;
4875 tp->ups_info.speed_duplex = NWAY_10M_FULL;
4878 if (advertising & RTL_ADVERTISED_100_HALF) {
4879 tmp1 |= ADVERTISE_100HALF;
4880 tp->ups_info.speed_duplex = NWAY_100M_HALF;
4882 if (advertising & RTL_ADVERTISED_100_FULL) {
4883 tmp1 |= ADVERTISE_100FULL;
4884 tp->ups_info.speed_duplex = NWAY_100M_FULL;
4888 r8152_mdio_write(tp, MII_ADVERTISE, tmp1);
4889 tp->mii.advertising = tmp1;
4892 if (tp->mii.supports_gmii) {
4895 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
4896 tmp1 = gbcr & ~(ADVERTISE_1000FULL |
4897 ADVERTISE_1000HALF);
4899 if (advertising & RTL_ADVERTISED_1000_FULL) {
4900 tmp1 |= ADVERTISE_1000FULL;
4901 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
4905 r8152_mdio_write(tp, MII_CTRL1000, tmp1);
4908 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
4910 tp->mii.force_media = 0;
4913 if (test_and_clear_bit(PHY_RESET, &tp->flags))
4916 r8152_mdio_write(tp, MII_BMCR, bmcr);
4918 if (bmcr & BMCR_RESET) {
4921 for (i = 0; i < 50; i++) {
4923 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
4932 static void rtl8152_up(struct r8152 *tp)
4934 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4937 r8152_aldps_en(tp, false);
4938 r8152b_exit_oob(tp);
4939 r8152_aldps_en(tp, true);
4942 static void rtl8152_down(struct r8152 *tp)
4944 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
4945 rtl_drop_queued_tx(tp);
4949 r8152_power_cut_en(tp, false);
4950 r8152_aldps_en(tp, false);
4951 r8152b_enter_oob(tp);
4952 r8152_aldps_en(tp, true);
4955 static void rtl8153_up(struct r8152 *tp)
4957 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4960 r8153_u1u2en(tp, false);
4961 r8153_u2p3en(tp, false);
4962 r8153_aldps_en(tp, false);
4963 r8153_first_init(tp);
4964 r8153_aldps_en(tp, true);
4966 switch (tp->version) {
4973 r8153_u2p3en(tp, true);
4977 r8153_u1u2en(tp, true);
4980 static void rtl8153_down(struct r8152 *tp)
4982 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
4983 rtl_drop_queued_tx(tp);
4987 r8153_u1u2en(tp, false);
4988 r8153_u2p3en(tp, false);
4989 r8153_power_cut_en(tp, false);
4990 r8153_aldps_en(tp, false);
4991 r8153_enter_oob(tp);
4992 r8153_aldps_en(tp, true);
4995 static void rtl8153b_up(struct r8152 *tp)
4997 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5000 r8153b_u1u2en(tp, false);
5001 r8153_u2p3en(tp, false);
5002 r8153_aldps_en(tp, false);
5004 r8153_first_init(tp);
5005 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
5007 r8153_aldps_en(tp, true);
5008 r8153_u2p3en(tp, true);
5009 r8153b_u1u2en(tp, true);
5012 static void rtl8153b_down(struct r8152 *tp)
5014 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
5015 rtl_drop_queued_tx(tp);
5019 r8153b_u1u2en(tp, false);
5020 r8153_u2p3en(tp, false);
5021 r8153b_power_cut_en(tp, false);
5022 r8153_aldps_en(tp, false);
5023 r8153_enter_oob(tp);
5024 r8153_aldps_en(tp, true);
5027 static bool rtl8152_in_nway(struct r8152 *tp)
5031 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
5032 tp->ocp_base = 0x2000;
5033 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
5034 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
5036 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
5037 if (nway_state & 0xc000)
5043 static bool rtl8153_in_nway(struct r8152 *tp)
5045 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
5047 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
5053 static void set_carrier(struct r8152 *tp)
5055 struct net_device *netdev = tp->netdev;
5056 struct napi_struct *napi = &tp->napi;
5059 speed = rtl8152_get_speed(tp);
5061 if (speed & LINK_STATUS) {
5062 if (!netif_carrier_ok(netdev)) {
5063 tp->rtl_ops.enable(tp);
5064 netif_stop_queue(netdev);
5066 netif_carrier_on(netdev);
5068 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
5069 _rtl8152_set_rx_mode(netdev);
5070 napi_enable(&tp->napi);
5071 netif_wake_queue(netdev);
5072 netif_info(tp, link, netdev, "carrier on\n");
5073 } else if (netif_queue_stopped(netdev) &&
5074 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
5075 netif_wake_queue(netdev);
5078 if (netif_carrier_ok(netdev)) {
5079 netif_carrier_off(netdev);
5080 tasklet_disable(&tp->tx_tl);
5082 tp->rtl_ops.disable(tp);
5084 tasklet_enable(&tp->tx_tl);
5085 netif_info(tp, link, netdev, "carrier off\n");
5090 static void rtl_work_func_t(struct work_struct *work)
5092 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
5094 /* If the device is unplugged or !netif_running(), the workqueue
5095 * doesn't need to wake the device, and could return directly.
5097 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
5100 if (usb_autopm_get_interface(tp->intf) < 0)
5103 if (!test_bit(WORK_ENABLE, &tp->flags))
5106 if (!mutex_trylock(&tp->control)) {
5107 schedule_delayed_work(&tp->schedule, 0);
5111 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
5114 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
5115 _rtl8152_set_rx_mode(tp->netdev);
5117 /* don't schedule tasket before linking */
5118 if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) &&
5119 netif_carrier_ok(tp->netdev))
5120 tasklet_schedule(&tp->tx_tl);
5122 mutex_unlock(&tp->control);
5125 usb_autopm_put_interface(tp->intf);
5128 static void rtl_hw_phy_work_func_t(struct work_struct *work)
5130 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
5132 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5135 if (usb_autopm_get_interface(tp->intf) < 0)
5138 mutex_lock(&tp->control);
5140 if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {
5141 tp->rtl_fw.retry = false;
5142 tp->rtl_fw.fw = NULL;
5144 /* Delay execution in case request_firmware() is not ready yet.
5146 queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10);
5150 tp->rtl_ops.hw_phy_cfg(tp);
5152 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex,
5156 mutex_unlock(&tp->control);
5158 usb_autopm_put_interface(tp->intf);
5161 #ifdef CONFIG_PM_SLEEP
5162 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
5165 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
5168 case PM_HIBERNATION_PREPARE:
5169 case PM_SUSPEND_PREPARE:
5170 usb_autopm_get_interface(tp->intf);
5173 case PM_POST_HIBERNATION:
5174 case PM_POST_SUSPEND:
5175 usb_autopm_put_interface(tp->intf);
5178 case PM_POST_RESTORE:
5179 case PM_RESTORE_PREPARE:
5188 static int rtl8152_open(struct net_device *netdev)
5190 struct r8152 *tp = netdev_priv(netdev);
5193 if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) {
5194 cancel_delayed_work_sync(&tp->hw_phy_work);
5195 rtl_hw_phy_work_func_t(&tp->hw_phy_work.work);
5198 res = alloc_all_mem(tp);
5202 res = usb_autopm_get_interface(tp->intf);
5206 mutex_lock(&tp->control);
5210 netif_carrier_off(netdev);
5211 netif_start_queue(netdev);
5212 set_bit(WORK_ENABLE, &tp->flags);
5214 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
5217 netif_device_detach(tp->netdev);
5218 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
5222 napi_enable(&tp->napi);
5223 tasklet_enable(&tp->tx_tl);
5225 mutex_unlock(&tp->control);
5227 usb_autopm_put_interface(tp->intf);
5228 #ifdef CONFIG_PM_SLEEP
5229 tp->pm_notifier.notifier_call = rtl_notifier;
5230 register_pm_notifier(&tp->pm_notifier);
5235 mutex_unlock(&tp->control);
5236 usb_autopm_put_interface(tp->intf);
5243 static int rtl8152_close(struct net_device *netdev)
5245 struct r8152 *tp = netdev_priv(netdev);
5248 #ifdef CONFIG_PM_SLEEP
5249 unregister_pm_notifier(&tp->pm_notifier);
5251 tasklet_disable(&tp->tx_tl);
5252 clear_bit(WORK_ENABLE, &tp->flags);
5253 usb_kill_urb(tp->intr_urb);
5254 cancel_delayed_work_sync(&tp->schedule);
5255 napi_disable(&tp->napi);
5256 netif_stop_queue(netdev);
5258 res = usb_autopm_get_interface(tp->intf);
5259 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
5260 rtl_drop_queued_tx(tp);
5263 mutex_lock(&tp->control);
5265 tp->rtl_ops.down(tp);
5267 mutex_unlock(&tp->control);
5269 usb_autopm_put_interface(tp->intf);
5277 static void rtl_tally_reset(struct r8152 *tp)
5281 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
5282 ocp_data |= TALLY_RESET;
5283 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
5286 static void r8152b_init(struct r8152 *tp)
5291 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5294 data = r8152_mdio_read(tp, MII_BMCR);
5295 if (data & BMCR_PDOWN) {
5296 data &= ~BMCR_PDOWN;
5297 r8152_mdio_write(tp, MII_BMCR, data);
5300 r8152_aldps_en(tp, false);
5302 if (tp->version == RTL_VER_01) {
5303 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
5304 ocp_data &= ~LED_MODE_MASK;
5305 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
5308 r8152_power_cut_en(tp, false);
5310 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5311 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
5312 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5313 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
5314 ocp_data &= ~MCU_CLK_RATIO_MASK;
5315 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
5316 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
5317 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
5318 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
5319 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
5321 rtl_tally_reset(tp);
5323 /* enable rx aggregation */
5324 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5325 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5326 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5329 static void r8153_init(struct r8152 *tp)
5335 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5338 r8153_u1u2en(tp, false);
5340 for (i = 0; i < 500; i++) {
5341 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
5347 data = r8153_phy_status(tp, 0);
5349 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
5350 tp->version == RTL_VER_05)
5351 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
5353 data = r8152_mdio_read(tp, MII_BMCR);
5354 if (data & BMCR_PDOWN) {
5355 data &= ~BMCR_PDOWN;
5356 r8152_mdio_write(tp, MII_BMCR, data);
5359 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
5361 r8153_u2p3en(tp, false);
5363 if (tp->version == RTL_VER_04) {
5364 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
5365 ocp_data &= ~pwd_dn_scale_mask;
5366 ocp_data |= pwd_dn_scale(96);
5367 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
5369 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5370 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5371 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5372 } else if (tp->version == RTL_VER_05) {
5373 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
5374 ocp_data &= ~ECM_ALDPS;
5375 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
5377 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
5378 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
5379 ocp_data &= ~DYNAMIC_BURST;
5381 ocp_data |= DYNAMIC_BURST;
5382 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
5383 } else if (tp->version == RTL_VER_06) {
5384 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
5385 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
5386 ocp_data &= ~DYNAMIC_BURST;
5388 ocp_data |= DYNAMIC_BURST;
5389 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
5392 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
5393 ocp_data |= EP4_FULL_FC;
5394 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
5396 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
5397 ocp_data &= ~TIMER11_EN;
5398 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
5400 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
5401 ocp_data &= ~LED_MODE_MASK;
5402 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
5404 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
5405 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
5406 ocp_data |= LPM_TIMER_500MS;
5408 ocp_data |= LPM_TIMER_500US;
5409 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
5411 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
5412 ocp_data &= ~SEN_VAL_MASK;
5413 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
5414 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
5416 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
5418 r8153_power_cut_en(tp, false);
5419 r8153_u1u2en(tp, true);
5420 r8153_mac_clk_spd(tp, false);
5421 usb_enable_lpm(tp->udev);
5423 /* rx aggregation */
5424 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5425 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5426 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
5427 ocp_data |= RX_AGG_DISABLE;
5429 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5431 rtl_tally_reset(tp);
5433 switch (tp->udev->speed) {
5434 case USB_SPEED_SUPER:
5435 case USB_SPEED_SUPER_PLUS:
5436 tp->coalesce = COALESCE_SUPER;
5438 case USB_SPEED_HIGH:
5439 tp->coalesce = COALESCE_HIGH;
5442 tp->coalesce = COALESCE_SLOW;
5447 static void r8153b_init(struct r8152 *tp)
5453 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5456 r8153b_u1u2en(tp, false);
5458 for (i = 0; i < 500; i++) {
5459 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
5465 data = r8153_phy_status(tp, 0);
5467 data = r8152_mdio_read(tp, MII_BMCR);
5468 if (data & BMCR_PDOWN) {
5469 data &= ~BMCR_PDOWN;
5470 r8152_mdio_write(tp, MII_BMCR, data);
5473 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
5475 r8153_u2p3en(tp, false);
5477 /* MSC timer = 0xfff * 8ms = 32760 ms */
5478 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
5480 /* U1/U2/L1 idle timer. 500 us */
5481 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
5483 r8153b_power_cut_en(tp, false);
5484 r8153b_ups_en(tp, false);
5485 r8153_queue_wake(tp, false);
5486 rtl_runtime_suspend_enable(tp, false);
5487 r8153b_u1u2en(tp, true);
5488 usb_enable_lpm(tp->udev);
5490 /* MAC clock speed down */
5491 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
5492 ocp_data |= MAC_CLK_SPDWN_EN;
5493 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
5495 set_bit(GREEN_ETHERNET, &tp->flags);
5497 /* rx aggregation */
5498 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5499 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5500 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5502 rtl_tally_reset(tp);
5504 tp->coalesce = 15000; /* 15 us */
5507 static int rtl8152_pre_reset(struct usb_interface *intf)
5509 struct r8152 *tp = usb_get_intfdata(intf);
5510 struct net_device *netdev;
5515 netdev = tp->netdev;
5516 if (!netif_running(netdev))
5519 netif_stop_queue(netdev);
5520 tasklet_disable(&tp->tx_tl);
5521 clear_bit(WORK_ENABLE, &tp->flags);
5522 usb_kill_urb(tp->intr_urb);
5523 cancel_delayed_work_sync(&tp->schedule);
5524 napi_disable(&tp->napi);
5525 if (netif_carrier_ok(netdev)) {
5526 mutex_lock(&tp->control);
5527 tp->rtl_ops.disable(tp);
5528 mutex_unlock(&tp->control);
5534 static int rtl8152_post_reset(struct usb_interface *intf)
5536 struct r8152 *tp = usb_get_intfdata(intf);
5537 struct net_device *netdev;
5543 /* reset the MAC adddress in case of policy change */
5544 if (determine_ethernet_addr(tp, &sa) >= 0) {
5546 dev_set_mac_address (tp->netdev, &sa, NULL);
5550 netdev = tp->netdev;
5551 if (!netif_running(netdev))
5554 set_bit(WORK_ENABLE, &tp->flags);
5555 if (netif_carrier_ok(netdev)) {
5556 mutex_lock(&tp->control);
5557 tp->rtl_ops.enable(tp);
5559 _rtl8152_set_rx_mode(netdev);
5560 mutex_unlock(&tp->control);
5563 napi_enable(&tp->napi);
5564 tasklet_enable(&tp->tx_tl);
5565 netif_wake_queue(netdev);
5566 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
5568 if (!list_empty(&tp->rx_done))
5569 napi_schedule(&tp->napi);
5574 static bool delay_autosuspend(struct r8152 *tp)
5576 bool sw_linking = !!netif_carrier_ok(tp->netdev);
5577 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
5579 /* This means a linking change occurs and the driver doesn't detect it,
5580 * yet. If the driver has disabled tx/rx and hw is linking on, the
5581 * device wouldn't wake up by receiving any packet.
5583 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
5586 /* If the linking down is occurred by nway, the device may miss the
5587 * linking change event. And it wouldn't wake when linking on.
5589 if (!sw_linking && tp->rtl_ops.in_nway(tp))
5591 else if (!skb_queue_empty(&tp->tx_queue))
5597 static int rtl8152_runtime_resume(struct r8152 *tp)
5599 struct net_device *netdev = tp->netdev;
5601 if (netif_running(netdev) && netdev->flags & IFF_UP) {
5602 struct napi_struct *napi = &tp->napi;
5604 tp->rtl_ops.autosuspend_en(tp, false);
5606 set_bit(WORK_ENABLE, &tp->flags);
5608 if (netif_carrier_ok(netdev)) {
5609 if (rtl8152_get_speed(tp) & LINK_STATUS) {
5612 netif_carrier_off(netdev);
5613 tp->rtl_ops.disable(tp);
5614 netif_info(tp, link, netdev, "linking down\n");
5619 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5620 smp_mb__after_atomic();
5622 if (!list_empty(&tp->rx_done))
5623 napi_schedule(&tp->napi);
5625 usb_submit_urb(tp->intr_urb, GFP_NOIO);
5627 if (netdev->flags & IFF_UP)
5628 tp->rtl_ops.autosuspend_en(tp, false);
5630 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5636 static int rtl8152_system_resume(struct r8152 *tp)
5638 struct net_device *netdev = tp->netdev;
5640 netif_device_attach(netdev);
5642 if (netif_running(netdev) && (netdev->flags & IFF_UP)) {
5644 netif_carrier_off(netdev);
5645 set_bit(WORK_ENABLE, &tp->flags);
5646 usb_submit_urb(tp->intr_urb, GFP_NOIO);
5652 static int rtl8152_runtime_suspend(struct r8152 *tp)
5654 struct net_device *netdev = tp->netdev;
5657 set_bit(SELECTIVE_SUSPEND, &tp->flags);
5658 smp_mb__after_atomic();
5660 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
5663 if (netif_carrier_ok(netdev)) {
5666 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5667 ocp_data = rcr & ~RCR_ACPT_ALL;
5668 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5669 rxdy_gated_en(tp, true);
5670 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
5672 if (!(ocp_data & RXFIFO_EMPTY)) {
5673 rxdy_gated_en(tp, false);
5674 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
5675 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5676 smp_mb__after_atomic();
5682 clear_bit(WORK_ENABLE, &tp->flags);
5683 usb_kill_urb(tp->intr_urb);
5685 tp->rtl_ops.autosuspend_en(tp, true);
5687 if (netif_carrier_ok(netdev)) {
5688 struct napi_struct *napi = &tp->napi;
5692 rxdy_gated_en(tp, false);
5693 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
5697 if (delay_autosuspend(tp)) {
5698 rtl8152_runtime_resume(tp);
5707 static int rtl8152_system_suspend(struct r8152 *tp)
5709 struct net_device *netdev = tp->netdev;
5711 netif_device_detach(netdev);
5713 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
5714 struct napi_struct *napi = &tp->napi;
5716 clear_bit(WORK_ENABLE, &tp->flags);
5717 usb_kill_urb(tp->intr_urb);
5718 tasklet_disable(&tp->tx_tl);
5720 cancel_delayed_work_sync(&tp->schedule);
5721 tp->rtl_ops.down(tp);
5723 tasklet_enable(&tp->tx_tl);
5729 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
5731 struct r8152 *tp = usb_get_intfdata(intf);
5734 mutex_lock(&tp->control);
5736 if (PMSG_IS_AUTO(message))
5737 ret = rtl8152_runtime_suspend(tp);
5739 ret = rtl8152_system_suspend(tp);
5741 mutex_unlock(&tp->control);
5746 static int rtl8152_resume(struct usb_interface *intf)
5748 struct r8152 *tp = usb_get_intfdata(intf);
5751 mutex_lock(&tp->control);
5753 if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
5754 ret = rtl8152_runtime_resume(tp);
5756 ret = rtl8152_system_resume(tp);
5758 mutex_unlock(&tp->control);
5763 static int rtl8152_reset_resume(struct usb_interface *intf)
5765 struct r8152 *tp = usb_get_intfdata(intf);
5767 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5768 tp->rtl_ops.init(tp);
5769 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
5770 set_ethernet_addr(tp);
5771 return rtl8152_resume(intf);
5774 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5776 struct r8152 *tp = netdev_priv(dev);
5778 if (usb_autopm_get_interface(tp->intf) < 0)
5781 if (!rtl_can_wakeup(tp)) {
5785 mutex_lock(&tp->control);
5786 wol->supported = WAKE_ANY;
5787 wol->wolopts = __rtl_get_wol(tp);
5788 mutex_unlock(&tp->control);
5791 usb_autopm_put_interface(tp->intf);
5794 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5796 struct r8152 *tp = netdev_priv(dev);
5799 if (!rtl_can_wakeup(tp))
5802 if (wol->wolopts & ~WAKE_ANY)
5805 ret = usb_autopm_get_interface(tp->intf);
5809 mutex_lock(&tp->control);
5811 __rtl_set_wol(tp, wol->wolopts);
5812 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
5814 mutex_unlock(&tp->control);
5816 usb_autopm_put_interface(tp->intf);
5822 static u32 rtl8152_get_msglevel(struct net_device *dev)
5824 struct r8152 *tp = netdev_priv(dev);
5826 return tp->msg_enable;
5829 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
5831 struct r8152 *tp = netdev_priv(dev);
5833 tp->msg_enable = value;
5836 static void rtl8152_get_drvinfo(struct net_device *netdev,
5837 struct ethtool_drvinfo *info)
5839 struct r8152 *tp = netdev_priv(netdev);
5841 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
5842 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
5843 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
5844 if (!IS_ERR_OR_NULL(tp->rtl_fw.fw))
5845 strlcpy(info->fw_version, tp->rtl_fw.version,
5846 sizeof(info->fw_version));
5850 int rtl8152_get_link_ksettings(struct net_device *netdev,
5851 struct ethtool_link_ksettings *cmd)
5853 struct r8152 *tp = netdev_priv(netdev);
5856 if (!tp->mii.mdio_read)
5859 ret = usb_autopm_get_interface(tp->intf);
5863 mutex_lock(&tp->control);
5865 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
5867 mutex_unlock(&tp->control);
5869 usb_autopm_put_interface(tp->intf);
5875 static int rtl8152_set_link_ksettings(struct net_device *dev,
5876 const struct ethtool_link_ksettings *cmd)
5878 struct r8152 *tp = netdev_priv(dev);
5879 u32 advertising = 0;
5882 ret = usb_autopm_get_interface(tp->intf);
5886 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
5887 cmd->link_modes.advertising))
5888 advertising |= RTL_ADVERTISED_10_HALF;
5890 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
5891 cmd->link_modes.advertising))
5892 advertising |= RTL_ADVERTISED_10_FULL;
5894 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
5895 cmd->link_modes.advertising))
5896 advertising |= RTL_ADVERTISED_100_HALF;
5898 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
5899 cmd->link_modes.advertising))
5900 advertising |= RTL_ADVERTISED_100_FULL;
5902 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
5903 cmd->link_modes.advertising))
5904 advertising |= RTL_ADVERTISED_1000_HALF;
5906 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
5907 cmd->link_modes.advertising))
5908 advertising |= RTL_ADVERTISED_1000_FULL;
5910 mutex_lock(&tp->control);
5912 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
5913 cmd->base.duplex, advertising);
5915 tp->autoneg = cmd->base.autoneg;
5916 tp->speed = cmd->base.speed;
5917 tp->duplex = cmd->base.duplex;
5918 tp->advertising = advertising;
5921 mutex_unlock(&tp->control);
5923 usb_autopm_put_interface(tp->intf);
5929 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
5936 "tx_single_collisions",
5937 "tx_multi_collisions",
5945 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
5949 return ARRAY_SIZE(rtl8152_gstrings);
5955 static void rtl8152_get_ethtool_stats(struct net_device *dev,
5956 struct ethtool_stats *stats, u64 *data)
5958 struct r8152 *tp = netdev_priv(dev);
5959 struct tally_counter tally;
5961 if (usb_autopm_get_interface(tp->intf) < 0)
5964 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
5966 usb_autopm_put_interface(tp->intf);
5968 data[0] = le64_to_cpu(tally.tx_packets);
5969 data[1] = le64_to_cpu(tally.rx_packets);
5970 data[2] = le64_to_cpu(tally.tx_errors);
5971 data[3] = le32_to_cpu(tally.rx_errors);
5972 data[4] = le16_to_cpu(tally.rx_missed);
5973 data[5] = le16_to_cpu(tally.align_errors);
5974 data[6] = le32_to_cpu(tally.tx_one_collision);
5975 data[7] = le32_to_cpu(tally.tx_multi_collision);
5976 data[8] = le64_to_cpu(tally.rx_unicast);
5977 data[9] = le64_to_cpu(tally.rx_broadcast);
5978 data[10] = le32_to_cpu(tally.rx_multicast);
5979 data[11] = le16_to_cpu(tally.tx_aborted);
5980 data[12] = le16_to_cpu(tally.tx_underrun);
5983 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
5985 switch (stringset) {
5987 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
5992 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
5994 u32 lp, adv, supported = 0;
5997 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
5998 supported = mmd_eee_cap_to_ethtool_sup_t(val);
6000 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
6001 adv = mmd_eee_adv_to_ethtool_adv_t(val);
6003 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
6004 lp = mmd_eee_adv_to_ethtool_adv_t(val);
6006 eee->eee_enabled = tp->eee_en;
6007 eee->eee_active = !!(supported & adv & lp);
6008 eee->supported = supported;
6009 eee->advertised = tp->eee_adv;
6010 eee->lp_advertised = lp;
6015 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
6017 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
6019 tp->eee_en = eee->eee_enabled;
6022 rtl_eee_enable(tp, tp->eee_en);
6027 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
6029 u32 lp, adv, supported = 0;
6032 val = ocp_reg_read(tp, OCP_EEE_ABLE);
6033 supported = mmd_eee_cap_to_ethtool_sup_t(val);
6035 val = ocp_reg_read(tp, OCP_EEE_ADV);
6036 adv = mmd_eee_adv_to_ethtool_adv_t(val);
6038 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
6039 lp = mmd_eee_adv_to_ethtool_adv_t(val);
6041 eee->eee_enabled = tp->eee_en;
6042 eee->eee_active = !!(supported & adv & lp);
6043 eee->supported = supported;
6044 eee->advertised = tp->eee_adv;
6045 eee->lp_advertised = lp;
6051 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
6053 struct r8152 *tp = netdev_priv(net);
6056 ret = usb_autopm_get_interface(tp->intf);
6060 mutex_lock(&tp->control);
6062 ret = tp->rtl_ops.eee_get(tp, edata);
6064 mutex_unlock(&tp->control);
6066 usb_autopm_put_interface(tp->intf);
6073 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
6075 struct r8152 *tp = netdev_priv(net);
6078 ret = usb_autopm_get_interface(tp->intf);
6082 mutex_lock(&tp->control);
6084 ret = tp->rtl_ops.eee_set(tp, edata);
6086 ret = mii_nway_restart(&tp->mii);
6088 mutex_unlock(&tp->control);
6090 usb_autopm_put_interface(tp->intf);
6096 static int rtl8152_nway_reset(struct net_device *dev)
6098 struct r8152 *tp = netdev_priv(dev);
6101 ret = usb_autopm_get_interface(tp->intf);
6105 mutex_lock(&tp->control);
6107 ret = mii_nway_restart(&tp->mii);
6109 mutex_unlock(&tp->control);
6111 usb_autopm_put_interface(tp->intf);
6117 static int rtl8152_get_coalesce(struct net_device *netdev,
6118 struct ethtool_coalesce *coalesce)
6120 struct r8152 *tp = netdev_priv(netdev);
6122 switch (tp->version) {
6131 coalesce->rx_coalesce_usecs = tp->coalesce;
6136 static int rtl8152_set_coalesce(struct net_device *netdev,
6137 struct ethtool_coalesce *coalesce)
6139 struct r8152 *tp = netdev_priv(netdev);
6142 switch (tp->version) {
6151 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
6154 ret = usb_autopm_get_interface(tp->intf);
6158 mutex_lock(&tp->control);
6160 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
6161 tp->coalesce = coalesce->rx_coalesce_usecs;
6163 if (netif_running(netdev) && netif_carrier_ok(netdev)) {
6164 netif_stop_queue(netdev);
6165 napi_disable(&tp->napi);
6166 tp->rtl_ops.disable(tp);
6167 tp->rtl_ops.enable(tp);
6169 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
6170 _rtl8152_set_rx_mode(netdev);
6171 napi_enable(&tp->napi);
6172 netif_wake_queue(netdev);
6176 mutex_unlock(&tp->control);
6178 usb_autopm_put_interface(tp->intf);
6183 static int rtl8152_get_tunable(struct net_device *netdev,
6184 const struct ethtool_tunable *tunable, void *d)
6186 struct r8152 *tp = netdev_priv(netdev);
6188 switch (tunable->id) {
6189 case ETHTOOL_RX_COPYBREAK:
6190 *(u32 *)d = tp->rx_copybreak;
6199 static int rtl8152_set_tunable(struct net_device *netdev,
6200 const struct ethtool_tunable *tunable,
6203 struct r8152 *tp = netdev_priv(netdev);
6206 switch (tunable->id) {
6207 case ETHTOOL_RX_COPYBREAK:
6209 if (val < ETH_ZLEN) {
6210 netif_err(tp, rx_err, netdev,
6211 "Invalid rx copy break value\n");
6215 if (tp->rx_copybreak != val) {
6216 if (netdev->flags & IFF_UP) {
6217 mutex_lock(&tp->control);
6218 napi_disable(&tp->napi);
6219 tp->rx_copybreak = val;
6220 napi_enable(&tp->napi);
6221 mutex_unlock(&tp->control);
6223 tp->rx_copybreak = val;
6234 static void rtl8152_get_ringparam(struct net_device *netdev,
6235 struct ethtool_ringparam *ring)
6237 struct r8152 *tp = netdev_priv(netdev);
6239 ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
6240 ring->rx_pending = tp->rx_pending;
6243 static int rtl8152_set_ringparam(struct net_device *netdev,
6244 struct ethtool_ringparam *ring)
6246 struct r8152 *tp = netdev_priv(netdev);
6248 if (ring->rx_pending < (RTL8152_MAX_RX * 2))
6251 if (tp->rx_pending != ring->rx_pending) {
6252 if (netdev->flags & IFF_UP) {
6253 mutex_lock(&tp->control);
6254 napi_disable(&tp->napi);
6255 tp->rx_pending = ring->rx_pending;
6256 napi_enable(&tp->napi);
6257 mutex_unlock(&tp->control);
6259 tp->rx_pending = ring->rx_pending;
6266 static const struct ethtool_ops ops = {
6267 .get_drvinfo = rtl8152_get_drvinfo,
6268 .get_link = ethtool_op_get_link,
6269 .nway_reset = rtl8152_nway_reset,
6270 .get_msglevel = rtl8152_get_msglevel,
6271 .set_msglevel = rtl8152_set_msglevel,
6272 .get_wol = rtl8152_get_wol,
6273 .set_wol = rtl8152_set_wol,
6274 .get_strings = rtl8152_get_strings,
6275 .get_sset_count = rtl8152_get_sset_count,
6276 .get_ethtool_stats = rtl8152_get_ethtool_stats,
6277 .get_coalesce = rtl8152_get_coalesce,
6278 .set_coalesce = rtl8152_set_coalesce,
6279 .get_eee = rtl_ethtool_get_eee,
6280 .set_eee = rtl_ethtool_set_eee,
6281 .get_link_ksettings = rtl8152_get_link_ksettings,
6282 .set_link_ksettings = rtl8152_set_link_ksettings,
6283 .get_tunable = rtl8152_get_tunable,
6284 .set_tunable = rtl8152_set_tunable,
6285 .get_ringparam = rtl8152_get_ringparam,
6286 .set_ringparam = rtl8152_set_ringparam,
6289 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
6291 struct r8152 *tp = netdev_priv(netdev);
6292 struct mii_ioctl_data *data = if_mii(rq);
6295 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6298 res = usb_autopm_get_interface(tp->intf);
6304 data->phy_id = R8152_PHY_ID; /* Internal PHY */
6308 mutex_lock(&tp->control);
6309 data->val_out = r8152_mdio_read(tp, data->reg_num);
6310 mutex_unlock(&tp->control);
6314 if (!capable(CAP_NET_ADMIN)) {
6318 mutex_lock(&tp->control);
6319 r8152_mdio_write(tp, data->reg_num, data->val_in);
6320 mutex_unlock(&tp->control);
6327 usb_autopm_put_interface(tp->intf);
6333 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
6335 struct r8152 *tp = netdev_priv(dev);
6338 switch (tp->version) {
6348 ret = usb_autopm_get_interface(tp->intf);
6352 mutex_lock(&tp->control);
6356 if (netif_running(dev)) {
6357 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
6359 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
6361 if (netif_carrier_ok(dev))
6362 r8153_set_rx_early_size(tp);
6365 mutex_unlock(&tp->control);
6367 usb_autopm_put_interface(tp->intf);
6372 static const struct net_device_ops rtl8152_netdev_ops = {
6373 .ndo_open = rtl8152_open,
6374 .ndo_stop = rtl8152_close,
6375 .ndo_do_ioctl = rtl8152_ioctl,
6376 .ndo_start_xmit = rtl8152_start_xmit,
6377 .ndo_tx_timeout = rtl8152_tx_timeout,
6378 .ndo_set_features = rtl8152_set_features,
6379 .ndo_set_rx_mode = rtl8152_set_rx_mode,
6380 .ndo_set_mac_address = rtl8152_set_mac_address,
6381 .ndo_change_mtu = rtl8152_change_mtu,
6382 .ndo_validate_addr = eth_validate_addr,
6383 .ndo_features_check = rtl8152_features_check,
6386 static void rtl8152_unload(struct r8152 *tp)
6388 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6391 if (tp->version != RTL_VER_01)
6392 r8152_power_cut_en(tp, true);
6395 static void rtl8153_unload(struct r8152 *tp)
6397 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6400 r8153_power_cut_en(tp, false);
6403 static void rtl8153b_unload(struct r8152 *tp)
6405 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6408 r8153b_power_cut_en(tp, false);
6411 static int rtl_ops_init(struct r8152 *tp)
6413 struct rtl_ops *ops = &tp->rtl_ops;
6416 switch (tp->version) {
6420 ops->init = r8152b_init;
6421 ops->enable = rtl8152_enable;
6422 ops->disable = rtl8152_disable;
6423 ops->up = rtl8152_up;
6424 ops->down = rtl8152_down;
6425 ops->unload = rtl8152_unload;
6426 ops->eee_get = r8152_get_eee;
6427 ops->eee_set = r8152_set_eee;
6428 ops->in_nway = rtl8152_in_nway;
6429 ops->hw_phy_cfg = r8152b_hw_phy_cfg;
6430 ops->autosuspend_en = rtl_runtime_suspend_enable;
6431 tp->rx_buf_sz = 16 * 1024;
6433 tp->eee_adv = MDIO_EEE_100TX;
6440 ops->init = r8153_init;
6441 ops->enable = rtl8153_enable;
6442 ops->disable = rtl8153_disable;
6443 ops->up = rtl8153_up;
6444 ops->down = rtl8153_down;
6445 ops->unload = rtl8153_unload;
6446 ops->eee_get = r8153_get_eee;
6447 ops->eee_set = r8152_set_eee;
6448 ops->in_nway = rtl8153_in_nway;
6449 ops->hw_phy_cfg = r8153_hw_phy_cfg;
6450 ops->autosuspend_en = rtl8153_runtime_enable;
6451 tp->rx_buf_sz = 32 * 1024;
6453 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
6458 ops->init = r8153b_init;
6459 ops->enable = rtl8153_enable;
6460 ops->disable = rtl8153_disable;
6461 ops->up = rtl8153b_up;
6462 ops->down = rtl8153b_down;
6463 ops->unload = rtl8153b_unload;
6464 ops->eee_get = r8153_get_eee;
6465 ops->eee_set = r8152_set_eee;
6466 ops->in_nway = rtl8153_in_nway;
6467 ops->hw_phy_cfg = r8153b_hw_phy_cfg;
6468 ops->autosuspend_en = rtl8153b_runtime_enable;
6469 tp->rx_buf_sz = 32 * 1024;
6471 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
6476 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
6483 #define FIRMWARE_8153A_2 "rtl_nic/rtl8153a-2.fw"
6484 #define FIRMWARE_8153A_3 "rtl_nic/rtl8153a-3.fw"
6485 #define FIRMWARE_8153A_4 "rtl_nic/rtl8153a-4.fw"
6486 #define FIRMWARE_8153B_2 "rtl_nic/rtl8153b-2.fw"
6488 MODULE_FIRMWARE(FIRMWARE_8153A_2);
6489 MODULE_FIRMWARE(FIRMWARE_8153A_3);
6490 MODULE_FIRMWARE(FIRMWARE_8153A_4);
6491 MODULE_FIRMWARE(FIRMWARE_8153B_2);
6493 static int rtl_fw_init(struct r8152 *tp)
6495 struct rtl_fw *rtl_fw = &tp->rtl_fw;
6497 switch (tp->version) {
6499 rtl_fw->fw_name = FIRMWARE_8153A_2;
6500 rtl_fw->pre_fw = r8153_pre_firmware_1;
6501 rtl_fw->post_fw = r8153_post_firmware_1;
6504 rtl_fw->fw_name = FIRMWARE_8153A_3;
6505 rtl_fw->pre_fw = r8153_pre_firmware_2;
6506 rtl_fw->post_fw = r8153_post_firmware_2;
6509 rtl_fw->fw_name = FIRMWARE_8153A_4;
6510 rtl_fw->post_fw = r8153_post_firmware_3;
6513 rtl_fw->fw_name = FIRMWARE_8153B_2;
6514 rtl_fw->pre_fw = r8153b_pre_firmware_1;
6515 rtl_fw->post_fw = r8153b_post_firmware_1;
6524 static u8 rtl_get_version(struct usb_interface *intf)
6526 struct usb_device *udev = interface_to_usbdev(intf);
6532 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
6536 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
6537 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
6538 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
6540 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
6546 version = RTL_VER_01;
6549 version = RTL_VER_02;
6552 version = RTL_VER_03;
6555 version = RTL_VER_04;
6558 version = RTL_VER_05;
6561 version = RTL_VER_06;
6564 version = RTL_VER_07;
6567 version = RTL_VER_08;
6570 version = RTL_VER_09;
6573 version = RTL_VER_UNKNOWN;
6574 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
6578 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
6583 static int rtl8152_probe(struct usb_interface *intf,
6584 const struct usb_device_id *id)
6586 struct usb_device *udev = interface_to_usbdev(intf);
6587 u8 version = rtl_get_version(intf);
6589 struct net_device *netdev;
6592 if (version == RTL_VER_UNKNOWN)
6595 if (udev->actconfig->desc.bConfigurationValue != 1) {
6596 usb_driver_set_configuration(udev, 1);
6600 usb_reset_device(udev);
6601 netdev = alloc_etherdev(sizeof(struct r8152));
6603 dev_err(&intf->dev, "Out of memory\n");
6607 SET_NETDEV_DEV(netdev, &intf->dev);
6608 tp = netdev_priv(netdev);
6609 tp->msg_enable = 0x7FFF;
6612 tp->netdev = netdev;
6614 tp->version = version;
6620 tp->mii.supports_gmii = 0;
6623 tp->mii.supports_gmii = 1;
6627 ret = rtl_ops_init(tp);
6633 mutex_init(&tp->control);
6634 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
6635 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
6636 tasklet_init(&tp->tx_tl, bottom_half, (unsigned long)tp);
6637 tasklet_disable(&tp->tx_tl);
6639 netdev->netdev_ops = &rtl8152_netdev_ops;
6640 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
6642 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6643 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
6644 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
6645 NETIF_F_HW_VLAN_CTAG_TX;
6646 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6647 NETIF_F_TSO | NETIF_F_FRAGLIST |
6648 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
6649 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
6650 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6651 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
6652 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
6654 if (tp->version == RTL_VER_01) {
6655 netdev->features &= ~NETIF_F_RXCSUM;
6656 netdev->hw_features &= ~NETIF_F_RXCSUM;
6659 if (le16_to_cpu(udev->descriptor.idVendor) == VENDOR_ID_LENOVO &&
6660 le16_to_cpu(udev->descriptor.idProduct) == 0x3082)
6661 set_bit(LENOVO_MACPASSTHRU, &tp->flags);
6663 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
6664 (!strcmp(udev->serial, "000001000000") ||
6665 !strcmp(udev->serial, "000002000000"))) {
6666 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
6667 set_bit(DELL_TB_RX_AGG_BUG, &tp->flags);
6670 netdev->ethtool_ops = &ops;
6671 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
6673 /* MTU range: 68 - 1500 or 9194 */
6674 netdev->min_mtu = ETH_MIN_MTU;
6675 switch (tp->version) {
6678 netdev->max_mtu = ETH_DATA_LEN;
6681 netdev->max_mtu = RTL8153_MAX_MTU;
6685 tp->mii.dev = netdev;
6686 tp->mii.mdio_read = read_mii_word;
6687 tp->mii.mdio_write = write_mii_word;
6688 tp->mii.phy_id_mask = 0x3f;
6689 tp->mii.reg_num_mask = 0x1f;
6690 tp->mii.phy_id = R8152_PHY_ID;
6692 tp->autoneg = AUTONEG_ENABLE;
6693 tp->speed = SPEED_100;
6694 tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
6695 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
6696 if (tp->mii.supports_gmii) {
6697 tp->speed = SPEED_1000;
6698 tp->advertising |= RTL_ADVERTISED_1000_FULL;
6700 tp->duplex = DUPLEX_FULL;
6702 tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
6703 tp->rx_pending = 10 * RTL8152_MAX_RX;
6705 intf->needs_remote_wakeup = 1;
6707 tp->rtl_ops.init(tp);
6708 #if IS_BUILTIN(CONFIG_USB_RTL8152)
6709 /* Retry in case request_firmware() is not ready yet. */
6710 tp->rtl_fw.retry = true;
6712 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
6713 set_ethernet_addr(tp);
6715 usb_set_intfdata(intf, tp);
6716 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
6718 ret = register_netdev(netdev);
6720 netif_err(tp, probe, netdev, "couldn't register the device\n");
6724 if (!rtl_can_wakeup(tp))
6725 __rtl_set_wol(tp, 0);
6727 tp->saved_wolopts = __rtl_get_wol(tp);
6728 if (tp->saved_wolopts)
6729 device_set_wakeup_enable(&udev->dev, true);
6731 device_set_wakeup_enable(&udev->dev, false);
6733 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
6738 tasklet_kill(&tp->tx_tl);
6739 usb_set_intfdata(intf, NULL);
6741 free_netdev(netdev);
6745 static void rtl8152_disconnect(struct usb_interface *intf)
6747 struct r8152 *tp = usb_get_intfdata(intf);
6749 usb_set_intfdata(intf, NULL);
6753 unregister_netdev(tp->netdev);
6754 tasklet_kill(&tp->tx_tl);
6755 cancel_delayed_work_sync(&tp->hw_phy_work);
6756 tp->rtl_ops.unload(tp);
6757 rtl8152_release_firmware(tp);
6758 free_netdev(tp->netdev);
6762 #define REALTEK_USB_DEVICE(vend, prod) \
6763 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
6764 USB_DEVICE_ID_MATCH_INT_CLASS, \
6765 .idVendor = (vend), \
6766 .idProduct = (prod), \
6767 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
6770 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
6771 USB_DEVICE_ID_MATCH_DEVICE, \
6772 .idVendor = (vend), \
6773 .idProduct = (prod), \
6774 .bInterfaceClass = USB_CLASS_COMM, \
6775 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
6776 .bInterfaceProtocol = USB_CDC_PROTO_NONE
6778 /* table of devices that work with this driver */
6779 static const struct usb_device_id rtl8152_table[] = {
6780 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
6781 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
6782 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
6783 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
6784 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
6785 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
6786 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
6787 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)},
6788 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)},
6789 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3082)},
6790 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
6791 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)},
6792 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)},
6793 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0xa387)},
6794 {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
6795 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
6796 {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601)},
6800 MODULE_DEVICE_TABLE(usb, rtl8152_table);
6802 static struct usb_driver rtl8152_driver = {
6804 .id_table = rtl8152_table,
6805 .probe = rtl8152_probe,
6806 .disconnect = rtl8152_disconnect,
6807 .suspend = rtl8152_suspend,
6808 .resume = rtl8152_resume,
6809 .reset_resume = rtl8152_reset_resume,
6810 .pre_reset = rtl8152_pre_reset,
6811 .post_reset = rtl8152_post_reset,
6812 .supports_autosuspend = 1,
6813 .disable_hub_initiated_lpm = 1,
6816 module_usb_driver(rtl8152_driver);
6818 MODULE_AUTHOR(DRIVER_AUTHOR);
6819 MODULE_DESCRIPTION(DRIVER_DESC);
6820 MODULE_LICENSE("GPL");
6821 MODULE_VERSION(DRIVER_VERSION);