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r8152: disable test IO for RTL8153B
[tomoyo/tomoyo-test1.git] / drivers / net / usb / r8152.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *  Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
4  */
5
6 #include <linux/signal.h>
7 #include <linux/slab.h>
8 #include <linux/module.h>
9 #include <linux/netdevice.h>
10 #include <linux/etherdevice.h>
11 #include <linux/mii.h>
12 #include <linux/ethtool.h>
13 #include <linux/usb.h>
14 #include <linux/crc32.h>
15 #include <linux/if_vlan.h>
16 #include <linux/uaccess.h>
17 #include <linux/list.h>
18 #include <linux/ip.h>
19 #include <linux/ipv6.h>
20 #include <net/ip6_checksum.h>
21 #include <uapi/linux/mdio.h>
22 #include <linux/mdio.h>
23 #include <linux/usb/cdc.h>
24 #include <linux/suspend.h>
25 #include <linux/atomic.h>
26 #include <linux/acpi.h>
27 #include <linux/firmware.h>
28 #include <crypto/hash.h>
29
30 /* Information for net-next */
31 #define NETNEXT_VERSION         "11"
32
33 /* Information for net */
34 #define NET_VERSION             "10"
35
36 #define DRIVER_VERSION          "v1." NETNEXT_VERSION "." NET_VERSION
37 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
38 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
39 #define MODULENAME "r8152"
40
41 #define R8152_PHY_ID            32
42
43 #define PLA_IDR                 0xc000
44 #define PLA_RCR                 0xc010
45 #define PLA_RMS                 0xc016
46 #define PLA_RXFIFO_CTRL0        0xc0a0
47 #define PLA_RXFIFO_CTRL1        0xc0a4
48 #define PLA_RXFIFO_CTRL2        0xc0a8
49 #define PLA_DMY_REG0            0xc0b0
50 #define PLA_FMC                 0xc0b4
51 #define PLA_CFG_WOL             0xc0b6
52 #define PLA_TEREDO_CFG          0xc0bc
53 #define PLA_TEREDO_WAKE_BASE    0xc0c4
54 #define PLA_MAR                 0xcd00
55 #define PLA_BACKUP              0xd000
56 #define PLA_BDC_CR              0xd1a0
57 #define PLA_TEREDO_TIMER        0xd2cc
58 #define PLA_REALWOW_TIMER       0xd2e8
59 #define PLA_UPHY_TIMER          0xd388
60 #define PLA_SUSPEND_FLAG        0xd38a
61 #define PLA_INDICATE_FALG       0xd38c
62 #define PLA_MACDBG_PRE          0xd38c  /* RTL_VER_04 only */
63 #define PLA_MACDBG_POST         0xd38e  /* RTL_VER_04 only */
64 #define PLA_EXTRA_STATUS        0xd398
65 #define PLA_EFUSE_DATA          0xdd00
66 #define PLA_EFUSE_CMD           0xdd02
67 #define PLA_LEDSEL              0xdd90
68 #define PLA_LED_FEATURE         0xdd92
69 #define PLA_PHYAR               0xde00
70 #define PLA_BOOT_CTRL           0xe004
71 #define PLA_GPHY_INTR_IMR       0xe022
72 #define PLA_EEE_CR              0xe040
73 #define PLA_EEEP_CR             0xe080
74 #define PLA_MAC_PWR_CTRL        0xe0c0
75 #define PLA_MAC_PWR_CTRL2       0xe0ca
76 #define PLA_MAC_PWR_CTRL3       0xe0cc
77 #define PLA_MAC_PWR_CTRL4       0xe0ce
78 #define PLA_WDT6_CTRL           0xe428
79 #define PLA_TCR0                0xe610
80 #define PLA_TCR1                0xe612
81 #define PLA_MTPS                0xe615
82 #define PLA_TXFIFO_CTRL         0xe618
83 #define PLA_RSTTALLY            0xe800
84 #define PLA_CR                  0xe813
85 #define PLA_CRWECR              0xe81c
86 #define PLA_CONFIG12            0xe81e  /* CONFIG1, CONFIG2 */
87 #define PLA_CONFIG34            0xe820  /* CONFIG3, CONFIG4 */
88 #define PLA_CONFIG5             0xe822
89 #define PLA_PHY_PWR             0xe84c
90 #define PLA_OOB_CTRL            0xe84f
91 #define PLA_CPCR                0xe854
92 #define PLA_MISC_0              0xe858
93 #define PLA_MISC_1              0xe85a
94 #define PLA_OCP_GPHY_BASE       0xe86c
95 #define PLA_TALLYCNT            0xe890
96 #define PLA_SFF_STS_7           0xe8de
97 #define PLA_PHYSTATUS           0xe908
98 #define PLA_BP_BA               0xfc26
99 #define PLA_BP_0                0xfc28
100 #define PLA_BP_1                0xfc2a
101 #define PLA_BP_2                0xfc2c
102 #define PLA_BP_3                0xfc2e
103 #define PLA_BP_4                0xfc30
104 #define PLA_BP_5                0xfc32
105 #define PLA_BP_6                0xfc34
106 #define PLA_BP_7                0xfc36
107 #define PLA_BP_EN               0xfc38
108
109 #define USB_USB2PHY             0xb41e
110 #define USB_SSPHYLINK2          0xb428
111 #define USB_U2P3_CTRL           0xb460
112 #define USB_CSR_DUMMY1          0xb464
113 #define USB_CSR_DUMMY2          0xb466
114 #define USB_DEV_STAT            0xb808
115 #define USB_CONNECT_TIMER       0xcbf8
116 #define USB_MSC_TIMER           0xcbfc
117 #define USB_BURST_SIZE          0xcfc0
118 #define USB_FW_FIX_EN0          0xcfca
119 #define USB_FW_FIX_EN1          0xcfcc
120 #define USB_LPM_CONFIG          0xcfd8
121 #define USB_CSTMR               0xcfef  /* RTL8153A */
122 #define USB_FW_CTRL             0xd334  /* RTL8153B */
123 #define USB_FC_TIMER            0xd340
124 #define USB_USB_CTRL            0xd406
125 #define USB_PHY_CTRL            0xd408
126 #define USB_TX_AGG              0xd40a
127 #define USB_RX_BUF_TH           0xd40c
128 #define USB_USB_TIMER           0xd428
129 #define USB_RX_EARLY_TIMEOUT    0xd42c
130 #define USB_RX_EARLY_SIZE       0xd42e
131 #define USB_PM_CTRL_STATUS      0xd432  /* RTL8153A */
132 #define USB_RX_EXTRA_AGGR_TMR   0xd432  /* RTL8153B */
133 #define USB_TX_DMA              0xd434
134 #define USB_UPT_RXDMA_OWN       0xd437
135 #define USB_TOLERANCE           0xd490
136 #define USB_LPM_CTRL            0xd41a
137 #define USB_BMU_RESET           0xd4b0
138 #define USB_U1U2_TIMER          0xd4da
139 #define USB_FW_TASK             0xd4e8  /* RTL8153B */
140 #define USB_UPS_CTRL            0xd800
141 #define USB_POWER_CUT           0xd80a
142 #define USB_MISC_0              0xd81a
143 #define USB_MISC_1              0xd81f
144 #define USB_AFE_CTRL2           0xd824
145 #define USB_UPS_CFG             0xd842
146 #define USB_UPS_FLAGS           0xd848
147 #define USB_WDT1_CTRL           0xe404
148 #define USB_WDT11_CTRL          0xe43c
149 #define USB_BP_BA               PLA_BP_BA
150 #define USB_BP_0                PLA_BP_0
151 #define USB_BP_1                PLA_BP_1
152 #define USB_BP_2                PLA_BP_2
153 #define USB_BP_3                PLA_BP_3
154 #define USB_BP_4                PLA_BP_4
155 #define USB_BP_5                PLA_BP_5
156 #define USB_BP_6                PLA_BP_6
157 #define USB_BP_7                PLA_BP_7
158 #define USB_BP_EN               PLA_BP_EN       /* RTL8153A */
159 #define USB_BP_8                0xfc38          /* RTL8153B */
160 #define USB_BP_9                0xfc3a
161 #define USB_BP_10               0xfc3c
162 #define USB_BP_11               0xfc3e
163 #define USB_BP_12               0xfc40
164 #define USB_BP_13               0xfc42
165 #define USB_BP_14               0xfc44
166 #define USB_BP_15               0xfc46
167 #define USB_BP2_EN              0xfc48
168
169 /* OCP Registers */
170 #define OCP_ALDPS_CONFIG        0x2010
171 #define OCP_EEE_CONFIG1         0x2080
172 #define OCP_EEE_CONFIG2         0x2092
173 #define OCP_EEE_CONFIG3         0x2094
174 #define OCP_BASE_MII            0xa400
175 #define OCP_EEE_AR              0xa41a
176 #define OCP_EEE_DATA            0xa41c
177 #define OCP_PHY_STATUS          0xa420
178 #define OCP_NCTL_CFG            0xa42c
179 #define OCP_POWER_CFG           0xa430
180 #define OCP_EEE_CFG             0xa432
181 #define OCP_SRAM_ADDR           0xa436
182 #define OCP_SRAM_DATA           0xa438
183 #define OCP_DOWN_SPEED          0xa442
184 #define OCP_EEE_ABLE            0xa5c4
185 #define OCP_EEE_ADV             0xa5d0
186 #define OCP_EEE_LPABLE          0xa5d2
187 #define OCP_PHY_STATE           0xa708          /* nway state for 8153 */
188 #define OCP_PHY_PATCH_STAT      0xb800
189 #define OCP_PHY_PATCH_CMD       0xb820
190 #define OCP_PHY_LOCK            0xb82e
191 #define OCP_ADC_IOFFSET         0xbcfc
192 #define OCP_ADC_CFG             0xbc06
193 #define OCP_SYSCLK_CFG          0xc416
194
195 /* SRAM Register */
196 #define SRAM_GREEN_CFG          0x8011
197 #define SRAM_LPF_CFG            0x8012
198 #define SRAM_10M_AMP1           0x8080
199 #define SRAM_10M_AMP2           0x8082
200 #define SRAM_IMPEDANCE          0x8084
201 #define SRAM_PHY_LOCK           0xb82e
202
203 /* PLA_RCR */
204 #define RCR_AAP                 0x00000001
205 #define RCR_APM                 0x00000002
206 #define RCR_AM                  0x00000004
207 #define RCR_AB                  0x00000008
208 #define RCR_ACPT_ALL            (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
209
210 /* PLA_RXFIFO_CTRL0 */
211 #define RXFIFO_THR1_NORMAL      0x00080002
212 #define RXFIFO_THR1_OOB         0x01800003
213
214 /* PLA_RXFIFO_CTRL1 */
215 #define RXFIFO_THR2_FULL        0x00000060
216 #define RXFIFO_THR2_HIGH        0x00000038
217 #define RXFIFO_THR2_OOB         0x0000004a
218 #define RXFIFO_THR2_NORMAL      0x00a0
219
220 /* PLA_RXFIFO_CTRL2 */
221 #define RXFIFO_THR3_FULL        0x00000078
222 #define RXFIFO_THR3_HIGH        0x00000048
223 #define RXFIFO_THR3_OOB         0x0000005a
224 #define RXFIFO_THR3_NORMAL      0x0110
225
226 /* PLA_TXFIFO_CTRL */
227 #define TXFIFO_THR_NORMAL       0x00400008
228 #define TXFIFO_THR_NORMAL2      0x01000008
229
230 /* PLA_DMY_REG0 */
231 #define ECM_ALDPS               0x0002
232
233 /* PLA_FMC */
234 #define FMC_FCR_MCU_EN          0x0001
235
236 /* PLA_EEEP_CR */
237 #define EEEP_CR_EEEP_TX         0x0002
238
239 /* PLA_WDT6_CTRL */
240 #define WDT6_SET_MODE           0x0010
241
242 /* PLA_TCR0 */
243 #define TCR0_TX_EMPTY           0x0800
244 #define TCR0_AUTO_FIFO          0x0080
245
246 /* PLA_TCR1 */
247 #define VERSION_MASK            0x7cf0
248
249 /* PLA_MTPS */
250 #define MTPS_JUMBO              (12 * 1024 / 64)
251 #define MTPS_DEFAULT            (6 * 1024 / 64)
252
253 /* PLA_RSTTALLY */
254 #define TALLY_RESET             0x0001
255
256 /* PLA_CR */
257 #define CR_RST                  0x10
258 #define CR_RE                   0x08
259 #define CR_TE                   0x04
260
261 /* PLA_CRWECR */
262 #define CRWECR_NORAML           0x00
263 #define CRWECR_CONFIG           0xc0
264
265 /* PLA_OOB_CTRL */
266 #define NOW_IS_OOB              0x80
267 #define TXFIFO_EMPTY            0x20
268 #define RXFIFO_EMPTY            0x10
269 #define LINK_LIST_READY         0x02
270 #define DIS_MCU_CLROOB          0x01
271 #define FIFO_EMPTY              (TXFIFO_EMPTY | RXFIFO_EMPTY)
272
273 /* PLA_MISC_1 */
274 #define RXDY_GATED_EN           0x0008
275
276 /* PLA_SFF_STS_7 */
277 #define RE_INIT_LL              0x8000
278 #define MCU_BORW_EN             0x4000
279
280 /* PLA_CPCR */
281 #define CPCR_RX_VLAN            0x0040
282
283 /* PLA_CFG_WOL */
284 #define MAGIC_EN                0x0001
285
286 /* PLA_TEREDO_CFG */
287 #define TEREDO_SEL              0x8000
288 #define TEREDO_WAKE_MASK        0x7f00
289 #define TEREDO_RS_EVENT_MASK    0x00fe
290 #define OOB_TEREDO_EN           0x0001
291
292 /* PLA_BDC_CR */
293 #define ALDPS_PROXY_MODE        0x0001
294
295 /* PLA_EFUSE_CMD */
296 #define EFUSE_READ_CMD          BIT(15)
297 #define EFUSE_DATA_BIT16        BIT(7)
298
299 /* PLA_CONFIG34 */
300 #define LINK_ON_WAKE_EN         0x0010
301 #define LINK_OFF_WAKE_EN        0x0008
302
303 /* PLA_CONFIG5 */
304 #define BWF_EN                  0x0040
305 #define MWF_EN                  0x0020
306 #define UWF_EN                  0x0010
307 #define LAN_WAKE_EN             0x0002
308
309 /* PLA_LED_FEATURE */
310 #define LED_MODE_MASK           0x0700
311
312 /* PLA_PHY_PWR */
313 #define TX_10M_IDLE_EN          0x0080
314 #define PFM_PWM_SWITCH          0x0040
315 #define TEST_IO_OFF             BIT(4)
316
317 /* PLA_MAC_PWR_CTRL */
318 #define D3_CLK_GATED_EN         0x00004000
319 #define MCU_CLK_RATIO           0x07010f07
320 #define MCU_CLK_RATIO_MASK      0x0f0f0f0f
321 #define ALDPS_SPDWN_RATIO       0x0f87
322
323 /* PLA_MAC_PWR_CTRL2 */
324 #define EEE_SPDWN_RATIO         0x8007
325 #define MAC_CLK_SPDWN_EN        BIT(15)
326
327 /* PLA_MAC_PWR_CTRL3 */
328 #define PLA_MCU_SPDWN_EN        BIT(14)
329 #define PKT_AVAIL_SPDWN_EN      0x0100
330 #define SUSPEND_SPDWN_EN        0x0004
331 #define U1U2_SPDWN_EN           0x0002
332 #define L1_SPDWN_EN             0x0001
333
334 /* PLA_MAC_PWR_CTRL4 */
335 #define PWRSAVE_SPDWN_EN        0x1000
336 #define RXDV_SPDWN_EN           0x0800
337 #define TX10MIDLE_EN            0x0100
338 #define TP100_SPDWN_EN          0x0020
339 #define TP500_SPDWN_EN          0x0010
340 #define TP1000_SPDWN_EN         0x0008
341 #define EEE_SPDWN_EN            0x0001
342
343 /* PLA_GPHY_INTR_IMR */
344 #define GPHY_STS_MSK            0x0001
345 #define SPEED_DOWN_MSK          0x0002
346 #define SPDWN_RXDV_MSK          0x0004
347 #define SPDWN_LINKCHG_MSK       0x0008
348
349 /* PLA_PHYAR */
350 #define PHYAR_FLAG              0x80000000
351
352 /* PLA_EEE_CR */
353 #define EEE_RX_EN               0x0001
354 #define EEE_TX_EN               0x0002
355
356 /* PLA_BOOT_CTRL */
357 #define AUTOLOAD_DONE           0x0002
358
359 /* PLA_SUSPEND_FLAG */
360 #define LINK_CHG_EVENT          BIT(0)
361
362 /* PLA_INDICATE_FALG */
363 #define UPCOMING_RUNTIME_D3     BIT(0)
364
365 /* PLA_MACDBG_PRE and PLA_MACDBG_POST */
366 #define DEBUG_OE                BIT(0)
367 #define DEBUG_LTSSM             0x0082
368
369 /* PLA_EXTRA_STATUS */
370 #define CUR_LINK_OK             BIT(15)
371 #define U3P3_CHECK_EN           BIT(7)  /* RTL_VER_05 only */
372 #define LINK_CHANGE_FLAG        BIT(8)
373 #define POLL_LINK_CHG           BIT(0)
374
375 /* USB_USB2PHY */
376 #define USB2PHY_SUSPEND         0x0001
377 #define USB2PHY_L1              0x0002
378
379 /* USB_SSPHYLINK2 */
380 #define pwd_dn_scale_mask       0x3ffe
381 #define pwd_dn_scale(x)         ((x) << 1)
382
383 /* USB_CSR_DUMMY1 */
384 #define DYNAMIC_BURST           0x0001
385
386 /* USB_CSR_DUMMY2 */
387 #define EP4_FULL_FC             0x0001
388
389 /* USB_DEV_STAT */
390 #define STAT_SPEED_MASK         0x0006
391 #define STAT_SPEED_HIGH         0x0000
392 #define STAT_SPEED_FULL         0x0002
393
394 /* USB_FW_FIX_EN0 */
395 #define FW_FIX_SUSPEND          BIT(14)
396
397 /* USB_FW_FIX_EN1 */
398 #define FW_IP_RESET_EN          BIT(9)
399
400 /* USB_LPM_CONFIG */
401 #define LPM_U1U2_EN             BIT(0)
402
403 /* USB_TX_AGG */
404 #define TX_AGG_MAX_THRESHOLD    0x03
405
406 /* USB_RX_BUF_TH */
407 #define RX_THR_SUPPER           0x0c350180
408 #define RX_THR_HIGH             0x7a120180
409 #define RX_THR_SLOW             0xffff0180
410 #define RX_THR_B                0x00010001
411
412 /* USB_TX_DMA */
413 #define TEST_MODE_DISABLE       0x00000001
414 #define TX_SIZE_ADJUST1         0x00000100
415
416 /* USB_BMU_RESET */
417 #define BMU_RESET_EP_IN         0x01
418 #define BMU_RESET_EP_OUT        0x02
419
420 /* USB_UPT_RXDMA_OWN */
421 #define OWN_UPDATE              BIT(0)
422 #define OWN_CLEAR               BIT(1)
423
424 /* USB_FW_TASK */
425 #define FC_PATCH_TASK           BIT(1)
426
427 /* USB_UPS_CTRL */
428 #define POWER_CUT               0x0100
429
430 /* USB_PM_CTRL_STATUS */
431 #define RESUME_INDICATE         0x0001
432
433 /* USB_CSTMR */
434 #define FORCE_SUPER             BIT(0)
435
436 /* USB_FW_CTRL */
437 #define FLOW_CTRL_PATCH_OPT     BIT(1)
438
439 /* USB_FC_TIMER */
440 #define CTRL_TIMER_EN           BIT(15)
441
442 /* USB_USB_CTRL */
443 #define RX_AGG_DISABLE          0x0010
444 #define RX_ZERO_EN              0x0080
445
446 /* USB_U2P3_CTRL */
447 #define U2P3_ENABLE             0x0001
448
449 /* USB_POWER_CUT */
450 #define PWR_EN                  0x0001
451 #define PHASE2_EN               0x0008
452 #define UPS_EN                  BIT(4)
453 #define USP_PREWAKE             BIT(5)
454
455 /* USB_MISC_0 */
456 #define PCUT_STATUS             0x0001
457
458 /* USB_RX_EARLY_TIMEOUT */
459 #define COALESCE_SUPER           85000U
460 #define COALESCE_HIGH           250000U
461 #define COALESCE_SLOW           524280U
462
463 /* USB_WDT1_CTRL */
464 #define WTD1_EN                 BIT(0)
465
466 /* USB_WDT11_CTRL */
467 #define TIMER11_EN              0x0001
468
469 /* USB_LPM_CTRL */
470 /* bit 4 ~ 5: fifo empty boundary */
471 #define FIFO_EMPTY_1FB          0x30    /* 0x1fb * 64 = 32448 bytes */
472 /* bit 2 ~ 3: LMP timer */
473 #define LPM_TIMER_MASK          0x0c
474 #define LPM_TIMER_500MS         0x04    /* 500 ms */
475 #define LPM_TIMER_500US         0x0c    /* 500 us */
476 #define ROK_EXIT_LPM            0x02
477
478 /* USB_AFE_CTRL2 */
479 #define SEN_VAL_MASK            0xf800
480 #define SEN_VAL_NORMAL          0xa000
481 #define SEL_RXIDLE              0x0100
482
483 /* USB_UPS_CFG */
484 #define SAW_CNT_1MS_MASK        0x0fff
485
486 /* USB_UPS_FLAGS */
487 #define UPS_FLAGS_R_TUNE                BIT(0)
488 #define UPS_FLAGS_EN_10M_CKDIV          BIT(1)
489 #define UPS_FLAGS_250M_CKDIV            BIT(2)
490 #define UPS_FLAGS_EN_ALDPS              BIT(3)
491 #define UPS_FLAGS_CTAP_SHORT_DIS        BIT(4)
492 #define ups_flags_speed(x)              ((x) << 16)
493 #define UPS_FLAGS_EN_EEE                BIT(20)
494 #define UPS_FLAGS_EN_500M_EEE           BIT(21)
495 #define UPS_FLAGS_EN_EEE_CKDIV          BIT(22)
496 #define UPS_FLAGS_EEE_PLLOFF_100        BIT(23)
497 #define UPS_FLAGS_EEE_PLLOFF_GIGA       BIT(24)
498 #define UPS_FLAGS_EEE_CMOD_LV_EN        BIT(25)
499 #define UPS_FLAGS_EN_GREEN              BIT(26)
500 #define UPS_FLAGS_EN_FLOW_CTR           BIT(27)
501
502 enum spd_duplex {
503         NWAY_10M_HALF,
504         NWAY_10M_FULL,
505         NWAY_100M_HALF,
506         NWAY_100M_FULL,
507         NWAY_1000M_FULL,
508         FORCE_10M_HALF,
509         FORCE_10M_FULL,
510         FORCE_100M_HALF,
511         FORCE_100M_FULL,
512 };
513
514 /* OCP_ALDPS_CONFIG */
515 #define ENPWRSAVE               0x8000
516 #define ENPDNPS                 0x0200
517 #define LINKENA                 0x0100
518 #define DIS_SDSAVE              0x0010
519
520 /* OCP_PHY_STATUS */
521 #define PHY_STAT_MASK           0x0007
522 #define PHY_STAT_EXT_INIT       2
523 #define PHY_STAT_LAN_ON         3
524 #define PHY_STAT_PWRDN          5
525
526 /* OCP_NCTL_CFG */
527 #define PGA_RETURN_EN           BIT(1)
528
529 /* OCP_POWER_CFG */
530 #define EEE_CLKDIV_EN           0x8000
531 #define EN_ALDPS                0x0004
532 #define EN_10M_PLLOFF           0x0001
533
534 /* OCP_EEE_CONFIG1 */
535 #define RG_TXLPI_MSK_HFDUP      0x8000
536 #define RG_MATCLR_EN            0x4000
537 #define EEE_10_CAP              0x2000
538 #define EEE_NWAY_EN             0x1000
539 #define TX_QUIET_EN             0x0200
540 #define RX_QUIET_EN             0x0100
541 #define sd_rise_time_mask       0x0070
542 #define sd_rise_time(x)         (min(x, 7) << 4)        /* bit 4 ~ 6 */
543 #define RG_RXLPI_MSK_HFDUP      0x0008
544 #define SDFALLTIME              0x0007  /* bit 0 ~ 2 */
545
546 /* OCP_EEE_CONFIG2 */
547 #define RG_LPIHYS_NUM           0x7000  /* bit 12 ~ 15 */
548 #define RG_DACQUIET_EN          0x0400
549 #define RG_LDVQUIET_EN          0x0200
550 #define RG_CKRSEL               0x0020
551 #define RG_EEEPRG_EN            0x0010
552
553 /* OCP_EEE_CONFIG3 */
554 #define fast_snr_mask           0xff80
555 #define fast_snr(x)             (min(x, 0x1ff) << 7)    /* bit 7 ~ 15 */
556 #define RG_LFS_SEL              0x0060  /* bit 6 ~ 5 */
557 #define MSK_PH                  0x0006  /* bit 0 ~ 3 */
558
559 /* OCP_EEE_AR */
560 /* bit[15:14] function */
561 #define FUN_ADDR                0x0000
562 #define FUN_DATA                0x4000
563 /* bit[4:0] device addr */
564
565 /* OCP_EEE_CFG */
566 #define CTAP_SHORT_EN           0x0040
567 #define EEE10_EN                0x0010
568
569 /* OCP_DOWN_SPEED */
570 #define EN_EEE_CMODE            BIT(14)
571 #define EN_EEE_1000             BIT(13)
572 #define EN_EEE_100              BIT(12)
573 #define EN_10M_CLKDIV           BIT(11)
574 #define EN_10M_BGOFF            0x0080
575
576 /* OCP_PHY_STATE */
577 #define TXDIS_STATE             0x01
578 #define ABD_STATE               0x02
579
580 /* OCP_PHY_PATCH_STAT */
581 #define PATCH_READY             BIT(6)
582
583 /* OCP_PHY_PATCH_CMD */
584 #define PATCH_REQUEST           BIT(4)
585
586 /* OCP_PHY_LOCK */
587 #define PATCH_LOCK              BIT(0)
588
589 /* OCP_ADC_CFG */
590 #define CKADSEL_L               0x0100
591 #define ADC_EN                  0x0080
592 #define EN_EMI_L                0x0040
593
594 /* OCP_SYSCLK_CFG */
595 #define clk_div_expo(x)         (min(x, 5) << 8)
596
597 /* SRAM_GREEN_CFG */
598 #define GREEN_ETH_EN            BIT(15)
599 #define R_TUNE_EN               BIT(11)
600
601 /* SRAM_LPF_CFG */
602 #define LPF_AUTO_TUNE           0x8000
603
604 /* SRAM_10M_AMP1 */
605 #define GDAC_IB_UPALL           0x0008
606
607 /* SRAM_10M_AMP2 */
608 #define AMP_DN                  0x0200
609
610 /* SRAM_IMPEDANCE */
611 #define RX_DRIVING_MASK         0x6000
612
613 /* SRAM_PHY_LOCK */
614 #define PHY_PATCH_LOCK          0x0001
615
616 /* MAC PASSTHRU */
617 #define AD_MASK                 0xfee0
618 #define BND_MASK                0x0004
619 #define BD_MASK                 0x0001
620 #define EFUSE                   0xcfdb
621 #define PASS_THRU_MASK          0x1
622
623 #define BP4_SUPER_ONLY          0x1578  /* RTL_VER_04 only */
624
625 enum rtl_register_content {
626         _1000bps        = 0x10,
627         _100bps         = 0x08,
628         _10bps          = 0x04,
629         LINK_STATUS     = 0x02,
630         FULL_DUP        = 0x01,
631 };
632
633 #define RTL8152_MAX_TX          4
634 #define RTL8152_MAX_RX          10
635 #define INTBUFSIZE              2
636 #define TX_ALIGN                4
637 #define RX_ALIGN                8
638
639 #define RTL8152_RX_MAX_PENDING  4096
640 #define RTL8152_RXFG_HEADSZ     256
641
642 #define INTR_LINK               0x0004
643
644 #define RTL8152_REQT_READ       0xc0
645 #define RTL8152_REQT_WRITE      0x40
646 #define RTL8152_REQ_GET_REGS    0x05
647 #define RTL8152_REQ_SET_REGS    0x05
648
649 #define BYTE_EN_DWORD           0xff
650 #define BYTE_EN_WORD            0x33
651 #define BYTE_EN_BYTE            0x11
652 #define BYTE_EN_SIX_BYTES       0x3f
653 #define BYTE_EN_START_MASK      0x0f
654 #define BYTE_EN_END_MASK        0xf0
655
656 #define RTL8153_MAX_PACKET      9216 /* 9K */
657 #define RTL8153_MAX_MTU         (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
658                                  ETH_FCS_LEN)
659 #define RTL8152_RMS             (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
660 #define RTL8153_RMS             RTL8153_MAX_PACKET
661 #define RTL8152_TX_TIMEOUT      (5 * HZ)
662 #define RTL8152_NAPI_WEIGHT     64
663 #define rx_reserved_size(x)     ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
664                                  sizeof(struct rx_desc) + RX_ALIGN)
665
666 /* rtl8152 flags */
667 enum rtl8152_flags {
668         RTL8152_UNPLUG = 0,
669         RTL8152_SET_RX_MODE,
670         WORK_ENABLE,
671         RTL8152_LINK_CHG,
672         SELECTIVE_SUSPEND,
673         PHY_RESET,
674         SCHEDULE_TASKLET,
675         GREEN_ETHERNET,
676         DELL_TB_RX_AGG_BUG,
677         LENOVO_MACPASSTHRU,
678 };
679
680 /* Define these values to match your device */
681 #define VENDOR_ID_REALTEK               0x0bda
682 #define VENDOR_ID_MICROSOFT             0x045e
683 #define VENDOR_ID_SAMSUNG               0x04e8
684 #define VENDOR_ID_LENOVO                0x17ef
685 #define VENDOR_ID_LINKSYS               0x13b1
686 #define VENDOR_ID_NVIDIA                0x0955
687 #define VENDOR_ID_TPLINK                0x2357
688
689 #define MCU_TYPE_PLA                    0x0100
690 #define MCU_TYPE_USB                    0x0000
691
692 struct tally_counter {
693         __le64  tx_packets;
694         __le64  rx_packets;
695         __le64  tx_errors;
696         __le32  rx_errors;
697         __le16  rx_missed;
698         __le16  align_errors;
699         __le32  tx_one_collision;
700         __le32  tx_multi_collision;
701         __le64  rx_unicast;
702         __le64  rx_broadcast;
703         __le32  rx_multicast;
704         __le16  tx_aborted;
705         __le16  tx_underrun;
706 };
707
708 struct rx_desc {
709         __le32 opts1;
710 #define RX_LEN_MASK                     0x7fff
711
712         __le32 opts2;
713 #define RD_UDP_CS                       BIT(23)
714 #define RD_TCP_CS                       BIT(22)
715 #define RD_IPV6_CS                      BIT(20)
716 #define RD_IPV4_CS                      BIT(19)
717
718         __le32 opts3;
719 #define IPF                             BIT(23) /* IP checksum fail */
720 #define UDPF                            BIT(22) /* UDP checksum fail */
721 #define TCPF                            BIT(21) /* TCP checksum fail */
722 #define RX_VLAN_TAG                     BIT(16)
723
724         __le32 opts4;
725         __le32 opts5;
726         __le32 opts6;
727 };
728
729 struct tx_desc {
730         __le32 opts1;
731 #define TX_FS                   BIT(31) /* First segment of a packet */
732 #define TX_LS                   BIT(30) /* Final segment of a packet */
733 #define GTSENDV4                BIT(28)
734 #define GTSENDV6                BIT(27)
735 #define GTTCPHO_SHIFT           18
736 #define GTTCPHO_MAX             0x7fU
737 #define TX_LEN_MAX              0x3ffffU
738
739         __le32 opts2;
740 #define UDP_CS                  BIT(31) /* Calculate UDP/IP checksum */
741 #define TCP_CS                  BIT(30) /* Calculate TCP/IP checksum */
742 #define IPV4_CS                 BIT(29) /* Calculate IPv4 checksum */
743 #define IPV6_CS                 BIT(28) /* Calculate IPv6 checksum */
744 #define MSS_SHIFT               17
745 #define MSS_MAX                 0x7ffU
746 #define TCPHO_SHIFT             17
747 #define TCPHO_MAX               0x7ffU
748 #define TX_VLAN_TAG             BIT(16)
749 };
750
751 struct r8152;
752
753 struct rx_agg {
754         struct list_head list, info_list;
755         struct urb *urb;
756         struct r8152 *context;
757         struct page *page;
758         void *buffer;
759 };
760
761 struct tx_agg {
762         struct list_head list;
763         struct urb *urb;
764         struct r8152 *context;
765         void *buffer;
766         void *head;
767         u32 skb_num;
768         u32 skb_len;
769 };
770
771 struct r8152 {
772         unsigned long flags;
773         struct usb_device *udev;
774         struct napi_struct napi;
775         struct usb_interface *intf;
776         struct net_device *netdev;
777         struct urb *intr_urb;
778         struct tx_agg tx_info[RTL8152_MAX_TX];
779         struct list_head rx_info, rx_used;
780         struct list_head rx_done, tx_free;
781         struct sk_buff_head tx_queue, rx_queue;
782         spinlock_t rx_lock, tx_lock;
783         struct delayed_work schedule, hw_phy_work;
784         struct mii_if_info mii;
785         struct mutex control;   /* use for hw setting */
786 #ifdef CONFIG_PM_SLEEP
787         struct notifier_block pm_notifier;
788 #endif
789         struct tasklet_struct tx_tl;
790
791         struct rtl_ops {
792                 void (*init)(struct r8152 *tp);
793                 int (*enable)(struct r8152 *tp);
794                 void (*disable)(struct r8152 *tp);
795                 void (*up)(struct r8152 *tp);
796                 void (*down)(struct r8152 *tp);
797                 void (*unload)(struct r8152 *tp);
798                 int (*eee_get)(struct r8152 *tp, struct ethtool_eee *eee);
799                 int (*eee_set)(struct r8152 *tp, struct ethtool_eee *eee);
800                 bool (*in_nway)(struct r8152 *tp);
801                 void (*hw_phy_cfg)(struct r8152 *tp);
802                 void (*autosuspend_en)(struct r8152 *tp, bool enable);
803         } rtl_ops;
804
805         struct ups_info {
806                 u32 _10m_ckdiv:1;
807                 u32 _250m_ckdiv:1;
808                 u32 aldps:1;
809                 u32 lite_mode:2;
810                 u32 speed_duplex:4;
811                 u32 eee:1;
812                 u32 eee_lite:1;
813                 u32 eee_ckdiv:1;
814                 u32 eee_plloff_100:1;
815                 u32 eee_plloff_giga:1;
816                 u32 eee_cmod_lv:1;
817                 u32 green:1;
818                 u32 flow_control:1;
819                 u32 ctap_short_off:1;
820         } ups_info;
821
822 #define RTL_VER_SIZE            32
823
824         struct rtl_fw {
825                 const char *fw_name;
826                 const struct firmware *fw;
827
828                 char version[RTL_VER_SIZE];
829                 int (*pre_fw)(struct r8152 *tp);
830                 int (*post_fw)(struct r8152 *tp);
831
832                 bool retry;
833         } rtl_fw;
834
835         atomic_t rx_count;
836
837         bool eee_en;
838         int intr_interval;
839         u32 saved_wolopts;
840         u32 msg_enable;
841         u32 tx_qlen;
842         u32 coalesce;
843         u32 advertising;
844         u32 rx_buf_sz;
845         u32 rx_copybreak;
846         u32 rx_pending;
847
848         u16 ocp_base;
849         u16 speed;
850         u16 eee_adv;
851         u8 *intr_buff;
852         u8 version;
853         u8 duplex;
854         u8 autoneg;
855 };
856
857 /**
858  * struct fw_block - block type and total length
859  * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
860  *      RTL_FW_USB and so on.
861  * @length: total length of the current block.
862  */
863 struct fw_block {
864         __le32 type;
865         __le32 length;
866 } __packed;
867
868 /**
869  * struct fw_header - header of the firmware file
870  * @checksum: checksum of sha256 which is calculated from the whole file
871  *      except the checksum field of the file. That is, calculate sha256
872  *      from the version field to the end of the file.
873  * @version: version of this firmware.
874  * @blocks: the first firmware block of the file
875  */
876 struct fw_header {
877         u8 checksum[32];
878         char version[RTL_VER_SIZE];
879         struct fw_block blocks[0];
880 } __packed;
881
882 /**
883  * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
884  *      The layout of the firmware block is:
885  *      <struct fw_mac> + <info> + <firmware data>.
886  * @fw_offset: offset of the firmware binary data. The start address of
887  *      the data would be the address of struct fw_mac + @fw_offset.
888  * @fw_reg: the register to load the firmware. Depends on chip.
889  * @bp_ba_addr: the register to write break point base address. Depends on
890  *      chip.
891  * @bp_ba_value: break point base address. Depends on chip.
892  * @bp_en_addr: the register to write break point enabled mask. Depends
893  *      on chip.
894  * @bp_en_value: break point enabled mask. Depends on the firmware.
895  * @bp_start: the start register of break points. Depends on chip.
896  * @bp_num: the break point number which needs to be set for this firmware.
897  *      Depends on the firmware.
898  * @bp: break points. Depends on firmware.
899  * @fw_ver_reg: the register to store the fw version.
900  * @fw_ver_data: the firmware version of the current type.
901  * @info: additional information for debugging, and is followed by the
902  *      binary data of firmware.
903  */
904 struct fw_mac {
905         struct fw_block blk_hdr;
906         __le16 fw_offset;
907         __le16 fw_reg;
908         __le16 bp_ba_addr;
909         __le16 bp_ba_value;
910         __le16 bp_en_addr;
911         __le16 bp_en_value;
912         __le16 bp_start;
913         __le16 bp_num;
914         __le16 bp[16]; /* any value determined by firmware */
915         __le32 reserved;
916         __le16 fw_ver_reg;
917         u8 fw_ver_data;
918         char info[0];
919 } __packed;
920
921 /**
922  * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.
923  *      This is used to set patch key when loading the firmware of PHY.
924  * @key_reg: the register to write the patch key.
925  * @key_data: patch key.
926  */
927 struct fw_phy_patch_key {
928         struct fw_block blk_hdr;
929         __le16 key_reg;
930         __le16 key_data;
931         __le32 reserved;
932 } __packed;
933
934 /**
935  * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.
936  *      The layout of the firmware block is:
937  *      <struct fw_phy_nc> + <info> + <firmware data>.
938  * @fw_offset: offset of the firmware binary data. The start address of
939  *      the data would be the address of struct fw_phy_nc + @fw_offset.
940  * @fw_reg: the register to load the firmware. Depends on chip.
941  * @ba_reg: the register to write the base address. Depends on chip.
942  * @ba_data: base address. Depends on chip.
943  * @patch_en_addr: the register of enabling patch mode. Depends on chip.
944  * @patch_en_value: patch mode enabled mask. Depends on the firmware.
945  * @mode_reg: the regitster of switching the mode.
946  * @mod_pre: the mode needing to be set before loading the firmware.
947  * @mod_post: the mode to be set when finishing to load the firmware.
948  * @bp_start: the start register of break points. Depends on chip.
949  * @bp_num: the break point number which needs to be set for this firmware.
950  *      Depends on the firmware.
951  * @bp: break points. Depends on firmware.
952  * @info: additional information for debugging, and is followed by the
953  *      binary data of firmware.
954  */
955 struct fw_phy_nc {
956         struct fw_block blk_hdr;
957         __le16 fw_offset;
958         __le16 fw_reg;
959         __le16 ba_reg;
960         __le16 ba_data;
961         __le16 patch_en_addr;
962         __le16 patch_en_value;
963         __le16 mode_reg;
964         __le16 mode_pre;
965         __le16 mode_post;
966         __le16 reserved;
967         __le16 bp_start;
968         __le16 bp_num;
969         __le16 bp[4];
970         char info[0];
971 } __packed;
972
973 enum rtl_fw_type {
974         RTL_FW_END = 0,
975         RTL_FW_PLA,
976         RTL_FW_USB,
977         RTL_FW_PHY_START,
978         RTL_FW_PHY_STOP,
979         RTL_FW_PHY_NC,
980 };
981
982 enum rtl_version {
983         RTL_VER_UNKNOWN = 0,
984         RTL_VER_01,
985         RTL_VER_02,
986         RTL_VER_03,
987         RTL_VER_04,
988         RTL_VER_05,
989         RTL_VER_06,
990         RTL_VER_07,
991         RTL_VER_08,
992         RTL_VER_09,
993         RTL_VER_MAX
994 };
995
996 enum tx_csum_stat {
997         TX_CSUM_SUCCESS = 0,
998         TX_CSUM_TSO,
999         TX_CSUM_NONE
1000 };
1001
1002 #define RTL_ADVERTISED_10_HALF                  BIT(0)
1003 #define RTL_ADVERTISED_10_FULL                  BIT(1)
1004 #define RTL_ADVERTISED_100_HALF                 BIT(2)
1005 #define RTL_ADVERTISED_100_FULL                 BIT(3)
1006 #define RTL_ADVERTISED_1000_HALF                BIT(4)
1007 #define RTL_ADVERTISED_1000_FULL                BIT(5)
1008
1009 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
1010  * The RTL chips use a 64 element hash table based on the Ethernet CRC.
1011  */
1012 static const int multicast_filter_limit = 32;
1013 static unsigned int agg_buf_sz = 16384;
1014
1015 #define RTL_LIMITED_TSO_SIZE    (agg_buf_sz - sizeof(struct tx_desc) - \
1016                                  VLAN_ETH_HLEN - ETH_FCS_LEN)
1017
1018 static
1019 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1020 {
1021         int ret;
1022         void *tmp;
1023
1024         tmp = kmalloc(size, GFP_KERNEL);
1025         if (!tmp)
1026                 return -ENOMEM;
1027
1028         ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
1029                               RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
1030                               value, index, tmp, size, 500);
1031         if (ret < 0)
1032                 memset(data, 0xff, size);
1033         else
1034                 memcpy(data, tmp, size);
1035
1036         kfree(tmp);
1037
1038         return ret;
1039 }
1040
1041 static
1042 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1043 {
1044         int ret;
1045         void *tmp;
1046
1047         tmp = kmemdup(data, size, GFP_KERNEL);
1048         if (!tmp)
1049                 return -ENOMEM;
1050
1051         ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
1052                               RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
1053                               value, index, tmp, size, 500);
1054
1055         kfree(tmp);
1056
1057         return ret;
1058 }
1059
1060 static void rtl_set_unplug(struct r8152 *tp)
1061 {
1062         if (tp->udev->state == USB_STATE_NOTATTACHED) {
1063                 set_bit(RTL8152_UNPLUG, &tp->flags);
1064                 smp_mb__after_atomic();
1065         }
1066 }
1067
1068 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
1069                             void *data, u16 type)
1070 {
1071         u16 limit = 64;
1072         int ret = 0;
1073
1074         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1075                 return -ENODEV;
1076
1077         /* both size and indix must be 4 bytes align */
1078         if ((size & 3) || !size || (index & 3) || !data)
1079                 return -EPERM;
1080
1081         if ((u32)index + (u32)size > 0xffff)
1082                 return -EPERM;
1083
1084         while (size) {
1085                 if (size > limit) {
1086                         ret = get_registers(tp, index, type, limit, data);
1087                         if (ret < 0)
1088                                 break;
1089
1090                         index += limit;
1091                         data += limit;
1092                         size -= limit;
1093                 } else {
1094                         ret = get_registers(tp, index, type, size, data);
1095                         if (ret < 0)
1096                                 break;
1097
1098                         index += size;
1099                         data += size;
1100                         size = 0;
1101                         break;
1102                 }
1103         }
1104
1105         if (ret == -ENODEV)
1106                 rtl_set_unplug(tp);
1107
1108         return ret;
1109 }
1110
1111 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
1112                              u16 size, void *data, u16 type)
1113 {
1114         int ret;
1115         u16 byteen_start, byteen_end, byen;
1116         u16 limit = 512;
1117
1118         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1119                 return -ENODEV;
1120
1121         /* both size and indix must be 4 bytes align */
1122         if ((size & 3) || !size || (index & 3) || !data)
1123                 return -EPERM;
1124
1125         if ((u32)index + (u32)size > 0xffff)
1126                 return -EPERM;
1127
1128         byteen_start = byteen & BYTE_EN_START_MASK;
1129         byteen_end = byteen & BYTE_EN_END_MASK;
1130
1131         byen = byteen_start | (byteen_start << 4);
1132         ret = set_registers(tp, index, type | byen, 4, data);
1133         if (ret < 0)
1134                 goto error1;
1135
1136         index += 4;
1137         data += 4;
1138         size -= 4;
1139
1140         if (size) {
1141                 size -= 4;
1142
1143                 while (size) {
1144                         if (size > limit) {
1145                                 ret = set_registers(tp, index,
1146                                                     type | BYTE_EN_DWORD,
1147                                                     limit, data);
1148                                 if (ret < 0)
1149                                         goto error1;
1150
1151                                 index += limit;
1152                                 data += limit;
1153                                 size -= limit;
1154                         } else {
1155                                 ret = set_registers(tp, index,
1156                                                     type | BYTE_EN_DWORD,
1157                                                     size, data);
1158                                 if (ret < 0)
1159                                         goto error1;
1160
1161                                 index += size;
1162                                 data += size;
1163                                 size = 0;
1164                                 break;
1165                         }
1166                 }
1167
1168                 byen = byteen_end | (byteen_end >> 4);
1169                 ret = set_registers(tp, index, type | byen, 4, data);
1170                 if (ret < 0)
1171                         goto error1;
1172         }
1173
1174 error1:
1175         if (ret == -ENODEV)
1176                 rtl_set_unplug(tp);
1177
1178         return ret;
1179 }
1180
1181 static inline
1182 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
1183 {
1184         return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
1185 }
1186
1187 static inline
1188 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1189 {
1190         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
1191 }
1192
1193 static inline
1194 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1195 {
1196         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
1197 }
1198
1199 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
1200 {
1201         __le32 data;
1202
1203         generic_ocp_read(tp, index, sizeof(data), &data, type);
1204
1205         return __le32_to_cpu(data);
1206 }
1207
1208 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
1209 {
1210         __le32 tmp = __cpu_to_le32(data);
1211
1212         generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
1213 }
1214
1215 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
1216 {
1217         u32 data;
1218         __le32 tmp;
1219         u16 byen = BYTE_EN_WORD;
1220         u8 shift = index & 2;
1221
1222         index &= ~3;
1223         byen <<= shift;
1224
1225         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
1226
1227         data = __le32_to_cpu(tmp);
1228         data >>= (shift * 8);
1229         data &= 0xffff;
1230
1231         return (u16)data;
1232 }
1233
1234 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1235 {
1236         u32 mask = 0xffff;
1237         __le32 tmp;
1238         u16 byen = BYTE_EN_WORD;
1239         u8 shift = index & 2;
1240
1241         data &= mask;
1242
1243         if (index & 2) {
1244                 byen <<= shift;
1245                 mask <<= (shift * 8);
1246                 data <<= (shift * 8);
1247                 index &= ~3;
1248         }
1249
1250         tmp = __cpu_to_le32(data);
1251
1252         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1253 }
1254
1255 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1256 {
1257         u32 data;
1258         __le32 tmp;
1259         u8 shift = index & 3;
1260
1261         index &= ~3;
1262
1263         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1264
1265         data = __le32_to_cpu(tmp);
1266         data >>= (shift * 8);
1267         data &= 0xff;
1268
1269         return (u8)data;
1270 }
1271
1272 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1273 {
1274         u32 mask = 0xff;
1275         __le32 tmp;
1276         u16 byen = BYTE_EN_BYTE;
1277         u8 shift = index & 3;
1278
1279         data &= mask;
1280
1281         if (index & 3) {
1282                 byen <<= shift;
1283                 mask <<= (shift * 8);
1284                 data <<= (shift * 8);
1285                 index &= ~3;
1286         }
1287
1288         tmp = __cpu_to_le32(data);
1289
1290         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1291 }
1292
1293 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1294 {
1295         u16 ocp_base, ocp_index;
1296
1297         ocp_base = addr & 0xf000;
1298         if (ocp_base != tp->ocp_base) {
1299                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1300                 tp->ocp_base = ocp_base;
1301         }
1302
1303         ocp_index = (addr & 0x0fff) | 0xb000;
1304         return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1305 }
1306
1307 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1308 {
1309         u16 ocp_base, ocp_index;
1310
1311         ocp_base = addr & 0xf000;
1312         if (ocp_base != tp->ocp_base) {
1313                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1314                 tp->ocp_base = ocp_base;
1315         }
1316
1317         ocp_index = (addr & 0x0fff) | 0xb000;
1318         ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1319 }
1320
1321 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1322 {
1323         ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1324 }
1325
1326 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1327 {
1328         return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1329 }
1330
1331 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1332 {
1333         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1334         ocp_reg_write(tp, OCP_SRAM_DATA, data);
1335 }
1336
1337 static u16 sram_read(struct r8152 *tp, u16 addr)
1338 {
1339         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1340         return ocp_reg_read(tp, OCP_SRAM_DATA);
1341 }
1342
1343 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1344 {
1345         struct r8152 *tp = netdev_priv(netdev);
1346         int ret;
1347
1348         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1349                 return -ENODEV;
1350
1351         if (phy_id != R8152_PHY_ID)
1352                 return -EINVAL;
1353
1354         ret = r8152_mdio_read(tp, reg);
1355
1356         return ret;
1357 }
1358
1359 static
1360 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1361 {
1362         struct r8152 *tp = netdev_priv(netdev);
1363
1364         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1365                 return;
1366
1367         if (phy_id != R8152_PHY_ID)
1368                 return;
1369
1370         r8152_mdio_write(tp, reg, val);
1371 }
1372
1373 static int
1374 r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1375
1376 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1377 {
1378         struct r8152 *tp = netdev_priv(netdev);
1379         struct sockaddr *addr = p;
1380         int ret = -EADDRNOTAVAIL;
1381
1382         if (!is_valid_ether_addr(addr->sa_data))
1383                 goto out1;
1384
1385         ret = usb_autopm_get_interface(tp->intf);
1386         if (ret < 0)
1387                 goto out1;
1388
1389         mutex_lock(&tp->control);
1390
1391         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1392
1393         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1394         pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1395         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1396
1397         mutex_unlock(&tp->control);
1398
1399         usb_autopm_put_interface(tp->intf);
1400 out1:
1401         return ret;
1402 }
1403
1404 /* Devices containing proper chips can support a persistent
1405  * host system provided MAC address.
1406  * Examples of this are Dell TB15 and Dell WD15 docks
1407  */
1408 static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1409 {
1410         acpi_status status;
1411         struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1412         union acpi_object *obj;
1413         int ret = -EINVAL;
1414         u32 ocp_data;
1415         unsigned char buf[6];
1416         char *mac_obj_name;
1417         acpi_object_type mac_obj_type;
1418         int mac_strlen;
1419
1420         if (test_bit(LENOVO_MACPASSTHRU, &tp->flags)) {
1421                 mac_obj_name = "\\MACA";
1422                 mac_obj_type = ACPI_TYPE_STRING;
1423                 mac_strlen = 0x16;
1424         } else {
1425                 /* test for -AD variant of RTL8153 */
1426                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1427                 if ((ocp_data & AD_MASK) == 0x1000) {
1428                         /* test for MAC address pass-through bit */
1429                         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1430                         if ((ocp_data & PASS_THRU_MASK) != 1) {
1431                                 netif_dbg(tp, probe, tp->netdev,
1432                                                 "No efuse for RTL8153-AD MAC pass through\n");
1433                                 return -ENODEV;
1434                         }
1435                 } else {
1436                         /* test for RTL8153-BND and RTL8153-BD */
1437                         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1438                         if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1439                                 netif_dbg(tp, probe, tp->netdev,
1440                                                 "Invalid variant for MAC pass through\n");
1441                                 return -ENODEV;
1442                         }
1443                 }
1444
1445                 mac_obj_name = "\\_SB.AMAC";
1446                 mac_obj_type = ACPI_TYPE_BUFFER;
1447                 mac_strlen = 0x17;
1448         }
1449
1450         /* returns _AUXMAC_#AABBCCDDEEFF# */
1451         status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer);
1452         obj = (union acpi_object *)buffer.pointer;
1453         if (!ACPI_SUCCESS(status))
1454                 return -ENODEV;
1455         if (obj->type != mac_obj_type || obj->string.length != mac_strlen) {
1456                 netif_warn(tp, probe, tp->netdev,
1457                            "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1458                            obj->type, obj->string.length);
1459                 goto amacout;
1460         }
1461
1462         if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1463             strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1464                 netif_warn(tp, probe, tp->netdev,
1465                            "Invalid header when reading pass-thru MAC addr\n");
1466                 goto amacout;
1467         }
1468         ret = hex2bin(buf, obj->string.pointer + 9, 6);
1469         if (!(ret == 0 && is_valid_ether_addr(buf))) {
1470                 netif_warn(tp, probe, tp->netdev,
1471                            "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1472                            ret, buf);
1473                 ret = -EINVAL;
1474                 goto amacout;
1475         }
1476         memcpy(sa->sa_data, buf, 6);
1477         netif_info(tp, probe, tp->netdev,
1478                    "Using pass-thru MAC addr %pM\n", sa->sa_data);
1479
1480 amacout:
1481         kfree(obj);
1482         return ret;
1483 }
1484
1485 static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
1486 {
1487         struct net_device *dev = tp->netdev;
1488         int ret;
1489
1490         sa->sa_family = dev->type;
1491
1492         if (tp->version == RTL_VER_01) {
1493                 ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
1494         } else {
1495                 /* if device doesn't support MAC pass through this will
1496                  * be expected to be non-zero
1497                  */
1498                 ret = vendor_mac_passthru_addr_read(tp, sa);
1499                 if (ret < 0)
1500                         ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa->sa_data);
1501         }
1502
1503         if (ret < 0) {
1504                 netif_err(tp, probe, dev, "Get ether addr fail\n");
1505         } else if (!is_valid_ether_addr(sa->sa_data)) {
1506                 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1507                           sa->sa_data);
1508                 eth_hw_addr_random(dev);
1509                 ether_addr_copy(sa->sa_data, dev->dev_addr);
1510                 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1511                            sa->sa_data);
1512                 return 0;
1513         }
1514
1515         return ret;
1516 }
1517
1518 static int set_ethernet_addr(struct r8152 *tp)
1519 {
1520         struct net_device *dev = tp->netdev;
1521         struct sockaddr sa;
1522         int ret;
1523
1524         ret = determine_ethernet_addr(tp, &sa);
1525         if (ret < 0)
1526                 return ret;
1527
1528         if (tp->version == RTL_VER_01)
1529                 ether_addr_copy(dev->dev_addr, sa.sa_data);
1530         else
1531                 ret = rtl8152_set_mac_address(dev, &sa);
1532
1533         return ret;
1534 }
1535
1536 static void read_bulk_callback(struct urb *urb)
1537 {
1538         struct net_device *netdev;
1539         int status = urb->status;
1540         struct rx_agg *agg;
1541         struct r8152 *tp;
1542         unsigned long flags;
1543
1544         agg = urb->context;
1545         if (!agg)
1546                 return;
1547
1548         tp = agg->context;
1549         if (!tp)
1550                 return;
1551
1552         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1553                 return;
1554
1555         if (!test_bit(WORK_ENABLE, &tp->flags))
1556                 return;
1557
1558         netdev = tp->netdev;
1559
1560         /* When link down, the driver would cancel all bulks. */
1561         /* This avoid the re-submitting bulk */
1562         if (!netif_carrier_ok(netdev))
1563                 return;
1564
1565         usb_mark_last_busy(tp->udev);
1566
1567         switch (status) {
1568         case 0:
1569                 if (urb->actual_length < ETH_ZLEN)
1570                         break;
1571
1572                 spin_lock_irqsave(&tp->rx_lock, flags);
1573                 list_add_tail(&agg->list, &tp->rx_done);
1574                 spin_unlock_irqrestore(&tp->rx_lock, flags);
1575                 napi_schedule(&tp->napi);
1576                 return;
1577         case -ESHUTDOWN:
1578                 rtl_set_unplug(tp);
1579                 netif_device_detach(tp->netdev);
1580                 return;
1581         case -ENOENT:
1582                 return; /* the urb is in unlink state */
1583         case -ETIME:
1584                 if (net_ratelimit())
1585                         netdev_warn(netdev, "maybe reset is needed?\n");
1586                 break;
1587         default:
1588                 if (net_ratelimit())
1589                         netdev_warn(netdev, "Rx status %d\n", status);
1590                 break;
1591         }
1592
1593         r8152_submit_rx(tp, agg, GFP_ATOMIC);
1594 }
1595
1596 static void write_bulk_callback(struct urb *urb)
1597 {
1598         struct net_device_stats *stats;
1599         struct net_device *netdev;
1600         struct tx_agg *agg;
1601         struct r8152 *tp;
1602         unsigned long flags;
1603         int status = urb->status;
1604
1605         agg = urb->context;
1606         if (!agg)
1607                 return;
1608
1609         tp = agg->context;
1610         if (!tp)
1611                 return;
1612
1613         netdev = tp->netdev;
1614         stats = &netdev->stats;
1615         if (status) {
1616                 if (net_ratelimit())
1617                         netdev_warn(netdev, "Tx status %d\n", status);
1618                 stats->tx_errors += agg->skb_num;
1619         } else {
1620                 stats->tx_packets += agg->skb_num;
1621                 stats->tx_bytes += agg->skb_len;
1622         }
1623
1624         spin_lock_irqsave(&tp->tx_lock, flags);
1625         list_add_tail(&agg->list, &tp->tx_free);
1626         spin_unlock_irqrestore(&tp->tx_lock, flags);
1627
1628         usb_autopm_put_interface_async(tp->intf);
1629
1630         if (!netif_carrier_ok(netdev))
1631                 return;
1632
1633         if (!test_bit(WORK_ENABLE, &tp->flags))
1634                 return;
1635
1636         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1637                 return;
1638
1639         if (!skb_queue_empty(&tp->tx_queue))
1640                 tasklet_schedule(&tp->tx_tl);
1641 }
1642
1643 static void intr_callback(struct urb *urb)
1644 {
1645         struct r8152 *tp;
1646         __le16 *d;
1647         int status = urb->status;
1648         int res;
1649
1650         tp = urb->context;
1651         if (!tp)
1652                 return;
1653
1654         if (!test_bit(WORK_ENABLE, &tp->flags))
1655                 return;
1656
1657         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1658                 return;
1659
1660         switch (status) {
1661         case 0:                 /* success */
1662                 break;
1663         case -ECONNRESET:       /* unlink */
1664         case -ESHUTDOWN:
1665                 netif_device_detach(tp->netdev);
1666                 /* fall through */
1667         case -ENOENT:
1668         case -EPROTO:
1669                 netif_info(tp, intr, tp->netdev,
1670                            "Stop submitting intr, status %d\n", status);
1671                 return;
1672         case -EOVERFLOW:
1673                 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1674                 goto resubmit;
1675         /* -EPIPE:  should clear the halt */
1676         default:
1677                 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1678                 goto resubmit;
1679         }
1680
1681         d = urb->transfer_buffer;
1682         if (INTR_LINK & __le16_to_cpu(d[0])) {
1683                 if (!netif_carrier_ok(tp->netdev)) {
1684                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1685                         schedule_delayed_work(&tp->schedule, 0);
1686                 }
1687         } else {
1688                 if (netif_carrier_ok(tp->netdev)) {
1689                         netif_stop_queue(tp->netdev);
1690                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1691                         schedule_delayed_work(&tp->schedule, 0);
1692                 }
1693         }
1694
1695 resubmit:
1696         res = usb_submit_urb(urb, GFP_ATOMIC);
1697         if (res == -ENODEV) {
1698                 rtl_set_unplug(tp);
1699                 netif_device_detach(tp->netdev);
1700         } else if (res) {
1701                 netif_err(tp, intr, tp->netdev,
1702                           "can't resubmit intr, status %d\n", res);
1703         }
1704 }
1705
1706 static inline void *rx_agg_align(void *data)
1707 {
1708         return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1709 }
1710
1711 static inline void *tx_agg_align(void *data)
1712 {
1713         return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1714 }
1715
1716 static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
1717 {
1718         list_del(&agg->info_list);
1719
1720         usb_free_urb(agg->urb);
1721         put_page(agg->page);
1722         kfree(agg);
1723
1724         atomic_dec(&tp->rx_count);
1725 }
1726
1727 static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
1728 {
1729         struct net_device *netdev = tp->netdev;
1730         int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1731         unsigned int order = get_order(tp->rx_buf_sz);
1732         struct rx_agg *rx_agg;
1733         unsigned long flags;
1734
1735         rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);
1736         if (!rx_agg)
1737                 return NULL;
1738
1739         rx_agg->page = alloc_pages(mflags | __GFP_COMP, order);
1740         if (!rx_agg->page)
1741                 goto free_rx;
1742
1743         rx_agg->buffer = page_address(rx_agg->page);
1744
1745         rx_agg->urb = usb_alloc_urb(0, mflags);
1746         if (!rx_agg->urb)
1747                 goto free_buf;
1748
1749         rx_agg->context = tp;
1750
1751         INIT_LIST_HEAD(&rx_agg->list);
1752         INIT_LIST_HEAD(&rx_agg->info_list);
1753         spin_lock_irqsave(&tp->rx_lock, flags);
1754         list_add_tail(&rx_agg->info_list, &tp->rx_info);
1755         spin_unlock_irqrestore(&tp->rx_lock, flags);
1756
1757         atomic_inc(&tp->rx_count);
1758
1759         return rx_agg;
1760
1761 free_buf:
1762         __free_pages(rx_agg->page, order);
1763 free_rx:
1764         kfree(rx_agg);
1765         return NULL;
1766 }
1767
1768 static void free_all_mem(struct r8152 *tp)
1769 {
1770         struct rx_agg *agg, *agg_next;
1771         unsigned long flags;
1772         int i;
1773
1774         spin_lock_irqsave(&tp->rx_lock, flags);
1775
1776         list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
1777                 free_rx_agg(tp, agg);
1778
1779         spin_unlock_irqrestore(&tp->rx_lock, flags);
1780
1781         WARN_ON(atomic_read(&tp->rx_count));
1782
1783         for (i = 0; i < RTL8152_MAX_TX; i++) {
1784                 usb_free_urb(tp->tx_info[i].urb);
1785                 tp->tx_info[i].urb = NULL;
1786
1787                 kfree(tp->tx_info[i].buffer);
1788                 tp->tx_info[i].buffer = NULL;
1789                 tp->tx_info[i].head = NULL;
1790         }
1791
1792         usb_free_urb(tp->intr_urb);
1793         tp->intr_urb = NULL;
1794
1795         kfree(tp->intr_buff);
1796         tp->intr_buff = NULL;
1797 }
1798
1799 static int alloc_all_mem(struct r8152 *tp)
1800 {
1801         struct net_device *netdev = tp->netdev;
1802         struct usb_interface *intf = tp->intf;
1803         struct usb_host_interface *alt = intf->cur_altsetting;
1804         struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1805         int node, i;
1806
1807         node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1808
1809         spin_lock_init(&tp->rx_lock);
1810         spin_lock_init(&tp->tx_lock);
1811         INIT_LIST_HEAD(&tp->rx_info);
1812         INIT_LIST_HEAD(&tp->tx_free);
1813         INIT_LIST_HEAD(&tp->rx_done);
1814         skb_queue_head_init(&tp->tx_queue);
1815         skb_queue_head_init(&tp->rx_queue);
1816         atomic_set(&tp->rx_count, 0);
1817
1818         for (i = 0; i < RTL8152_MAX_RX; i++) {
1819                 if (!alloc_rx_agg(tp, GFP_KERNEL))
1820                         goto err1;
1821         }
1822
1823         for (i = 0; i < RTL8152_MAX_TX; i++) {
1824                 struct urb *urb;
1825                 u8 *buf;
1826
1827                 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1828                 if (!buf)
1829                         goto err1;
1830
1831                 if (buf != tx_agg_align(buf)) {
1832                         kfree(buf);
1833                         buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1834                                            node);
1835                         if (!buf)
1836                                 goto err1;
1837                 }
1838
1839                 urb = usb_alloc_urb(0, GFP_KERNEL);
1840                 if (!urb) {
1841                         kfree(buf);
1842                         goto err1;
1843                 }
1844
1845                 INIT_LIST_HEAD(&tp->tx_info[i].list);
1846                 tp->tx_info[i].context = tp;
1847                 tp->tx_info[i].urb = urb;
1848                 tp->tx_info[i].buffer = buf;
1849                 tp->tx_info[i].head = tx_agg_align(buf);
1850
1851                 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1852         }
1853
1854         tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1855         if (!tp->intr_urb)
1856                 goto err1;
1857
1858         tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1859         if (!tp->intr_buff)
1860                 goto err1;
1861
1862         tp->intr_interval = (int)ep_intr->desc.bInterval;
1863         usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1864                          tp->intr_buff, INTBUFSIZE, intr_callback,
1865                          tp, tp->intr_interval);
1866
1867         return 0;
1868
1869 err1:
1870         free_all_mem(tp);
1871         return -ENOMEM;
1872 }
1873
1874 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1875 {
1876         struct tx_agg *agg = NULL;
1877         unsigned long flags;
1878
1879         if (list_empty(&tp->tx_free))
1880                 return NULL;
1881
1882         spin_lock_irqsave(&tp->tx_lock, flags);
1883         if (!list_empty(&tp->tx_free)) {
1884                 struct list_head *cursor;
1885
1886                 cursor = tp->tx_free.next;
1887                 list_del_init(cursor);
1888                 agg = list_entry(cursor, struct tx_agg, list);
1889         }
1890         spin_unlock_irqrestore(&tp->tx_lock, flags);
1891
1892         return agg;
1893 }
1894
1895 /* r8152_csum_workaround()
1896  * The hw limits the value of the transport offset. When the offset is out of
1897  * range, calculate the checksum by sw.
1898  */
1899 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1900                                   struct sk_buff_head *list)
1901 {
1902         if (skb_shinfo(skb)->gso_size) {
1903                 netdev_features_t features = tp->netdev->features;
1904                 struct sk_buff_head seg_list;
1905                 struct sk_buff *segs, *nskb;
1906
1907                 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1908                 segs = skb_gso_segment(skb, features);
1909                 if (IS_ERR(segs) || !segs)
1910                         goto drop;
1911
1912                 __skb_queue_head_init(&seg_list);
1913
1914                 do {
1915                         nskb = segs;
1916                         segs = segs->next;
1917                         nskb->next = NULL;
1918                         __skb_queue_tail(&seg_list, nskb);
1919                 } while (segs);
1920
1921                 skb_queue_splice(&seg_list, list);
1922                 dev_kfree_skb(skb);
1923         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1924                 if (skb_checksum_help(skb) < 0)
1925                         goto drop;
1926
1927                 __skb_queue_head(list, skb);
1928         } else {
1929                 struct net_device_stats *stats;
1930
1931 drop:
1932                 stats = &tp->netdev->stats;
1933                 stats->tx_dropped++;
1934                 dev_kfree_skb(skb);
1935         }
1936 }
1937
1938 /* msdn_giant_send_check()
1939  * According to the document of microsoft, the TCP Pseudo Header excludes the
1940  * packet length for IPv6 TCP large packets.
1941  */
1942 static int msdn_giant_send_check(struct sk_buff *skb)
1943 {
1944         const struct ipv6hdr *ipv6h;
1945         struct tcphdr *th;
1946         int ret;
1947
1948         ret = skb_cow_head(skb, 0);
1949         if (ret)
1950                 return ret;
1951
1952         ipv6h = ipv6_hdr(skb);
1953         th = tcp_hdr(skb);
1954
1955         th->check = 0;
1956         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1957
1958         return ret;
1959 }
1960
1961 static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1962 {
1963         if (skb_vlan_tag_present(skb)) {
1964                 u32 opts2;
1965
1966                 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1967                 desc->opts2 |= cpu_to_le32(opts2);
1968         }
1969 }
1970
1971 static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1972 {
1973         u32 opts2 = le32_to_cpu(desc->opts2);
1974
1975         if (opts2 & RX_VLAN_TAG)
1976                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1977                                        swab16(opts2 & 0xffff));
1978 }
1979
1980 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1981                          struct sk_buff *skb, u32 len, u32 transport_offset)
1982 {
1983         u32 mss = skb_shinfo(skb)->gso_size;
1984         u32 opts1, opts2 = 0;
1985         int ret = TX_CSUM_SUCCESS;
1986
1987         WARN_ON_ONCE(len > TX_LEN_MAX);
1988
1989         opts1 = len | TX_FS | TX_LS;
1990
1991         if (mss) {
1992                 if (transport_offset > GTTCPHO_MAX) {
1993                         netif_warn(tp, tx_err, tp->netdev,
1994                                    "Invalid transport offset 0x%x for TSO\n",
1995                                    transport_offset);
1996                         ret = TX_CSUM_TSO;
1997                         goto unavailable;
1998                 }
1999
2000                 switch (vlan_get_protocol(skb)) {
2001                 case htons(ETH_P_IP):
2002                         opts1 |= GTSENDV4;
2003                         break;
2004
2005                 case htons(ETH_P_IPV6):
2006                         if (msdn_giant_send_check(skb)) {
2007                                 ret = TX_CSUM_TSO;
2008                                 goto unavailable;
2009                         }
2010                         opts1 |= GTSENDV6;
2011                         break;
2012
2013                 default:
2014                         WARN_ON_ONCE(1);
2015                         break;
2016                 }
2017
2018                 opts1 |= transport_offset << GTTCPHO_SHIFT;
2019                 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
2020         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2021                 u8 ip_protocol;
2022
2023                 if (transport_offset > TCPHO_MAX) {
2024                         netif_warn(tp, tx_err, tp->netdev,
2025                                    "Invalid transport offset 0x%x\n",
2026                                    transport_offset);
2027                         ret = TX_CSUM_NONE;
2028                         goto unavailable;
2029                 }
2030
2031                 switch (vlan_get_protocol(skb)) {
2032                 case htons(ETH_P_IP):
2033                         opts2 |= IPV4_CS;
2034                         ip_protocol = ip_hdr(skb)->protocol;
2035                         break;
2036
2037                 case htons(ETH_P_IPV6):
2038                         opts2 |= IPV6_CS;
2039                         ip_protocol = ipv6_hdr(skb)->nexthdr;
2040                         break;
2041
2042                 default:
2043                         ip_protocol = IPPROTO_RAW;
2044                         break;
2045                 }
2046
2047                 if (ip_protocol == IPPROTO_TCP)
2048                         opts2 |= TCP_CS;
2049                 else if (ip_protocol == IPPROTO_UDP)
2050                         opts2 |= UDP_CS;
2051                 else
2052                         WARN_ON_ONCE(1);
2053
2054                 opts2 |= transport_offset << TCPHO_SHIFT;
2055         }
2056
2057         desc->opts2 = cpu_to_le32(opts2);
2058         desc->opts1 = cpu_to_le32(opts1);
2059
2060 unavailable:
2061         return ret;
2062 }
2063
2064 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
2065 {
2066         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2067         int remain, ret;
2068         u8 *tx_data;
2069
2070         __skb_queue_head_init(&skb_head);
2071         spin_lock(&tx_queue->lock);
2072         skb_queue_splice_init(tx_queue, &skb_head);
2073         spin_unlock(&tx_queue->lock);
2074
2075         tx_data = agg->head;
2076         agg->skb_num = 0;
2077         agg->skb_len = 0;
2078         remain = agg_buf_sz;
2079
2080         while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
2081                 struct tx_desc *tx_desc;
2082                 struct sk_buff *skb;
2083                 unsigned int len;
2084                 u32 offset;
2085
2086                 skb = __skb_dequeue(&skb_head);
2087                 if (!skb)
2088                         break;
2089
2090                 len = skb->len + sizeof(*tx_desc);
2091
2092                 if (len > remain) {
2093                         __skb_queue_head(&skb_head, skb);
2094                         break;
2095                 }
2096
2097                 tx_data = tx_agg_align(tx_data);
2098                 tx_desc = (struct tx_desc *)tx_data;
2099
2100                 offset = (u32)skb_transport_offset(skb);
2101
2102                 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
2103                         r8152_csum_workaround(tp, skb, &skb_head);
2104                         continue;
2105                 }
2106
2107                 rtl_tx_vlan_tag(tx_desc, skb);
2108
2109                 tx_data += sizeof(*tx_desc);
2110
2111                 len = skb->len;
2112                 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
2113                         struct net_device_stats *stats = &tp->netdev->stats;
2114
2115                         stats->tx_dropped++;
2116                         dev_kfree_skb_any(skb);
2117                         tx_data -= sizeof(*tx_desc);
2118                         continue;
2119                 }
2120
2121                 tx_data += len;
2122                 agg->skb_len += len;
2123                 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
2124
2125                 dev_kfree_skb_any(skb);
2126
2127                 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
2128
2129                 if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
2130                         break;
2131         }
2132
2133         if (!skb_queue_empty(&skb_head)) {
2134                 spin_lock(&tx_queue->lock);
2135                 skb_queue_splice(&skb_head, tx_queue);
2136                 spin_unlock(&tx_queue->lock);
2137         }
2138
2139         netif_tx_lock(tp->netdev);
2140
2141         if (netif_queue_stopped(tp->netdev) &&
2142             skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
2143                 netif_wake_queue(tp->netdev);
2144
2145         netif_tx_unlock(tp->netdev);
2146
2147         ret = usb_autopm_get_interface_async(tp->intf);
2148         if (ret < 0)
2149                 goto out_tx_fill;
2150
2151         usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
2152                           agg->head, (int)(tx_data - (u8 *)agg->head),
2153                           (usb_complete_t)write_bulk_callback, agg);
2154
2155         ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
2156         if (ret < 0)
2157                 usb_autopm_put_interface_async(tp->intf);
2158
2159 out_tx_fill:
2160         return ret;
2161 }
2162
2163 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
2164 {
2165         u8 checksum = CHECKSUM_NONE;
2166         u32 opts2, opts3;
2167
2168         if (!(tp->netdev->features & NETIF_F_RXCSUM))
2169                 goto return_result;
2170
2171         opts2 = le32_to_cpu(rx_desc->opts2);
2172         opts3 = le32_to_cpu(rx_desc->opts3);
2173
2174         if (opts2 & RD_IPV4_CS) {
2175                 if (opts3 & IPF)
2176                         checksum = CHECKSUM_NONE;
2177                 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2178                         checksum = CHECKSUM_UNNECESSARY;
2179                 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2180                         checksum = CHECKSUM_UNNECESSARY;
2181         } else if (opts2 & RD_IPV6_CS) {
2182                 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2183                         checksum = CHECKSUM_UNNECESSARY;
2184                 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2185                         checksum = CHECKSUM_UNNECESSARY;
2186         }
2187
2188 return_result:
2189         return checksum;
2190 }
2191
2192 static inline bool rx_count_exceed(struct r8152 *tp)
2193 {
2194         return atomic_read(&tp->rx_count) > RTL8152_MAX_RX;
2195 }
2196
2197 static inline int agg_offset(struct rx_agg *agg, void *addr)
2198 {
2199         return (int)(addr - agg->buffer);
2200 }
2201
2202 static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
2203 {
2204         struct rx_agg *agg, *agg_next, *agg_free = NULL;
2205         unsigned long flags;
2206
2207         spin_lock_irqsave(&tp->rx_lock, flags);
2208
2209         list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
2210                 if (page_count(agg->page) == 1) {
2211                         if (!agg_free) {
2212                                 list_del_init(&agg->list);
2213                                 agg_free = agg;
2214                                 continue;
2215                         }
2216                         if (rx_count_exceed(tp)) {
2217                                 list_del_init(&agg->list);
2218                                 free_rx_agg(tp, agg);
2219                         }
2220                         break;
2221                 }
2222         }
2223
2224         spin_unlock_irqrestore(&tp->rx_lock, flags);
2225
2226         if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending)
2227                 agg_free = alloc_rx_agg(tp, mflags);
2228
2229         return agg_free;
2230 }
2231
2232 static int rx_bottom(struct r8152 *tp, int budget)
2233 {
2234         unsigned long flags;
2235         struct list_head *cursor, *next, rx_queue;
2236         int ret = 0, work_done = 0;
2237         struct napi_struct *napi = &tp->napi;
2238
2239         if (!skb_queue_empty(&tp->rx_queue)) {
2240                 while (work_done < budget) {
2241                         struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
2242                         struct net_device *netdev = tp->netdev;
2243                         struct net_device_stats *stats = &netdev->stats;
2244                         unsigned int pkt_len;
2245
2246                         if (!skb)
2247                                 break;
2248
2249                         pkt_len = skb->len;
2250                         napi_gro_receive(napi, skb);
2251                         work_done++;
2252                         stats->rx_packets++;
2253                         stats->rx_bytes += pkt_len;
2254                 }
2255         }
2256
2257         if (list_empty(&tp->rx_done))
2258                 goto out1;
2259
2260         INIT_LIST_HEAD(&rx_queue);
2261         spin_lock_irqsave(&tp->rx_lock, flags);
2262         list_splice_init(&tp->rx_done, &rx_queue);
2263         spin_unlock_irqrestore(&tp->rx_lock, flags);
2264
2265         list_for_each_safe(cursor, next, &rx_queue) {
2266                 struct rx_desc *rx_desc;
2267                 struct rx_agg *agg, *agg_free;
2268                 int len_used = 0;
2269                 struct urb *urb;
2270                 u8 *rx_data;
2271
2272                 list_del_init(cursor);
2273
2274                 agg = list_entry(cursor, struct rx_agg, list);
2275                 urb = agg->urb;
2276                 if (urb->actual_length < ETH_ZLEN)
2277                         goto submit;
2278
2279                 agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
2280
2281                 rx_desc = agg->buffer;
2282                 rx_data = agg->buffer;
2283                 len_used += sizeof(struct rx_desc);
2284
2285                 while (urb->actual_length > len_used) {
2286                         struct net_device *netdev = tp->netdev;
2287                         struct net_device_stats *stats = &netdev->stats;
2288                         unsigned int pkt_len, rx_frag_head_sz;
2289                         struct sk_buff *skb;
2290
2291                         /* limite the skb numbers for rx_queue */
2292                         if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
2293                                 break;
2294
2295                         pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
2296                         if (pkt_len < ETH_ZLEN)
2297                                 break;
2298
2299                         len_used += pkt_len;
2300                         if (urb->actual_length < len_used)
2301                                 break;
2302
2303                         pkt_len -= ETH_FCS_LEN;
2304                         rx_data += sizeof(struct rx_desc);
2305
2306                         if (!agg_free || tp->rx_copybreak > pkt_len)
2307                                 rx_frag_head_sz = pkt_len;
2308                         else
2309                                 rx_frag_head_sz = tp->rx_copybreak;
2310
2311                         skb = napi_alloc_skb(napi, rx_frag_head_sz);
2312                         if (!skb) {
2313                                 stats->rx_dropped++;
2314                                 goto find_next_rx;
2315                         }
2316
2317                         skb->ip_summed = r8152_rx_csum(tp, rx_desc);
2318                         memcpy(skb->data, rx_data, rx_frag_head_sz);
2319                         skb_put(skb, rx_frag_head_sz);
2320                         pkt_len -= rx_frag_head_sz;
2321                         rx_data += rx_frag_head_sz;
2322                         if (pkt_len) {
2323                                 skb_add_rx_frag(skb, 0, agg->page,
2324                                                 agg_offset(agg, rx_data),
2325                                                 pkt_len,
2326                                                 SKB_DATA_ALIGN(pkt_len));
2327                                 get_page(agg->page);
2328                         }
2329
2330                         skb->protocol = eth_type_trans(skb, netdev);
2331                         rtl_rx_vlan_tag(rx_desc, skb);
2332                         if (work_done < budget) {
2333                                 work_done++;
2334                                 stats->rx_packets++;
2335                                 stats->rx_bytes += skb->len;
2336                                 napi_gro_receive(napi, skb);
2337                         } else {
2338                                 __skb_queue_tail(&tp->rx_queue, skb);
2339                         }
2340
2341 find_next_rx:
2342                         rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
2343                         rx_desc = (struct rx_desc *)rx_data;
2344                         len_used = agg_offset(agg, rx_data);
2345                         len_used += sizeof(struct rx_desc);
2346                 }
2347
2348                 WARN_ON(!agg_free && page_count(agg->page) > 1);
2349
2350                 if (agg_free) {
2351                         spin_lock_irqsave(&tp->rx_lock, flags);
2352                         if (page_count(agg->page) == 1) {
2353                                 list_add(&agg_free->list, &tp->rx_used);
2354                         } else {
2355                                 list_add_tail(&agg->list, &tp->rx_used);
2356                                 agg = agg_free;
2357                                 urb = agg->urb;
2358                         }
2359                         spin_unlock_irqrestore(&tp->rx_lock, flags);
2360                 }
2361
2362 submit:
2363                 if (!ret) {
2364                         ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
2365                 } else {
2366                         urb->actual_length = 0;
2367                         list_add_tail(&agg->list, next);
2368                 }
2369         }
2370
2371         if (!list_empty(&rx_queue)) {
2372                 spin_lock_irqsave(&tp->rx_lock, flags);
2373                 list_splice_tail(&rx_queue, &tp->rx_done);
2374                 spin_unlock_irqrestore(&tp->rx_lock, flags);
2375         }
2376
2377 out1:
2378         return work_done;
2379 }
2380
2381 static void tx_bottom(struct r8152 *tp)
2382 {
2383         int res;
2384
2385         do {
2386                 struct net_device *netdev = tp->netdev;
2387                 struct tx_agg *agg;
2388
2389                 if (skb_queue_empty(&tp->tx_queue))
2390                         break;
2391
2392                 agg = r8152_get_tx_agg(tp);
2393                 if (!agg)
2394                         break;
2395
2396                 res = r8152_tx_agg_fill(tp, agg);
2397                 if (!res)
2398                         continue;
2399
2400                 if (res == -ENODEV) {
2401                         rtl_set_unplug(tp);
2402                         netif_device_detach(netdev);
2403                 } else {
2404                         struct net_device_stats *stats = &netdev->stats;
2405                         unsigned long flags;
2406
2407                         netif_warn(tp, tx_err, netdev,
2408                                    "failed tx_urb %d\n", res);
2409                         stats->tx_dropped += agg->skb_num;
2410
2411                         spin_lock_irqsave(&tp->tx_lock, flags);
2412                         list_add_tail(&agg->list, &tp->tx_free);
2413                         spin_unlock_irqrestore(&tp->tx_lock, flags);
2414                 }
2415         } while (res == 0);
2416 }
2417
2418 static void bottom_half(unsigned long data)
2419 {
2420         struct r8152 *tp;
2421
2422         tp = (struct r8152 *)data;
2423
2424         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2425                 return;
2426
2427         if (!test_bit(WORK_ENABLE, &tp->flags))
2428                 return;
2429
2430         /* When link down, the driver would cancel all bulks. */
2431         /* This avoid the re-submitting bulk */
2432         if (!netif_carrier_ok(tp->netdev))
2433                 return;
2434
2435         clear_bit(SCHEDULE_TASKLET, &tp->flags);
2436
2437         tx_bottom(tp);
2438 }
2439
2440 static int r8152_poll(struct napi_struct *napi, int budget)
2441 {
2442         struct r8152 *tp = container_of(napi, struct r8152, napi);
2443         int work_done;
2444
2445         work_done = rx_bottom(tp, budget);
2446
2447         if (work_done < budget) {
2448                 if (!napi_complete_done(napi, work_done))
2449                         goto out;
2450                 if (!list_empty(&tp->rx_done))
2451                         napi_schedule(napi);
2452         }
2453
2454 out:
2455         return work_done;
2456 }
2457
2458 static
2459 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2460 {
2461         int ret;
2462
2463         /* The rx would be stopped, so skip submitting */
2464         if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2465             !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2466                 return 0;
2467
2468         usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
2469                           agg->buffer, tp->rx_buf_sz,
2470                           (usb_complete_t)read_bulk_callback, agg);
2471
2472         ret = usb_submit_urb(agg->urb, mem_flags);
2473         if (ret == -ENODEV) {
2474                 rtl_set_unplug(tp);
2475                 netif_device_detach(tp->netdev);
2476         } else if (ret) {
2477                 struct urb *urb = agg->urb;
2478                 unsigned long flags;
2479
2480                 urb->actual_length = 0;
2481                 spin_lock_irqsave(&tp->rx_lock, flags);
2482                 list_add_tail(&agg->list, &tp->rx_done);
2483                 spin_unlock_irqrestore(&tp->rx_lock, flags);
2484
2485                 netif_err(tp, rx_err, tp->netdev,
2486                           "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2487
2488                 napi_schedule(&tp->napi);
2489         }
2490
2491         return ret;
2492 }
2493
2494 static void rtl_drop_queued_tx(struct r8152 *tp)
2495 {
2496         struct net_device_stats *stats = &tp->netdev->stats;
2497         struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2498         struct sk_buff *skb;
2499
2500         if (skb_queue_empty(tx_queue))
2501                 return;
2502
2503         __skb_queue_head_init(&skb_head);
2504         spin_lock_bh(&tx_queue->lock);
2505         skb_queue_splice_init(tx_queue, &skb_head);
2506         spin_unlock_bh(&tx_queue->lock);
2507
2508         while ((skb = __skb_dequeue(&skb_head))) {
2509                 dev_kfree_skb(skb);
2510                 stats->tx_dropped++;
2511         }
2512 }
2513
2514 static void rtl8152_tx_timeout(struct net_device *netdev)
2515 {
2516         struct r8152 *tp = netdev_priv(netdev);
2517
2518         netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2519
2520         usb_queue_reset_device(tp->intf);
2521 }
2522
2523 static void rtl8152_set_rx_mode(struct net_device *netdev)
2524 {
2525         struct r8152 *tp = netdev_priv(netdev);
2526
2527         if (netif_carrier_ok(netdev)) {
2528                 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2529                 schedule_delayed_work(&tp->schedule, 0);
2530         }
2531 }
2532
2533 static void _rtl8152_set_rx_mode(struct net_device *netdev)
2534 {
2535         struct r8152 *tp = netdev_priv(netdev);
2536         u32 mc_filter[2];       /* Multicast hash filter */
2537         __le32 tmp[2];
2538         u32 ocp_data;
2539
2540         netif_stop_queue(netdev);
2541         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2542         ocp_data &= ~RCR_ACPT_ALL;
2543         ocp_data |= RCR_AB | RCR_APM;
2544
2545         if (netdev->flags & IFF_PROMISC) {
2546                 /* Unconditionally log net taps. */
2547                 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2548                 ocp_data |= RCR_AM | RCR_AAP;
2549                 mc_filter[1] = 0xffffffff;
2550                 mc_filter[0] = 0xffffffff;
2551         } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2552                    (netdev->flags & IFF_ALLMULTI)) {
2553                 /* Too many to filter perfectly -- accept all multicasts. */
2554                 ocp_data |= RCR_AM;
2555                 mc_filter[1] = 0xffffffff;
2556                 mc_filter[0] = 0xffffffff;
2557         } else {
2558                 struct netdev_hw_addr *ha;
2559
2560                 mc_filter[1] = 0;
2561                 mc_filter[0] = 0;
2562                 netdev_for_each_mc_addr(ha, netdev) {
2563                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2564
2565                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2566                         ocp_data |= RCR_AM;
2567                 }
2568         }
2569
2570         tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2571         tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2572
2573         pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2574         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2575         netif_wake_queue(netdev);
2576 }
2577
2578 static netdev_features_t
2579 rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2580                        netdev_features_t features)
2581 {
2582         u32 mss = skb_shinfo(skb)->gso_size;
2583         int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2584         int offset = skb_transport_offset(skb);
2585
2586         if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2587                 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2588         else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2589                 features &= ~NETIF_F_GSO_MASK;
2590
2591         return features;
2592 }
2593
2594 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2595                                       struct net_device *netdev)
2596 {
2597         struct r8152 *tp = netdev_priv(netdev);
2598
2599         skb_tx_timestamp(skb);
2600
2601         skb_queue_tail(&tp->tx_queue, skb);
2602
2603         if (!list_empty(&tp->tx_free)) {
2604                 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2605                         set_bit(SCHEDULE_TASKLET, &tp->flags);
2606                         schedule_delayed_work(&tp->schedule, 0);
2607                 } else {
2608                         usb_mark_last_busy(tp->udev);
2609                         tasklet_schedule(&tp->tx_tl);
2610                 }
2611         } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2612                 netif_stop_queue(netdev);
2613         }
2614
2615         return NETDEV_TX_OK;
2616 }
2617
2618 static void r8152b_reset_packet_filter(struct r8152 *tp)
2619 {
2620         u32     ocp_data;
2621
2622         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2623         ocp_data &= ~FMC_FCR_MCU_EN;
2624         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2625         ocp_data |= FMC_FCR_MCU_EN;
2626         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2627 }
2628
2629 static void rtl8152_nic_reset(struct r8152 *tp)
2630 {
2631         int     i;
2632
2633         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2634
2635         for (i = 0; i < 1000; i++) {
2636                 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2637                         break;
2638                 usleep_range(100, 400);
2639         }
2640 }
2641
2642 static void set_tx_qlen(struct r8152 *tp)
2643 {
2644         struct net_device *netdev = tp->netdev;
2645
2646         tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
2647                                     sizeof(struct tx_desc));
2648 }
2649
2650 static inline u8 rtl8152_get_speed(struct r8152 *tp)
2651 {
2652         return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2653 }
2654
2655 static void rtl_set_eee_plus(struct r8152 *tp)
2656 {
2657         u32 ocp_data;
2658         u8 speed;
2659
2660         speed = rtl8152_get_speed(tp);
2661         if (speed & _10bps) {
2662                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2663                 ocp_data |= EEEP_CR_EEEP_TX;
2664                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2665         } else {
2666                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2667                 ocp_data &= ~EEEP_CR_EEEP_TX;
2668                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2669         }
2670 }
2671
2672 static void rxdy_gated_en(struct r8152 *tp, bool enable)
2673 {
2674         u32 ocp_data;
2675
2676         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2677         if (enable)
2678                 ocp_data |= RXDY_GATED_EN;
2679         else
2680                 ocp_data &= ~RXDY_GATED_EN;
2681         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2682 }
2683
2684 static int rtl_start_rx(struct r8152 *tp)
2685 {
2686         struct rx_agg *agg, *agg_next;
2687         struct list_head tmp_list;
2688         unsigned long flags;
2689         int ret = 0, i = 0;
2690
2691         INIT_LIST_HEAD(&tmp_list);
2692
2693         spin_lock_irqsave(&tp->rx_lock, flags);
2694
2695         INIT_LIST_HEAD(&tp->rx_done);
2696         INIT_LIST_HEAD(&tp->rx_used);
2697
2698         list_splice_init(&tp->rx_info, &tmp_list);
2699
2700         spin_unlock_irqrestore(&tp->rx_lock, flags);
2701
2702         list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2703                 INIT_LIST_HEAD(&agg->list);
2704
2705                 /* Only RTL8152_MAX_RX rx_agg need to be submitted. */
2706                 if (++i > RTL8152_MAX_RX) {
2707                         spin_lock_irqsave(&tp->rx_lock, flags);
2708                         list_add_tail(&agg->list, &tp->rx_used);
2709                         spin_unlock_irqrestore(&tp->rx_lock, flags);
2710                 } else if (unlikely(ret < 0)) {
2711                         spin_lock_irqsave(&tp->rx_lock, flags);
2712                         list_add_tail(&agg->list, &tp->rx_done);
2713                         spin_unlock_irqrestore(&tp->rx_lock, flags);
2714                 } else {
2715                         ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
2716                 }
2717         }
2718
2719         spin_lock_irqsave(&tp->rx_lock, flags);
2720         WARN_ON(!list_empty(&tp->rx_info));
2721         list_splice(&tmp_list, &tp->rx_info);
2722         spin_unlock_irqrestore(&tp->rx_lock, flags);
2723
2724         return ret;
2725 }
2726
2727 static int rtl_stop_rx(struct r8152 *tp)
2728 {
2729         struct rx_agg *agg, *agg_next;
2730         struct list_head tmp_list;
2731         unsigned long flags;
2732
2733         INIT_LIST_HEAD(&tmp_list);
2734
2735         /* The usb_kill_urb() couldn't be used in atomic.
2736          * Therefore, move the list of rx_info to a tmp one.
2737          * Then, list_for_each_entry_safe could be used without
2738          * spin lock.
2739          */
2740
2741         spin_lock_irqsave(&tp->rx_lock, flags);
2742         list_splice_init(&tp->rx_info, &tmp_list);
2743         spin_unlock_irqrestore(&tp->rx_lock, flags);
2744
2745         list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2746                 /* At least RTL8152_MAX_RX rx_agg have the page_count being
2747                  * equal to 1, so the other ones could be freed safely.
2748                  */
2749                 if (page_count(agg->page) > 1)
2750                         free_rx_agg(tp, agg);
2751                 else
2752                         usb_kill_urb(agg->urb);
2753         }
2754
2755         /* Move back the list of temp to the rx_info */
2756         spin_lock_irqsave(&tp->rx_lock, flags);
2757         WARN_ON(!list_empty(&tp->rx_info));
2758         list_splice(&tmp_list, &tp->rx_info);
2759         spin_unlock_irqrestore(&tp->rx_lock, flags);
2760
2761         while (!skb_queue_empty(&tp->rx_queue))
2762                 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2763
2764         return 0;
2765 }
2766
2767 static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2768 {
2769         ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2770                        OWN_UPDATE | OWN_CLEAR);
2771 }
2772
2773 static int rtl_enable(struct r8152 *tp)
2774 {
2775         u32 ocp_data;
2776
2777         r8152b_reset_packet_filter(tp);
2778
2779         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2780         ocp_data |= CR_RE | CR_TE;
2781         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2782
2783         switch (tp->version) {
2784         case RTL_VER_08:
2785         case RTL_VER_09:
2786                 r8153b_rx_agg_chg_indicate(tp);
2787                 break;
2788         default:
2789                 break;
2790         }
2791
2792         rxdy_gated_en(tp, false);
2793
2794         return 0;
2795 }
2796
2797 static int rtl8152_enable(struct r8152 *tp)
2798 {
2799         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2800                 return -ENODEV;
2801
2802         set_tx_qlen(tp);
2803         rtl_set_eee_plus(tp);
2804
2805         return rtl_enable(tp);
2806 }
2807
2808 static void r8153_set_rx_early_timeout(struct r8152 *tp)
2809 {
2810         u32 ocp_data = tp->coalesce / 8;
2811
2812         switch (tp->version) {
2813         case RTL_VER_03:
2814         case RTL_VER_04:
2815         case RTL_VER_05:
2816         case RTL_VER_06:
2817                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2818                                ocp_data);
2819                 break;
2820
2821         case RTL_VER_08:
2822         case RTL_VER_09:
2823                 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
2824                  * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
2825                  */
2826                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2827                                128 / 8);
2828                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
2829                                ocp_data);
2830                 break;
2831
2832         default:
2833                 break;
2834         }
2835 }
2836
2837 static void r8153_set_rx_early_size(struct r8152 *tp)
2838 {
2839         u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
2840
2841         switch (tp->version) {
2842         case RTL_VER_03:
2843         case RTL_VER_04:
2844         case RTL_VER_05:
2845         case RTL_VER_06:
2846                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2847                                ocp_data / 4);
2848                 break;
2849         case RTL_VER_08:
2850         case RTL_VER_09:
2851                 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2852                                ocp_data / 8);
2853                 break;
2854         default:
2855                 WARN_ON_ONCE(1);
2856                 break;
2857         }
2858 }
2859
2860 static int rtl8153_enable(struct r8152 *tp)
2861 {
2862         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2863                 return -ENODEV;
2864
2865         set_tx_qlen(tp);
2866         rtl_set_eee_plus(tp);
2867         r8153_set_rx_early_timeout(tp);
2868         r8153_set_rx_early_size(tp);
2869
2870         if (tp->version == RTL_VER_09) {
2871                 u32 ocp_data;
2872
2873                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
2874                 ocp_data &= ~FC_PATCH_TASK;
2875                 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
2876                 usleep_range(1000, 2000);
2877                 ocp_data |= FC_PATCH_TASK;
2878                 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
2879         }
2880
2881         return rtl_enable(tp);
2882 }
2883
2884 static void rtl_disable(struct r8152 *tp)
2885 {
2886         u32 ocp_data;
2887         int i;
2888
2889         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2890                 rtl_drop_queued_tx(tp);
2891                 return;
2892         }
2893
2894         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2895         ocp_data &= ~RCR_ACPT_ALL;
2896         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2897
2898         rtl_drop_queued_tx(tp);
2899
2900         for (i = 0; i < RTL8152_MAX_TX; i++)
2901                 usb_kill_urb(tp->tx_info[i].urb);
2902
2903         rxdy_gated_en(tp, true);
2904
2905         for (i = 0; i < 1000; i++) {
2906                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2907                 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2908                         break;
2909                 usleep_range(1000, 2000);
2910         }
2911
2912         for (i = 0; i < 1000; i++) {
2913                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2914                         break;
2915                 usleep_range(1000, 2000);
2916         }
2917
2918         rtl_stop_rx(tp);
2919
2920         rtl8152_nic_reset(tp);
2921 }
2922
2923 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2924 {
2925         u32 ocp_data;
2926
2927         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2928         if (enable)
2929                 ocp_data |= POWER_CUT;
2930         else
2931                 ocp_data &= ~POWER_CUT;
2932         ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2933
2934         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2935         ocp_data &= ~RESUME_INDICATE;
2936         ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2937 }
2938
2939 static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2940 {
2941         u32 ocp_data;
2942
2943         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2944         if (enable)
2945                 ocp_data |= CPCR_RX_VLAN;
2946         else
2947                 ocp_data &= ~CPCR_RX_VLAN;
2948         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2949 }
2950
2951 static int rtl8152_set_features(struct net_device *dev,
2952                                 netdev_features_t features)
2953 {
2954         netdev_features_t changed = features ^ dev->features;
2955         struct r8152 *tp = netdev_priv(dev);
2956         int ret;
2957
2958         ret = usb_autopm_get_interface(tp->intf);
2959         if (ret < 0)
2960                 goto out;
2961
2962         mutex_lock(&tp->control);
2963
2964         if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2965                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2966                         rtl_rx_vlan_en(tp, true);
2967                 else
2968                         rtl_rx_vlan_en(tp, false);
2969         }
2970
2971         mutex_unlock(&tp->control);
2972
2973         usb_autopm_put_interface(tp->intf);
2974
2975 out:
2976         return ret;
2977 }
2978
2979 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2980
2981 static u32 __rtl_get_wol(struct r8152 *tp)
2982 {
2983         u32 ocp_data;
2984         u32 wolopts = 0;
2985
2986         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2987         if (ocp_data & LINK_ON_WAKE_EN)
2988                 wolopts |= WAKE_PHY;
2989
2990         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2991         if (ocp_data & UWF_EN)
2992                 wolopts |= WAKE_UCAST;
2993         if (ocp_data & BWF_EN)
2994                 wolopts |= WAKE_BCAST;
2995         if (ocp_data & MWF_EN)
2996                 wolopts |= WAKE_MCAST;
2997
2998         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2999         if (ocp_data & MAGIC_EN)
3000                 wolopts |= WAKE_MAGIC;
3001
3002         return wolopts;
3003 }
3004
3005 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
3006 {
3007         u32 ocp_data;
3008
3009         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3010
3011         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3012         ocp_data &= ~LINK_ON_WAKE_EN;
3013         if (wolopts & WAKE_PHY)
3014                 ocp_data |= LINK_ON_WAKE_EN;
3015         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3016
3017         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3018         ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
3019         if (wolopts & WAKE_UCAST)
3020                 ocp_data |= UWF_EN;
3021         if (wolopts & WAKE_BCAST)
3022                 ocp_data |= BWF_EN;
3023         if (wolopts & WAKE_MCAST)
3024                 ocp_data |= MWF_EN;
3025         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
3026
3027         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3028
3029         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3030         ocp_data &= ~MAGIC_EN;
3031         if (wolopts & WAKE_MAGIC)
3032                 ocp_data |= MAGIC_EN;
3033         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
3034
3035         if (wolopts & WAKE_ANY)
3036                 device_set_wakeup_enable(&tp->udev->dev, true);
3037         else
3038                 device_set_wakeup_enable(&tp->udev->dev, false);
3039 }
3040
3041 static void r8153_mac_clk_spd(struct r8152 *tp, bool enable)
3042 {
3043         /* MAC clock speed down */
3044         if (enable) {
3045                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
3046                                ALDPS_SPDWN_RATIO);
3047                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2,
3048                                EEE_SPDWN_RATIO);
3049                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3050                                PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3051                                U1U2_SPDWN_EN | L1_SPDWN_EN);
3052                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3053                                PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3054                                TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN |
3055                                TP1000_SPDWN_EN);
3056         } else {
3057                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
3058                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
3059                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
3060                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
3061         }
3062 }
3063
3064 static void r8153_u1u2en(struct r8152 *tp, bool enable)
3065 {
3066         u8 u1u2[8];
3067
3068         if (enable)
3069                 memset(u1u2, 0xff, sizeof(u1u2));
3070         else
3071                 memset(u1u2, 0x00, sizeof(u1u2));
3072
3073         usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
3074 }
3075
3076 static void r8153b_u1u2en(struct r8152 *tp, bool enable)
3077 {
3078         u32 ocp_data;
3079
3080         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
3081         if (enable)
3082                 ocp_data |= LPM_U1U2_EN;
3083         else
3084                 ocp_data &= ~LPM_U1U2_EN;
3085
3086         ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
3087 }
3088
3089 static void r8153_u2p3en(struct r8152 *tp, bool enable)
3090 {
3091         u32 ocp_data;
3092
3093         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
3094         if (enable)
3095                 ocp_data |= U2P3_ENABLE;
3096         else
3097                 ocp_data &= ~U2P3_ENABLE;
3098         ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
3099 }
3100
3101 static void r8153b_ups_flags(struct r8152 *tp)
3102 {
3103         u32 ups_flags = 0;
3104
3105         if (tp->ups_info.green)
3106                 ups_flags |= UPS_FLAGS_EN_GREEN;
3107
3108         if (tp->ups_info.aldps)
3109                 ups_flags |= UPS_FLAGS_EN_ALDPS;
3110
3111         if (tp->ups_info.eee)
3112                 ups_flags |= UPS_FLAGS_EN_EEE;
3113
3114         if (tp->ups_info.flow_control)
3115                 ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3116
3117         if (tp->ups_info.eee_ckdiv)
3118                 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3119
3120         if (tp->ups_info.eee_cmod_lv)
3121                 ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
3122
3123         if (tp->ups_info._10m_ckdiv)
3124                 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3125
3126         if (tp->ups_info.eee_plloff_100)
3127                 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3128
3129         if (tp->ups_info.eee_plloff_giga)
3130                 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3131
3132         if (tp->ups_info._250m_ckdiv)
3133                 ups_flags |= UPS_FLAGS_250M_CKDIV;
3134
3135         if (tp->ups_info.ctap_short_off)
3136                 ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
3137
3138         switch (tp->ups_info.speed_duplex) {
3139         case NWAY_10M_HALF:
3140                 ups_flags |= ups_flags_speed(1);
3141                 break;
3142         case NWAY_10M_FULL:
3143                 ups_flags |= ups_flags_speed(2);
3144                 break;
3145         case NWAY_100M_HALF:
3146                 ups_flags |= ups_flags_speed(3);
3147                 break;
3148         case NWAY_100M_FULL:
3149                 ups_flags |= ups_flags_speed(4);
3150                 break;
3151         case NWAY_1000M_FULL:
3152                 ups_flags |= ups_flags_speed(5);
3153                 break;
3154         case FORCE_10M_HALF:
3155                 ups_flags |= ups_flags_speed(6);
3156                 break;
3157         case FORCE_10M_FULL:
3158                 ups_flags |= ups_flags_speed(7);
3159                 break;
3160         case FORCE_100M_HALF:
3161                 ups_flags |= ups_flags_speed(8);
3162                 break;
3163         case FORCE_100M_FULL:
3164                 ups_flags |= ups_flags_speed(9);
3165                 break;
3166         default:
3167                 break;
3168         }
3169
3170         ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3171 }
3172
3173 static void r8153b_green_en(struct r8152 *tp, bool enable)
3174 {
3175         u16 data;
3176
3177         if (enable) {
3178                 sram_write(tp, 0x8045, 0);      /* 10M abiq&ldvbias */
3179                 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
3180                 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
3181         } else {
3182                 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
3183                 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
3184                 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
3185         }
3186
3187         data = sram_read(tp, SRAM_GREEN_CFG);
3188         data |= GREEN_ETH_EN;
3189         sram_write(tp, SRAM_GREEN_CFG, data);
3190
3191         tp->ups_info.green = enable;
3192 }
3193
3194 static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
3195 {
3196         u16 data;
3197         int i;
3198
3199         for (i = 0; i < 500; i++) {
3200                 data = ocp_reg_read(tp, OCP_PHY_STATUS);
3201                 data &= PHY_STAT_MASK;
3202                 if (desired) {
3203                         if (data == desired)
3204                                 break;
3205                 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
3206                            data == PHY_STAT_EXT_INIT) {
3207                         break;
3208                 }
3209
3210                 msleep(20);
3211         }
3212
3213         return data;
3214 }
3215
3216 static void r8153b_ups_en(struct r8152 *tp, bool enable)
3217 {
3218         u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3219
3220         if (enable) {
3221                 r8153b_ups_flags(tp);
3222
3223                 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3224                 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3225
3226                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
3227                 ocp_data |= BIT(0);
3228                 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
3229         } else {
3230                 u16 data;
3231
3232                 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3233                 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3234
3235                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
3236                 ocp_data &= ~BIT(0);
3237                 ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
3238
3239                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3240                 ocp_data &= ~PCUT_STATUS;
3241                 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3242
3243                 data = r8153_phy_status(tp, 0);
3244
3245                 switch (data) {
3246                 case PHY_STAT_PWRDN:
3247                 case PHY_STAT_EXT_INIT:
3248                         r8153b_green_en(tp,
3249                                         test_bit(GREEN_ETHERNET, &tp->flags));
3250
3251                         data = r8152_mdio_read(tp, MII_BMCR);
3252                         data &= ~BMCR_PDOWN;
3253                         data |= BMCR_RESET;
3254                         r8152_mdio_write(tp, MII_BMCR, data);
3255
3256                         data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
3257                         /* fall through */
3258
3259                 default:
3260                         if (data != PHY_STAT_LAN_ON)
3261                                 netif_warn(tp, link, tp->netdev,
3262                                            "PHY not ready");
3263                         break;
3264                 }
3265         }
3266 }
3267
3268 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
3269 {
3270         u32 ocp_data;
3271
3272         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3273         if (enable)
3274                 ocp_data |= PWR_EN | PHASE2_EN;
3275         else
3276                 ocp_data &= ~(PWR_EN | PHASE2_EN);
3277         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3278
3279         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3280         ocp_data &= ~PCUT_STATUS;
3281         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3282 }
3283
3284 static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
3285 {
3286         u32 ocp_data;
3287
3288         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3289         if (enable)
3290                 ocp_data |= PWR_EN | PHASE2_EN;
3291         else
3292                 ocp_data &= ~PWR_EN;
3293         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3294
3295         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3296         ocp_data &= ~PCUT_STATUS;
3297         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3298 }
3299
3300 static void r8153_queue_wake(struct r8152 *tp, bool enable)
3301 {
3302         u32 ocp_data;
3303
3304         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
3305         if (enable)
3306                 ocp_data |= UPCOMING_RUNTIME_D3;
3307         else
3308                 ocp_data &= ~UPCOMING_RUNTIME_D3;
3309         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
3310
3311         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
3312         ocp_data &= ~LINK_CHG_EVENT;
3313         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
3314
3315         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
3316         ocp_data &= ~LINK_CHANGE_FLAG;
3317         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
3318 }
3319
3320 static bool rtl_can_wakeup(struct r8152 *tp)
3321 {
3322         struct usb_device *udev = tp->udev;
3323
3324         return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
3325 }
3326
3327 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
3328 {
3329         if (enable) {
3330                 u32 ocp_data;
3331
3332                 __rtl_set_wol(tp, WAKE_ANY);
3333
3334                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3335
3336                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3337                 ocp_data |= LINK_OFF_WAKE_EN;
3338                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3339
3340                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3341         } else {
3342                 u32 ocp_data;
3343
3344                 __rtl_set_wol(tp, tp->saved_wolopts);
3345
3346                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3347
3348                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3349                 ocp_data &= ~LINK_OFF_WAKE_EN;
3350                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3351
3352                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3353         }
3354 }
3355
3356 static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
3357 {
3358         if (enable) {
3359                 r8153_u1u2en(tp, false);
3360                 r8153_u2p3en(tp, false);
3361                 r8153_mac_clk_spd(tp, true);
3362                 rtl_runtime_suspend_enable(tp, true);
3363         } else {
3364                 rtl_runtime_suspend_enable(tp, false);
3365                 r8153_mac_clk_spd(tp, false);
3366
3367                 switch (tp->version) {
3368                 case RTL_VER_03:
3369                 case RTL_VER_04:
3370                         break;
3371                 case RTL_VER_05:
3372                 case RTL_VER_06:
3373                 default:
3374                         r8153_u2p3en(tp, true);
3375                         break;
3376                 }
3377
3378                 r8153_u1u2en(tp, true);
3379         }
3380 }
3381
3382 static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
3383 {
3384         if (enable) {
3385                 r8153_queue_wake(tp, true);
3386                 r8153b_u1u2en(tp, false);
3387                 r8153_u2p3en(tp, false);
3388                 rtl_runtime_suspend_enable(tp, true);
3389                 r8153b_ups_en(tp, true);
3390         } else {
3391                 r8153b_ups_en(tp, false);
3392                 r8153_queue_wake(tp, false);
3393                 rtl_runtime_suspend_enable(tp, false);
3394                 r8153b_u1u2en(tp, true);
3395         }
3396 }
3397
3398 static void r8153_teredo_off(struct r8152 *tp)
3399 {
3400         u32 ocp_data;
3401
3402         switch (tp->version) {
3403         case RTL_VER_01:
3404         case RTL_VER_02:
3405         case RTL_VER_03:
3406         case RTL_VER_04:
3407         case RTL_VER_05:
3408         case RTL_VER_06:
3409         case RTL_VER_07:
3410                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3411                 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
3412                               OOB_TEREDO_EN);
3413                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3414                 break;
3415
3416         case RTL_VER_08:
3417         case RTL_VER_09:
3418                 /* The bit 0 ~ 7 are relative with teredo settings. They are
3419                  * W1C (write 1 to clear), so set all 1 to disable it.
3420                  */
3421                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
3422                 break;
3423
3424         default:
3425                 break;
3426         }
3427
3428         ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
3429         ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
3430         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
3431 }
3432
3433 static void rtl_reset_bmu(struct r8152 *tp)
3434 {
3435         u32 ocp_data;
3436
3437         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
3438         ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
3439         ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3440         ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
3441         ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3442 }
3443
3444 /* Clear the bp to stop the firmware before loading a new one */
3445 static void rtl_clear_bp(struct r8152 *tp, u16 type)
3446 {
3447         switch (tp->version) {
3448         case RTL_VER_01:
3449         case RTL_VER_02:
3450         case RTL_VER_07:
3451                 break;
3452         case RTL_VER_03:
3453         case RTL_VER_04:
3454         case RTL_VER_05:
3455         case RTL_VER_06:
3456                 ocp_write_byte(tp, type, PLA_BP_EN, 0);
3457                 break;
3458         case RTL_VER_08:
3459         case RTL_VER_09:
3460         default:
3461                 if (type == MCU_TYPE_USB) {
3462                         ocp_write_byte(tp, MCU_TYPE_USB, USB_BP2_EN, 0);
3463
3464                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_8, 0);
3465                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_9, 0);
3466                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_10, 0);
3467                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_11, 0);
3468                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_12, 0);
3469                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_13, 0);
3470                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_14, 0);
3471                         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_15, 0);
3472                 } else {
3473                         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
3474                 }
3475                 break;
3476         }
3477
3478         ocp_write_word(tp, type, PLA_BP_0, 0);
3479         ocp_write_word(tp, type, PLA_BP_1, 0);
3480         ocp_write_word(tp, type, PLA_BP_2, 0);
3481         ocp_write_word(tp, type, PLA_BP_3, 0);
3482         ocp_write_word(tp, type, PLA_BP_4, 0);
3483         ocp_write_word(tp, type, PLA_BP_5, 0);
3484         ocp_write_word(tp, type, PLA_BP_6, 0);
3485         ocp_write_word(tp, type, PLA_BP_7, 0);
3486
3487         /* wait 3 ms to make sure the firmware is stopped */
3488         usleep_range(3000, 6000);
3489         ocp_write_word(tp, type, PLA_BP_BA, 0);
3490 }
3491
3492 static int r8153_patch_request(struct r8152 *tp, bool request)
3493 {
3494         u16 data;
3495         int i;
3496
3497         data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
3498         if (request)
3499                 data |= PATCH_REQUEST;
3500         else
3501                 data &= ~PATCH_REQUEST;
3502         ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
3503
3504         for (i = 0; request && i < 5000; i++) {
3505                 usleep_range(1000, 2000);
3506                 if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)
3507                         break;
3508         }
3509
3510         if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
3511                 netif_err(tp, drv, tp->netdev, "patch request fail\n");
3512                 r8153_patch_request(tp, false);
3513                 return -ETIME;
3514         } else {
3515                 return 0;
3516         }
3517 }
3518
3519 static int r8153_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key)
3520 {
3521         if (r8153_patch_request(tp, true)) {
3522                 dev_err(&tp->intf->dev, "patch request fail\n");
3523                 return -ETIME;
3524         }
3525
3526         sram_write(tp, key_addr, patch_key);
3527         sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);
3528
3529         return 0;
3530 }
3531
3532 static int r8153_post_ram_code(struct r8152 *tp, u16 key_addr)
3533 {
3534         u16 data;
3535
3536         sram_write(tp, 0x0000, 0x0000);
3537
3538         data = ocp_reg_read(tp, OCP_PHY_LOCK);
3539         data &= ~PATCH_LOCK;
3540         ocp_reg_write(tp, OCP_PHY_LOCK, data);
3541
3542         sram_write(tp, key_addr, 0x0000);
3543
3544         r8153_patch_request(tp, false);
3545
3546         ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base);
3547
3548         return 0;
3549 }
3550
3551 static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)
3552 {
3553         u32 length;
3554         u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start;
3555         bool rc = false;
3556
3557         switch (tp->version) {
3558         case RTL_VER_04:
3559         case RTL_VER_05:
3560         case RTL_VER_06:
3561                 fw_reg = 0xa014;
3562                 ba_reg = 0xa012;
3563                 patch_en_addr = 0xa01a;
3564                 mode_reg = 0xb820;
3565                 bp_start = 0xa000;
3566                 break;
3567         default:
3568                 goto out;
3569         }
3570
3571         fw_offset = __le16_to_cpu(phy->fw_offset);
3572         if (fw_offset < sizeof(*phy)) {
3573                 dev_err(&tp->intf->dev, "fw_offset too small\n");
3574                 goto out;
3575         }
3576
3577         length = __le32_to_cpu(phy->blk_hdr.length);
3578         if (length < fw_offset) {
3579                 dev_err(&tp->intf->dev, "invalid fw_offset\n");
3580                 goto out;
3581         }
3582
3583         length -= __le16_to_cpu(phy->fw_offset);
3584         if (!length || (length & 1)) {
3585                 dev_err(&tp->intf->dev, "invalid block length\n");
3586                 goto out;
3587         }
3588
3589         if (__le16_to_cpu(phy->fw_reg) != fw_reg) {
3590                 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
3591                 goto out;
3592         }
3593
3594         if (__le16_to_cpu(phy->ba_reg) != ba_reg) {
3595                 dev_err(&tp->intf->dev, "invalid base address register\n");
3596                 goto out;
3597         }
3598
3599         if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) {
3600                 dev_err(&tp->intf->dev,
3601                         "invalid patch mode enabled register\n");
3602                 goto out;
3603         }
3604
3605         if (__le16_to_cpu(phy->mode_reg) != mode_reg) {
3606                 dev_err(&tp->intf->dev,
3607                         "invalid register to switch the mode\n");
3608                 goto out;
3609         }
3610
3611         if (__le16_to_cpu(phy->bp_start) != bp_start) {
3612                 dev_err(&tp->intf->dev,
3613                         "invalid start register of break point\n");
3614                 goto out;
3615         }
3616
3617         if (__le16_to_cpu(phy->bp_num) > 4) {
3618                 dev_err(&tp->intf->dev, "invalid break point number\n");
3619                 goto out;
3620         }
3621
3622         rc = true;
3623 out:
3624         return rc;
3625 }
3626
3627 static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)
3628 {
3629         u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;
3630         bool rc = false;
3631         u32 length, type;
3632         int i, max_bp;
3633
3634         type = __le32_to_cpu(mac->blk_hdr.type);
3635         if (type == RTL_FW_PLA) {
3636                 switch (tp->version) {
3637                 case RTL_VER_01:
3638                 case RTL_VER_02:
3639                 case RTL_VER_07:
3640                         fw_reg = 0xf800;
3641                         bp_ba_addr = PLA_BP_BA;
3642                         bp_en_addr = 0;
3643                         bp_start = PLA_BP_0;
3644                         max_bp = 8;
3645                         break;
3646                 case RTL_VER_03:
3647                 case RTL_VER_04:
3648                 case RTL_VER_05:
3649                 case RTL_VER_06:
3650                 case RTL_VER_08:
3651                 case RTL_VER_09:
3652                         fw_reg = 0xf800;
3653                         bp_ba_addr = PLA_BP_BA;
3654                         bp_en_addr = PLA_BP_EN;
3655                         bp_start = PLA_BP_0;
3656                         max_bp = 8;
3657                         break;
3658                 default:
3659                         goto out;
3660                 }
3661         } else if (type == RTL_FW_USB) {
3662                 switch (tp->version) {
3663                 case RTL_VER_03:
3664                 case RTL_VER_04:
3665                 case RTL_VER_05:
3666                 case RTL_VER_06:
3667                         fw_reg = 0xf800;
3668                         bp_ba_addr = USB_BP_BA;
3669                         bp_en_addr = USB_BP_EN;
3670                         bp_start = USB_BP_0;
3671                         max_bp = 8;
3672                         break;
3673                 case RTL_VER_08:
3674                 case RTL_VER_09:
3675                         fw_reg = 0xe600;
3676                         bp_ba_addr = USB_BP_BA;
3677                         bp_en_addr = USB_BP2_EN;
3678                         bp_start = USB_BP_0;
3679                         max_bp = 16;
3680                         break;
3681                 case RTL_VER_01:
3682                 case RTL_VER_02:
3683                 case RTL_VER_07:
3684                 default:
3685                         goto out;
3686                 }
3687         } else {
3688                 goto out;
3689         }
3690
3691         fw_offset = __le16_to_cpu(mac->fw_offset);
3692         if (fw_offset < sizeof(*mac)) {
3693                 dev_err(&tp->intf->dev, "fw_offset too small\n");
3694                 goto out;
3695         }
3696
3697         length = __le32_to_cpu(mac->blk_hdr.length);
3698         if (length < fw_offset) {
3699                 dev_err(&tp->intf->dev, "invalid fw_offset\n");
3700                 goto out;
3701         }
3702
3703         length -= fw_offset;
3704         if (length < 4 || (length & 3)) {
3705                 dev_err(&tp->intf->dev, "invalid block length\n");
3706                 goto out;
3707         }
3708
3709         if (__le16_to_cpu(mac->fw_reg) != fw_reg) {
3710                 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
3711                 goto out;
3712         }
3713
3714         if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {
3715                 dev_err(&tp->intf->dev, "invalid base address register\n");
3716                 goto out;
3717         }
3718
3719         if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {
3720                 dev_err(&tp->intf->dev, "invalid enabled mask register\n");
3721                 goto out;
3722         }
3723
3724         if (__le16_to_cpu(mac->bp_start) != bp_start) {
3725                 dev_err(&tp->intf->dev,
3726                         "invalid start register of break point\n");
3727                 goto out;
3728         }
3729
3730         if (__le16_to_cpu(mac->bp_num) > max_bp) {
3731                 dev_err(&tp->intf->dev, "invalid break point number\n");
3732                 goto out;
3733         }
3734
3735         for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {
3736                 if (mac->bp[i]) {
3737                         dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);
3738                         goto out;
3739                 }
3740         }
3741
3742         rc = true;
3743 out:
3744         return rc;
3745 }
3746
3747 /* Verify the checksum for the firmware file. It is calculated from the version
3748  * field to the end of the file. Compare the result with the checksum field to
3749  * make sure the file is correct.
3750  */
3751 static long rtl8152_fw_verify_checksum(struct r8152 *tp,
3752                                        struct fw_header *fw_hdr, size_t size)
3753 {
3754         unsigned char checksum[sizeof(fw_hdr->checksum)];
3755         struct crypto_shash *alg;
3756         struct shash_desc *sdesc;
3757         size_t len;
3758         long rc;
3759
3760         alg = crypto_alloc_shash("sha256", 0, 0);
3761         if (IS_ERR(alg)) {
3762                 rc = PTR_ERR(alg);
3763                 goto out;
3764         }
3765
3766         if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) {
3767                 rc = -EFAULT;
3768                 dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n",
3769                         crypto_shash_digestsize(alg));
3770                 goto free_shash;
3771         }
3772
3773         len = sizeof(*sdesc) + crypto_shash_descsize(alg);
3774         sdesc = kmalloc(len, GFP_KERNEL);
3775         if (!sdesc) {
3776                 rc = -ENOMEM;
3777                 goto free_shash;
3778         }
3779         sdesc->tfm = alg;
3780
3781         len = size - sizeof(fw_hdr->checksum);
3782         rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum);
3783         kfree(sdesc);
3784         if (rc)
3785                 goto free_shash;
3786
3787         if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) {
3788                 dev_err(&tp->intf->dev, "checksum fail\n");
3789                 rc = -EFAULT;
3790         }
3791
3792 free_shash:
3793         crypto_free_shash(alg);
3794 out:
3795         return rc;
3796 }
3797
3798 static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)
3799 {
3800         const struct firmware *fw = rtl_fw->fw;
3801         struct fw_header *fw_hdr = (struct fw_header *)fw->data;
3802         struct fw_mac *pla = NULL, *usb = NULL;
3803         struct fw_phy_patch_key *start = NULL;
3804         struct fw_phy_nc *phy_nc = NULL;
3805         struct fw_block *stop = NULL;
3806         long ret = -EFAULT;
3807         int i;
3808
3809         if (fw->size < sizeof(*fw_hdr)) {
3810                 dev_err(&tp->intf->dev, "file too small\n");
3811                 goto fail;
3812         }
3813
3814         ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size);
3815         if (ret)
3816                 goto fail;
3817
3818         ret = -EFAULT;
3819
3820         for (i = sizeof(*fw_hdr); i < fw->size;) {
3821                 struct fw_block *block = (struct fw_block *)&fw->data[i];
3822                 u32 type;
3823
3824                 if ((i + sizeof(*block)) > fw->size)
3825                         goto fail;
3826
3827                 type = __le32_to_cpu(block->type);
3828                 switch (type) {
3829                 case RTL_FW_END:
3830                         if (__le32_to_cpu(block->length) != sizeof(*block))
3831                                 goto fail;
3832                         goto fw_end;
3833                 case RTL_FW_PLA:
3834                         if (pla) {
3835                                 dev_err(&tp->intf->dev,
3836                                         "multiple PLA firmware encountered");
3837                                 goto fail;
3838                         }
3839
3840                         pla = (struct fw_mac *)block;
3841                         if (!rtl8152_is_fw_mac_ok(tp, pla)) {
3842                                 dev_err(&tp->intf->dev,
3843                                         "check PLA firmware failed\n");
3844                                 goto fail;
3845                         }
3846                         break;
3847                 case RTL_FW_USB:
3848                         if (usb) {
3849                                 dev_err(&tp->intf->dev,
3850                                         "multiple USB firmware encountered");
3851                                 goto fail;
3852                         }
3853
3854                         usb = (struct fw_mac *)block;
3855                         if (!rtl8152_is_fw_mac_ok(tp, usb)) {
3856                                 dev_err(&tp->intf->dev,
3857                                         "check USB firmware failed\n");
3858                                 goto fail;
3859                         }
3860                         break;
3861                 case RTL_FW_PHY_START:
3862                         if (start || phy_nc || stop) {
3863                                 dev_err(&tp->intf->dev,
3864                                         "check PHY_START fail\n");
3865                                 goto fail;
3866                         }
3867
3868                         if (__le32_to_cpu(block->length) != sizeof(*start)) {
3869                                 dev_err(&tp->intf->dev,
3870                                         "Invalid length for PHY_START\n");
3871                                 goto fail;
3872                         }
3873
3874                         start = (struct fw_phy_patch_key *)block;
3875                         break;
3876                 case RTL_FW_PHY_STOP:
3877                         if (stop || !start) {
3878                                 dev_err(&tp->intf->dev,
3879                                         "Check PHY_STOP fail\n");
3880                                 goto fail;
3881                         }
3882
3883                         if (__le32_to_cpu(block->length) != sizeof(*block)) {
3884                                 dev_err(&tp->intf->dev,
3885                                         "Invalid length for PHY_STOP\n");
3886                                 goto fail;
3887                         }
3888
3889                         stop = block;
3890                         break;
3891                 case RTL_FW_PHY_NC:
3892                         if (!start || stop) {
3893                                 dev_err(&tp->intf->dev,
3894                                         "check PHY_NC fail\n");
3895                                 goto fail;
3896                         }
3897
3898                         if (phy_nc) {
3899                                 dev_err(&tp->intf->dev,
3900                                         "multiple PHY NC encountered\n");
3901                                 goto fail;
3902                         }
3903
3904                         phy_nc = (struct fw_phy_nc *)block;
3905                         if (!rtl8152_is_fw_phy_nc_ok(tp, phy_nc)) {
3906                                 dev_err(&tp->intf->dev,
3907                                         "check PHY NC firmware failed\n");
3908                                 goto fail;
3909                         }
3910
3911                         break;
3912                 default:
3913                         dev_warn(&tp->intf->dev, "Unknown type %u is found\n",
3914                                  type);
3915                         break;
3916                 }
3917
3918                 /* next block */
3919                 i += ALIGN(__le32_to_cpu(block->length), 8);
3920         }
3921
3922 fw_end:
3923         if ((phy_nc || start) && !stop) {
3924                 dev_err(&tp->intf->dev, "without PHY_STOP\n");
3925                 goto fail;
3926         }
3927
3928         return 0;
3929 fail:
3930         return ret;
3931 }
3932
3933 static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)
3934 {
3935         u16 mode_reg, bp_index;
3936         u32 length, i, num;
3937         __le16 *data;
3938
3939         mode_reg = __le16_to_cpu(phy->mode_reg);
3940         sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre));
3941         sram_write(tp, __le16_to_cpu(phy->ba_reg),
3942                    __le16_to_cpu(phy->ba_data));
3943
3944         length = __le32_to_cpu(phy->blk_hdr.length);
3945         length -= __le16_to_cpu(phy->fw_offset);
3946         num = length / 2;
3947         data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
3948
3949         ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
3950         for (i = 0; i < num; i++)
3951                 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
3952
3953         sram_write(tp, __le16_to_cpu(phy->patch_en_addr),
3954                    __le16_to_cpu(phy->patch_en_value));
3955
3956         bp_index = __le16_to_cpu(phy->bp_start);
3957         num = __le16_to_cpu(phy->bp_num);
3958         for (i = 0; i < num; i++) {
3959                 sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i]));
3960                 bp_index += 2;
3961         }
3962
3963         sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post));
3964
3965         dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
3966 }
3967
3968 static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
3969 {
3970         u16 bp_en_addr, bp_index, type, bp_num, fw_ver_reg;
3971         u32 length;
3972         u8 *data;
3973         int i;
3974
3975         switch (__le32_to_cpu(mac->blk_hdr.type)) {
3976         case RTL_FW_PLA:
3977                 type = MCU_TYPE_PLA;
3978                 break;
3979         case RTL_FW_USB:
3980                 type = MCU_TYPE_USB;
3981                 break;
3982         default:
3983                 return;
3984         }
3985
3986         rtl_clear_bp(tp, type);
3987
3988         /* Enable backup/restore of MACDBG. This is required after clearing PLA
3989          * break points and before applying the PLA firmware.
3990          */
3991         if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&
3992             !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {
3993                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);
3994                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);
3995         }
3996
3997         length = __le32_to_cpu(mac->blk_hdr.length);
3998         length -= __le16_to_cpu(mac->fw_offset);
3999
4000         data = (u8 *)mac;
4001         data += __le16_to_cpu(mac->fw_offset);
4002
4003         generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data,
4004                           type);
4005
4006         ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
4007                        __le16_to_cpu(mac->bp_ba_value));
4008
4009         bp_index = __le16_to_cpu(mac->bp_start);
4010         bp_num = __le16_to_cpu(mac->bp_num);
4011         for (i = 0; i < bp_num; i++) {
4012                 ocp_write_word(tp, type, bp_index, __le16_to_cpu(mac->bp[i]));
4013                 bp_index += 2;
4014         }
4015
4016         bp_en_addr = __le16_to_cpu(mac->bp_en_addr);
4017         if (bp_en_addr)
4018                 ocp_write_word(tp, type, bp_en_addr,
4019                                __le16_to_cpu(mac->bp_en_value));
4020
4021         fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);
4022         if (fw_ver_reg)
4023                 ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg,
4024                                mac->fw_ver_data);
4025
4026         dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);
4027 }
4028
4029 static void rtl8152_apply_firmware(struct r8152 *tp)
4030 {
4031         struct rtl_fw *rtl_fw = &tp->rtl_fw;
4032         const struct firmware *fw;
4033         struct fw_header *fw_hdr;
4034         struct fw_phy_patch_key *key;
4035         u16 key_addr = 0;
4036         int i;
4037
4038         if (IS_ERR_OR_NULL(rtl_fw->fw))
4039                 return;
4040
4041         fw = rtl_fw->fw;
4042         fw_hdr = (struct fw_header *)fw->data;
4043
4044         if (rtl_fw->pre_fw)
4045                 rtl_fw->pre_fw(tp);
4046
4047         for (i = offsetof(struct fw_header, blocks); i < fw->size;) {
4048                 struct fw_block *block = (struct fw_block *)&fw->data[i];
4049
4050                 switch (__le32_to_cpu(block->type)) {
4051                 case RTL_FW_END:
4052                         goto post_fw;
4053                 case RTL_FW_PLA:
4054                 case RTL_FW_USB:
4055                         rtl8152_fw_mac_apply(tp, (struct fw_mac *)block);
4056                         break;
4057                 case RTL_FW_PHY_START:
4058                         key = (struct fw_phy_patch_key *)block;
4059                         key_addr = __le16_to_cpu(key->key_reg);
4060                         r8153_pre_ram_code(tp, key_addr,
4061                                            __le16_to_cpu(key->key_data));
4062                         break;
4063                 case RTL_FW_PHY_STOP:
4064                         WARN_ON(!key_addr);
4065                         r8153_post_ram_code(tp, key_addr);
4066                         break;
4067                 case RTL_FW_PHY_NC:
4068                         rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block);
4069                         break;
4070                 default:
4071                         break;
4072                 }
4073
4074                 i += ALIGN(__le32_to_cpu(block->length), 8);
4075         }
4076
4077 post_fw:
4078         if (rtl_fw->post_fw)
4079                 rtl_fw->post_fw(tp);
4080
4081         strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE);
4082         dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);
4083 }
4084
4085 static void rtl8152_release_firmware(struct r8152 *tp)
4086 {
4087         struct rtl_fw *rtl_fw = &tp->rtl_fw;
4088
4089         if (!IS_ERR_OR_NULL(rtl_fw->fw)) {
4090                 release_firmware(rtl_fw->fw);
4091                 rtl_fw->fw = NULL;
4092         }
4093 }
4094
4095 static int rtl8152_request_firmware(struct r8152 *tp)
4096 {
4097         struct rtl_fw *rtl_fw = &tp->rtl_fw;
4098         long rc;
4099
4100         if (rtl_fw->fw || !rtl_fw->fw_name) {
4101                 dev_info(&tp->intf->dev, "skip request firmware\n");
4102                 rc = 0;
4103                 goto result;
4104         }
4105
4106         rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev);
4107         if (rc < 0)
4108                 goto result;
4109
4110         rc = rtl8152_check_firmware(tp, rtl_fw);
4111         if (rc < 0)
4112                 release_firmware(rtl_fw->fw);
4113
4114 result:
4115         if (rc) {
4116                 rtl_fw->fw = ERR_PTR(rc);
4117
4118                 dev_warn(&tp->intf->dev,
4119                          "unable to load firmware patch %s (%ld)\n",
4120                          rtl_fw->fw_name, rc);
4121         }
4122
4123         return rc;
4124 }
4125
4126 static void r8152_aldps_en(struct r8152 *tp, bool enable)
4127 {
4128         if (enable) {
4129                 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
4130                                                     LINKENA | DIS_SDSAVE);
4131         } else {
4132                 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
4133                                                     DIS_SDSAVE);
4134                 msleep(20);
4135         }
4136 }
4137
4138 static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
4139 {
4140         ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
4141         ocp_reg_write(tp, OCP_EEE_DATA, reg);
4142         ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
4143 }
4144
4145 static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
4146 {
4147         u16 data;
4148
4149         r8152_mmd_indirect(tp, dev, reg);
4150         data = ocp_reg_read(tp, OCP_EEE_DATA);
4151         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
4152
4153         return data;
4154 }
4155
4156 static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
4157 {
4158         r8152_mmd_indirect(tp, dev, reg);
4159         ocp_reg_write(tp, OCP_EEE_DATA, data);
4160         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
4161 }
4162
4163 static void r8152_eee_en(struct r8152 *tp, bool enable)
4164 {
4165         u16 config1, config2, config3;
4166         u32 ocp_data;
4167
4168         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4169         config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
4170         config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
4171         config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
4172
4173         if (enable) {
4174                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
4175                 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
4176                 config1 |= sd_rise_time(1);
4177                 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
4178                 config3 |= fast_snr(42);
4179         } else {
4180                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
4181                 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
4182                              RX_QUIET_EN);
4183                 config1 |= sd_rise_time(7);
4184                 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
4185                 config3 |= fast_snr(511);
4186         }
4187
4188         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
4189         ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
4190         ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
4191         ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
4192 }
4193
4194 static void r8153_eee_en(struct r8152 *tp, bool enable)
4195 {
4196         u32 ocp_data;
4197         u16 config;
4198
4199         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4200         config = ocp_reg_read(tp, OCP_EEE_CFG);
4201
4202         if (enable) {
4203                 ocp_data |= EEE_RX_EN | EEE_TX_EN;
4204                 config |= EEE10_EN;
4205         } else {
4206                 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
4207                 config &= ~EEE10_EN;
4208         }
4209
4210         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
4211         ocp_reg_write(tp, OCP_EEE_CFG, config);
4212
4213         tp->ups_info.eee = enable;
4214 }
4215
4216 static void rtl_eee_enable(struct r8152 *tp, bool enable)
4217 {
4218         switch (tp->version) {
4219         case RTL_VER_01:
4220         case RTL_VER_02:
4221         case RTL_VER_07:
4222                 if (enable) {
4223                         r8152_eee_en(tp, true);
4224                         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
4225                                         tp->eee_adv);
4226                 } else {
4227                         r8152_eee_en(tp, false);
4228                         r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
4229                 }
4230                 break;
4231         case RTL_VER_03:
4232         case RTL_VER_04:
4233         case RTL_VER_05:
4234         case RTL_VER_06:
4235         case RTL_VER_08:
4236         case RTL_VER_09:
4237                 if (enable) {
4238                         r8153_eee_en(tp, true);
4239                         ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
4240                 } else {
4241                         r8153_eee_en(tp, false);
4242                         ocp_reg_write(tp, OCP_EEE_ADV, 0);
4243                 }
4244                 break;
4245         default:
4246                 break;
4247         }
4248 }
4249
4250 static void r8152b_enable_fc(struct r8152 *tp)
4251 {
4252         u16 anar;
4253
4254         anar = r8152_mdio_read(tp, MII_ADVERTISE);
4255         anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4256         r8152_mdio_write(tp, MII_ADVERTISE, anar);
4257
4258         tp->ups_info.flow_control = true;
4259 }
4260
4261 static void rtl8152_disable(struct r8152 *tp)
4262 {
4263         r8152_aldps_en(tp, false);
4264         rtl_disable(tp);
4265         r8152_aldps_en(tp, true);
4266 }
4267
4268 static void r8152b_hw_phy_cfg(struct r8152 *tp)
4269 {
4270         rtl8152_apply_firmware(tp);
4271         rtl_eee_enable(tp, tp->eee_en);
4272         r8152_aldps_en(tp, true);
4273         r8152b_enable_fc(tp);
4274
4275         set_bit(PHY_RESET, &tp->flags);
4276 }
4277
4278 static void wait_oob_link_list_ready(struct r8152 *tp)
4279 {
4280         u32 ocp_data;
4281         int i;
4282
4283         for (i = 0; i < 1000; i++) {
4284                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4285                 if (ocp_data & LINK_LIST_READY)
4286                         break;
4287                 usleep_range(1000, 2000);
4288         }
4289 }
4290
4291 static void r8152b_exit_oob(struct r8152 *tp)
4292 {
4293         u32 ocp_data;
4294
4295         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4296         ocp_data &= ~RCR_ACPT_ALL;
4297         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4298
4299         rxdy_gated_en(tp, true);
4300         r8153_teredo_off(tp);
4301         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
4302         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
4303
4304         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4305         ocp_data &= ~NOW_IS_OOB;
4306         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4307
4308         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4309         ocp_data &= ~MCU_BORW_EN;
4310         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4311
4312         wait_oob_link_list_ready(tp);
4313
4314         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4315         ocp_data |= RE_INIT_LL;
4316         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4317
4318         wait_oob_link_list_ready(tp);
4319
4320         rtl8152_nic_reset(tp);
4321
4322         /* rx share fifo credit full threshold */
4323         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
4324
4325         if (tp->udev->speed == USB_SPEED_FULL ||
4326             tp->udev->speed == USB_SPEED_LOW) {
4327                 /* rx share fifo credit near full threshold */
4328                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
4329                                 RXFIFO_THR2_FULL);
4330                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
4331                                 RXFIFO_THR3_FULL);
4332         } else {
4333                 /* rx share fifo credit near full threshold */
4334                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
4335                                 RXFIFO_THR2_HIGH);
4336                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
4337                                 RXFIFO_THR3_HIGH);
4338         }
4339
4340         /* TX share fifo free credit full threshold */
4341         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
4342
4343         ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
4344         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
4345         ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
4346                         TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
4347
4348         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
4349
4350         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
4351
4352         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
4353         ocp_data |= TCR0_AUTO_FIFO;
4354         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
4355 }
4356
4357 static void r8152b_enter_oob(struct r8152 *tp)
4358 {
4359         u32 ocp_data;
4360
4361         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4362         ocp_data &= ~NOW_IS_OOB;
4363         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4364
4365         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
4366         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
4367         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
4368
4369         rtl_disable(tp);
4370
4371         wait_oob_link_list_ready(tp);
4372
4373         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4374         ocp_data |= RE_INIT_LL;
4375         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4376
4377         wait_oob_link_list_ready(tp);
4378
4379         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
4380
4381         rtl_rx_vlan_en(tp, true);
4382
4383         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
4384         ocp_data |= ALDPS_PROXY_MODE;
4385         ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
4386
4387         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4388         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
4389         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4390
4391         rxdy_gated_en(tp, false);
4392
4393         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4394         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
4395         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4396 }
4397
4398 static int r8153_pre_firmware_1(struct r8152 *tp)
4399 {
4400         int i;
4401
4402         /* Wait till the WTD timer is ready. It would take at most 104 ms. */
4403         for (i = 0; i < 104; i++) {
4404                 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);
4405
4406                 if (!(ocp_data & WTD1_EN))
4407                         break;
4408                 usleep_range(1000, 2000);
4409         }
4410
4411         return 0;
4412 }
4413
4414 static int r8153_post_firmware_1(struct r8152 *tp)
4415 {
4416         /* set USB_BP_4 to support USB_SPEED_SUPER only */
4417         if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
4418                 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);
4419
4420         /* reset UPHY timer to 36 ms */
4421         ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
4422
4423         return 0;
4424 }
4425
4426 static int r8153_pre_firmware_2(struct r8152 *tp)
4427 {
4428         u32 ocp_data;
4429
4430         r8153_pre_firmware_1(tp);
4431
4432         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
4433         ocp_data &= ~FW_FIX_SUSPEND;
4434         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
4435
4436         return 0;
4437 }
4438
4439 static int r8153_post_firmware_2(struct r8152 *tp)
4440 {
4441         u32 ocp_data;
4442
4443         /* enable bp0 if support USB_SPEED_SUPER only */
4444         if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
4445                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
4446                 ocp_data |= BIT(0);
4447                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
4448         }
4449
4450         /* reset UPHY timer to 36 ms */
4451         ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
4452
4453         /* enable U3P3 check, set the counter to 4 */
4454         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
4455
4456         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
4457         ocp_data |= FW_FIX_SUSPEND;
4458         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
4459
4460         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4461         ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4462         ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4463
4464         return 0;
4465 }
4466
4467 static int r8153_post_firmware_3(struct r8152 *tp)
4468 {
4469         u32 ocp_data;
4470
4471         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4472         ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4473         ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4474
4475         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
4476         ocp_data |= FW_IP_RESET_EN;
4477         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
4478
4479         return 0;
4480 }
4481
4482 static int r8153b_pre_firmware_1(struct r8152 *tp)
4483 {
4484         /* enable fc timer and set timer to 1 second. */
4485         ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
4486                        CTRL_TIMER_EN | (1000 / 8));
4487
4488         return 0;
4489 }
4490
4491 static int r8153b_post_firmware_1(struct r8152 *tp)
4492 {
4493         u32 ocp_data;
4494
4495         /* enable bp0 for RTL8153-BND */
4496         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
4497         if (ocp_data & BND_MASK) {
4498                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
4499                 ocp_data |= BIT(0);
4500                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
4501         }
4502
4503         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
4504         ocp_data |= FLOW_CTRL_PATCH_OPT;
4505         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
4506
4507         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
4508         ocp_data |= FC_PATCH_TASK;
4509         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
4510
4511         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
4512         ocp_data |= FW_IP_RESET_EN;
4513         ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
4514
4515         return 0;
4516 }
4517
4518 static void r8153_aldps_en(struct r8152 *tp, bool enable)
4519 {
4520         u16 data;
4521
4522         data = ocp_reg_read(tp, OCP_POWER_CFG);
4523         if (enable) {
4524                 data |= EN_ALDPS;
4525                 ocp_reg_write(tp, OCP_POWER_CFG, data);
4526         } else {
4527                 int i;
4528
4529                 data &= ~EN_ALDPS;
4530                 ocp_reg_write(tp, OCP_POWER_CFG, data);
4531                 for (i = 0; i < 20; i++) {
4532                         usleep_range(1000, 2000);
4533                         if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
4534                                 break;
4535                 }
4536         }
4537
4538         tp->ups_info.aldps = enable;
4539 }
4540
4541 static void r8153_hw_phy_cfg(struct r8152 *tp)
4542 {
4543         u32 ocp_data;
4544         u16 data;
4545
4546         /* disable ALDPS before updating the PHY parameters */
4547         r8153_aldps_en(tp, false);
4548
4549         /* disable EEE before updating the PHY parameters */
4550         rtl_eee_enable(tp, false);
4551
4552         rtl8152_apply_firmware(tp);
4553
4554         if (tp->version == RTL_VER_03) {
4555                 data = ocp_reg_read(tp, OCP_EEE_CFG);
4556                 data &= ~CTAP_SHORT_EN;
4557                 ocp_reg_write(tp, OCP_EEE_CFG, data);
4558         }
4559
4560         data = ocp_reg_read(tp, OCP_POWER_CFG);
4561         data |= EEE_CLKDIV_EN;
4562         ocp_reg_write(tp, OCP_POWER_CFG, data);
4563
4564         data = ocp_reg_read(tp, OCP_DOWN_SPEED);
4565         data |= EN_10M_BGOFF;
4566         ocp_reg_write(tp, OCP_DOWN_SPEED, data);
4567         data = ocp_reg_read(tp, OCP_POWER_CFG);
4568         data |= EN_10M_PLLOFF;
4569         ocp_reg_write(tp, OCP_POWER_CFG, data);
4570         sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
4571
4572         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4573         ocp_data |= PFM_PWM_SWITCH;
4574         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4575
4576         /* Enable LPF corner auto tune */
4577         sram_write(tp, SRAM_LPF_CFG, 0xf70f);
4578
4579         /* Adjust 10M Amplitude */
4580         sram_write(tp, SRAM_10M_AMP1, 0x00af);
4581         sram_write(tp, SRAM_10M_AMP2, 0x0208);
4582
4583         if (tp->eee_en)
4584                 rtl_eee_enable(tp, true);
4585
4586         r8153_aldps_en(tp, true);
4587         r8152b_enable_fc(tp);
4588
4589         switch (tp->version) {
4590         case RTL_VER_03:
4591         case RTL_VER_04:
4592                 break;
4593         case RTL_VER_05:
4594         case RTL_VER_06:
4595         default:
4596                 r8153_u2p3en(tp, true);
4597                 break;
4598         }
4599
4600         set_bit(PHY_RESET, &tp->flags);
4601 }
4602
4603 static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
4604 {
4605         u32 ocp_data;
4606
4607         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
4608         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
4609         ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9;  /* data of bit16 */
4610         ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
4611
4612         return ocp_data;
4613 }
4614
4615 static void r8153b_hw_phy_cfg(struct r8152 *tp)
4616 {
4617         u32 ocp_data;
4618         u16 data;
4619
4620         /* disable ALDPS before updating the PHY parameters */
4621         r8153_aldps_en(tp, false);
4622
4623         /* disable EEE before updating the PHY parameters */
4624         rtl_eee_enable(tp, false);
4625
4626         rtl8152_apply_firmware(tp);
4627
4628         r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
4629
4630         data = sram_read(tp, SRAM_GREEN_CFG);
4631         data |= R_TUNE_EN;
4632         sram_write(tp, SRAM_GREEN_CFG, data);
4633         data = ocp_reg_read(tp, OCP_NCTL_CFG);
4634         data |= PGA_RETURN_EN;
4635         ocp_reg_write(tp, OCP_NCTL_CFG, data);
4636
4637         /* ADC Bias Calibration:
4638          * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
4639          * bit (bit3) to rebuild the real 16-bit data. Write the data to the
4640          * ADC ioffset.
4641          */
4642         ocp_data = r8152_efuse_read(tp, 0x7d);
4643         data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
4644         if (data != 0xffff)
4645                 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
4646
4647         /* ups mode tx-link-pulse timing adjustment:
4648          * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
4649          * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
4650          */
4651         ocp_data = ocp_reg_read(tp, 0xc426);
4652         ocp_data &= 0x3fff;
4653         if (ocp_data) {
4654                 u32 swr_cnt_1ms_ini;
4655
4656                 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
4657                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
4658                 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
4659                 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
4660         }
4661
4662         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4663         ocp_data |= PFM_PWM_SWITCH;
4664         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4665
4666         /* Advnace EEE */
4667         if (!r8153_patch_request(tp, true)) {
4668                 data = ocp_reg_read(tp, OCP_POWER_CFG);
4669                 data |= EEE_CLKDIV_EN;
4670                 ocp_reg_write(tp, OCP_POWER_CFG, data);
4671                 tp->ups_info.eee_ckdiv = true;
4672
4673                 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
4674                 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
4675                 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
4676                 tp->ups_info.eee_cmod_lv = true;
4677                 tp->ups_info._10m_ckdiv = true;
4678                 tp->ups_info.eee_plloff_giga = true;
4679
4680                 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
4681                 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
4682                 tp->ups_info._250m_ckdiv = true;
4683
4684                 r8153_patch_request(tp, false);
4685         }
4686
4687         if (tp->eee_en)
4688                 rtl_eee_enable(tp, true);
4689
4690         r8153_aldps_en(tp, true);
4691         r8152b_enable_fc(tp);
4692
4693         set_bit(PHY_RESET, &tp->flags);
4694 }
4695
4696 static void r8153_first_init(struct r8152 *tp)
4697 {
4698         u32 ocp_data;
4699
4700         r8153_mac_clk_spd(tp, false);
4701         rxdy_gated_en(tp, true);
4702         r8153_teredo_off(tp);
4703
4704         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4705         ocp_data &= ~RCR_ACPT_ALL;
4706         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4707
4708         rtl8152_nic_reset(tp);
4709         rtl_reset_bmu(tp);
4710
4711         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4712         ocp_data &= ~NOW_IS_OOB;
4713         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4714
4715         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4716         ocp_data &= ~MCU_BORW_EN;
4717         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4718
4719         wait_oob_link_list_ready(tp);
4720
4721         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4722         ocp_data |= RE_INIT_LL;
4723         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4724
4725         wait_oob_link_list_ready(tp);
4726
4727         rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
4728
4729         ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4730         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
4731         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
4732
4733         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
4734         ocp_data |= TCR0_AUTO_FIFO;
4735         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
4736
4737         rtl8152_nic_reset(tp);
4738
4739         /* rx share fifo credit full threshold */
4740         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
4741         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
4742         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
4743         /* TX share fifo free credit full threshold */
4744         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
4745 }
4746
4747 static void r8153_enter_oob(struct r8152 *tp)
4748 {
4749         u32 ocp_data;
4750
4751         r8153_mac_clk_spd(tp, true);
4752
4753         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4754         ocp_data &= ~NOW_IS_OOB;
4755         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4756
4757         rtl_disable(tp);
4758         rtl_reset_bmu(tp);
4759
4760         wait_oob_link_list_ready(tp);
4761
4762         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
4763         ocp_data |= RE_INIT_LL;
4764         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
4765
4766         wait_oob_link_list_ready(tp);
4767
4768         ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4769         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
4770
4771         switch (tp->version) {
4772         case RTL_VER_03:
4773         case RTL_VER_04:
4774         case RTL_VER_05:
4775         case RTL_VER_06:
4776                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
4777                 ocp_data &= ~TEREDO_WAKE_MASK;
4778                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
4779                 break;
4780
4781         case RTL_VER_08:
4782         case RTL_VER_09:
4783                 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
4784                  * type. Set it to zero. bits[7:0] are the W1C bits about
4785                  * the events. Set them to all 1 to clear them.
4786                  */
4787                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
4788                 break;
4789
4790         default:
4791                 break;
4792         }
4793
4794         rtl_rx_vlan_en(tp, true);
4795
4796         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
4797         ocp_data |= ALDPS_PROXY_MODE;
4798         ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
4799
4800         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
4801         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
4802         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
4803
4804         rxdy_gated_en(tp, false);
4805
4806         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4807         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
4808         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4809 }
4810
4811 static void rtl8153_disable(struct r8152 *tp)
4812 {
4813         r8153_aldps_en(tp, false);
4814         rtl_disable(tp);
4815         rtl_reset_bmu(tp);
4816         r8153_aldps_en(tp, true);
4817 }
4818
4819 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
4820                              u32 advertising)
4821 {
4822         u16 bmcr;
4823         int ret = 0;
4824
4825         if (autoneg == AUTONEG_DISABLE) {
4826                 if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
4827                         return -EINVAL;
4828
4829                 switch (speed) {
4830                 case SPEED_10:
4831                         bmcr = BMCR_SPEED10;
4832                         if (duplex == DUPLEX_FULL) {
4833                                 bmcr |= BMCR_FULLDPLX;
4834                                 tp->ups_info.speed_duplex = FORCE_10M_FULL;
4835                         } else {
4836                                 tp->ups_info.speed_duplex = FORCE_10M_HALF;
4837                         }
4838                         break;
4839                 case SPEED_100:
4840                         bmcr = BMCR_SPEED100;
4841                         if (duplex == DUPLEX_FULL) {
4842                                 bmcr |= BMCR_FULLDPLX;
4843                                 tp->ups_info.speed_duplex = FORCE_100M_FULL;
4844                         } else {
4845                                 tp->ups_info.speed_duplex = FORCE_100M_HALF;
4846                         }
4847                         break;
4848                 case SPEED_1000:
4849                         if (tp->mii.supports_gmii) {
4850                                 bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
4851                                 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
4852                                 break;
4853                         }
4854                         /* fall through */
4855                 default:
4856                         ret = -EINVAL;
4857                         goto out;
4858                 }
4859
4860                 if (duplex == DUPLEX_FULL)
4861                         tp->mii.full_duplex = 1;
4862                 else
4863                         tp->mii.full_duplex = 0;
4864
4865                 tp->mii.force_media = 1;
4866         } else {
4867                 u16 anar, tmp1;
4868                 u32 support;
4869
4870                 support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
4871                           RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
4872
4873                 if (tp->mii.supports_gmii)
4874                         support |= RTL_ADVERTISED_1000_FULL;
4875
4876                 if (!(advertising & support))
4877                         return -EINVAL;
4878
4879                 anar = r8152_mdio_read(tp, MII_ADVERTISE);
4880                 tmp1 = anar & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
4881                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
4882                 if (advertising & RTL_ADVERTISED_10_HALF) {
4883                         tmp1 |= ADVERTISE_10HALF;
4884                         tp->ups_info.speed_duplex = NWAY_10M_HALF;
4885                 }
4886                 if (advertising & RTL_ADVERTISED_10_FULL) {
4887                         tmp1 |= ADVERTISE_10FULL;
4888                         tp->ups_info.speed_duplex = NWAY_10M_FULL;
4889                 }
4890
4891                 if (advertising & RTL_ADVERTISED_100_HALF) {
4892                         tmp1 |= ADVERTISE_100HALF;
4893                         tp->ups_info.speed_duplex = NWAY_100M_HALF;
4894                 }
4895                 if (advertising & RTL_ADVERTISED_100_FULL) {
4896                         tmp1 |= ADVERTISE_100FULL;
4897                         tp->ups_info.speed_duplex = NWAY_100M_FULL;
4898                 }
4899
4900                 if (anar != tmp1) {
4901                         r8152_mdio_write(tp, MII_ADVERTISE, tmp1);
4902                         tp->mii.advertising = tmp1;
4903                 }
4904
4905                 if (tp->mii.supports_gmii) {
4906                         u16 gbcr;
4907
4908                         gbcr = r8152_mdio_read(tp, MII_CTRL1000);
4909                         tmp1 = gbcr & ~(ADVERTISE_1000FULL |
4910                                         ADVERTISE_1000HALF);
4911
4912                         if (advertising & RTL_ADVERTISED_1000_FULL) {
4913                                 tmp1 |= ADVERTISE_1000FULL;
4914                                 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
4915                         }
4916
4917                         if (gbcr != tmp1)
4918                                 r8152_mdio_write(tp, MII_CTRL1000, tmp1);
4919                 }
4920
4921                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
4922
4923                 tp->mii.force_media = 0;
4924         }
4925
4926         if (test_and_clear_bit(PHY_RESET, &tp->flags))
4927                 bmcr |= BMCR_RESET;
4928
4929         r8152_mdio_write(tp, MII_BMCR, bmcr);
4930
4931         if (bmcr & BMCR_RESET) {
4932                 int i;
4933
4934                 for (i = 0; i < 50; i++) {
4935                         msleep(20);
4936                         if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
4937                                 break;
4938                 }
4939         }
4940
4941 out:
4942         return ret;
4943 }
4944
4945 static void rtl8152_up(struct r8152 *tp)
4946 {
4947         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4948                 return;
4949
4950         r8152_aldps_en(tp, false);
4951         r8152b_exit_oob(tp);
4952         r8152_aldps_en(tp, true);
4953 }
4954
4955 static void rtl8152_down(struct r8152 *tp)
4956 {
4957         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
4958                 rtl_drop_queued_tx(tp);
4959                 return;
4960         }
4961
4962         r8152_power_cut_en(tp, false);
4963         r8152_aldps_en(tp, false);
4964         r8152b_enter_oob(tp);
4965         r8152_aldps_en(tp, true);
4966 }
4967
4968 static void rtl8153_up(struct r8152 *tp)
4969 {
4970         if (test_bit(RTL8152_UNPLUG, &tp->flags))
4971                 return;
4972
4973         r8153_u1u2en(tp, false);
4974         r8153_u2p3en(tp, false);
4975         r8153_aldps_en(tp, false);
4976         r8153_first_init(tp);
4977         r8153_aldps_en(tp, true);
4978
4979         switch (tp->version) {
4980         case RTL_VER_03:
4981         case RTL_VER_04:
4982                 break;
4983         case RTL_VER_05:
4984         case RTL_VER_06:
4985         default:
4986                 r8153_u2p3en(tp, true);
4987                 break;
4988         }
4989
4990         r8153_u1u2en(tp, true);
4991 }
4992
4993 static void rtl8153_down(struct r8152 *tp)
4994 {
4995         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
4996                 rtl_drop_queued_tx(tp);
4997                 return;
4998         }
4999
5000         r8153_u1u2en(tp, false);
5001         r8153_u2p3en(tp, false);
5002         r8153_power_cut_en(tp, false);
5003         r8153_aldps_en(tp, false);
5004         r8153_enter_oob(tp);
5005         r8153_aldps_en(tp, true);
5006 }
5007
5008 static void rtl8153b_up(struct r8152 *tp)
5009 {
5010         u32 ocp_data;
5011
5012         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5013                 return;
5014
5015         r8153b_u1u2en(tp, false);
5016         r8153_u2p3en(tp, false);
5017         r8153_aldps_en(tp, false);
5018
5019         r8153_first_init(tp);
5020         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
5021
5022         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5023         ocp_data &= ~PLA_MCU_SPDWN_EN;
5024         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5025
5026         r8153_aldps_en(tp, true);
5027         r8153b_u1u2en(tp, true);
5028 }
5029
5030 static void rtl8153b_down(struct r8152 *tp)
5031 {
5032         u32 ocp_data;
5033
5034         if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
5035                 rtl_drop_queued_tx(tp);
5036                 return;
5037         }
5038
5039         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5040         ocp_data |= PLA_MCU_SPDWN_EN;
5041         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5042
5043         r8153b_u1u2en(tp, false);
5044         r8153_u2p3en(tp, false);
5045         r8153b_power_cut_en(tp, false);
5046         r8153_aldps_en(tp, false);
5047         r8153_enter_oob(tp);
5048         r8153_aldps_en(tp, true);
5049 }
5050
5051 static bool rtl8152_in_nway(struct r8152 *tp)
5052 {
5053         u16 nway_state;
5054
5055         ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
5056         tp->ocp_base = 0x2000;
5057         ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c);         /* phy state */
5058         nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
5059
5060         /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
5061         if (nway_state & 0xc000)
5062                 return false;
5063         else
5064                 return true;
5065 }
5066
5067 static bool rtl8153_in_nway(struct r8152 *tp)
5068 {
5069         u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
5070
5071         if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
5072                 return false;
5073         else
5074                 return true;
5075 }
5076
5077 static void set_carrier(struct r8152 *tp)
5078 {
5079         struct net_device *netdev = tp->netdev;
5080         struct napi_struct *napi = &tp->napi;
5081         u8 speed;
5082
5083         speed = rtl8152_get_speed(tp);
5084
5085         if (speed & LINK_STATUS) {
5086                 if (!netif_carrier_ok(netdev)) {
5087                         tp->rtl_ops.enable(tp);
5088                         netif_stop_queue(netdev);
5089                         napi_disable(napi);
5090                         netif_carrier_on(netdev);
5091                         rtl_start_rx(tp);
5092                         clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
5093                         _rtl8152_set_rx_mode(netdev);
5094                         napi_enable(&tp->napi);
5095                         netif_wake_queue(netdev);
5096                         netif_info(tp, link, netdev, "carrier on\n");
5097                 } else if (netif_queue_stopped(netdev) &&
5098                            skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
5099                         netif_wake_queue(netdev);
5100                 }
5101         } else {
5102                 if (netif_carrier_ok(netdev)) {
5103                         netif_carrier_off(netdev);
5104                         tasklet_disable(&tp->tx_tl);
5105                         napi_disable(napi);
5106                         tp->rtl_ops.disable(tp);
5107                         napi_enable(napi);
5108                         tasklet_enable(&tp->tx_tl);
5109                         netif_info(tp, link, netdev, "carrier off\n");
5110                 }
5111         }
5112 }
5113
5114 static void rtl_work_func_t(struct work_struct *work)
5115 {
5116         struct r8152 *tp = container_of(work, struct r8152, schedule.work);
5117
5118         /* If the device is unplugged or !netif_running(), the workqueue
5119          * doesn't need to wake the device, and could return directly.
5120          */
5121         if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
5122                 return;
5123
5124         if (usb_autopm_get_interface(tp->intf) < 0)
5125                 return;
5126
5127         if (!test_bit(WORK_ENABLE, &tp->flags))
5128                 goto out1;
5129
5130         if (!mutex_trylock(&tp->control)) {
5131                 schedule_delayed_work(&tp->schedule, 0);
5132                 goto out1;
5133         }
5134
5135         if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
5136                 set_carrier(tp);
5137
5138         if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
5139                 _rtl8152_set_rx_mode(tp->netdev);
5140
5141         /* don't schedule tasket before linking */
5142         if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) &&
5143             netif_carrier_ok(tp->netdev))
5144                 tasklet_schedule(&tp->tx_tl);
5145
5146         mutex_unlock(&tp->control);
5147
5148 out1:
5149         usb_autopm_put_interface(tp->intf);
5150 }
5151
5152 static void rtl_hw_phy_work_func_t(struct work_struct *work)
5153 {
5154         struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
5155
5156         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5157                 return;
5158
5159         if (usb_autopm_get_interface(tp->intf) < 0)
5160                 return;
5161
5162         mutex_lock(&tp->control);
5163
5164         if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {
5165                 tp->rtl_fw.retry = false;
5166                 tp->rtl_fw.fw = NULL;
5167
5168                 /* Delay execution in case request_firmware() is not ready yet.
5169                  */
5170                 queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10);
5171                 goto ignore_once;
5172         }
5173
5174         tp->rtl_ops.hw_phy_cfg(tp);
5175
5176         rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex,
5177                           tp->advertising);
5178
5179 ignore_once:
5180         mutex_unlock(&tp->control);
5181
5182         usb_autopm_put_interface(tp->intf);
5183 }
5184
5185 #ifdef CONFIG_PM_SLEEP
5186 static int rtl_notifier(struct notifier_block *nb, unsigned long action,
5187                         void *data)
5188 {
5189         struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
5190
5191         switch (action) {
5192         case PM_HIBERNATION_PREPARE:
5193         case PM_SUSPEND_PREPARE:
5194                 usb_autopm_get_interface(tp->intf);
5195                 break;
5196
5197         case PM_POST_HIBERNATION:
5198         case PM_POST_SUSPEND:
5199                 usb_autopm_put_interface(tp->intf);
5200                 break;
5201
5202         case PM_POST_RESTORE:
5203         case PM_RESTORE_PREPARE:
5204         default:
5205                 break;
5206         }
5207
5208         return NOTIFY_DONE;
5209 }
5210 #endif
5211
5212 static int rtl8152_open(struct net_device *netdev)
5213 {
5214         struct r8152 *tp = netdev_priv(netdev);
5215         int res = 0;
5216
5217         if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) {
5218                 cancel_delayed_work_sync(&tp->hw_phy_work);
5219                 rtl_hw_phy_work_func_t(&tp->hw_phy_work.work);
5220         }
5221
5222         res = alloc_all_mem(tp);
5223         if (res)
5224                 goto out;
5225
5226         res = usb_autopm_get_interface(tp->intf);
5227         if (res < 0)
5228                 goto out_free;
5229
5230         mutex_lock(&tp->control);
5231
5232         tp->rtl_ops.up(tp);
5233
5234         netif_carrier_off(netdev);
5235         netif_start_queue(netdev);
5236         set_bit(WORK_ENABLE, &tp->flags);
5237
5238         res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
5239         if (res) {
5240                 if (res == -ENODEV)
5241                         netif_device_detach(tp->netdev);
5242                 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
5243                            res);
5244                 goto out_unlock;
5245         }
5246         napi_enable(&tp->napi);
5247         tasklet_enable(&tp->tx_tl);
5248
5249         mutex_unlock(&tp->control);
5250
5251         usb_autopm_put_interface(tp->intf);
5252 #ifdef CONFIG_PM_SLEEP
5253         tp->pm_notifier.notifier_call = rtl_notifier;
5254         register_pm_notifier(&tp->pm_notifier);
5255 #endif
5256         return 0;
5257
5258 out_unlock:
5259         mutex_unlock(&tp->control);
5260         usb_autopm_put_interface(tp->intf);
5261 out_free:
5262         free_all_mem(tp);
5263 out:
5264         return res;
5265 }
5266
5267 static int rtl8152_close(struct net_device *netdev)
5268 {
5269         struct r8152 *tp = netdev_priv(netdev);
5270         int res = 0;
5271
5272 #ifdef CONFIG_PM_SLEEP
5273         unregister_pm_notifier(&tp->pm_notifier);
5274 #endif
5275         tasklet_disable(&tp->tx_tl);
5276         clear_bit(WORK_ENABLE, &tp->flags);
5277         usb_kill_urb(tp->intr_urb);
5278         cancel_delayed_work_sync(&tp->schedule);
5279         napi_disable(&tp->napi);
5280         netif_stop_queue(netdev);
5281
5282         res = usb_autopm_get_interface(tp->intf);
5283         if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
5284                 rtl_drop_queued_tx(tp);
5285                 rtl_stop_rx(tp);
5286         } else {
5287                 mutex_lock(&tp->control);
5288
5289                 tp->rtl_ops.down(tp);
5290
5291                 mutex_unlock(&tp->control);
5292
5293                 usb_autopm_put_interface(tp->intf);
5294         }
5295
5296         free_all_mem(tp);
5297
5298         return res;
5299 }
5300
5301 static void rtl_tally_reset(struct r8152 *tp)
5302 {
5303         u32 ocp_data;
5304
5305         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
5306         ocp_data |= TALLY_RESET;
5307         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
5308 }
5309
5310 static void r8152b_init(struct r8152 *tp)
5311 {
5312         u32 ocp_data;
5313         u16 data;
5314
5315         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5316                 return;
5317
5318         data = r8152_mdio_read(tp, MII_BMCR);
5319         if (data & BMCR_PDOWN) {
5320                 data &= ~BMCR_PDOWN;
5321                 r8152_mdio_write(tp, MII_BMCR, data);
5322         }
5323
5324         r8152_aldps_en(tp, false);
5325
5326         if (tp->version == RTL_VER_01) {
5327                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
5328                 ocp_data &= ~LED_MODE_MASK;
5329                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
5330         }
5331
5332         r8152_power_cut_en(tp, false);
5333
5334         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5335         ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
5336         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5337         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
5338         ocp_data &= ~MCU_CLK_RATIO_MASK;
5339         ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
5340         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
5341         ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
5342                    SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
5343         ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
5344
5345         rtl_tally_reset(tp);
5346
5347         /* enable rx aggregation */
5348         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5349         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5350         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5351 }
5352
5353 static void r8153_init(struct r8152 *tp)
5354 {
5355         u32 ocp_data;
5356         u16 data;
5357         int i;
5358
5359         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5360                 return;
5361
5362         r8153_u1u2en(tp, false);
5363
5364         for (i = 0; i < 500; i++) {
5365                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
5366                     AUTOLOAD_DONE)
5367                         break;
5368                 msleep(20);
5369         }
5370
5371         data = r8153_phy_status(tp, 0);
5372
5373         if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
5374             tp->version == RTL_VER_05)
5375                 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
5376
5377         data = r8152_mdio_read(tp, MII_BMCR);
5378         if (data & BMCR_PDOWN) {
5379                 data &= ~BMCR_PDOWN;
5380                 r8152_mdio_write(tp, MII_BMCR, data);
5381         }
5382
5383         data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
5384
5385         r8153_u2p3en(tp, false);
5386
5387         if (tp->version == RTL_VER_04) {
5388                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
5389                 ocp_data &= ~pwd_dn_scale_mask;
5390                 ocp_data |= pwd_dn_scale(96);
5391                 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
5392
5393                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5394                 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5395                 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5396         } else if (tp->version == RTL_VER_05) {
5397                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
5398                 ocp_data &= ~ECM_ALDPS;
5399                 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
5400
5401                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
5402                 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
5403                         ocp_data &= ~DYNAMIC_BURST;
5404                 else
5405                         ocp_data |= DYNAMIC_BURST;
5406                 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
5407         } else if (tp->version == RTL_VER_06) {
5408                 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
5409                 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
5410                         ocp_data &= ~DYNAMIC_BURST;
5411                 else
5412                         ocp_data |= DYNAMIC_BURST;
5413                 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
5414
5415                 r8153_queue_wake(tp, false);
5416
5417                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
5418                 if (rtl8152_get_speed(tp) & LINK_STATUS)
5419                         ocp_data |= CUR_LINK_OK;
5420                 else
5421                         ocp_data &= ~CUR_LINK_OK;
5422                 ocp_data |= POLL_LINK_CHG;
5423                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
5424         }
5425
5426         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
5427         ocp_data |= EP4_FULL_FC;
5428         ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
5429
5430         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
5431         ocp_data &= ~TIMER11_EN;
5432         ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
5433
5434         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
5435         ocp_data &= ~LED_MODE_MASK;
5436         ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
5437
5438         ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
5439         if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
5440                 ocp_data |= LPM_TIMER_500MS;
5441         else
5442                 ocp_data |= LPM_TIMER_500US;
5443         ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
5444
5445         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
5446         ocp_data &= ~SEN_VAL_MASK;
5447         ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
5448         ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
5449
5450         ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
5451
5452         r8153_power_cut_en(tp, false);
5453         rtl_runtime_suspend_enable(tp, false);
5454         r8153_u1u2en(tp, true);
5455         r8153_mac_clk_spd(tp, false);
5456         usb_enable_lpm(tp->udev);
5457
5458         /* rx aggregation */
5459         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5460         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5461         if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
5462                 ocp_data |= RX_AGG_DISABLE;
5463
5464         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5465
5466         rtl_tally_reset(tp);
5467
5468         switch (tp->udev->speed) {
5469         case USB_SPEED_SUPER:
5470         case USB_SPEED_SUPER_PLUS:
5471                 tp->coalesce = COALESCE_SUPER;
5472                 break;
5473         case USB_SPEED_HIGH:
5474                 tp->coalesce = COALESCE_HIGH;
5475                 break;
5476         default:
5477                 tp->coalesce = COALESCE_SLOW;
5478                 break;
5479         }
5480 }
5481
5482 static void r8153b_init(struct r8152 *tp)
5483 {
5484         u32 ocp_data;
5485         u16 data;
5486         int i;
5487
5488         if (test_bit(RTL8152_UNPLUG, &tp->flags))
5489                 return;
5490
5491         r8153b_u1u2en(tp, false);
5492
5493         for (i = 0; i < 500; i++) {
5494                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
5495                     AUTOLOAD_DONE)
5496                         break;
5497                 msleep(20);
5498         }
5499
5500         data = r8153_phy_status(tp, 0);
5501
5502         data = r8152_mdio_read(tp, MII_BMCR);
5503         if (data & BMCR_PDOWN) {
5504                 data &= ~BMCR_PDOWN;
5505                 r8152_mdio_write(tp, MII_BMCR, data);
5506         }
5507
5508         data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
5509
5510         r8153_u2p3en(tp, false);
5511
5512         /* MSC timer = 0xfff * 8ms = 32760 ms */
5513         ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
5514
5515         /* U1/U2/L1 idle timer. 500 us */
5516         ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
5517
5518         r8153b_power_cut_en(tp, false);
5519         r8153b_ups_en(tp, false);
5520         r8153_queue_wake(tp, false);
5521         rtl_runtime_suspend_enable(tp, false);
5522
5523         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
5524         if (rtl8152_get_speed(tp) & LINK_STATUS)
5525                 ocp_data |= CUR_LINK_OK;
5526         else
5527                 ocp_data &= ~CUR_LINK_OK;
5528         ocp_data |= POLL_LINK_CHG;
5529         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
5530         r8153b_u1u2en(tp, true);
5531         usb_enable_lpm(tp->udev);
5532
5533         /* MAC clock speed down */
5534         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
5535         ocp_data |= MAC_CLK_SPDWN_EN;
5536         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
5537
5538         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
5539         ocp_data &= ~PLA_MCU_SPDWN_EN;
5540         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
5541
5542         if (tp->version == RTL_VER_09) {
5543                 /* Disable Test IO for 32QFN */
5544                 if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
5545                         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5546                         ocp_data |= TEST_IO_OFF;
5547                         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5548                 }
5549         }
5550
5551         set_bit(GREEN_ETHERNET, &tp->flags);
5552
5553         /* rx aggregation */
5554         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
5555         ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
5556         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
5557
5558         rtl_tally_reset(tp);
5559
5560         tp->coalesce = 15000;   /* 15 us */
5561 }
5562
5563 static int rtl8152_pre_reset(struct usb_interface *intf)
5564 {
5565         struct r8152 *tp = usb_get_intfdata(intf);
5566         struct net_device *netdev;
5567
5568         if (!tp)
5569                 return 0;
5570
5571         netdev = tp->netdev;
5572         if (!netif_running(netdev))
5573                 return 0;
5574
5575         netif_stop_queue(netdev);
5576         tasklet_disable(&tp->tx_tl);
5577         clear_bit(WORK_ENABLE, &tp->flags);
5578         usb_kill_urb(tp->intr_urb);
5579         cancel_delayed_work_sync(&tp->schedule);
5580         napi_disable(&tp->napi);
5581         if (netif_carrier_ok(netdev)) {
5582                 mutex_lock(&tp->control);
5583                 tp->rtl_ops.disable(tp);
5584                 mutex_unlock(&tp->control);
5585         }
5586
5587         return 0;
5588 }
5589
5590 static int rtl8152_post_reset(struct usb_interface *intf)
5591 {
5592         struct r8152 *tp = usb_get_intfdata(intf);
5593         struct net_device *netdev;
5594         struct sockaddr sa;
5595
5596         if (!tp)
5597                 return 0;
5598
5599         /* reset the MAC adddress in case of policy change */
5600         if (determine_ethernet_addr(tp, &sa) >= 0) {
5601                 rtnl_lock();
5602                 dev_set_mac_address (tp->netdev, &sa, NULL);
5603                 rtnl_unlock();
5604         }
5605
5606         netdev = tp->netdev;
5607         if (!netif_running(netdev))
5608                 return 0;
5609
5610         set_bit(WORK_ENABLE, &tp->flags);
5611         if (netif_carrier_ok(netdev)) {
5612                 mutex_lock(&tp->control);
5613                 tp->rtl_ops.enable(tp);
5614                 rtl_start_rx(tp);
5615                 _rtl8152_set_rx_mode(netdev);
5616                 mutex_unlock(&tp->control);
5617         }
5618
5619         napi_enable(&tp->napi);
5620         tasklet_enable(&tp->tx_tl);
5621         netif_wake_queue(netdev);
5622         usb_submit_urb(tp->intr_urb, GFP_KERNEL);
5623
5624         if (!list_empty(&tp->rx_done))
5625                 napi_schedule(&tp->napi);
5626
5627         return 0;
5628 }
5629
5630 static bool delay_autosuspend(struct r8152 *tp)
5631 {
5632         bool sw_linking = !!netif_carrier_ok(tp->netdev);
5633         bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
5634
5635         /* This means a linking change occurs and the driver doesn't detect it,
5636          * yet. If the driver has disabled tx/rx and hw is linking on, the
5637          * device wouldn't wake up by receiving any packet.
5638          */
5639         if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
5640                 return true;
5641
5642         /* If the linking down is occurred by nway, the device may miss the
5643          * linking change event. And it wouldn't wake when linking on.
5644          */
5645         if (!sw_linking && tp->rtl_ops.in_nway(tp))
5646                 return true;
5647         else if (!skb_queue_empty(&tp->tx_queue))
5648                 return true;
5649         else
5650                 return false;
5651 }
5652
5653 static int rtl8152_runtime_resume(struct r8152 *tp)
5654 {
5655         struct net_device *netdev = tp->netdev;
5656
5657         if (netif_running(netdev) && netdev->flags & IFF_UP) {
5658                 struct napi_struct *napi = &tp->napi;
5659
5660                 tp->rtl_ops.autosuspend_en(tp, false);
5661                 napi_disable(napi);
5662                 set_bit(WORK_ENABLE, &tp->flags);
5663
5664                 if (netif_carrier_ok(netdev)) {
5665                         if (rtl8152_get_speed(tp) & LINK_STATUS) {
5666                                 rtl_start_rx(tp);
5667                         } else {
5668                                 netif_carrier_off(netdev);
5669                                 tp->rtl_ops.disable(tp);
5670                                 netif_info(tp, link, netdev, "linking down\n");
5671                         }
5672                 }
5673
5674                 napi_enable(napi);
5675                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5676                 smp_mb__after_atomic();
5677
5678                 if (!list_empty(&tp->rx_done))
5679                         napi_schedule(&tp->napi);
5680
5681                 usb_submit_urb(tp->intr_urb, GFP_NOIO);
5682         } else {
5683                 if (netdev->flags & IFF_UP)
5684                         tp->rtl_ops.autosuspend_en(tp, false);
5685
5686                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5687         }
5688
5689         return 0;
5690 }
5691
5692 static int rtl8152_system_resume(struct r8152 *tp)
5693 {
5694         struct net_device *netdev = tp->netdev;
5695
5696         netif_device_attach(netdev);
5697
5698         if (netif_running(netdev) && (netdev->flags & IFF_UP)) {
5699                 tp->rtl_ops.up(tp);
5700                 netif_carrier_off(netdev);
5701                 set_bit(WORK_ENABLE, &tp->flags);
5702                 usb_submit_urb(tp->intr_urb, GFP_NOIO);
5703         }
5704
5705         return 0;
5706 }
5707
5708 static int rtl8152_runtime_suspend(struct r8152 *tp)
5709 {
5710         struct net_device *netdev = tp->netdev;
5711         int ret = 0;
5712
5713         set_bit(SELECTIVE_SUSPEND, &tp->flags);
5714         smp_mb__after_atomic();
5715
5716         if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
5717                 u32 rcr = 0;
5718
5719                 if (netif_carrier_ok(netdev)) {
5720                         u32 ocp_data;
5721
5722                         rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5723                         ocp_data = rcr & ~RCR_ACPT_ALL;
5724                         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5725                         rxdy_gated_en(tp, true);
5726                         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
5727                                                  PLA_OOB_CTRL);
5728                         if (!(ocp_data & RXFIFO_EMPTY)) {
5729                                 rxdy_gated_en(tp, false);
5730                                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
5731                                 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5732                                 smp_mb__after_atomic();
5733                                 ret = -EBUSY;
5734                                 goto out1;
5735                         }
5736                 }
5737
5738                 clear_bit(WORK_ENABLE, &tp->flags);
5739                 usb_kill_urb(tp->intr_urb);
5740
5741                 tp->rtl_ops.autosuspend_en(tp, true);
5742
5743                 if (netif_carrier_ok(netdev)) {
5744                         struct napi_struct *napi = &tp->napi;
5745
5746                         napi_disable(napi);
5747                         rtl_stop_rx(tp);
5748                         rxdy_gated_en(tp, false);
5749                         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
5750                         napi_enable(napi);
5751                 }
5752
5753                 if (delay_autosuspend(tp)) {
5754                         rtl8152_runtime_resume(tp);
5755                         ret = -EBUSY;
5756                 }
5757         }
5758
5759 out1:
5760         return ret;
5761 }
5762
5763 static int rtl8152_system_suspend(struct r8152 *tp)
5764 {
5765         struct net_device *netdev = tp->netdev;
5766
5767         netif_device_detach(netdev);
5768
5769         if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
5770                 struct napi_struct *napi = &tp->napi;
5771
5772                 clear_bit(WORK_ENABLE, &tp->flags);
5773                 usb_kill_urb(tp->intr_urb);
5774                 tasklet_disable(&tp->tx_tl);
5775                 napi_disable(napi);
5776                 cancel_delayed_work_sync(&tp->schedule);
5777                 tp->rtl_ops.down(tp);
5778                 napi_enable(napi);
5779                 tasklet_enable(&tp->tx_tl);
5780         }
5781
5782         return 0;
5783 }
5784
5785 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
5786 {
5787         struct r8152 *tp = usb_get_intfdata(intf);
5788         int ret;
5789
5790         mutex_lock(&tp->control);
5791
5792         if (PMSG_IS_AUTO(message))
5793                 ret = rtl8152_runtime_suspend(tp);
5794         else
5795                 ret = rtl8152_system_suspend(tp);
5796
5797         mutex_unlock(&tp->control);
5798
5799         return ret;
5800 }
5801
5802 static int rtl8152_resume(struct usb_interface *intf)
5803 {
5804         struct r8152 *tp = usb_get_intfdata(intf);
5805         int ret;
5806
5807         mutex_lock(&tp->control);
5808
5809         if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
5810                 ret = rtl8152_runtime_resume(tp);
5811         else
5812                 ret = rtl8152_system_resume(tp);
5813
5814         mutex_unlock(&tp->control);
5815
5816         return ret;
5817 }
5818
5819 static int rtl8152_reset_resume(struct usb_interface *intf)
5820 {
5821         struct r8152 *tp = usb_get_intfdata(intf);
5822
5823         clear_bit(SELECTIVE_SUSPEND, &tp->flags);
5824         tp->rtl_ops.init(tp);
5825         queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
5826         set_ethernet_addr(tp);
5827         return rtl8152_resume(intf);
5828 }
5829
5830 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5831 {
5832         struct r8152 *tp = netdev_priv(dev);
5833
5834         if (usb_autopm_get_interface(tp->intf) < 0)
5835                 return;
5836
5837         if (!rtl_can_wakeup(tp)) {
5838                 wol->supported = 0;
5839                 wol->wolopts = 0;
5840         } else {
5841                 mutex_lock(&tp->control);
5842                 wol->supported = WAKE_ANY;
5843                 wol->wolopts = __rtl_get_wol(tp);
5844                 mutex_unlock(&tp->control);
5845         }
5846
5847         usb_autopm_put_interface(tp->intf);
5848 }
5849
5850 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5851 {
5852         struct r8152 *tp = netdev_priv(dev);
5853         int ret;
5854
5855         if (!rtl_can_wakeup(tp))
5856                 return -EOPNOTSUPP;
5857
5858         if (wol->wolopts & ~WAKE_ANY)
5859                 return -EINVAL;
5860
5861         ret = usb_autopm_get_interface(tp->intf);
5862         if (ret < 0)
5863                 goto out_set_wol;
5864
5865         mutex_lock(&tp->control);
5866
5867         __rtl_set_wol(tp, wol->wolopts);
5868         tp->saved_wolopts = wol->wolopts & WAKE_ANY;
5869
5870         mutex_unlock(&tp->control);
5871
5872         usb_autopm_put_interface(tp->intf);
5873
5874 out_set_wol:
5875         return ret;
5876 }
5877
5878 static u32 rtl8152_get_msglevel(struct net_device *dev)
5879 {
5880         struct r8152 *tp = netdev_priv(dev);
5881
5882         return tp->msg_enable;
5883 }
5884
5885 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
5886 {
5887         struct r8152 *tp = netdev_priv(dev);
5888
5889         tp->msg_enable = value;
5890 }
5891
5892 static void rtl8152_get_drvinfo(struct net_device *netdev,
5893                                 struct ethtool_drvinfo *info)
5894 {
5895         struct r8152 *tp = netdev_priv(netdev);
5896
5897         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
5898         strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
5899         usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
5900         if (!IS_ERR_OR_NULL(tp->rtl_fw.fw))
5901                 strlcpy(info->fw_version, tp->rtl_fw.version,
5902                         sizeof(info->fw_version));
5903 }
5904
5905 static
5906 int rtl8152_get_link_ksettings(struct net_device *netdev,
5907                                struct ethtool_link_ksettings *cmd)
5908 {
5909         struct r8152 *tp = netdev_priv(netdev);
5910         int ret;
5911
5912         if (!tp->mii.mdio_read)
5913                 return -EOPNOTSUPP;
5914
5915         ret = usb_autopm_get_interface(tp->intf);
5916         if (ret < 0)
5917                 goto out;
5918
5919         mutex_lock(&tp->control);
5920
5921         mii_ethtool_get_link_ksettings(&tp->mii, cmd);
5922
5923         mutex_unlock(&tp->control);
5924
5925         usb_autopm_put_interface(tp->intf);
5926
5927 out:
5928         return ret;
5929 }
5930
5931 static int rtl8152_set_link_ksettings(struct net_device *dev,
5932                                       const struct ethtool_link_ksettings *cmd)
5933 {
5934         struct r8152 *tp = netdev_priv(dev);
5935         u32 advertising = 0;
5936         int ret;
5937
5938         ret = usb_autopm_get_interface(tp->intf);
5939         if (ret < 0)
5940                 goto out;
5941
5942         if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
5943                      cmd->link_modes.advertising))
5944                 advertising |= RTL_ADVERTISED_10_HALF;
5945
5946         if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
5947                      cmd->link_modes.advertising))
5948                 advertising |= RTL_ADVERTISED_10_FULL;
5949
5950         if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
5951                      cmd->link_modes.advertising))
5952                 advertising |= RTL_ADVERTISED_100_HALF;
5953
5954         if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
5955                      cmd->link_modes.advertising))
5956                 advertising |= RTL_ADVERTISED_100_FULL;
5957
5958         if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
5959                      cmd->link_modes.advertising))
5960                 advertising |= RTL_ADVERTISED_1000_HALF;
5961
5962         if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
5963                      cmd->link_modes.advertising))
5964                 advertising |= RTL_ADVERTISED_1000_FULL;
5965
5966         mutex_lock(&tp->control);
5967
5968         ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
5969                                 cmd->base.duplex, advertising);
5970         if (!ret) {
5971                 tp->autoneg = cmd->base.autoneg;
5972                 tp->speed = cmd->base.speed;
5973                 tp->duplex = cmd->base.duplex;
5974                 tp->advertising = advertising;
5975         }
5976
5977         mutex_unlock(&tp->control);
5978
5979         usb_autopm_put_interface(tp->intf);
5980
5981 out:
5982         return ret;
5983 }
5984
5985 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
5986         "tx_packets",
5987         "rx_packets",
5988         "tx_errors",
5989         "rx_errors",
5990         "rx_missed",
5991         "align_errors",
5992         "tx_single_collisions",
5993         "tx_multi_collisions",
5994         "rx_unicast",
5995         "rx_broadcast",
5996         "rx_multicast",
5997         "tx_aborted",
5998         "tx_underrun",
5999 };
6000
6001 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
6002 {
6003         switch (sset) {
6004         case ETH_SS_STATS:
6005                 return ARRAY_SIZE(rtl8152_gstrings);
6006         default:
6007                 return -EOPNOTSUPP;
6008         }
6009 }
6010
6011 static void rtl8152_get_ethtool_stats(struct net_device *dev,
6012                                       struct ethtool_stats *stats, u64 *data)
6013 {
6014         struct r8152 *tp = netdev_priv(dev);
6015         struct tally_counter tally;
6016
6017         if (usb_autopm_get_interface(tp->intf) < 0)
6018                 return;
6019
6020         generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
6021
6022         usb_autopm_put_interface(tp->intf);
6023
6024         data[0] = le64_to_cpu(tally.tx_packets);
6025         data[1] = le64_to_cpu(tally.rx_packets);
6026         data[2] = le64_to_cpu(tally.tx_errors);
6027         data[3] = le32_to_cpu(tally.rx_errors);
6028         data[4] = le16_to_cpu(tally.rx_missed);
6029         data[5] = le16_to_cpu(tally.align_errors);
6030         data[6] = le32_to_cpu(tally.tx_one_collision);
6031         data[7] = le32_to_cpu(tally.tx_multi_collision);
6032         data[8] = le64_to_cpu(tally.rx_unicast);
6033         data[9] = le64_to_cpu(tally.rx_broadcast);
6034         data[10] = le32_to_cpu(tally.rx_multicast);
6035         data[11] = le16_to_cpu(tally.tx_aborted);
6036         data[12] = le16_to_cpu(tally.tx_underrun);
6037 }
6038
6039 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
6040 {
6041         switch (stringset) {
6042         case ETH_SS_STATS:
6043                 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
6044                 break;
6045         }
6046 }
6047
6048 static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
6049 {
6050         u32 lp, adv, supported = 0;
6051         u16 val;
6052
6053         val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
6054         supported = mmd_eee_cap_to_ethtool_sup_t(val);
6055
6056         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
6057         adv = mmd_eee_adv_to_ethtool_adv_t(val);
6058
6059         val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
6060         lp = mmd_eee_adv_to_ethtool_adv_t(val);
6061
6062         eee->eee_enabled = tp->eee_en;
6063         eee->eee_active = !!(supported & adv & lp);
6064         eee->supported = supported;
6065         eee->advertised = tp->eee_adv;
6066         eee->lp_advertised = lp;
6067
6068         return 0;
6069 }
6070
6071 static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
6072 {
6073         u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
6074
6075         tp->eee_en = eee->eee_enabled;
6076         tp->eee_adv = val;
6077
6078         rtl_eee_enable(tp, tp->eee_en);
6079
6080         return 0;
6081 }
6082
6083 static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
6084 {
6085         u32 lp, adv, supported = 0;
6086         u16 val;
6087
6088         val = ocp_reg_read(tp, OCP_EEE_ABLE);
6089         supported = mmd_eee_cap_to_ethtool_sup_t(val);
6090
6091         val = ocp_reg_read(tp, OCP_EEE_ADV);
6092         adv = mmd_eee_adv_to_ethtool_adv_t(val);
6093
6094         val = ocp_reg_read(tp, OCP_EEE_LPABLE);
6095         lp = mmd_eee_adv_to_ethtool_adv_t(val);
6096
6097         eee->eee_enabled = tp->eee_en;
6098         eee->eee_active = !!(supported & adv & lp);
6099         eee->supported = supported;
6100         eee->advertised = tp->eee_adv;
6101         eee->lp_advertised = lp;
6102
6103         return 0;
6104 }
6105
6106 static int
6107 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
6108 {
6109         struct r8152 *tp = netdev_priv(net);
6110         int ret;
6111
6112         ret = usb_autopm_get_interface(tp->intf);
6113         if (ret < 0)
6114                 goto out;
6115
6116         mutex_lock(&tp->control);
6117
6118         ret = tp->rtl_ops.eee_get(tp, edata);
6119
6120         mutex_unlock(&tp->control);
6121
6122         usb_autopm_put_interface(tp->intf);
6123
6124 out:
6125         return ret;
6126 }
6127
6128 static int
6129 rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
6130 {
6131         struct r8152 *tp = netdev_priv(net);
6132         int ret;
6133
6134         ret = usb_autopm_get_interface(tp->intf);
6135         if (ret < 0)
6136                 goto out;
6137
6138         mutex_lock(&tp->control);
6139
6140         ret = tp->rtl_ops.eee_set(tp, edata);
6141         if (!ret)
6142                 ret = mii_nway_restart(&tp->mii);
6143
6144         mutex_unlock(&tp->control);
6145
6146         usb_autopm_put_interface(tp->intf);
6147
6148 out:
6149         return ret;
6150 }
6151
6152 static int rtl8152_nway_reset(struct net_device *dev)
6153 {
6154         struct r8152 *tp = netdev_priv(dev);
6155         int ret;
6156
6157         ret = usb_autopm_get_interface(tp->intf);
6158         if (ret < 0)
6159                 goto out;
6160
6161         mutex_lock(&tp->control);
6162
6163         ret = mii_nway_restart(&tp->mii);
6164
6165         mutex_unlock(&tp->control);
6166
6167         usb_autopm_put_interface(tp->intf);
6168
6169 out:
6170         return ret;
6171 }
6172
6173 static int rtl8152_get_coalesce(struct net_device *netdev,
6174                                 struct ethtool_coalesce *coalesce)
6175 {
6176         struct r8152 *tp = netdev_priv(netdev);
6177
6178         switch (tp->version) {
6179         case RTL_VER_01:
6180         case RTL_VER_02:
6181         case RTL_VER_07:
6182                 return -EOPNOTSUPP;
6183         default:
6184                 break;
6185         }
6186
6187         coalesce->rx_coalesce_usecs = tp->coalesce;
6188
6189         return 0;
6190 }
6191
6192 static int rtl8152_set_coalesce(struct net_device *netdev,
6193                                 struct ethtool_coalesce *coalesce)
6194 {
6195         struct r8152 *tp = netdev_priv(netdev);
6196         int ret;
6197
6198         switch (tp->version) {
6199         case RTL_VER_01:
6200         case RTL_VER_02:
6201         case RTL_VER_07:
6202                 return -EOPNOTSUPP;
6203         default:
6204                 break;
6205         }
6206
6207         if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
6208                 return -EINVAL;
6209
6210         ret = usb_autopm_get_interface(tp->intf);
6211         if (ret < 0)
6212                 return ret;
6213
6214         mutex_lock(&tp->control);
6215
6216         if (tp->coalesce != coalesce->rx_coalesce_usecs) {
6217                 tp->coalesce = coalesce->rx_coalesce_usecs;
6218
6219                 if (netif_running(netdev) && netif_carrier_ok(netdev)) {
6220                         netif_stop_queue(netdev);
6221                         napi_disable(&tp->napi);
6222                         tp->rtl_ops.disable(tp);
6223                         tp->rtl_ops.enable(tp);
6224                         rtl_start_rx(tp);
6225                         clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
6226                         _rtl8152_set_rx_mode(netdev);
6227                         napi_enable(&tp->napi);
6228                         netif_wake_queue(netdev);
6229                 }
6230         }
6231
6232         mutex_unlock(&tp->control);
6233
6234         usb_autopm_put_interface(tp->intf);
6235
6236         return ret;
6237 }
6238
6239 static int rtl8152_get_tunable(struct net_device *netdev,
6240                                const struct ethtool_tunable *tunable, void *d)
6241 {
6242         struct r8152 *tp = netdev_priv(netdev);
6243
6244         switch (tunable->id) {
6245         case ETHTOOL_RX_COPYBREAK:
6246                 *(u32 *)d = tp->rx_copybreak;
6247                 break;
6248         default:
6249                 return -EOPNOTSUPP;
6250         }
6251
6252         return 0;
6253 }
6254
6255 static int rtl8152_set_tunable(struct net_device *netdev,
6256                                const struct ethtool_tunable *tunable,
6257                                const void *d)
6258 {
6259         struct r8152 *tp = netdev_priv(netdev);
6260         u32 val;
6261
6262         switch (tunable->id) {
6263         case ETHTOOL_RX_COPYBREAK:
6264                 val = *(u32 *)d;
6265                 if (val < ETH_ZLEN) {
6266                         netif_err(tp, rx_err, netdev,
6267                                   "Invalid rx copy break value\n");
6268                         return -EINVAL;
6269                 }
6270
6271                 if (tp->rx_copybreak != val) {
6272                         if (netdev->flags & IFF_UP) {
6273                                 mutex_lock(&tp->control);
6274                                 napi_disable(&tp->napi);
6275                                 tp->rx_copybreak = val;
6276                                 napi_enable(&tp->napi);
6277                                 mutex_unlock(&tp->control);
6278                         } else {
6279                                 tp->rx_copybreak = val;
6280                         }
6281                 }
6282                 break;
6283         default:
6284                 return -EOPNOTSUPP;
6285         }
6286
6287         return 0;
6288 }
6289
6290 static void rtl8152_get_ringparam(struct net_device *netdev,
6291                                   struct ethtool_ringparam *ring)
6292 {
6293         struct r8152 *tp = netdev_priv(netdev);
6294
6295         ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
6296         ring->rx_pending = tp->rx_pending;
6297 }
6298
6299 static int rtl8152_set_ringparam(struct net_device *netdev,
6300                                  struct ethtool_ringparam *ring)
6301 {
6302         struct r8152 *tp = netdev_priv(netdev);
6303
6304         if (ring->rx_pending < (RTL8152_MAX_RX * 2))
6305                 return -EINVAL;
6306
6307         if (tp->rx_pending != ring->rx_pending) {
6308                 if (netdev->flags & IFF_UP) {
6309                         mutex_lock(&tp->control);
6310                         napi_disable(&tp->napi);
6311                         tp->rx_pending = ring->rx_pending;
6312                         napi_enable(&tp->napi);
6313                         mutex_unlock(&tp->control);
6314                 } else {
6315                         tp->rx_pending = ring->rx_pending;
6316                 }
6317         }
6318
6319         return 0;
6320 }
6321
6322 static const struct ethtool_ops ops = {
6323         .get_drvinfo = rtl8152_get_drvinfo,
6324         .get_link = ethtool_op_get_link,
6325         .nway_reset = rtl8152_nway_reset,
6326         .get_msglevel = rtl8152_get_msglevel,
6327         .set_msglevel = rtl8152_set_msglevel,
6328         .get_wol = rtl8152_get_wol,
6329         .set_wol = rtl8152_set_wol,
6330         .get_strings = rtl8152_get_strings,
6331         .get_sset_count = rtl8152_get_sset_count,
6332         .get_ethtool_stats = rtl8152_get_ethtool_stats,
6333         .get_coalesce = rtl8152_get_coalesce,
6334         .set_coalesce = rtl8152_set_coalesce,
6335         .get_eee = rtl_ethtool_get_eee,
6336         .set_eee = rtl_ethtool_set_eee,
6337         .get_link_ksettings = rtl8152_get_link_ksettings,
6338         .set_link_ksettings = rtl8152_set_link_ksettings,
6339         .get_tunable = rtl8152_get_tunable,
6340         .set_tunable = rtl8152_set_tunable,
6341         .get_ringparam = rtl8152_get_ringparam,
6342         .set_ringparam = rtl8152_set_ringparam,
6343 };
6344
6345 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
6346 {
6347         struct r8152 *tp = netdev_priv(netdev);
6348         struct mii_ioctl_data *data = if_mii(rq);
6349         int res;
6350
6351         if (test_bit(RTL8152_UNPLUG, &tp->flags))
6352                 return -ENODEV;
6353
6354         res = usb_autopm_get_interface(tp->intf);
6355         if (res < 0)
6356                 goto out;
6357
6358         switch (cmd) {
6359         case SIOCGMIIPHY:
6360                 data->phy_id = R8152_PHY_ID; /* Internal PHY */
6361                 break;
6362
6363         case SIOCGMIIREG:
6364                 mutex_lock(&tp->control);
6365                 data->val_out = r8152_mdio_read(tp, data->reg_num);
6366                 mutex_unlock(&tp->control);
6367                 break;
6368
6369         case SIOCSMIIREG:
6370                 if (!capable(CAP_NET_ADMIN)) {
6371                         res = -EPERM;
6372                         break;
6373                 }
6374                 mutex_lock(&tp->control);
6375                 r8152_mdio_write(tp, data->reg_num, data->val_in);
6376                 mutex_unlock(&tp->control);
6377                 break;
6378
6379         default:
6380                 res = -EOPNOTSUPP;
6381         }
6382
6383         usb_autopm_put_interface(tp->intf);
6384
6385 out:
6386         return res;
6387 }
6388
6389 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
6390 {
6391         struct r8152 *tp = netdev_priv(dev);
6392         int ret;
6393
6394         switch (tp->version) {
6395         case RTL_VER_01:
6396         case RTL_VER_02:
6397         case RTL_VER_07:
6398                 dev->mtu = new_mtu;
6399                 return 0;
6400         default:
6401                 break;
6402         }
6403
6404         ret = usb_autopm_get_interface(tp->intf);
6405         if (ret < 0)
6406                 return ret;
6407
6408         mutex_lock(&tp->control);
6409
6410         dev->mtu = new_mtu;
6411
6412         if (netif_running(dev)) {
6413                 u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
6414
6415                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
6416
6417                 if (netif_carrier_ok(dev))
6418                         r8153_set_rx_early_size(tp);
6419         }
6420
6421         mutex_unlock(&tp->control);
6422
6423         usb_autopm_put_interface(tp->intf);
6424
6425         return ret;
6426 }
6427
6428 static const struct net_device_ops rtl8152_netdev_ops = {
6429         .ndo_open               = rtl8152_open,
6430         .ndo_stop               = rtl8152_close,
6431         .ndo_do_ioctl           = rtl8152_ioctl,
6432         .ndo_start_xmit         = rtl8152_start_xmit,
6433         .ndo_tx_timeout         = rtl8152_tx_timeout,
6434         .ndo_set_features       = rtl8152_set_features,
6435         .ndo_set_rx_mode        = rtl8152_set_rx_mode,
6436         .ndo_set_mac_address    = rtl8152_set_mac_address,
6437         .ndo_change_mtu         = rtl8152_change_mtu,
6438         .ndo_validate_addr      = eth_validate_addr,
6439         .ndo_features_check     = rtl8152_features_check,
6440 };
6441
6442 static void rtl8152_unload(struct r8152 *tp)
6443 {
6444         if (test_bit(RTL8152_UNPLUG, &tp->flags))
6445                 return;
6446
6447         if (tp->version != RTL_VER_01)
6448                 r8152_power_cut_en(tp, true);
6449 }
6450
6451 static void rtl8153_unload(struct r8152 *tp)
6452 {
6453         if (test_bit(RTL8152_UNPLUG, &tp->flags))
6454                 return;
6455
6456         r8153_power_cut_en(tp, false);
6457 }
6458
6459 static void rtl8153b_unload(struct r8152 *tp)
6460 {
6461         if (test_bit(RTL8152_UNPLUG, &tp->flags))
6462                 return;
6463
6464         r8153b_power_cut_en(tp, false);
6465 }
6466
6467 static int rtl_ops_init(struct r8152 *tp)
6468 {
6469         struct rtl_ops *ops = &tp->rtl_ops;
6470         int ret = 0;
6471
6472         switch (tp->version) {
6473         case RTL_VER_01:
6474         case RTL_VER_02:
6475         case RTL_VER_07:
6476                 ops->init               = r8152b_init;
6477                 ops->enable             = rtl8152_enable;
6478                 ops->disable            = rtl8152_disable;
6479                 ops->up                 = rtl8152_up;
6480                 ops->down               = rtl8152_down;
6481                 ops->unload             = rtl8152_unload;
6482                 ops->eee_get            = r8152_get_eee;
6483                 ops->eee_set            = r8152_set_eee;
6484                 ops->in_nway            = rtl8152_in_nway;
6485                 ops->hw_phy_cfg         = r8152b_hw_phy_cfg;
6486                 ops->autosuspend_en     = rtl_runtime_suspend_enable;
6487                 tp->rx_buf_sz           = 16 * 1024;
6488                 tp->eee_en              = true;
6489                 tp->eee_adv             = MDIO_EEE_100TX;
6490                 break;
6491
6492         case RTL_VER_03:
6493         case RTL_VER_04:
6494         case RTL_VER_05:
6495         case RTL_VER_06:
6496                 ops->init               = r8153_init;
6497                 ops->enable             = rtl8153_enable;
6498                 ops->disable            = rtl8153_disable;
6499                 ops->up                 = rtl8153_up;
6500                 ops->down               = rtl8153_down;
6501                 ops->unload             = rtl8153_unload;
6502                 ops->eee_get            = r8153_get_eee;
6503                 ops->eee_set            = r8152_set_eee;
6504                 ops->in_nway            = rtl8153_in_nway;
6505                 ops->hw_phy_cfg         = r8153_hw_phy_cfg;
6506                 ops->autosuspend_en     = rtl8153_runtime_enable;
6507                 tp->rx_buf_sz           = 32 * 1024;
6508                 tp->eee_en              = true;
6509                 tp->eee_adv             = MDIO_EEE_1000T | MDIO_EEE_100TX;
6510                 break;
6511
6512         case RTL_VER_08:
6513         case RTL_VER_09:
6514                 ops->init               = r8153b_init;
6515                 ops->enable             = rtl8153_enable;
6516                 ops->disable            = rtl8153_disable;
6517                 ops->up                 = rtl8153b_up;
6518                 ops->down               = rtl8153b_down;
6519                 ops->unload             = rtl8153b_unload;
6520                 ops->eee_get            = r8153_get_eee;
6521                 ops->eee_set            = r8152_set_eee;
6522                 ops->in_nway            = rtl8153_in_nway;
6523                 ops->hw_phy_cfg         = r8153b_hw_phy_cfg;
6524                 ops->autosuspend_en     = rtl8153b_runtime_enable;
6525                 tp->rx_buf_sz           = 32 * 1024;
6526                 tp->eee_en              = true;
6527                 tp->eee_adv             = MDIO_EEE_1000T | MDIO_EEE_100TX;
6528                 break;
6529
6530         default:
6531                 ret = -ENODEV;
6532                 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
6533                 break;
6534         }
6535
6536         return ret;
6537 }
6538
6539 #define FIRMWARE_8153A_2        "rtl_nic/rtl8153a-2.fw"
6540 #define FIRMWARE_8153A_3        "rtl_nic/rtl8153a-3.fw"
6541 #define FIRMWARE_8153A_4        "rtl_nic/rtl8153a-4.fw"
6542 #define FIRMWARE_8153B_2        "rtl_nic/rtl8153b-2.fw"
6543
6544 MODULE_FIRMWARE(FIRMWARE_8153A_2);
6545 MODULE_FIRMWARE(FIRMWARE_8153A_3);
6546 MODULE_FIRMWARE(FIRMWARE_8153A_4);
6547 MODULE_FIRMWARE(FIRMWARE_8153B_2);
6548
6549 static int rtl_fw_init(struct r8152 *tp)
6550 {
6551         struct rtl_fw *rtl_fw = &tp->rtl_fw;
6552
6553         switch (tp->version) {
6554         case RTL_VER_04:
6555                 rtl_fw->fw_name         = FIRMWARE_8153A_2;
6556                 rtl_fw->pre_fw          = r8153_pre_firmware_1;
6557                 rtl_fw->post_fw         = r8153_post_firmware_1;
6558                 break;
6559         case RTL_VER_05:
6560                 rtl_fw->fw_name         = FIRMWARE_8153A_3;
6561                 rtl_fw->pre_fw          = r8153_pre_firmware_2;
6562                 rtl_fw->post_fw         = r8153_post_firmware_2;
6563                 break;
6564         case RTL_VER_06:
6565                 rtl_fw->fw_name         = FIRMWARE_8153A_4;
6566                 rtl_fw->post_fw         = r8153_post_firmware_3;
6567                 break;
6568         case RTL_VER_09:
6569                 rtl_fw->fw_name         = FIRMWARE_8153B_2;
6570                 rtl_fw->pre_fw          = r8153b_pre_firmware_1;
6571                 rtl_fw->post_fw         = r8153b_post_firmware_1;
6572                 break;
6573         default:
6574                 break;
6575         }
6576
6577         return 0;
6578 }
6579
6580 static u8 rtl_get_version(struct usb_interface *intf)
6581 {
6582         struct usb_device *udev = interface_to_usbdev(intf);
6583         u32 ocp_data = 0;
6584         __le32 *tmp;
6585         u8 version;
6586         int ret;
6587
6588         tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
6589         if (!tmp)
6590                 return 0;
6591
6592         ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
6593                               RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
6594                               PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
6595         if (ret > 0)
6596                 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
6597
6598         kfree(tmp);
6599
6600         switch (ocp_data) {
6601         case 0x4c00:
6602                 version = RTL_VER_01;
6603                 break;
6604         case 0x4c10:
6605                 version = RTL_VER_02;
6606                 break;
6607         case 0x5c00:
6608                 version = RTL_VER_03;
6609                 break;
6610         case 0x5c10:
6611                 version = RTL_VER_04;
6612                 break;
6613         case 0x5c20:
6614                 version = RTL_VER_05;
6615                 break;
6616         case 0x5c30:
6617                 version = RTL_VER_06;
6618                 break;
6619         case 0x4800:
6620                 version = RTL_VER_07;
6621                 break;
6622         case 0x6000:
6623                 version = RTL_VER_08;
6624                 break;
6625         case 0x6010:
6626                 version = RTL_VER_09;
6627                 break;
6628         default:
6629                 version = RTL_VER_UNKNOWN;
6630                 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
6631                 break;
6632         }
6633
6634         dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
6635
6636         return version;
6637 }
6638
6639 static int rtl8152_probe(struct usb_interface *intf,
6640                          const struct usb_device_id *id)
6641 {
6642         struct usb_device *udev = interface_to_usbdev(intf);
6643         u8 version = rtl_get_version(intf);
6644         struct r8152 *tp;
6645         struct net_device *netdev;
6646         int ret;
6647
6648         if (version == RTL_VER_UNKNOWN)
6649                 return -ENODEV;
6650
6651         if (udev->actconfig->desc.bConfigurationValue != 1) {
6652                 usb_driver_set_configuration(udev, 1);
6653                 return -ENODEV;
6654         }
6655
6656         if (intf->cur_altsetting->desc.bNumEndpoints < 3)
6657                 return -ENODEV;
6658
6659         usb_reset_device(udev);
6660         netdev = alloc_etherdev(sizeof(struct r8152));
6661         if (!netdev) {
6662                 dev_err(&intf->dev, "Out of memory\n");
6663                 return -ENOMEM;
6664         }
6665
6666         SET_NETDEV_DEV(netdev, &intf->dev);
6667         tp = netdev_priv(netdev);
6668         tp->msg_enable = 0x7FFF;
6669
6670         tp->udev = udev;
6671         tp->netdev = netdev;
6672         tp->intf = intf;
6673         tp->version = version;
6674
6675         switch (version) {
6676         case RTL_VER_01:
6677         case RTL_VER_02:
6678         case RTL_VER_07:
6679                 tp->mii.supports_gmii = 0;
6680                 break;
6681         default:
6682                 tp->mii.supports_gmii = 1;
6683                 break;
6684         }
6685
6686         ret = rtl_ops_init(tp);
6687         if (ret)
6688                 goto out;
6689
6690         rtl_fw_init(tp);
6691
6692         mutex_init(&tp->control);
6693         INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
6694         INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
6695         tasklet_init(&tp->tx_tl, bottom_half, (unsigned long)tp);
6696         tasklet_disable(&tp->tx_tl);
6697
6698         netdev->netdev_ops = &rtl8152_netdev_ops;
6699         netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
6700
6701         netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6702                             NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
6703                             NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
6704                             NETIF_F_HW_VLAN_CTAG_TX;
6705         netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6706                               NETIF_F_TSO | NETIF_F_FRAGLIST |
6707                               NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
6708                               NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
6709         netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6710                                 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
6711                                 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
6712
6713         if (tp->version == RTL_VER_01) {
6714                 netdev->features &= ~NETIF_F_RXCSUM;
6715                 netdev->hw_features &= ~NETIF_F_RXCSUM;
6716         }
6717
6718         if (le16_to_cpu(udev->descriptor.idVendor) == VENDOR_ID_LENOVO &&
6719             le16_to_cpu(udev->descriptor.idProduct) == 0x3082)
6720                 set_bit(LENOVO_MACPASSTHRU, &tp->flags);
6721
6722         if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
6723             (!strcmp(udev->serial, "000001000000") ||
6724              !strcmp(udev->serial, "000002000000"))) {
6725                 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
6726                 set_bit(DELL_TB_RX_AGG_BUG, &tp->flags);
6727         }
6728
6729         netdev->ethtool_ops = &ops;
6730         netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
6731
6732         /* MTU range: 68 - 1500 or 9194 */
6733         netdev->min_mtu = ETH_MIN_MTU;
6734         switch (tp->version) {
6735         case RTL_VER_01:
6736         case RTL_VER_02:
6737                 netdev->max_mtu = ETH_DATA_LEN;
6738                 break;
6739         default:
6740                 netdev->max_mtu = RTL8153_MAX_MTU;
6741                 break;
6742         }
6743
6744         tp->mii.dev = netdev;
6745         tp->mii.mdio_read = read_mii_word;
6746         tp->mii.mdio_write = write_mii_word;
6747         tp->mii.phy_id_mask = 0x3f;
6748         tp->mii.reg_num_mask = 0x1f;
6749         tp->mii.phy_id = R8152_PHY_ID;
6750
6751         tp->autoneg = AUTONEG_ENABLE;
6752         tp->speed = SPEED_100;
6753         tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
6754                           RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
6755         if (tp->mii.supports_gmii) {
6756                 tp->speed = SPEED_1000;
6757                 tp->advertising |= RTL_ADVERTISED_1000_FULL;
6758         }
6759         tp->duplex = DUPLEX_FULL;
6760
6761         tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
6762         tp->rx_pending = 10 * RTL8152_MAX_RX;
6763
6764         intf->needs_remote_wakeup = 1;
6765
6766         if (!rtl_can_wakeup(tp))
6767                 __rtl_set_wol(tp, 0);
6768         else
6769                 tp->saved_wolopts = __rtl_get_wol(tp);
6770
6771         tp->rtl_ops.init(tp);
6772 #if IS_BUILTIN(CONFIG_USB_RTL8152)
6773         /* Retry in case request_firmware() is not ready yet. */
6774         tp->rtl_fw.retry = true;
6775 #endif
6776         queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
6777         set_ethernet_addr(tp);
6778
6779         usb_set_intfdata(intf, tp);
6780         netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
6781
6782         ret = register_netdev(netdev);
6783         if (ret != 0) {
6784                 netif_err(tp, probe, netdev, "couldn't register the device\n");
6785                 goto out1;
6786         }
6787
6788         if (tp->saved_wolopts)
6789                 device_set_wakeup_enable(&udev->dev, true);
6790         else
6791                 device_set_wakeup_enable(&udev->dev, false);
6792
6793         netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
6794
6795         return 0;
6796
6797 out1:
6798         tasklet_kill(&tp->tx_tl);
6799         usb_set_intfdata(intf, NULL);
6800 out:
6801         free_netdev(netdev);
6802         return ret;
6803 }
6804
6805 static void rtl8152_disconnect(struct usb_interface *intf)
6806 {
6807         struct r8152 *tp = usb_get_intfdata(intf);
6808
6809         usb_set_intfdata(intf, NULL);
6810         if (tp) {
6811                 rtl_set_unplug(tp);
6812
6813                 unregister_netdev(tp->netdev);
6814                 tasklet_kill(&tp->tx_tl);
6815                 cancel_delayed_work_sync(&tp->hw_phy_work);
6816                 tp->rtl_ops.unload(tp);
6817                 rtl8152_release_firmware(tp);
6818                 free_netdev(tp->netdev);
6819         }
6820 }
6821
6822 #define REALTEK_USB_DEVICE(vend, prod)  \
6823         .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
6824                        USB_DEVICE_ID_MATCH_INT_CLASS, \
6825         .idVendor = (vend), \
6826         .idProduct = (prod), \
6827         .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
6828 }, \
6829 { \
6830         .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
6831                        USB_DEVICE_ID_MATCH_DEVICE, \
6832         .idVendor = (vend), \
6833         .idProduct = (prod), \
6834         .bInterfaceClass = USB_CLASS_COMM, \
6835         .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
6836         .bInterfaceProtocol = USB_CDC_PROTO_NONE
6837
6838 /* table of devices that work with this driver */
6839 static const struct usb_device_id rtl8152_table[] = {
6840         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
6841         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
6842         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
6843         {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
6844         {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
6845         {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
6846         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x304f)},
6847         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3062)},
6848         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3069)},
6849         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3082)},
6850         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7205)},
6851         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x720c)},
6852         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7214)},
6853         {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0xa387)},
6854         {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
6855         {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA,  0x09ff)},
6856         {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK,  0x0601)},
6857         {}
6858 };
6859
6860 MODULE_DEVICE_TABLE(usb, rtl8152_table);
6861
6862 static struct usb_driver rtl8152_driver = {
6863         .name =         MODULENAME,
6864         .id_table =     rtl8152_table,
6865         .probe =        rtl8152_probe,
6866         .disconnect =   rtl8152_disconnect,
6867         .suspend =      rtl8152_suspend,
6868         .resume =       rtl8152_resume,
6869         .reset_resume = rtl8152_reset_resume,
6870         .pre_reset =    rtl8152_pre_reset,
6871         .post_reset =   rtl8152_post_reset,
6872         .supports_autosuspend = 1,
6873         .disable_hub_initiated_lpm = 1,
6874 };
6875
6876 module_usb_driver(rtl8152_driver);
6877
6878 MODULE_AUTHOR(DRIVER_AUTHOR);
6879 MODULE_DESCRIPTION(DRIVER_DESC);
6880 MODULE_LICENSE("GPL");
6881 MODULE_VERSION(DRIVER_VERSION);