drivers/net/wireless/ath/ath9k/ar9002_hw.c

   1 /*
   2  * Copyright (c) 2008-2010 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "ar5008_initvals.h"
  19 #include "ar9001_initvals.h"
  20 #include "ar9002_initvals.h"
  21 #include "ar9002_phy.h"
  22
  23 int modparam_force_new_ani;
  24 module_param_named(force_new_ani, modparam_force_new_ani, int, 0444);
  25 MODULE_PARM_DESC(nohwcrypt, "Force new ANI for AR5008, AR9001, AR9002");
  26
  27 /* General hardware code for the A5008/AR9001/AR9002 hadware families */
  28
  29 static bool ar9002_hw_macversion_supported(u32 macversion)
  30 {
  31         switch (macversion) {
  32         case AR_SREV_VERSION_5416_PCI:
  33         case AR_SREV_VERSION_5416_PCIE:
  34         case AR_SREV_VERSION_9160:
  35         case AR_SREV_VERSION_9100:
  36         case AR_SREV_VERSION_9280:
  37         case AR_SREV_VERSION_9285:
  38         case AR_SREV_VERSION_9287:
  39         case AR_SREV_VERSION_9271:
  40                 return true;
  41         default:
  42                 break;
  43         }
  44         return false;
  45 }
  46
  47 static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
  48 {
  49         if (AR_SREV_9271(ah)) {
  50                 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
  51                                ARRAY_SIZE(ar9271Modes_9271), 6);
  52                 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
  53                                ARRAY_SIZE(ar9271Common_9271), 2);
  54                 INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
  55                                ar9271Common_normal_cck_fir_coeff_9271,
  56                                ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
  57                 INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
  58                                ar9271Common_japan_2484_cck_fir_coeff_9271,
  59                                ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
  60                 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
  61                                ar9271Modes_9271_1_0_only,
  62                                ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
  63                 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
  64                                ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
  65                 INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
  66                                ar9271Modes_high_power_tx_gain_9271,
  67                                ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
  68                 INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
  69                                ar9271Modes_normal_power_tx_gain_9271,
  70                                ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
  71                 return;
  72         }
  73
  74         if (AR_SREV_9287_11_OR_LATER(ah)) {
  75                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
  76                                 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
  77                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
  78                                 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
  79                 if (ah->config.pcie_clock_req)
  80                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
  81                         ar9287PciePhy_clkreq_off_L1_9287_1_1,
  82                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
  83                 else
  84                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
  85                         ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
  86                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
  87                                         2);
  88         } else if (AR_SREV_9287_10_OR_LATER(ah)) {
  89                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
  90                                 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
  91                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
  92                                 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
  93
  94                 if (ah->config.pcie_clock_req)
  95                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
  96                         ar9287PciePhy_clkreq_off_L1_9287_1_0,
  97                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
  98                 else
  99                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 100                         ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
 101                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
 102                                   2);
 103         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 104
 105
 106                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
 107                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 108                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
 109                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 110
 111                 if (ah->config.pcie_clock_req) {
 112                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 113                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 114                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 115                 } else {
 116                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 117                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 118                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 119                                   2);
 120                 }
 121         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 122                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
 123                                ARRAY_SIZE(ar9285Modes_9285), 6);
 124                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
 125                                ARRAY_SIZE(ar9285Common_9285), 2);
 126
 127                 if (ah->config.pcie_clock_req) {
 128                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 129                         ar9285PciePhy_clkreq_off_L1_9285,
 130                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 131                 } else {
 132                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 133                         ar9285PciePhy_clkreq_always_on_L1_9285,
 134                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 135                 }
 136         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 137                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 138                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 139                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 140                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 141
 142                 if (ah->config.pcie_clock_req) {
 143                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 144                                ar9280PciePhy_clkreq_off_L1_9280,
 145                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280), 2);
 146                 } else {
 147                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 148                                ar9280PciePhy_clkreq_always_on_L1_9280,
 149                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 150                 }
 151                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 152                                ar9280Modes_fast_clock_9280_2,
 153                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 154         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 155                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
 156                                ARRAY_SIZE(ar9280Modes_9280), 6);
 157                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
 158                                ARRAY_SIZE(ar9280Common_9280), 2);
 159         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 160                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 161                                ARRAY_SIZE(ar5416Modes_9160), 6);
 162                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 163                                ARRAY_SIZE(ar5416Common_9160), 2);
 164                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 165                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 166                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 167                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 168                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 169                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 170                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 171                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 172                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 173                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 174                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 175                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 176                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 177                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 178                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 179                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 180                 if (AR_SREV_9160_11(ah)) {
 181                         INIT_INI_ARRAY(&ah->iniAddac,
 182                                        ar5416Addac_91601_1,
 183                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 184                 } else {
 185                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 186                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 187                 }
 188         } else if (AR_SREV_9100_OR_LATER(ah)) {
 189                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 190                                ARRAY_SIZE(ar5416Modes_9100), 6);
 191                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 192                                ARRAY_SIZE(ar5416Common_9100), 2);
 193                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 194                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 195                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 196                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 197                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 198                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 199                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 200                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 201                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 202                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 203                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 204                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 205                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 206                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 207                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 208                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 209                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 210                                ARRAY_SIZE(ar5416Addac_9100), 2);
 211         } else {
 212                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 213                                ARRAY_SIZE(ar5416Modes), 6);
 214                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 215                                ARRAY_SIZE(ar5416Common), 2);
 216                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 217                                ARRAY_SIZE(ar5416Bank0), 2);
 218                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 219                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 220                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 221                                ARRAY_SIZE(ar5416Bank1), 2);
 222                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 223                                ARRAY_SIZE(ar5416Bank2), 2);
 224                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 225                                ARRAY_SIZE(ar5416Bank3), 3);
 226                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 227                                ARRAY_SIZE(ar5416Bank6), 3);
 228                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 229                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 230                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 231                                ARRAY_SIZE(ar5416Bank7), 2);
 232                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 233                                ARRAY_SIZE(ar5416Addac), 2);
 234         }
 235 }
 236
 237 /* Support for Japan ch.14 (2484) spread */
 238 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah)
 239 {
 240         if (AR_SREV_9287_11_OR_LATER(ah)) {
 241                 INIT_INI_ARRAY(&ah->iniCckfirNormal,
 242                        ar9287Common_normal_cck_fir_coeff_92871_1,
 243                        ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1),
 244                        2);
 245                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 246                        ar9287Common_japan_2484_cck_fir_coeff_92871_1,
 247                        ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1),
 248                        2);
 249         }
 250 }
 251
 252 static void ar9280_20_hw_init_rxgain_ini(struct ath_hw *ah)
 253 {
 254         u32 rxgain_type;
 255
 256         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >=
 257             AR5416_EEP_MINOR_VER_17) {
 258                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 259
 260                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 261                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 262                         ar9280Modes_backoff_13db_rxgain_9280_2,
 263                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 264                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 265                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 266                         ar9280Modes_backoff_23db_rxgain_9280_2,
 267                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 268                 else
 269                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 270                         ar9280Modes_original_rxgain_9280_2,
 271                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 272         } else {
 273                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 274                         ar9280Modes_original_rxgain_9280_2,
 275                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 276         }
 277 }
 278
 279 static void ar9280_20_hw_init_txgain_ini(struct ath_hw *ah)
 280 {
 281         u32 txgain_type;
 282
 283         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >=
 284             AR5416_EEP_MINOR_VER_19) {
 285                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 286
 287                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 288                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 289                         ar9280Modes_high_power_tx_gain_9280_2,
 290                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 291                 else
 292                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 293                         ar9280Modes_original_tx_gain_9280_2,
 294                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 295         } else {
 296                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 297                 ar9280Modes_original_tx_gain_9280_2,
 298                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 299         }
 300 }
 301
 302 static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
 303 {
 304         if (AR_SREV_9287_11_OR_LATER(ah))
 305                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 306                 ar9287Modes_rx_gain_9287_1_1,
 307                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
 308         else if (AR_SREV_9287_10(ah))
 309                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 310                 ar9287Modes_rx_gain_9287_1_0,
 311                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
 312         else if (AR_SREV_9280_20(ah))
 313                 ar9280_20_hw_init_rxgain_ini(ah);
 314
 315         if (AR_SREV_9287_11_OR_LATER(ah)) {
 316                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 317                 ar9287Modes_tx_gain_9287_1_1,
 318                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
 319         } else if (AR_SREV_9287_10(ah)) {
 320                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 321                 ar9287Modes_tx_gain_9287_1_0,
 322                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
 323         } else if (AR_SREV_9280_20(ah)) {
 324                 ar9280_20_hw_init_txgain_ini(ah);
 325         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 326                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 327
 328                 /* txgain table */
 329                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 330                         if (AR_SREV_9285E_20(ah)) {
 331                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 332                                 ar9285Modes_XE2_0_high_power,
 333                                 ARRAY_SIZE(
 334                                   ar9285Modes_XE2_0_high_power), 6);
 335                         } else {
 336                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 337                                 ar9285Modes_high_power_tx_gain_9285_1_2,
 338                                 ARRAY_SIZE(
 339                                   ar9285Modes_high_power_tx_gain_9285_1_2), 6);
 340                         }
 341                 } else {
 342                         if (AR_SREV_9285E_20(ah)) {
 343                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 344                                 ar9285Modes_XE2_0_normal_power,
 345                                 ARRAY_SIZE(
 346                                   ar9285Modes_XE2_0_normal_power), 6);
 347                         } else {
 348                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 349                                 ar9285Modes_original_tx_gain_9285_1_2,
 350                                 ARRAY_SIZE(
 351                                   ar9285Modes_original_tx_gain_9285_1_2), 6);
 352                         }
 353                 }
 354         }
 355 }
 356
 357 /*
 358  * Helper for ASPM support.
 359  *
 360  * Disable PLL when in L0s as well as receiver clock when in L1.
 361  * This power saving option must be enabled through the SerDes.
 362  *
 363  * Programming the SerDes must go through the same 288 bit serial shift
 364  * register as the other analog registers.  Hence the 9 writes.
 365  */
 366 static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
 367                                          int restore,
 368                                          int power_off)
 369 {
 370         u8 i;
 371         u32 val;
 372
 373         if (ah->is_pciexpress != true)
 374                 return;
 375
 376         /* Do not touch SerDes registers */
 377         if (ah->config.pcie_powersave_enable == 2)
 378                 return;
 379
 380         /* Nothing to do on restore for 11N */
 381         if (!restore) {
 382                 if (AR_SREV_9280_20_OR_LATER(ah)) {
 383                         /*
 384                          * AR9280 2.0 or later chips use SerDes values from the
 385                          * initvals.h initialized depending on chipset during
 386                          * __ath9k_hw_init()
 387                          */
 388                         for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
 389                                 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
 390                                           INI_RA(&ah->iniPcieSerdes, i, 1));
 391                         }
 392                 } else if (AR_SREV_9280(ah) &&
 393                            (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
 394                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
 395                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 396
 397                         /* RX shut off when elecidle is asserted */
 398                         REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
 399                         REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
 400                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
 401
 402                         /* Shut off CLKREQ active in L1 */
 403                         if (ah->config.pcie_clock_req)
 404                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
 405                         else
 406                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
 407
 408                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 409                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 410                         REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
 411
 412                         /* Load the new settings */
 413                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 414
 415                 } else {
 416                         ENABLE_REGWRITE_BUFFER(ah);
 417
 418                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 419                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 420
 421                         /* RX shut off when elecidle is asserted */
 422                         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
 423                         REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
 424                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
 425
 426                         /*
 427                          * Ignore ah->ah_config.pcie_clock_req setting for
 428                          * pre-AR9280 11n
 429                          */
 430                         REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
 431
 432                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 433                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 434                         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
 435
 436                         /* Load the new settings */
 437                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 438
 439                         REGWRITE_BUFFER_FLUSH(ah);
 440                         DISABLE_REGWRITE_BUFFER(ah);
 441                 }
 442
 443                 udelay(1000);
 444         }
 445
 446         if (power_off) {
 447                 /* clear bit 19 to disable L1 */
 448                 REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
 449
 450                 val = REG_READ(ah, AR_WA);
 451
 452                 /*
 453                  * Set PCIe workaround bits
 454                  * In AR9280 and AR9285, bit 14 in WA register (disable L1)
 455                  * should only  be set when device enters D3 and be
 456                  * cleared when device comes back to D0.
 457                  */
 458                 if (ah->config.pcie_waen) {
 459                         if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
 460                                 val |= AR_WA_D3_L1_DISABLE;
 461                 } else {
 462                         if (((AR_SREV_9285(ah) ||
 463                               AR_SREV_9271(ah) ||
 464                               AR_SREV_9287(ah)) &&
 465                              (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
 466                             (AR_SREV_9280(ah) &&
 467                              (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
 468                                 val |= AR_WA_D3_L1_DISABLE;
 469                         }
 470                 }
 471
 472                 if (AR_SREV_9280(ah) || AR_SREV_9285(ah) || AR_SREV_9287(ah)) {
 473                         /*
 474                          * Disable bit 6 and 7 before entering D3 to
 475                          * prevent system hang.
 476                          */
 477                         val &= ~(AR_WA_BIT6 | AR_WA_BIT7);
 478                 }
 479
 480                 if (AR_SREV_9285E_20(ah))
 481                         val |= AR_WA_BIT23;
 482
 483                 REG_WRITE(ah, AR_WA, val);
 484         } else {
 485                 if (ah->config.pcie_waen) {
 486                         val = ah->config.pcie_waen;
 487                         if (!power_off)
 488                                 val &= (~AR_WA_D3_L1_DISABLE);
 489                 } else {
 490                         if (AR_SREV_9285(ah) ||
 491                             AR_SREV_9271(ah) ||
 492                             AR_SREV_9287(ah)) {
 493                                 val = AR9285_WA_DEFAULT;
 494                                 if (!power_off)
 495                                         val &= (~AR_WA_D3_L1_DISABLE);
 496                         }
 497                         else if (AR_SREV_9280(ah)) {
 498                                 /*
 499                                  * For AR9280 chips, bit 22 of 0x4004
 500                                  * needs to be set.
 501                                  */
 502                                 val = AR9280_WA_DEFAULT;
 503                                 if (!power_off)
 504                                         val &= (~AR_WA_D3_L1_DISABLE);
 505                         } else {
 506                                 val = AR_WA_DEFAULT;
 507                         }
 508                 }
 509
 510                 /* WAR for ASPM system hang */
 511                 if (AR_SREV_9280(ah) || AR_SREV_9285(ah) || AR_SREV_9287(ah)) {
 512                         val |= (AR_WA_BIT6 | AR_WA_BIT7);
 513                 }
 514
 515                 if (AR_SREV_9285E_20(ah))
 516                         val |= AR_WA_BIT23;
 517
 518                 REG_WRITE(ah, AR_WA, val);
 519
 520                 /* set bit 19 to allow forcing of pcie core into L1 state */
 521                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
 522         }
 523 }
 524
 525 static int ar9002_hw_get_radiorev(struct ath_hw *ah)
 526 {
 527         u32 val;
 528         int i;
 529
 530         ENABLE_REGWRITE_BUFFER(ah);
 531
 532         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 533         for (i = 0; i < 8; i++)
 534                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 535
 536         REGWRITE_BUFFER_FLUSH(ah);
 537         DISABLE_REGWRITE_BUFFER(ah);
 538
 539         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 540         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 541
 542         return ath9k_hw_reverse_bits(val, 8);
 543 }
 544
 545 int ar9002_hw_rf_claim(struct ath_hw *ah)
 546 {
 547         u32 val;
 548
 549         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 550
 551         val = ar9002_hw_get_radiorev(ah);
 552         switch (val & AR_RADIO_SREV_MAJOR) {
 553         case 0:
 554                 val = AR_RAD5133_SREV_MAJOR;
 555                 break;
 556         case AR_RAD5133_SREV_MAJOR:
 557         case AR_RAD5122_SREV_MAJOR:
 558         case AR_RAD2133_SREV_MAJOR:
 559         case AR_RAD2122_SREV_MAJOR:
 560                 break;
 561         default:
 562                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 563                           "Radio Chip Rev 0x%02X not supported\n",
 564                           val & AR_RADIO_SREV_MAJOR);
 565                 return -EOPNOTSUPP;
 566         }
 567
 568         ah->hw_version.analog5GhzRev = val;
 569
 570         return 0;
 571 }
 572
 573 void ar9002_hw_enable_async_fifo(struct ath_hw *ah)
 574 {
 575         if (AR_SREV_9287_13_OR_LATER(ah)) {
 576                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
 577                                 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
 578                 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
 579                 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
 580                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
 581                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
 582                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
 583         }
 584 }
 585
 586 /*
 587  * If Async FIFO is enabled, the following counters change as MAC now runs
 588  * at 117 Mhz instead of 88/44MHz when async FIFO is disabled.
 589  *
 590  * The values below tested for ht40 2 chain.
 591  * Overwrite the delay/timeouts initialized in process ini.
 592  */
 593 void ar9002_hw_update_async_fifo(struct ath_hw *ah)
 594 {
 595         if (AR_SREV_9287_13_OR_LATER(ah)) {
 596                 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
 597                           AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
 598                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
 599                           AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
 600                 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
 601                           AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
 602
 603                 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
 604                 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
 605
 606                 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
 607                             AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
 608                 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
 609                               AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
 610         }
 611 }
 612
 613 /*
 614  * We don't enable WEP aggregation on mac80211 but we keep this
 615  * around for HAL unification purposes.
 616  */
 617 void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah)
 618 {
 619         if (AR_SREV_9287_13_OR_LATER(ah)) {
 620                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
 621                             AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
 622         }
 623 }
 624
 625 /* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
 626 void ar9002_hw_attach_ops(struct ath_hw *ah)
 627 {
 628         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
 629         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
 630
 631         priv_ops->init_mode_regs = ar9002_hw_init_mode_regs;
 632         priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs;
 633         priv_ops->macversion_supported = ar9002_hw_macversion_supported;
 634
 635         ops->config_pci_powersave = ar9002_hw_configpcipowersave;
 636
 637         ar5008_hw_attach_phy_ops(ah);
 638         if (AR_SREV_9280_10_OR_LATER(ah))
 639                 ar9002_hw_attach_phy_ops(ah);
 640
 641         ar9002_hw_attach_calib_ops(ah);
 642         ar9002_hw_attach_mac_ops(ah);
 643
 644         if (modparam_force_new_ani)
 645                 ath9k_hw_attach_ani_ops_new(ah);
 646         else
 647                 ath9k_hw_attach_ani_ops_old(ah);
 648 }