drivers/net/wireless/ath/ath9k/ar9002_hw.c

   1 /*
   2  * Copyright (c) 2008-2010 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "ar5008_initvals.h"
  19 #include "ar9001_initvals.h"
  20 #include "ar9002_initvals.h"
  21 #include "ar9002_phy.h"
  22
  23 /* General hardware code for the A5008/AR9001/AR9002 hadware families */
  24
  25 static bool ar9002_hw_macversion_supported(u32 macversion)
  26 {
  27         switch (macversion) {
  28         case AR_SREV_VERSION_5416_PCI:
  29         case AR_SREV_VERSION_5416_PCIE:
  30         case AR_SREV_VERSION_9160:
  31         case AR_SREV_VERSION_9100:
  32         case AR_SREV_VERSION_9280:
  33         case AR_SREV_VERSION_9285:
  34         case AR_SREV_VERSION_9287:
  35         case AR_SREV_VERSION_9271:
  36                 return true;
  37         default:
  38                 break;
  39         }
  40         return false;
  41 }
  42
  43 static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
  44 {
  45         if (AR_SREV_9271(ah)) {
  46                 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
  47                                ARRAY_SIZE(ar9271Modes_9271), 6);
  48                 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
  49                                ARRAY_SIZE(ar9271Common_9271), 2);
  50                 INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
  51                                ar9271Common_normal_cck_fir_coeff_9271,
  52                                ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
  53                 INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
  54                                ar9271Common_japan_2484_cck_fir_coeff_9271,
  55                                ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
  56                 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
  57                                ar9271Modes_9271_1_0_only,
  58                                ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
  59                 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
  60                                ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
  61                 INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
  62                                ar9271Modes_high_power_tx_gain_9271,
  63                                ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
  64                 INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
  65                                ar9271Modes_normal_power_tx_gain_9271,
  66                                ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
  67                 return;
  68         }
  69
  70         if (AR_SREV_9287_11_OR_LATER(ah)) {
  71                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
  72                                 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
  73                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
  74                                 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
  75                 if (ah->config.pcie_clock_req)
  76                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
  77                         ar9287PciePhy_clkreq_off_L1_9287_1_1,
  78                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
  79                 else
  80                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
  81                         ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
  82                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
  83                                         2);
  84         } else if (AR_SREV_9287_10_OR_LATER(ah)) {
  85                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
  86                                 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
  87                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
  88                                 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
  89
  90                 if (ah->config.pcie_clock_req)
  91                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
  92                         ar9287PciePhy_clkreq_off_L1_9287_1_0,
  93                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
  94                 else
  95                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
  96                         ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
  97                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
  98                                   2);
  99         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 100
 101
 102                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
 103                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 104                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
 105                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 106
 107                 if (ah->config.pcie_clock_req) {
 108                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 109                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 110                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 111                 } else {
 112                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 113                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 114                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 115                                   2);
 116                 }
 117         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 118                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
 119                                ARRAY_SIZE(ar9285Modes_9285), 6);
 120                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
 121                                ARRAY_SIZE(ar9285Common_9285), 2);
 122
 123                 if (ah->config.pcie_clock_req) {
 124                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 125                         ar9285PciePhy_clkreq_off_L1_9285,
 126                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 127                 } else {
 128                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 129                         ar9285PciePhy_clkreq_always_on_L1_9285,
 130                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 131                 }
 132         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 133                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 134                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 135                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 136                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 137
 138                 if (ah->config.pcie_clock_req) {
 139                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 140                                ar9280PciePhy_clkreq_off_L1_9280,
 141                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280), 2);
 142                 } else {
 143                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 144                                ar9280PciePhy_clkreq_always_on_L1_9280,
 145                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 146                 }
 147                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 148                                ar9280Modes_fast_clock_9280_2,
 149                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 150         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 151                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
 152                                ARRAY_SIZE(ar9280Modes_9280), 6);
 153                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
 154                                ARRAY_SIZE(ar9280Common_9280), 2);
 155         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 156                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 157                                ARRAY_SIZE(ar5416Modes_9160), 6);
 158                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 159                                ARRAY_SIZE(ar5416Common_9160), 2);
 160                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 161                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 162                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 163                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 164                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 165                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 166                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 167                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 168                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 169                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 170                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 171                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 172                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 173                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 174                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 175                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 176                 if (AR_SREV_9160_11(ah)) {
 177                         INIT_INI_ARRAY(&ah->iniAddac,
 178                                        ar5416Addac_91601_1,
 179                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 180                 } else {
 181                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 182                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 183                 }
 184         } else if (AR_SREV_9100_OR_LATER(ah)) {
 185                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 186                                ARRAY_SIZE(ar5416Modes_9100), 6);
 187                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 188                                ARRAY_SIZE(ar5416Common_9100), 2);
 189                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 190                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 191                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 192                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 193                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 194                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 195                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 196                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 197                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 198                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 199                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 200                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 201                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 202                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 203                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 204                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 205                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 206                                ARRAY_SIZE(ar5416Addac_9100), 2);
 207         } else {
 208                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 209                                ARRAY_SIZE(ar5416Modes), 6);
 210                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 211                                ARRAY_SIZE(ar5416Common), 2);
 212                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 213                                ARRAY_SIZE(ar5416Bank0), 2);
 214                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 215                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 216                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 217                                ARRAY_SIZE(ar5416Bank1), 2);
 218                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 219                                ARRAY_SIZE(ar5416Bank2), 2);
 220                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 221                                ARRAY_SIZE(ar5416Bank3), 3);
 222                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 223                                ARRAY_SIZE(ar5416Bank6), 3);
 224                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 225                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 226                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 227                                ARRAY_SIZE(ar5416Bank7), 2);
 228                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 229                                ARRAY_SIZE(ar5416Addac), 2);
 230         }
 231 }
 232
 233 /* Support for Japan ch.14 (2484) spread */
 234 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah)
 235 {
 236         if (AR_SREV_9287_11_OR_LATER(ah)) {
 237                 INIT_INI_ARRAY(&ah->iniCckfirNormal,
 238                        ar9287Common_normal_cck_fir_coeff_92871_1,
 239                        ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1),
 240                        2);
 241                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 242                        ar9287Common_japan_2484_cck_fir_coeff_92871_1,
 243                        ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1),
 244                        2);
 245         }
 246 }
 247
 248 static void ar9280_20_hw_init_rxgain_ini(struct ath_hw *ah)
 249 {
 250         u32 rxgain_type;
 251
 252         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >=
 253             AR5416_EEP_MINOR_VER_17) {
 254                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 255
 256                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 257                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 258                         ar9280Modes_backoff_13db_rxgain_9280_2,
 259                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 260                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 261                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 262                         ar9280Modes_backoff_23db_rxgain_9280_2,
 263                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 264                 else
 265                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 266                         ar9280Modes_original_rxgain_9280_2,
 267                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 268         } else {
 269                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 270                         ar9280Modes_original_rxgain_9280_2,
 271                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 272         }
 273 }
 274
 275 static void ar9280_20_hw_init_txgain_ini(struct ath_hw *ah)
 276 {
 277         u32 txgain_type;
 278
 279         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >=
 280             AR5416_EEP_MINOR_VER_19) {
 281                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 282
 283                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 284                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 285                         ar9280Modes_high_power_tx_gain_9280_2,
 286                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 287                 else
 288                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 289                         ar9280Modes_original_tx_gain_9280_2,
 290                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 291         } else {
 292                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 293                 ar9280Modes_original_tx_gain_9280_2,
 294                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 295         }
 296 }
 297
 298 static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
 299 {
 300         if (AR_SREV_9287_11_OR_LATER(ah))
 301                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 302                 ar9287Modes_rx_gain_9287_1_1,
 303                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
 304         else if (AR_SREV_9287_10(ah))
 305                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 306                 ar9287Modes_rx_gain_9287_1_0,
 307                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
 308         else if (AR_SREV_9280_20(ah))
 309                 ar9280_20_hw_init_rxgain_ini(ah);
 310
 311         if (AR_SREV_9287_11_OR_LATER(ah)) {
 312                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 313                 ar9287Modes_tx_gain_9287_1_1,
 314                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
 315         } else if (AR_SREV_9287_10(ah)) {
 316                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 317                 ar9287Modes_tx_gain_9287_1_0,
 318                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
 319         } else if (AR_SREV_9280_20(ah)) {
 320                 ar9280_20_hw_init_txgain_ini(ah);
 321         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 322                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 323
 324                 /* txgain table */
 325                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 326                         if (AR_SREV_9285E_20(ah)) {
 327                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 328                                 ar9285Modes_XE2_0_high_power,
 329                                 ARRAY_SIZE(
 330                                   ar9285Modes_XE2_0_high_power), 6);
 331                         } else {
 332                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 333                                 ar9285Modes_high_power_tx_gain_9285_1_2,
 334                                 ARRAY_SIZE(
 335                                   ar9285Modes_high_power_tx_gain_9285_1_2), 6);
 336                         }
 337                 } else {
 338                         if (AR_SREV_9285E_20(ah)) {
 339                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 340                                 ar9285Modes_XE2_0_normal_power,
 341                                 ARRAY_SIZE(
 342                                   ar9285Modes_XE2_0_normal_power), 6);
 343                         } else {
 344                                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 345                                 ar9285Modes_original_tx_gain_9285_1_2,
 346                                 ARRAY_SIZE(
 347                                   ar9285Modes_original_tx_gain_9285_1_2), 6);
 348                         }
 349                 }
 350         }
 351 }
 352
 353 /*
 354  * Helper for ASPM support.
 355  *
 356  * Disable PLL when in L0s as well as receiver clock when in L1.
 357  * This power saving option must be enabled through the SerDes.
 358  *
 359  * Programming the SerDes must go through the same 288 bit serial shift
 360  * register as the other analog registers.  Hence the 9 writes.
 361  */
 362 static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
 363                                          int restore,
 364                                          int power_off)
 365 {
 366         u8 i;
 367         u32 val;
 368
 369         if (ah->is_pciexpress != true)
 370                 return;
 371
 372         /* Do not touch SerDes registers */
 373         if (ah->config.pcie_powersave_enable == 2)
 374                 return;
 375
 376         /* Nothing to do on restore for 11N */
 377         if (!restore) {
 378                 if (AR_SREV_9280_20_OR_LATER(ah)) {
 379                         /*
 380                          * AR9280 2.0 or later chips use SerDes values from the
 381                          * initvals.h initialized depending on chipset during
 382                          * __ath9k_hw_init()
 383                          */
 384                         for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
 385                                 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
 386                                           INI_RA(&ah->iniPcieSerdes, i, 1));
 387                         }
 388                 } else if (AR_SREV_9280(ah) &&
 389                            (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
 390                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
 391                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 392
 393                         /* RX shut off when elecidle is asserted */
 394                         REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
 395                         REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
 396                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
 397
 398                         /* Shut off CLKREQ active in L1 */
 399                         if (ah->config.pcie_clock_req)
 400                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
 401                         else
 402                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
 403
 404                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 405                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 406                         REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
 407
 408                         /* Load the new settings */
 409                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 410
 411                 } else {
 412                         ENABLE_REGWRITE_BUFFER(ah);
 413
 414                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 415                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 416
 417                         /* RX shut off when elecidle is asserted */
 418                         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
 419                         REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
 420                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
 421
 422                         /*
 423                          * Ignore ah->ah_config.pcie_clock_req setting for
 424                          * pre-AR9280 11n
 425                          */
 426                         REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
 427
 428                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 429                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 430                         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
 431
 432                         /* Load the new settings */
 433                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 434
 435                         REGWRITE_BUFFER_FLUSH(ah);
 436                         DISABLE_REGWRITE_BUFFER(ah);
 437                 }
 438
 439                 udelay(1000);
 440         }
 441
 442         if (power_off) {
 443                 /* clear bit 19 to disable L1 */
 444                 REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
 445
 446                 val = REG_READ(ah, AR_WA);
 447
 448                 /*
 449                  * Set PCIe workaround bits
 450                  * In AR9280 and AR9285, bit 14 in WA register (disable L1)
 451                  * should only  be set when device enters D3 and be
 452                  * cleared when device comes back to D0.
 453                  */
 454                 if (ah->config.pcie_waen) {
 455                         if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
 456                                 val |= AR_WA_D3_L1_DISABLE;
 457                 } else {
 458                         if (((AR_SREV_9285(ah) ||
 459                               AR_SREV_9271(ah) ||
 460                               AR_SREV_9287(ah)) &&
 461                              (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
 462                             (AR_SREV_9280(ah) &&
 463                              (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
 464                                 val |= AR_WA_D3_L1_DISABLE;
 465                         }
 466                 }
 467
 468                 if (AR_SREV_9280(ah) || AR_SREV_9285(ah) || AR_SREV_9287(ah)) {
 469                         /*
 470                          * Disable bit 6 and 7 before entering D3 to
 471                          * prevent system hang.
 472                          */
 473                         val &= ~(AR_WA_BIT6 | AR_WA_BIT7);
 474                 }
 475
 476                 if (AR_SREV_9285E_20(ah))
 477                         val |= AR_WA_BIT23;
 478
 479                 REG_WRITE(ah, AR_WA, val);
 480         } else {
 481                 if (ah->config.pcie_waen) {
 482                         val = ah->config.pcie_waen;
 483                         if (!power_off)
 484                                 val &= (~AR_WA_D3_L1_DISABLE);
 485                 } else {
 486                         if (AR_SREV_9285(ah) ||
 487                             AR_SREV_9271(ah) ||
 488                             AR_SREV_9287(ah)) {
 489                                 val = AR9285_WA_DEFAULT;
 490                                 if (!power_off)
 491                                         val &= (~AR_WA_D3_L1_DISABLE);
 492                         }
 493                         else if (AR_SREV_9280(ah)) {
 494                                 /*
 495                                  * For AR9280 chips, bit 22 of 0x4004
 496                                  * needs to be set.
 497                                  */
 498                                 val = AR9280_WA_DEFAULT;
 499                                 if (!power_off)
 500                                         val &= (~AR_WA_D3_L1_DISABLE);
 501                         } else {
 502                                 val = AR_WA_DEFAULT;
 503                         }
 504                 }
 505
 506                 /* WAR for ASPM system hang */
 507                 if (AR_SREV_9280(ah) || AR_SREV_9285(ah) || AR_SREV_9287(ah)) {
 508                         val |= (AR_WA_BIT6 | AR_WA_BIT7);
 509                 }
 510
 511                 if (AR_SREV_9285E_20(ah))
 512                         val |= AR_WA_BIT23;
 513
 514                 REG_WRITE(ah, AR_WA, val);
 515
 516                 /* set bit 19 to allow forcing of pcie core into L1 state */
 517                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
 518         }
 519 }
 520
 521 static int ar9002_hw_get_radiorev(struct ath_hw *ah)
 522 {
 523         u32 val;
 524         int i;
 525
 526         ENABLE_REGWRITE_BUFFER(ah);
 527
 528         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 529         for (i = 0; i < 8; i++)
 530                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 531
 532         REGWRITE_BUFFER_FLUSH(ah);
 533         DISABLE_REGWRITE_BUFFER(ah);
 534
 535         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 536         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 537
 538         return ath9k_hw_reverse_bits(val, 8);
 539 }
 540
 541 int ar9002_hw_rf_claim(struct ath_hw *ah)
 542 {
 543         u32 val;
 544
 545         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 546
 547         val = ar9002_hw_get_radiorev(ah);
 548         switch (val & AR_RADIO_SREV_MAJOR) {
 549         case 0:
 550                 val = AR_RAD5133_SREV_MAJOR;
 551                 break;
 552         case AR_RAD5133_SREV_MAJOR:
 553         case AR_RAD5122_SREV_MAJOR:
 554         case AR_RAD2133_SREV_MAJOR:
 555         case AR_RAD2122_SREV_MAJOR:
 556                 break;
 557         default:
 558                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 559                           "Radio Chip Rev 0x%02X not supported\n",
 560                           val & AR_RADIO_SREV_MAJOR);
 561                 return -EOPNOTSUPP;
 562         }
 563
 564         ah->hw_version.analog5GhzRev = val;
 565
 566         return 0;
 567 }
 568
 569 void ar9002_hw_enable_async_fifo(struct ath_hw *ah)
 570 {
 571         if (AR_SREV_9287_13_OR_LATER(ah)) {
 572                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
 573                                 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
 574                 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
 575                 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
 576                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
 577                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
 578                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
 579         }
 580 }
 581
 582 /*
 583  * If Async FIFO is enabled, the following counters change as MAC now runs
 584  * at 117 Mhz instead of 88/44MHz when async FIFO is disabled.
 585  *
 586  * The values below tested for ht40 2 chain.
 587  * Overwrite the delay/timeouts initialized in process ini.
 588  */
 589 void ar9002_hw_update_async_fifo(struct ath_hw *ah)
 590 {
 591         if (AR_SREV_9287_13_OR_LATER(ah)) {
 592                 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
 593                           AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
 594                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
 595                           AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
 596                 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
 597                           AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
 598
 599                 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
 600                 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
 601
 602                 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
 603                             AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
 604                 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
 605                               AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
 606         }
 607 }
 608
 609 /*
 610  * We don't enable WEP aggregation on mac80211 but we keep this
 611  * around for HAL unification purposes.
 612  */
 613 void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah)
 614 {
 615         if (AR_SREV_9287_13_OR_LATER(ah)) {
 616                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
 617                             AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
 618         }
 619 }
 620
 621 /* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
 622 void ar9002_hw_attach_ops(struct ath_hw *ah)
 623 {
 624         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
 625         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
 626
 627         priv_ops->init_mode_regs = ar9002_hw_init_mode_regs;
 628         priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs;
 629         priv_ops->macversion_supported = ar9002_hw_macversion_supported;
 630
 631         ops->config_pci_powersave = ar9002_hw_configpcipowersave;
 632
 633         ar5008_hw_attach_phy_ops(ah);
 634         if (AR_SREV_9280_10_OR_LATER(ah))
 635                 ar9002_hw_attach_phy_ops(ah);
 636
 637         ar9002_hw_attach_calib_ops(ah);
 638         ar9002_hw_attach_mac_ops(ah);
 639
 640         ath9k_hw_attach_ani_ops_old(ah);
 641 }