drivers/net/wireless/ath/ath9k/ar9003_phy.c

   1 /*
   2  * Copyright (c) 2010 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "ar9003_phy.h"
  19
  20 static const int firstep_table[] =
  21 /* level:  0   1   2   3   4   5   6   7   8  */
  22         { -4, -2,  0,  2,  4,  6,  8, 10, 12 }; /* lvl 0-8, default 2 */
  23
  24 static const int cycpwrThr1_table[] =
  25 /* level:  0   1   2   3   4   5   6   7   8  */
  26         { -6, -4, -2,  0,  2,  4,  6,  8 };     /* lvl 0-7, default 3 */
  27
  28 /*
  29  * register values to turn OFDM weak signal detection OFF
  30  */
  31 static const int m1ThreshLow_off = 127;
  32 static const int m2ThreshLow_off = 127;
  33 static const int m1Thresh_off = 127;
  34 static const int m2Thresh_off = 127;
  35 static const int m2CountThr_off =  31;
  36 static const int m2CountThrLow_off =  63;
  37 static const int m1ThreshLowExt_off = 127;
  38 static const int m2ThreshLowExt_off = 127;
  39 static const int m1ThreshExt_off = 127;
  40 static const int m2ThreshExt_off = 127;
  41
  42 /**
  43  * ar9003_hw_set_channel - set channel on single-chip device
  44  * @ah: atheros hardware structure
  45  * @chan:
  46  *
  47  * This is the function to change channel on single-chip devices, that is
  48  * all devices after ar9280.
  49  *
  50  * This function takes the channel value in MHz and sets
  51  * hardware channel value. Assumes writes have been enabled to analog bus.
  52  *
  53  * Actual Expression,
  54  *
  55  * For 2GHz channel,
  56  * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
  57  * (freq_ref = 40MHz)
  58  *
  59  * For 5GHz channel,
  60  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
  61  * (freq_ref = 40MHz/(24>>amodeRefSel))
  62  *
  63  * For 5GHz channels which are 5MHz spaced,
  64  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
  65  * (freq_ref = 40MHz)
  66  */
  67 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
  68 {
  69         u16 bMode, fracMode = 0, aModeRefSel = 0;
  70         u32 freq, channelSel = 0, reg32 = 0;
  71         struct chan_centers centers;
  72         int loadSynthChannel;
  73
  74         ath9k_hw_get_channel_centers(ah, chan, &centers);
  75         freq = centers.synth_center;
  76
  77         if (freq < 4800) {     /* 2 GHz, fractional mode */
  78                 channelSel = CHANSEL_2G(freq);
  79                 /* Set to 2G mode */
  80                 bMode = 1;
  81         } else {
  82                 channelSel = CHANSEL_5G(freq);
  83                 /* Doubler is ON, so, divide channelSel by 2. */
  84                 channelSel >>= 1;
  85                 /* Set to 5G mode */
  86                 bMode = 0;
  87         }
  88
  89         /* Enable fractional mode for all channels */
  90         fracMode = 1;
  91         aModeRefSel = 0;
  92         loadSynthChannel = 0;
  93
  94         reg32 = (bMode << 29);
  95         REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
  96
  97         /* Enable Long shift Select for Synthesizer */
  98         REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
  99                       AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
 100
 101         /* Program Synth. setting */
 102         reg32 = (channelSel << 2) | (fracMode << 30) |
 103                 (aModeRefSel << 28) | (loadSynthChannel << 31);
 104         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
 105
 106         /* Toggle Load Synth channel bit */
 107         loadSynthChannel = 1;
 108         reg32 = (channelSel << 2) | (fracMode << 30) |
 109                 (aModeRefSel << 28) | (loadSynthChannel << 31);
 110         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
 111
 112         ah->curchan = chan;
 113         ah->curchan_rad_index = -1;
 114
 115         return 0;
 116 }
 117
 118 /**
 119  * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
 120  * @ah: atheros hardware structure
 121  * @chan:
 122  *
 123  * For single-chip solutions. Converts to baseband spur frequency given the
 124  * input channel frequency and compute register settings below.
 125  *
 126  * Spur mitigation for MRC CCK
 127  */
 128 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
 129                                             struct ath9k_channel *chan)
 130 {
 131         u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
 132         int cur_bb_spur, negative = 0, cck_spur_freq;
 133         int i;
 134
 135         /*
 136          * Need to verify range +/- 10 MHz in control channel, otherwise spur
 137          * is out-of-band and can be ignored.
 138          */
 139
 140         for (i = 0; i < 4; i++) {
 141                 negative = 0;
 142                 cur_bb_spur = spur_freq[i] - chan->channel;
 143
 144                 if (cur_bb_spur < 0) {
 145                         negative = 1;
 146                         cur_bb_spur = -cur_bb_spur;
 147                 }
 148                 if (cur_bb_spur < 10) {
 149                         cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
 150
 151                         if (negative == 1)
 152                                 cck_spur_freq = -cck_spur_freq;
 153
 154                         cck_spur_freq = cck_spur_freq & 0xfffff;
 155
 156                         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
 157                                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
 158                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 159                                       AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
 160                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 161                                       AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
 162                                       0x2);
 163                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 164                                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
 165                                       0x1);
 166                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 167                                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
 168                                       cck_spur_freq);
 169
 170                         return;
 171                 }
 172         }
 173
 174         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
 175                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
 176         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 177                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
 178         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 179                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
 180 }
 181
 182 /* Clean all spur register fields */
 183 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
 184 {
 185         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 186                       AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
 187         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 188                       AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
 189         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 190                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
 191         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 192                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
 193         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 194                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
 195         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 196                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
 197         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 198                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
 199         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 200                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
 201         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 202                       AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
 203
 204         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 205                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
 206         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 207                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
 208         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 209                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
 210         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 211                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
 212         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 213                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
 214         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 215                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
 216         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 217                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
 218         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 219                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
 220         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 221                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
 222         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 223                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
 224 }
 225
 226 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
 227                                 int freq_offset,
 228                                 int spur_freq_sd,
 229                                 int spur_delta_phase,
 230                                 int spur_subchannel_sd)
 231 {
 232         int mask_index = 0;
 233
 234         /* OFDM Spur mitigation */
 235         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 236                  AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
 237         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 238                       AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
 239         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 240                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
 241         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 242                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
 243         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 244                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
 245         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 246                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
 247         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 248                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
 249         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 250                       AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
 251         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 252                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
 253
 254         if (REG_READ_FIELD(ah, AR_PHY_MODE,
 255                            AR_PHY_MODE_DYNAMIC) == 0x1)
 256                 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 257                               AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
 258
 259         mask_index = (freq_offset << 4) / 5;
 260         if (mask_index < 0)
 261                 mask_index = mask_index - 1;
 262
 263         mask_index = mask_index & 0x7f;
 264
 265         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 266                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
 267         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 268                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
 269         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 270                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
 271         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 272                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
 273         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 274                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
 275         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 276                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
 277         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 278                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
 279         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 280                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
 281         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 282                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
 283         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 284                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
 285 }
 286
 287 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
 288                                      struct ath9k_channel *chan,
 289                                      int freq_offset)
 290 {
 291         int spur_freq_sd = 0;
 292         int spur_subchannel_sd = 0;
 293         int spur_delta_phase = 0;
 294
 295         if (IS_CHAN_HT40(chan)) {
 296                 if (freq_offset < 0) {
 297                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 298                                            AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 299                                 spur_subchannel_sd = 1;
 300                         else
 301                                 spur_subchannel_sd = 0;
 302
 303                         spur_freq_sd = ((freq_offset + 10) << 9) / 11;
 304
 305                 } else {
 306                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 307                             AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 308                                 spur_subchannel_sd = 0;
 309                         else
 310                                 spur_subchannel_sd = 1;
 311
 312                         spur_freq_sd = ((freq_offset - 10) << 9) / 11;
 313
 314                 }
 315
 316                 spur_delta_phase = (freq_offset << 17) / 5;
 317
 318         } else {
 319                 spur_subchannel_sd = 0;
 320                 spur_freq_sd = (freq_offset << 9) /11;
 321                 spur_delta_phase = (freq_offset << 18) / 5;
 322         }
 323
 324         spur_freq_sd = spur_freq_sd & 0x3ff;
 325         spur_delta_phase = spur_delta_phase & 0xfffff;
 326
 327         ar9003_hw_spur_ofdm(ah,
 328                             freq_offset,
 329                             spur_freq_sd,
 330                             spur_delta_phase,
 331                             spur_subchannel_sd);
 332 }
 333
 334 /* Spur mitigation for OFDM */
 335 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
 336                                          struct ath9k_channel *chan)
 337 {
 338         int synth_freq;
 339         int range = 10;
 340         int freq_offset = 0;
 341         int mode;
 342         u8* spurChansPtr;
 343         unsigned int i;
 344         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
 345
 346         if (IS_CHAN_5GHZ(chan)) {
 347                 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
 348                 mode = 0;
 349         }
 350         else {
 351                 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
 352                 mode = 1;
 353         }
 354
 355         if (spurChansPtr[0] == 0)
 356                 return; /* No spur in the mode */
 357
 358         if (IS_CHAN_HT40(chan)) {
 359                 range = 19;
 360                 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 361                                    AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 362                         synth_freq = chan->channel - 10;
 363                 else
 364                         synth_freq = chan->channel + 10;
 365         } else {
 366                 range = 10;
 367                 synth_freq = chan->channel;
 368         }
 369
 370         ar9003_hw_spur_ofdm_clear(ah);
 371
 372         for (i = 0; spurChansPtr[i] && i < 5; i++) {
 373                 freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq;
 374                 if (abs(freq_offset) < range) {
 375                         ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
 376                         break;
 377                 }
 378         }
 379 }
 380
 381 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
 382                                     struct ath9k_channel *chan)
 383 {
 384         ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
 385         ar9003_hw_spur_mitigate_ofdm(ah, chan);
 386 }
 387
 388 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
 389                                          struct ath9k_channel *chan)
 390 {
 391         u32 pll;
 392
 393         pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
 394
 395         if (chan && IS_CHAN_HALF_RATE(chan))
 396                 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
 397         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 398                 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
 399
 400         pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
 401
 402         return pll;
 403 }
 404
 405 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
 406                                        struct ath9k_channel *chan)
 407 {
 408         u32 phymode;
 409         u32 enableDacFifo = 0;
 410
 411         enableDacFifo =
 412                 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
 413
 414         /* Enable 11n HT, 20 MHz */
 415         phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH |
 416                   AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
 417
 418         /* Configure baseband for dynamic 20/40 operation */
 419         if (IS_CHAN_HT40(chan)) {
 420                 phymode |= AR_PHY_GC_DYN2040_EN;
 421                 /* Configure control (primary) channel at +-10MHz */
 422                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 423                     (chan->chanmode == CHANNEL_G_HT40PLUS))
 424                         phymode |= AR_PHY_GC_DYN2040_PRI_CH;
 425
 426         }
 427
 428         /* make sure we preserve INI settings */
 429         phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
 430         /* turn off Green Field detection for STA for now */
 431         phymode &= ~AR_PHY_GC_GF_DETECT_EN;
 432
 433         REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
 434
 435         /* Configure MAC for 20/40 operation */
 436         ath9k_hw_set11nmac2040(ah);
 437
 438         /* global transmit timeout (25 TUs default)*/
 439         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
 440         /* carrier sense timeout */
 441         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
 442 }
 443
 444 static void ar9003_hw_init_bb(struct ath_hw *ah,
 445                               struct ath9k_channel *chan)
 446 {
 447         u32 synthDelay;
 448
 449         /*
 450          * Wait for the frequency synth to settle (synth goes on
 451          * via AR_PHY_ACTIVE_EN).  Read the phy active delay register.
 452          * Value is in 100ns increments.
 453          */
 454         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 455         if (IS_CHAN_B(chan))
 456                 synthDelay = (4 * synthDelay) / 22;
 457         else
 458                 synthDelay /= 10;
 459
 460         /* Activate the PHY (includes baseband activate + synthesizer on) */
 461         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 462
 463         /*
 464          * There is an issue if the AP starts the calibration before
 465          * the base band timeout completes.  This could result in the
 466          * rx_clear false triggering.  As a workaround we add delay an
 467          * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
 468          * does not happen.
 469          */
 470         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 471 }
 472
 473 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
 474 {
 475         switch (rx) {
 476         case 0x5:
 477                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
 478                             AR_PHY_SWAP_ALT_CHAIN);
 479         case 0x3:
 480         case 0x1:
 481         case 0x2:
 482         case 0x7:
 483                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
 484                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
 485                 break;
 486         default:
 487                 break;
 488         }
 489
 490         REG_WRITE(ah, AR_SELFGEN_MASK, tx);
 491         if (tx == 0x5) {
 492                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
 493                             AR_PHY_SWAP_ALT_CHAIN);
 494         }
 495 }
 496
 497 /*
 498  * Override INI values with chip specific configuration.
 499  */
 500 static void ar9003_hw_override_ini(struct ath_hw *ah)
 501 {
 502         u32 val;
 503
 504         /*
 505          * Set the RX_ABORT and RX_DIS and clear it only after
 506          * RXE is set for MAC. This prevents frames with
 507          * corrupted descriptor status.
 508          */
 509         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
 510
 511         /*
 512          * For AR9280 and above, there is a new feature that allows
 513          * Multicast search based on both MAC Address and Key ID. By default,
 514          * this feature is enabled. But since the driver is not using this
 515          * feature, we switch it off; otherwise multicast search based on
 516          * MAC addr only will fail.
 517          */
 518         val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
 519         REG_WRITE(ah, AR_PCU_MISC_MODE2,
 520                   val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
 521 }
 522
 523 static void ar9003_hw_prog_ini(struct ath_hw *ah,
 524                                struct ar5416IniArray *iniArr,
 525                                int column)
 526 {
 527         unsigned int i, regWrites = 0;
 528
 529         /* New INI format: Array may be undefined (pre, core, post arrays) */
 530         if (!iniArr->ia_array)
 531                 return;
 532
 533         /*
 534          * New INI format: Pre, core, and post arrays for a given subsystem
 535          * may be modal (> 2 columns) or non-modal (2 columns). Determine if
 536          * the array is non-modal and force the column to 1.
 537          */
 538         if (column >= iniArr->ia_columns)
 539                 column = 1;
 540
 541         for (i = 0; i < iniArr->ia_rows; i++) {
 542                 u32 reg = INI_RA(iniArr, i, 0);
 543                 u32 val = INI_RA(iniArr, i, column);
 544
 545                 REG_WRITE(ah, reg, val);
 546
 547                 /*
 548                  * Determine if this is a shift register value, and insert the
 549                  * configured delay if so.
 550                  */
 551                 if (reg >= 0x16000 && reg < 0x17000
 552                     && ah->config.analog_shiftreg)
 553                         udelay(100);
 554
 555                 DO_DELAY(regWrites);
 556         }
 557 }
 558
 559 static int ar9003_hw_process_ini(struct ath_hw *ah,
 560                                  struct ath9k_channel *chan)
 561 {
 562         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 563         unsigned int regWrites = 0, i;
 564         struct ieee80211_channel *channel = chan->chan;
 565         u32 modesIndex, freqIndex;
 566
 567         switch (chan->chanmode) {
 568         case CHANNEL_A:
 569         case CHANNEL_A_HT20:
 570                 modesIndex = 1;
 571                 freqIndex = 1;
 572                 break;
 573         case CHANNEL_A_HT40PLUS:
 574         case CHANNEL_A_HT40MINUS:
 575                 modesIndex = 2;
 576                 freqIndex = 1;
 577                 break;
 578         case CHANNEL_G:
 579         case CHANNEL_G_HT20:
 580         case CHANNEL_B:
 581                 modesIndex = 4;
 582                 freqIndex = 2;
 583                 break;
 584         case CHANNEL_G_HT40PLUS:
 585         case CHANNEL_G_HT40MINUS:
 586                 modesIndex = 3;
 587                 freqIndex = 2;
 588                 break;
 589
 590         default:
 591                 return -EINVAL;
 592         }
 593
 594         for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
 595                 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
 596                 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
 597                 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
 598                 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
 599         }
 600
 601         REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
 602         REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
 603
 604         /*
 605          * For 5GHz channels requiring Fast Clock, apply
 606          * different modal values.
 607          */
 608         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
 609                 REG_WRITE_ARRAY(&ah->iniModesAdditional,
 610                                 modesIndex, regWrites);
 611
 612         ar9003_hw_override_ini(ah);
 613         ar9003_hw_set_channel_regs(ah, chan);
 614         ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
 615
 616         /* Set TX power */
 617         ah->eep_ops->set_txpower(ah, chan,
 618                                  ath9k_regd_get_ctl(regulatory, chan),
 619                                  channel->max_antenna_gain * 2,
 620                                  channel->max_power * 2,
 621                                  min((u32) MAX_RATE_POWER,
 622                                  (u32) regulatory->power_limit));
 623
 624         return 0;
 625 }
 626
 627 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
 628                                  struct ath9k_channel *chan)
 629 {
 630         u32 rfMode = 0;
 631
 632         if (chan == NULL)
 633                 return;
 634
 635         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
 636                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
 637
 638         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
 639                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
 640
 641         REG_WRITE(ah, AR_PHY_MODE, rfMode);
 642 }
 643
 644 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
 645 {
 646         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
 647 }
 648
 649 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
 650                                       struct ath9k_channel *chan)
 651 {
 652         u32 coef_scaled, ds_coef_exp, ds_coef_man;
 653         u32 clockMhzScaled = 0x64000000;
 654         struct chan_centers centers;
 655
 656         /*
 657          * half and quarter rate can divide the scaled clock by 2 or 4
 658          * scale for selected channel bandwidth
 659          */
 660         if (IS_CHAN_HALF_RATE(chan))
 661                 clockMhzScaled = clockMhzScaled >> 1;
 662         else if (IS_CHAN_QUARTER_RATE(chan))
 663                 clockMhzScaled = clockMhzScaled >> 2;
 664
 665         /*
 666          * ALGO -> coef = 1e8/fcarrier*fclock/40;
 667          * scaled coef to provide precision for this floating calculation
 668          */
 669         ath9k_hw_get_channel_centers(ah, chan, &centers);
 670         coef_scaled = clockMhzScaled / centers.synth_center;
 671
 672         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
 673                                       &ds_coef_exp);
 674
 675         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
 676                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
 677         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
 678                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
 679
 680         /*
 681          * For Short GI,
 682          * scaled coeff is 9/10 that of normal coeff
 683          */
 684         coef_scaled = (9 * coef_scaled) / 10;
 685
 686         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
 687                                       &ds_coef_exp);
 688
 689         /* for short gi */
 690         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
 691                       AR_PHY_SGI_DSC_MAN, ds_coef_man);
 692         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
 693                       AR_PHY_SGI_DSC_EXP, ds_coef_exp);
 694 }
 695
 696 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
 697 {
 698         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
 699         return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
 700                              AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
 701 }
 702
 703 /*
 704  * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
 705  * Read the phy active delay register. Value is in 100ns increments.
 706  */
 707 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
 708 {
 709         u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 710         if (IS_CHAN_B(ah->curchan))
 711                 synthDelay = (4 * synthDelay) / 22;
 712         else
 713                 synthDelay /= 10;
 714
 715         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 716
 717         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
 718 }
 719
 720 /*
 721  * Set the interrupt and GPIO values so the ISR can disable RF
 722  * on a switch signal.  Assumes GPIO port and interrupt polarity
 723  * are set prior to call.
 724  */
 725 static void ar9003_hw_enable_rfkill(struct ath_hw *ah)
 726 {
 727         /* Connect rfsilent_bb_l to baseband */
 728         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
 729                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
 730         /* Set input mux for rfsilent_bb_l to GPIO #0 */
 731         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
 732                     AR_GPIO_INPUT_MUX2_RFSILENT);
 733
 734         /*
 735          * Configure the desired GPIO port for input and
 736          * enable baseband rf silence.
 737          */
 738         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
 739         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
 740 }
 741
 742 static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
 743 {
 744         u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
 745         if (value)
 746                 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
 747         else
 748                 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
 749         REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
 750 }
 751
 752 static bool ar9003_hw_ani_control(struct ath_hw *ah,
 753                                   enum ath9k_ani_cmd cmd, int param)
 754 {
 755         struct ar5416AniState *aniState = ah->curani;
 756         struct ath_common *common = ath9k_hw_common(ah);
 757         struct ath9k_channel *chan = ah->curchan;
 758         s32 value, value2;
 759
 760         switch (cmd & ah->ani_function) {
 761         case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
 762                 /*
 763                  * on == 1 means ofdm weak signal detection is ON
 764                  * on == 1 is the default, for less noise immunity
 765                  *
 766                  * on == 0 means ofdm weak signal detection is OFF
 767                  * on == 0 means more noise imm
 768                  */
 769                 u32 on = param ? 1 : 0;
 770                 /*
 771                  * make register setting for default
 772                  * (weak sig detect ON) come from INI file
 773                  */
 774                 int m1ThreshLow = on ?
 775                         aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
 776                 int m2ThreshLow = on ?
 777                         aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
 778                 int m1Thresh = on ?
 779                         aniState->iniDef.m1Thresh : m1Thresh_off;
 780                 int m2Thresh = on ?
 781                         aniState->iniDef.m2Thresh : m2Thresh_off;
 782                 int m2CountThr = on ?
 783                         aniState->iniDef.m2CountThr : m2CountThr_off;
 784                 int m2CountThrLow = on ?
 785                         aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
 786                 int m1ThreshLowExt = on ?
 787                         aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
 788                 int m2ThreshLowExt = on ?
 789                         aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
 790                 int m1ThreshExt = on ?
 791                         aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
 792                 int m2ThreshExt = on ?
 793                         aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
 794
 795                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
 796                               AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
 797                               m1ThreshLow);
 798                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
 799                               AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
 800                               m2ThreshLow);
 801                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
 802                               AR_PHY_SFCORR_M1_THRESH, m1Thresh);
 803                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
 804                               AR_PHY_SFCORR_M2_THRESH, m2Thresh);
 805                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
 806                               AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
 807                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
 808                               AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
 809                               m2CountThrLow);
 810
 811                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 812                               AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
 813                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 814                               AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
 815                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 816                               AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
 817                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 818                               AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
 819
 820                 if (on)
 821                         REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
 822                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
 823                 else
 824                         REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
 825                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
 826
 827                 if (!on != aniState->ofdmWeakSigDetectOff) {
 828                         ath_print(common, ATH_DBG_ANI,
 829                                   "** ch %d: ofdm weak signal: %s=>%s\n",
 830                                   chan->channel,
 831                                   !aniState->ofdmWeakSigDetectOff ?
 832                                         "on" : "off",
 833                                   on ? "on" : "off");
 834                         if (on)
 835                                 ah->stats.ast_ani_ofdmon++;
 836                         else
 837                                 ah->stats.ast_ani_ofdmoff++;
 838                         aniState->ofdmWeakSigDetectOff = !on;
 839                 }
 840                 break;
 841         }
 842         case ATH9K_ANI_FIRSTEP_LEVEL:{
 843                 u32 level = param;
 844
 845                 if (level >= ARRAY_SIZE(firstep_table)) {
 846                         ath_print(common, ATH_DBG_ANI,
 847                                   "ATH9K_ANI_FIRSTEP_LEVEL: level "
 848                                   "out of range (%u > %u)\n",
 849                                   level,
 850                                   (unsigned) ARRAY_SIZE(firstep_table));
 851                         return false;
 852                 }
 853
 854                 /*
 855                  * make register setting relative to default
 856                  * from INI file & cap value
 857                  */
 858                 value = firstep_table[level] -
 859                         firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
 860                         aniState->iniDef.firstep;
 861                 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
 862                         value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
 863                 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
 864                         value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
 865                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
 866                               AR_PHY_FIND_SIG_FIRSTEP,
 867                               value);
 868                 /*
 869                  * we need to set first step low register too
 870                  * make register setting relative to default
 871                  * from INI file & cap value
 872                  */
 873                 value2 = firstep_table[level] -
 874                          firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
 875                          aniState->iniDef.firstepLow;
 876                 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
 877                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
 878                 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
 879                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
 880
 881                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
 882                               AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
 883
 884                 if (level != aniState->firstepLevel) {
 885                         ath_print(common, ATH_DBG_ANI,
 886                                   "** ch %d: level %d=>%d[def:%d] "
 887                                   "firstep[level]=%d ini=%d\n",
 888                                   chan->channel,
 889                                   aniState->firstepLevel,
 890                                   level,
 891                                   ATH9K_ANI_FIRSTEP_LVL_NEW,
 892                                   value,
 893                                   aniState->iniDef.firstep);
 894                         ath_print(common, ATH_DBG_ANI,
 895                                   "** ch %d: level %d=>%d[def:%d] "
 896                                   "firstep_low[level]=%d ini=%d\n",
 897                                   chan->channel,
 898                                   aniState->firstepLevel,
 899                                   level,
 900                                   ATH9K_ANI_FIRSTEP_LVL_NEW,
 901                                   value2,
 902                                   aniState->iniDef.firstepLow);
 903                         if (level > aniState->firstepLevel)
 904                                 ah->stats.ast_ani_stepup++;
 905                         else if (level < aniState->firstepLevel)
 906                                 ah->stats.ast_ani_stepdown++;
 907                         aniState->firstepLevel = level;
 908                 }
 909                 break;
 910         }
 911         case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
 912                 u32 level = param;
 913
 914                 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
 915                         ath_print(common, ATH_DBG_ANI,
 916                                   "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level "
 917                                   "out of range (%u > %u)\n",
 918                                   level,
 919                                   (unsigned) ARRAY_SIZE(cycpwrThr1_table));
 920                         return false;
 921                 }
 922                 /*
 923                  * make register setting relative to default
 924                  * from INI file & cap value
 925                  */
 926                 value = cycpwrThr1_table[level] -
 927                         cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
 928                         aniState->iniDef.cycpwrThr1;
 929                 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
 930                         value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
 931                 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
 932                         value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
 933                 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
 934                               AR_PHY_TIMING5_CYCPWR_THR1,
 935                               value);
 936
 937                 /*
 938                  * set AR_PHY_EXT_CCA for extension channel
 939                  * make register setting relative to default
 940                  * from INI file & cap value
 941                  */
 942                 value2 = cycpwrThr1_table[level] -
 943                          cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
 944                          aniState->iniDef.cycpwrThr1Ext;
 945                 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
 946                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
 947                 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
 948                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
 949                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
 950                               AR_PHY_EXT_CYCPWR_THR1, value2);
 951
 952                 if (level != aniState->spurImmunityLevel) {
 953                         ath_print(common, ATH_DBG_ANI,
 954                                   "** ch %d: level %d=>%d[def:%d] "
 955                                   "cycpwrThr1[level]=%d ini=%d\n",
 956                                   chan->channel,
 957                                   aniState->spurImmunityLevel,
 958                                   level,
 959                                   ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
 960                                   value,
 961                                   aniState->iniDef.cycpwrThr1);
 962                         ath_print(common, ATH_DBG_ANI,
 963                                   "** ch %d: level %d=>%d[def:%d] "
 964                                   "cycpwrThr1Ext[level]=%d ini=%d\n",
 965                                   chan->channel,
 966                                   aniState->spurImmunityLevel,
 967                                   level,
 968                                   ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
 969                                   value2,
 970                                   aniState->iniDef.cycpwrThr1Ext);
 971                         if (level > aniState->spurImmunityLevel)
 972                                 ah->stats.ast_ani_spurup++;
 973                         else if (level < aniState->spurImmunityLevel)
 974                                 ah->stats.ast_ani_spurdown++;
 975                         aniState->spurImmunityLevel = level;
 976                 }
 977                 break;
 978         }
 979         case ATH9K_ANI_MRC_CCK:{
 980                 /*
 981                  * is_on == 1 means MRC CCK ON (default, less noise imm)
 982                  * is_on == 0 means MRC CCK is OFF (more noise imm)
 983                  */
 984                 bool is_on = param ? 1 : 0;
 985                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
 986                               AR_PHY_MRC_CCK_ENABLE, is_on);
 987                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
 988                               AR_PHY_MRC_CCK_MUX_REG, is_on);
 989                 if (!is_on != aniState->mrcCCKOff) {
 990                         ath_print(common, ATH_DBG_ANI,
 991                                   "** ch %d: MRC CCK: %s=>%s\n",
 992                                   chan->channel,
 993                                   !aniState->mrcCCKOff ? "on" : "off",
 994                                   is_on ? "on" : "off");
 995                 if (is_on)
 996                         ah->stats.ast_ani_ccklow++;
 997                 else
 998                         ah->stats.ast_ani_cckhigh++;
 999                 aniState->mrcCCKOff = !is_on;
1000                 }
1001         break;
1002         }
1003         case ATH9K_ANI_PRESENT:
1004                 break;
1005         default:
1006                 ath_print(common, ATH_DBG_ANI,
1007                           "invalid cmd %u\n", cmd);
1008                 return false;
1009         }
1010
1011         ath_print(common, ATH_DBG_ANI,
1012                   "ANI parameters: SI=%d, ofdmWS=%s FS=%d "
1013                   "MRCcck=%s listenTime=%d CC=%d listen=%d "
1014                   "ofdmErrs=%d cckErrs=%d\n",
1015                   aniState->spurImmunityLevel,
1016                   !aniState->ofdmWeakSigDetectOff ? "on" : "off",
1017                   aniState->firstepLevel,
1018                   !aniState->mrcCCKOff ? "on" : "off",
1019                   aniState->listenTime,
1020                   aniState->cycleCount,
1021                   aniState->listenTime,
1022                   aniState->ofdmPhyErrCount,
1023                   aniState->cckPhyErrCount);
1024         return true;
1025 }
1026
1027 static void ar9003_hw_nf_sanitize_2g(struct ath_hw *ah, s16 *nf)
1028 {
1029         struct ath_common *common = ath9k_hw_common(ah);
1030
1031         if (*nf > ah->nf_2g_max) {
1032                 ath_print(common, ATH_DBG_CALIBRATE,
1033                           "2 GHz NF (%d) > MAX (%d), "
1034                           "correcting to MAX",
1035                           *nf, ah->nf_2g_max);
1036                 *nf = ah->nf_2g_max;
1037         } else if (*nf < ah->nf_2g_min) {
1038                 ath_print(common, ATH_DBG_CALIBRATE,
1039                           "2 GHz NF (%d) < MIN (%d), "
1040                           "correcting to MIN",
1041                           *nf, ah->nf_2g_min);
1042                 *nf = ah->nf_2g_min;
1043         }
1044 }
1045
1046 static void ar9003_hw_nf_sanitize_5g(struct ath_hw *ah, s16 *nf)
1047 {
1048         struct ath_common *common = ath9k_hw_common(ah);
1049
1050         if (*nf > ah->nf_5g_max) {
1051                 ath_print(common, ATH_DBG_CALIBRATE,
1052                           "5 GHz NF (%d) > MAX (%d), "
1053                           "correcting to MAX",
1054                           *nf, ah->nf_5g_max);
1055                 *nf = ah->nf_5g_max;
1056         } else if (*nf < ah->nf_5g_min) {
1057                 ath_print(common, ATH_DBG_CALIBRATE,
1058                           "5 GHz NF (%d) < MIN (%d), "
1059                           "correcting to MIN",
1060                           *nf, ah->nf_5g_min);
1061                 *nf = ah->nf_5g_min;
1062         }
1063 }
1064
1065 static void ar9003_hw_nf_sanitize(struct ath_hw *ah, s16 *nf)
1066 {
1067         if (IS_CHAN_2GHZ(ah->curchan))
1068                 ar9003_hw_nf_sanitize_2g(ah, nf);
1069         else
1070                 ar9003_hw_nf_sanitize_5g(ah, nf);
1071 }
1072
1073 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1074                               int16_t nfarray[NUM_NF_READINGS])
1075 {
1076         struct ath_common *common = ath9k_hw_common(ah);
1077         int16_t nf;
1078
1079         nf = MS(REG_READ(ah, AR_PHY_CCA_0), AR_PHY_MINCCA_PWR);
1080         if (nf & 0x100)
1081                 nf = 0 - ((nf ^ 0x1ff) + 1);
1082         ar9003_hw_nf_sanitize(ah, &nf);
1083         ath_print(common, ATH_DBG_CALIBRATE,
1084                   "NF calibrated [ctl] [chain 0] is %d\n", nf);
1085         nfarray[0] = nf;
1086
1087         nf = MS(REG_READ(ah, AR_PHY_CCA_1), AR_PHY_CH1_MINCCA_PWR);
1088         if (nf & 0x100)
1089                 nf = 0 - ((nf ^ 0x1ff) + 1);
1090         ar9003_hw_nf_sanitize(ah, &nf);
1091         ath_print(common, ATH_DBG_CALIBRATE,
1092                   "NF calibrated [ctl] [chain 1] is %d\n", nf);
1093         nfarray[1] = nf;
1094
1095         nf = MS(REG_READ(ah, AR_PHY_CCA_2), AR_PHY_CH2_MINCCA_PWR);
1096         if (nf & 0x100)
1097                 nf = 0 - ((nf ^ 0x1ff) + 1);
1098         ar9003_hw_nf_sanitize(ah, &nf);
1099         ath_print(common, ATH_DBG_CALIBRATE,
1100                   "NF calibrated [ctl] [chain 2] is %d\n", nf);
1101         nfarray[2] = nf;
1102
1103         nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
1104         if (nf & 0x100)
1105                 nf = 0 - ((nf ^ 0x1ff) + 1);
1106         ar9003_hw_nf_sanitize(ah, &nf);
1107         ath_print(common, ATH_DBG_CALIBRATE,
1108                   "NF calibrated [ext] [chain 0] is %d\n", nf);
1109         nfarray[3] = nf;
1110
1111         nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_1), AR_PHY_CH1_EXT_MINCCA_PWR);
1112         if (nf & 0x100)
1113                 nf = 0 - ((nf ^ 0x1ff) + 1);
1114         ar9003_hw_nf_sanitize(ah, &nf);
1115         ath_print(common, ATH_DBG_CALIBRATE,
1116                   "NF calibrated [ext] [chain 1] is %d\n", nf);
1117         nfarray[4] = nf;
1118
1119         nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_2), AR_PHY_CH2_EXT_MINCCA_PWR);
1120         if (nf & 0x100)
1121                 nf = 0 - ((nf ^ 0x1ff) + 1);
1122         ar9003_hw_nf_sanitize(ah, &nf);
1123         ath_print(common, ATH_DBG_CALIBRATE,
1124                   "NF calibrated [ext] [chain 2] is %d\n", nf);
1125         nfarray[5] = nf;
1126 }
1127
1128 void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1129 {
1130         ah->nf_2g_max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1131         ah->nf_2g_min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1132         ah->nf_5g_max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1133         ah->nf_5g_min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1134 }
1135
1136 /*
1137  * Find out which of the RX chains are enabled
1138  */
1139 static u32 ar9003_hw_get_rx_chainmask(struct ath_hw *ah)
1140 {
1141         u32 chain = REG_READ(ah, AR_PHY_RX_CHAINMASK);
1142         /*
1143          * The bits [2:0] indicate the rx chain mask and are to be
1144          * interpreted as follows:
1145          * 00x => Only chain 0 is enabled
1146          * 01x => Chain 1 and 0 enabled
1147          * 1xx => Chain 2,1 and 0 enabled
1148          */
1149         return chain & 0x7;
1150 }
1151
1152 static void ar9003_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
1153 {
1154         struct ath9k_nfcal_hist *h;
1155         unsigned i, j;
1156         int32_t val;
1157         const u32 ar9300_cca_regs[6] = {
1158                 AR_PHY_CCA_0,
1159                 AR_PHY_CCA_1,
1160                 AR_PHY_CCA_2,
1161                 AR_PHY_EXT_CCA,
1162                 AR_PHY_EXT_CCA_1,
1163                 AR_PHY_EXT_CCA_2,
1164         };
1165         u8 chainmask, rx_chain_status;
1166         struct ath_common *common = ath9k_hw_common(ah);
1167
1168         rx_chain_status = ar9003_hw_get_rx_chainmask(ah);
1169
1170         chainmask = 0x3F;
1171         h = ah->nfCalHist;
1172
1173         for (i = 0; i < NUM_NF_READINGS; i++) {
1174                 if (chainmask & (1 << i)) {
1175                         val = REG_READ(ah, ar9300_cca_regs[i]);
1176                         val &= 0xFFFFFE00;
1177                         val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
1178                         REG_WRITE(ah, ar9300_cca_regs[i], val);
1179                 }
1180         }
1181
1182         /*
1183          * Load software filtered NF value into baseband internal minCCApwr
1184          * variable.
1185          */
1186         REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1187                     AR_PHY_AGC_CONTROL_ENABLE_NF);
1188         REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1189                     AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1190         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1191
1192         /*
1193          * Wait for load to complete, should be fast, a few 10s of us.
1194          * The max delay was changed from an original 250us to 10000us
1195          * since 250us often results in NF load timeout and causes deaf
1196          * condition during stress testing 12/12/2009
1197          */
1198         for (j = 0; j < 1000; j++) {
1199                 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
1200                      AR_PHY_AGC_CONTROL_NF) == 0)
1201                         break;
1202                 udelay(10);
1203         }
1204
1205         /*
1206          * We timed out waiting for the noisefloor to load, probably due to an
1207          * in-progress rx. Simply return here and allow the load plenty of time
1208          * to complete before the next calibration interval.  We need to avoid
1209          * trying to load -50 (which happens below) while the previous load is
1210          * still in progress as this can cause rx deafness. Instead by returning
1211          * here, the baseband nf cal will just be capped by our present
1212          * noisefloor until the next calibration timer.
1213          */
1214         if (j == 1000) {
1215                 ath_print(common, ATH_DBG_ANY, "Timeout while waiting for nf "
1216                           "to load: AR_PHY_AGC_CONTROL=0x%x\n",
1217                           REG_READ(ah, AR_PHY_AGC_CONTROL));
1218                 return;
1219         }
1220
1221         /*
1222          * Restore maxCCAPower register parameter again so that we're not capped
1223          * by the median we just loaded.  This will be initial (and max) value
1224          * of next noise floor calibration the baseband does.
1225          */
1226         for (i = 0; i < NUM_NF_READINGS; i++) {
1227                 if (chainmask & (1 << i)) {
1228                         val = REG_READ(ah, ar9300_cca_regs[i]);
1229                         val &= 0xFFFFFE00;
1230                         val |= (((u32) (-50) << 1) & 0x1ff);
1231                         REG_WRITE(ah, ar9300_cca_regs[i], val);
1232                 }
1233         }
1234 }
1235
1236 /*
1237  * Initialize the ANI register values with default (ini) values.
1238  * This routine is called during a (full) hardware reset after
1239  * all the registers are initialised from the INI.
1240  */
1241 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1242 {
1243         struct ar5416AniState *aniState;
1244         struct ath_common *common = ath9k_hw_common(ah);
1245         struct ath9k_channel *chan = ah->curchan;
1246         struct ath9k_ani_default *iniDef;
1247         int index;
1248         u32 val;
1249
1250         index = ath9k_hw_get_ani_channel_idx(ah, chan);
1251         aniState = &ah->ani[index];
1252         ah->curani = aniState;
1253         iniDef = &aniState->iniDef;
1254
1255         ath_print(common, ATH_DBG_ANI,
1256                   "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1257                   ah->hw_version.macVersion,
1258                   ah->hw_version.macRev,
1259                   ah->opmode,
1260                   chan->channel,
1261                   chan->channelFlags);
1262
1263         val = REG_READ(ah, AR_PHY_SFCORR);
1264         iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1265         iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1266         iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1267
1268         val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1269         iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1270         iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1271         iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1272
1273         val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1274         iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1275         iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1276         iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1277         iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1278         iniDef->firstep = REG_READ_FIELD(ah,
1279                                          AR_PHY_FIND_SIG,
1280                                          AR_PHY_FIND_SIG_FIRSTEP);
1281         iniDef->firstepLow = REG_READ_FIELD(ah,
1282                                             AR_PHY_FIND_SIG_LOW,
1283                                             AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1284         iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1285                                             AR_PHY_TIMING5,
1286                                             AR_PHY_TIMING5_CYCPWR_THR1);
1287         iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1288                                                AR_PHY_EXT_CCA,
1289                                                AR_PHY_EXT_CYCPWR_THR1);
1290
1291         /* these levels just got reset to defaults by the INI */
1292         aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
1293         aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
1294         aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
1295         aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
1296
1297         aniState->cycleCount = 0;
1298 }
1299
1300 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1301 {
1302         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1303
1304         priv_ops->rf_set_freq = ar9003_hw_set_channel;
1305         priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1306         priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1307         priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1308         priv_ops->init_bb = ar9003_hw_init_bb;
1309         priv_ops->process_ini = ar9003_hw_process_ini;
1310         priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1311         priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1312         priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1313         priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1314         priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1315         priv_ops->enable_rfkill = ar9003_hw_enable_rfkill;
1316         priv_ops->set_diversity = ar9003_hw_set_diversity;
1317         priv_ops->ani_control = ar9003_hw_ani_control;
1318         priv_ops->do_getnf = ar9003_hw_do_getnf;
1319         priv_ops->loadnf = ar9003_hw_loadnf;
1320         priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1321 }
1322
1323 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1324 {
1325         struct ath_common *common = ath9k_hw_common(ah);
1326         u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1327         u32 val, idle_count;
1328
1329         if (!idle_tmo_ms) {
1330                 /* disable IRQ, disable chip-reset for BB panic */
1331                 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1332                           REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1333                           ~(AR_PHY_WATCHDOG_RST_ENABLE |
1334                             AR_PHY_WATCHDOG_IRQ_ENABLE));
1335
1336                 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1337                 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1338                           REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1339                           ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1340                             AR_PHY_WATCHDOG_IDLE_ENABLE));
1341
1342                 ath_print(common, ATH_DBG_RESET, "Disabled BB Watchdog\n");
1343                 return;
1344         }
1345
1346         /* enable IRQ, disable chip-reset for BB watchdog */
1347         val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1348         REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1349                   (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1350                   ~AR_PHY_WATCHDOG_RST_ENABLE);
1351
1352         /* bound limit to 10 secs */
1353         if (idle_tmo_ms > 10000)
1354                 idle_tmo_ms = 10000;
1355
1356         /*
1357          * The time unit for watchdog event is 2^15 44/88MHz cycles.
1358          *
1359          * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1360          * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1361          *
1362          * Given we use fast clock now in 5 GHz, these time units should
1363          * be common for both 2 GHz and 5 GHz.
1364          */
1365         idle_count = (100 * idle_tmo_ms) / 74;
1366         if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1367                 idle_count = (100 * idle_tmo_ms) / 37;
1368
1369         /*
1370          * enable watchdog in non-IDLE mode, disable in IDLE mode,
1371          * set idle time-out.
1372          */
1373         REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1374                   AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1375                   AR_PHY_WATCHDOG_IDLE_MASK |
1376                   (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1377
1378         ath_print(common, ATH_DBG_RESET,
1379                   "Enabled BB Watchdog timeout (%u ms)\n",
1380                   idle_tmo_ms);
1381 }
1382
1383 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1384 {
1385         /*
1386          * we want to avoid printing in ISR context so we save the
1387          * watchdog status to be printed later in bottom half context.
1388          */
1389         ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1390
1391         /*
1392          * the watchdog timer should reset on status read but to be sure
1393          * sure we write 0 to the watchdog status bit.
1394          */
1395         REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1396                   ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1397 }
1398
1399 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1400 {
1401         struct ath_common *common = ath9k_hw_common(ah);
1402         u32 rxc_pcnt = 0, rxf_pcnt = 0, txf_pcnt = 0, status;
1403
1404         if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1405                 return;
1406
1407         status = ah->bb_watchdog_last_status;
1408         ath_print(common, ATH_DBG_RESET,
1409                   "\n==== BB update: BB status=0x%08x ====\n", status);
1410         ath_print(common, ATH_DBG_RESET,
1411                   "** BB state: wd=%u det=%u rdar=%u rOFDM=%d "
1412                   "rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1413                   MS(status, AR_PHY_WATCHDOG_INFO),
1414                   MS(status, AR_PHY_WATCHDOG_DET_HANG),
1415                   MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1416                   MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1417                   MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1418                   MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1419                   MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1420                   MS(status, AR_PHY_WATCHDOG_AGC_SM),
1421                   MS(status,AR_PHY_WATCHDOG_SRCH_SM));
1422
1423         ath_print(common, ATH_DBG_RESET,
1424                   "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1425                   REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1426                   REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
1427         ath_print(common, ATH_DBG_RESET,
1428                   "** BB mode: BB_gen_controls=0x%08x **\n",
1429                   REG_READ(ah, AR_PHY_GEN_CTRL));
1430
1431         if (ath9k_hw_GetMibCycleCountsPct(ah, &rxc_pcnt, &rxf_pcnt, &txf_pcnt))
1432                 ath_print(common, ATH_DBG_RESET,
1433                           "** BB busy times: rx_clear=%d%%, "
1434                           "rx_frame=%d%%, tx_frame=%d%% **\n",
1435                           rxc_pcnt, rxf_pcnt, txf_pcnt);
1436
1437         ath_print(common, ATH_DBG_RESET,
1438                   "==== BB update: done ====\n\n");
1439 }
1440 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);