drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2010 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <linux/slab.h>
  19 #include <asm/unaligned.h>
  20
  21 #include "hw.h"
  22 #include "hw-ops.h"
  23 #include "rc.h"
  24 #include "ar9003_mac.h"
  25
  26 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  27
  28 MODULE_AUTHOR("Atheros Communications");
  29 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  30 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  31 MODULE_LICENSE("Dual BSD/GPL");
  32
  33 static int __init ath9k_init(void)
  34 {
  35         return 0;
  36 }
  37 module_init(ath9k_init);
  38
  39 static void __exit ath9k_exit(void)
  40 {
  41         return;
  42 }
  43 module_exit(ath9k_exit);
  44
  45 /* Private hardware callbacks */
  46
  47 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
  48 {
  49         ath9k_hw_private_ops(ah)->init_cal_settings(ah);
  50 }
  51
  52 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
  53 {
  54         ath9k_hw_private_ops(ah)->init_mode_regs(ah);
  55 }
  56
  57 static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
  58 {
  59         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
  60
  61         return priv_ops->macversion_supported(ah->hw_version.macVersion);
  62 }
  63
  64 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
  65                                         struct ath9k_channel *chan)
  66 {
  67         return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
  68 }
  69
  70 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
  71 {
  72         if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
  73                 return;
  74
  75         ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
  76 }
  77
  78 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
  79 {
  80         /* You will not have this callback if using the old ANI */
  81         if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
  82                 return;
  83
  84         ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
  85 }
  86
  87 /********************/
  88 /* Helper Functions */
  89 /********************/
  90
  91 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  92 {
  93         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  94
  95         if (!ah->curchan) /* should really check for CCK instead */
  96                 return usecs *ATH9K_CLOCK_RATE_CCK;
  97         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  98                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  99
 100         if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
 101                 return usecs * ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
 102         else
 103                 return usecs * ATH9K_CLOCK_RATE_5GHZ_OFDM;
 104 }
 105
 106 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
 107 {
 108         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
 109
 110         if (conf_is_ht40(conf))
 111                 return ath9k_hw_mac_clks(ah, usecs) * 2;
 112         else
 113                 return ath9k_hw_mac_clks(ah, usecs);
 114 }
 115
 116 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
 117 {
 118         int i;
 119
 120         BUG_ON(timeout < AH_TIME_QUANTUM);
 121
 122         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
 123                 if ((REG_READ(ah, reg) & mask) == val)
 124                         return true;
 125
 126                 udelay(AH_TIME_QUANTUM);
 127         }
 128
 129         ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
 130                   "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 131                   timeout, reg, REG_READ(ah, reg), mask, val);
 132
 133         return false;
 134 }
 135 EXPORT_SYMBOL(ath9k_hw_wait);
 136
 137 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 138 {
 139         u32 retval;
 140         int i;
 141
 142         for (i = 0, retval = 0; i < n; i++) {
 143                 retval = (retval << 1) | (val & 1);
 144                 val >>= 1;
 145         }
 146         return retval;
 147 }
 148
 149 bool ath9k_get_channel_edges(struct ath_hw *ah,
 150                              u16 flags, u16 *low,
 151                              u16 *high)
 152 {
 153         struct ath9k_hw_capabilities *pCap = &ah->caps;
 154
 155         if (flags & CHANNEL_5GHZ) {
 156                 *low = pCap->low_5ghz_chan;
 157                 *high = pCap->high_5ghz_chan;
 158                 return true;
 159         }
 160         if ((flags & CHANNEL_2GHZ)) {
 161                 *low = pCap->low_2ghz_chan;
 162                 *high = pCap->high_2ghz_chan;
 163                 return true;
 164         }
 165         return false;
 166 }
 167
 168 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 169                            u8 phy, int kbps,
 170                            u32 frameLen, u16 rateix,
 171                            bool shortPreamble)
 172 {
 173         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 174
 175         if (kbps == 0)
 176                 return 0;
 177
 178         switch (phy) {
 179         case WLAN_RC_PHY_CCK:
 180                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 181                 if (shortPreamble)
 182                         phyTime >>= 1;
 183                 numBits = frameLen << 3;
 184                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 185                 break;
 186         case WLAN_RC_PHY_OFDM:
 187                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 188                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 189                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 190                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 191                         txTime = OFDM_SIFS_TIME_QUARTER
 192                                 + OFDM_PREAMBLE_TIME_QUARTER
 193                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 194                 } else if (ah->curchan &&
 195                            IS_CHAN_HALF_RATE(ah->curchan)) {
 196                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 197                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 198                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 199                         txTime = OFDM_SIFS_TIME_HALF +
 200                                 OFDM_PREAMBLE_TIME_HALF
 201                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 202                 } else {
 203                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 204                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 205                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 206                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 207                                 + (numSymbols * OFDM_SYMBOL_TIME);
 208                 }
 209                 break;
 210         default:
 211                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 212                           "Unknown phy %u (rate ix %u)\n", phy, rateix);
 213                 txTime = 0;
 214                 break;
 215         }
 216
 217         return txTime;
 218 }
 219 EXPORT_SYMBOL(ath9k_hw_computetxtime);
 220
 221 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 222                                   struct ath9k_channel *chan,
 223                                   struct chan_centers *centers)
 224 {
 225         int8_t extoff;
 226
 227         if (!IS_CHAN_HT40(chan)) {
 228                 centers->ctl_center = centers->ext_center =
 229                         centers->synth_center = chan->channel;
 230                 return;
 231         }
 232
 233         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 234             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 235                 centers->synth_center =
 236                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 237                 extoff = 1;
 238         } else {
 239                 centers->synth_center =
 240                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 241                 extoff = -1;
 242         }
 243
 244         centers->ctl_center =
 245                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 246         /* 25 MHz spacing is supported by hw but not on upper layers */
 247         centers->ext_center =
 248                 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
 249 }
 250
 251 /******************/
 252 /* Chip Revisions */
 253 /******************/
 254
 255 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 256 {
 257         u32 val;
 258
 259         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 260
 261         if (val == 0xFF) {
 262                 val = REG_READ(ah, AR_SREV);
 263                 ah->hw_version.macVersion =
 264                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 265                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 266                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 267         } else {
 268                 if (!AR_SREV_9100(ah))
 269                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 270
 271                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 272
 273                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 274                         ah->is_pciexpress = true;
 275         }
 276 }
 277
 278 /************************************/
 279 /* HW Attach, Detach, Init Routines */
 280 /************************************/
 281
 282 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 283 {
 284         if (AR_SREV_9100(ah))
 285                 return;
 286
 287         ENABLE_REGWRITE_BUFFER(ah);
 288
 289         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 290         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 291         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 292         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 293         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 294         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 295         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 296         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 297         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 298
 299         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 300
 301         REGWRITE_BUFFER_FLUSH(ah);
 302         DISABLE_REGWRITE_BUFFER(ah);
 303 }
 304
 305 /* This should work for all families including legacy */
 306 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 307 {
 308         struct ath_common *common = ath9k_hw_common(ah);
 309         u32 regAddr[2] = { AR_STA_ID0 };
 310         u32 regHold[2];
 311         u32 patternData[4] = { 0x55555555,
 312                                0xaaaaaaaa,
 313                                0x66666666,
 314                                0x99999999 };
 315         int i, j, loop_max;
 316
 317         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 318                 loop_max = 2;
 319                 regAddr[1] = AR_PHY_BASE + (8 << 2);
 320         } else
 321                 loop_max = 1;
 322
 323         for (i = 0; i < loop_max; i++) {
 324                 u32 addr = regAddr[i];
 325                 u32 wrData, rdData;
 326
 327                 regHold[i] = REG_READ(ah, addr);
 328                 for (j = 0; j < 0x100; j++) {
 329                         wrData = (j << 16) | j;
 330                         REG_WRITE(ah, addr, wrData);
 331                         rdData = REG_READ(ah, addr);
 332                         if (rdData != wrData) {
 333                                 ath_print(common, ATH_DBG_FATAL,
 334                                           "address test failed "
 335                                           "addr: 0x%08x - wr:0x%08x != "
 336                                           "rd:0x%08x\n",
 337                                           addr, wrData, rdData);
 338                                 return false;
 339                         }
 340                 }
 341                 for (j = 0; j < 4; j++) {
 342                         wrData = patternData[j];
 343                         REG_WRITE(ah, addr, wrData);
 344                         rdData = REG_READ(ah, addr);
 345                         if (wrData != rdData) {
 346                                 ath_print(common, ATH_DBG_FATAL,
 347                                           "address test failed "
 348                                           "addr: 0x%08x - wr:0x%08x != "
 349                                           "rd:0x%08x\n",
 350                                           addr, wrData, rdData);
 351                                 return false;
 352                         }
 353                 }
 354                 REG_WRITE(ah, regAddr[i], regHold[i]);
 355         }
 356         udelay(100);
 357
 358         return true;
 359 }
 360
 361 static void ath9k_hw_init_config(struct ath_hw *ah)
 362 {
 363         int i;
 364
 365         ah->config.dma_beacon_response_time = 2;
 366         ah->config.sw_beacon_response_time = 10;
 367         ah->config.additional_swba_backoff = 0;
 368         ah->config.ack_6mb = 0x0;
 369         ah->config.cwm_ignore_extcca = 0;
 370         ah->config.pcie_powersave_enable = 0;
 371         ah->config.pcie_clock_req = 0;
 372         ah->config.pcie_waen = 0;
 373         ah->config.analog_shiftreg = 1;
 374         ah->config.ofdm_trig_low = 200;
 375         ah->config.ofdm_trig_high = 500;
 376         ah->config.cck_trig_high = 200;
 377         ah->config.cck_trig_low = 100;
 378         ah->config.enable_ani = true;
 379
 380         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 381                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 382                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 383         }
 384
 385         if (ah->hw_version.devid != AR2427_DEVID_PCIE)
 386                 ah->config.ht_enable = 1;
 387         else
 388                 ah->config.ht_enable = 0;
 389
 390         ah->config.rx_intr_mitigation = true;
 391
 392         /*
 393          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 394          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 395          * This means we use it for all AR5416 devices, and the few
 396          * minor PCI AR9280 devices out there.
 397          *
 398          * Serialization is required because these devices do not handle
 399          * well the case of two concurrent reads/writes due to the latency
 400          * involved. During one read/write another read/write can be issued
 401          * on another CPU while the previous read/write may still be working
 402          * on our hardware, if we hit this case the hardware poops in a loop.
 403          * We prevent this by serializing reads and writes.
 404          *
 405          * This issue is not present on PCI-Express devices or pre-AR5416
 406          * devices (legacy, 802.11abg).
 407          */
 408         if (num_possible_cpus() > 1)
 409                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 410 }
 411
 412 static void ath9k_hw_init_defaults(struct ath_hw *ah)
 413 {
 414         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 415
 416         regulatory->country_code = CTRY_DEFAULT;
 417         regulatory->power_limit = MAX_RATE_POWER;
 418         regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
 419
 420         ah->hw_version.magic = AR5416_MAGIC;
 421         ah->hw_version.subvendorid = 0;
 422
 423         ah->ah_flags = 0;
 424         if (!AR_SREV_9100(ah))
 425                 ah->ah_flags = AH_USE_EEPROM;
 426
 427         ah->atim_window = 0;
 428         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 429         ah->beacon_interval = 100;
 430         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 431         ah->slottime = (u32) -1;
 432         ah->globaltxtimeout = (u32) -1;
 433         ah->power_mode = ATH9K_PM_UNDEFINED;
 434 }
 435
 436 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 437 {
 438         struct ath_common *common = ath9k_hw_common(ah);
 439         u32 sum;
 440         int i;
 441         u16 eeval;
 442         u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
 443
 444         sum = 0;
 445         for (i = 0; i < 3; i++) {
 446                 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
 447                 sum += eeval;
 448                 common->macaddr[2 * i] = eeval >> 8;
 449                 common->macaddr[2 * i + 1] = eeval & 0xff;
 450         }
 451         if (sum == 0 || sum == 0xffff * 3)
 452                 return -EADDRNOTAVAIL;
 453
 454         return 0;
 455 }
 456
 457 static int ath9k_hw_post_init(struct ath_hw *ah)
 458 {
 459         int ecode;
 460
 461         if (!AR_SREV_9271(ah)) {
 462                 if (!ath9k_hw_chip_test(ah))
 463                         return -ENODEV;
 464         }
 465
 466         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 467                 ecode = ar9002_hw_rf_claim(ah);
 468                 if (ecode != 0)
 469                         return ecode;
 470         }
 471
 472         ecode = ath9k_hw_eeprom_init(ah);
 473         if (ecode != 0)
 474                 return ecode;
 475
 476         ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
 477                   "Eeprom VER: %d, REV: %d\n",
 478                   ah->eep_ops->get_eeprom_ver(ah),
 479                   ah->eep_ops->get_eeprom_rev(ah));
 480
 481         ecode = ath9k_hw_rf_alloc_ext_banks(ah);
 482         if (ecode) {
 483                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 484                           "Failed allocating banks for "
 485                           "external radio\n");
 486                 return ecode;
 487         }
 488
 489         if (!AR_SREV_9100(ah)) {
 490                 ath9k_hw_ani_setup(ah);
 491                 ath9k_hw_ani_init(ah);
 492         }
 493
 494         return 0;
 495 }
 496
 497 static void ath9k_hw_attach_ops(struct ath_hw *ah)
 498 {
 499         if (AR_SREV_9300_20_OR_LATER(ah))
 500                 ar9003_hw_attach_ops(ah);
 501         else
 502                 ar9002_hw_attach_ops(ah);
 503 }
 504
 505 /* Called for all hardware families */
 506 static int __ath9k_hw_init(struct ath_hw *ah)
 507 {
 508         struct ath_common *common = ath9k_hw_common(ah);
 509         int r = 0;
 510
 511         if (ah->hw_version.devid == AR5416_AR9100_DEVID)
 512                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 513
 514         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 515                 ath_print(common, ATH_DBG_FATAL,
 516                           "Couldn't reset chip\n");
 517                 return -EIO;
 518         }
 519
 520         ath9k_hw_init_defaults(ah);
 521         ath9k_hw_init_config(ah);
 522
 523         ath9k_hw_attach_ops(ah);
 524
 525         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 526                 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 527                 return -EIO;
 528         }
 529
 530         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 531                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 532                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 533                         ah->config.serialize_regmode =
 534                                 SER_REG_MODE_ON;
 535                 } else {
 536                         ah->config.serialize_regmode =
 537                                 SER_REG_MODE_OFF;
 538                 }
 539         }
 540
 541         ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
 542                 ah->config.serialize_regmode);
 543
 544         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 545                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
 546         else
 547                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
 548
 549         if (!ath9k_hw_macversion_supported(ah)) {
 550                 ath_print(common, ATH_DBG_FATAL,
 551                           "Mac Chip Rev 0x%02x.%x is not supported by "
 552                           "this driver\n", ah->hw_version.macVersion,
 553                           ah->hw_version.macRev);
 554                 return -EOPNOTSUPP;
 555         }
 556
 557         if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
 558                 ah->is_pciexpress = false;
 559
 560         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 561         ath9k_hw_init_cal_settings(ah);
 562
 563         ah->ani_function = ATH9K_ANI_ALL;
 564         if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
 565                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 566         if (!AR_SREV_9300_20_OR_LATER(ah))
 567                 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
 568
 569         ath9k_hw_init_mode_regs(ah);
 570
 571         /*
 572          * Configire PCIE after Ini init. SERDES values now come from ini file
 573          * This enables PCIe low power mode.
 574          */
 575         if (AR_SREV_9300_20_OR_LATER(ah)) {
 576                 u32 regval;
 577                 unsigned int i;
 578
 579                 /* Set Bits 16 and 17 in the AR_WA register. */
 580                 regval = REG_READ(ah, AR_WA);
 581                 regval |= 0x00030000;
 582                 REG_WRITE(ah, AR_WA, regval);
 583
 584                 for (i = 0; i < ah->iniPcieSerdesLowPower.ia_rows; i++) {
 585                         REG_WRITE(ah,
 586                                   INI_RA(&ah->iniPcieSerdesLowPower, i, 0),
 587                                   INI_RA(&ah->iniPcieSerdesLowPower, i, 1));
 588                 }
 589         }
 590
 591         if (ah->is_pciexpress)
 592                 ath9k_hw_configpcipowersave(ah, 0, 0);
 593         else
 594                 ath9k_hw_disablepcie(ah);
 595
 596         if (!AR_SREV_9300_20_OR_LATER(ah))
 597                 ar9002_hw_cck_chan14_spread(ah);
 598
 599         r = ath9k_hw_post_init(ah);
 600         if (r)
 601                 return r;
 602
 603         ath9k_hw_init_mode_gain_regs(ah);
 604         r = ath9k_hw_fill_cap_info(ah);
 605         if (r)
 606                 return r;
 607
 608         r = ath9k_hw_init_macaddr(ah);
 609         if (r) {
 610                 ath_print(common, ATH_DBG_FATAL,
 611                           "Failed to initialize MAC address\n");
 612                 return r;
 613         }
 614
 615         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 616                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 617         else
 618                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 619
 620         if (AR_SREV_9300_20_OR_LATER(ah))
 621                 ar9003_hw_set_nf_limits(ah);
 622
 623         ath9k_init_nfcal_hist_buffer(ah);
 624         ah->bb_watchdog_timeout_ms = 25;
 625
 626         common->state = ATH_HW_INITIALIZED;
 627
 628         return 0;
 629 }
 630
 631 int ath9k_hw_init(struct ath_hw *ah)
 632 {
 633         int ret;
 634         struct ath_common *common = ath9k_hw_common(ah);
 635
 636         /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
 637         switch (ah->hw_version.devid) {
 638         case AR5416_DEVID_PCI:
 639         case AR5416_DEVID_PCIE:
 640         case AR5416_AR9100_DEVID:
 641         case AR9160_DEVID_PCI:
 642         case AR9280_DEVID_PCI:
 643         case AR9280_DEVID_PCIE:
 644         case AR9285_DEVID_PCIE:
 645         case AR9287_DEVID_PCI:
 646         case AR9287_DEVID_PCIE:
 647         case AR2427_DEVID_PCIE:
 648         case AR9300_DEVID_PCIE:
 649                 break;
 650         default:
 651                 if (common->bus_ops->ath_bus_type == ATH_USB)
 652                         break;
 653                 ath_print(common, ATH_DBG_FATAL,
 654                           "Hardware device ID 0x%04x not supported\n",
 655                           ah->hw_version.devid);
 656                 return -EOPNOTSUPP;
 657         }
 658
 659         ret = __ath9k_hw_init(ah);
 660         if (ret) {
 661                 ath_print(common, ATH_DBG_FATAL,
 662                           "Unable to initialize hardware; "
 663                           "initialization status: %d\n", ret);
 664                 return ret;
 665         }
 666
 667         return 0;
 668 }
 669 EXPORT_SYMBOL(ath9k_hw_init);
 670
 671 static void ath9k_hw_init_qos(struct ath_hw *ah)
 672 {
 673         ENABLE_REGWRITE_BUFFER(ah);
 674
 675         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 676         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 677
 678         REG_WRITE(ah, AR_QOS_NO_ACK,
 679                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 680                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 681                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 682
 683         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 684         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 685         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 686         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 687         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 688
 689         REGWRITE_BUFFER_FLUSH(ah);
 690         DISABLE_REGWRITE_BUFFER(ah);
 691 }
 692
 693 static void ath9k_hw_init_pll(struct ath_hw *ah,
 694                               struct ath9k_channel *chan)
 695 {
 696         u32 pll = ath9k_hw_compute_pll_control(ah, chan);
 697
 698         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
 699
 700         /* Switch the core clock for ar9271 to 117Mhz */
 701         if (AR_SREV_9271(ah)) {
 702                 udelay(500);
 703                 REG_WRITE(ah, 0x50040, 0x304);
 704         }
 705
 706         udelay(RTC_PLL_SETTLE_DELAY);
 707
 708         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
 709 }
 710
 711 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
 712                                           enum nl80211_iftype opmode)
 713 {
 714         u32 imr_reg = AR_IMR_TXERR |
 715                 AR_IMR_TXURN |
 716                 AR_IMR_RXERR |
 717                 AR_IMR_RXORN |
 718                 AR_IMR_BCNMISC;
 719
 720         if (AR_SREV_9300_20_OR_LATER(ah)) {
 721                 imr_reg |= AR_IMR_RXOK_HP;
 722                 if (ah->config.rx_intr_mitigation)
 723                         imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
 724                 else
 725                         imr_reg |= AR_IMR_RXOK_LP;
 726
 727         } else {
 728                 if (ah->config.rx_intr_mitigation)
 729                         imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
 730                 else
 731                         imr_reg |= AR_IMR_RXOK;
 732         }
 733
 734         if (ah->config.tx_intr_mitigation)
 735                 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
 736         else
 737                 imr_reg |= AR_IMR_TXOK;
 738
 739         if (opmode == NL80211_IFTYPE_AP)
 740                 imr_reg |= AR_IMR_MIB;
 741
 742         ENABLE_REGWRITE_BUFFER(ah);
 743
 744         REG_WRITE(ah, AR_IMR, imr_reg);
 745         ah->imrs2_reg |= AR_IMR_S2_GTT;
 746         REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
 747
 748         if (!AR_SREV_9100(ah)) {
 749                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
 750                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
 751                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
 752         }
 753
 754         REGWRITE_BUFFER_FLUSH(ah);
 755         DISABLE_REGWRITE_BUFFER(ah);
 756
 757         if (AR_SREV_9300_20_OR_LATER(ah)) {
 758                 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
 759                 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
 760                 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
 761                 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
 762         }
 763 }
 764
 765 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
 766 {
 767         u32 val = ath9k_hw_mac_to_clks(ah, us);
 768         val = min(val, (u32) 0xFFFF);
 769         REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
 770 }
 771
 772 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
 773 {
 774         u32 val = ath9k_hw_mac_to_clks(ah, us);
 775         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
 776         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
 777 }
 778
 779 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
 780 {
 781         u32 val = ath9k_hw_mac_to_clks(ah, us);
 782         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
 783         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
 784 }
 785
 786 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
 787 {
 788         if (tu > 0xFFFF) {
 789                 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
 790                           "bad global tx timeout %u\n", tu);
 791                 ah->globaltxtimeout = (u32) -1;
 792                 return false;
 793         } else {
 794                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
 795                 ah->globaltxtimeout = tu;
 796                 return true;
 797         }
 798 }
 799
 800 void ath9k_hw_init_global_settings(struct ath_hw *ah)
 801 {
 802         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
 803         int acktimeout;
 804         int slottime;
 805         int sifstime;
 806
 807         ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
 808                   ah->misc_mode);
 809
 810         if (ah->misc_mode != 0)
 811                 REG_WRITE(ah, AR_PCU_MISC,
 812                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
 813
 814         if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
 815                 sifstime = 16;
 816         else
 817                 sifstime = 10;
 818
 819         /* As defined by IEEE 802.11-2007 17.3.8.6 */
 820         slottime = ah->slottime + 3 * ah->coverage_class;
 821         acktimeout = slottime + sifstime;
 822
 823         /*
 824          * Workaround for early ACK timeouts, add an offset to match the
 825          * initval's 64us ack timeout value.
 826          * This was initially only meant to work around an issue with delayed
 827          * BA frames in some implementations, but it has been found to fix ACK
 828          * timeout issues in other cases as well.
 829          */
 830         if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
 831                 acktimeout += 64 - sifstime - ah->slottime;
 832
 833         ath9k_hw_setslottime(ah, slottime);
 834         ath9k_hw_set_ack_timeout(ah, acktimeout);
 835         ath9k_hw_set_cts_timeout(ah, acktimeout);
 836         if (ah->globaltxtimeout != (u32) -1)
 837                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
 838 }
 839 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
 840
 841 void ath9k_hw_deinit(struct ath_hw *ah)
 842 {
 843         struct ath_common *common = ath9k_hw_common(ah);
 844
 845         if (common->state < ATH_HW_INITIALIZED)
 846                 goto free_hw;
 847
 848         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
 849
 850 free_hw:
 851         ath9k_hw_rf_free_ext_banks(ah);
 852 }
 853 EXPORT_SYMBOL(ath9k_hw_deinit);
 854
 855 /*******/
 856 /* INI */
 857 /*******/
 858
 859 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
 860 {
 861         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
 862
 863         if (IS_CHAN_B(chan))
 864                 ctl |= CTL_11B;
 865         else if (IS_CHAN_G(chan))
 866                 ctl |= CTL_11G;
 867         else
 868                 ctl |= CTL_11A;
 869
 870         return ctl;
 871 }
 872
 873 /****************************************/
 874 /* Reset and Channel Switching Routines */
 875 /****************************************/
 876
 877 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
 878 {
 879         struct ath_common *common = ath9k_hw_common(ah);
 880         u32 regval;
 881
 882         ENABLE_REGWRITE_BUFFER(ah);
 883
 884         /*
 885          * set AHB_MODE not to do cacheline prefetches
 886         */
 887         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 888                 regval = REG_READ(ah, AR_AHB_MODE);
 889                 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
 890         }
 891
 892         /*
 893          * let mac dma reads be in 128 byte chunks
 894          */
 895         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
 896         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
 897
 898         REGWRITE_BUFFER_FLUSH(ah);
 899         DISABLE_REGWRITE_BUFFER(ah);
 900
 901         /*
 902          * Restore TX Trigger Level to its pre-reset value.
 903          * The initial value depends on whether aggregation is enabled, and is
 904          * adjusted whenever underruns are detected.
 905          */
 906         if (!AR_SREV_9300_20_OR_LATER(ah))
 907                 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
 908
 909         ENABLE_REGWRITE_BUFFER(ah);
 910
 911         /*
 912          * let mac dma writes be in 128 byte chunks
 913          */
 914         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
 915         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
 916
 917         /*
 918          * Setup receive FIFO threshold to hold off TX activities
 919          */
 920         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
 921
 922         if (AR_SREV_9300_20_OR_LATER(ah)) {
 923                 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
 924                 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
 925
 926                 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
 927                         ah->caps.rx_status_len);
 928         }
 929
 930         /*
 931          * reduce the number of usable entries in PCU TXBUF to avoid
 932          * wrap around issues.
 933          */
 934         if (AR_SREV_9285(ah)) {
 935                 /* For AR9285 the number of Fifos are reduced to half.
 936                  * So set the usable tx buf size also to half to
 937                  * avoid data/delimiter underruns
 938                  */
 939                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
 940                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
 941         } else if (!AR_SREV_9271(ah)) {
 942                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
 943                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
 944         }
 945
 946         REGWRITE_BUFFER_FLUSH(ah);
 947         DISABLE_REGWRITE_BUFFER(ah);
 948
 949         if (AR_SREV_9300_20_OR_LATER(ah))
 950                 ath9k_hw_reset_txstatus_ring(ah);
 951 }
 952
 953 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
 954 {
 955         u32 val;
 956
 957         val = REG_READ(ah, AR_STA_ID1);
 958         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
 959         switch (opmode) {
 960         case NL80211_IFTYPE_AP:
 961                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
 962                           | AR_STA_ID1_KSRCH_MODE);
 963                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
 964                 break;
 965         case NL80211_IFTYPE_ADHOC:
 966         case NL80211_IFTYPE_MESH_POINT:
 967                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
 968                           | AR_STA_ID1_KSRCH_MODE);
 969                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
 970                 break;
 971         case NL80211_IFTYPE_STATION:
 972         case NL80211_IFTYPE_MONITOR:
 973                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
 974                 break;
 975         }
 976 }
 977
 978 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
 979                                    u32 *coef_mantissa, u32 *coef_exponent)
 980 {
 981         u32 coef_exp, coef_man;
 982
 983         for (coef_exp = 31; coef_exp > 0; coef_exp--)
 984                 if ((coef_scaled >> coef_exp) & 0x1)
 985                         break;
 986
 987         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
 988
 989         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
 990
 991         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
 992         *coef_exponent = coef_exp - 16;
 993 }
 994
 995 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
 996 {
 997         u32 rst_flags;
 998         u32 tmpReg;
 999
1000         if (AR_SREV_9100(ah)) {
1001                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1002                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1003                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1004                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1005                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1006         }
1007
1008         ENABLE_REGWRITE_BUFFER(ah);
1009
1010         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1011                   AR_RTC_FORCE_WAKE_ON_INT);
1012
1013         if (AR_SREV_9100(ah)) {
1014                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1015                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1016         } else {
1017                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1018                 if (tmpReg &
1019                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1020                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1021                         u32 val;
1022                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1023
1024                         val = AR_RC_HOSTIF;
1025                         if (!AR_SREV_9300_20_OR_LATER(ah))
1026                                 val |= AR_RC_AHB;
1027                         REG_WRITE(ah, AR_RC, val);
1028
1029                 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1030                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1031
1032                 rst_flags = AR_RTC_RC_MAC_WARM;
1033                 if (type == ATH9K_RESET_COLD)
1034                         rst_flags |= AR_RTC_RC_MAC_COLD;
1035         }
1036
1037         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1038
1039         REGWRITE_BUFFER_FLUSH(ah);
1040         DISABLE_REGWRITE_BUFFER(ah);
1041
1042         udelay(50);
1043
1044         REG_WRITE(ah, AR_RTC_RC, 0);
1045         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1046                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1047                           "RTC stuck in MAC reset\n");
1048                 return false;
1049         }
1050
1051         if (!AR_SREV_9100(ah))
1052                 REG_WRITE(ah, AR_RC, 0);
1053
1054         if (AR_SREV_9100(ah))
1055                 udelay(50);
1056
1057         return true;
1058 }
1059
1060 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1061 {
1062         ENABLE_REGWRITE_BUFFER(ah);
1063
1064         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1065                   AR_RTC_FORCE_WAKE_ON_INT);
1066
1067         if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1068                 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1069
1070         REG_WRITE(ah, AR_RTC_RESET, 0);
1071
1072         REGWRITE_BUFFER_FLUSH(ah);
1073         DISABLE_REGWRITE_BUFFER(ah);
1074
1075         if (!AR_SREV_9300_20_OR_LATER(ah))
1076                 udelay(2);
1077
1078         if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1079                 REG_WRITE(ah, AR_RC, 0);
1080
1081         REG_WRITE(ah, AR_RTC_RESET, 1);
1082
1083         if (!ath9k_hw_wait(ah,
1084                            AR_RTC_STATUS,
1085                            AR_RTC_STATUS_M,
1086                            AR_RTC_STATUS_ON,
1087                            AH_WAIT_TIMEOUT)) {
1088                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1089                           "RTC not waking up\n");
1090                 return false;
1091         }
1092
1093         ath9k_hw_read_revisions(ah);
1094
1095         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1096 }
1097
1098 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1099 {
1100         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1101                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1102
1103         switch (type) {
1104         case ATH9K_RESET_POWER_ON:
1105                 return ath9k_hw_set_reset_power_on(ah);
1106         case ATH9K_RESET_WARM:
1107         case ATH9K_RESET_COLD:
1108                 return ath9k_hw_set_reset(ah, type);
1109         default:
1110                 return false;
1111         }
1112 }
1113
1114 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1115                                 struct ath9k_channel *chan)
1116 {
1117         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1118                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1119                         return false;
1120         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1121                 return false;
1122
1123         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1124                 return false;
1125
1126         ah->chip_fullsleep = false;
1127         ath9k_hw_init_pll(ah, chan);
1128         ath9k_hw_set_rfmode(ah, chan);
1129
1130         return true;
1131 }
1132
1133 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1134                                     struct ath9k_channel *chan)
1135 {
1136         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1137         struct ath_common *common = ath9k_hw_common(ah);
1138         struct ieee80211_channel *channel = chan->chan;
1139         u32 qnum;
1140         int r;
1141
1142         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1143                 if (ath9k_hw_numtxpending(ah, qnum)) {
1144                         ath_print(common, ATH_DBG_QUEUE,
1145                                   "Transmit frames pending on "
1146                                   "queue %d\n", qnum);
1147                         return false;
1148                 }
1149         }
1150
1151         if (!ath9k_hw_rfbus_req(ah)) {
1152                 ath_print(common, ATH_DBG_FATAL,
1153                           "Could not kill baseband RX\n");
1154                 return false;
1155         }
1156
1157         ath9k_hw_set_channel_regs(ah, chan);
1158
1159         r = ath9k_hw_rf_set_freq(ah, chan);
1160         if (r) {
1161                 ath_print(common, ATH_DBG_FATAL,
1162                           "Failed to set channel\n");
1163                 return false;
1164         }
1165
1166         ah->eep_ops->set_txpower(ah, chan,
1167                              ath9k_regd_get_ctl(regulatory, chan),
1168                              channel->max_antenna_gain * 2,
1169                              channel->max_power * 2,
1170                              min((u32) MAX_RATE_POWER,
1171                              (u32) regulatory->power_limit));
1172
1173         ath9k_hw_rfbus_done(ah);
1174
1175         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1176                 ath9k_hw_set_delta_slope(ah, chan);
1177
1178         ath9k_hw_spur_mitigate_freq(ah, chan);
1179
1180         if (!chan->oneTimeCalsDone)
1181                 chan->oneTimeCalsDone = true;
1182
1183         return true;
1184 }
1185
1186 bool ath9k_hw_check_alive(struct ath_hw *ah)
1187 {
1188         int count = 50;
1189         u32 reg;
1190
1191         if (AR_SREV_9285_10_OR_LATER(ah))
1192                 return true;
1193
1194         do {
1195                 reg = REG_READ(ah, AR_OBS_BUS_1);
1196
1197                 if ((reg & 0x7E7FFFEF) == 0x00702400)
1198                         continue;
1199
1200                 switch (reg & 0x7E000B00) {
1201                 case 0x1E000000:
1202                 case 0x52000B00:
1203                 case 0x18000B00:
1204                         continue;
1205                 default:
1206                         return true;
1207                 }
1208         } while (count-- > 0);
1209
1210         return false;
1211 }
1212 EXPORT_SYMBOL(ath9k_hw_check_alive);
1213
1214 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1215                     bool bChannelChange)
1216 {
1217         struct ath_common *common = ath9k_hw_common(ah);
1218         u32 saveLedState;
1219         struct ath9k_channel *curchan = ah->curchan;
1220         u32 saveDefAntenna;
1221         u32 macStaId1;
1222         u64 tsf = 0;
1223         int i, r;
1224
1225         ah->txchainmask = common->tx_chainmask;
1226         ah->rxchainmask = common->rx_chainmask;
1227
1228         if (!ah->chip_fullsleep) {
1229                 ath9k_hw_abortpcurecv(ah);
1230                 if (!ath9k_hw_stopdmarecv(ah))
1231                         ath_print(common, ATH_DBG_XMIT,
1232                                 "Failed to stop receive dma\n");
1233         }
1234
1235         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1236                 return -EIO;
1237
1238         if (curchan && !ah->chip_fullsleep)
1239                 ath9k_hw_getnf(ah, curchan);
1240
1241         if (bChannelChange &&
1242             (ah->chip_fullsleep != true) &&
1243             (ah->curchan != NULL) &&
1244             (chan->channel != ah->curchan->channel) &&
1245             ((chan->channelFlags & CHANNEL_ALL) ==
1246              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1247             !AR_SREV_9280(ah)) {
1248
1249                 if (ath9k_hw_channel_change(ah, chan)) {
1250                         ath9k_hw_loadnf(ah, ah->curchan);
1251                         ath9k_hw_start_nfcal(ah);
1252                         return 0;
1253                 }
1254         }
1255
1256         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1257         if (saveDefAntenna == 0)
1258                 saveDefAntenna = 1;
1259
1260         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1261
1262         /* For chips on which RTC reset is done, save TSF before it gets cleared */
1263         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1264                 tsf = ath9k_hw_gettsf64(ah);
1265
1266         saveLedState = REG_READ(ah, AR_CFG_LED) &
1267                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1268                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1269
1270         ath9k_hw_mark_phy_inactive(ah);
1271
1272         /* Only required on the first reset */
1273         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1274                 REG_WRITE(ah,
1275                           AR9271_RESET_POWER_DOWN_CONTROL,
1276                           AR9271_RADIO_RF_RST);
1277                 udelay(50);
1278         }
1279
1280         if (!ath9k_hw_chip_reset(ah, chan)) {
1281                 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1282                 return -EINVAL;
1283         }
1284
1285         /* Only required on the first reset */
1286         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1287                 ah->htc_reset_init = false;
1288                 REG_WRITE(ah,
1289                           AR9271_RESET_POWER_DOWN_CONTROL,
1290                           AR9271_GATE_MAC_CTL);
1291                 udelay(50);
1292         }
1293
1294         /* Restore TSF */
1295         if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1296                 ath9k_hw_settsf64(ah, tsf);
1297
1298         if (AR_SREV_9280_10_OR_LATER(ah))
1299                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1300
1301         if (!AR_SREV_9300_20_OR_LATER(ah))
1302                 ar9002_hw_enable_async_fifo(ah);
1303
1304         r = ath9k_hw_process_ini(ah, chan);
1305         if (r)
1306                 return r;
1307
1308         /* Setup MFP options for CCMP */
1309         if (AR_SREV_9280_20_OR_LATER(ah)) {
1310                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1311                  * frames when constructing CCMP AAD. */
1312                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1313                               0xc7ff);
1314                 ah->sw_mgmt_crypto = false;
1315         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1316                 /* Disable hardware crypto for management frames */
1317                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1318                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1319                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1320                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1321                 ah->sw_mgmt_crypto = true;
1322         } else
1323                 ah->sw_mgmt_crypto = true;
1324
1325         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1326                 ath9k_hw_set_delta_slope(ah, chan);
1327
1328         ath9k_hw_spur_mitigate_freq(ah, chan);
1329         ah->eep_ops->set_board_values(ah, chan);
1330
1331         ath9k_hw_set_operating_mode(ah, ah->opmode);
1332
1333         ENABLE_REGWRITE_BUFFER(ah);
1334
1335         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1336         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1337                   | macStaId1
1338                   | AR_STA_ID1_RTS_USE_DEF
1339                   | (ah->config.
1340                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1341                   | ah->sta_id1_defaults);
1342         ath_hw_setbssidmask(common);
1343         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1344         ath9k_hw_write_associd(ah);
1345         REG_WRITE(ah, AR_ISR, ~0);
1346         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1347
1348         REGWRITE_BUFFER_FLUSH(ah);
1349         DISABLE_REGWRITE_BUFFER(ah);
1350
1351         r = ath9k_hw_rf_set_freq(ah, chan);
1352         if (r)
1353                 return r;
1354
1355         ENABLE_REGWRITE_BUFFER(ah);
1356
1357         for (i = 0; i < AR_NUM_DCU; i++)
1358                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1359
1360         REGWRITE_BUFFER_FLUSH(ah);
1361         DISABLE_REGWRITE_BUFFER(ah);
1362
1363         ah->intr_txqs = 0;
1364         for (i = 0; i < ah->caps.total_queues; i++)
1365                 ath9k_hw_resettxqueue(ah, i);
1366
1367         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1368         ath9k_hw_ani_cache_ini_regs(ah);
1369         ath9k_hw_init_qos(ah);
1370
1371         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1372                 ath9k_enable_rfkill(ah);
1373
1374         ath9k_hw_init_global_settings(ah);
1375
1376         if (!AR_SREV_9300_20_OR_LATER(ah)) {
1377                 ar9002_hw_update_async_fifo(ah);
1378                 ar9002_hw_enable_wep_aggregation(ah);
1379         }
1380
1381         REG_WRITE(ah, AR_STA_ID1,
1382                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1383
1384         ath9k_hw_set_dma(ah);
1385
1386         REG_WRITE(ah, AR_OBS, 8);
1387
1388         if (ah->config.rx_intr_mitigation) {
1389                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1390                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1391         }
1392
1393         if (ah->config.tx_intr_mitigation) {
1394                 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1395                 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1396         }
1397
1398         ath9k_hw_init_bb(ah, chan);
1399
1400         if (!ath9k_hw_init_cal(ah, chan))
1401                 return -EIO;
1402
1403         ENABLE_REGWRITE_BUFFER(ah);
1404
1405         ath9k_hw_restore_chainmask(ah);
1406         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1407
1408         REGWRITE_BUFFER_FLUSH(ah);
1409         DISABLE_REGWRITE_BUFFER(ah);
1410
1411         /*
1412          * For big endian systems turn on swapping for descriptors
1413          */
1414         if (AR_SREV_9100(ah)) {
1415                 u32 mask;
1416                 mask = REG_READ(ah, AR_CFG);
1417                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1418                         ath_print(common, ATH_DBG_RESET,
1419                                 "CFG Byte Swap Set 0x%x\n", mask);
1420                 } else {
1421                         mask =
1422                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1423                         REG_WRITE(ah, AR_CFG, mask);
1424                         ath_print(common, ATH_DBG_RESET,
1425                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1426                 }
1427         } else {
1428                 if (common->bus_ops->ath_bus_type == ATH_USB) {
1429                         /* Configure AR9271 target WLAN */
1430                         if (AR_SREV_9271(ah))
1431                                 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1432                         else
1433                                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1434                 }
1435 #ifdef __BIG_ENDIAN
1436                 else
1437                         REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1438 #endif
1439         }
1440
1441         if (ah->btcoex_hw.enabled)
1442                 ath9k_hw_btcoex_enable(ah);
1443
1444         if (AR_SREV_9300_20_OR_LATER(ah)) {
1445                 ath9k_hw_loadnf(ah, curchan);
1446                 ath9k_hw_start_nfcal(ah);
1447                 ar9003_hw_bb_watchdog_config(ah);
1448         }
1449
1450         return 0;
1451 }
1452 EXPORT_SYMBOL(ath9k_hw_reset);
1453
1454 /************************/
1455 /* Key Cache Management */
1456 /************************/
1457
1458 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
1459 {
1460         u32 keyType;
1461
1462         if (entry >= ah->caps.keycache_size) {
1463                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1464                           "keychache entry %u out of range\n", entry);
1465                 return false;
1466         }
1467
1468         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
1469
1470         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1471         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1472         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1473         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1474         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1475         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1476         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1477         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
1478
1479         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1480                 u16 micentry = entry + 64;
1481
1482                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1483                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1484                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1485                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1486
1487         }
1488
1489         return true;
1490 }
1491 EXPORT_SYMBOL(ath9k_hw_keyreset);
1492
1493 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
1494 {
1495         u32 macHi, macLo;
1496         u32 unicast_flag = AR_KEYTABLE_VALID;
1497
1498         if (entry >= ah->caps.keycache_size) {
1499                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1500                           "keychache entry %u out of range\n", entry);
1501                 return false;
1502         }
1503
1504         if (mac != NULL) {
1505                 /*
1506                  * AR_KEYTABLE_VALID indicates that the address is a unicast
1507                  * address, which must match the transmitter address for
1508                  * decrypting frames.
1509                  * Not setting this bit allows the hardware to use the key
1510                  * for multicast frame decryption.
1511                  */
1512                 if (mac[0] & 0x01)
1513                         unicast_flag = 0;
1514
1515                 macHi = (mac[5] << 8) | mac[4];
1516                 macLo = (mac[3] << 24) |
1517                         (mac[2] << 16) |
1518                         (mac[1] << 8) |
1519                         mac[0];
1520                 macLo >>= 1;
1521                 macLo |= (macHi & 1) << 31;
1522                 macHi >>= 1;
1523         } else {
1524                 macLo = macHi = 0;
1525         }
1526         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1527         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | unicast_flag);
1528
1529         return true;
1530 }
1531 EXPORT_SYMBOL(ath9k_hw_keysetmac);
1532
1533 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
1534                                  const struct ath9k_keyval *k,
1535                                  const u8 *mac)
1536 {
1537         const struct ath9k_hw_capabilities *pCap = &ah->caps;
1538         struct ath_common *common = ath9k_hw_common(ah);
1539         u32 key0, key1, key2, key3, key4;
1540         u32 keyType;
1541
1542         if (entry >= pCap->keycache_size) {
1543                 ath_print(common, ATH_DBG_FATAL,
1544                           "keycache entry %u out of range\n", entry);
1545                 return false;
1546         }
1547
1548         switch (k->kv_type) {
1549         case ATH9K_CIPHER_AES_OCB:
1550                 keyType = AR_KEYTABLE_TYPE_AES;
1551                 break;
1552         case ATH9K_CIPHER_AES_CCM:
1553                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
1554                         ath_print(common, ATH_DBG_ANY,
1555                                   "AES-CCM not supported by mac rev 0x%x\n",
1556                                   ah->hw_version.macRev);
1557                         return false;
1558                 }
1559                 keyType = AR_KEYTABLE_TYPE_CCM;
1560                 break;
1561         case ATH9K_CIPHER_TKIP:
1562                 keyType = AR_KEYTABLE_TYPE_TKIP;
1563                 if (ATH9K_IS_MIC_ENABLED(ah)
1564                     && entry + 64 >= pCap->keycache_size) {
1565                         ath_print(common, ATH_DBG_ANY,
1566                                   "entry %u inappropriate for TKIP\n", entry);
1567                         return false;
1568                 }
1569                 break;
1570         case ATH9K_CIPHER_WEP:
1571                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
1572                         ath_print(common, ATH_DBG_ANY,
1573                                   "WEP key length %u too small\n", k->kv_len);
1574                         return false;
1575                 }
1576                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
1577                         keyType = AR_KEYTABLE_TYPE_40;
1578                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1579                         keyType = AR_KEYTABLE_TYPE_104;
1580                 else
1581                         keyType = AR_KEYTABLE_TYPE_128;
1582                 break;
1583         case ATH9K_CIPHER_CLR:
1584                 keyType = AR_KEYTABLE_TYPE_CLR;
1585                 break;
1586         default:
1587                 ath_print(common, ATH_DBG_FATAL,
1588                           "cipher %u not supported\n", k->kv_type);
1589                 return false;
1590         }
1591
1592         key0 = get_unaligned_le32(k->kv_val + 0);
1593         key1 = get_unaligned_le16(k->kv_val + 4);
1594         key2 = get_unaligned_le32(k->kv_val + 6);
1595         key3 = get_unaligned_le16(k->kv_val + 10);
1596         key4 = get_unaligned_le32(k->kv_val + 12);
1597         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1598                 key4 &= 0xff;
1599
1600         /*
1601          * Note: Key cache registers access special memory area that requires
1602          * two 32-bit writes to actually update the values in the internal
1603          * memory. Consequently, the exact order and pairs used here must be
1604          * maintained.
1605          */
1606
1607         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1608                 u16 micentry = entry + 64;
1609
1610                 /*
1611                  * Write inverted key[47:0] first to avoid Michael MIC errors
1612                  * on frames that could be sent or received at the same time.
1613                  * The correct key will be written in the end once everything
1614                  * else is ready.
1615                  */
1616                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1617                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
1618
1619                 /* Write key[95:48] */
1620                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1621                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1622
1623                 /* Write key[127:96] and key type */
1624                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1625                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1626
1627                 /* Write MAC address for the entry */
1628                 (void) ath9k_hw_keysetmac(ah, entry, mac);
1629
1630                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
1631                         /*
1632                          * TKIP uses two key cache entries:
1633                          * Michael MIC TX/RX keys in the same key cache entry
1634                          * (idx = main index + 64):
1635                          * key0 [31:0] = RX key [31:0]
1636                          * key1 [15:0] = TX key [31:16]
1637                          * key1 [31:16] = reserved
1638                          * key2 [31:0] = RX key [63:32]
1639                          * key3 [15:0] = TX key [15:0]
1640                          * key3 [31:16] = reserved
1641                          * key4 [31:0] = TX key [63:32]
1642                          */
1643                         u32 mic0, mic1, mic2, mic3, mic4;
1644
1645                         mic0 = get_unaligned_le32(k->kv_mic + 0);
1646                         mic2 = get_unaligned_le32(k->kv_mic + 4);
1647                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1648                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1649                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
1650
1651                         /* Write RX[31:0] and TX[31:16] */
1652                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1653                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
1654
1655                         /* Write RX[63:32] and TX[15:0] */
1656                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1657                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
1658
1659                         /* Write TX[63:32] and keyType(reserved) */
1660                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1661                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1662                                   AR_KEYTABLE_TYPE_CLR);
1663
1664                 } else {
1665                         /*
1666                          * TKIP uses four key cache entries (two for group
1667                          * keys):
1668                          * Michael MIC TX/RX keys are in different key cache
1669                          * entries (idx = main index + 64 for TX and
1670                          * main index + 32 + 96 for RX):
1671                          * key0 [31:0] = TX/RX MIC key [31:0]
1672                          * key1 [31:0] = reserved
1673                          * key2 [31:0] = TX/RX MIC key [63:32]
1674                          * key3 [31:0] = reserved
1675                          * key4 [31:0] = reserved
1676                          *
1677                          * Upper layer code will call this function separately
1678                          * for TX and RX keys when these registers offsets are
1679                          * used.
1680                          */
1681                         u32 mic0, mic2;
1682
1683                         mic0 = get_unaligned_le32(k->kv_mic + 0);
1684                         mic2 = get_unaligned_le32(k->kv_mic + 4);
1685
1686                         /* Write MIC key[31:0] */
1687                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1688                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1689
1690                         /* Write MIC key[63:32] */
1691                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1692                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1693
1694                         /* Write TX[63:32] and keyType(reserved) */
1695                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1696                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1697                                   AR_KEYTABLE_TYPE_CLR);
1698                 }
1699
1700                 /* MAC address registers are reserved for the MIC entry */
1701                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1702                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
1703
1704                 /*
1705                  * Write the correct (un-inverted) key[47:0] last to enable
1706                  * TKIP now that all other registers are set with correct
1707                  * values.
1708                  */
1709                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1710                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1711         } else {
1712                 /* Write key[47:0] */
1713                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1714                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1715
1716                 /* Write key[95:48] */
1717                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1718                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1719
1720                 /* Write key[127:96] and key type */
1721                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1722                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1723
1724                 /* Write MAC address for the entry */
1725                 (void) ath9k_hw_keysetmac(ah, entry, mac);
1726         }
1727
1728         return true;
1729 }
1730 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
1731
1732 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
1733 {
1734         if (entry < ah->caps.keycache_size) {
1735                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
1736                 if (val & AR_KEYTABLE_VALID)
1737                         return true;
1738         }
1739         return false;
1740 }
1741 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
1742
1743 /******************************/
1744 /* Power Management (Chipset) */
1745 /******************************/
1746
1747 /*
1748  * Notify Power Mgt is disabled in self-generated frames.
1749  * If requested, force chip to sleep.
1750  */
1751 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1752 {
1753         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1754         if (setChip) {
1755                 /*
1756                  * Clear the RTC force wake bit to allow the
1757                  * mac to go to sleep.
1758                  */
1759                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1760                             AR_RTC_FORCE_WAKE_EN);
1761                 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1762                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1763
1764                 /* Shutdown chip. Active low */
1765                 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1766                         REG_CLR_BIT(ah, (AR_RTC_RESET),
1767                                     AR_RTC_RESET_EN);
1768         }
1769 }
1770
1771 /*
1772  * Notify Power Management is enabled in self-generating
1773  * frames. If request, set power mode of chip to
1774  * auto/normal.  Duration in units of 128us (1/8 TU).
1775  */
1776 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1777 {
1778         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1779         if (setChip) {
1780                 struct ath9k_hw_capabilities *pCap = &ah->caps;
1781
1782                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1783                         /* Set WakeOnInterrupt bit; clear ForceWake bit */
1784                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1785                                   AR_RTC_FORCE_WAKE_ON_INT);
1786                 } else {
1787                         /*
1788                          * Clear the RTC force wake bit to allow the
1789                          * mac to go to sleep.
1790                          */
1791                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1792                                     AR_RTC_FORCE_WAKE_EN);
1793                 }
1794         }
1795 }
1796
1797 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1798 {
1799         u32 val;
1800         int i;
1801
1802         if (setChip) {
1803                 if ((REG_READ(ah, AR_RTC_STATUS) &
1804                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1805                         if (ath9k_hw_set_reset_reg(ah,
1806                                            ATH9K_RESET_POWER_ON) != true) {
1807                                 return false;
1808                         }
1809                         if (!AR_SREV_9300_20_OR_LATER(ah))
1810                                 ath9k_hw_init_pll(ah, NULL);
1811                 }
1812                 if (AR_SREV_9100(ah))
1813                         REG_SET_BIT(ah, AR_RTC_RESET,
1814                                     AR_RTC_RESET_EN);
1815
1816                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1817                             AR_RTC_FORCE_WAKE_EN);
1818                 udelay(50);
1819
1820                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1821                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1822                         if (val == AR_RTC_STATUS_ON)
1823                                 break;
1824                         udelay(50);
1825                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1826                                     AR_RTC_FORCE_WAKE_EN);
1827                 }
1828                 if (i == 0) {
1829                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1830                                   "Failed to wakeup in %uus\n",
1831                                   POWER_UP_TIME / 20);
1832                         return false;
1833                 }
1834         }
1835
1836         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1837
1838         return true;
1839 }
1840
1841 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1842 {
1843         struct ath_common *common = ath9k_hw_common(ah);
1844         int status = true, setChip = true;
1845         static const char *modes[] = {
1846                 "AWAKE",
1847                 "FULL-SLEEP",
1848                 "NETWORK SLEEP",
1849                 "UNDEFINED"
1850         };
1851
1852         if (ah->power_mode == mode)
1853                 return status;
1854
1855         ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1856                   modes[ah->power_mode], modes[mode]);
1857
1858         switch (mode) {
1859         case ATH9K_PM_AWAKE:
1860                 status = ath9k_hw_set_power_awake(ah, setChip);
1861                 break;
1862         case ATH9K_PM_FULL_SLEEP:
1863                 ath9k_set_power_sleep(ah, setChip);
1864                 ah->chip_fullsleep = true;
1865                 break;
1866         case ATH9K_PM_NETWORK_SLEEP:
1867                 ath9k_set_power_network_sleep(ah, setChip);
1868                 break;
1869         default:
1870                 ath_print(common, ATH_DBG_FATAL,
1871                           "Unknown power mode %u\n", mode);
1872                 return false;
1873         }
1874         ah->power_mode = mode;
1875
1876         return status;
1877 }
1878 EXPORT_SYMBOL(ath9k_hw_setpower);
1879
1880 /*******************/
1881 /* Beacon Handling */
1882 /*******************/
1883
1884 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1885 {
1886         int flags = 0;
1887
1888         ah->beacon_interval = beacon_period;
1889
1890         ENABLE_REGWRITE_BUFFER(ah);
1891
1892         switch (ah->opmode) {
1893         case NL80211_IFTYPE_STATION:
1894         case NL80211_IFTYPE_MONITOR:
1895                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1896                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1897                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1898                 flags |= AR_TBTT_TIMER_EN;
1899                 break;
1900         case NL80211_IFTYPE_ADHOC:
1901         case NL80211_IFTYPE_MESH_POINT:
1902                 REG_SET_BIT(ah, AR_TXCFG,
1903                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1904                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1905                           TU_TO_USEC(next_beacon +
1906                                      (ah->atim_window ? ah->
1907                                       atim_window : 1)));
1908                 flags |= AR_NDP_TIMER_EN;
1909         case NL80211_IFTYPE_AP:
1910                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1911                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1912                           TU_TO_USEC(next_beacon -
1913                                      ah->config.
1914                                      dma_beacon_response_time));
1915                 REG_WRITE(ah, AR_NEXT_SWBA,
1916                           TU_TO_USEC(next_beacon -
1917                                      ah->config.
1918                                      sw_beacon_response_time));
1919                 flags |=
1920                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1921                 break;
1922         default:
1923                 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1924                           "%s: unsupported opmode: %d\n",
1925                           __func__, ah->opmode);
1926                 return;
1927                 break;
1928         }
1929
1930         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1931         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1932         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1933         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1934
1935         REGWRITE_BUFFER_FLUSH(ah);
1936         DISABLE_REGWRITE_BUFFER(ah);
1937
1938         beacon_period &= ~ATH9K_BEACON_ENA;
1939         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
1940                 ath9k_hw_reset_tsf(ah);
1941         }
1942
1943         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1944 }
1945 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1946
1947 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1948                                     const struct ath9k_beacon_state *bs)
1949 {
1950         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1951         struct ath9k_hw_capabilities *pCap = &ah->caps;
1952         struct ath_common *common = ath9k_hw_common(ah);
1953
1954         ENABLE_REGWRITE_BUFFER(ah);
1955
1956         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1957
1958         REG_WRITE(ah, AR_BEACON_PERIOD,
1959                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1960         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1961                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1962
1963         REGWRITE_BUFFER_FLUSH(ah);
1964         DISABLE_REGWRITE_BUFFER(ah);
1965
1966         REG_RMW_FIELD(ah, AR_RSSI_THR,
1967                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1968
1969         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1970
1971         if (bs->bs_sleepduration > beaconintval)
1972                 beaconintval = bs->bs_sleepduration;
1973
1974         dtimperiod = bs->bs_dtimperiod;
1975         if (bs->bs_sleepduration > dtimperiod)
1976                 dtimperiod = bs->bs_sleepduration;
1977
1978         if (beaconintval == dtimperiod)
1979                 nextTbtt = bs->bs_nextdtim;
1980         else
1981                 nextTbtt = bs->bs_nexttbtt;
1982
1983         ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1984         ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1985         ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1986         ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1987
1988         ENABLE_REGWRITE_BUFFER(ah);
1989
1990         REG_WRITE(ah, AR_NEXT_DTIM,
1991                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1992         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1993
1994         REG_WRITE(ah, AR_SLEEP1,
1995                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1996                   | AR_SLEEP1_ASSUME_DTIM);
1997
1998         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1999                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2000         else
2001                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2002
2003         REG_WRITE(ah, AR_SLEEP2,
2004                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2005
2006         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2007         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2008
2009         REGWRITE_BUFFER_FLUSH(ah);
2010         DISABLE_REGWRITE_BUFFER(ah);
2011
2012         REG_SET_BIT(ah, AR_TIMER_MODE,
2013                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2014                     AR_DTIM_TIMER_EN);
2015
2016         /* TSF Out of Range Threshold */
2017         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2018 }
2019 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2020
2021 /*******************/
2022 /* HW Capabilities */
2023 /*******************/
2024
2025 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2026 {
2027         struct ath9k_hw_capabilities *pCap = &ah->caps;
2028         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2029         struct ath_common *common = ath9k_hw_common(ah);
2030         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
2031
2032         u16 capField = 0, eeval;
2033
2034         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2035         regulatory->current_rd = eeval;
2036
2037         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
2038         if (AR_SREV_9285_10_OR_LATER(ah))
2039                 eeval |= AR9285_RDEXT_DEFAULT;
2040         regulatory->current_rd_ext = eeval;
2041
2042         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
2043
2044         if (ah->opmode != NL80211_IFTYPE_AP &&
2045             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2046                 if (regulatory->current_rd == 0x64 ||
2047                     regulatory->current_rd == 0x65)
2048                         regulatory->current_rd += 5;
2049                 else if (regulatory->current_rd == 0x41)
2050                         regulatory->current_rd = 0x43;
2051                 ath_print(common, ATH_DBG_REGULATORY,
2052                           "regdomain mapped to 0x%x\n", regulatory->current_rd);
2053         }
2054
2055         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2056         if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2057                 ath_print(common, ATH_DBG_FATAL,
2058                           "no band has been marked as supported in EEPROM.\n");
2059                 return -EINVAL;
2060         }
2061
2062         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
2063
2064         if (eeval & AR5416_OPFLAGS_11A) {
2065                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2066                 if (ah->config.ht_enable) {
2067                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2068                                 set_bit(ATH9K_MODE_11NA_HT20,
2069                                         pCap->wireless_modes);
2070                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2071                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2072                                         pCap->wireless_modes);
2073                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2074                                         pCap->wireless_modes);
2075                         }
2076                 }
2077         }
2078
2079         if (eeval & AR5416_OPFLAGS_11G) {
2080                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2081                 if (ah->config.ht_enable) {
2082                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2083                                 set_bit(ATH9K_MODE_11NG_HT20,
2084                                         pCap->wireless_modes);
2085                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2086                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2087                                         pCap->wireless_modes);
2088                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
2089                                         pCap->wireless_modes);
2090                         }
2091                 }
2092         }
2093
2094         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2095         /*
2096          * For AR9271 we will temporarilly uses the rx chainmax as read from
2097          * the EEPROM.
2098          */
2099         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2100             !(eeval & AR5416_OPFLAGS_11A) &&
2101             !(AR_SREV_9271(ah)))
2102                 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2103                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2104         else
2105                 /* Use rx_chainmask from EEPROM. */
2106                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2107
2108         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2109                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2110
2111         pCap->low_2ghz_chan = 2312;
2112         pCap->high_2ghz_chan = 2732;
2113
2114         pCap->low_5ghz_chan = 4920;
2115         pCap->high_5ghz_chan = 6100;
2116
2117         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2118         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2119         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
2120
2121         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
2122         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2123         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
2124
2125         if (ah->config.ht_enable)
2126                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2127         else
2128                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2129
2130         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2131         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2132         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2133         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
2134
2135         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
2136                 pCap->total_queues =
2137                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
2138         else
2139                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
2140
2141         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2142                 pCap->keycache_size =
2143                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2144         else
2145                 pCap->keycache_size = AR_KEYTABLE_SIZE;
2146
2147         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
2148
2149         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2150                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2151         else
2152                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
2153
2154         if (AR_SREV_9271(ah))
2155                 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2156         else if (AR_SREV_9285_10_OR_LATER(ah))
2157                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2158         else if (AR_SREV_9280_10_OR_LATER(ah))
2159                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2160         else
2161                 pCap->num_gpio_pins = AR_NUM_GPIO;
2162
2163         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2164                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2165                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2166         } else {
2167                 pCap->rts_aggr_limit = (8 * 1024);
2168         }
2169
2170         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2171
2172 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2173         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2174         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2175                 ah->rfkill_gpio =
2176                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2177                 ah->rfkill_polarity =
2178                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2179
2180                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2181         }
2182 #endif
2183         if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2184                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2185         else
2186                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2187
2188         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2189                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2190         else
2191                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2192
2193         if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
2194                 pCap->reg_cap =
2195                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2196                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2197                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
2198                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
2199         } else {
2200                 pCap->reg_cap =
2201                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2202                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
2203         }
2204
2205         /* Advertise midband for AR5416 with FCC midband set in eeprom */
2206         if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2207             AR_SREV_5416(ah))
2208                 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
2209
2210         pCap->num_antcfg_5ghz =
2211                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
2212         pCap->num_antcfg_2ghz =
2213                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
2214
2215         if (AR_SREV_9280_10_OR_LATER(ah) &&
2216             ath9k_hw_btcoex_supported(ah)) {
2217                 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2218                 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
2219
2220                 if (AR_SREV_9285(ah)) {
2221                         btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2222                         btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
2223                 } else {
2224                         btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2225                 }
2226         } else {
2227                 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2228         }
2229
2230         if (AR_SREV_9300_20_OR_LATER(ah)) {
2231                 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC |
2232                                  ATH9K_HW_CAP_FASTCLOCK;
2233                 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2234                 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2235                 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2236                 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2237                 pCap->txs_len = sizeof(struct ar9003_txs);
2238                 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2239                         pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2240         } else {
2241                 pCap->tx_desc_len = sizeof(struct ath_desc);
2242                 if (AR_SREV_9280_20(ah) &&
2243                     ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
2244                       AR5416_EEP_MINOR_VER_16) ||
2245                      ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
2246                         pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2247         }
2248
2249         if (AR_SREV_9300_20_OR_LATER(ah))
2250                 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2251
2252         if (AR_SREV_9287_10_OR_LATER(ah) || AR_SREV_9271(ah))
2253                 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2254
2255         return 0;
2256 }
2257
2258 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2259                             u32 capability, u32 *result)
2260 {
2261         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2262         switch (type) {
2263         case ATH9K_CAP_TKIP_MIC:
2264                 switch (capability) {
2265                 case 0:
2266                         return true;
2267                 case 1:
2268                         return (ah->sta_id1_defaults &
2269                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
2270                         false;
2271                 }
2272         case ATH9K_CAP_TKIP_SPLIT:
2273                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
2274                         false : true;
2275         case ATH9K_CAP_MCAST_KEYSRCH:
2276                 switch (capability) {
2277                 case 0:
2278                         return true;
2279                 case 1:
2280                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
2281                                 return false;
2282                         } else {
2283                                 return (ah->sta_id1_defaults &
2284                                         AR_STA_ID1_MCAST_KSRCH) ? true :
2285                                         false;
2286                         }
2287                 }
2288                 return false;
2289         case ATH9K_CAP_TXPOW:
2290                 switch (capability) {
2291                 case 0:
2292                         return 0;
2293                 case 1:
2294                         *result = regulatory->power_limit;
2295                         return 0;
2296                 case 2:
2297                         *result = regulatory->max_power_level;
2298                         return 0;
2299                 case 3:
2300                         *result = regulatory->tp_scale;
2301                         return 0;
2302                 }
2303                 return false;
2304         case ATH9K_CAP_DS:
2305                 return (AR_SREV_9280_20_OR_LATER(ah) &&
2306                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
2307                         ? false : true;
2308         default:
2309                 return false;
2310         }
2311 }
2312 EXPORT_SYMBOL(ath9k_hw_getcapability);
2313
2314 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2315                             u32 capability, u32 setting, int *status)
2316 {
2317         switch (type) {
2318         case ATH9K_CAP_TKIP_MIC:
2319                 if (setting)
2320                         ah->sta_id1_defaults |=
2321                                 AR_STA_ID1_CRPT_MIC_ENABLE;
2322                 else
2323                         ah->sta_id1_defaults &=
2324                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
2325                 return true;
2326         case ATH9K_CAP_MCAST_KEYSRCH:
2327                 if (setting)
2328                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
2329                 else
2330                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
2331                 return true;
2332         default:
2333                 return false;
2334         }
2335 }
2336 EXPORT_SYMBOL(ath9k_hw_setcapability);
2337
2338 /****************************/
2339 /* GPIO / RFKILL / Antennae */
2340 /****************************/
2341
2342 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2343                                          u32 gpio, u32 type)
2344 {
2345         int addr;
2346         u32 gpio_shift, tmp;
2347
2348         if (gpio > 11)
2349                 addr = AR_GPIO_OUTPUT_MUX3;
2350         else if (gpio > 5)
2351                 addr = AR_GPIO_OUTPUT_MUX2;
2352         else
2353                 addr = AR_GPIO_OUTPUT_MUX1;
2354
2355         gpio_shift = (gpio % 6) * 5;
2356
2357         if (AR_SREV_9280_20_OR_LATER(ah)
2358             || (addr != AR_GPIO_OUTPUT_MUX1)) {
2359                 REG_RMW(ah, addr, (type << gpio_shift),
2360                         (0x1f << gpio_shift));
2361         } else {
2362                 tmp = REG_READ(ah, addr);
2363                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2364                 tmp &= ~(0x1f << gpio_shift);
2365                 tmp |= (type << gpio_shift);
2366                 REG_WRITE(ah, addr, tmp);
2367         }
2368 }
2369
2370 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2371 {
2372         u32 gpio_shift;
2373
2374         BUG_ON(gpio >= ah->caps.num_gpio_pins);
2375
2376         gpio_shift = gpio << 1;
2377
2378         REG_RMW(ah,
2379                 AR_GPIO_OE_OUT,
2380                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2381                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2382 }
2383 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2384
2385 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2386 {
2387 #define MS_REG_READ(x, y) \
2388         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2389
2390         if (gpio >= ah->caps.num_gpio_pins)
2391                 return 0xffffffff;
2392
2393         if (AR_SREV_9300_20_OR_LATER(ah))
2394                 return MS_REG_READ(AR9300, gpio) != 0;
2395         else if (AR_SREV_9271(ah))
2396                 return MS_REG_READ(AR9271, gpio) != 0;
2397         else if (AR_SREV_9287_10_OR_LATER(ah))
2398                 return MS_REG_READ(AR9287, gpio) != 0;
2399         else if (AR_SREV_9285_10_OR_LATER(ah))
2400                 return MS_REG_READ(AR9285, gpio) != 0;
2401         else if (AR_SREV_9280_10_OR_LATER(ah))
2402                 return MS_REG_READ(AR928X, gpio) != 0;
2403         else
2404                 return MS_REG_READ(AR, gpio) != 0;
2405 }
2406 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2407
2408 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2409                          u32 ah_signal_type)
2410 {
2411         u32 gpio_shift;
2412
2413         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2414
2415         gpio_shift = 2 * gpio;
2416
2417         REG_RMW(ah,
2418                 AR_GPIO_OE_OUT,
2419                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2420                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2421 }
2422 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2423
2424 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2425 {
2426         if (AR_SREV_9271(ah))
2427                 val = ~val;
2428
2429         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2430                 AR_GPIO_BIT(gpio));
2431 }
2432 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2433
2434 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2435 {
2436         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2437 }
2438 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2439
2440 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2441 {
2442         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2443 }
2444 EXPORT_SYMBOL(ath9k_hw_setantenna);
2445
2446 /*********************/
2447 /* General Operation */
2448 /*********************/
2449
2450 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2451 {
2452         u32 bits = REG_READ(ah, AR_RX_FILTER);
2453         u32 phybits = REG_READ(ah, AR_PHY_ERR);
2454
2455         if (phybits & AR_PHY_ERR_RADAR)
2456                 bits |= ATH9K_RX_FILTER_PHYRADAR;
2457         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2458                 bits |= ATH9K_RX_FILTER_PHYERR;
2459
2460         return bits;
2461 }
2462 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2463
2464 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2465 {
2466         u32 phybits;
2467
2468         ENABLE_REGWRITE_BUFFER(ah);
2469
2470         REG_WRITE(ah, AR_RX_FILTER, bits);
2471
2472         phybits = 0;
2473         if (bits & ATH9K_RX_FILTER_PHYRADAR)
2474                 phybits |= AR_PHY_ERR_RADAR;
2475         if (bits & ATH9K_RX_FILTER_PHYERR)
2476                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2477         REG_WRITE(ah, AR_PHY_ERR, phybits);
2478
2479         if (phybits)
2480                 REG_WRITE(ah, AR_RXCFG,
2481                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2482         else
2483                 REG_WRITE(ah, AR_RXCFG,
2484                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2485
2486         REGWRITE_BUFFER_FLUSH(ah);
2487         DISABLE_REGWRITE_BUFFER(ah);
2488 }
2489 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2490
2491 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2492 {
2493         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2494                 return false;
2495
2496         ath9k_hw_init_pll(ah, NULL);
2497         return true;
2498 }
2499 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2500
2501 bool ath9k_hw_disable(struct ath_hw *ah)
2502 {
2503         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2504                 return false;
2505
2506         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2507                 return false;
2508
2509         ath9k_hw_init_pll(ah, NULL);
2510         return true;
2511 }
2512 EXPORT_SYMBOL(ath9k_hw_disable);
2513
2514 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
2515 {
2516         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2517         struct ath9k_channel *chan = ah->curchan;
2518         struct ieee80211_channel *channel = chan->chan;
2519
2520         regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2521
2522         ah->eep_ops->set_txpower(ah, chan,
2523                                  ath9k_regd_get_ctl(regulatory, chan),
2524                                  channel->max_antenna_gain * 2,
2525                                  channel->max_power * 2,
2526                                  min((u32) MAX_RATE_POWER,
2527                                  (u32) regulatory->power_limit));
2528 }
2529 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2530
2531 void ath9k_hw_setopmode(struct ath_hw *ah)
2532 {
2533         ath9k_hw_set_operating_mode(ah, ah->opmode);
2534 }
2535 EXPORT_SYMBOL(ath9k_hw_setopmode);
2536
2537 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2538 {
2539         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2540         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2541 }
2542 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2543
2544 void ath9k_hw_write_associd(struct ath_hw *ah)
2545 {
2546         struct ath_common *common = ath9k_hw_common(ah);
2547
2548         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2549         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2550                   ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2551 }
2552 EXPORT_SYMBOL(ath9k_hw_write_associd);
2553
2554 #define ATH9K_MAX_TSF_READ 10
2555
2556 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2557 {
2558         u32 tsf_lower, tsf_upper1, tsf_upper2;
2559         int i;
2560
2561         tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2562         for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2563                 tsf_lower = REG_READ(ah, AR_TSF_L32);
2564                 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2565                 if (tsf_upper2 == tsf_upper1)
2566                         break;
2567                 tsf_upper1 = tsf_upper2;
2568         }
2569
2570         WARN_ON( i == ATH9K_MAX_TSF_READ );
2571
2572         return (((u64)tsf_upper1 << 32) | tsf_lower);
2573 }
2574 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2575
2576 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2577 {
2578         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2579         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2580 }
2581 EXPORT_SYMBOL(ath9k_hw_settsf64);
2582
2583 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2584 {
2585         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2586                            AH_TSF_WRITE_TIMEOUT))
2587                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2588                           "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2589
2590         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2591 }
2592 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2593
2594 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2595 {
2596         if (setting)
2597                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2598         else
2599                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2600 }
2601 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2602
2603 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2604 {
2605         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2606         u32 macmode;
2607
2608         if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2609                 macmode = AR_2040_JOINED_RX_CLEAR;
2610         else
2611                 macmode = 0;
2612
2613         REG_WRITE(ah, AR_2040_MODE, macmode);
2614 }
2615
2616 /* HW Generic timers configuration */
2617
2618 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2619 {
2620         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2621         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2622         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2623         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2624         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2625         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2626         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2627         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2628         {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2629         {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2630                                 AR_NDP2_TIMER_MODE, 0x0002},
2631         {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2632                                 AR_NDP2_TIMER_MODE, 0x0004},
2633         {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2634                                 AR_NDP2_TIMER_MODE, 0x0008},
2635         {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2636                                 AR_NDP2_TIMER_MODE, 0x0010},
2637         {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2638                                 AR_NDP2_TIMER_MODE, 0x0020},
2639         {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2640                                 AR_NDP2_TIMER_MODE, 0x0040},
2641         {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2642                                 AR_NDP2_TIMER_MODE, 0x0080}
2643 };
2644
2645 /* HW generic timer primitives */
2646
2647 /* compute and clear index of rightmost 1 */
2648 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2649 {
2650         u32 b;
2651
2652         b = *mask;
2653         b &= (0-b);
2654         *mask &= ~b;
2655         b *= debruijn32;
2656         b >>= 27;
2657
2658         return timer_table->gen_timer_index[b];
2659 }
2660
2661 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2662 {
2663         return REG_READ(ah, AR_TSF_L32);
2664 }
2665 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2666
2667 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2668                                           void (*trigger)(void *),
2669                                           void (*overflow)(void *),
2670                                           void *arg,
2671                                           u8 timer_index)
2672 {
2673         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2674         struct ath_gen_timer *timer;
2675
2676         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2677
2678         if (timer == NULL) {
2679                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2680                           "Failed to allocate memory"
2681                           "for hw timer[%d]\n", timer_index);
2682                 return NULL;
2683         }
2684
2685         /* allocate a hardware generic timer slot */
2686         timer_table->timers[timer_index] = timer;
2687         timer->index = timer_index;
2688         timer->trigger = trigger;
2689         timer->overflow = overflow;
2690         timer->arg = arg;
2691
2692         return timer;
2693 }
2694 EXPORT_SYMBOL(ath_gen_timer_alloc);
2695
2696 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2697                               struct ath_gen_timer *timer,
2698                               u32 timer_next,
2699                               u32 timer_period)
2700 {
2701         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2702         u32 tsf;
2703
2704         BUG_ON(!timer_period);
2705
2706         set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2707
2708         tsf = ath9k_hw_gettsf32(ah);
2709
2710         ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2711                   "curent tsf %x period %x"
2712                   "timer_next %x\n", tsf, timer_period, timer_next);
2713
2714         /*
2715          * Pull timer_next forward if the current TSF already passed it
2716          * because of software latency
2717          */
2718         if (timer_next < tsf)
2719                 timer_next = tsf + timer_period;
2720
2721         /*
2722          * Program generic timer registers
2723          */
2724         REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2725                  timer_next);
2726         REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2727                   timer_period);
2728         REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2729                     gen_tmr_configuration[timer->index].mode_mask);
2730
2731         /* Enable both trigger and thresh interrupt masks */
2732         REG_SET_BIT(ah, AR_IMR_S5,
2733                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2734                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2735 }
2736 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2737
2738 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2739 {
2740         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2741
2742         if ((timer->index < AR_FIRST_NDP_TIMER) ||
2743                 (timer->index >= ATH_MAX_GEN_TIMER)) {
2744                 return;
2745         }
2746
2747         /* Clear generic timer enable bits. */
2748         REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2749                         gen_tmr_configuration[timer->index].mode_mask);
2750
2751         /* Disable both trigger and thresh interrupt masks */
2752         REG_CLR_BIT(ah, AR_IMR_S5,
2753                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2754                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2755
2756         clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2757 }
2758 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2759
2760 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2761 {
2762         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2763
2764         /* free the hardware generic timer slot */
2765         timer_table->timers[timer->index] = NULL;
2766         kfree(timer);
2767 }
2768 EXPORT_SYMBOL(ath_gen_timer_free);
2769
2770 /*
2771  * Generic Timer Interrupts handling
2772  */
2773 void ath_gen_timer_isr(struct ath_hw *ah)
2774 {
2775         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2776         struct ath_gen_timer *timer;
2777         struct ath_common *common = ath9k_hw_common(ah);
2778         u32 trigger_mask, thresh_mask, index;
2779
2780         /* get hardware generic timer interrupt status */
2781         trigger_mask = ah->intr_gen_timer_trigger;
2782         thresh_mask = ah->intr_gen_timer_thresh;
2783         trigger_mask &= timer_table->timer_mask.val;
2784         thresh_mask &= timer_table->timer_mask.val;
2785
2786         trigger_mask &= ~thresh_mask;
2787
2788         while (thresh_mask) {
2789                 index = rightmost_index(timer_table, &thresh_mask);
2790                 timer = timer_table->timers[index];
2791                 BUG_ON(!timer);
2792                 ath_print(common, ATH_DBG_HWTIMER,
2793                           "TSF overflow for Gen timer %d\n", index);
2794                 timer->overflow(timer->arg);
2795         }
2796
2797         while (trigger_mask) {
2798                 index = rightmost_index(timer_table, &trigger_mask);
2799                 timer = timer_table->timers[index];
2800                 BUG_ON(!timer);
2801                 ath_print(common, ATH_DBG_HWTIMER,
2802                           "Gen timer[%d] trigger\n", index);
2803                 timer->trigger(timer->arg);
2804         }
2805 }
2806 EXPORT_SYMBOL(ath_gen_timer_isr);
2807
2808 /********/
2809 /* HTC  */
2810 /********/
2811
2812 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2813 {
2814         ah->htc_reset_init = true;
2815 }
2816 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2817
2818 static struct {
2819         u32 version;
2820         const char * name;
2821 } ath_mac_bb_names[] = {
2822         /* Devices with external radios */
2823         { AR_SREV_VERSION_5416_PCI,     "5416" },
2824         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2825         { AR_SREV_VERSION_9100,         "9100" },
2826         { AR_SREV_VERSION_9160,         "9160" },
2827         /* Single-chip solutions */
2828         { AR_SREV_VERSION_9280,         "9280" },
2829         { AR_SREV_VERSION_9285,         "9285" },
2830         { AR_SREV_VERSION_9287,         "9287" },
2831         { AR_SREV_VERSION_9271,         "9271" },
2832         { AR_SREV_VERSION_9300,         "9300" },
2833 };
2834
2835 /* For devices with external radios */
2836 static struct {
2837         u16 version;
2838         const char * name;
2839 } ath_rf_names[] = {
2840         { 0,                            "5133" },
2841         { AR_RAD5133_SREV_MAJOR,        "5133" },
2842         { AR_RAD5122_SREV_MAJOR,        "5122" },
2843         { AR_RAD2133_SREV_MAJOR,        "2133" },
2844         { AR_RAD2122_SREV_MAJOR,        "2122" }
2845 };
2846
2847 /*
2848  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2849  */
2850 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2851 {
2852         int i;
2853
2854         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2855                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2856                         return ath_mac_bb_names[i].name;
2857                 }
2858         }
2859
2860         return "????";
2861 }
2862
2863 /*
2864  * Return the RF name. "????" is returned if the RF is unknown.
2865  * Used for devices with external radios.
2866  */
2867 static const char *ath9k_hw_rf_name(u16 rf_version)
2868 {
2869         int i;
2870
2871         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2872                 if (ath_rf_names[i].version == rf_version) {
2873                         return ath_rf_names[i].name;
2874                 }
2875         }
2876
2877         return "????";
2878 }
2879
2880 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2881 {
2882         int used;
2883
2884         /* chipsets >= AR9280 are single-chip */
2885         if (AR_SREV_9280_10_OR_LATER(ah)) {
2886                 used = snprintf(hw_name, len,
2887                                "Atheros AR%s Rev:%x",
2888                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2889                                ah->hw_version.macRev);
2890         }
2891         else {
2892                 used = snprintf(hw_name, len,
2893                                "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2894                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2895                                ah->hw_version.macRev,
2896                                ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2897                                                 AR_RADIO_SREV_MAJOR)),
2898                                ah->hw_version.phyRev);
2899         }
2900
2901         hw_name[used] = '\0';
2902 }
2903 EXPORT_SYMBOL(ath9k_hw_name);