2 * Copyright (c) 2008-2010 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
35 #define ATHEROS_VENDOR_ID 0x168c
37 #define AR5416_DEVID_PCI 0x0023
38 #define AR5416_DEVID_PCIE 0x0024
39 #define AR9160_DEVID_PCI 0x0027
40 #define AR9280_DEVID_PCI 0x0029
41 #define AR9280_DEVID_PCIE 0x002a
42 #define AR9285_DEVID_PCIE 0x002b
43 #define AR2427_DEVID_PCIE 0x002c
44 #define AR9287_DEVID_PCI 0x002d
45 #define AR9287_DEVID_PCIE 0x002e
46 #define AR9300_DEVID_PCIE 0x0030
48 #define AR5416_AR9100_DEVID 0x000b
50 #define AR_SUBVENDOR_ID_NOG 0x0e11
51 #define AR_SUBVENDOR_ID_NEW_A 0x7065
52 #define AR5416_MAGIC 0x19641014
54 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
55 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
56 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
58 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
60 #define ATH_DEFAULT_NOISE_FLOOR -95
62 #define ATH9K_RSSI_BAD -128
64 /* Register read/write primitives */
65 #define REG_WRITE(_ah, _reg, _val) \
66 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
68 #define REG_READ(_ah, _reg) \
69 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
71 #define ENABLE_REGWRITE_BUFFER(_ah) \
73 if (AR_SREV_9271(_ah)) \
74 ath9k_hw_common(_ah)->ops->enable_write_buffer((_ah)); \
77 #define DISABLE_REGWRITE_BUFFER(_ah) \
79 if (AR_SREV_9271(_ah)) \
80 ath9k_hw_common(_ah)->ops->disable_write_buffer((_ah)); \
83 #define REGWRITE_BUFFER_FLUSH(_ah) \
85 if (AR_SREV_9271(_ah)) \
86 ath9k_hw_common(_ah)->ops->write_flush((_ah)); \
89 #define SM(_v, _f) (((_v) << _f##_S) & _f)
90 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
91 #define REG_RMW(_a, _r, _set, _clr) \
92 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
93 #define REG_RMW_FIELD(_a, _r, _f, _v) \
95 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
96 #define REG_READ_FIELD(_a, _r, _f) \
97 (((REG_READ(_a, _r) & _f) >> _f##_S))
98 #define REG_SET_BIT(_a, _r, _f) \
99 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
100 #define REG_CLR_BIT(_a, _r, _f) \
101 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
103 #define DO_DELAY(x) do { \
104 if ((++(x) % 64) == 0) \
108 #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
110 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
111 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
112 INI_RA((iniarray), r, (column))); \
117 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
118 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
119 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
120 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
121 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
122 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
123 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
125 #define AR_GPIOD_MASK 0x00001FFF
126 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
128 #define BASE_ACTIVATE_DELAY 100
129 #define RTC_PLL_SETTLE_DELAY 100
130 #define COEF_SCALE_S 24
131 #define HT40_CHANNEL_CENTER_SHIFT 10
133 #define ATH9K_ANTENNA0_CHAINMASK 0x1
134 #define ATH9K_ANTENNA1_CHAINMASK 0x2
136 #define ATH9K_NUM_DMA_DEBUG_REGS 8
137 #define ATH9K_NUM_QUEUES 10
139 #define MAX_RATE_POWER 63
140 #define AH_WAIT_TIMEOUT 100000 /* (us) */
141 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
142 #define AH_TIME_QUANTUM 10
143 #define AR_KEYTABLE_SIZE 128
144 #define POWER_UP_TIME 10000
145 #define SPUR_RSSI_THRESH 40
147 #define CAB_TIMEOUT_VAL 10
148 #define BEACON_TIMEOUT_VAL 10
149 #define MIN_BEACON_TIMEOUT_VAL 1
152 #define INIT_CONFIG_STATUS 0x00000000
153 #define INIT_RSSI_THR 0x00000700
154 #define INIT_BCON_CNTRL_REG 0x00000000
156 #define TU_TO_USEC(_tu) ((_tu) << 10)
158 #define ATH9K_HW_RX_HP_QDEPTH 16
159 #define ATH9K_HW_RX_LP_QDEPTH 128
161 enum ath_ini_subsys {
171 ATH9K_MODE_11NA_HT20,
172 ATH9K_MODE_11NG_HT20,
173 ATH9K_MODE_11NA_HT40PLUS,
174 ATH9K_MODE_11NA_HT40MINUS,
175 ATH9K_MODE_11NG_HT40PLUS,
176 ATH9K_MODE_11NG_HT40MINUS,
181 ATH9K_HW_CAP_MIC_AESCCM = BIT(0),
182 ATH9K_HW_CAP_MIC_CKIP = BIT(1),
183 ATH9K_HW_CAP_MIC_TKIP = BIT(2),
184 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3),
185 ATH9K_HW_CAP_CIPHER_CKIP = BIT(4),
186 ATH9K_HW_CAP_CIPHER_TKIP = BIT(5),
187 ATH9K_HW_CAP_VEOL = BIT(6),
188 ATH9K_HW_CAP_BSSIDMASK = BIT(7),
189 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8),
190 ATH9K_HW_CAP_HT = BIT(9),
191 ATH9K_HW_CAP_GTT = BIT(10),
192 ATH9K_HW_CAP_FASTCC = BIT(11),
193 ATH9K_HW_CAP_RFSILENT = BIT(12),
194 ATH9K_HW_CAP_CST = BIT(13),
195 ATH9K_HW_CAP_ENHANCEDPM = BIT(14),
196 ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
197 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
198 ATH9K_HW_CAP_EDMA = BIT(17),
199 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(18),
200 ATH9K_HW_CAP_LDPC = BIT(19),
203 enum ath9k_capability_type {
204 ATH9K_CAP_CIPHER = 0,
206 ATH9K_CAP_TKIP_SPLIT,
208 ATH9K_CAP_MCAST_KEYSRCH,
212 struct ath9k_hw_capabilities {
213 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
214 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
217 u16 low_5ghz_chan, high_5ghz_chan;
218 u16 low_2ghz_chan, high_2ghz_chan;
222 u16 tx_triglevel_max;
234 struct ath9k_ops_config {
235 int dma_beacon_response_time;
236 int sw_beacon_response_time;
237 int additional_swba_backoff;
239 int cwm_ignore_extcca;
240 u8 pcie_powersave_enable;
250 int serialize_regmode;
251 bool rx_intr_mitigation;
252 bool tx_intr_mitigation;
253 #define SPUR_DISABLE 0
254 #define SPUR_ENABLE_IOCTL 1
255 #define SPUR_ENABLE_EEPROM 2
256 #define AR_EEPROM_MODAL_SPURS 5
257 #define AR_SPUR_5413_1 1640
258 #define AR_SPUR_5413_2 1200
259 #define AR_NO_SPUR 0x8000
260 #define AR_BASE_FREQ_2GHZ 2300
261 #define AR_BASE_FREQ_5GHZ 4900
262 #define AR_SPUR_FEEQ_BOUND_HT40 19
263 #define AR_SPUR_FEEQ_BOUND_HT20 10
265 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
270 ATH9K_INT_RX = 0x00000001,
271 ATH9K_INT_RXDESC = 0x00000002,
272 ATH9K_INT_RXHP = 0x00000001,
273 ATH9K_INT_RXLP = 0x00000002,
274 ATH9K_INT_RXNOFRM = 0x00000008,
275 ATH9K_INT_RXEOL = 0x00000010,
276 ATH9K_INT_RXORN = 0x00000020,
277 ATH9K_INT_TX = 0x00000040,
278 ATH9K_INT_TXDESC = 0x00000080,
279 ATH9K_INT_TIM_TIMER = 0x00000100,
280 ATH9K_INT_TXURN = 0x00000800,
281 ATH9K_INT_MIB = 0x00001000,
282 ATH9K_INT_RXPHY = 0x00004000,
283 ATH9K_INT_RXKCM = 0x00008000,
284 ATH9K_INT_SWBA = 0x00010000,
285 ATH9K_INT_BMISS = 0x00040000,
286 ATH9K_INT_BNR = 0x00100000,
287 ATH9K_INT_TIM = 0x00200000,
288 ATH9K_INT_DTIM = 0x00400000,
289 ATH9K_INT_DTIMSYNC = 0x00800000,
290 ATH9K_INT_GPIO = 0x01000000,
291 ATH9K_INT_CABEND = 0x02000000,
292 ATH9K_INT_TSFOOR = 0x04000000,
293 ATH9K_INT_GENTIMER = 0x08000000,
294 ATH9K_INT_CST = 0x10000000,
295 ATH9K_INT_GTT = 0x20000000,
296 ATH9K_INT_FATAL = 0x40000000,
297 ATH9K_INT_GLOBAL = 0x80000000,
298 ATH9K_INT_BMISC = ATH9K_INT_TIM |
303 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
315 ATH9K_INT_NOCARD = 0xffffffff
318 #define CHANNEL_CW_INT 0x00002
319 #define CHANNEL_CCK 0x00020
320 #define CHANNEL_OFDM 0x00040
321 #define CHANNEL_2GHZ 0x00080
322 #define CHANNEL_5GHZ 0x00100
323 #define CHANNEL_PASSIVE 0x00200
324 #define CHANNEL_DYN 0x00400
325 #define CHANNEL_HALF 0x04000
326 #define CHANNEL_QUARTER 0x08000
327 #define CHANNEL_HT20 0x10000
328 #define CHANNEL_HT40PLUS 0x20000
329 #define CHANNEL_HT40MINUS 0x40000
331 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
332 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
333 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
334 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
335 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
336 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
337 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
338 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
339 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
340 #define CHANNEL_ALL \
349 struct ath9k_channel {
350 struct ieee80211_channel *chan;
355 bool oneTimeCalsDone;
358 int16_t rawNoiseFloor;
361 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
362 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
363 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
364 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
365 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
366 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
367 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
368 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
369 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
370 #define IS_CHAN_A_5MHZ_SPACED(_c) \
371 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
372 (((_c)->channel % 20) != 0) && \
373 (((_c)->channel % 10) != 0))
375 /* These macros check chanmode and not channelFlags */
376 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
377 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
378 ((_c)->chanmode == CHANNEL_G_HT20))
379 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
380 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
381 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
382 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
383 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
385 enum ath9k_power_mode {
388 ATH9K_PM_NETWORK_SLEEP,
392 enum ath9k_tp_scale {
393 ATH9K_TP_SCALE_MAX = 0,
401 SER_REG_MODE_OFF = 0,
403 SER_REG_MODE_AUTO = 2,
406 enum ath9k_rx_qtype {
412 struct ath9k_beacon_state {
416 #define ATH9K_BEACON_PERIOD 0x0000ffff
417 #define ATH9K_BEACON_ENA 0x00800000
418 #define ATH9K_BEACON_RESET_TSF 0x01000000
419 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
422 u16 bs_cfpmaxduration;
425 u16 bs_bmissthreshold;
426 u32 bs_sleepduration;
427 u32 bs_tsfoor_threshold;
430 struct chan_centers {
437 ATH9K_RESET_POWER_ON,
442 struct ath9k_hw_version {
454 /* Generic TSF timer definitions */
456 #define ATH_MAX_GEN_TIMER 16
458 #define AR_GENTMR_BIT(_index) (1 << (_index))
461 * Using de Bruijin sequence to to look up 1's index in a 32 bit number
462 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
464 #define debruijn32 0x077CB531U
466 struct ath_gen_timer_configuration {
473 struct ath_gen_timer {
474 void (*trigger)(void *arg);
475 void (*overflow)(void *arg);
480 struct ath_gen_timer_table {
481 u32 gen_timer_index[32];
482 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
484 unsigned long timer_bits;
490 * struct ath_hw_private_ops - callbacks used internally by hardware code
492 * This structure contains private callbacks designed to only be used internally
493 * by the hardware core.
495 * @init_cal_settings: setup types of calibrations supported
496 * @init_cal: starts actual calibration
498 * @init_mode_regs: Initializes mode registers
499 * @init_mode_gain_regs: Initialize TX/RX gain registers
500 * @macversion_supported: If this specific mac revision is supported
502 * @rf_set_freq: change frequency
503 * @spur_mitigate_freq: spur mitigation
504 * @rf_alloc_ext_banks:
505 * @rf_free_ext_banks:
507 * @compute_pll_control: compute the PLL control value to use for
508 * AR_RTC_PLL_CONTROL for a given channel
509 * @setup_calibration: set up calibration
510 * @iscal_supported: used to query if a type of calibration is supported
511 * @loadnf: load noise floor read from each chain on the CCA registers
513 struct ath_hw_private_ops {
514 /* Calibration ops */
515 void (*init_cal_settings)(struct ath_hw *ah);
516 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
518 void (*init_mode_regs)(struct ath_hw *ah);
519 void (*init_mode_gain_regs)(struct ath_hw *ah);
520 bool (*macversion_supported)(u32 macversion);
521 void (*setup_calibration)(struct ath_hw *ah,
522 struct ath9k_cal_list *currCal);
523 bool (*iscal_supported)(struct ath_hw *ah,
524 enum ath9k_cal_types calType);
527 int (*rf_set_freq)(struct ath_hw *ah,
528 struct ath9k_channel *chan);
529 void (*spur_mitigate_freq)(struct ath_hw *ah,
530 struct ath9k_channel *chan);
531 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
532 void (*rf_free_ext_banks)(struct ath_hw *ah);
533 bool (*set_rf_regs)(struct ath_hw *ah,
534 struct ath9k_channel *chan,
536 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
537 void (*init_bb)(struct ath_hw *ah,
538 struct ath9k_channel *chan);
539 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
540 void (*olc_init)(struct ath_hw *ah);
541 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
542 void (*mark_phy_inactive)(struct ath_hw *ah);
543 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
544 bool (*rfbus_req)(struct ath_hw *ah);
545 void (*rfbus_done)(struct ath_hw *ah);
546 void (*enable_rfkill)(struct ath_hw *ah);
547 void (*restore_chainmask)(struct ath_hw *ah);
548 void (*set_diversity)(struct ath_hw *ah, bool value);
549 u32 (*compute_pll_control)(struct ath_hw *ah,
550 struct ath9k_channel *chan);
551 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
553 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
554 void (*loadnf)(struct ath_hw *ah, struct ath9k_channel *chan);
558 * struct ath_hw_ops - callbacks used by hardware code and driver code
560 * This structure contains callbacks designed to to be used internally by
561 * hardware code and also by the lower level driver.
563 * @config_pci_powersave:
564 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
567 void (*config_pci_powersave)(struct ath_hw *ah,
570 void (*rx_enable)(struct ath_hw *ah);
571 void (*set_desc_link)(void *ds, u32 link);
572 void (*get_desc_link)(void *ds, u32 **link);
573 bool (*calibrate)(struct ath_hw *ah,
574 struct ath9k_channel *chan,
577 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
578 void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
579 bool is_firstseg, bool is_is_lastseg,
580 const void *ds0, dma_addr_t buf_addr,
582 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
583 struct ath_tx_status *ts);
584 void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
585 u32 pktLen, enum ath9k_pkt_type type,
586 u32 txPower, u32 keyIx,
587 enum ath9k_key_type keyType,
589 void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
591 u32 durUpdateEn, u32 rtsctsRate,
593 struct ath9k_11n_rate_series series[],
594 u32 nseries, u32 flags);
595 void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
597 void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
599 void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
600 void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
601 void (*set11n_burstduration)(struct ath_hw *ah, void *ds,
603 void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds,
608 struct ieee80211_hw *hw;
609 struct ath_common common;
610 struct ath9k_hw_version hw_version;
611 struct ath9k_ops_config config;
612 struct ath9k_hw_capabilities caps;
613 struct ath9k_channel channels[38];
614 struct ath9k_channel *curchan;
617 struct ar5416_eeprom_def def;
618 struct ar5416_eeprom_4k map4k;
619 struct ar9287_eeprom map9287;
620 struct ar9300_eeprom ar9300_eep;
622 const struct eeprom_ops *eep_ops;
626 bool need_an_top2_fixup;
639 enum nl80211_iftype opmode;
640 enum ath9k_power_mode power_mode;
642 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
643 struct ath9k_pacal_info pacal_info;
644 struct ar5416Stats stats;
645 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
647 int16_t curchan_rad_index;
648 enum ath9k_int imask;
650 u32 txok_interrupt_mask;
651 u32 txerr_interrupt_mask;
652 u32 txdesc_interrupt_mask;
653 u32 txeol_interrupt_mask;
654 u32 txurn_interrupt_mask;
659 enum ath9k_cal_types supp_cals;
660 struct ath9k_cal_list iq_caldata;
661 struct ath9k_cal_list adcgain_caldata;
662 struct ath9k_cal_list adcdc_calinitdata;
663 struct ath9k_cal_list adcdc_caldata;
664 struct ath9k_cal_list tempCompCalData;
665 struct ath9k_cal_list *cal_list;
666 struct ath9k_cal_list *cal_list_last;
667 struct ath9k_cal_list *cal_list_curr;
668 #define totalPowerMeasI meas0.unsign
669 #define totalPowerMeasQ meas1.unsign
670 #define totalIqCorrMeas meas2.sign
671 #define totalAdcIOddPhase meas0.unsign
672 #define totalAdcIEvenPhase meas1.unsign
673 #define totalAdcQOddPhase meas2.unsign
674 #define totalAdcQEvenPhase meas3.unsign
675 #define totalAdcDcOffsetIOddPhase meas0.sign
676 #define totalAdcDcOffsetIEvenPhase meas1.sign
677 #define totalAdcDcOffsetQOddPhase meas2.sign
678 #define totalAdcDcOffsetQEvenPhase meas3.sign
680 u32 unsign[AR5416_MAX_CHAINS];
681 int32_t sign[AR5416_MAX_CHAINS];
684 u32 unsign[AR5416_MAX_CHAINS];
685 int32_t sign[AR5416_MAX_CHAINS];
688 u32 unsign[AR5416_MAX_CHAINS];
689 int32_t sign[AR5416_MAX_CHAINS];
692 u32 unsign[AR5416_MAX_CHAINS];
693 int32_t sign[AR5416_MAX_CHAINS];
697 u32 sta_id1_defaults;
703 } enable_32kHz_clock;
705 /* Private to hardware code */
706 struct ath_hw_private_ops private_ops;
707 /* Accessed by the lower level driver */
708 struct ath_hw_ops ops;
710 /* Used to program the radio on non single-chip devices */
711 u32 *analogBank0Data;
712 u32 *analogBank1Data;
713 u32 *analogBank2Data;
714 u32 *analogBank3Data;
715 u32 *analogBank6Data;
716 u32 *analogBank6TPCData;
717 u32 *analogBank7Data;
721 int16_t txpower_indexoffset;
730 struct ar5416AniState *curani;
731 struct ar5416AniState ani[255];
732 int totalSizeDesired[5];
736 enum ath9k_ani_cmd ani_function;
738 /* Bluetooth coexistance */
739 struct ath_btcoex_hw btcoex_hw;
745 u32 originalGain[22];
750 struct ar5416IniArray iniModes;
751 struct ar5416IniArray iniCommon;
752 struct ar5416IniArray iniBank0;
753 struct ar5416IniArray iniBB_RfGain;
754 struct ar5416IniArray iniBank1;
755 struct ar5416IniArray iniBank2;
756 struct ar5416IniArray iniBank3;
757 struct ar5416IniArray iniBank6;
758 struct ar5416IniArray iniBank6TPC;
759 struct ar5416IniArray iniBank7;
760 struct ar5416IniArray iniAddac;
761 struct ar5416IniArray iniPcieSerdes;
762 struct ar5416IniArray iniPcieSerdesLowPower;
763 struct ar5416IniArray iniModesAdditional;
764 struct ar5416IniArray iniModesRxGain;
765 struct ar5416IniArray iniModesTxGain;
766 struct ar5416IniArray iniModes_9271_1_0_only;
767 struct ar5416IniArray iniCckfirNormal;
768 struct ar5416IniArray iniCckfirJapan2484;
769 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
770 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
771 struct ar5416IniArray iniModes_9271_ANI_reg;
772 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
773 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
775 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
776 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
777 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
778 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
780 u32 intr_gen_timer_trigger;
781 u32 intr_gen_timer_thresh;
782 struct ath_gen_timer_table hw_gen_timers;
784 struct ar9003_txs *ts_ring;
792 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
797 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
799 return &(ath9k_hw_common(ah)->regulatory);
802 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
804 return &ah->private_ops;
807 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
812 /* Initialization, Detach, Reset */
813 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
814 void ath9k_hw_deinit(struct ath_hw *ah);
815 int ath9k_hw_init(struct ath_hw *ah);
816 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
817 bool bChannelChange);
818 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
819 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
820 u32 capability, u32 *result);
821 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
822 u32 capability, u32 setting, int *status);
823 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
825 /* Key Cache Management */
826 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
827 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
828 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
829 const struct ath9k_keyval *k,
831 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
833 /* GPIO / RFKILL / Antennae */
834 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
835 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
836 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
838 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
839 u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
840 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
842 /* General Operation */
843 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
844 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
845 bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
846 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
848 u32 frameLen, u16 rateix, bool shortPreamble);
849 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
850 struct ath9k_channel *chan,
851 struct chan_centers *centers);
852 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
853 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
854 bool ath9k_hw_phy_disable(struct ath_hw *ah);
855 bool ath9k_hw_disable(struct ath_hw *ah);
856 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
857 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
858 void ath9k_hw_setopmode(struct ath_hw *ah);
859 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
860 void ath9k_hw_setbssidmask(struct ath_hw *ah);
861 void ath9k_hw_write_associd(struct ath_hw *ah);
862 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
863 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
864 void ath9k_hw_reset_tsf(struct ath_hw *ah);
865 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
866 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp);
867 void ath9k_hw_init_global_settings(struct ath_hw *ah);
868 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
869 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
870 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
871 const struct ath9k_beacon_state *bs);
872 bool ath9k_hw_check_alive(struct ath_hw *ah);
874 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
876 /* Generic hw timer primitives */
877 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
878 void (*trigger)(void *),
879 void (*overflow)(void *),
882 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
883 struct ath_gen_timer *timer,
886 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
888 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
889 void ath_gen_timer_isr(struct ath_hw *hw);
890 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
892 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
895 void ath9k_hw_htc_resetinit(struct ath_hw *ah);
898 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
899 u32 *coef_mantissa, u32 *coef_exponent);
902 * Code Specific to AR5008, AR9001 or AR9002,
903 * we stuff these here to avoid callbacks for AR9003.
905 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
906 int ar9002_hw_rf_claim(struct ath_hw *ah);
907 void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
908 void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
911 * Code specifric to AR9003, we stuff these here to avoid callbacks
914 void ar9003_hw_set_nf_limits(struct ath_hw *ah);
916 /* Hardware family op attach helpers */
917 void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
918 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
919 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
921 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
922 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
924 void ar9002_hw_attach_ops(struct ath_hw *ah);
925 void ar9003_hw_attach_ops(struct ath_hw *ah);
927 #define ATH_PCIE_CAP_LINK_CTRL 0x70
928 #define ATH_PCIE_CAP_LINK_L0S 1
929 #define ATH_PCIE_CAP_LINK_L1 2